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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux...
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / t4_hw.c
1 /*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/delay.h>
36 #include "cxgb4.h"
37 #include "t4_regs.h"
38 #include "t4_values.h"
39 #include "t4fw_api.h"
40 #include "t4fw_version.h"
41
42 /**
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
51 *
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
56 */
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
59 {
60 while (1) {
61 u32 val = t4_read_reg(adapter, reg);
62
63 if (!!(val & mask) == polarity) {
64 if (valp)
65 *valp = val;
66 return 0;
67 }
68 if (--attempts == 0)
69 return -EAGAIN;
70 if (delay)
71 udelay(delay);
72 }
73 }
74
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
77 {
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
79 delay, NULL);
80 }
81
82 /**
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
88 *
89 * Sets a register field specified by the supplied mask to the
90 * given value.
91 */
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
93 u32 val)
94 {
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
96
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
99 }
100
101 /**
102 * t4_read_indirect - read indirectly addressed registers
103 * @adap: the adapter
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
109 *
110 * Reads registers that are accessed indirectly through an address/data
111 * register pair.
112 */
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
116 {
117 while (nregs--) {
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
120 start_idx++;
121 }
122 }
123
124 /**
125 * t4_write_indirect - write indirectly addressed registers
126 * @adap: the adapter
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
132 *
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
135 */
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
139 {
140 while (nregs--) {
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
143 }
144 }
145
146 /*
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
151 */
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
153 {
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
155
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
157 req |= ENABLE_F;
158 else
159 req |= T6_ENABLE_F;
160
161 if (is_t4(adap->params.chip))
162 req |= LOCALCFG_F;
163
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
166
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
171 */
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
173 }
174
175 /*
176 * t4_report_fw_error - report firmware error
177 * @adap: the adapter
178 *
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
182 */
183 static void t4_report_fw_error(struct adapter *adap)
184 {
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
194 };
195 u32 pcie_fw;
196
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F)
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
201 }
202
203 /*
204 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
205 */
206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
207 u32 mbox_addr)
208 {
209 for ( ; nflit; nflit--, mbox_addr += 8)
210 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
211 }
212
213 /*
214 * Handle a FW assertion reported in a mailbox.
215 */
216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
217 {
218 struct fw_debug_cmd asrt;
219
220 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
221 dev_alert(adap->pdev_dev,
222 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
223 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
224 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
225 }
226
227 static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg)
228 {
229 dev_err(adap->pdev_dev,
230 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
231 (unsigned long long)t4_read_reg64(adap, data_reg),
232 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
233 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
234 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
235 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
236 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
237 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
238 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
239 }
240
241 /**
242 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
243 * @adap: the adapter
244 * @mbox: index of the mailbox to use
245 * @cmd: the command to write
246 * @size: command length in bytes
247 * @rpl: where to optionally store the reply
248 * @sleep_ok: if true we may sleep while awaiting command completion
249 * @timeout: time to wait for command to finish before timing out
250 *
251 * Sends the given command to FW through the selected mailbox and waits
252 * for the FW to execute the command. If @rpl is not %NULL it is used to
253 * store the FW's reply to the command. The command and its optional
254 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
255 * to respond. @sleep_ok determines whether we may sleep while awaiting
256 * the response. If sleeping is allowed we use progressive backoff
257 * otherwise we spin.
258 *
259 * The return value is 0 on success or a negative errno on failure. A
260 * failure can happen either because we are not able to execute the
261 * command or FW executes it but signals an error. In the latter case
262 * the return value is the error code indicated by FW (negated).
263 */
264 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
265 int size, void *rpl, bool sleep_ok, int timeout)
266 {
267 static const int delay[] = {
268 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
269 };
270
271 u32 v;
272 u64 res;
273 int i, ms, delay_idx;
274 const __be64 *p = cmd;
275 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
276 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
277
278 if ((size & 15) || size > MBOX_LEN)
279 return -EINVAL;
280
281 /*
282 * If the device is off-line, as in EEH, commands will time out.
283 * Fail them early so we don't waste time waiting.
284 */
285 if (adap->pdev->error_state != pci_channel_io_normal)
286 return -EIO;
287
288 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
289 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
290 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
291
292 if (v != MBOX_OWNER_DRV)
293 return v ? -EBUSY : -ETIMEDOUT;
294
295 for (i = 0; i < size; i += 8)
296 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
297
298 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
299 t4_read_reg(adap, ctl_reg); /* flush write */
300
301 delay_idx = 0;
302 ms = delay[0];
303
304 for (i = 0; i < timeout; i += ms) {
305 if (sleep_ok) {
306 ms = delay[delay_idx]; /* last element may repeat */
307 if (delay_idx < ARRAY_SIZE(delay) - 1)
308 delay_idx++;
309 msleep(ms);
310 } else
311 mdelay(ms);
312
313 v = t4_read_reg(adap, ctl_reg);
314 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
315 if (!(v & MBMSGVALID_F)) {
316 t4_write_reg(adap, ctl_reg, 0);
317 continue;
318 }
319
320 res = t4_read_reg64(adap, data_reg);
321 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
322 fw_asrt(adap, data_reg);
323 res = FW_CMD_RETVAL_V(EIO);
324 } else if (rpl) {
325 get_mbox_rpl(adap, rpl, size / 8, data_reg);
326 }
327
328 if (FW_CMD_RETVAL_G((int)res))
329 dump_mbox(adap, mbox, data_reg);
330 t4_write_reg(adap, ctl_reg, 0);
331 return -FW_CMD_RETVAL_G((int)res);
332 }
333 }
334
335 dump_mbox(adap, mbox, data_reg);
336 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
337 *(const u8 *)cmd, mbox);
338 t4_report_fw_error(adap);
339 return -ETIMEDOUT;
340 }
341
342 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
343 void *rpl, bool sleep_ok)
344 {
345 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
346 FW_CMD_MAX_TIMEOUT);
347 }
348
349 static int t4_edc_err_read(struct adapter *adap, int idx)
350 {
351 u32 edc_ecc_err_addr_reg;
352 u32 rdata_reg;
353
354 if (is_t4(adap->params.chip)) {
355 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
356 return 0;
357 }
358 if (idx != 0 && idx != 1) {
359 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
360 return 0;
361 }
362
363 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
364 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
365
366 CH_WARN(adap,
367 "edc%d err addr 0x%x: 0x%x.\n",
368 idx, edc_ecc_err_addr_reg,
369 t4_read_reg(adap, edc_ecc_err_addr_reg));
370 CH_WARN(adap,
371 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
372 rdata_reg,
373 (unsigned long long)t4_read_reg64(adap, rdata_reg),
374 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
375 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
376 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
377 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
378 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
379 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
380 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
381 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
382
383 return 0;
384 }
385
386 /**
387 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
388 * @adap: the adapter
389 * @win: PCI-E Memory Window to use
390 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
391 * @addr: address within indicated memory type
392 * @len: amount of memory to transfer
393 * @hbuf: host memory buffer
394 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
395 *
396 * Reads/writes an [almost] arbitrary memory region in the firmware: the
397 * firmware memory address and host buffer must be aligned on 32-bit
398 * boudaries; the length may be arbitrary. The memory is transferred as
399 * a raw byte sequence from/to the firmware's memory. If this memory
400 * contains data structures which contain multi-byte integers, it's the
401 * caller's responsibility to perform appropriate byte order conversions.
402 */
403 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
404 u32 len, void *hbuf, int dir)
405 {
406 u32 pos, offset, resid, memoffset;
407 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
408 u32 *buf;
409
410 /* Argument sanity checks ...
411 */
412 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
413 return -EINVAL;
414 buf = (u32 *)hbuf;
415
416 /* It's convenient to be able to handle lengths which aren't a
417 * multiple of 32-bits because we often end up transferring files to
418 * the firmware. So we'll handle that by normalizing the length here
419 * and then handling any residual transfer at the end.
420 */
421 resid = len & 0x3;
422 len -= resid;
423
424 /* Offset into the region of memory which is being accessed
425 * MEM_EDC0 = 0
426 * MEM_EDC1 = 1
427 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
428 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
429 */
430 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
431 if (mtype != MEM_MC1)
432 memoffset = (mtype * (edc_size * 1024 * 1024));
433 else {
434 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
435 MA_EXT_MEMORY0_BAR_A));
436 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
437 }
438
439 /* Determine the PCIE_MEM_ACCESS_OFFSET */
440 addr = addr + memoffset;
441
442 /* Each PCI-E Memory Window is programmed with a window size -- or
443 * "aperture" -- which controls the granularity of its mapping onto
444 * adapter memory. We need to grab that aperture in order to know
445 * how to use the specified window. The window is also programmed
446 * with the base address of the Memory Window in BAR0's address
447 * space. For T4 this is an absolute PCI-E Bus Address. For T5
448 * the address is relative to BAR0.
449 */
450 mem_reg = t4_read_reg(adap,
451 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
452 win));
453 mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
454 mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
455 if (is_t4(adap->params.chip))
456 mem_base -= adap->t4_bar0;
457 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
458
459 /* Calculate our initial PCI-E Memory Window Position and Offset into
460 * that Window.
461 */
462 pos = addr & ~(mem_aperture-1);
463 offset = addr - pos;
464
465 /* Set up initial PCI-E Memory Window to cover the start of our
466 * transfer. (Read it back to ensure that changes propagate before we
467 * attempt to use the new value.)
468 */
469 t4_write_reg(adap,
470 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
471 pos | win_pf);
472 t4_read_reg(adap,
473 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
474
475 /* Transfer data to/from the adapter as long as there's an integral
476 * number of 32-bit transfers to complete.
477 *
478 * A note on Endianness issues:
479 *
480 * The "register" reads and writes below from/to the PCI-E Memory
481 * Window invoke the standard adapter Big-Endian to PCI-E Link
482 * Little-Endian "swizzel." As a result, if we have the following
483 * data in adapter memory:
484 *
485 * Memory: ... | b0 | b1 | b2 | b3 | ...
486 * Address: i+0 i+1 i+2 i+3
487 *
488 * Then a read of the adapter memory via the PCI-E Memory Window
489 * will yield:
490 *
491 * x = readl(i)
492 * 31 0
493 * [ b3 | b2 | b1 | b0 ]
494 *
495 * If this value is stored into local memory on a Little-Endian system
496 * it will show up correctly in local memory as:
497 *
498 * ( ..., b0, b1, b2, b3, ... )
499 *
500 * But on a Big-Endian system, the store will show up in memory
501 * incorrectly swizzled as:
502 *
503 * ( ..., b3, b2, b1, b0, ... )
504 *
505 * So we need to account for this in the reads and writes to the
506 * PCI-E Memory Window below by undoing the register read/write
507 * swizzels.
508 */
509 while (len > 0) {
510 if (dir == T4_MEMORY_READ)
511 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
512 mem_base + offset));
513 else
514 t4_write_reg(adap, mem_base + offset,
515 (__force u32)cpu_to_le32(*buf++));
516 offset += sizeof(__be32);
517 len -= sizeof(__be32);
518
519 /* If we've reached the end of our current window aperture,
520 * move the PCI-E Memory Window on to the next. Note that
521 * doing this here after "len" may be 0 allows us to set up
522 * the PCI-E Memory Window for a possible final residual
523 * transfer below ...
524 */
525 if (offset == mem_aperture) {
526 pos += mem_aperture;
527 offset = 0;
528 t4_write_reg(adap,
529 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
530 win), pos | win_pf);
531 t4_read_reg(adap,
532 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
533 win));
534 }
535 }
536
537 /* If the original transfer had a length which wasn't a multiple of
538 * 32-bits, now's where we need to finish off the transfer of the
539 * residual amount. The PCI-E Memory Window has already been moved
540 * above (if necessary) to cover this final transfer.
541 */
542 if (resid) {
543 union {
544 u32 word;
545 char byte[4];
546 } last;
547 unsigned char *bp;
548 int i;
549
550 if (dir == T4_MEMORY_READ) {
551 last.word = le32_to_cpu(
552 (__force __le32)t4_read_reg(adap,
553 mem_base + offset));
554 for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
555 bp[i] = last.byte[i];
556 } else {
557 last.word = *buf;
558 for (i = resid; i < 4; i++)
559 last.byte[i] = 0;
560 t4_write_reg(adap, mem_base + offset,
561 (__force u32)cpu_to_le32(last.word));
562 }
563 }
564
565 return 0;
566 }
567
568 /* Return the specified PCI-E Configuration Space register from our Physical
569 * Function. We try first via a Firmware LDST Command since we prefer to let
570 * the firmware own all of these registers, but if that fails we go for it
571 * directly ourselves.
572 */
573 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
574 {
575 u32 val, ldst_addrspace;
576
577 /* If fw_attach != 0, construct and send the Firmware LDST Command to
578 * retrieve the specified PCI-E Configuration Space register.
579 */
580 struct fw_ldst_cmd ldst_cmd;
581 int ret;
582
583 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
584 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
585 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
586 FW_CMD_REQUEST_F |
587 FW_CMD_READ_F |
588 ldst_addrspace);
589 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
590 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
591 ldst_cmd.u.pcie.ctrl_to_fn =
592 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
593 ldst_cmd.u.pcie.r = reg;
594
595 /* If the LDST Command succeeds, return the result, otherwise
596 * fall through to reading it directly ourselves ...
597 */
598 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
599 &ldst_cmd);
600 if (ret == 0)
601 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
602 else
603 /* Read the desired Configuration Space register via the PCI-E
604 * Backdoor mechanism.
605 */
606 t4_hw_pci_read_cfg4(adap, reg, &val);
607 return val;
608 }
609
610 /* Get the window based on base passed to it.
611 * Window aperture is currently unhandled, but there is no use case for it
612 * right now
613 */
614 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
615 u32 memwin_base)
616 {
617 u32 ret;
618
619 if (is_t4(adap->params.chip)) {
620 u32 bar0;
621
622 /* Truncation intentional: we only read the bottom 32-bits of
623 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
624 * mechanism to read BAR0 instead of using
625 * pci_resource_start() because we could be operating from
626 * within a Virtual Machine which is trapping our accesses to
627 * our Configuration Space and we need to set up the PCI-E
628 * Memory Window decoders with the actual addresses which will
629 * be coming across the PCI-E link.
630 */
631 bar0 = t4_read_pcie_cfg4(adap, pci_base);
632 bar0 &= pci_mask;
633 adap->t4_bar0 = bar0;
634
635 ret = bar0 + memwin_base;
636 } else {
637 /* For T5, only relative offset inside the PCIe BAR is passed */
638 ret = memwin_base;
639 }
640 return ret;
641 }
642
643 /* Get the default utility window (win0) used by everyone */
644 u32 t4_get_util_window(struct adapter *adap)
645 {
646 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
647 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
648 }
649
650 /* Set up memory window for accessing adapter memory ranges. (Read
651 * back MA register to ensure that changes propagate before we attempt
652 * to use the new values.)
653 */
654 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
655 {
656 t4_write_reg(adap,
657 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
658 memwin_base | BIR_V(0) |
659 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
660 t4_read_reg(adap,
661 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
662 }
663
664 /**
665 * t4_get_regs_len - return the size of the chips register set
666 * @adapter: the adapter
667 *
668 * Returns the size of the chip's BAR0 register space.
669 */
670 unsigned int t4_get_regs_len(struct adapter *adapter)
671 {
672 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
673
674 switch (chip_version) {
675 case CHELSIO_T4:
676 return T4_REGMAP_SIZE;
677
678 case CHELSIO_T5:
679 case CHELSIO_T6:
680 return T5_REGMAP_SIZE;
681 }
682
683 dev_err(adapter->pdev_dev,
684 "Unsupported chip version %d\n", chip_version);
685 return 0;
686 }
687
688 /**
689 * t4_get_regs - read chip registers into provided buffer
690 * @adap: the adapter
691 * @buf: register buffer
692 * @buf_size: size (in bytes) of register buffer
693 *
694 * If the provided register buffer isn't large enough for the chip's
695 * full register range, the register dump will be truncated to the
696 * register buffer's size.
697 */
698 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
699 {
700 static const unsigned int t4_reg_ranges[] = {
701 0x1008, 0x1108,
702 0x1180, 0x1184,
703 0x1190, 0x1194,
704 0x11a0, 0x11a4,
705 0x11b0, 0x11b4,
706 0x11fc, 0x123c,
707 0x1300, 0x173c,
708 0x1800, 0x18fc,
709 0x3000, 0x30d8,
710 0x30e0, 0x30e4,
711 0x30ec, 0x5910,
712 0x5920, 0x5924,
713 0x5960, 0x5960,
714 0x5968, 0x5968,
715 0x5970, 0x5970,
716 0x5978, 0x5978,
717 0x5980, 0x5980,
718 0x5988, 0x5988,
719 0x5990, 0x5990,
720 0x5998, 0x5998,
721 0x59a0, 0x59d4,
722 0x5a00, 0x5ae0,
723 0x5ae8, 0x5ae8,
724 0x5af0, 0x5af0,
725 0x5af8, 0x5af8,
726 0x6000, 0x6098,
727 0x6100, 0x6150,
728 0x6200, 0x6208,
729 0x6240, 0x6248,
730 0x6280, 0x62b0,
731 0x62c0, 0x6338,
732 0x6370, 0x638c,
733 0x6400, 0x643c,
734 0x6500, 0x6524,
735 0x6a00, 0x6a04,
736 0x6a14, 0x6a38,
737 0x6a60, 0x6a70,
738 0x6a78, 0x6a78,
739 0x6b00, 0x6b0c,
740 0x6b1c, 0x6b84,
741 0x6bf0, 0x6bf8,
742 0x6c00, 0x6c0c,
743 0x6c1c, 0x6c84,
744 0x6cf0, 0x6cf8,
745 0x6d00, 0x6d0c,
746 0x6d1c, 0x6d84,
747 0x6df0, 0x6df8,
748 0x6e00, 0x6e0c,
749 0x6e1c, 0x6e84,
750 0x6ef0, 0x6ef8,
751 0x6f00, 0x6f0c,
752 0x6f1c, 0x6f84,
753 0x6ff0, 0x6ff8,
754 0x7000, 0x700c,
755 0x701c, 0x7084,
756 0x70f0, 0x70f8,
757 0x7100, 0x710c,
758 0x711c, 0x7184,
759 0x71f0, 0x71f8,
760 0x7200, 0x720c,
761 0x721c, 0x7284,
762 0x72f0, 0x72f8,
763 0x7300, 0x730c,
764 0x731c, 0x7384,
765 0x73f0, 0x73f8,
766 0x7400, 0x7450,
767 0x7500, 0x7530,
768 0x7600, 0x760c,
769 0x7614, 0x761c,
770 0x7680, 0x76cc,
771 0x7700, 0x7798,
772 0x77c0, 0x77fc,
773 0x7900, 0x79fc,
774 0x7b00, 0x7b58,
775 0x7b60, 0x7b84,
776 0x7b8c, 0x7c38,
777 0x7d00, 0x7d38,
778 0x7d40, 0x7d80,
779 0x7d8c, 0x7ddc,
780 0x7de4, 0x7e04,
781 0x7e10, 0x7e1c,
782 0x7e24, 0x7e38,
783 0x7e40, 0x7e44,
784 0x7e4c, 0x7e78,
785 0x7e80, 0x7ea4,
786 0x7eac, 0x7edc,
787 0x7ee8, 0x7efc,
788 0x8dc0, 0x8e04,
789 0x8e10, 0x8e1c,
790 0x8e30, 0x8e78,
791 0x8ea0, 0x8eb8,
792 0x8ec0, 0x8f6c,
793 0x8fc0, 0x9008,
794 0x9010, 0x9058,
795 0x9060, 0x9060,
796 0x9068, 0x9074,
797 0x90fc, 0x90fc,
798 0x9400, 0x9408,
799 0x9410, 0x9458,
800 0x9600, 0x9600,
801 0x9608, 0x9638,
802 0x9640, 0x96bc,
803 0x9800, 0x9808,
804 0x9820, 0x983c,
805 0x9850, 0x9864,
806 0x9c00, 0x9c6c,
807 0x9c80, 0x9cec,
808 0x9d00, 0x9d6c,
809 0x9d80, 0x9dec,
810 0x9e00, 0x9e6c,
811 0x9e80, 0x9eec,
812 0x9f00, 0x9f6c,
813 0x9f80, 0x9fec,
814 0xd004, 0xd004,
815 0xd010, 0xd03c,
816 0xdfc0, 0xdfe0,
817 0xe000, 0xea7c,
818 0xf000, 0x11190,
819 0x19040, 0x1906c,
820 0x19078, 0x19080,
821 0x1908c, 0x190e4,
822 0x190f0, 0x190f8,
823 0x19100, 0x19110,
824 0x19120, 0x19124,
825 0x19150, 0x19194,
826 0x1919c, 0x191b0,
827 0x191d0, 0x191e8,
828 0x19238, 0x1924c,
829 0x193f8, 0x1943c,
830 0x1944c, 0x19474,
831 0x19490, 0x194e0,
832 0x194f0, 0x194f8,
833 0x19800, 0x19c08,
834 0x19c10, 0x19c90,
835 0x19ca0, 0x19ce4,
836 0x19cf0, 0x19d40,
837 0x19d50, 0x19d94,
838 0x19da0, 0x19de8,
839 0x19df0, 0x19e40,
840 0x19e50, 0x19e90,
841 0x19ea0, 0x19f4c,
842 0x1a000, 0x1a004,
843 0x1a010, 0x1a06c,
844 0x1a0b0, 0x1a0e4,
845 0x1a0ec, 0x1a0f4,
846 0x1a100, 0x1a108,
847 0x1a114, 0x1a120,
848 0x1a128, 0x1a130,
849 0x1a138, 0x1a138,
850 0x1a190, 0x1a1c4,
851 0x1a1fc, 0x1a1fc,
852 0x1e040, 0x1e04c,
853 0x1e284, 0x1e28c,
854 0x1e2c0, 0x1e2c0,
855 0x1e2e0, 0x1e2e0,
856 0x1e300, 0x1e384,
857 0x1e3c0, 0x1e3c8,
858 0x1e440, 0x1e44c,
859 0x1e684, 0x1e68c,
860 0x1e6c0, 0x1e6c0,
861 0x1e6e0, 0x1e6e0,
862 0x1e700, 0x1e784,
863 0x1e7c0, 0x1e7c8,
864 0x1e840, 0x1e84c,
865 0x1ea84, 0x1ea8c,
866 0x1eac0, 0x1eac0,
867 0x1eae0, 0x1eae0,
868 0x1eb00, 0x1eb84,
869 0x1ebc0, 0x1ebc8,
870 0x1ec40, 0x1ec4c,
871 0x1ee84, 0x1ee8c,
872 0x1eec0, 0x1eec0,
873 0x1eee0, 0x1eee0,
874 0x1ef00, 0x1ef84,
875 0x1efc0, 0x1efc8,
876 0x1f040, 0x1f04c,
877 0x1f284, 0x1f28c,
878 0x1f2c0, 0x1f2c0,
879 0x1f2e0, 0x1f2e0,
880 0x1f300, 0x1f384,
881 0x1f3c0, 0x1f3c8,
882 0x1f440, 0x1f44c,
883 0x1f684, 0x1f68c,
884 0x1f6c0, 0x1f6c0,
885 0x1f6e0, 0x1f6e0,
886 0x1f700, 0x1f784,
887 0x1f7c0, 0x1f7c8,
888 0x1f840, 0x1f84c,
889 0x1fa84, 0x1fa8c,
890 0x1fac0, 0x1fac0,
891 0x1fae0, 0x1fae0,
892 0x1fb00, 0x1fb84,
893 0x1fbc0, 0x1fbc8,
894 0x1fc40, 0x1fc4c,
895 0x1fe84, 0x1fe8c,
896 0x1fec0, 0x1fec0,
897 0x1fee0, 0x1fee0,
898 0x1ff00, 0x1ff84,
899 0x1ffc0, 0x1ffc8,
900 0x20000, 0x2002c,
901 0x20100, 0x2013c,
902 0x20190, 0x201a0,
903 0x201a8, 0x201b8,
904 0x201c4, 0x201c8,
905 0x20200, 0x20318,
906 0x20400, 0x204b4,
907 0x204c0, 0x20528,
908 0x20540, 0x20614,
909 0x21000, 0x21040,
910 0x2104c, 0x21060,
911 0x210c0, 0x210ec,
912 0x21200, 0x21268,
913 0x21270, 0x21284,
914 0x212fc, 0x21388,
915 0x21400, 0x21404,
916 0x21500, 0x21500,
917 0x21510, 0x21518,
918 0x2152c, 0x21530,
919 0x2153c, 0x2153c,
920 0x21550, 0x21554,
921 0x21600, 0x21600,
922 0x21608, 0x2161c,
923 0x21624, 0x21628,
924 0x21630, 0x21634,
925 0x2163c, 0x2163c,
926 0x21700, 0x2171c,
927 0x21780, 0x2178c,
928 0x21800, 0x21818,
929 0x21820, 0x21828,
930 0x21830, 0x21848,
931 0x21850, 0x21854,
932 0x21860, 0x21868,
933 0x21870, 0x21870,
934 0x21878, 0x21898,
935 0x218a0, 0x218a8,
936 0x218b0, 0x218c8,
937 0x218d0, 0x218d4,
938 0x218e0, 0x218e8,
939 0x218f0, 0x218f0,
940 0x218f8, 0x21a18,
941 0x21a20, 0x21a28,
942 0x21a30, 0x21a48,
943 0x21a50, 0x21a54,
944 0x21a60, 0x21a68,
945 0x21a70, 0x21a70,
946 0x21a78, 0x21a98,
947 0x21aa0, 0x21aa8,
948 0x21ab0, 0x21ac8,
949 0x21ad0, 0x21ad4,
950 0x21ae0, 0x21ae8,
951 0x21af0, 0x21af0,
952 0x21af8, 0x21c18,
953 0x21c20, 0x21c20,
954 0x21c28, 0x21c30,
955 0x21c38, 0x21c38,
956 0x21c80, 0x21c98,
957 0x21ca0, 0x21ca8,
958 0x21cb0, 0x21cc8,
959 0x21cd0, 0x21cd4,
960 0x21ce0, 0x21ce8,
961 0x21cf0, 0x21cf0,
962 0x21cf8, 0x21d7c,
963 0x21e00, 0x21e04,
964 0x22000, 0x2202c,
965 0x22100, 0x2213c,
966 0x22190, 0x221a0,
967 0x221a8, 0x221b8,
968 0x221c4, 0x221c8,
969 0x22200, 0x22318,
970 0x22400, 0x224b4,
971 0x224c0, 0x22528,
972 0x22540, 0x22614,
973 0x23000, 0x23040,
974 0x2304c, 0x23060,
975 0x230c0, 0x230ec,
976 0x23200, 0x23268,
977 0x23270, 0x23284,
978 0x232fc, 0x23388,
979 0x23400, 0x23404,
980 0x23500, 0x23500,
981 0x23510, 0x23518,
982 0x2352c, 0x23530,
983 0x2353c, 0x2353c,
984 0x23550, 0x23554,
985 0x23600, 0x23600,
986 0x23608, 0x2361c,
987 0x23624, 0x23628,
988 0x23630, 0x23634,
989 0x2363c, 0x2363c,
990 0x23700, 0x2371c,
991 0x23780, 0x2378c,
992 0x23800, 0x23818,
993 0x23820, 0x23828,
994 0x23830, 0x23848,
995 0x23850, 0x23854,
996 0x23860, 0x23868,
997 0x23870, 0x23870,
998 0x23878, 0x23898,
999 0x238a0, 0x238a8,
1000 0x238b0, 0x238c8,
1001 0x238d0, 0x238d4,
1002 0x238e0, 0x238e8,
1003 0x238f0, 0x238f0,
1004 0x238f8, 0x23a18,
1005 0x23a20, 0x23a28,
1006 0x23a30, 0x23a48,
1007 0x23a50, 0x23a54,
1008 0x23a60, 0x23a68,
1009 0x23a70, 0x23a70,
1010 0x23a78, 0x23a98,
1011 0x23aa0, 0x23aa8,
1012 0x23ab0, 0x23ac8,
1013 0x23ad0, 0x23ad4,
1014 0x23ae0, 0x23ae8,
1015 0x23af0, 0x23af0,
1016 0x23af8, 0x23c18,
1017 0x23c20, 0x23c20,
1018 0x23c28, 0x23c30,
1019 0x23c38, 0x23c38,
1020 0x23c80, 0x23c98,
1021 0x23ca0, 0x23ca8,
1022 0x23cb0, 0x23cc8,
1023 0x23cd0, 0x23cd4,
1024 0x23ce0, 0x23ce8,
1025 0x23cf0, 0x23cf0,
1026 0x23cf8, 0x23d7c,
1027 0x23e00, 0x23e04,
1028 0x24000, 0x2402c,
1029 0x24100, 0x2413c,
1030 0x24190, 0x241a0,
1031 0x241a8, 0x241b8,
1032 0x241c4, 0x241c8,
1033 0x24200, 0x24318,
1034 0x24400, 0x244b4,
1035 0x244c0, 0x24528,
1036 0x24540, 0x24614,
1037 0x25000, 0x25040,
1038 0x2504c, 0x25060,
1039 0x250c0, 0x250ec,
1040 0x25200, 0x25268,
1041 0x25270, 0x25284,
1042 0x252fc, 0x25388,
1043 0x25400, 0x25404,
1044 0x25500, 0x25500,
1045 0x25510, 0x25518,
1046 0x2552c, 0x25530,
1047 0x2553c, 0x2553c,
1048 0x25550, 0x25554,
1049 0x25600, 0x25600,
1050 0x25608, 0x2561c,
1051 0x25624, 0x25628,
1052 0x25630, 0x25634,
1053 0x2563c, 0x2563c,
1054 0x25700, 0x2571c,
1055 0x25780, 0x2578c,
1056 0x25800, 0x25818,
1057 0x25820, 0x25828,
1058 0x25830, 0x25848,
1059 0x25850, 0x25854,
1060 0x25860, 0x25868,
1061 0x25870, 0x25870,
1062 0x25878, 0x25898,
1063 0x258a0, 0x258a8,
1064 0x258b0, 0x258c8,
1065 0x258d0, 0x258d4,
1066 0x258e0, 0x258e8,
1067 0x258f0, 0x258f0,
1068 0x258f8, 0x25a18,
1069 0x25a20, 0x25a28,
1070 0x25a30, 0x25a48,
1071 0x25a50, 0x25a54,
1072 0x25a60, 0x25a68,
1073 0x25a70, 0x25a70,
1074 0x25a78, 0x25a98,
1075 0x25aa0, 0x25aa8,
1076 0x25ab0, 0x25ac8,
1077 0x25ad0, 0x25ad4,
1078 0x25ae0, 0x25ae8,
1079 0x25af0, 0x25af0,
1080 0x25af8, 0x25c18,
1081 0x25c20, 0x25c20,
1082 0x25c28, 0x25c30,
1083 0x25c38, 0x25c38,
1084 0x25c80, 0x25c98,
1085 0x25ca0, 0x25ca8,
1086 0x25cb0, 0x25cc8,
1087 0x25cd0, 0x25cd4,
1088 0x25ce0, 0x25ce8,
1089 0x25cf0, 0x25cf0,
1090 0x25cf8, 0x25d7c,
1091 0x25e00, 0x25e04,
1092 0x26000, 0x2602c,
1093 0x26100, 0x2613c,
1094 0x26190, 0x261a0,
1095 0x261a8, 0x261b8,
1096 0x261c4, 0x261c8,
1097 0x26200, 0x26318,
1098 0x26400, 0x264b4,
1099 0x264c0, 0x26528,
1100 0x26540, 0x26614,
1101 0x27000, 0x27040,
1102 0x2704c, 0x27060,
1103 0x270c0, 0x270ec,
1104 0x27200, 0x27268,
1105 0x27270, 0x27284,
1106 0x272fc, 0x27388,
1107 0x27400, 0x27404,
1108 0x27500, 0x27500,
1109 0x27510, 0x27518,
1110 0x2752c, 0x27530,
1111 0x2753c, 0x2753c,
1112 0x27550, 0x27554,
1113 0x27600, 0x27600,
1114 0x27608, 0x2761c,
1115 0x27624, 0x27628,
1116 0x27630, 0x27634,
1117 0x2763c, 0x2763c,
1118 0x27700, 0x2771c,
1119 0x27780, 0x2778c,
1120 0x27800, 0x27818,
1121 0x27820, 0x27828,
1122 0x27830, 0x27848,
1123 0x27850, 0x27854,
1124 0x27860, 0x27868,
1125 0x27870, 0x27870,
1126 0x27878, 0x27898,
1127 0x278a0, 0x278a8,
1128 0x278b0, 0x278c8,
1129 0x278d0, 0x278d4,
1130 0x278e0, 0x278e8,
1131 0x278f0, 0x278f0,
1132 0x278f8, 0x27a18,
1133 0x27a20, 0x27a28,
1134 0x27a30, 0x27a48,
1135 0x27a50, 0x27a54,
1136 0x27a60, 0x27a68,
1137 0x27a70, 0x27a70,
1138 0x27a78, 0x27a98,
1139 0x27aa0, 0x27aa8,
1140 0x27ab0, 0x27ac8,
1141 0x27ad0, 0x27ad4,
1142 0x27ae0, 0x27ae8,
1143 0x27af0, 0x27af0,
1144 0x27af8, 0x27c18,
1145 0x27c20, 0x27c20,
1146 0x27c28, 0x27c30,
1147 0x27c38, 0x27c38,
1148 0x27c80, 0x27c98,
1149 0x27ca0, 0x27ca8,
1150 0x27cb0, 0x27cc8,
1151 0x27cd0, 0x27cd4,
1152 0x27ce0, 0x27ce8,
1153 0x27cf0, 0x27cf0,
1154 0x27cf8, 0x27d7c,
1155 0x27e00, 0x27e04,
1156 };
1157
1158 static const unsigned int t5_reg_ranges[] = {
1159 0x1008, 0x10c0,
1160 0x10cc, 0x10f8,
1161 0x1100, 0x1100,
1162 0x110c, 0x1148,
1163 0x1180, 0x1184,
1164 0x1190, 0x1194,
1165 0x11a0, 0x11a4,
1166 0x11b0, 0x11b4,
1167 0x11fc, 0x123c,
1168 0x1280, 0x173c,
1169 0x1800, 0x18fc,
1170 0x3000, 0x3028,
1171 0x3060, 0x30b0,
1172 0x30b8, 0x30d8,
1173 0x30e0, 0x30fc,
1174 0x3140, 0x357c,
1175 0x35a8, 0x35cc,
1176 0x35ec, 0x35ec,
1177 0x3600, 0x5624,
1178 0x56cc, 0x56ec,
1179 0x56f4, 0x5720,
1180 0x5728, 0x575c,
1181 0x580c, 0x5814,
1182 0x5890, 0x589c,
1183 0x58a4, 0x58ac,
1184 0x58b8, 0x58bc,
1185 0x5940, 0x59c8,
1186 0x59d0, 0x59dc,
1187 0x59fc, 0x5a18,
1188 0x5a60, 0x5a70,
1189 0x5a80, 0x5a9c,
1190 0x5b94, 0x5bfc,
1191 0x6000, 0x6020,
1192 0x6028, 0x6040,
1193 0x6058, 0x609c,
1194 0x60a8, 0x614c,
1195 0x7700, 0x7798,
1196 0x77c0, 0x78fc,
1197 0x7b00, 0x7b58,
1198 0x7b60, 0x7b84,
1199 0x7b8c, 0x7c54,
1200 0x7d00, 0x7d38,
1201 0x7d40, 0x7d80,
1202 0x7d8c, 0x7ddc,
1203 0x7de4, 0x7e04,
1204 0x7e10, 0x7e1c,
1205 0x7e24, 0x7e38,
1206 0x7e40, 0x7e44,
1207 0x7e4c, 0x7e78,
1208 0x7e80, 0x7edc,
1209 0x7ee8, 0x7efc,
1210 0x8dc0, 0x8de0,
1211 0x8df8, 0x8e04,
1212 0x8e10, 0x8e84,
1213 0x8ea0, 0x8f84,
1214 0x8fc0, 0x9058,
1215 0x9060, 0x9060,
1216 0x9068, 0x90f8,
1217 0x9400, 0x9408,
1218 0x9410, 0x9470,
1219 0x9600, 0x9600,
1220 0x9608, 0x9638,
1221 0x9640, 0x96f4,
1222 0x9800, 0x9808,
1223 0x9820, 0x983c,
1224 0x9850, 0x9864,
1225 0x9c00, 0x9c6c,
1226 0x9c80, 0x9cec,
1227 0x9d00, 0x9d6c,
1228 0x9d80, 0x9dec,
1229 0x9e00, 0x9e6c,
1230 0x9e80, 0x9eec,
1231 0x9f00, 0x9f6c,
1232 0x9f80, 0xa020,
1233 0xd004, 0xd004,
1234 0xd010, 0xd03c,
1235 0xdfc0, 0xdfe0,
1236 0xe000, 0x1106c,
1237 0x11074, 0x11088,
1238 0x1109c, 0x1117c,
1239 0x11190, 0x11204,
1240 0x19040, 0x1906c,
1241 0x19078, 0x19080,
1242 0x1908c, 0x190e8,
1243 0x190f0, 0x190f8,
1244 0x19100, 0x19110,
1245 0x19120, 0x19124,
1246 0x19150, 0x19194,
1247 0x1919c, 0x191b0,
1248 0x191d0, 0x191e8,
1249 0x19238, 0x19290,
1250 0x193f8, 0x19428,
1251 0x19430, 0x19444,
1252 0x1944c, 0x1946c,
1253 0x19474, 0x19474,
1254 0x19490, 0x194cc,
1255 0x194f0, 0x194f8,
1256 0x19c00, 0x19c08,
1257 0x19c10, 0x19c60,
1258 0x19c94, 0x19ce4,
1259 0x19cf0, 0x19d40,
1260 0x19d50, 0x19d94,
1261 0x19da0, 0x19de8,
1262 0x19df0, 0x19e10,
1263 0x19e50, 0x19e90,
1264 0x19ea0, 0x19f24,
1265 0x19f34, 0x19f34,
1266 0x19f40, 0x19f50,
1267 0x19f90, 0x19fb4,
1268 0x19fc4, 0x19fe4,
1269 0x1a000, 0x1a004,
1270 0x1a010, 0x1a06c,
1271 0x1a0b0, 0x1a0e4,
1272 0x1a0ec, 0x1a0f8,
1273 0x1a100, 0x1a108,
1274 0x1a114, 0x1a120,
1275 0x1a128, 0x1a130,
1276 0x1a138, 0x1a138,
1277 0x1a190, 0x1a1c4,
1278 0x1a1fc, 0x1a1fc,
1279 0x1e008, 0x1e00c,
1280 0x1e040, 0x1e044,
1281 0x1e04c, 0x1e04c,
1282 0x1e284, 0x1e290,
1283 0x1e2c0, 0x1e2c0,
1284 0x1e2e0, 0x1e2e0,
1285 0x1e300, 0x1e384,
1286 0x1e3c0, 0x1e3c8,
1287 0x1e408, 0x1e40c,
1288 0x1e440, 0x1e444,
1289 0x1e44c, 0x1e44c,
1290 0x1e684, 0x1e690,
1291 0x1e6c0, 0x1e6c0,
1292 0x1e6e0, 0x1e6e0,
1293 0x1e700, 0x1e784,
1294 0x1e7c0, 0x1e7c8,
1295 0x1e808, 0x1e80c,
1296 0x1e840, 0x1e844,
1297 0x1e84c, 0x1e84c,
1298 0x1ea84, 0x1ea90,
1299 0x1eac0, 0x1eac0,
1300 0x1eae0, 0x1eae0,
1301 0x1eb00, 0x1eb84,
1302 0x1ebc0, 0x1ebc8,
1303 0x1ec08, 0x1ec0c,
1304 0x1ec40, 0x1ec44,
1305 0x1ec4c, 0x1ec4c,
1306 0x1ee84, 0x1ee90,
1307 0x1eec0, 0x1eec0,
1308 0x1eee0, 0x1eee0,
1309 0x1ef00, 0x1ef84,
1310 0x1efc0, 0x1efc8,
1311 0x1f008, 0x1f00c,
1312 0x1f040, 0x1f044,
1313 0x1f04c, 0x1f04c,
1314 0x1f284, 0x1f290,
1315 0x1f2c0, 0x1f2c0,
1316 0x1f2e0, 0x1f2e0,
1317 0x1f300, 0x1f384,
1318 0x1f3c0, 0x1f3c8,
1319 0x1f408, 0x1f40c,
1320 0x1f440, 0x1f444,
1321 0x1f44c, 0x1f44c,
1322 0x1f684, 0x1f690,
1323 0x1f6c0, 0x1f6c0,
1324 0x1f6e0, 0x1f6e0,
1325 0x1f700, 0x1f784,
1326 0x1f7c0, 0x1f7c8,
1327 0x1f808, 0x1f80c,
1328 0x1f840, 0x1f844,
1329 0x1f84c, 0x1f84c,
1330 0x1fa84, 0x1fa90,
1331 0x1fac0, 0x1fac0,
1332 0x1fae0, 0x1fae0,
1333 0x1fb00, 0x1fb84,
1334 0x1fbc0, 0x1fbc8,
1335 0x1fc08, 0x1fc0c,
1336 0x1fc40, 0x1fc44,
1337 0x1fc4c, 0x1fc4c,
1338 0x1fe84, 0x1fe90,
1339 0x1fec0, 0x1fec0,
1340 0x1fee0, 0x1fee0,
1341 0x1ff00, 0x1ff84,
1342 0x1ffc0, 0x1ffc8,
1343 0x30000, 0x30030,
1344 0x30038, 0x30038,
1345 0x30040, 0x30040,
1346 0x30100, 0x30144,
1347 0x30190, 0x301a0,
1348 0x301a8, 0x301b8,
1349 0x301c4, 0x301c8,
1350 0x301d0, 0x301d0,
1351 0x30200, 0x30318,
1352 0x30400, 0x304b4,
1353 0x304c0, 0x3052c,
1354 0x30540, 0x3061c,
1355 0x30800, 0x30828,
1356 0x30834, 0x30834,
1357 0x308c0, 0x30908,
1358 0x30910, 0x309ac,
1359 0x30a00, 0x30a14,
1360 0x30a1c, 0x30a2c,
1361 0x30a44, 0x30a50,
1362 0x30a74, 0x30a74,
1363 0x30a7c, 0x30afc,
1364 0x30b08, 0x30c24,
1365 0x30d00, 0x30d00,
1366 0x30d08, 0x30d14,
1367 0x30d1c, 0x30d20,
1368 0x30d3c, 0x30d3c,
1369 0x30d48, 0x30d50,
1370 0x31200, 0x3120c,
1371 0x31220, 0x31220,
1372 0x31240, 0x31240,
1373 0x31600, 0x3160c,
1374 0x31a00, 0x31a1c,
1375 0x31e00, 0x31e20,
1376 0x31e38, 0x31e3c,
1377 0x31e80, 0x31e80,
1378 0x31e88, 0x31ea8,
1379 0x31eb0, 0x31eb4,
1380 0x31ec8, 0x31ed4,
1381 0x31fb8, 0x32004,
1382 0x32200, 0x32200,
1383 0x32208, 0x32240,
1384 0x32248, 0x32280,
1385 0x32288, 0x322c0,
1386 0x322c8, 0x322fc,
1387 0x32600, 0x32630,
1388 0x32a00, 0x32abc,
1389 0x32b00, 0x32b10,
1390 0x32b20, 0x32b30,
1391 0x32b40, 0x32b50,
1392 0x32b60, 0x32b70,
1393 0x33000, 0x33028,
1394 0x33030, 0x33048,
1395 0x33060, 0x33068,
1396 0x33070, 0x3309c,
1397 0x330f0, 0x33128,
1398 0x33130, 0x33148,
1399 0x33160, 0x33168,
1400 0x33170, 0x3319c,
1401 0x331f0, 0x33238,
1402 0x33240, 0x33240,
1403 0x33248, 0x33250,
1404 0x3325c, 0x33264,
1405 0x33270, 0x332b8,
1406 0x332c0, 0x332e4,
1407 0x332f8, 0x33338,
1408 0x33340, 0x33340,
1409 0x33348, 0x33350,
1410 0x3335c, 0x33364,
1411 0x33370, 0x333b8,
1412 0x333c0, 0x333e4,
1413 0x333f8, 0x33428,
1414 0x33430, 0x33448,
1415 0x33460, 0x33468,
1416 0x33470, 0x3349c,
1417 0x334f0, 0x33528,
1418 0x33530, 0x33548,
1419 0x33560, 0x33568,
1420 0x33570, 0x3359c,
1421 0x335f0, 0x33638,
1422 0x33640, 0x33640,
1423 0x33648, 0x33650,
1424 0x3365c, 0x33664,
1425 0x33670, 0x336b8,
1426 0x336c0, 0x336e4,
1427 0x336f8, 0x33738,
1428 0x33740, 0x33740,
1429 0x33748, 0x33750,
1430 0x3375c, 0x33764,
1431 0x33770, 0x337b8,
1432 0x337c0, 0x337e4,
1433 0x337f8, 0x337fc,
1434 0x33814, 0x33814,
1435 0x3382c, 0x3382c,
1436 0x33880, 0x3388c,
1437 0x338e8, 0x338ec,
1438 0x33900, 0x33928,
1439 0x33930, 0x33948,
1440 0x33960, 0x33968,
1441 0x33970, 0x3399c,
1442 0x339f0, 0x33a38,
1443 0x33a40, 0x33a40,
1444 0x33a48, 0x33a50,
1445 0x33a5c, 0x33a64,
1446 0x33a70, 0x33ab8,
1447 0x33ac0, 0x33ae4,
1448 0x33af8, 0x33b10,
1449 0x33b28, 0x33b28,
1450 0x33b3c, 0x33b50,
1451 0x33bf0, 0x33c10,
1452 0x33c28, 0x33c28,
1453 0x33c3c, 0x33c50,
1454 0x33cf0, 0x33cfc,
1455 0x34000, 0x34030,
1456 0x34038, 0x34038,
1457 0x34040, 0x34040,
1458 0x34100, 0x34144,
1459 0x34190, 0x341a0,
1460 0x341a8, 0x341b8,
1461 0x341c4, 0x341c8,
1462 0x341d0, 0x341d0,
1463 0x34200, 0x34318,
1464 0x34400, 0x344b4,
1465 0x344c0, 0x3452c,
1466 0x34540, 0x3461c,
1467 0x34800, 0x34828,
1468 0x34834, 0x34834,
1469 0x348c0, 0x34908,
1470 0x34910, 0x349ac,
1471 0x34a00, 0x34a14,
1472 0x34a1c, 0x34a2c,
1473 0x34a44, 0x34a50,
1474 0x34a74, 0x34a74,
1475 0x34a7c, 0x34afc,
1476 0x34b08, 0x34c24,
1477 0x34d00, 0x34d00,
1478 0x34d08, 0x34d14,
1479 0x34d1c, 0x34d20,
1480 0x34d3c, 0x34d3c,
1481 0x34d48, 0x34d50,
1482 0x35200, 0x3520c,
1483 0x35220, 0x35220,
1484 0x35240, 0x35240,
1485 0x35600, 0x3560c,
1486 0x35a00, 0x35a1c,
1487 0x35e00, 0x35e20,
1488 0x35e38, 0x35e3c,
1489 0x35e80, 0x35e80,
1490 0x35e88, 0x35ea8,
1491 0x35eb0, 0x35eb4,
1492 0x35ec8, 0x35ed4,
1493 0x35fb8, 0x36004,
1494 0x36200, 0x36200,
1495 0x36208, 0x36240,
1496 0x36248, 0x36280,
1497 0x36288, 0x362c0,
1498 0x362c8, 0x362fc,
1499 0x36600, 0x36630,
1500 0x36a00, 0x36abc,
1501 0x36b00, 0x36b10,
1502 0x36b20, 0x36b30,
1503 0x36b40, 0x36b50,
1504 0x36b60, 0x36b70,
1505 0x37000, 0x37028,
1506 0x37030, 0x37048,
1507 0x37060, 0x37068,
1508 0x37070, 0x3709c,
1509 0x370f0, 0x37128,
1510 0x37130, 0x37148,
1511 0x37160, 0x37168,
1512 0x37170, 0x3719c,
1513 0x371f0, 0x37238,
1514 0x37240, 0x37240,
1515 0x37248, 0x37250,
1516 0x3725c, 0x37264,
1517 0x37270, 0x372b8,
1518 0x372c0, 0x372e4,
1519 0x372f8, 0x37338,
1520 0x37340, 0x37340,
1521 0x37348, 0x37350,
1522 0x3735c, 0x37364,
1523 0x37370, 0x373b8,
1524 0x373c0, 0x373e4,
1525 0x373f8, 0x37428,
1526 0x37430, 0x37448,
1527 0x37460, 0x37468,
1528 0x37470, 0x3749c,
1529 0x374f0, 0x37528,
1530 0x37530, 0x37548,
1531 0x37560, 0x37568,
1532 0x37570, 0x3759c,
1533 0x375f0, 0x37638,
1534 0x37640, 0x37640,
1535 0x37648, 0x37650,
1536 0x3765c, 0x37664,
1537 0x37670, 0x376b8,
1538 0x376c0, 0x376e4,
1539 0x376f8, 0x37738,
1540 0x37740, 0x37740,
1541 0x37748, 0x37750,
1542 0x3775c, 0x37764,
1543 0x37770, 0x377b8,
1544 0x377c0, 0x377e4,
1545 0x377f8, 0x377fc,
1546 0x37814, 0x37814,
1547 0x3782c, 0x3782c,
1548 0x37880, 0x3788c,
1549 0x378e8, 0x378ec,
1550 0x37900, 0x37928,
1551 0x37930, 0x37948,
1552 0x37960, 0x37968,
1553 0x37970, 0x3799c,
1554 0x379f0, 0x37a38,
1555 0x37a40, 0x37a40,
1556 0x37a48, 0x37a50,
1557 0x37a5c, 0x37a64,
1558 0x37a70, 0x37ab8,
1559 0x37ac0, 0x37ae4,
1560 0x37af8, 0x37b10,
1561 0x37b28, 0x37b28,
1562 0x37b3c, 0x37b50,
1563 0x37bf0, 0x37c10,
1564 0x37c28, 0x37c28,
1565 0x37c3c, 0x37c50,
1566 0x37cf0, 0x37cfc,
1567 0x38000, 0x38030,
1568 0x38038, 0x38038,
1569 0x38040, 0x38040,
1570 0x38100, 0x38144,
1571 0x38190, 0x381a0,
1572 0x381a8, 0x381b8,
1573 0x381c4, 0x381c8,
1574 0x381d0, 0x381d0,
1575 0x38200, 0x38318,
1576 0x38400, 0x384b4,
1577 0x384c0, 0x3852c,
1578 0x38540, 0x3861c,
1579 0x38800, 0x38828,
1580 0x38834, 0x38834,
1581 0x388c0, 0x38908,
1582 0x38910, 0x389ac,
1583 0x38a00, 0x38a14,
1584 0x38a1c, 0x38a2c,
1585 0x38a44, 0x38a50,
1586 0x38a74, 0x38a74,
1587 0x38a7c, 0x38afc,
1588 0x38b08, 0x38c24,
1589 0x38d00, 0x38d00,
1590 0x38d08, 0x38d14,
1591 0x38d1c, 0x38d20,
1592 0x38d3c, 0x38d3c,
1593 0x38d48, 0x38d50,
1594 0x39200, 0x3920c,
1595 0x39220, 0x39220,
1596 0x39240, 0x39240,
1597 0x39600, 0x3960c,
1598 0x39a00, 0x39a1c,
1599 0x39e00, 0x39e20,
1600 0x39e38, 0x39e3c,
1601 0x39e80, 0x39e80,
1602 0x39e88, 0x39ea8,
1603 0x39eb0, 0x39eb4,
1604 0x39ec8, 0x39ed4,
1605 0x39fb8, 0x3a004,
1606 0x3a200, 0x3a200,
1607 0x3a208, 0x3a240,
1608 0x3a248, 0x3a280,
1609 0x3a288, 0x3a2c0,
1610 0x3a2c8, 0x3a2fc,
1611 0x3a600, 0x3a630,
1612 0x3aa00, 0x3aabc,
1613 0x3ab00, 0x3ab10,
1614 0x3ab20, 0x3ab30,
1615 0x3ab40, 0x3ab50,
1616 0x3ab60, 0x3ab70,
1617 0x3b000, 0x3b028,
1618 0x3b030, 0x3b048,
1619 0x3b060, 0x3b068,
1620 0x3b070, 0x3b09c,
1621 0x3b0f0, 0x3b128,
1622 0x3b130, 0x3b148,
1623 0x3b160, 0x3b168,
1624 0x3b170, 0x3b19c,
1625 0x3b1f0, 0x3b238,
1626 0x3b240, 0x3b240,
1627 0x3b248, 0x3b250,
1628 0x3b25c, 0x3b264,
1629 0x3b270, 0x3b2b8,
1630 0x3b2c0, 0x3b2e4,
1631 0x3b2f8, 0x3b338,
1632 0x3b340, 0x3b340,
1633 0x3b348, 0x3b350,
1634 0x3b35c, 0x3b364,
1635 0x3b370, 0x3b3b8,
1636 0x3b3c0, 0x3b3e4,
1637 0x3b3f8, 0x3b428,
1638 0x3b430, 0x3b448,
1639 0x3b460, 0x3b468,
1640 0x3b470, 0x3b49c,
1641 0x3b4f0, 0x3b528,
1642 0x3b530, 0x3b548,
1643 0x3b560, 0x3b568,
1644 0x3b570, 0x3b59c,
1645 0x3b5f0, 0x3b638,
1646 0x3b640, 0x3b640,
1647 0x3b648, 0x3b650,
1648 0x3b65c, 0x3b664,
1649 0x3b670, 0x3b6b8,
1650 0x3b6c0, 0x3b6e4,
1651 0x3b6f8, 0x3b738,
1652 0x3b740, 0x3b740,
1653 0x3b748, 0x3b750,
1654 0x3b75c, 0x3b764,
1655 0x3b770, 0x3b7b8,
1656 0x3b7c0, 0x3b7e4,
1657 0x3b7f8, 0x3b7fc,
1658 0x3b814, 0x3b814,
1659 0x3b82c, 0x3b82c,
1660 0x3b880, 0x3b88c,
1661 0x3b8e8, 0x3b8ec,
1662 0x3b900, 0x3b928,
1663 0x3b930, 0x3b948,
1664 0x3b960, 0x3b968,
1665 0x3b970, 0x3b99c,
1666 0x3b9f0, 0x3ba38,
1667 0x3ba40, 0x3ba40,
1668 0x3ba48, 0x3ba50,
1669 0x3ba5c, 0x3ba64,
1670 0x3ba70, 0x3bab8,
1671 0x3bac0, 0x3bae4,
1672 0x3baf8, 0x3bb10,
1673 0x3bb28, 0x3bb28,
1674 0x3bb3c, 0x3bb50,
1675 0x3bbf0, 0x3bc10,
1676 0x3bc28, 0x3bc28,
1677 0x3bc3c, 0x3bc50,
1678 0x3bcf0, 0x3bcfc,
1679 0x3c000, 0x3c030,
1680 0x3c038, 0x3c038,
1681 0x3c040, 0x3c040,
1682 0x3c100, 0x3c144,
1683 0x3c190, 0x3c1a0,
1684 0x3c1a8, 0x3c1b8,
1685 0x3c1c4, 0x3c1c8,
1686 0x3c1d0, 0x3c1d0,
1687 0x3c200, 0x3c318,
1688 0x3c400, 0x3c4b4,
1689 0x3c4c0, 0x3c52c,
1690 0x3c540, 0x3c61c,
1691 0x3c800, 0x3c828,
1692 0x3c834, 0x3c834,
1693 0x3c8c0, 0x3c908,
1694 0x3c910, 0x3c9ac,
1695 0x3ca00, 0x3ca14,
1696 0x3ca1c, 0x3ca2c,
1697 0x3ca44, 0x3ca50,
1698 0x3ca74, 0x3ca74,
1699 0x3ca7c, 0x3cafc,
1700 0x3cb08, 0x3cc24,
1701 0x3cd00, 0x3cd00,
1702 0x3cd08, 0x3cd14,
1703 0x3cd1c, 0x3cd20,
1704 0x3cd3c, 0x3cd3c,
1705 0x3cd48, 0x3cd50,
1706 0x3d200, 0x3d20c,
1707 0x3d220, 0x3d220,
1708 0x3d240, 0x3d240,
1709 0x3d600, 0x3d60c,
1710 0x3da00, 0x3da1c,
1711 0x3de00, 0x3de20,
1712 0x3de38, 0x3de3c,
1713 0x3de80, 0x3de80,
1714 0x3de88, 0x3dea8,
1715 0x3deb0, 0x3deb4,
1716 0x3dec8, 0x3ded4,
1717 0x3dfb8, 0x3e004,
1718 0x3e200, 0x3e200,
1719 0x3e208, 0x3e240,
1720 0x3e248, 0x3e280,
1721 0x3e288, 0x3e2c0,
1722 0x3e2c8, 0x3e2fc,
1723 0x3e600, 0x3e630,
1724 0x3ea00, 0x3eabc,
1725 0x3eb00, 0x3eb10,
1726 0x3eb20, 0x3eb30,
1727 0x3eb40, 0x3eb50,
1728 0x3eb60, 0x3eb70,
1729 0x3f000, 0x3f028,
1730 0x3f030, 0x3f048,
1731 0x3f060, 0x3f068,
1732 0x3f070, 0x3f09c,
1733 0x3f0f0, 0x3f128,
1734 0x3f130, 0x3f148,
1735 0x3f160, 0x3f168,
1736 0x3f170, 0x3f19c,
1737 0x3f1f0, 0x3f238,
1738 0x3f240, 0x3f240,
1739 0x3f248, 0x3f250,
1740 0x3f25c, 0x3f264,
1741 0x3f270, 0x3f2b8,
1742 0x3f2c0, 0x3f2e4,
1743 0x3f2f8, 0x3f338,
1744 0x3f340, 0x3f340,
1745 0x3f348, 0x3f350,
1746 0x3f35c, 0x3f364,
1747 0x3f370, 0x3f3b8,
1748 0x3f3c0, 0x3f3e4,
1749 0x3f3f8, 0x3f428,
1750 0x3f430, 0x3f448,
1751 0x3f460, 0x3f468,
1752 0x3f470, 0x3f49c,
1753 0x3f4f0, 0x3f528,
1754 0x3f530, 0x3f548,
1755 0x3f560, 0x3f568,
1756 0x3f570, 0x3f59c,
1757 0x3f5f0, 0x3f638,
1758 0x3f640, 0x3f640,
1759 0x3f648, 0x3f650,
1760 0x3f65c, 0x3f664,
1761 0x3f670, 0x3f6b8,
1762 0x3f6c0, 0x3f6e4,
1763 0x3f6f8, 0x3f738,
1764 0x3f740, 0x3f740,
1765 0x3f748, 0x3f750,
1766 0x3f75c, 0x3f764,
1767 0x3f770, 0x3f7b8,
1768 0x3f7c0, 0x3f7e4,
1769 0x3f7f8, 0x3f7fc,
1770 0x3f814, 0x3f814,
1771 0x3f82c, 0x3f82c,
1772 0x3f880, 0x3f88c,
1773 0x3f8e8, 0x3f8ec,
1774 0x3f900, 0x3f928,
1775 0x3f930, 0x3f948,
1776 0x3f960, 0x3f968,
1777 0x3f970, 0x3f99c,
1778 0x3f9f0, 0x3fa38,
1779 0x3fa40, 0x3fa40,
1780 0x3fa48, 0x3fa50,
1781 0x3fa5c, 0x3fa64,
1782 0x3fa70, 0x3fab8,
1783 0x3fac0, 0x3fae4,
1784 0x3faf8, 0x3fb10,
1785 0x3fb28, 0x3fb28,
1786 0x3fb3c, 0x3fb50,
1787 0x3fbf0, 0x3fc10,
1788 0x3fc28, 0x3fc28,
1789 0x3fc3c, 0x3fc50,
1790 0x3fcf0, 0x3fcfc,
1791 0x40000, 0x4000c,
1792 0x40040, 0x40050,
1793 0x40060, 0x40068,
1794 0x4007c, 0x4008c,
1795 0x40094, 0x400b0,
1796 0x400c0, 0x40144,
1797 0x40180, 0x4018c,
1798 0x40200, 0x40254,
1799 0x40260, 0x40264,
1800 0x40270, 0x40288,
1801 0x40290, 0x40298,
1802 0x402ac, 0x402c8,
1803 0x402d0, 0x402e0,
1804 0x402f0, 0x402f0,
1805 0x40300, 0x4033c,
1806 0x403f8, 0x403fc,
1807 0x41304, 0x413c4,
1808 0x41400, 0x4140c,
1809 0x41414, 0x4141c,
1810 0x41480, 0x414d0,
1811 0x44000, 0x44054,
1812 0x4405c, 0x44078,
1813 0x440c0, 0x44174,
1814 0x44180, 0x441ac,
1815 0x441b4, 0x441b8,
1816 0x441c0, 0x44254,
1817 0x4425c, 0x44278,
1818 0x442c0, 0x44374,
1819 0x44380, 0x443ac,
1820 0x443b4, 0x443b8,
1821 0x443c0, 0x44454,
1822 0x4445c, 0x44478,
1823 0x444c0, 0x44574,
1824 0x44580, 0x445ac,
1825 0x445b4, 0x445b8,
1826 0x445c0, 0x44654,
1827 0x4465c, 0x44678,
1828 0x446c0, 0x44774,
1829 0x44780, 0x447ac,
1830 0x447b4, 0x447b8,
1831 0x447c0, 0x44854,
1832 0x4485c, 0x44878,
1833 0x448c0, 0x44974,
1834 0x44980, 0x449ac,
1835 0x449b4, 0x449b8,
1836 0x449c0, 0x449fc,
1837 0x45000, 0x45004,
1838 0x45010, 0x45030,
1839 0x45040, 0x45060,
1840 0x45068, 0x45068,
1841 0x45080, 0x45084,
1842 0x450a0, 0x450b0,
1843 0x45200, 0x45204,
1844 0x45210, 0x45230,
1845 0x45240, 0x45260,
1846 0x45268, 0x45268,
1847 0x45280, 0x45284,
1848 0x452a0, 0x452b0,
1849 0x460c0, 0x460e4,
1850 0x47000, 0x4703c,
1851 0x47044, 0x4708c,
1852 0x47200, 0x47250,
1853 0x47400, 0x47408,
1854 0x47414, 0x47420,
1855 0x47600, 0x47618,
1856 0x47800, 0x47814,
1857 0x48000, 0x4800c,
1858 0x48040, 0x48050,
1859 0x48060, 0x48068,
1860 0x4807c, 0x4808c,
1861 0x48094, 0x480b0,
1862 0x480c0, 0x48144,
1863 0x48180, 0x4818c,
1864 0x48200, 0x48254,
1865 0x48260, 0x48264,
1866 0x48270, 0x48288,
1867 0x48290, 0x48298,
1868 0x482ac, 0x482c8,
1869 0x482d0, 0x482e0,
1870 0x482f0, 0x482f0,
1871 0x48300, 0x4833c,
1872 0x483f8, 0x483fc,
1873 0x49304, 0x493c4,
1874 0x49400, 0x4940c,
1875 0x49414, 0x4941c,
1876 0x49480, 0x494d0,
1877 0x4c000, 0x4c054,
1878 0x4c05c, 0x4c078,
1879 0x4c0c0, 0x4c174,
1880 0x4c180, 0x4c1ac,
1881 0x4c1b4, 0x4c1b8,
1882 0x4c1c0, 0x4c254,
1883 0x4c25c, 0x4c278,
1884 0x4c2c0, 0x4c374,
1885 0x4c380, 0x4c3ac,
1886 0x4c3b4, 0x4c3b8,
1887 0x4c3c0, 0x4c454,
1888 0x4c45c, 0x4c478,
1889 0x4c4c0, 0x4c574,
1890 0x4c580, 0x4c5ac,
1891 0x4c5b4, 0x4c5b8,
1892 0x4c5c0, 0x4c654,
1893 0x4c65c, 0x4c678,
1894 0x4c6c0, 0x4c774,
1895 0x4c780, 0x4c7ac,
1896 0x4c7b4, 0x4c7b8,
1897 0x4c7c0, 0x4c854,
1898 0x4c85c, 0x4c878,
1899 0x4c8c0, 0x4c974,
1900 0x4c980, 0x4c9ac,
1901 0x4c9b4, 0x4c9b8,
1902 0x4c9c0, 0x4c9fc,
1903 0x4d000, 0x4d004,
1904 0x4d010, 0x4d030,
1905 0x4d040, 0x4d060,
1906 0x4d068, 0x4d068,
1907 0x4d080, 0x4d084,
1908 0x4d0a0, 0x4d0b0,
1909 0x4d200, 0x4d204,
1910 0x4d210, 0x4d230,
1911 0x4d240, 0x4d260,
1912 0x4d268, 0x4d268,
1913 0x4d280, 0x4d284,
1914 0x4d2a0, 0x4d2b0,
1915 0x4e0c0, 0x4e0e4,
1916 0x4f000, 0x4f03c,
1917 0x4f044, 0x4f08c,
1918 0x4f200, 0x4f250,
1919 0x4f400, 0x4f408,
1920 0x4f414, 0x4f420,
1921 0x4f600, 0x4f618,
1922 0x4f800, 0x4f814,
1923 0x50000, 0x50084,
1924 0x50090, 0x500cc,
1925 0x50400, 0x50400,
1926 0x50800, 0x50884,
1927 0x50890, 0x508cc,
1928 0x50c00, 0x50c00,
1929 0x51000, 0x5101c,
1930 0x51300, 0x51308,
1931 };
1932
1933 static const unsigned int t6_reg_ranges[] = {
1934 0x1008, 0x101c,
1935 0x1024, 0x10a8,
1936 0x10b4, 0x10f8,
1937 0x1100, 0x1114,
1938 0x111c, 0x112c,
1939 0x1138, 0x113c,
1940 0x1144, 0x114c,
1941 0x1180, 0x1184,
1942 0x1190, 0x1194,
1943 0x11a0, 0x11a4,
1944 0x11b0, 0x11b4,
1945 0x11fc, 0x1258,
1946 0x1280, 0x12d4,
1947 0x12d9, 0x12d9,
1948 0x12de, 0x12de,
1949 0x12e3, 0x12e3,
1950 0x12e8, 0x133c,
1951 0x1800, 0x18fc,
1952 0x3000, 0x302c,
1953 0x3060, 0x30b0,
1954 0x30b8, 0x30d8,
1955 0x30e0, 0x30fc,
1956 0x3140, 0x357c,
1957 0x35a8, 0x35cc,
1958 0x35ec, 0x35ec,
1959 0x3600, 0x5624,
1960 0x56cc, 0x56ec,
1961 0x56f4, 0x5720,
1962 0x5728, 0x575c,
1963 0x580c, 0x5814,
1964 0x5890, 0x589c,
1965 0x58a4, 0x58ac,
1966 0x58b8, 0x58bc,
1967 0x5940, 0x595c,
1968 0x5980, 0x598c,
1969 0x59b0, 0x59c8,
1970 0x59d0, 0x59dc,
1971 0x59fc, 0x5a18,
1972 0x5a60, 0x5a6c,
1973 0x5a80, 0x5a8c,
1974 0x5a94, 0x5a9c,
1975 0x5b94, 0x5bfc,
1976 0x5c10, 0x5e48,
1977 0x5e50, 0x5e94,
1978 0x5ea0, 0x5eb0,
1979 0x5ec0, 0x5ec0,
1980 0x5ec8, 0x5ed0,
1981 0x6000, 0x6020,
1982 0x6028, 0x6040,
1983 0x6058, 0x609c,
1984 0x60a8, 0x619c,
1985 0x7700, 0x7798,
1986 0x77c0, 0x7880,
1987 0x78cc, 0x78fc,
1988 0x7b00, 0x7b58,
1989 0x7b60, 0x7b84,
1990 0x7b8c, 0x7c54,
1991 0x7d00, 0x7d38,
1992 0x7d40, 0x7d84,
1993 0x7d8c, 0x7ddc,
1994 0x7de4, 0x7e04,
1995 0x7e10, 0x7e1c,
1996 0x7e24, 0x7e38,
1997 0x7e40, 0x7e44,
1998 0x7e4c, 0x7e78,
1999 0x7e80, 0x7edc,
2000 0x7ee8, 0x7efc,
2001 0x8dc0, 0x8de4,
2002 0x8df8, 0x8e04,
2003 0x8e10, 0x8e84,
2004 0x8ea0, 0x8f88,
2005 0x8fb8, 0x9058,
2006 0x9060, 0x9060,
2007 0x9068, 0x90f8,
2008 0x9100, 0x9124,
2009 0x9400, 0x9470,
2010 0x9600, 0x9600,
2011 0x9608, 0x9638,
2012 0x9640, 0x9704,
2013 0x9710, 0x971c,
2014 0x9800, 0x9808,
2015 0x9820, 0x983c,
2016 0x9850, 0x9864,
2017 0x9c00, 0x9c6c,
2018 0x9c80, 0x9cec,
2019 0x9d00, 0x9d6c,
2020 0x9d80, 0x9dec,
2021 0x9e00, 0x9e6c,
2022 0x9e80, 0x9eec,
2023 0x9f00, 0x9f6c,
2024 0x9f80, 0xa020,
2025 0xd004, 0xd03c,
2026 0xd100, 0xd118,
2027 0xd200, 0xd214,
2028 0xd220, 0xd234,
2029 0xd240, 0xd254,
2030 0xd260, 0xd274,
2031 0xd280, 0xd294,
2032 0xd2a0, 0xd2b4,
2033 0xd2c0, 0xd2d4,
2034 0xd2e0, 0xd2f4,
2035 0xd300, 0xd31c,
2036 0xdfc0, 0xdfe0,
2037 0xe000, 0xf008,
2038 0x11000, 0x11014,
2039 0x11048, 0x1106c,
2040 0x11074, 0x11088,
2041 0x11098, 0x11120,
2042 0x1112c, 0x1117c,
2043 0x11190, 0x112e0,
2044 0x11300, 0x1130c,
2045 0x12000, 0x1206c,
2046 0x19040, 0x1906c,
2047 0x19078, 0x19080,
2048 0x1908c, 0x190e8,
2049 0x190f0, 0x190f8,
2050 0x19100, 0x19110,
2051 0x19120, 0x19124,
2052 0x19150, 0x19194,
2053 0x1919c, 0x191b0,
2054 0x191d0, 0x191e8,
2055 0x19238, 0x19290,
2056 0x192a4, 0x192b0,
2057 0x192bc, 0x192bc,
2058 0x19348, 0x1934c,
2059 0x193f8, 0x19418,
2060 0x19420, 0x19428,
2061 0x19430, 0x19444,
2062 0x1944c, 0x1946c,
2063 0x19474, 0x19474,
2064 0x19490, 0x194cc,
2065 0x194f0, 0x194f8,
2066 0x19c00, 0x19c48,
2067 0x19c50, 0x19c80,
2068 0x19c94, 0x19c98,
2069 0x19ca0, 0x19cbc,
2070 0x19ce4, 0x19ce4,
2071 0x19cf0, 0x19cf8,
2072 0x19d00, 0x19d28,
2073 0x19d50, 0x19d78,
2074 0x19d94, 0x19d98,
2075 0x19da0, 0x19dc8,
2076 0x19df0, 0x19e10,
2077 0x19e50, 0x19e6c,
2078 0x19ea0, 0x19ebc,
2079 0x19ec4, 0x19ef4,
2080 0x19f04, 0x19f2c,
2081 0x19f34, 0x19f34,
2082 0x19f40, 0x19f50,
2083 0x19f90, 0x19fac,
2084 0x19fc4, 0x19fc8,
2085 0x19fd0, 0x19fe4,
2086 0x1a000, 0x1a004,
2087 0x1a010, 0x1a06c,
2088 0x1a0b0, 0x1a0e4,
2089 0x1a0ec, 0x1a0f8,
2090 0x1a100, 0x1a108,
2091 0x1a114, 0x1a120,
2092 0x1a128, 0x1a130,
2093 0x1a138, 0x1a138,
2094 0x1a190, 0x1a1c4,
2095 0x1a1fc, 0x1a1fc,
2096 0x1e008, 0x1e00c,
2097 0x1e040, 0x1e044,
2098 0x1e04c, 0x1e04c,
2099 0x1e284, 0x1e290,
2100 0x1e2c0, 0x1e2c0,
2101 0x1e2e0, 0x1e2e0,
2102 0x1e300, 0x1e384,
2103 0x1e3c0, 0x1e3c8,
2104 0x1e408, 0x1e40c,
2105 0x1e440, 0x1e444,
2106 0x1e44c, 0x1e44c,
2107 0x1e684, 0x1e690,
2108 0x1e6c0, 0x1e6c0,
2109 0x1e6e0, 0x1e6e0,
2110 0x1e700, 0x1e784,
2111 0x1e7c0, 0x1e7c8,
2112 0x1e808, 0x1e80c,
2113 0x1e840, 0x1e844,
2114 0x1e84c, 0x1e84c,
2115 0x1ea84, 0x1ea90,
2116 0x1eac0, 0x1eac0,
2117 0x1eae0, 0x1eae0,
2118 0x1eb00, 0x1eb84,
2119 0x1ebc0, 0x1ebc8,
2120 0x1ec08, 0x1ec0c,
2121 0x1ec40, 0x1ec44,
2122 0x1ec4c, 0x1ec4c,
2123 0x1ee84, 0x1ee90,
2124 0x1eec0, 0x1eec0,
2125 0x1eee0, 0x1eee0,
2126 0x1ef00, 0x1ef84,
2127 0x1efc0, 0x1efc8,
2128 0x1f008, 0x1f00c,
2129 0x1f040, 0x1f044,
2130 0x1f04c, 0x1f04c,
2131 0x1f284, 0x1f290,
2132 0x1f2c0, 0x1f2c0,
2133 0x1f2e0, 0x1f2e0,
2134 0x1f300, 0x1f384,
2135 0x1f3c0, 0x1f3c8,
2136 0x1f408, 0x1f40c,
2137 0x1f440, 0x1f444,
2138 0x1f44c, 0x1f44c,
2139 0x1f684, 0x1f690,
2140 0x1f6c0, 0x1f6c0,
2141 0x1f6e0, 0x1f6e0,
2142 0x1f700, 0x1f784,
2143 0x1f7c0, 0x1f7c8,
2144 0x1f808, 0x1f80c,
2145 0x1f840, 0x1f844,
2146 0x1f84c, 0x1f84c,
2147 0x1fa84, 0x1fa90,
2148 0x1fac0, 0x1fac0,
2149 0x1fae0, 0x1fae0,
2150 0x1fb00, 0x1fb84,
2151 0x1fbc0, 0x1fbc8,
2152 0x1fc08, 0x1fc0c,
2153 0x1fc40, 0x1fc44,
2154 0x1fc4c, 0x1fc4c,
2155 0x1fe84, 0x1fe90,
2156 0x1fec0, 0x1fec0,
2157 0x1fee0, 0x1fee0,
2158 0x1ff00, 0x1ff84,
2159 0x1ffc0, 0x1ffc8,
2160 0x30000, 0x30030,
2161 0x30038, 0x30038,
2162 0x30040, 0x30040,
2163 0x30048, 0x30048,
2164 0x30050, 0x30050,
2165 0x3005c, 0x30060,
2166 0x30068, 0x30068,
2167 0x30070, 0x30070,
2168 0x30100, 0x30168,
2169 0x30190, 0x301a0,
2170 0x301a8, 0x301b8,
2171 0x301c4, 0x301c8,
2172 0x301d0, 0x301d0,
2173 0x30200, 0x30320,
2174 0x30400, 0x304b4,
2175 0x304c0, 0x3052c,
2176 0x30540, 0x3061c,
2177 0x30800, 0x308a0,
2178 0x308c0, 0x30908,
2179 0x30910, 0x309b8,
2180 0x30a00, 0x30a04,
2181 0x30a0c, 0x30a14,
2182 0x30a1c, 0x30a2c,
2183 0x30a44, 0x30a50,
2184 0x30a74, 0x30a74,
2185 0x30a7c, 0x30afc,
2186 0x30b08, 0x30c24,
2187 0x30d00, 0x30d14,
2188 0x30d1c, 0x30d3c,
2189 0x30d44, 0x30d4c,
2190 0x30d54, 0x30d74,
2191 0x30d7c, 0x30d7c,
2192 0x30de0, 0x30de0,
2193 0x30e00, 0x30ed4,
2194 0x30f00, 0x30fa4,
2195 0x30fc0, 0x30fc4,
2196 0x31000, 0x31004,
2197 0x31080, 0x310fc,
2198 0x31208, 0x31220,
2199 0x3123c, 0x31254,
2200 0x31300, 0x31300,
2201 0x31308, 0x3131c,
2202 0x31338, 0x3133c,
2203 0x31380, 0x31380,
2204 0x31388, 0x313a8,
2205 0x313b4, 0x313b4,
2206 0x31400, 0x31420,
2207 0x31438, 0x3143c,
2208 0x31480, 0x31480,
2209 0x314a8, 0x314a8,
2210 0x314b0, 0x314b4,
2211 0x314c8, 0x314d4,
2212 0x31a40, 0x31a4c,
2213 0x31af0, 0x31b20,
2214 0x31b38, 0x31b3c,
2215 0x31b80, 0x31b80,
2216 0x31ba8, 0x31ba8,
2217 0x31bb0, 0x31bb4,
2218 0x31bc8, 0x31bd4,
2219 0x32140, 0x3218c,
2220 0x321f0, 0x321f4,
2221 0x32200, 0x32200,
2222 0x32218, 0x32218,
2223 0x32400, 0x32400,
2224 0x32408, 0x3241c,
2225 0x32618, 0x32620,
2226 0x32664, 0x32664,
2227 0x326a8, 0x326a8,
2228 0x326ec, 0x326ec,
2229 0x32a00, 0x32abc,
2230 0x32b00, 0x32b38,
2231 0x32b40, 0x32b58,
2232 0x32b60, 0x32b78,
2233 0x32c00, 0x32c00,
2234 0x32c08, 0x32c3c,
2235 0x32e00, 0x32e2c,
2236 0x32f00, 0x32f2c,
2237 0x33000, 0x3302c,
2238 0x33034, 0x33050,
2239 0x33058, 0x33058,
2240 0x33060, 0x3308c,
2241 0x3309c, 0x330ac,
2242 0x330c0, 0x330c0,
2243 0x330c8, 0x330d0,
2244 0x330d8, 0x330e0,
2245 0x330ec, 0x3312c,
2246 0x33134, 0x33150,
2247 0x33158, 0x33158,
2248 0x33160, 0x3318c,
2249 0x3319c, 0x331ac,
2250 0x331c0, 0x331c0,
2251 0x331c8, 0x331d0,
2252 0x331d8, 0x331e0,
2253 0x331ec, 0x33290,
2254 0x33298, 0x332c4,
2255 0x332e4, 0x33390,
2256 0x33398, 0x333c4,
2257 0x333e4, 0x3342c,
2258 0x33434, 0x33450,
2259 0x33458, 0x33458,
2260 0x33460, 0x3348c,
2261 0x3349c, 0x334ac,
2262 0x334c0, 0x334c0,
2263 0x334c8, 0x334d0,
2264 0x334d8, 0x334e0,
2265 0x334ec, 0x3352c,
2266 0x33534, 0x33550,
2267 0x33558, 0x33558,
2268 0x33560, 0x3358c,
2269 0x3359c, 0x335ac,
2270 0x335c0, 0x335c0,
2271 0x335c8, 0x335d0,
2272 0x335d8, 0x335e0,
2273 0x335ec, 0x33690,
2274 0x33698, 0x336c4,
2275 0x336e4, 0x33790,
2276 0x33798, 0x337c4,
2277 0x337e4, 0x337fc,
2278 0x33814, 0x33814,
2279 0x33854, 0x33868,
2280 0x33880, 0x3388c,
2281 0x338c0, 0x338d0,
2282 0x338e8, 0x338ec,
2283 0x33900, 0x3392c,
2284 0x33934, 0x33950,
2285 0x33958, 0x33958,
2286 0x33960, 0x3398c,
2287 0x3399c, 0x339ac,
2288 0x339c0, 0x339c0,
2289 0x339c8, 0x339d0,
2290 0x339d8, 0x339e0,
2291 0x339ec, 0x33a90,
2292 0x33a98, 0x33ac4,
2293 0x33ae4, 0x33b10,
2294 0x33b24, 0x33b28,
2295 0x33b38, 0x33b50,
2296 0x33bf0, 0x33c10,
2297 0x33c24, 0x33c28,
2298 0x33c38, 0x33c50,
2299 0x33cf0, 0x33cfc,
2300 0x34000, 0x34030,
2301 0x34038, 0x34038,
2302 0x34040, 0x34040,
2303 0x34048, 0x34048,
2304 0x34050, 0x34050,
2305 0x3405c, 0x34060,
2306 0x34068, 0x34068,
2307 0x34070, 0x34070,
2308 0x34100, 0x34168,
2309 0x34190, 0x341a0,
2310 0x341a8, 0x341b8,
2311 0x341c4, 0x341c8,
2312 0x341d0, 0x341d0,
2313 0x34200, 0x34320,
2314 0x34400, 0x344b4,
2315 0x344c0, 0x3452c,
2316 0x34540, 0x3461c,
2317 0x34800, 0x348a0,
2318 0x348c0, 0x34908,
2319 0x34910, 0x349b8,
2320 0x34a00, 0x34a04,
2321 0x34a0c, 0x34a14,
2322 0x34a1c, 0x34a2c,
2323 0x34a44, 0x34a50,
2324 0x34a74, 0x34a74,
2325 0x34a7c, 0x34afc,
2326 0x34b08, 0x34c24,
2327 0x34d00, 0x34d14,
2328 0x34d1c, 0x34d3c,
2329 0x34d44, 0x34d4c,
2330 0x34d54, 0x34d74,
2331 0x34d7c, 0x34d7c,
2332 0x34de0, 0x34de0,
2333 0x34e00, 0x34ed4,
2334 0x34f00, 0x34fa4,
2335 0x34fc0, 0x34fc4,
2336 0x35000, 0x35004,
2337 0x35080, 0x350fc,
2338 0x35208, 0x35220,
2339 0x3523c, 0x35254,
2340 0x35300, 0x35300,
2341 0x35308, 0x3531c,
2342 0x35338, 0x3533c,
2343 0x35380, 0x35380,
2344 0x35388, 0x353a8,
2345 0x353b4, 0x353b4,
2346 0x35400, 0x35420,
2347 0x35438, 0x3543c,
2348 0x35480, 0x35480,
2349 0x354a8, 0x354a8,
2350 0x354b0, 0x354b4,
2351 0x354c8, 0x354d4,
2352 0x35a40, 0x35a4c,
2353 0x35af0, 0x35b20,
2354 0x35b38, 0x35b3c,
2355 0x35b80, 0x35b80,
2356 0x35ba8, 0x35ba8,
2357 0x35bb0, 0x35bb4,
2358 0x35bc8, 0x35bd4,
2359 0x36140, 0x3618c,
2360 0x361f0, 0x361f4,
2361 0x36200, 0x36200,
2362 0x36218, 0x36218,
2363 0x36400, 0x36400,
2364 0x36408, 0x3641c,
2365 0x36618, 0x36620,
2366 0x36664, 0x36664,
2367 0x366a8, 0x366a8,
2368 0x366ec, 0x366ec,
2369 0x36a00, 0x36abc,
2370 0x36b00, 0x36b38,
2371 0x36b40, 0x36b58,
2372 0x36b60, 0x36b78,
2373 0x36c00, 0x36c00,
2374 0x36c08, 0x36c3c,
2375 0x36e00, 0x36e2c,
2376 0x36f00, 0x36f2c,
2377 0x37000, 0x3702c,
2378 0x37034, 0x37050,
2379 0x37058, 0x37058,
2380 0x37060, 0x3708c,
2381 0x3709c, 0x370ac,
2382 0x370c0, 0x370c0,
2383 0x370c8, 0x370d0,
2384 0x370d8, 0x370e0,
2385 0x370ec, 0x3712c,
2386 0x37134, 0x37150,
2387 0x37158, 0x37158,
2388 0x37160, 0x3718c,
2389 0x3719c, 0x371ac,
2390 0x371c0, 0x371c0,
2391 0x371c8, 0x371d0,
2392 0x371d8, 0x371e0,
2393 0x371ec, 0x37290,
2394 0x37298, 0x372c4,
2395 0x372e4, 0x37390,
2396 0x37398, 0x373c4,
2397 0x373e4, 0x3742c,
2398 0x37434, 0x37450,
2399 0x37458, 0x37458,
2400 0x37460, 0x3748c,
2401 0x3749c, 0x374ac,
2402 0x374c0, 0x374c0,
2403 0x374c8, 0x374d0,
2404 0x374d8, 0x374e0,
2405 0x374ec, 0x3752c,
2406 0x37534, 0x37550,
2407 0x37558, 0x37558,
2408 0x37560, 0x3758c,
2409 0x3759c, 0x375ac,
2410 0x375c0, 0x375c0,
2411 0x375c8, 0x375d0,
2412 0x375d8, 0x375e0,
2413 0x375ec, 0x37690,
2414 0x37698, 0x376c4,
2415 0x376e4, 0x37790,
2416 0x37798, 0x377c4,
2417 0x377e4, 0x377fc,
2418 0x37814, 0x37814,
2419 0x37854, 0x37868,
2420 0x37880, 0x3788c,
2421 0x378c0, 0x378d0,
2422 0x378e8, 0x378ec,
2423 0x37900, 0x3792c,
2424 0x37934, 0x37950,
2425 0x37958, 0x37958,
2426 0x37960, 0x3798c,
2427 0x3799c, 0x379ac,
2428 0x379c0, 0x379c0,
2429 0x379c8, 0x379d0,
2430 0x379d8, 0x379e0,
2431 0x379ec, 0x37a90,
2432 0x37a98, 0x37ac4,
2433 0x37ae4, 0x37b10,
2434 0x37b24, 0x37b28,
2435 0x37b38, 0x37b50,
2436 0x37bf0, 0x37c10,
2437 0x37c24, 0x37c28,
2438 0x37c38, 0x37c50,
2439 0x37cf0, 0x37cfc,
2440 0x40040, 0x40040,
2441 0x40080, 0x40084,
2442 0x40100, 0x40100,
2443 0x40140, 0x401bc,
2444 0x40200, 0x40214,
2445 0x40228, 0x40228,
2446 0x40240, 0x40258,
2447 0x40280, 0x40280,
2448 0x40304, 0x40304,
2449 0x40330, 0x4033c,
2450 0x41304, 0x413b8,
2451 0x413c0, 0x413c8,
2452 0x413d0, 0x413dc,
2453 0x413f0, 0x413f0,
2454 0x41400, 0x4140c,
2455 0x41414, 0x4141c,
2456 0x41480, 0x414d0,
2457 0x44000, 0x4407c,
2458 0x440c0, 0x441ac,
2459 0x441b4, 0x4427c,
2460 0x442c0, 0x443ac,
2461 0x443b4, 0x4447c,
2462 0x444c0, 0x445ac,
2463 0x445b4, 0x4467c,
2464 0x446c0, 0x447ac,
2465 0x447b4, 0x4487c,
2466 0x448c0, 0x449ac,
2467 0x449b4, 0x44a7c,
2468 0x44ac0, 0x44bac,
2469 0x44bb4, 0x44c7c,
2470 0x44cc0, 0x44dac,
2471 0x44db4, 0x44e7c,
2472 0x44ec0, 0x44fac,
2473 0x44fb4, 0x4507c,
2474 0x450c0, 0x451ac,
2475 0x451b4, 0x451fc,
2476 0x45800, 0x45804,
2477 0x45810, 0x45830,
2478 0x45840, 0x45860,
2479 0x45868, 0x45868,
2480 0x45880, 0x45884,
2481 0x458a0, 0x458b0,
2482 0x45a00, 0x45a04,
2483 0x45a10, 0x45a30,
2484 0x45a40, 0x45a60,
2485 0x45a68, 0x45a68,
2486 0x45a80, 0x45a84,
2487 0x45aa0, 0x45ab0,
2488 0x460c0, 0x460e4,
2489 0x47000, 0x4703c,
2490 0x47044, 0x4708c,
2491 0x47200, 0x47250,
2492 0x47400, 0x47408,
2493 0x47414, 0x47420,
2494 0x47600, 0x47618,
2495 0x47800, 0x47814,
2496 0x47820, 0x4782c,
2497 0x50000, 0x50084,
2498 0x50090, 0x500cc,
2499 0x50300, 0x50384,
2500 0x50400, 0x50400,
2501 0x50800, 0x50884,
2502 0x50890, 0x508cc,
2503 0x50b00, 0x50b84,
2504 0x50c00, 0x50c00,
2505 0x51000, 0x51020,
2506 0x51028, 0x510b0,
2507 0x51300, 0x51324,
2508 };
2509
2510 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2511 const unsigned int *reg_ranges;
2512 int reg_ranges_size, range;
2513 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2514
2515 /* Select the right set of register ranges to dump depending on the
2516 * adapter chip type.
2517 */
2518 switch (chip_version) {
2519 case CHELSIO_T4:
2520 reg_ranges = t4_reg_ranges;
2521 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2522 break;
2523
2524 case CHELSIO_T5:
2525 reg_ranges = t5_reg_ranges;
2526 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2527 break;
2528
2529 case CHELSIO_T6:
2530 reg_ranges = t6_reg_ranges;
2531 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2532 break;
2533
2534 default:
2535 dev_err(adap->pdev_dev,
2536 "Unsupported chip version %d\n", chip_version);
2537 return;
2538 }
2539
2540 /* Clear the register buffer and insert the appropriate register
2541 * values selected by the above register ranges.
2542 */
2543 memset(buf, 0, buf_size);
2544 for (range = 0; range < reg_ranges_size; range += 2) {
2545 unsigned int reg = reg_ranges[range];
2546 unsigned int last_reg = reg_ranges[range + 1];
2547 u32 *bufp = (u32 *)((char *)buf + reg);
2548
2549 /* Iterate across the register range filling in the register
2550 * buffer but don't write past the end of the register buffer.
2551 */
2552 while (reg <= last_reg && bufp < buf_end) {
2553 *bufp++ = t4_read_reg(adap, reg);
2554 reg += sizeof(u32);
2555 }
2556 }
2557 }
2558
2559 #define EEPROM_STAT_ADDR 0x7bfc
2560 #define VPD_SIZE 0x800
2561 #define VPD_BASE 0x400
2562 #define VPD_BASE_OLD 0
2563 #define VPD_LEN 1024
2564 #define CHELSIO_VPD_UNIQUE_ID 0x82
2565
2566 /**
2567 * t4_seeprom_wp - enable/disable EEPROM write protection
2568 * @adapter: the adapter
2569 * @enable: whether to enable or disable write protection
2570 *
2571 * Enables or disables write protection on the serial EEPROM.
2572 */
2573 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2574 {
2575 unsigned int v = enable ? 0xc : 0;
2576 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2577 return ret < 0 ? ret : 0;
2578 }
2579
2580 /**
2581 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2582 * @adapter: adapter to read
2583 * @p: where to store the parameters
2584 *
2585 * Reads card parameters stored in VPD EEPROM.
2586 */
2587 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2588 {
2589 int i, ret = 0, addr;
2590 int ec, sn, pn, na;
2591 u8 *vpd, csum;
2592 unsigned int vpdr_len, kw_offset, id_len;
2593
2594 vpd = vmalloc(VPD_LEN);
2595 if (!vpd)
2596 return -ENOMEM;
2597
2598 /* We have two VPD data structures stored in the adapter VPD area.
2599 * By default, Linux calculates the size of the VPD area by traversing
2600 * the first VPD area at offset 0x0, so we need to tell the OS what
2601 * our real VPD size is.
2602 */
2603 ret = pci_set_vpd_size(adapter->pdev, VPD_SIZE);
2604 if (ret < 0)
2605 goto out;
2606
2607 /* Card information normally starts at VPD_BASE but early cards had
2608 * it at 0.
2609 */
2610 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2611 if (ret < 0)
2612 goto out;
2613
2614 /* The VPD shall have a unique identifier specified by the PCI SIG.
2615 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2616 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2617 * is expected to automatically put this entry at the
2618 * beginning of the VPD.
2619 */
2620 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2621
2622 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2623 if (ret < 0)
2624 goto out;
2625
2626 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2627 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2628 ret = -EINVAL;
2629 goto out;
2630 }
2631
2632 id_len = pci_vpd_lrdt_size(vpd);
2633 if (id_len > ID_LEN)
2634 id_len = ID_LEN;
2635
2636 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2637 if (i < 0) {
2638 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2639 ret = -EINVAL;
2640 goto out;
2641 }
2642
2643 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2644 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2645 if (vpdr_len + kw_offset > VPD_LEN) {
2646 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2647 ret = -EINVAL;
2648 goto out;
2649 }
2650
2651 #define FIND_VPD_KW(var, name) do { \
2652 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2653 if (var < 0) { \
2654 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2655 ret = -EINVAL; \
2656 goto out; \
2657 } \
2658 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2659 } while (0)
2660
2661 FIND_VPD_KW(i, "RV");
2662 for (csum = 0; i >= 0; i--)
2663 csum += vpd[i];
2664
2665 if (csum) {
2666 dev_err(adapter->pdev_dev,
2667 "corrupted VPD EEPROM, actual csum %u\n", csum);
2668 ret = -EINVAL;
2669 goto out;
2670 }
2671
2672 FIND_VPD_KW(ec, "EC");
2673 FIND_VPD_KW(sn, "SN");
2674 FIND_VPD_KW(pn, "PN");
2675 FIND_VPD_KW(na, "NA");
2676 #undef FIND_VPD_KW
2677
2678 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2679 strim(p->id);
2680 memcpy(p->ec, vpd + ec, EC_LEN);
2681 strim(p->ec);
2682 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2683 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2684 strim(p->sn);
2685 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2686 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2687 strim(p->pn);
2688 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2689 strim((char *)p->na);
2690
2691 out:
2692 vfree(vpd);
2693 return ret;
2694 }
2695
2696 /**
2697 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2698 * @adapter: adapter to read
2699 * @p: where to store the parameters
2700 *
2701 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2702 * Clock. This can only be called after a connection to the firmware
2703 * is established.
2704 */
2705 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2706 {
2707 u32 cclk_param, cclk_val;
2708 int ret;
2709
2710 /* Grab the raw VPD parameters.
2711 */
2712 ret = t4_get_raw_vpd_params(adapter, p);
2713 if (ret)
2714 return ret;
2715
2716 /* Ask firmware for the Core Clock since it knows how to translate the
2717 * Reference Clock ('V2') VPD field into a Core Clock value ...
2718 */
2719 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2720 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2721 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2722 1, &cclk_param, &cclk_val);
2723
2724 if (ret)
2725 return ret;
2726 p->cclk = cclk_val;
2727
2728 return 0;
2729 }
2730
2731 /* serial flash and firmware constants */
2732 enum {
2733 SF_ATTEMPTS = 10, /* max retries for SF operations */
2734
2735 /* flash command opcodes */
2736 SF_PROG_PAGE = 2, /* program page */
2737 SF_WR_DISABLE = 4, /* disable writes */
2738 SF_RD_STATUS = 5, /* read status register */
2739 SF_WR_ENABLE = 6, /* enable writes */
2740 SF_RD_DATA_FAST = 0xb, /* read flash */
2741 SF_RD_ID = 0x9f, /* read ID */
2742 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2743
2744 FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2745 };
2746
2747 /**
2748 * sf1_read - read data from the serial flash
2749 * @adapter: the adapter
2750 * @byte_cnt: number of bytes to read
2751 * @cont: whether another operation will be chained
2752 * @lock: whether to lock SF for PL access only
2753 * @valp: where to store the read data
2754 *
2755 * Reads up to 4 bytes of data from the serial flash. The location of
2756 * the read needs to be specified prior to calling this by issuing the
2757 * appropriate commands to the serial flash.
2758 */
2759 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2760 int lock, u32 *valp)
2761 {
2762 int ret;
2763
2764 if (!byte_cnt || byte_cnt > 4)
2765 return -EINVAL;
2766 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2767 return -EBUSY;
2768 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2769 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2770 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2771 if (!ret)
2772 *valp = t4_read_reg(adapter, SF_DATA_A);
2773 return ret;
2774 }
2775
2776 /**
2777 * sf1_write - write data to the serial flash
2778 * @adapter: the adapter
2779 * @byte_cnt: number of bytes to write
2780 * @cont: whether another operation will be chained
2781 * @lock: whether to lock SF for PL access only
2782 * @val: value to write
2783 *
2784 * Writes up to 4 bytes of data to the serial flash. The location of
2785 * the write needs to be specified prior to calling this by issuing the
2786 * appropriate commands to the serial flash.
2787 */
2788 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2789 int lock, u32 val)
2790 {
2791 if (!byte_cnt || byte_cnt > 4)
2792 return -EINVAL;
2793 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2794 return -EBUSY;
2795 t4_write_reg(adapter, SF_DATA_A, val);
2796 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2797 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2798 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2799 }
2800
2801 /**
2802 * flash_wait_op - wait for a flash operation to complete
2803 * @adapter: the adapter
2804 * @attempts: max number of polls of the status register
2805 * @delay: delay between polls in ms
2806 *
2807 * Wait for a flash operation to complete by polling the status register.
2808 */
2809 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2810 {
2811 int ret;
2812 u32 status;
2813
2814 while (1) {
2815 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2816 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2817 return ret;
2818 if (!(status & 1))
2819 return 0;
2820 if (--attempts == 0)
2821 return -EAGAIN;
2822 if (delay)
2823 msleep(delay);
2824 }
2825 }
2826
2827 /**
2828 * t4_read_flash - read words from serial flash
2829 * @adapter: the adapter
2830 * @addr: the start address for the read
2831 * @nwords: how many 32-bit words to read
2832 * @data: where to store the read data
2833 * @byte_oriented: whether to store data as bytes or as words
2834 *
2835 * Read the specified number of 32-bit words from the serial flash.
2836 * If @byte_oriented is set the read data is stored as a byte array
2837 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2838 * natural endianness.
2839 */
2840 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2841 unsigned int nwords, u32 *data, int byte_oriented)
2842 {
2843 int ret;
2844
2845 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2846 return -EINVAL;
2847
2848 addr = swab32(addr) | SF_RD_DATA_FAST;
2849
2850 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2851 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2852 return ret;
2853
2854 for ( ; nwords; nwords--, data++) {
2855 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2856 if (nwords == 1)
2857 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2858 if (ret)
2859 return ret;
2860 if (byte_oriented)
2861 *data = (__force __u32)(cpu_to_be32(*data));
2862 }
2863 return 0;
2864 }
2865
2866 /**
2867 * t4_write_flash - write up to a page of data to the serial flash
2868 * @adapter: the adapter
2869 * @addr: the start address to write
2870 * @n: length of data to write in bytes
2871 * @data: the data to write
2872 *
2873 * Writes up to a page of data (256 bytes) to the serial flash starting
2874 * at the given address. All the data must be written to the same page.
2875 */
2876 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2877 unsigned int n, const u8 *data)
2878 {
2879 int ret;
2880 u32 buf[64];
2881 unsigned int i, c, left, val, offset = addr & 0xff;
2882
2883 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2884 return -EINVAL;
2885
2886 val = swab32(addr) | SF_PROG_PAGE;
2887
2888 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2889 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2890 goto unlock;
2891
2892 for (left = n; left; left -= c) {
2893 c = min(left, 4U);
2894 for (val = 0, i = 0; i < c; ++i)
2895 val = (val << 8) + *data++;
2896
2897 ret = sf1_write(adapter, c, c != left, 1, val);
2898 if (ret)
2899 goto unlock;
2900 }
2901 ret = flash_wait_op(adapter, 8, 1);
2902 if (ret)
2903 goto unlock;
2904
2905 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2906
2907 /* Read the page to verify the write succeeded */
2908 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
2909 if (ret)
2910 return ret;
2911
2912 if (memcmp(data - n, (u8 *)buf + offset, n)) {
2913 dev_err(adapter->pdev_dev,
2914 "failed to correctly write the flash page at %#x\n",
2915 addr);
2916 return -EIO;
2917 }
2918 return 0;
2919
2920 unlock:
2921 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2922 return ret;
2923 }
2924
2925 /**
2926 * t4_get_fw_version - read the firmware version
2927 * @adapter: the adapter
2928 * @vers: where to place the version
2929 *
2930 * Reads the FW version from flash.
2931 */
2932 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2933 {
2934 return t4_read_flash(adapter, FLASH_FW_START +
2935 offsetof(struct fw_hdr, fw_ver), 1,
2936 vers, 0);
2937 }
2938
2939 /**
2940 * t4_get_tp_version - read the TP microcode version
2941 * @adapter: the adapter
2942 * @vers: where to place the version
2943 *
2944 * Reads the TP microcode version from flash.
2945 */
2946 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2947 {
2948 return t4_read_flash(adapter, FLASH_FW_START +
2949 offsetof(struct fw_hdr, tp_microcode_ver),
2950 1, vers, 0);
2951 }
2952
2953 /**
2954 * t4_get_exprom_version - return the Expansion ROM version (if any)
2955 * @adapter: the adapter
2956 * @vers: where to place the version
2957 *
2958 * Reads the Expansion ROM header from FLASH and returns the version
2959 * number (if present) through the @vers return value pointer. We return
2960 * this in the Firmware Version Format since it's convenient. Return
2961 * 0 on success, -ENOENT if no Expansion ROM is present.
2962 */
2963 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
2964 {
2965 struct exprom_header {
2966 unsigned char hdr_arr[16]; /* must start with 0x55aa */
2967 unsigned char hdr_ver[4]; /* Expansion ROM version */
2968 } *hdr;
2969 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2970 sizeof(u32))];
2971 int ret;
2972
2973 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
2974 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
2975 0);
2976 if (ret)
2977 return ret;
2978
2979 hdr = (struct exprom_header *)exprom_header_buf;
2980 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2981 return -ENOENT;
2982
2983 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
2984 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
2985 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
2986 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
2987 return 0;
2988 }
2989
2990 /**
2991 * t4_check_fw_version - check if the FW is supported with this driver
2992 * @adap: the adapter
2993 *
2994 * Checks if an adapter's FW is compatible with the driver. Returns 0
2995 * if there's exact match, a negative error if the version could not be
2996 * read or there's a major version mismatch
2997 */
2998 int t4_check_fw_version(struct adapter *adap)
2999 {
3000 int i, ret, major, minor, micro;
3001 int exp_major, exp_minor, exp_micro;
3002 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3003
3004 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3005 /* Try multiple times before returning error */
3006 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3007 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3008
3009 if (ret)
3010 return ret;
3011
3012 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3013 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3014 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3015
3016 switch (chip_version) {
3017 case CHELSIO_T4:
3018 exp_major = T4FW_MIN_VERSION_MAJOR;
3019 exp_minor = T4FW_MIN_VERSION_MINOR;
3020 exp_micro = T4FW_MIN_VERSION_MICRO;
3021 break;
3022 case CHELSIO_T5:
3023 exp_major = T5FW_MIN_VERSION_MAJOR;
3024 exp_minor = T5FW_MIN_VERSION_MINOR;
3025 exp_micro = T5FW_MIN_VERSION_MICRO;
3026 break;
3027 case CHELSIO_T6:
3028 exp_major = T6FW_MIN_VERSION_MAJOR;
3029 exp_minor = T6FW_MIN_VERSION_MINOR;
3030 exp_micro = T6FW_MIN_VERSION_MICRO;
3031 break;
3032 default:
3033 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3034 adap->chip);
3035 return -EINVAL;
3036 }
3037
3038 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3039 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3040 dev_err(adap->pdev_dev,
3041 "Card has firmware version %u.%u.%u, minimum "
3042 "supported firmware is %u.%u.%u.\n", major, minor,
3043 micro, exp_major, exp_minor, exp_micro);
3044 return -EFAULT;
3045 }
3046 return 0;
3047 }
3048
3049 /* Is the given firmware API compatible with the one the driver was compiled
3050 * with?
3051 */
3052 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3053 {
3054
3055 /* short circuit if it's the exact same firmware version */
3056 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3057 return 1;
3058
3059 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3060 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3061 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3062 return 1;
3063 #undef SAME_INTF
3064
3065 return 0;
3066 }
3067
3068 /* The firmware in the filesystem is usable, but should it be installed?
3069 * This routine explains itself in detail if it indicates the filesystem
3070 * firmware should be installed.
3071 */
3072 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3073 int k, int c)
3074 {
3075 const char *reason;
3076
3077 if (!card_fw_usable) {
3078 reason = "incompatible or unusable";
3079 goto install;
3080 }
3081
3082 if (k > c) {
3083 reason = "older than the version supported with this driver";
3084 goto install;
3085 }
3086
3087 return 0;
3088
3089 install:
3090 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3091 "installing firmware %u.%u.%u.%u on card.\n",
3092 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3093 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3094 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3095 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3096
3097 return 1;
3098 }
3099
3100 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3101 const u8 *fw_data, unsigned int fw_size,
3102 struct fw_hdr *card_fw, enum dev_state state,
3103 int *reset)
3104 {
3105 int ret, card_fw_usable, fs_fw_usable;
3106 const struct fw_hdr *fs_fw;
3107 const struct fw_hdr *drv_fw;
3108
3109 drv_fw = &fw_info->fw_hdr;
3110
3111 /* Read the header of the firmware on the card */
3112 ret = -t4_read_flash(adap, FLASH_FW_START,
3113 sizeof(*card_fw) / sizeof(uint32_t),
3114 (uint32_t *)card_fw, 1);
3115 if (ret == 0) {
3116 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3117 } else {
3118 dev_err(adap->pdev_dev,
3119 "Unable to read card's firmware header: %d\n", ret);
3120 card_fw_usable = 0;
3121 }
3122
3123 if (fw_data != NULL) {
3124 fs_fw = (const void *)fw_data;
3125 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3126 } else {
3127 fs_fw = NULL;
3128 fs_fw_usable = 0;
3129 }
3130
3131 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3132 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3133 /* Common case: the firmware on the card is an exact match and
3134 * the filesystem one is an exact match too, or the filesystem
3135 * one is absent/incompatible.
3136 */
3137 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3138 should_install_fs_fw(adap, card_fw_usable,
3139 be32_to_cpu(fs_fw->fw_ver),
3140 be32_to_cpu(card_fw->fw_ver))) {
3141 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3142 fw_size, 0);
3143 if (ret != 0) {
3144 dev_err(adap->pdev_dev,
3145 "failed to install firmware: %d\n", ret);
3146 goto bye;
3147 }
3148
3149 /* Installed successfully, update the cached header too. */
3150 *card_fw = *fs_fw;
3151 card_fw_usable = 1;
3152 *reset = 0; /* already reset as part of load_fw */
3153 }
3154
3155 if (!card_fw_usable) {
3156 uint32_t d, c, k;
3157
3158 d = be32_to_cpu(drv_fw->fw_ver);
3159 c = be32_to_cpu(card_fw->fw_ver);
3160 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3161
3162 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3163 "chip state %d, "
3164 "driver compiled with %d.%d.%d.%d, "
3165 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3166 state,
3167 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3168 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3169 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3170 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3171 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3172 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3173 ret = EINVAL;
3174 goto bye;
3175 }
3176
3177 /* We're using whatever's on the card and it's known to be good. */
3178 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3179 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3180
3181 bye:
3182 return ret;
3183 }
3184
3185 /**
3186 * t4_flash_erase_sectors - erase a range of flash sectors
3187 * @adapter: the adapter
3188 * @start: the first sector to erase
3189 * @end: the last sector to erase
3190 *
3191 * Erases the sectors in the given inclusive range.
3192 */
3193 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3194 {
3195 int ret = 0;
3196
3197 if (end >= adapter->params.sf_nsec)
3198 return -EINVAL;
3199
3200 while (start <= end) {
3201 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3202 (ret = sf1_write(adapter, 4, 0, 1,
3203 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3204 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3205 dev_err(adapter->pdev_dev,
3206 "erase of flash sector %d failed, error %d\n",
3207 start, ret);
3208 break;
3209 }
3210 start++;
3211 }
3212 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3213 return ret;
3214 }
3215
3216 /**
3217 * t4_flash_cfg_addr - return the address of the flash configuration file
3218 * @adapter: the adapter
3219 *
3220 * Return the address within the flash where the Firmware Configuration
3221 * File is stored.
3222 */
3223 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3224 {
3225 if (adapter->params.sf_size == 0x100000)
3226 return FLASH_FPGA_CFG_START;
3227 else
3228 return FLASH_CFG_START;
3229 }
3230
3231 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3232 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3233 * and emit an error message for mismatched firmware to save our caller the
3234 * effort ...
3235 */
3236 static bool t4_fw_matches_chip(const struct adapter *adap,
3237 const struct fw_hdr *hdr)
3238 {
3239 /* The expression below will return FALSE for any unsupported adapter
3240 * which will keep us "honest" in the future ...
3241 */
3242 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3243 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3244 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3245 return true;
3246
3247 dev_err(adap->pdev_dev,
3248 "FW image (%d) is not suitable for this adapter (%d)\n",
3249 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3250 return false;
3251 }
3252
3253 /**
3254 * t4_load_fw - download firmware
3255 * @adap: the adapter
3256 * @fw_data: the firmware image to write
3257 * @size: image size
3258 *
3259 * Write the supplied firmware image to the card's serial flash.
3260 */
3261 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3262 {
3263 u32 csum;
3264 int ret, addr;
3265 unsigned int i;
3266 u8 first_page[SF_PAGE_SIZE];
3267 const __be32 *p = (const __be32 *)fw_data;
3268 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3269 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3270 unsigned int fw_img_start = adap->params.sf_fw_start;
3271 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3272
3273 if (!size) {
3274 dev_err(adap->pdev_dev, "FW image has no data\n");
3275 return -EINVAL;
3276 }
3277 if (size & 511) {
3278 dev_err(adap->pdev_dev,
3279 "FW image size not multiple of 512 bytes\n");
3280 return -EINVAL;
3281 }
3282 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3283 dev_err(adap->pdev_dev,
3284 "FW image size differs from size in FW header\n");
3285 return -EINVAL;
3286 }
3287 if (size > FW_MAX_SIZE) {
3288 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3289 FW_MAX_SIZE);
3290 return -EFBIG;
3291 }
3292 if (!t4_fw_matches_chip(adap, hdr))
3293 return -EINVAL;
3294
3295 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3296 csum += be32_to_cpu(p[i]);
3297
3298 if (csum != 0xffffffff) {
3299 dev_err(adap->pdev_dev,
3300 "corrupted firmware image, checksum %#x\n", csum);
3301 return -EINVAL;
3302 }
3303
3304 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3305 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3306 if (ret)
3307 goto out;
3308
3309 /*
3310 * We write the correct version at the end so the driver can see a bad
3311 * version if the FW write fails. Start by writing a copy of the
3312 * first page with a bad version.
3313 */
3314 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3315 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3316 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3317 if (ret)
3318 goto out;
3319
3320 addr = fw_img_start;
3321 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3322 addr += SF_PAGE_SIZE;
3323 fw_data += SF_PAGE_SIZE;
3324 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3325 if (ret)
3326 goto out;
3327 }
3328
3329 ret = t4_write_flash(adap,
3330 fw_img_start + offsetof(struct fw_hdr, fw_ver),
3331 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3332 out:
3333 if (ret)
3334 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3335 ret);
3336 else
3337 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3338 return ret;
3339 }
3340
3341 /**
3342 * t4_phy_fw_ver - return current PHY firmware version
3343 * @adap: the adapter
3344 * @phy_fw_ver: return value buffer for PHY firmware version
3345 *
3346 * Returns the current version of external PHY firmware on the
3347 * adapter.
3348 */
3349 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3350 {
3351 u32 param, val;
3352 int ret;
3353
3354 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3355 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3356 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3357 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3358 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3359 &param, &val);
3360 if (ret < 0)
3361 return ret;
3362 *phy_fw_ver = val;
3363 return 0;
3364 }
3365
3366 /**
3367 * t4_load_phy_fw - download port PHY firmware
3368 * @adap: the adapter
3369 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3370 * @win_lock: the lock to use to guard the memory copy
3371 * @phy_fw_version: function to check PHY firmware versions
3372 * @phy_fw_data: the PHY firmware image to write
3373 * @phy_fw_size: image size
3374 *
3375 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3376 * @phy_fw_version is supplied, then it will be used to determine if
3377 * it's necessary to perform the transfer by comparing the version
3378 * of any existing adapter PHY firmware with that of the passed in
3379 * PHY firmware image. If @win_lock is non-NULL then it will be used
3380 * around the call to t4_memory_rw() which transfers the PHY firmware
3381 * to the adapter.
3382 *
3383 * A negative error number will be returned if an error occurs. If
3384 * version number support is available and there's no need to upgrade
3385 * the firmware, 0 will be returned. If firmware is successfully
3386 * transferred to the adapter, 1 will be retured.
3387 *
3388 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3389 * a result, a RESET of the adapter would cause that RAM to lose its
3390 * contents. Thus, loading PHY firmware on such adapters must happen
3391 * after any FW_RESET_CMDs ...
3392 */
3393 int t4_load_phy_fw(struct adapter *adap,
3394 int win, spinlock_t *win_lock,
3395 int (*phy_fw_version)(const u8 *, size_t),
3396 const u8 *phy_fw_data, size_t phy_fw_size)
3397 {
3398 unsigned long mtype = 0, maddr = 0;
3399 u32 param, val;
3400 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3401 int ret;
3402
3403 /* If we have version number support, then check to see if the adapter
3404 * already has up-to-date PHY firmware loaded.
3405 */
3406 if (phy_fw_version) {
3407 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3408 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3409 if (ret < 0)
3410 return ret;
3411
3412 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3413 CH_WARN(adap, "PHY Firmware already up-to-date, "
3414 "version %#x\n", cur_phy_fw_ver);
3415 return 0;
3416 }
3417 }
3418
3419 /* Ask the firmware where it wants us to copy the PHY firmware image.
3420 * The size of the file requires a special version of the READ coommand
3421 * which will pass the file size via the values field in PARAMS_CMD and
3422 * retrieve the return value from firmware and place it in the same
3423 * buffer values
3424 */
3425 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3426 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3427 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3428 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3429 val = phy_fw_size;
3430 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3431 &param, &val, 1);
3432 if (ret < 0)
3433 return ret;
3434 mtype = val >> 8;
3435 maddr = (val & 0xff) << 16;
3436
3437 /* Copy the supplied PHY Firmware image to the adapter memory location
3438 * allocated by the adapter firmware.
3439 */
3440 if (win_lock)
3441 spin_lock_bh(win_lock);
3442 ret = t4_memory_rw(adap, win, mtype, maddr,
3443 phy_fw_size, (__be32 *)phy_fw_data,
3444 T4_MEMORY_WRITE);
3445 if (win_lock)
3446 spin_unlock_bh(win_lock);
3447 if (ret)
3448 return ret;
3449
3450 /* Tell the firmware that the PHY firmware image has been written to
3451 * RAM and it can now start copying it over to the PHYs. The chip
3452 * firmware will RESET the affected PHYs as part of this operation
3453 * leaving them running the new PHY firmware image.
3454 */
3455 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3456 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3457 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3458 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3459 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3460 &param, &val, 30000);
3461
3462 /* If we have version number support, then check to see that the new
3463 * firmware got loaded properly.
3464 */
3465 if (phy_fw_version) {
3466 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3467 if (ret < 0)
3468 return ret;
3469
3470 if (cur_phy_fw_ver != new_phy_fw_vers) {
3471 CH_WARN(adap, "PHY Firmware did not update: "
3472 "version on adapter %#x, "
3473 "version flashed %#x\n",
3474 cur_phy_fw_ver, new_phy_fw_vers);
3475 return -ENXIO;
3476 }
3477 }
3478
3479 return 1;
3480 }
3481
3482 /**
3483 * t4_fwcache - firmware cache operation
3484 * @adap: the adapter
3485 * @op : the operation (flush or flush and invalidate)
3486 */
3487 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3488 {
3489 struct fw_params_cmd c;
3490
3491 memset(&c, 0, sizeof(c));
3492 c.op_to_vfn =
3493 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3494 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3495 FW_PARAMS_CMD_PFN_V(adap->pf) |
3496 FW_PARAMS_CMD_VFN_V(0));
3497 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3498 c.param[0].mnem =
3499 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3500 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3501 c.param[0].val = (__force __be32)op;
3502
3503 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3504 }
3505
3506 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3507 unsigned int *pif_req_wrptr,
3508 unsigned int *pif_rsp_wrptr)
3509 {
3510 int i, j;
3511 u32 cfg, val, req, rsp;
3512
3513 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3514 if (cfg & LADBGEN_F)
3515 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3516
3517 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3518 req = POLADBGWRPTR_G(val);
3519 rsp = PILADBGWRPTR_G(val);
3520 if (pif_req_wrptr)
3521 *pif_req_wrptr = req;
3522 if (pif_rsp_wrptr)
3523 *pif_rsp_wrptr = rsp;
3524
3525 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3526 for (j = 0; j < 6; j++) {
3527 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3528 PILADBGRDPTR_V(rsp));
3529 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3530 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3531 req++;
3532 rsp++;
3533 }
3534 req = (req + 2) & POLADBGRDPTR_M;
3535 rsp = (rsp + 2) & PILADBGRDPTR_M;
3536 }
3537 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3538 }
3539
3540 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3541 {
3542 u32 cfg;
3543 int i, j, idx;
3544
3545 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3546 if (cfg & LADBGEN_F)
3547 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3548
3549 for (i = 0; i < CIM_MALA_SIZE; i++) {
3550 for (j = 0; j < 5; j++) {
3551 idx = 8 * i + j;
3552 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3553 PILADBGRDPTR_V(idx));
3554 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3555 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3556 }
3557 }
3558 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3559 }
3560
3561 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3562 {
3563 unsigned int i, j;
3564
3565 for (i = 0; i < 8; i++) {
3566 u32 *p = la_buf + i;
3567
3568 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3569 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3570 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3571 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3572 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3573 }
3574 }
3575
3576 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3577 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
3578 FW_PORT_CAP_ANEG)
3579
3580 /**
3581 * t4_link_l1cfg - apply link configuration to MAC/PHY
3582 * @phy: the PHY to setup
3583 * @mac: the MAC to setup
3584 * @lc: the requested link configuration
3585 *
3586 * Set up a port's MAC and PHY according to a desired link configuration.
3587 * - If the PHY can auto-negotiate first decide what to advertise, then
3588 * enable/disable auto-negotiation as desired, and reset.
3589 * - If the PHY does not auto-negotiate just reset it.
3590 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3591 * otherwise do it later based on the outcome of auto-negotiation.
3592 */
3593 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3594 struct link_config *lc)
3595 {
3596 struct fw_port_cmd c;
3597 unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
3598
3599 lc->link_ok = 0;
3600 if (lc->requested_fc & PAUSE_RX)
3601 fc |= FW_PORT_CAP_FC_RX;
3602 if (lc->requested_fc & PAUSE_TX)
3603 fc |= FW_PORT_CAP_FC_TX;
3604
3605 memset(&c, 0, sizeof(c));
3606 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3607 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3608 FW_PORT_CMD_PORTID_V(port));
3609 c.action_to_len16 =
3610 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3611 FW_LEN16(c));
3612
3613 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3614 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3615 fc);
3616 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3617 } else if (lc->autoneg == AUTONEG_DISABLE) {
3618 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
3619 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3620 } else
3621 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
3622
3623 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3624 }
3625
3626 /**
3627 * t4_restart_aneg - restart autonegotiation
3628 * @adap: the adapter
3629 * @mbox: mbox to use for the FW command
3630 * @port: the port id
3631 *
3632 * Restarts autonegotiation for the selected port.
3633 */
3634 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3635 {
3636 struct fw_port_cmd c;
3637
3638 memset(&c, 0, sizeof(c));
3639 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3640 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3641 FW_PORT_CMD_PORTID_V(port));
3642 c.action_to_len16 =
3643 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3644 FW_LEN16(c));
3645 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3646 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3647 }
3648
3649 typedef void (*int_handler_t)(struct adapter *adap);
3650
3651 struct intr_info {
3652 unsigned int mask; /* bits to check in interrupt status */
3653 const char *msg; /* message to print or NULL */
3654 short stat_idx; /* stat counter to increment or -1 */
3655 unsigned short fatal; /* whether the condition reported is fatal */
3656 int_handler_t int_handler; /* platform-specific int handler */
3657 };
3658
3659 /**
3660 * t4_handle_intr_status - table driven interrupt handler
3661 * @adapter: the adapter that generated the interrupt
3662 * @reg: the interrupt status register to process
3663 * @acts: table of interrupt actions
3664 *
3665 * A table driven interrupt handler that applies a set of masks to an
3666 * interrupt status word and performs the corresponding actions if the
3667 * interrupts described by the mask have occurred. The actions include
3668 * optionally emitting a warning or alert message. The table is terminated
3669 * by an entry specifying mask 0. Returns the number of fatal interrupt
3670 * conditions.
3671 */
3672 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3673 const struct intr_info *acts)
3674 {
3675 int fatal = 0;
3676 unsigned int mask = 0;
3677 unsigned int status = t4_read_reg(adapter, reg);
3678
3679 for ( ; acts->mask; ++acts) {
3680 if (!(status & acts->mask))
3681 continue;
3682 if (acts->fatal) {
3683 fatal++;
3684 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3685 status & acts->mask);
3686 } else if (acts->msg && printk_ratelimit())
3687 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3688 status & acts->mask);
3689 if (acts->int_handler)
3690 acts->int_handler(adapter);
3691 mask |= acts->mask;
3692 }
3693 status &= mask;
3694 if (status) /* clear processed interrupts */
3695 t4_write_reg(adapter, reg, status);
3696 return fatal;
3697 }
3698
3699 /*
3700 * Interrupt handler for the PCIE module.
3701 */
3702 static void pcie_intr_handler(struct adapter *adapter)
3703 {
3704 static const struct intr_info sysbus_intr_info[] = {
3705 { RNPP_F, "RXNP array parity error", -1, 1 },
3706 { RPCP_F, "RXPC array parity error", -1, 1 },
3707 { RCIP_F, "RXCIF array parity error", -1, 1 },
3708 { RCCP_F, "Rx completions control array parity error", -1, 1 },
3709 { RFTP_F, "RXFT array parity error", -1, 1 },
3710 { 0 }
3711 };
3712 static const struct intr_info pcie_port_intr_info[] = {
3713 { TPCP_F, "TXPC array parity error", -1, 1 },
3714 { TNPP_F, "TXNP array parity error", -1, 1 },
3715 { TFTP_F, "TXFT array parity error", -1, 1 },
3716 { TCAP_F, "TXCA array parity error", -1, 1 },
3717 { TCIP_F, "TXCIF array parity error", -1, 1 },
3718 { RCAP_F, "RXCA array parity error", -1, 1 },
3719 { OTDD_F, "outbound request TLP discarded", -1, 1 },
3720 { RDPE_F, "Rx data parity error", -1, 1 },
3721 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
3722 { 0 }
3723 };
3724 static const struct intr_info pcie_intr_info[] = {
3725 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
3726 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
3727 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
3728 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3729 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3730 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3731 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3732 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
3733 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
3734 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3735 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
3736 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3737 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3738 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
3739 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3740 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3741 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
3742 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3743 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3744 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3745 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3746 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
3747 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
3748 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3749 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
3750 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
3751 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
3752 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
3753 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
3754 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
3755 -1, 0 },
3756 { 0 }
3757 };
3758
3759 static struct intr_info t5_pcie_intr_info[] = {
3760 { MSTGRPPERR_F, "Master Response Read Queue parity error",
3761 -1, 1 },
3762 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
3763 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
3764 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3765 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3766 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3767 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3768 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
3769 -1, 1 },
3770 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
3771 -1, 1 },
3772 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3773 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
3774 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3775 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3776 { DREQWRPERR_F, "PCI DMA channel write request parity error",
3777 -1, 1 },
3778 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3779 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3780 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
3781 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3782 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3783 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3784 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3785 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
3786 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
3787 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3788 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
3789 -1, 1 },
3790 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
3791 -1, 1 },
3792 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
3793 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
3794 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3795 { READRSPERR_F, "Outbound read error", -1, 0 },
3796 { 0 }
3797 };
3798
3799 int fat;
3800
3801 if (is_t4(adapter->params.chip))
3802 fat = t4_handle_intr_status(adapter,
3803 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
3804 sysbus_intr_info) +
3805 t4_handle_intr_status(adapter,
3806 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
3807 pcie_port_intr_info) +
3808 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3809 pcie_intr_info);
3810 else
3811 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3812 t5_pcie_intr_info);
3813
3814 if (fat)
3815 t4_fatal_err(adapter);
3816 }
3817
3818 /*
3819 * TP interrupt handler.
3820 */
3821 static void tp_intr_handler(struct adapter *adapter)
3822 {
3823 static const struct intr_info tp_intr_info[] = {
3824 { 0x3fffffff, "TP parity error", -1, 1 },
3825 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
3826 { 0 }
3827 };
3828
3829 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
3830 t4_fatal_err(adapter);
3831 }
3832
3833 /*
3834 * SGE interrupt handler.
3835 */
3836 static void sge_intr_handler(struct adapter *adapter)
3837 {
3838 u64 v;
3839 u32 err;
3840
3841 static const struct intr_info sge_intr_info[] = {
3842 { ERR_CPL_EXCEED_IQE_SIZE_F,
3843 "SGE received CPL exceeding IQE size", -1, 1 },
3844 { ERR_INVALID_CIDX_INC_F,
3845 "SGE GTS CIDX increment too large", -1, 0 },
3846 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
3847 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
3848 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
3849 "SGE IQID > 1023 received CPL for FL", -1, 0 },
3850 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
3851 0 },
3852 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
3853 0 },
3854 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
3855 0 },
3856 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
3857 0 },
3858 { ERR_ING_CTXT_PRIO_F,
3859 "SGE too many priority ingress contexts", -1, 0 },
3860 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
3861 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
3862 { 0 }
3863 };
3864
3865 static struct intr_info t4t5_sge_intr_info[] = {
3866 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
3867 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
3868 { ERR_EGR_CTXT_PRIO_F,
3869 "SGE too many priority egress contexts", -1, 0 },
3870 { 0 }
3871 };
3872
3873 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
3874 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
3875 if (v) {
3876 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
3877 (unsigned long long)v);
3878 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
3879 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
3880 }
3881
3882 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
3883 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
3884 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
3885 t4t5_sge_intr_info);
3886
3887 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
3888 if (err & ERROR_QID_VALID_F) {
3889 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
3890 ERROR_QID_G(err));
3891 if (err & UNCAPTURED_ERROR_F)
3892 dev_err(adapter->pdev_dev,
3893 "SGE UNCAPTURED_ERROR set (clearing)\n");
3894 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
3895 UNCAPTURED_ERROR_F);
3896 }
3897
3898 if (v != 0)
3899 t4_fatal_err(adapter);
3900 }
3901
3902 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
3903 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
3904 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
3905 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
3906
3907 /*
3908 * CIM interrupt handler.
3909 */
3910 static void cim_intr_handler(struct adapter *adapter)
3911 {
3912 static const struct intr_info cim_intr_info[] = {
3913 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
3914 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
3915 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
3916 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
3917 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
3918 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
3919 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
3920 { 0 }
3921 };
3922 static const struct intr_info cim_upintr_info[] = {
3923 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
3924 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
3925 { ILLWRINT_F, "CIM illegal write", -1, 1 },
3926 { ILLRDINT_F, "CIM illegal read", -1, 1 },
3927 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
3928 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
3929 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
3930 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
3931 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
3932 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
3933 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
3934 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
3935 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
3936 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
3937 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
3938 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
3939 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
3940 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
3941 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
3942 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
3943 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
3944 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
3945 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
3946 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
3947 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
3948 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
3949 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
3950 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
3951 { 0 }
3952 };
3953
3954 int fat;
3955
3956 if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
3957 t4_report_fw_error(adapter);
3958
3959 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
3960 cim_intr_info) +
3961 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
3962 cim_upintr_info);
3963 if (fat)
3964 t4_fatal_err(adapter);
3965 }
3966
3967 /*
3968 * ULP RX interrupt handler.
3969 */
3970 static void ulprx_intr_handler(struct adapter *adapter)
3971 {
3972 static const struct intr_info ulprx_intr_info[] = {
3973 { 0x1800000, "ULPRX context error", -1, 1 },
3974 { 0x7fffff, "ULPRX parity error", -1, 1 },
3975 { 0 }
3976 };
3977
3978 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
3979 t4_fatal_err(adapter);
3980 }
3981
3982 /*
3983 * ULP TX interrupt handler.
3984 */
3985 static void ulptx_intr_handler(struct adapter *adapter)
3986 {
3987 static const struct intr_info ulptx_intr_info[] = {
3988 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
3989 0 },
3990 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
3991 0 },
3992 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
3993 0 },
3994 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
3995 0 },
3996 { 0xfffffff, "ULPTX parity error", -1, 1 },
3997 { 0 }
3998 };
3999
4000 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4001 t4_fatal_err(adapter);
4002 }
4003
4004 /*
4005 * PM TX interrupt handler.
4006 */
4007 static void pmtx_intr_handler(struct adapter *adapter)
4008 {
4009 static const struct intr_info pmtx_intr_info[] = {
4010 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4011 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4012 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4013 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4014 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4015 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4016 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4017 -1, 1 },
4018 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4019 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4020 { 0 }
4021 };
4022
4023 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4024 t4_fatal_err(adapter);
4025 }
4026
4027 /*
4028 * PM RX interrupt handler.
4029 */
4030 static void pmrx_intr_handler(struct adapter *adapter)
4031 {
4032 static const struct intr_info pmrx_intr_info[] = {
4033 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4034 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4035 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4036 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4037 -1, 1 },
4038 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4039 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4040 { 0 }
4041 };
4042
4043 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4044 t4_fatal_err(adapter);
4045 }
4046
4047 /*
4048 * CPL switch interrupt handler.
4049 */
4050 static void cplsw_intr_handler(struct adapter *adapter)
4051 {
4052 static const struct intr_info cplsw_intr_info[] = {
4053 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4054 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4055 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4056 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4057 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4058 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4059 { 0 }
4060 };
4061
4062 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4063 t4_fatal_err(adapter);
4064 }
4065
4066 /*
4067 * LE interrupt handler.
4068 */
4069 static void le_intr_handler(struct adapter *adap)
4070 {
4071 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4072 static const struct intr_info le_intr_info[] = {
4073 { LIPMISS_F, "LE LIP miss", -1, 0 },
4074 { LIP0_F, "LE 0 LIP error", -1, 0 },
4075 { PARITYERR_F, "LE parity error", -1, 1 },
4076 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4077 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4078 { 0 }
4079 };
4080
4081 static struct intr_info t6_le_intr_info[] = {
4082 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4083 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4084 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4085 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4086 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4087 { 0 }
4088 };
4089
4090 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4091 (chip <= CHELSIO_T5) ?
4092 le_intr_info : t6_le_intr_info))
4093 t4_fatal_err(adap);
4094 }
4095
4096 /*
4097 * MPS interrupt handler.
4098 */
4099 static void mps_intr_handler(struct adapter *adapter)
4100 {
4101 static const struct intr_info mps_rx_intr_info[] = {
4102 { 0xffffff, "MPS Rx parity error", -1, 1 },
4103 { 0 }
4104 };
4105 static const struct intr_info mps_tx_intr_info[] = {
4106 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4107 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4108 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4109 -1, 1 },
4110 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4111 -1, 1 },
4112 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4113 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4114 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4115 { 0 }
4116 };
4117 static const struct intr_info mps_trc_intr_info[] = {
4118 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4119 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4120 -1, 1 },
4121 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4122 { 0 }
4123 };
4124 static const struct intr_info mps_stat_sram_intr_info[] = {
4125 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4126 { 0 }
4127 };
4128 static const struct intr_info mps_stat_tx_intr_info[] = {
4129 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4130 { 0 }
4131 };
4132 static const struct intr_info mps_stat_rx_intr_info[] = {
4133 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4134 { 0 }
4135 };
4136 static const struct intr_info mps_cls_intr_info[] = {
4137 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4138 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4139 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4140 { 0 }
4141 };
4142
4143 int fat;
4144
4145 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4146 mps_rx_intr_info) +
4147 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4148 mps_tx_intr_info) +
4149 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4150 mps_trc_intr_info) +
4151 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4152 mps_stat_sram_intr_info) +
4153 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4154 mps_stat_tx_intr_info) +
4155 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4156 mps_stat_rx_intr_info) +
4157 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4158 mps_cls_intr_info);
4159
4160 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4161 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4162 if (fat)
4163 t4_fatal_err(adapter);
4164 }
4165
4166 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4167 ECC_UE_INT_CAUSE_F)
4168
4169 /*
4170 * EDC/MC interrupt handler.
4171 */
4172 static void mem_intr_handler(struct adapter *adapter, int idx)
4173 {
4174 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4175
4176 unsigned int addr, cnt_addr, v;
4177
4178 if (idx <= MEM_EDC1) {
4179 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4180 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4181 } else if (idx == MEM_MC) {
4182 if (is_t4(adapter->params.chip)) {
4183 addr = MC_INT_CAUSE_A;
4184 cnt_addr = MC_ECC_STATUS_A;
4185 } else {
4186 addr = MC_P_INT_CAUSE_A;
4187 cnt_addr = MC_P_ECC_STATUS_A;
4188 }
4189 } else {
4190 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4191 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4192 }
4193
4194 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4195 if (v & PERR_INT_CAUSE_F)
4196 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4197 name[idx]);
4198 if (v & ECC_CE_INT_CAUSE_F) {
4199 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4200
4201 t4_edc_err_read(adapter, idx);
4202
4203 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4204 if (printk_ratelimit())
4205 dev_warn(adapter->pdev_dev,
4206 "%u %s correctable ECC data error%s\n",
4207 cnt, name[idx], cnt > 1 ? "s" : "");
4208 }
4209 if (v & ECC_UE_INT_CAUSE_F)
4210 dev_alert(adapter->pdev_dev,
4211 "%s uncorrectable ECC data error\n", name[idx]);
4212
4213 t4_write_reg(adapter, addr, v);
4214 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4215 t4_fatal_err(adapter);
4216 }
4217
4218 /*
4219 * MA interrupt handler.
4220 */
4221 static void ma_intr_handler(struct adapter *adap)
4222 {
4223 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4224
4225 if (status & MEM_PERR_INT_CAUSE_F) {
4226 dev_alert(adap->pdev_dev,
4227 "MA parity error, parity status %#x\n",
4228 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4229 if (is_t5(adap->params.chip))
4230 dev_alert(adap->pdev_dev,
4231 "MA parity error, parity status %#x\n",
4232 t4_read_reg(adap,
4233 MA_PARITY_ERROR_STATUS2_A));
4234 }
4235 if (status & MEM_WRAP_INT_CAUSE_F) {
4236 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4237 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4238 "client %u to address %#x\n",
4239 MEM_WRAP_CLIENT_NUM_G(v),
4240 MEM_WRAP_ADDRESS_G(v) << 4);
4241 }
4242 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4243 t4_fatal_err(adap);
4244 }
4245
4246 /*
4247 * SMB interrupt handler.
4248 */
4249 static void smb_intr_handler(struct adapter *adap)
4250 {
4251 static const struct intr_info smb_intr_info[] = {
4252 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4253 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4254 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4255 { 0 }
4256 };
4257
4258 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4259 t4_fatal_err(adap);
4260 }
4261
4262 /*
4263 * NC-SI interrupt handler.
4264 */
4265 static void ncsi_intr_handler(struct adapter *adap)
4266 {
4267 static const struct intr_info ncsi_intr_info[] = {
4268 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4269 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4270 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4271 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4272 { 0 }
4273 };
4274
4275 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4276 t4_fatal_err(adap);
4277 }
4278
4279 /*
4280 * XGMAC interrupt handler.
4281 */
4282 static void xgmac_intr_handler(struct adapter *adap, int port)
4283 {
4284 u32 v, int_cause_reg;
4285
4286 if (is_t4(adap->params.chip))
4287 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4288 else
4289 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4290
4291 v = t4_read_reg(adap, int_cause_reg);
4292
4293 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4294 if (!v)
4295 return;
4296
4297 if (v & TXFIFO_PRTY_ERR_F)
4298 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4299 port);
4300 if (v & RXFIFO_PRTY_ERR_F)
4301 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4302 port);
4303 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4304 t4_fatal_err(adap);
4305 }
4306
4307 /*
4308 * PL interrupt handler.
4309 */
4310 static void pl_intr_handler(struct adapter *adap)
4311 {
4312 static const struct intr_info pl_intr_info[] = {
4313 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4314 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4315 { 0 }
4316 };
4317
4318 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4319 t4_fatal_err(adap);
4320 }
4321
4322 #define PF_INTR_MASK (PFSW_F)
4323 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4324 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4325 CPL_SWITCH_F | SGE_F | ULP_TX_F)
4326
4327 /**
4328 * t4_slow_intr_handler - control path interrupt handler
4329 * @adapter: the adapter
4330 *
4331 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
4332 * The designation 'slow' is because it involves register reads, while
4333 * data interrupts typically don't involve any MMIOs.
4334 */
4335 int t4_slow_intr_handler(struct adapter *adapter)
4336 {
4337 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4338
4339 if (!(cause & GLBL_INTR_MASK))
4340 return 0;
4341 if (cause & CIM_F)
4342 cim_intr_handler(adapter);
4343 if (cause & MPS_F)
4344 mps_intr_handler(adapter);
4345 if (cause & NCSI_F)
4346 ncsi_intr_handler(adapter);
4347 if (cause & PL_F)
4348 pl_intr_handler(adapter);
4349 if (cause & SMB_F)
4350 smb_intr_handler(adapter);
4351 if (cause & XGMAC0_F)
4352 xgmac_intr_handler(adapter, 0);
4353 if (cause & XGMAC1_F)
4354 xgmac_intr_handler(adapter, 1);
4355 if (cause & XGMAC_KR0_F)
4356 xgmac_intr_handler(adapter, 2);
4357 if (cause & XGMAC_KR1_F)
4358 xgmac_intr_handler(adapter, 3);
4359 if (cause & PCIE_F)
4360 pcie_intr_handler(adapter);
4361 if (cause & MC_F)
4362 mem_intr_handler(adapter, MEM_MC);
4363 if (is_t5(adapter->params.chip) && (cause & MC1_F))
4364 mem_intr_handler(adapter, MEM_MC1);
4365 if (cause & EDC0_F)
4366 mem_intr_handler(adapter, MEM_EDC0);
4367 if (cause & EDC1_F)
4368 mem_intr_handler(adapter, MEM_EDC1);
4369 if (cause & LE_F)
4370 le_intr_handler(adapter);
4371 if (cause & TP_F)
4372 tp_intr_handler(adapter);
4373 if (cause & MA_F)
4374 ma_intr_handler(adapter);
4375 if (cause & PM_TX_F)
4376 pmtx_intr_handler(adapter);
4377 if (cause & PM_RX_F)
4378 pmrx_intr_handler(adapter);
4379 if (cause & ULP_RX_F)
4380 ulprx_intr_handler(adapter);
4381 if (cause & CPL_SWITCH_F)
4382 cplsw_intr_handler(adapter);
4383 if (cause & SGE_F)
4384 sge_intr_handler(adapter);
4385 if (cause & ULP_TX_F)
4386 ulptx_intr_handler(adapter);
4387
4388 /* Clear the interrupts just processed for which we are the master. */
4389 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4390 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4391 return 1;
4392 }
4393
4394 /**
4395 * t4_intr_enable - enable interrupts
4396 * @adapter: the adapter whose interrupts should be enabled
4397 *
4398 * Enable PF-specific interrupts for the calling function and the top-level
4399 * interrupt concentrator for global interrupts. Interrupts are already
4400 * enabled at each module, here we just enable the roots of the interrupt
4401 * hierarchies.
4402 *
4403 * Note: this function should be called only when the driver manages
4404 * non PF-specific interrupts from the various HW modules. Only one PCI
4405 * function at a time should be doing this.
4406 */
4407 void t4_intr_enable(struct adapter *adapter)
4408 {
4409 u32 val = 0;
4410 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4411 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4412 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4413
4414 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4415 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4416 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4417 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4418 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4419 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4420 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4421 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4422 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4423 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4424 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4425 }
4426
4427 /**
4428 * t4_intr_disable - disable interrupts
4429 * @adapter: the adapter whose interrupts should be disabled
4430 *
4431 * Disable interrupts. We only disable the top-level interrupt
4432 * concentrators. The caller must be a PCI function managing global
4433 * interrupts.
4434 */
4435 void t4_intr_disable(struct adapter *adapter)
4436 {
4437 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4438 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4439 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4440
4441 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4442 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4443 }
4444
4445 /**
4446 * t4_config_rss_range - configure a portion of the RSS mapping table
4447 * @adapter: the adapter
4448 * @mbox: mbox to use for the FW command
4449 * @viid: virtual interface whose RSS subtable is to be written
4450 * @start: start entry in the table to write
4451 * @n: how many table entries to write
4452 * @rspq: values for the response queue lookup table
4453 * @nrspq: number of values in @rspq
4454 *
4455 * Programs the selected part of the VI's RSS mapping table with the
4456 * provided values. If @nrspq < @n the supplied values are used repeatedly
4457 * until the full table range is populated.
4458 *
4459 * The caller must ensure the values in @rspq are in the range allowed for
4460 * @viid.
4461 */
4462 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4463 int start, int n, const u16 *rspq, unsigned int nrspq)
4464 {
4465 int ret;
4466 const u16 *rsp = rspq;
4467 const u16 *rsp_end = rspq + nrspq;
4468 struct fw_rss_ind_tbl_cmd cmd;
4469
4470 memset(&cmd, 0, sizeof(cmd));
4471 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4472 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4473 FW_RSS_IND_TBL_CMD_VIID_V(viid));
4474 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4475
4476 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4477 while (n > 0) {
4478 int nq = min(n, 32);
4479 __be32 *qp = &cmd.iq0_to_iq2;
4480
4481 cmd.niqid = cpu_to_be16(nq);
4482 cmd.startidx = cpu_to_be16(start);
4483
4484 start += nq;
4485 n -= nq;
4486
4487 while (nq > 0) {
4488 unsigned int v;
4489
4490 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4491 if (++rsp >= rsp_end)
4492 rsp = rspq;
4493 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4494 if (++rsp >= rsp_end)
4495 rsp = rspq;
4496 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4497 if (++rsp >= rsp_end)
4498 rsp = rspq;
4499
4500 *qp++ = cpu_to_be32(v);
4501 nq -= 3;
4502 }
4503
4504 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4505 if (ret)
4506 return ret;
4507 }
4508 return 0;
4509 }
4510
4511 /**
4512 * t4_config_glbl_rss - configure the global RSS mode
4513 * @adapter: the adapter
4514 * @mbox: mbox to use for the FW command
4515 * @mode: global RSS mode
4516 * @flags: mode-specific flags
4517 *
4518 * Sets the global RSS mode.
4519 */
4520 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4521 unsigned int flags)
4522 {
4523 struct fw_rss_glb_config_cmd c;
4524
4525 memset(&c, 0, sizeof(c));
4526 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4527 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4528 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4529 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4530 c.u.manual.mode_pkd =
4531 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4532 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4533 c.u.basicvirtual.mode_pkd =
4534 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4535 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4536 } else
4537 return -EINVAL;
4538 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4539 }
4540
4541 /**
4542 * t4_config_vi_rss - configure per VI RSS settings
4543 * @adapter: the adapter
4544 * @mbox: mbox to use for the FW command
4545 * @viid: the VI id
4546 * @flags: RSS flags
4547 * @defq: id of the default RSS queue for the VI.
4548 *
4549 * Configures VI-specific RSS properties.
4550 */
4551 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4552 unsigned int flags, unsigned int defq)
4553 {
4554 struct fw_rss_vi_config_cmd c;
4555
4556 memset(&c, 0, sizeof(c));
4557 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
4558 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4559 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
4560 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4561 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4562 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
4563 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4564 }
4565
4566 /* Read an RSS table row */
4567 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4568 {
4569 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
4570 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
4571 5, 0, val);
4572 }
4573
4574 /**
4575 * t4_read_rss - read the contents of the RSS mapping table
4576 * @adapter: the adapter
4577 * @map: holds the contents of the RSS mapping table
4578 *
4579 * Reads the contents of the RSS hash->queue mapping table.
4580 */
4581 int t4_read_rss(struct adapter *adapter, u16 *map)
4582 {
4583 u32 val;
4584 int i, ret;
4585
4586 for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4587 ret = rd_rss_row(adapter, i, &val);
4588 if (ret)
4589 return ret;
4590 *map++ = LKPTBLQUEUE0_G(val);
4591 *map++ = LKPTBLQUEUE1_G(val);
4592 }
4593 return 0;
4594 }
4595
4596 static unsigned int t4_use_ldst(struct adapter *adap)
4597 {
4598 return (adap->flags & FW_OK) || !adap->use_bd;
4599 }
4600
4601 /**
4602 * t4_fw_tp_pio_rw - Access TP PIO through LDST
4603 * @adap: the adapter
4604 * @vals: where the indirect register values are stored/written
4605 * @nregs: how many indirect registers to read/write
4606 * @start_idx: index of first indirect register to read/write
4607 * @rw: Read (1) or Write (0)
4608 *
4609 * Access TP PIO registers through LDST
4610 */
4611 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4612 unsigned int start_index, unsigned int rw)
4613 {
4614 int ret, i;
4615 int cmd = FW_LDST_ADDRSPC_TP_PIO;
4616 struct fw_ldst_cmd c;
4617
4618 for (i = 0 ; i < nregs; i++) {
4619 memset(&c, 0, sizeof(c));
4620 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4621 FW_CMD_REQUEST_F |
4622 (rw ? FW_CMD_READ_F :
4623 FW_CMD_WRITE_F) |
4624 FW_LDST_CMD_ADDRSPACE_V(cmd));
4625 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4626
4627 c.u.addrval.addr = cpu_to_be32(start_index + i);
4628 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
4629 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4630 if (!ret && rw)
4631 vals[i] = be32_to_cpu(c.u.addrval.val);
4632 }
4633 }
4634
4635 /**
4636 * t4_read_rss_key - read the global RSS key
4637 * @adap: the adapter
4638 * @key: 10-entry array holding the 320-bit RSS key
4639 *
4640 * Reads the global 320-bit RSS key.
4641 */
4642 void t4_read_rss_key(struct adapter *adap, u32 *key)
4643 {
4644 if (t4_use_ldst(adap))
4645 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
4646 else
4647 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4648 TP_RSS_SECRET_KEY0_A);
4649 }
4650
4651 /**
4652 * t4_write_rss_key - program one of the RSS keys
4653 * @adap: the adapter
4654 * @key: 10-entry array holding the 320-bit RSS key
4655 * @idx: which RSS key to write
4656 *
4657 * Writes one of the RSS keys with the given 320-bit value. If @idx is
4658 * 0..15 the corresponding entry in the RSS key table is written,
4659 * otherwise the global RSS key is written.
4660 */
4661 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
4662 {
4663 u8 rss_key_addr_cnt = 16;
4664 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
4665
4666 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4667 * allows access to key addresses 16-63 by using KeyWrAddrX
4668 * as index[5:4](upper 2) into key table
4669 */
4670 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
4671 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
4672 rss_key_addr_cnt = 32;
4673
4674 if (t4_use_ldst(adap))
4675 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
4676 else
4677 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4678 TP_RSS_SECRET_KEY0_A);
4679
4680 if (idx >= 0 && idx < rss_key_addr_cnt) {
4681 if (rss_key_addr_cnt > 16)
4682 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4683 KEYWRADDRX_V(idx >> 4) |
4684 T6_VFWRADDR_V(idx) | KEYWREN_F);
4685 else
4686 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4687 KEYWRADDR_V(idx) | KEYWREN_F);
4688 }
4689 }
4690
4691 /**
4692 * t4_read_rss_pf_config - read PF RSS Configuration Table
4693 * @adapter: the adapter
4694 * @index: the entry in the PF RSS table to read
4695 * @valp: where to store the returned value
4696 *
4697 * Reads the PF RSS Configuration Table at the specified index and returns
4698 * the value found there.
4699 */
4700 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4701 u32 *valp)
4702 {
4703 if (t4_use_ldst(adapter))
4704 t4_fw_tp_pio_rw(adapter, valp, 1,
4705 TP_RSS_PF0_CONFIG_A + index, 1);
4706 else
4707 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4708 valp, 1, TP_RSS_PF0_CONFIG_A + index);
4709 }
4710
4711 /**
4712 * t4_read_rss_vf_config - read VF RSS Configuration Table
4713 * @adapter: the adapter
4714 * @index: the entry in the VF RSS table to read
4715 * @vfl: where to store the returned VFL
4716 * @vfh: where to store the returned VFH
4717 *
4718 * Reads the VF RSS Configuration Table at the specified index and returns
4719 * the (VFL, VFH) values found there.
4720 */
4721 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4722 u32 *vfl, u32 *vfh)
4723 {
4724 u32 vrt, mask, data;
4725
4726 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
4727 mask = VFWRADDR_V(VFWRADDR_M);
4728 data = VFWRADDR_V(index);
4729 } else {
4730 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
4731 data = T6_VFWRADDR_V(index);
4732 }
4733
4734 /* Request that the index'th VF Table values be read into VFL/VFH.
4735 */
4736 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
4737 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
4738 vrt |= data | VFRDEN_F;
4739 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
4740
4741 /* Grab the VFL/VFH values ...
4742 */
4743 if (t4_use_ldst(adapter)) {
4744 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
4745 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
4746 } else {
4747 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4748 vfl, 1, TP_RSS_VFL_CONFIG_A);
4749 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4750 vfh, 1, TP_RSS_VFH_CONFIG_A);
4751 }
4752 }
4753
4754 /**
4755 * t4_read_rss_pf_map - read PF RSS Map
4756 * @adapter: the adapter
4757 *
4758 * Reads the PF RSS Map register and returns its value.
4759 */
4760 u32 t4_read_rss_pf_map(struct adapter *adapter)
4761 {
4762 u32 pfmap;
4763
4764 if (t4_use_ldst(adapter))
4765 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
4766 else
4767 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4768 &pfmap, 1, TP_RSS_PF_MAP_A);
4769 return pfmap;
4770 }
4771
4772 /**
4773 * t4_read_rss_pf_mask - read PF RSS Mask
4774 * @adapter: the adapter
4775 *
4776 * Reads the PF RSS Mask register and returns its value.
4777 */
4778 u32 t4_read_rss_pf_mask(struct adapter *adapter)
4779 {
4780 u32 pfmask;
4781
4782 if (t4_use_ldst(adapter))
4783 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
4784 else
4785 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4786 &pfmask, 1, TP_RSS_PF_MSK_A);
4787 return pfmask;
4788 }
4789
4790 /**
4791 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
4792 * @adap: the adapter
4793 * @v4: holds the TCP/IP counter values
4794 * @v6: holds the TCP/IPv6 counter values
4795 *
4796 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
4797 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
4798 */
4799 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
4800 struct tp_tcp_stats *v6)
4801 {
4802 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
4803
4804 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
4805 #define STAT(x) val[STAT_IDX(x)]
4806 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
4807
4808 if (v4) {
4809 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4810 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
4811 v4->tcp_out_rsts = STAT(OUT_RST);
4812 v4->tcp_in_segs = STAT64(IN_SEG);
4813 v4->tcp_out_segs = STAT64(OUT_SEG);
4814 v4->tcp_retrans_segs = STAT64(RXT_SEG);
4815 }
4816 if (v6) {
4817 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4818 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
4819 v6->tcp_out_rsts = STAT(OUT_RST);
4820 v6->tcp_in_segs = STAT64(IN_SEG);
4821 v6->tcp_out_segs = STAT64(OUT_SEG);
4822 v6->tcp_retrans_segs = STAT64(RXT_SEG);
4823 }
4824 #undef STAT64
4825 #undef STAT
4826 #undef STAT_IDX
4827 }
4828
4829 /**
4830 * t4_tp_get_err_stats - read TP's error MIB counters
4831 * @adap: the adapter
4832 * @st: holds the counter values
4833 *
4834 * Returns the values of TP's error counters.
4835 */
4836 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
4837 {
4838 int nchan = adap->params.arch.nchan;
4839
4840 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4841 st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
4842 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4843 st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
4844 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4845 st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
4846 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4847 st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
4848 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4849 st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
4850 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4851 st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
4852 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4853 st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
4854 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4855 st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
4856
4857 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4858 &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
4859 }
4860
4861 /**
4862 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
4863 * @adap: the adapter
4864 * @st: holds the counter values
4865 *
4866 * Returns the values of TP's CPL counters.
4867 */
4868 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
4869 {
4870 int nchan = adap->params.arch.nchan;
4871
4872 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
4873 nchan, TP_MIB_CPL_IN_REQ_0_A);
4874 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
4875 nchan, TP_MIB_CPL_OUT_RSP_0_A);
4876
4877 }
4878
4879 /**
4880 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
4881 * @adap: the adapter
4882 * @st: holds the counter values
4883 *
4884 * Returns the values of TP's RDMA counters.
4885 */
4886 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
4887 {
4888 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
4889 2, TP_MIB_RQE_DFR_PKT_A);
4890 }
4891
4892 /**
4893 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
4894 * @adap: the adapter
4895 * @idx: the port index
4896 * @st: holds the counter values
4897 *
4898 * Returns the values of TP's FCoE counters for the selected port.
4899 */
4900 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
4901 struct tp_fcoe_stats *st)
4902 {
4903 u32 val[2];
4904
4905 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
4906 1, TP_MIB_FCOE_DDP_0_A + idx);
4907 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
4908 1, TP_MIB_FCOE_DROP_0_A + idx);
4909 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4910 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
4911 st->octets_ddp = ((u64)val[0] << 32) | val[1];
4912 }
4913
4914 /**
4915 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
4916 * @adap: the adapter
4917 * @st: holds the counter values
4918 *
4919 * Returns the values of TP's counters for non-TCP directly-placed packets.
4920 */
4921 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
4922 {
4923 u32 val[4];
4924
4925 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
4926 TP_MIB_USM_PKTS_A);
4927 st->frames = val[0];
4928 st->drops = val[1];
4929 st->octets = ((u64)val[2] << 32) | val[3];
4930 }
4931
4932 /**
4933 * t4_read_mtu_tbl - returns the values in the HW path MTU table
4934 * @adap: the adapter
4935 * @mtus: where to store the MTU values
4936 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
4937 *
4938 * Reads the HW path MTU table.
4939 */
4940 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
4941 {
4942 u32 v;
4943 int i;
4944
4945 for (i = 0; i < NMTUS; ++i) {
4946 t4_write_reg(adap, TP_MTU_TABLE_A,
4947 MTUINDEX_V(0xff) | MTUVALUE_V(i));
4948 v = t4_read_reg(adap, TP_MTU_TABLE_A);
4949 mtus[i] = MTUVALUE_G(v);
4950 if (mtu_log)
4951 mtu_log[i] = MTUWIDTH_G(v);
4952 }
4953 }
4954
4955 /**
4956 * t4_read_cong_tbl - reads the congestion control table
4957 * @adap: the adapter
4958 * @incr: where to store the alpha values
4959 *
4960 * Reads the additive increments programmed into the HW congestion
4961 * control table.
4962 */
4963 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
4964 {
4965 unsigned int mtu, w;
4966
4967 for (mtu = 0; mtu < NMTUS; ++mtu)
4968 for (w = 0; w < NCCTRL_WIN; ++w) {
4969 t4_write_reg(adap, TP_CCTRL_TABLE_A,
4970 ROWINDEX_V(0xffff) | (mtu << 5) | w);
4971 incr[mtu][w] = (u16)t4_read_reg(adap,
4972 TP_CCTRL_TABLE_A) & 0x1fff;
4973 }
4974 }
4975
4976 /**
4977 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
4978 * @adap: the adapter
4979 * @addr: the indirect TP register address
4980 * @mask: specifies the field within the register to modify
4981 * @val: new value for the field
4982 *
4983 * Sets a field of an indirect TP register to the given value.
4984 */
4985 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
4986 unsigned int mask, unsigned int val)
4987 {
4988 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
4989 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
4990 t4_write_reg(adap, TP_PIO_DATA_A, val);
4991 }
4992
4993 /**
4994 * init_cong_ctrl - initialize congestion control parameters
4995 * @a: the alpha values for congestion control
4996 * @b: the beta values for congestion control
4997 *
4998 * Initialize the congestion control parameters.
4999 */
5000 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5001 {
5002 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5003 a[9] = 2;
5004 a[10] = 3;
5005 a[11] = 4;
5006 a[12] = 5;
5007 a[13] = 6;
5008 a[14] = 7;
5009 a[15] = 8;
5010 a[16] = 9;
5011 a[17] = 10;
5012 a[18] = 14;
5013 a[19] = 17;
5014 a[20] = 21;
5015 a[21] = 25;
5016 a[22] = 30;
5017 a[23] = 35;
5018 a[24] = 45;
5019 a[25] = 60;
5020 a[26] = 80;
5021 a[27] = 100;
5022 a[28] = 200;
5023 a[29] = 300;
5024 a[30] = 400;
5025 a[31] = 500;
5026
5027 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5028 b[9] = b[10] = 1;
5029 b[11] = b[12] = 2;
5030 b[13] = b[14] = b[15] = b[16] = 3;
5031 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5032 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5033 b[28] = b[29] = 6;
5034 b[30] = b[31] = 7;
5035 }
5036
5037 /* The minimum additive increment value for the congestion control table */
5038 #define CC_MIN_INCR 2U
5039
5040 /**
5041 * t4_load_mtus - write the MTU and congestion control HW tables
5042 * @adap: the adapter
5043 * @mtus: the values for the MTU table
5044 * @alpha: the values for the congestion control alpha parameter
5045 * @beta: the values for the congestion control beta parameter
5046 *
5047 * Write the HW MTU table with the supplied MTUs and the high-speed
5048 * congestion control table with the supplied alpha, beta, and MTUs.
5049 * We write the two tables together because the additive increments
5050 * depend on the MTUs.
5051 */
5052 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5053 const unsigned short *alpha, const unsigned short *beta)
5054 {
5055 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5056 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5057 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5058 28672, 40960, 57344, 81920, 114688, 163840, 229376
5059 };
5060
5061 unsigned int i, w;
5062
5063 for (i = 0; i < NMTUS; ++i) {
5064 unsigned int mtu = mtus[i];
5065 unsigned int log2 = fls(mtu);
5066
5067 if (!(mtu & ((1 << log2) >> 2))) /* round */
5068 log2--;
5069 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5070 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5071
5072 for (w = 0; w < NCCTRL_WIN; ++w) {
5073 unsigned int inc;
5074
5075 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5076 CC_MIN_INCR);
5077
5078 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5079 (w << 16) | (beta[w] << 13) | inc);
5080 }
5081 }
5082 }
5083
5084 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5085 * clocks. The formula is
5086 *
5087 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5088 *
5089 * which is equivalent to
5090 *
5091 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5092 */
5093 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5094 {
5095 u64 v = bytes256 * adap->params.vpd.cclk;
5096
5097 return v * 62 + v / 2;
5098 }
5099
5100 /**
5101 * t4_get_chan_txrate - get the current per channel Tx rates
5102 * @adap: the adapter
5103 * @nic_rate: rates for NIC traffic
5104 * @ofld_rate: rates for offloaded traffic
5105 *
5106 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5107 * for each channel.
5108 */
5109 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5110 {
5111 u32 v;
5112
5113 v = t4_read_reg(adap, TP_TX_TRATE_A);
5114 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5115 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5116 if (adap->params.arch.nchan == NCHAN) {
5117 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5118 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5119 }
5120
5121 v = t4_read_reg(adap, TP_TX_ORATE_A);
5122 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5123 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5124 if (adap->params.arch.nchan == NCHAN) {
5125 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5126 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5127 }
5128 }
5129
5130 /**
5131 * t4_set_trace_filter - configure one of the tracing filters
5132 * @adap: the adapter
5133 * @tp: the desired trace filter parameters
5134 * @idx: which filter to configure
5135 * @enable: whether to enable or disable the filter
5136 *
5137 * Configures one of the tracing filters available in HW. If @enable is
5138 * %0 @tp is not examined and may be %NULL. The user is responsible to
5139 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5140 */
5141 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5142 int idx, int enable)
5143 {
5144 int i, ofst = idx * 4;
5145 u32 data_reg, mask_reg, cfg;
5146 u32 multitrc = TRCMULTIFILTER_F;
5147
5148 if (!enable) {
5149 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5150 return 0;
5151 }
5152
5153 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5154 if (cfg & TRCMULTIFILTER_F) {
5155 /* If multiple tracers are enabled, then maximum
5156 * capture size is 2.5KB (FIFO size of a single channel)
5157 * minus 2 flits for CPL_TRACE_PKT header.
5158 */
5159 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5160 return -EINVAL;
5161 } else {
5162 /* If multiple tracers are disabled, to avoid deadlocks
5163 * maximum packet capture size of 9600 bytes is recommended.
5164 * Also in this mode, only trace0 can be enabled and running.
5165 */
5166 multitrc = 0;
5167 if (tp->snap_len > 9600 || idx)
5168 return -EINVAL;
5169 }
5170
5171 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5172 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5173 tp->min_len > TFMINPKTSIZE_M)
5174 return -EINVAL;
5175
5176 /* stop the tracer we'll be changing */
5177 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5178
5179 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5180 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5181 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5182
5183 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5184 t4_write_reg(adap, data_reg, tp->data[i]);
5185 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5186 }
5187 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5188 TFCAPTUREMAX_V(tp->snap_len) |
5189 TFMINPKTSIZE_V(tp->min_len));
5190 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5191 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5192 (is_t4(adap->params.chip) ?
5193 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5194 T5_TFPORT_V(tp->port) | T5_TFEN_F |
5195 T5_TFINVERTMATCH_V(tp->invert)));
5196
5197 return 0;
5198 }
5199
5200 /**
5201 * t4_get_trace_filter - query one of the tracing filters
5202 * @adap: the adapter
5203 * @tp: the current trace filter parameters
5204 * @idx: which trace filter to query
5205 * @enabled: non-zero if the filter is enabled
5206 *
5207 * Returns the current settings of one of the HW tracing filters.
5208 */
5209 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5210 int *enabled)
5211 {
5212 u32 ctla, ctlb;
5213 int i, ofst = idx * 4;
5214 u32 data_reg, mask_reg;
5215
5216 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5217 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5218
5219 if (is_t4(adap->params.chip)) {
5220 *enabled = !!(ctla & TFEN_F);
5221 tp->port = TFPORT_G(ctla);
5222 tp->invert = !!(ctla & TFINVERTMATCH_F);
5223 } else {
5224 *enabled = !!(ctla & T5_TFEN_F);
5225 tp->port = T5_TFPORT_G(ctla);
5226 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5227 }
5228 tp->snap_len = TFCAPTUREMAX_G(ctlb);
5229 tp->min_len = TFMINPKTSIZE_G(ctlb);
5230 tp->skip_ofst = TFOFFSET_G(ctla);
5231 tp->skip_len = TFLENGTH_G(ctla);
5232
5233 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5234 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5235 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5236
5237 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5238 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5239 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5240 }
5241 }
5242
5243 /**
5244 * t4_pmtx_get_stats - returns the HW stats from PMTX
5245 * @adap: the adapter
5246 * @cnt: where to store the count statistics
5247 * @cycles: where to store the cycle statistics
5248 *
5249 * Returns performance statistics from PMTX.
5250 */
5251 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5252 {
5253 int i;
5254 u32 data[2];
5255
5256 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5257 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5258 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5259 if (is_t4(adap->params.chip)) {
5260 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5261 } else {
5262 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5263 PM_TX_DBG_DATA_A, data, 2,
5264 PM_TX_DBG_STAT_MSB_A);
5265 cycles[i] = (((u64)data[0] << 32) | data[1]);
5266 }
5267 }
5268 }
5269
5270 /**
5271 * t4_pmrx_get_stats - returns the HW stats from PMRX
5272 * @adap: the adapter
5273 * @cnt: where to store the count statistics
5274 * @cycles: where to store the cycle statistics
5275 *
5276 * Returns performance statistics from PMRX.
5277 */
5278 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5279 {
5280 int i;
5281 u32 data[2];
5282
5283 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5284 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5285 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5286 if (is_t4(adap->params.chip)) {
5287 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5288 } else {
5289 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5290 PM_RX_DBG_DATA_A, data, 2,
5291 PM_RX_DBG_STAT_MSB_A);
5292 cycles[i] = (((u64)data[0] << 32) | data[1]);
5293 }
5294 }
5295 }
5296
5297 /**
5298 * t4_get_mps_bg_map - return the buffer groups associated with a port
5299 * @adap: the adapter
5300 * @idx: the port index
5301 *
5302 * Returns a bitmap indicating which MPS buffer groups are associated
5303 * with the given port. Bit i is set if buffer group i is used by the
5304 * port.
5305 */
5306 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5307 {
5308 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5309
5310 if (n == 0)
5311 return idx == 0 ? 0xf : 0;
5312 /* In T6 (which is a 2 port card),
5313 * port 0 is mapped to channel 0 and port 1 is mapped to channel 1.
5314 * For 2 port T4/T5 adapter,
5315 * port 0 is mapped to channel 0 and 1,
5316 * port 1 is mapped to channel 2 and 3.
5317 */
5318 if ((n == 1) &&
5319 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
5320 return idx < 2 ? (3 << (2 * idx)) : 0;
5321 return 1 << idx;
5322 }
5323
5324 /**
5325 * t4_get_port_type_description - return Port Type string description
5326 * @port_type: firmware Port Type enumeration
5327 */
5328 const char *t4_get_port_type_description(enum fw_port_type port_type)
5329 {
5330 static const char *const port_type_description[] = {
5331 "R XFI",
5332 "R XAUI",
5333 "T SGMII",
5334 "T XFI",
5335 "T XAUI",
5336 "KX4",
5337 "CX4",
5338 "KX",
5339 "KR",
5340 "R SFP+",
5341 "KR/KX",
5342 "KR/KX/KX4",
5343 "R QSFP_10G",
5344 "R QSA",
5345 "R QSFP",
5346 "R BP40_BA",
5347 };
5348
5349 if (port_type < ARRAY_SIZE(port_type_description))
5350 return port_type_description[port_type];
5351 return "UNKNOWN";
5352 }
5353
5354 /**
5355 * t4_get_port_stats_offset - collect port stats relative to a previous
5356 * snapshot
5357 * @adap: The adapter
5358 * @idx: The port
5359 * @stats: Current stats to fill
5360 * @offset: Previous stats snapshot
5361 */
5362 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5363 struct port_stats *stats,
5364 struct port_stats *offset)
5365 {
5366 u64 *s, *o;
5367 int i;
5368
5369 t4_get_port_stats(adap, idx, stats);
5370 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5371 i < (sizeof(struct port_stats) / sizeof(u64));
5372 i++, s++, o++)
5373 *s -= *o;
5374 }
5375
5376 /**
5377 * t4_get_port_stats - collect port statistics
5378 * @adap: the adapter
5379 * @idx: the port index
5380 * @p: the stats structure to fill
5381 *
5382 * Collect statistics related to the given port from HW.
5383 */
5384 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5385 {
5386 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5387
5388 #define GET_STAT(name) \
5389 t4_read_reg64(adap, \
5390 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5391 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5392 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5393
5394 p->tx_octets = GET_STAT(TX_PORT_BYTES);
5395 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
5396 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
5397 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
5398 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
5399 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
5400 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
5401 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
5402 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
5403 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
5404 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
5405 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5406 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
5407 p->tx_drop = GET_STAT(TX_PORT_DROP);
5408 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
5409 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
5410 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
5411 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
5412 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
5413 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
5414 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
5415 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
5416 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
5417
5418 p->rx_octets = GET_STAT(RX_PORT_BYTES);
5419 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
5420 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
5421 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
5422 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
5423 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
5424 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
5425 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
5426 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
5427 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
5428 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
5429 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
5430 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
5431 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
5432 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
5433 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
5434 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
5435 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
5436 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
5437 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
5438 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
5439 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
5440 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
5441 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
5442 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
5443 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
5444 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
5445
5446 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5447 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5448 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5449 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5450 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5451 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5452 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5453 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5454
5455 #undef GET_STAT
5456 #undef GET_STAT_COM
5457 }
5458
5459 /**
5460 * t4_get_lb_stats - collect loopback port statistics
5461 * @adap: the adapter
5462 * @idx: the loopback port index
5463 * @p: the stats structure to fill
5464 *
5465 * Return HW statistics for the given loopback port.
5466 */
5467 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5468 {
5469 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5470
5471 #define GET_STAT(name) \
5472 t4_read_reg64(adap, \
5473 (is_t4(adap->params.chip) ? \
5474 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
5475 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
5476 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5477
5478 p->octets = GET_STAT(BYTES);
5479 p->frames = GET_STAT(FRAMES);
5480 p->bcast_frames = GET_STAT(BCAST);
5481 p->mcast_frames = GET_STAT(MCAST);
5482 p->ucast_frames = GET_STAT(UCAST);
5483 p->error_frames = GET_STAT(ERROR);
5484
5485 p->frames_64 = GET_STAT(64B);
5486 p->frames_65_127 = GET_STAT(65B_127B);
5487 p->frames_128_255 = GET_STAT(128B_255B);
5488 p->frames_256_511 = GET_STAT(256B_511B);
5489 p->frames_512_1023 = GET_STAT(512B_1023B);
5490 p->frames_1024_1518 = GET_STAT(1024B_1518B);
5491 p->frames_1519_max = GET_STAT(1519B_MAX);
5492 p->drop = GET_STAT(DROP_FRAMES);
5493
5494 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5495 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5496 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5497 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5498 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5499 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5500 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5501 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5502
5503 #undef GET_STAT
5504 #undef GET_STAT_COM
5505 }
5506
5507 /* t4_mk_filtdelwr - create a delete filter WR
5508 * @ftid: the filter ID
5509 * @wr: the filter work request to populate
5510 * @qid: ingress queue to receive the delete notification
5511 *
5512 * Creates a filter work request to delete the supplied filter. If @qid is
5513 * negative the delete notification is suppressed.
5514 */
5515 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
5516 {
5517 memset(wr, 0, sizeof(*wr));
5518 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
5519 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
5520 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
5521 FW_FILTER_WR_NOREPLY_V(qid < 0));
5522 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
5523 if (qid >= 0)
5524 wr->rx_chan_rx_rpl_iq =
5525 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
5526 }
5527
5528 #define INIT_CMD(var, cmd, rd_wr) do { \
5529 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
5530 FW_CMD_REQUEST_F | \
5531 FW_CMD_##rd_wr##_F); \
5532 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
5533 } while (0)
5534
5535 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
5536 u32 addr, u32 val)
5537 {
5538 u32 ldst_addrspace;
5539 struct fw_ldst_cmd c;
5540
5541 memset(&c, 0, sizeof(c));
5542 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
5543 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5544 FW_CMD_REQUEST_F |
5545 FW_CMD_WRITE_F |
5546 ldst_addrspace);
5547 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5548 c.u.addrval.addr = cpu_to_be32(addr);
5549 c.u.addrval.val = cpu_to_be32(val);
5550
5551 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5552 }
5553
5554 /**
5555 * t4_mdio_rd - read a PHY register through MDIO
5556 * @adap: the adapter
5557 * @mbox: mailbox to use for the FW command
5558 * @phy_addr: the PHY address
5559 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5560 * @reg: the register to read
5561 * @valp: where to store the value
5562 *
5563 * Issues a FW command through the given mailbox to read a PHY register.
5564 */
5565 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5566 unsigned int mmd, unsigned int reg, u16 *valp)
5567 {
5568 int ret;
5569 u32 ldst_addrspace;
5570 struct fw_ldst_cmd c;
5571
5572 memset(&c, 0, sizeof(c));
5573 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5574 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5575 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5576 ldst_addrspace);
5577 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5578 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5579 FW_LDST_CMD_MMD_V(mmd));
5580 c.u.mdio.raddr = cpu_to_be16(reg);
5581
5582 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5583 if (ret == 0)
5584 *valp = be16_to_cpu(c.u.mdio.rval);
5585 return ret;
5586 }
5587
5588 /**
5589 * t4_mdio_wr - write a PHY register through MDIO
5590 * @adap: the adapter
5591 * @mbox: mailbox to use for the FW command
5592 * @phy_addr: the PHY address
5593 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5594 * @reg: the register to write
5595 * @valp: value to write
5596 *
5597 * Issues a FW command through the given mailbox to write a PHY register.
5598 */
5599 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5600 unsigned int mmd, unsigned int reg, u16 val)
5601 {
5602 u32 ldst_addrspace;
5603 struct fw_ldst_cmd c;
5604
5605 memset(&c, 0, sizeof(c));
5606 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5607 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5608 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5609 ldst_addrspace);
5610 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5611 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5612 FW_LDST_CMD_MMD_V(mmd));
5613 c.u.mdio.raddr = cpu_to_be16(reg);
5614 c.u.mdio.rval = cpu_to_be16(val);
5615
5616 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5617 }
5618
5619 /**
5620 * t4_sge_decode_idma_state - decode the idma state
5621 * @adap: the adapter
5622 * @state: the state idma is stuck in
5623 */
5624 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
5625 {
5626 static const char * const t4_decode[] = {
5627 "IDMA_IDLE",
5628 "IDMA_PUSH_MORE_CPL_FIFO",
5629 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5630 "Not used",
5631 "IDMA_PHYSADDR_SEND_PCIEHDR",
5632 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5633 "IDMA_PHYSADDR_SEND_PAYLOAD",
5634 "IDMA_SEND_FIFO_TO_IMSG",
5635 "IDMA_FL_REQ_DATA_FL_PREP",
5636 "IDMA_FL_REQ_DATA_FL",
5637 "IDMA_FL_DROP",
5638 "IDMA_FL_H_REQ_HEADER_FL",
5639 "IDMA_FL_H_SEND_PCIEHDR",
5640 "IDMA_FL_H_PUSH_CPL_FIFO",
5641 "IDMA_FL_H_SEND_CPL",
5642 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5643 "IDMA_FL_H_SEND_IP_HDR",
5644 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5645 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5646 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5647 "IDMA_FL_D_SEND_PCIEHDR",
5648 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5649 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5650 "IDMA_FL_SEND_PCIEHDR",
5651 "IDMA_FL_PUSH_CPL_FIFO",
5652 "IDMA_FL_SEND_CPL",
5653 "IDMA_FL_SEND_PAYLOAD_FIRST",
5654 "IDMA_FL_SEND_PAYLOAD",
5655 "IDMA_FL_REQ_NEXT_DATA_FL",
5656 "IDMA_FL_SEND_NEXT_PCIEHDR",
5657 "IDMA_FL_SEND_PADDING",
5658 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5659 "IDMA_FL_SEND_FIFO_TO_IMSG",
5660 "IDMA_FL_REQ_DATAFL_DONE",
5661 "IDMA_FL_REQ_HEADERFL_DONE",
5662 };
5663 static const char * const t5_decode[] = {
5664 "IDMA_IDLE",
5665 "IDMA_ALMOST_IDLE",
5666 "IDMA_PUSH_MORE_CPL_FIFO",
5667 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5668 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5669 "IDMA_PHYSADDR_SEND_PCIEHDR",
5670 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5671 "IDMA_PHYSADDR_SEND_PAYLOAD",
5672 "IDMA_SEND_FIFO_TO_IMSG",
5673 "IDMA_FL_REQ_DATA_FL",
5674 "IDMA_FL_DROP",
5675 "IDMA_FL_DROP_SEND_INC",
5676 "IDMA_FL_H_REQ_HEADER_FL",
5677 "IDMA_FL_H_SEND_PCIEHDR",
5678 "IDMA_FL_H_PUSH_CPL_FIFO",
5679 "IDMA_FL_H_SEND_CPL",
5680 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5681 "IDMA_FL_H_SEND_IP_HDR",
5682 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5683 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5684 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5685 "IDMA_FL_D_SEND_PCIEHDR",
5686 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5687 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5688 "IDMA_FL_SEND_PCIEHDR",
5689 "IDMA_FL_PUSH_CPL_FIFO",
5690 "IDMA_FL_SEND_CPL",
5691 "IDMA_FL_SEND_PAYLOAD_FIRST",
5692 "IDMA_FL_SEND_PAYLOAD",
5693 "IDMA_FL_REQ_NEXT_DATA_FL",
5694 "IDMA_FL_SEND_NEXT_PCIEHDR",
5695 "IDMA_FL_SEND_PADDING",
5696 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5697 };
5698 static const char * const t6_decode[] = {
5699 "IDMA_IDLE",
5700 "IDMA_PUSH_MORE_CPL_FIFO",
5701 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5702 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5703 "IDMA_PHYSADDR_SEND_PCIEHDR",
5704 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5705 "IDMA_PHYSADDR_SEND_PAYLOAD",
5706 "IDMA_FL_REQ_DATA_FL",
5707 "IDMA_FL_DROP",
5708 "IDMA_FL_DROP_SEND_INC",
5709 "IDMA_FL_H_REQ_HEADER_FL",
5710 "IDMA_FL_H_SEND_PCIEHDR",
5711 "IDMA_FL_H_PUSH_CPL_FIFO",
5712 "IDMA_FL_H_SEND_CPL",
5713 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5714 "IDMA_FL_H_SEND_IP_HDR",
5715 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5716 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5717 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5718 "IDMA_FL_D_SEND_PCIEHDR",
5719 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5720 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5721 "IDMA_FL_SEND_PCIEHDR",
5722 "IDMA_FL_PUSH_CPL_FIFO",
5723 "IDMA_FL_SEND_CPL",
5724 "IDMA_FL_SEND_PAYLOAD_FIRST",
5725 "IDMA_FL_SEND_PAYLOAD",
5726 "IDMA_FL_REQ_NEXT_DATA_FL",
5727 "IDMA_FL_SEND_NEXT_PCIEHDR",
5728 "IDMA_FL_SEND_PADDING",
5729 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5730 };
5731 static const u32 sge_regs[] = {
5732 SGE_DEBUG_DATA_LOW_INDEX_2_A,
5733 SGE_DEBUG_DATA_LOW_INDEX_3_A,
5734 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
5735 };
5736 const char **sge_idma_decode;
5737 int sge_idma_decode_nstates;
5738 int i;
5739 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5740
5741 /* Select the right set of decode strings to dump depending on the
5742 * adapter chip type.
5743 */
5744 switch (chip_version) {
5745 case CHELSIO_T4:
5746 sge_idma_decode = (const char **)t4_decode;
5747 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5748 break;
5749
5750 case CHELSIO_T5:
5751 sge_idma_decode = (const char **)t5_decode;
5752 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5753 break;
5754
5755 case CHELSIO_T6:
5756 sge_idma_decode = (const char **)t6_decode;
5757 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
5758 break;
5759
5760 default:
5761 dev_err(adapter->pdev_dev,
5762 "Unsupported chip version %d\n", chip_version);
5763 return;
5764 }
5765
5766 if (is_t4(adapter->params.chip)) {
5767 sge_idma_decode = (const char **)t4_decode;
5768 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5769 } else {
5770 sge_idma_decode = (const char **)t5_decode;
5771 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5772 }
5773
5774 if (state < sge_idma_decode_nstates)
5775 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
5776 else
5777 CH_WARN(adapter, "idma state %d unknown\n", state);
5778
5779 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
5780 CH_WARN(adapter, "SGE register %#x value %#x\n",
5781 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
5782 }
5783
5784 /**
5785 * t4_sge_ctxt_flush - flush the SGE context cache
5786 * @adap: the adapter
5787 * @mbox: mailbox to use for the FW command
5788 *
5789 * Issues a FW command through the given mailbox to flush the
5790 * SGE context cache.
5791 */
5792 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
5793 {
5794 int ret;
5795 u32 ldst_addrspace;
5796 struct fw_ldst_cmd c;
5797
5798 memset(&c, 0, sizeof(c));
5799 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
5800 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5801 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5802 ldst_addrspace);
5803 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5804 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
5805
5806 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5807 return ret;
5808 }
5809
5810 /**
5811 * t4_fw_hello - establish communication with FW
5812 * @adap: the adapter
5813 * @mbox: mailbox to use for the FW command
5814 * @evt_mbox: mailbox to receive async FW events
5815 * @master: specifies the caller's willingness to be the device master
5816 * @state: returns the current device state (if non-NULL)
5817 *
5818 * Issues a command to establish communication with FW. Returns either
5819 * an error (negative integer) or the mailbox of the Master PF.
5820 */
5821 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
5822 enum dev_master master, enum dev_state *state)
5823 {
5824 int ret;
5825 struct fw_hello_cmd c;
5826 u32 v;
5827 unsigned int master_mbox;
5828 int retries = FW_CMD_HELLO_RETRIES;
5829
5830 retry:
5831 memset(&c, 0, sizeof(c));
5832 INIT_CMD(c, HELLO, WRITE);
5833 c.err_to_clearinit = cpu_to_be32(
5834 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
5835 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
5836 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
5837 mbox : FW_HELLO_CMD_MBMASTER_M) |
5838 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
5839 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
5840 FW_HELLO_CMD_CLEARINIT_F);
5841
5842 /*
5843 * Issue the HELLO command to the firmware. If it's not successful
5844 * but indicates that we got a "busy" or "timeout" condition, retry
5845 * the HELLO until we exhaust our retry limit. If we do exceed our
5846 * retry limit, check to see if the firmware left us any error
5847 * information and report that if so.
5848 */
5849 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5850 if (ret < 0) {
5851 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
5852 goto retry;
5853 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
5854 t4_report_fw_error(adap);
5855 return ret;
5856 }
5857
5858 v = be32_to_cpu(c.err_to_clearinit);
5859 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
5860 if (state) {
5861 if (v & FW_HELLO_CMD_ERR_F)
5862 *state = DEV_STATE_ERR;
5863 else if (v & FW_HELLO_CMD_INIT_F)
5864 *state = DEV_STATE_INIT;
5865 else
5866 *state = DEV_STATE_UNINIT;
5867 }
5868
5869 /*
5870 * If we're not the Master PF then we need to wait around for the
5871 * Master PF Driver to finish setting up the adapter.
5872 *
5873 * Note that we also do this wait if we're a non-Master-capable PF and
5874 * there is no current Master PF; a Master PF may show up momentarily
5875 * and we wouldn't want to fail pointlessly. (This can happen when an
5876 * OS loads lots of different drivers rapidly at the same time). In
5877 * this case, the Master PF returned by the firmware will be
5878 * PCIE_FW_MASTER_M so the test below will work ...
5879 */
5880 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
5881 master_mbox != mbox) {
5882 int waiting = FW_CMD_HELLO_TIMEOUT;
5883
5884 /*
5885 * Wait for the firmware to either indicate an error or
5886 * initialized state. If we see either of these we bail out
5887 * and report the issue to the caller. If we exhaust the
5888 * "hello timeout" and we haven't exhausted our retries, try
5889 * again. Otherwise bail with a timeout error.
5890 */
5891 for (;;) {
5892 u32 pcie_fw;
5893
5894 msleep(50);
5895 waiting -= 50;
5896
5897 /*
5898 * If neither Error nor Initialialized are indicated
5899 * by the firmware keep waiting till we exaust our
5900 * timeout ... and then retry if we haven't exhausted
5901 * our retries ...
5902 */
5903 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
5904 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
5905 if (waiting <= 0) {
5906 if (retries-- > 0)
5907 goto retry;
5908
5909 return -ETIMEDOUT;
5910 }
5911 continue;
5912 }
5913
5914 /*
5915 * We either have an Error or Initialized condition
5916 * report errors preferentially.
5917 */
5918 if (state) {
5919 if (pcie_fw & PCIE_FW_ERR_F)
5920 *state = DEV_STATE_ERR;
5921 else if (pcie_fw & PCIE_FW_INIT_F)
5922 *state = DEV_STATE_INIT;
5923 }
5924
5925 /*
5926 * If we arrived before a Master PF was selected and
5927 * there's not a valid Master PF, grab its identity
5928 * for our caller.
5929 */
5930 if (master_mbox == PCIE_FW_MASTER_M &&
5931 (pcie_fw & PCIE_FW_MASTER_VLD_F))
5932 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
5933 break;
5934 }
5935 }
5936
5937 return master_mbox;
5938 }
5939
5940 /**
5941 * t4_fw_bye - end communication with FW
5942 * @adap: the adapter
5943 * @mbox: mailbox to use for the FW command
5944 *
5945 * Issues a command to terminate communication with FW.
5946 */
5947 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
5948 {
5949 struct fw_bye_cmd c;
5950
5951 memset(&c, 0, sizeof(c));
5952 INIT_CMD(c, BYE, WRITE);
5953 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5954 }
5955
5956 /**
5957 * t4_init_cmd - ask FW to initialize the device
5958 * @adap: the adapter
5959 * @mbox: mailbox to use for the FW command
5960 *
5961 * Issues a command to FW to partially initialize the device. This
5962 * performs initialization that generally doesn't depend on user input.
5963 */
5964 int t4_early_init(struct adapter *adap, unsigned int mbox)
5965 {
5966 struct fw_initialize_cmd c;
5967
5968 memset(&c, 0, sizeof(c));
5969 INIT_CMD(c, INITIALIZE, WRITE);
5970 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5971 }
5972
5973 /**
5974 * t4_fw_reset - issue a reset to FW
5975 * @adap: the adapter
5976 * @mbox: mailbox to use for the FW command
5977 * @reset: specifies the type of reset to perform
5978 *
5979 * Issues a reset command of the specified type to FW.
5980 */
5981 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
5982 {
5983 struct fw_reset_cmd c;
5984
5985 memset(&c, 0, sizeof(c));
5986 INIT_CMD(c, RESET, WRITE);
5987 c.val = cpu_to_be32(reset);
5988 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5989 }
5990
5991 /**
5992 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
5993 * @adap: the adapter
5994 * @mbox: mailbox to use for the FW RESET command (if desired)
5995 * @force: force uP into RESET even if FW RESET command fails
5996 *
5997 * Issues a RESET command to firmware (if desired) with a HALT indication
5998 * and then puts the microprocessor into RESET state. The RESET command
5999 * will only be issued if a legitimate mailbox is provided (mbox <=
6000 * PCIE_FW_MASTER_M).
6001 *
6002 * This is generally used in order for the host to safely manipulate the
6003 * adapter without fear of conflicting with whatever the firmware might
6004 * be doing. The only way out of this state is to RESTART the firmware
6005 * ...
6006 */
6007 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6008 {
6009 int ret = 0;
6010
6011 /*
6012 * If a legitimate mailbox is provided, issue a RESET command
6013 * with a HALT indication.
6014 */
6015 if (mbox <= PCIE_FW_MASTER_M) {
6016 struct fw_reset_cmd c;
6017
6018 memset(&c, 0, sizeof(c));
6019 INIT_CMD(c, RESET, WRITE);
6020 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6021 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6022 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6023 }
6024
6025 /*
6026 * Normally we won't complete the operation if the firmware RESET
6027 * command fails but if our caller insists we'll go ahead and put the
6028 * uP into RESET. This can be useful if the firmware is hung or even
6029 * missing ... We'll have to take the risk of putting the uP into
6030 * RESET without the cooperation of firmware in that case.
6031 *
6032 * We also force the firmware's HALT flag to be on in case we bypassed
6033 * the firmware RESET command above or we're dealing with old firmware
6034 * which doesn't have the HALT capability. This will serve as a flag
6035 * for the incoming firmware to know that it's coming out of a HALT
6036 * rather than a RESET ... if it's new enough to understand that ...
6037 */
6038 if (ret == 0 || force) {
6039 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6040 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6041 PCIE_FW_HALT_F);
6042 }
6043
6044 /*
6045 * And we always return the result of the firmware RESET command
6046 * even when we force the uP into RESET ...
6047 */
6048 return ret;
6049 }
6050
6051 /**
6052 * t4_fw_restart - restart the firmware by taking the uP out of RESET
6053 * @adap: the adapter
6054 * @reset: if we want to do a RESET to restart things
6055 *
6056 * Restart firmware previously halted by t4_fw_halt(). On successful
6057 * return the previous PF Master remains as the new PF Master and there
6058 * is no need to issue a new HELLO command, etc.
6059 *
6060 * We do this in two ways:
6061 *
6062 * 1. If we're dealing with newer firmware we'll simply want to take
6063 * the chip's microprocessor out of RESET. This will cause the
6064 * firmware to start up from its start vector. And then we'll loop
6065 * until the firmware indicates it's started again (PCIE_FW.HALT
6066 * reset to 0) or we timeout.
6067 *
6068 * 2. If we're dealing with older firmware then we'll need to RESET
6069 * the chip since older firmware won't recognize the PCIE_FW.HALT
6070 * flag and automatically RESET itself on startup.
6071 */
6072 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6073 {
6074 if (reset) {
6075 /*
6076 * Since we're directing the RESET instead of the firmware
6077 * doing it automatically, we need to clear the PCIE_FW.HALT
6078 * bit.
6079 */
6080 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6081
6082 /*
6083 * If we've been given a valid mailbox, first try to get the
6084 * firmware to do the RESET. If that works, great and we can
6085 * return success. Otherwise, if we haven't been given a
6086 * valid mailbox or the RESET command failed, fall back to
6087 * hitting the chip with a hammer.
6088 */
6089 if (mbox <= PCIE_FW_MASTER_M) {
6090 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6091 msleep(100);
6092 if (t4_fw_reset(adap, mbox,
6093 PIORST_F | PIORSTMODE_F) == 0)
6094 return 0;
6095 }
6096
6097 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6098 msleep(2000);
6099 } else {
6100 int ms;
6101
6102 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6103 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6104 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6105 return 0;
6106 msleep(100);
6107 ms += 100;
6108 }
6109 return -ETIMEDOUT;
6110 }
6111 return 0;
6112 }
6113
6114 /**
6115 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6116 * @adap: the adapter
6117 * @mbox: mailbox to use for the FW RESET command (if desired)
6118 * @fw_data: the firmware image to write
6119 * @size: image size
6120 * @force: force upgrade even if firmware doesn't cooperate
6121 *
6122 * Perform all of the steps necessary for upgrading an adapter's
6123 * firmware image. Normally this requires the cooperation of the
6124 * existing firmware in order to halt all existing activities
6125 * but if an invalid mailbox token is passed in we skip that step
6126 * (though we'll still put the adapter microprocessor into RESET in
6127 * that case).
6128 *
6129 * On successful return the new firmware will have been loaded and
6130 * the adapter will have been fully RESET losing all previous setup
6131 * state. On unsuccessful return the adapter may be completely hosed ...
6132 * positive errno indicates that the adapter is ~probably~ intact, a
6133 * negative errno indicates that things are looking bad ...
6134 */
6135 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6136 const u8 *fw_data, unsigned int size, int force)
6137 {
6138 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6139 int reset, ret;
6140
6141 if (!t4_fw_matches_chip(adap, fw_hdr))
6142 return -EINVAL;
6143
6144 ret = t4_fw_halt(adap, mbox, force);
6145 if (ret < 0 && !force)
6146 return ret;
6147
6148 ret = t4_load_fw(adap, fw_data, size);
6149 if (ret < 0)
6150 return ret;
6151
6152 /*
6153 * Older versions of the firmware don't understand the new
6154 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6155 * restart. So for newly loaded older firmware we'll have to do the
6156 * RESET for it so it starts up on a clean slate. We can tell if
6157 * the newly loaded firmware will handle this right by checking
6158 * its header flags to see if it advertises the capability.
6159 */
6160 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6161 return t4_fw_restart(adap, mbox, reset);
6162 }
6163
6164 /**
6165 * t4_fl_pkt_align - return the fl packet alignment
6166 * @adap: the adapter
6167 *
6168 * T4 has a single field to specify the packing and padding boundary.
6169 * T5 onwards has separate fields for this and hence the alignment for
6170 * next packet offset is maximum of these two.
6171 *
6172 */
6173 int t4_fl_pkt_align(struct adapter *adap)
6174 {
6175 u32 sge_control, sge_control2;
6176 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6177
6178 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6179
6180 /* T4 uses a single control field to specify both the PCIe Padding and
6181 * Packing Boundary. T5 introduced the ability to specify these
6182 * separately. The actual Ingress Packet Data alignment boundary
6183 * within Packed Buffer Mode is the maximum of these two
6184 * specifications. (Note that it makes no real practical sense to
6185 * have the Pading Boudary be larger than the Packing Boundary but you
6186 * could set the chip up that way and, in fact, legacy T4 code would
6187 * end doing this because it would initialize the Padding Boundary and
6188 * leave the Packing Boundary initialized to 0 (16 bytes).)
6189 * Padding Boundary values in T6 starts from 8B,
6190 * where as it is 32B for T4 and T5.
6191 */
6192 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6193 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6194 else
6195 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6196
6197 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6198
6199 fl_align = ingpadboundary;
6200 if (!is_t4(adap->params.chip)) {
6201 /* T5 has a weird interpretation of one of the PCIe Packing
6202 * Boundary values. No idea why ...
6203 */
6204 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6205 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6206 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6207 ingpackboundary = 16;
6208 else
6209 ingpackboundary = 1 << (ingpackboundary +
6210 INGPACKBOUNDARY_SHIFT_X);
6211
6212 fl_align = max(ingpadboundary, ingpackboundary);
6213 }
6214 return fl_align;
6215 }
6216
6217 /**
6218 * t4_fixup_host_params - fix up host-dependent parameters
6219 * @adap: the adapter
6220 * @page_size: the host's Base Page Size
6221 * @cache_line_size: the host's Cache Line Size
6222 *
6223 * Various registers in T4 contain values which are dependent on the
6224 * host's Base Page and Cache Line Sizes. This function will fix all of
6225 * those registers with the appropriate values as passed in ...
6226 */
6227 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6228 unsigned int cache_line_size)
6229 {
6230 unsigned int page_shift = fls(page_size) - 1;
6231 unsigned int sge_hps = page_shift - 10;
6232 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6233 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6234 unsigned int fl_align_log = fls(fl_align) - 1;
6235 unsigned int ingpad;
6236
6237 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6238 HOSTPAGESIZEPF0_V(sge_hps) |
6239 HOSTPAGESIZEPF1_V(sge_hps) |
6240 HOSTPAGESIZEPF2_V(sge_hps) |
6241 HOSTPAGESIZEPF3_V(sge_hps) |
6242 HOSTPAGESIZEPF4_V(sge_hps) |
6243 HOSTPAGESIZEPF5_V(sge_hps) |
6244 HOSTPAGESIZEPF6_V(sge_hps) |
6245 HOSTPAGESIZEPF7_V(sge_hps));
6246
6247 if (is_t4(adap->params.chip)) {
6248 t4_set_reg_field(adap, SGE_CONTROL_A,
6249 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6250 EGRSTATUSPAGESIZE_F,
6251 INGPADBOUNDARY_V(fl_align_log -
6252 INGPADBOUNDARY_SHIFT_X) |
6253 EGRSTATUSPAGESIZE_V(stat_len != 64));
6254 } else {
6255 /* T5 introduced the separation of the Free List Padding and
6256 * Packing Boundaries. Thus, we can select a smaller Padding
6257 * Boundary to avoid uselessly chewing up PCIe Link and Memory
6258 * Bandwidth, and use a Packing Boundary which is large enough
6259 * to avoid false sharing between CPUs, etc.
6260 *
6261 * For the PCI Link, the smaller the Padding Boundary the
6262 * better. For the Memory Controller, a smaller Padding
6263 * Boundary is better until we cross under the Memory Line
6264 * Size (the minimum unit of transfer to/from Memory). If we
6265 * have a Padding Boundary which is smaller than the Memory
6266 * Line Size, that'll involve a Read-Modify-Write cycle on the
6267 * Memory Controller which is never good. For T5 the smallest
6268 * Padding Boundary which we can select is 32 bytes which is
6269 * larger than any known Memory Controller Line Size so we'll
6270 * use that.
6271 *
6272 * T5 has a different interpretation of the "0" value for the
6273 * Packing Boundary. This corresponds to 16 bytes instead of
6274 * the expected 32 bytes. We never have a Packing Boundary
6275 * less than 32 bytes so we can't use that special value but
6276 * on the other hand, if we wanted 32 bytes, the best we can
6277 * really do is 64 bytes.
6278 */
6279 if (fl_align <= 32) {
6280 fl_align = 64;
6281 fl_align_log = 6;
6282 }
6283
6284 if (is_t5(adap->params.chip))
6285 ingpad = INGPCIEBOUNDARY_32B_X;
6286 else
6287 ingpad = T6_INGPADBOUNDARY_32B_X;
6288
6289 t4_set_reg_field(adap, SGE_CONTROL_A,
6290 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6291 EGRSTATUSPAGESIZE_F,
6292 INGPADBOUNDARY_V(ingpad) |
6293 EGRSTATUSPAGESIZE_V(stat_len != 64));
6294 t4_set_reg_field(adap, SGE_CONTROL2_A,
6295 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6296 INGPACKBOUNDARY_V(fl_align_log -
6297 INGPACKBOUNDARY_SHIFT_X));
6298 }
6299 /*
6300 * Adjust various SGE Free List Host Buffer Sizes.
6301 *
6302 * This is something of a crock since we're using fixed indices into
6303 * the array which are also known by the sge.c code and the T4
6304 * Firmware Configuration File. We need to come up with a much better
6305 * approach to managing this array. For now, the first four entries
6306 * are:
6307 *
6308 * 0: Host Page Size
6309 * 1: 64KB
6310 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6311 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6312 *
6313 * For the single-MTU buffers in unpacked mode we need to include
6314 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6315 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6316 * Padding boundary. All of these are accommodated in the Factory
6317 * Default Firmware Configuration File but we need to adjust it for
6318 * this host's cache line size.
6319 */
6320 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6321 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6322 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6323 & ~(fl_align-1));
6324 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6325 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6326 & ~(fl_align-1));
6327
6328 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6329
6330 return 0;
6331 }
6332
6333 /**
6334 * t4_fw_initialize - ask FW to initialize the device
6335 * @adap: the adapter
6336 * @mbox: mailbox to use for the FW command
6337 *
6338 * Issues a command to FW to partially initialize the device. This
6339 * performs initialization that generally doesn't depend on user input.
6340 */
6341 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6342 {
6343 struct fw_initialize_cmd c;
6344
6345 memset(&c, 0, sizeof(c));
6346 INIT_CMD(c, INITIALIZE, WRITE);
6347 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6348 }
6349
6350 /**
6351 * t4_query_params_rw - query FW or device parameters
6352 * @adap: the adapter
6353 * @mbox: mailbox to use for the FW command
6354 * @pf: the PF
6355 * @vf: the VF
6356 * @nparams: the number of parameters
6357 * @params: the parameter names
6358 * @val: the parameter values
6359 * @rw: Write and read flag
6360 *
6361 * Reads the value of FW or device parameters. Up to 7 parameters can be
6362 * queried at once.
6363 */
6364 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6365 unsigned int vf, unsigned int nparams, const u32 *params,
6366 u32 *val, int rw)
6367 {
6368 int i, ret;
6369 struct fw_params_cmd c;
6370 __be32 *p = &c.param[0].mnem;
6371
6372 if (nparams > 7)
6373 return -EINVAL;
6374
6375 memset(&c, 0, sizeof(c));
6376 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6377 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6378 FW_PARAMS_CMD_PFN_V(pf) |
6379 FW_PARAMS_CMD_VFN_V(vf));
6380 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6381
6382 for (i = 0; i < nparams; i++) {
6383 *p++ = cpu_to_be32(*params++);
6384 if (rw)
6385 *p = cpu_to_be32(*(val + i));
6386 p++;
6387 }
6388
6389 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6390 if (ret == 0)
6391 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6392 *val++ = be32_to_cpu(*p);
6393 return ret;
6394 }
6395
6396 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6397 unsigned int vf, unsigned int nparams, const u32 *params,
6398 u32 *val)
6399 {
6400 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6401 }
6402
6403 /**
6404 * t4_set_params_timeout - sets FW or device parameters
6405 * @adap: the adapter
6406 * @mbox: mailbox to use for the FW command
6407 * @pf: the PF
6408 * @vf: the VF
6409 * @nparams: the number of parameters
6410 * @params: the parameter names
6411 * @val: the parameter values
6412 * @timeout: the timeout time
6413 *
6414 * Sets the value of FW or device parameters. Up to 7 parameters can be
6415 * specified at once.
6416 */
6417 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6418 unsigned int pf, unsigned int vf,
6419 unsigned int nparams, const u32 *params,
6420 const u32 *val, int timeout)
6421 {
6422 struct fw_params_cmd c;
6423 __be32 *p = &c.param[0].mnem;
6424
6425 if (nparams > 7)
6426 return -EINVAL;
6427
6428 memset(&c, 0, sizeof(c));
6429 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6430 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6431 FW_PARAMS_CMD_PFN_V(pf) |
6432 FW_PARAMS_CMD_VFN_V(vf));
6433 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6434
6435 while (nparams--) {
6436 *p++ = cpu_to_be32(*params++);
6437 *p++ = cpu_to_be32(*val++);
6438 }
6439
6440 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6441 }
6442
6443 /**
6444 * t4_set_params - sets FW or device parameters
6445 * @adap: the adapter
6446 * @mbox: mailbox to use for the FW command
6447 * @pf: the PF
6448 * @vf: the VF
6449 * @nparams: the number of parameters
6450 * @params: the parameter names
6451 * @val: the parameter values
6452 *
6453 * Sets the value of FW or device parameters. Up to 7 parameters can be
6454 * specified at once.
6455 */
6456 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6457 unsigned int vf, unsigned int nparams, const u32 *params,
6458 const u32 *val)
6459 {
6460 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6461 FW_CMD_MAX_TIMEOUT);
6462 }
6463
6464 /**
6465 * t4_cfg_pfvf - configure PF/VF resource limits
6466 * @adap: the adapter
6467 * @mbox: mailbox to use for the FW command
6468 * @pf: the PF being configured
6469 * @vf: the VF being configured
6470 * @txq: the max number of egress queues
6471 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
6472 * @rxqi: the max number of interrupt-capable ingress queues
6473 * @rxq: the max number of interruptless ingress queues
6474 * @tc: the PCI traffic class
6475 * @vi: the max number of virtual interfaces
6476 * @cmask: the channel access rights mask for the PF/VF
6477 * @pmask: the port access rights mask for the PF/VF
6478 * @nexact: the maximum number of exact MPS filters
6479 * @rcaps: read capabilities
6480 * @wxcaps: write/execute capabilities
6481 *
6482 * Configures resource limits and capabilities for a physical or virtual
6483 * function.
6484 */
6485 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6486 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6487 unsigned int rxqi, unsigned int rxq, unsigned int tc,
6488 unsigned int vi, unsigned int cmask, unsigned int pmask,
6489 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6490 {
6491 struct fw_pfvf_cmd c;
6492
6493 memset(&c, 0, sizeof(c));
6494 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
6495 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
6496 FW_PFVF_CMD_VFN_V(vf));
6497 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6498 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
6499 FW_PFVF_CMD_NIQ_V(rxq));
6500 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
6501 FW_PFVF_CMD_PMASK_V(pmask) |
6502 FW_PFVF_CMD_NEQ_V(txq));
6503 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
6504 FW_PFVF_CMD_NVI_V(vi) |
6505 FW_PFVF_CMD_NEXACTF_V(nexact));
6506 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
6507 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
6508 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
6509 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6510 }
6511
6512 /**
6513 * t4_alloc_vi - allocate a virtual interface
6514 * @adap: the adapter
6515 * @mbox: mailbox to use for the FW command
6516 * @port: physical port associated with the VI
6517 * @pf: the PF owning the VI
6518 * @vf: the VF owning the VI
6519 * @nmac: number of MAC addresses needed (1 to 5)
6520 * @mac: the MAC addresses of the VI
6521 * @rss_size: size of RSS table slice associated with this VI
6522 *
6523 * Allocates a virtual interface for the given physical port. If @mac is
6524 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
6525 * @mac should be large enough to hold @nmac Ethernet addresses, they are
6526 * stored consecutively so the space needed is @nmac * 6 bytes.
6527 * Returns a negative error number or the non-negative VI id.
6528 */
6529 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6530 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6531 unsigned int *rss_size)
6532 {
6533 int ret;
6534 struct fw_vi_cmd c;
6535
6536 memset(&c, 0, sizeof(c));
6537 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
6538 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
6539 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
6540 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
6541 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
6542 c.nmac = nmac - 1;
6543
6544 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6545 if (ret)
6546 return ret;
6547
6548 if (mac) {
6549 memcpy(mac, c.mac, sizeof(c.mac));
6550 switch (nmac) {
6551 case 5:
6552 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6553 case 4:
6554 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6555 case 3:
6556 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6557 case 2:
6558 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
6559 }
6560 }
6561 if (rss_size)
6562 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
6563 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
6564 }
6565
6566 /**
6567 * t4_free_vi - free a virtual interface
6568 * @adap: the adapter
6569 * @mbox: mailbox to use for the FW command
6570 * @pf: the PF owning the VI
6571 * @vf: the VF owning the VI
6572 * @viid: virtual interface identifiler
6573 *
6574 * Free a previously allocated virtual interface.
6575 */
6576 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6577 unsigned int vf, unsigned int viid)
6578 {
6579 struct fw_vi_cmd c;
6580
6581 memset(&c, 0, sizeof(c));
6582 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
6583 FW_CMD_REQUEST_F |
6584 FW_CMD_EXEC_F |
6585 FW_VI_CMD_PFN_V(pf) |
6586 FW_VI_CMD_VFN_V(vf));
6587 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
6588 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
6589
6590 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6591 }
6592
6593 /**
6594 * t4_set_rxmode - set Rx properties of a virtual interface
6595 * @adap: the adapter
6596 * @mbox: mailbox to use for the FW command
6597 * @viid: the VI id
6598 * @mtu: the new MTU or -1
6599 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6600 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6601 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6602 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6603 * @sleep_ok: if true we may sleep while awaiting command completion
6604 *
6605 * Sets Rx properties of a virtual interface.
6606 */
6607 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
6608 int mtu, int promisc, int all_multi, int bcast, int vlanex,
6609 bool sleep_ok)
6610 {
6611 struct fw_vi_rxmode_cmd c;
6612
6613 /* convert to FW values */
6614 if (mtu < 0)
6615 mtu = FW_RXMODE_MTU_NO_CHG;
6616 if (promisc < 0)
6617 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
6618 if (all_multi < 0)
6619 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
6620 if (bcast < 0)
6621 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
6622 if (vlanex < 0)
6623 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
6624
6625 memset(&c, 0, sizeof(c));
6626 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
6627 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6628 FW_VI_RXMODE_CMD_VIID_V(viid));
6629 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6630 c.mtu_to_vlanexen =
6631 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
6632 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
6633 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
6634 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
6635 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
6636 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6637 }
6638
6639 /**
6640 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
6641 * @adap: the adapter
6642 * @mbox: mailbox to use for the FW command
6643 * @viid: the VI id
6644 * @free: if true any existing filters for this VI id are first removed
6645 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6646 * @addr: the MAC address(es)
6647 * @idx: where to store the index of each allocated filter
6648 * @hash: pointer to hash address filter bitmap
6649 * @sleep_ok: call is allowed to sleep
6650 *
6651 * Allocates an exact-match filter for each of the supplied addresses and
6652 * sets it to the corresponding address. If @idx is not %NULL it should
6653 * have at least @naddr entries, each of which will be set to the index of
6654 * the filter allocated for the corresponding MAC address. If a filter
6655 * could not be allocated for an address its index is set to 0xffff.
6656 * If @hash is not %NULL addresses that fail to allocate an exact filter
6657 * are hashed and update the hash filter bitmap pointed at by @hash.
6658 *
6659 * Returns a negative error number or the number of filters allocated.
6660 */
6661 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
6662 unsigned int viid, bool free, unsigned int naddr,
6663 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
6664 {
6665 int offset, ret = 0;
6666 struct fw_vi_mac_cmd c;
6667 unsigned int nfilters = 0;
6668 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
6669 unsigned int rem = naddr;
6670
6671 if (naddr > max_naddr)
6672 return -EINVAL;
6673
6674 for (offset = 0; offset < naddr ; /**/) {
6675 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
6676 rem : ARRAY_SIZE(c.u.exact));
6677 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6678 u.exact[fw_naddr]), 16);
6679 struct fw_vi_mac_exact *p;
6680 int i;
6681
6682 memset(&c, 0, sizeof(c));
6683 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6684 FW_CMD_REQUEST_F |
6685 FW_CMD_WRITE_F |
6686 FW_CMD_EXEC_V(free) |
6687 FW_VI_MAC_CMD_VIID_V(viid));
6688 c.freemacs_to_len16 =
6689 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
6690 FW_CMD_LEN16_V(len16));
6691
6692 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6693 p->valid_to_idx =
6694 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6695 FW_VI_MAC_CMD_IDX_V(
6696 FW_VI_MAC_ADD_MAC));
6697 memcpy(p->macaddr, addr[offset + i],
6698 sizeof(p->macaddr));
6699 }
6700
6701 /* It's okay if we run out of space in our MAC address arena.
6702 * Some of the addresses we submit may get stored so we need
6703 * to run through the reply to see what the results were ...
6704 */
6705 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6706 if (ret && ret != -FW_ENOMEM)
6707 break;
6708
6709 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6710 u16 index = FW_VI_MAC_CMD_IDX_G(
6711 be16_to_cpu(p->valid_to_idx));
6712
6713 if (idx)
6714 idx[offset + i] = (index >= max_naddr ?
6715 0xffff : index);
6716 if (index < max_naddr)
6717 nfilters++;
6718 else if (hash)
6719 *hash |= (1ULL <<
6720 hash_mac_addr(addr[offset + i]));
6721 }
6722
6723 free = false;
6724 offset += fw_naddr;
6725 rem -= fw_naddr;
6726 }
6727
6728 if (ret == 0 || ret == -FW_ENOMEM)
6729 ret = nfilters;
6730 return ret;
6731 }
6732
6733 /**
6734 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
6735 * @adap: the adapter
6736 * @mbox: mailbox to use for the FW command
6737 * @viid: the VI id
6738 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6739 * @addr: the MAC address(es)
6740 * @sleep_ok: call is allowed to sleep
6741 *
6742 * Frees the exact-match filter for each of the supplied addresses
6743 *
6744 * Returns a negative error number or the number of filters freed.
6745 */
6746 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
6747 unsigned int viid, unsigned int naddr,
6748 const u8 **addr, bool sleep_ok)
6749 {
6750 int offset, ret = 0;
6751 struct fw_vi_mac_cmd c;
6752 unsigned int nfilters = 0;
6753 unsigned int max_naddr = is_t4(adap->params.chip) ?
6754 NUM_MPS_CLS_SRAM_L_INSTANCES :
6755 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
6756 unsigned int rem = naddr;
6757
6758 if (naddr > max_naddr)
6759 return -EINVAL;
6760
6761 for (offset = 0; offset < (int)naddr ; /**/) {
6762 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
6763 ? rem
6764 : ARRAY_SIZE(c.u.exact));
6765 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6766 u.exact[fw_naddr]), 16);
6767 struct fw_vi_mac_exact *p;
6768 int i;
6769
6770 memset(&c, 0, sizeof(c));
6771 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6772 FW_CMD_REQUEST_F |
6773 FW_CMD_WRITE_F |
6774 FW_CMD_EXEC_V(0) |
6775 FW_VI_MAC_CMD_VIID_V(viid));
6776 c.freemacs_to_len16 =
6777 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
6778 FW_CMD_LEN16_V(len16));
6779
6780 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
6781 p->valid_to_idx = cpu_to_be16(
6782 FW_VI_MAC_CMD_VALID_F |
6783 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
6784 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
6785 }
6786
6787 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6788 if (ret)
6789 break;
6790
6791 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6792 u16 index = FW_VI_MAC_CMD_IDX_G(
6793 be16_to_cpu(p->valid_to_idx));
6794
6795 if (index < max_naddr)
6796 nfilters++;
6797 }
6798
6799 offset += fw_naddr;
6800 rem -= fw_naddr;
6801 }
6802
6803 if (ret == 0)
6804 ret = nfilters;
6805 return ret;
6806 }
6807
6808 /**
6809 * t4_change_mac - modifies the exact-match filter for a MAC address
6810 * @adap: the adapter
6811 * @mbox: mailbox to use for the FW command
6812 * @viid: the VI id
6813 * @idx: index of existing filter for old value of MAC address, or -1
6814 * @addr: the new MAC address value
6815 * @persist: whether a new MAC allocation should be persistent
6816 * @add_smt: if true also add the address to the HW SMT
6817 *
6818 * Modifies an exact-match filter and sets it to the new MAC address.
6819 * Note that in general it is not possible to modify the value of a given
6820 * filter so the generic way to modify an address filter is to free the one
6821 * being used by the old address value and allocate a new filter for the
6822 * new address value. @idx can be -1 if the address is a new addition.
6823 *
6824 * Returns a negative error number or the index of the filter with the new
6825 * MAC value.
6826 */
6827 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
6828 int idx, const u8 *addr, bool persist, bool add_smt)
6829 {
6830 int ret, mode;
6831 struct fw_vi_mac_cmd c;
6832 struct fw_vi_mac_exact *p = c.u.exact;
6833 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
6834
6835 if (idx < 0) /* new allocation */
6836 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
6837 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
6838
6839 memset(&c, 0, sizeof(c));
6840 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6841 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6842 FW_VI_MAC_CMD_VIID_V(viid));
6843 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
6844 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6845 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
6846 FW_VI_MAC_CMD_IDX_V(idx));
6847 memcpy(p->macaddr, addr, sizeof(p->macaddr));
6848
6849 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6850 if (ret == 0) {
6851 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
6852 if (ret >= max_mac_addr)
6853 ret = -ENOMEM;
6854 }
6855 return ret;
6856 }
6857
6858 /**
6859 * t4_set_addr_hash - program the MAC inexact-match hash filter
6860 * @adap: the adapter
6861 * @mbox: mailbox to use for the FW command
6862 * @viid: the VI id
6863 * @ucast: whether the hash filter should also match unicast addresses
6864 * @vec: the value to be written to the hash filter
6865 * @sleep_ok: call is allowed to sleep
6866 *
6867 * Sets the 64-bit inexact-match hash filter for a virtual interface.
6868 */
6869 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
6870 bool ucast, u64 vec, bool sleep_ok)
6871 {
6872 struct fw_vi_mac_cmd c;
6873
6874 memset(&c, 0, sizeof(c));
6875 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6876 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6877 FW_VI_ENABLE_CMD_VIID_V(viid));
6878 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
6879 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
6880 FW_CMD_LEN16_V(1));
6881 c.u.hash.hashvec = cpu_to_be64(vec);
6882 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6883 }
6884
6885 /**
6886 * t4_enable_vi_params - enable/disable a virtual interface
6887 * @adap: the adapter
6888 * @mbox: mailbox to use for the FW command
6889 * @viid: the VI id
6890 * @rx_en: 1=enable Rx, 0=disable Rx
6891 * @tx_en: 1=enable Tx, 0=disable Tx
6892 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
6893 *
6894 * Enables/disables a virtual interface. Note that setting DCB Enable
6895 * only makes sense when enabling a Virtual Interface ...
6896 */
6897 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
6898 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
6899 {
6900 struct fw_vi_enable_cmd c;
6901
6902 memset(&c, 0, sizeof(c));
6903 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6904 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6905 FW_VI_ENABLE_CMD_VIID_V(viid));
6906 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
6907 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
6908 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
6909 FW_LEN16(c));
6910 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
6911 }
6912
6913 /**
6914 * t4_enable_vi - enable/disable a virtual interface
6915 * @adap: the adapter
6916 * @mbox: mailbox to use for the FW command
6917 * @viid: the VI id
6918 * @rx_en: 1=enable Rx, 0=disable Rx
6919 * @tx_en: 1=enable Tx, 0=disable Tx
6920 *
6921 * Enables/disables a virtual interface.
6922 */
6923 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
6924 bool rx_en, bool tx_en)
6925 {
6926 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
6927 }
6928
6929 /**
6930 * t4_identify_port - identify a VI's port by blinking its LED
6931 * @adap: the adapter
6932 * @mbox: mailbox to use for the FW command
6933 * @viid: the VI id
6934 * @nblinks: how many times to blink LED at 2.5 Hz
6935 *
6936 * Identifies a VI's port by blinking its LED.
6937 */
6938 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
6939 unsigned int nblinks)
6940 {
6941 struct fw_vi_enable_cmd c;
6942
6943 memset(&c, 0, sizeof(c));
6944 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6945 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6946 FW_VI_ENABLE_CMD_VIID_V(viid));
6947 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
6948 c.blinkdur = cpu_to_be16(nblinks);
6949 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6950 }
6951
6952 /**
6953 * t4_iq_stop - stop an ingress queue and its FLs
6954 * @adap: the adapter
6955 * @mbox: mailbox to use for the FW command
6956 * @pf: the PF owning the queues
6957 * @vf: the VF owning the queues
6958 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
6959 * @iqid: ingress queue id
6960 * @fl0id: FL0 queue id or 0xffff if no attached FL0
6961 * @fl1id: FL1 queue id or 0xffff if no attached FL1
6962 *
6963 * Stops an ingress queue and its associated FLs, if any. This causes
6964 * any current or future data/messages destined for these queues to be
6965 * tossed.
6966 */
6967 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
6968 unsigned int vf, unsigned int iqtype, unsigned int iqid,
6969 unsigned int fl0id, unsigned int fl1id)
6970 {
6971 struct fw_iq_cmd c;
6972
6973 memset(&c, 0, sizeof(c));
6974 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
6975 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
6976 FW_IQ_CMD_VFN_V(vf));
6977 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
6978 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
6979 c.iqid = cpu_to_be16(iqid);
6980 c.fl0id = cpu_to_be16(fl0id);
6981 c.fl1id = cpu_to_be16(fl1id);
6982 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6983 }
6984
6985 /**
6986 * t4_iq_free - free an ingress queue and its FLs
6987 * @adap: the adapter
6988 * @mbox: mailbox to use for the FW command
6989 * @pf: the PF owning the queues
6990 * @vf: the VF owning the queues
6991 * @iqtype: the ingress queue type
6992 * @iqid: ingress queue id
6993 * @fl0id: FL0 queue id or 0xffff if no attached FL0
6994 * @fl1id: FL1 queue id or 0xffff if no attached FL1
6995 *
6996 * Frees an ingress queue and its associated FLs, if any.
6997 */
6998 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
6999 unsigned int vf, unsigned int iqtype, unsigned int iqid,
7000 unsigned int fl0id, unsigned int fl1id)
7001 {
7002 struct fw_iq_cmd c;
7003
7004 memset(&c, 0, sizeof(c));
7005 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7006 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7007 FW_IQ_CMD_VFN_V(vf));
7008 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7009 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7010 c.iqid = cpu_to_be16(iqid);
7011 c.fl0id = cpu_to_be16(fl0id);
7012 c.fl1id = cpu_to_be16(fl1id);
7013 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7014 }
7015
7016 /**
7017 * t4_eth_eq_free - free an Ethernet egress queue
7018 * @adap: the adapter
7019 * @mbox: mailbox to use for the FW command
7020 * @pf: the PF owning the queue
7021 * @vf: the VF owning the queue
7022 * @eqid: egress queue id
7023 *
7024 * Frees an Ethernet egress queue.
7025 */
7026 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7027 unsigned int vf, unsigned int eqid)
7028 {
7029 struct fw_eq_eth_cmd c;
7030
7031 memset(&c, 0, sizeof(c));
7032 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7033 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7034 FW_EQ_ETH_CMD_PFN_V(pf) |
7035 FW_EQ_ETH_CMD_VFN_V(vf));
7036 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7037 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7038 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7039 }
7040
7041 /**
7042 * t4_ctrl_eq_free - free a control egress queue
7043 * @adap: the adapter
7044 * @mbox: mailbox to use for the FW command
7045 * @pf: the PF owning the queue
7046 * @vf: the VF owning the queue
7047 * @eqid: egress queue id
7048 *
7049 * Frees a control egress queue.
7050 */
7051 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7052 unsigned int vf, unsigned int eqid)
7053 {
7054 struct fw_eq_ctrl_cmd c;
7055
7056 memset(&c, 0, sizeof(c));
7057 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7058 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7059 FW_EQ_CTRL_CMD_PFN_V(pf) |
7060 FW_EQ_CTRL_CMD_VFN_V(vf));
7061 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7062 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7063 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7064 }
7065
7066 /**
7067 * t4_ofld_eq_free - free an offload egress queue
7068 * @adap: the adapter
7069 * @mbox: mailbox to use for the FW command
7070 * @pf: the PF owning the queue
7071 * @vf: the VF owning the queue
7072 * @eqid: egress queue id
7073 *
7074 * Frees a control egress queue.
7075 */
7076 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7077 unsigned int vf, unsigned int eqid)
7078 {
7079 struct fw_eq_ofld_cmd c;
7080
7081 memset(&c, 0, sizeof(c));
7082 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7083 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7084 FW_EQ_OFLD_CMD_PFN_V(pf) |
7085 FW_EQ_OFLD_CMD_VFN_V(vf));
7086 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7087 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7088 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7089 }
7090
7091 /**
7092 * t4_handle_fw_rpl - process a FW reply message
7093 * @adap: the adapter
7094 * @rpl: start of the FW message
7095 *
7096 * Processes a FW message, such as link state change messages.
7097 */
7098 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7099 {
7100 u8 opcode = *(const u8 *)rpl;
7101
7102 if (opcode == FW_PORT_CMD) { /* link/module state change message */
7103 int speed = 0, fc = 0;
7104 const struct fw_port_cmd *p = (void *)rpl;
7105 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
7106 int port = adap->chan_map[chan];
7107 struct port_info *pi = adap2pinfo(adap, port);
7108 struct link_config *lc = &pi->link_cfg;
7109 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
7110 int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
7111 u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
7112
7113 if (stat & FW_PORT_CMD_RXPAUSE_F)
7114 fc |= PAUSE_RX;
7115 if (stat & FW_PORT_CMD_TXPAUSE_F)
7116 fc |= PAUSE_TX;
7117 if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
7118 speed = 100;
7119 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
7120 speed = 1000;
7121 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
7122 speed = 10000;
7123 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
7124 speed = 40000;
7125
7126 if (link_ok != lc->link_ok || speed != lc->speed ||
7127 fc != lc->fc) { /* something changed */
7128 lc->link_ok = link_ok;
7129 lc->speed = speed;
7130 lc->fc = fc;
7131 lc->supported = be16_to_cpu(p->u.info.pcap);
7132 t4_os_link_changed(adap, port, link_ok);
7133 }
7134 if (mod != pi->mod_type) {
7135 pi->mod_type = mod;
7136 t4_os_portmod_changed(adap, port);
7137 }
7138 }
7139 return 0;
7140 }
7141
7142 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
7143 {
7144 u16 val;
7145
7146 if (pci_is_pcie(adapter->pdev)) {
7147 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
7148 p->speed = val & PCI_EXP_LNKSTA_CLS;
7149 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7150 }
7151 }
7152
7153 /**
7154 * init_link_config - initialize a link's SW state
7155 * @lc: structure holding the link state
7156 * @caps: link capabilities
7157 *
7158 * Initializes the SW state maintained for each link, including the link's
7159 * capabilities and default speed/flow-control/autonegotiation settings.
7160 */
7161 static void init_link_config(struct link_config *lc, unsigned int caps)
7162 {
7163 lc->supported = caps;
7164 lc->requested_speed = 0;
7165 lc->speed = 0;
7166 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7167 if (lc->supported & FW_PORT_CAP_ANEG) {
7168 lc->advertising = lc->supported & ADVERT_MASK;
7169 lc->autoneg = AUTONEG_ENABLE;
7170 lc->requested_fc |= PAUSE_AUTONEG;
7171 } else {
7172 lc->advertising = 0;
7173 lc->autoneg = AUTONEG_DISABLE;
7174 }
7175 }
7176
7177 #define CIM_PF_NOACCESS 0xeeeeeeee
7178
7179 int t4_wait_dev_ready(void __iomem *regs)
7180 {
7181 u32 whoami;
7182
7183 whoami = readl(regs + PL_WHOAMI_A);
7184 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
7185 return 0;
7186
7187 msleep(500);
7188 whoami = readl(regs + PL_WHOAMI_A);
7189 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
7190 }
7191
7192 struct flash_desc {
7193 u32 vendor_and_model_id;
7194 u32 size_mb;
7195 };
7196
7197 static int get_flash_params(struct adapter *adap)
7198 {
7199 /* Table for non-Numonix supported flash parts. Numonix parts are left
7200 * to the preexisting code. All flash parts have 64KB sectors.
7201 */
7202 static struct flash_desc supported_flash[] = {
7203 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
7204 };
7205
7206 int ret;
7207 u32 info;
7208
7209 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
7210 if (!ret)
7211 ret = sf1_read(adap, 3, 0, 1, &info);
7212 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
7213 if (ret)
7214 return ret;
7215
7216 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7217 if (supported_flash[ret].vendor_and_model_id == info) {
7218 adap->params.sf_size = supported_flash[ret].size_mb;
7219 adap->params.sf_nsec =
7220 adap->params.sf_size / SF_SEC_SIZE;
7221 return 0;
7222 }
7223
7224 if ((info & 0xff) != 0x20) /* not a Numonix flash */
7225 return -EINVAL;
7226 info >>= 16; /* log2 of size */
7227 if (info >= 0x14 && info < 0x18)
7228 adap->params.sf_nsec = 1 << (info - 16);
7229 else if (info == 0x18)
7230 adap->params.sf_nsec = 64;
7231 else
7232 return -EINVAL;
7233 adap->params.sf_size = 1 << info;
7234 adap->params.sf_fw_start =
7235 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
7236
7237 if (adap->params.sf_size < FLASH_MIN_SIZE)
7238 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
7239 adap->params.sf_size, FLASH_MIN_SIZE);
7240 return 0;
7241 }
7242
7243 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
7244 {
7245 u16 val;
7246 u32 pcie_cap;
7247
7248 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
7249 if (pcie_cap) {
7250 pci_read_config_word(adapter->pdev,
7251 pcie_cap + PCI_EXP_DEVCTL2, &val);
7252 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
7253 val |= range;
7254 pci_write_config_word(adapter->pdev,
7255 pcie_cap + PCI_EXP_DEVCTL2, val);
7256 }
7257 }
7258
7259 /**
7260 * t4_prep_adapter - prepare SW and HW for operation
7261 * @adapter: the adapter
7262 * @reset: if true perform a HW reset
7263 *
7264 * Initialize adapter SW state for the various HW modules, set initial
7265 * values for some adapter tunables, take PHYs out of reset, and
7266 * initialize the MDIO interface.
7267 */
7268 int t4_prep_adapter(struct adapter *adapter)
7269 {
7270 int ret, ver;
7271 uint16_t device_id;
7272 u32 pl_rev;
7273
7274 get_pci_mode(adapter, &adapter->params.pci);
7275 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
7276
7277 ret = get_flash_params(adapter);
7278 if (ret < 0) {
7279 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
7280 return ret;
7281 }
7282
7283 /* Retrieve adapter's device ID
7284 */
7285 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
7286 ver = device_id >> 12;
7287 adapter->params.chip = 0;
7288 switch (ver) {
7289 case CHELSIO_T4:
7290 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
7291 adapter->params.arch.sge_fl_db = DBPRIO_F;
7292 adapter->params.arch.mps_tcam_size =
7293 NUM_MPS_CLS_SRAM_L_INSTANCES;
7294 adapter->params.arch.mps_rplc_size = 128;
7295 adapter->params.arch.nchan = NCHAN;
7296 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7297 adapter->params.arch.vfcount = 128;
7298 /* Congestion map is for 4 channels so that
7299 * MPS can have 4 priority per port.
7300 */
7301 adapter->params.arch.cng_ch_bits_log = 2;
7302 break;
7303 case CHELSIO_T5:
7304 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
7305 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
7306 adapter->params.arch.mps_tcam_size =
7307 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7308 adapter->params.arch.mps_rplc_size = 128;
7309 adapter->params.arch.nchan = NCHAN;
7310 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7311 adapter->params.arch.vfcount = 128;
7312 adapter->params.arch.cng_ch_bits_log = 2;
7313 break;
7314 case CHELSIO_T6:
7315 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
7316 adapter->params.arch.sge_fl_db = 0;
7317 adapter->params.arch.mps_tcam_size =
7318 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7319 adapter->params.arch.mps_rplc_size = 256;
7320 adapter->params.arch.nchan = 2;
7321 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
7322 adapter->params.arch.vfcount = 256;
7323 /* Congestion map will be for 2 channels so that
7324 * MPS can have 8 priority per port.
7325 */
7326 adapter->params.arch.cng_ch_bits_log = 3;
7327 break;
7328 default:
7329 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
7330 device_id);
7331 return -EINVAL;
7332 }
7333
7334 adapter->params.cim_la_size = CIMLA_SIZE;
7335 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7336
7337 /*
7338 * Default port for debugging in case we can't reach FW.
7339 */
7340 adapter->params.nports = 1;
7341 adapter->params.portvec = 1;
7342 adapter->params.vpd.cclk = 50000;
7343
7344 /* Set pci completion timeout value to 4 seconds. */
7345 set_pcie_completion_timeout(adapter, 0xd);
7346 return 0;
7347 }
7348
7349 /**
7350 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
7351 * @adapter: the adapter
7352 * @qid: the Queue ID
7353 * @qtype: the Ingress or Egress type for @qid
7354 * @user: true if this request is for a user mode queue
7355 * @pbar2_qoffset: BAR2 Queue Offset
7356 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
7357 *
7358 * Returns the BAR2 SGE Queue Registers information associated with the
7359 * indicated Absolute Queue ID. These are passed back in return value
7360 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
7361 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
7362 *
7363 * This may return an error which indicates that BAR2 SGE Queue
7364 * registers aren't available. If an error is not returned, then the
7365 * following values are returned:
7366 *
7367 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
7368 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
7369 *
7370 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
7371 * require the "Inferred Queue ID" ability may be used. E.g. the
7372 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
7373 * then these "Inferred Queue ID" register may not be used.
7374 */
7375 int t4_bar2_sge_qregs(struct adapter *adapter,
7376 unsigned int qid,
7377 enum t4_bar2_qtype qtype,
7378 int user,
7379 u64 *pbar2_qoffset,
7380 unsigned int *pbar2_qid)
7381 {
7382 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
7383 u64 bar2_page_offset, bar2_qoffset;
7384 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
7385
7386 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
7387 if (!user && is_t4(adapter->params.chip))
7388 return -EINVAL;
7389
7390 /* Get our SGE Page Size parameters.
7391 */
7392 page_shift = adapter->params.sge.hps + 10;
7393 page_size = 1 << page_shift;
7394
7395 /* Get the right Queues per Page parameters for our Queue.
7396 */
7397 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
7398 ? adapter->params.sge.eq_qpp
7399 : adapter->params.sge.iq_qpp);
7400 qpp_mask = (1 << qpp_shift) - 1;
7401
7402 /* Calculate the basics of the BAR2 SGE Queue register area:
7403 * o The BAR2 page the Queue registers will be in.
7404 * o The BAR2 Queue ID.
7405 * o The BAR2 Queue ID Offset into the BAR2 page.
7406 */
7407 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
7408 bar2_qid = qid & qpp_mask;
7409 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
7410
7411 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
7412 * hardware will infer the Absolute Queue ID simply from the writes to
7413 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
7414 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
7415 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
7416 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
7417 * from the BAR2 Page and BAR2 Queue ID.
7418 *
7419 * One important censequence of this is that some BAR2 SGE registers
7420 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
7421 * there. But other registers synthesize the SGE Queue ID purely
7422 * from the writes to the registers -- the Write Combined Doorbell
7423 * Buffer is a good example. These BAR2 SGE Registers are only
7424 * available for those BAR2 SGE Register areas where the SGE Absolute
7425 * Queue ID can be inferred from simple writes.
7426 */
7427 bar2_qoffset = bar2_page_offset;
7428 bar2_qinferred = (bar2_qid_offset < page_size);
7429 if (bar2_qinferred) {
7430 bar2_qoffset += bar2_qid_offset;
7431 bar2_qid = 0;
7432 }
7433
7434 *pbar2_qoffset = bar2_qoffset;
7435 *pbar2_qid = bar2_qid;
7436 return 0;
7437 }
7438
7439 /**
7440 * t4_init_devlog_params - initialize adapter->params.devlog
7441 * @adap: the adapter
7442 *
7443 * Initialize various fields of the adapter's Firmware Device Log
7444 * Parameters structure.
7445 */
7446 int t4_init_devlog_params(struct adapter *adap)
7447 {
7448 struct devlog_params *dparams = &adap->params.devlog;
7449 u32 pf_dparams;
7450 unsigned int devlog_meminfo;
7451 struct fw_devlog_cmd devlog_cmd;
7452 int ret;
7453
7454 /* If we're dealing with newer firmware, the Device Log Paramerters
7455 * are stored in a designated register which allows us to access the
7456 * Device Log even if we can't talk to the firmware.
7457 */
7458 pf_dparams =
7459 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
7460 if (pf_dparams) {
7461 unsigned int nentries, nentries128;
7462
7463 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
7464 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
7465
7466 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
7467 nentries = (nentries128 + 1) * 128;
7468 dparams->size = nentries * sizeof(struct fw_devlog_e);
7469
7470 return 0;
7471 }
7472
7473 /* Otherwise, ask the firmware for it's Device Log Parameters.
7474 */
7475 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
7476 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
7477 FW_CMD_REQUEST_F | FW_CMD_READ_F);
7478 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7479 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7480 &devlog_cmd);
7481 if (ret)
7482 return ret;
7483
7484 devlog_meminfo =
7485 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7486 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
7487 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
7488 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7489
7490 return 0;
7491 }
7492
7493 /**
7494 * t4_init_sge_params - initialize adap->params.sge
7495 * @adapter: the adapter
7496 *
7497 * Initialize various fields of the adapter's SGE Parameters structure.
7498 */
7499 int t4_init_sge_params(struct adapter *adapter)
7500 {
7501 struct sge_params *sge_params = &adapter->params.sge;
7502 u32 hps, qpp;
7503 unsigned int s_hps, s_qpp;
7504
7505 /* Extract the SGE Page Size for our PF.
7506 */
7507 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
7508 s_hps = (HOSTPAGESIZEPF0_S +
7509 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
7510 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
7511
7512 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
7513 */
7514 s_qpp = (QUEUESPERPAGEPF0_S +
7515 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
7516 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
7517 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7518 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
7519 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7520
7521 return 0;
7522 }
7523
7524 /**
7525 * t4_init_tp_params - initialize adap->params.tp
7526 * @adap: the adapter
7527 *
7528 * Initialize various fields of the adapter's TP Parameters structure.
7529 */
7530 int t4_init_tp_params(struct adapter *adap)
7531 {
7532 int chan;
7533 u32 v;
7534
7535 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
7536 adap->params.tp.tre = TIMERRESOLUTION_G(v);
7537 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
7538
7539 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
7540 for (chan = 0; chan < NCHAN; chan++)
7541 adap->params.tp.tx_modq[chan] = chan;
7542
7543 /* Cache the adapter's Compressed Filter Mode and global Incress
7544 * Configuration.
7545 */
7546 if (t4_use_ldst(adap)) {
7547 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
7548 TP_VLAN_PRI_MAP_A, 1);
7549 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
7550 TP_INGRESS_CONFIG_A, 1);
7551 } else {
7552 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7553 &adap->params.tp.vlan_pri_map, 1,
7554 TP_VLAN_PRI_MAP_A);
7555 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7556 &adap->params.tp.ingress_config, 1,
7557 TP_INGRESS_CONFIG_A);
7558 }
7559
7560 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7561 * shift positions of several elements of the Compressed Filter Tuple
7562 * for this adapter which we need frequently ...
7563 */
7564 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
7565 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
7566 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
7567 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
7568 PROTOCOL_F);
7569
7570 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
7571 * represents the presence of an Outer VLAN instead of a VNIC ID.
7572 */
7573 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
7574 adap->params.tp.vnic_shift = -1;
7575
7576 return 0;
7577 }
7578
7579 /**
7580 * t4_filter_field_shift - calculate filter field shift
7581 * @adap: the adapter
7582 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
7583 *
7584 * Return the shift position of a filter field within the Compressed
7585 * Filter Tuple. The filter field is specified via its selection bit
7586 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
7587 */
7588 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
7589 {
7590 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
7591 unsigned int sel;
7592 int field_shift;
7593
7594 if ((filter_mode & filter_sel) == 0)
7595 return -1;
7596
7597 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
7598 switch (filter_mode & sel) {
7599 case FCOE_F:
7600 field_shift += FT_FCOE_W;
7601 break;
7602 case PORT_F:
7603 field_shift += FT_PORT_W;
7604 break;
7605 case VNIC_ID_F:
7606 field_shift += FT_VNIC_ID_W;
7607 break;
7608 case VLAN_F:
7609 field_shift += FT_VLAN_W;
7610 break;
7611 case TOS_F:
7612 field_shift += FT_TOS_W;
7613 break;
7614 case PROTOCOL_F:
7615 field_shift += FT_PROTOCOL_W;
7616 break;
7617 case ETHERTYPE_F:
7618 field_shift += FT_ETHERTYPE_W;
7619 break;
7620 case MACMATCH_F:
7621 field_shift += FT_MACMATCH_W;
7622 break;
7623 case MPSHITTYPE_F:
7624 field_shift += FT_MPSHITTYPE_W;
7625 break;
7626 case FRAGMENTATION_F:
7627 field_shift += FT_FRAGMENTATION_W;
7628 break;
7629 }
7630 }
7631 return field_shift;
7632 }
7633
7634 int t4_init_rss_mode(struct adapter *adap, int mbox)
7635 {
7636 int i, ret;
7637 struct fw_rss_vi_config_cmd rvc;
7638
7639 memset(&rvc, 0, sizeof(rvc));
7640
7641 for_each_port(adap, i) {
7642 struct port_info *p = adap2pinfo(adap, i);
7643
7644 rvc.op_to_viid =
7645 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7646 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7647 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
7648 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7649 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7650 if (ret)
7651 return ret;
7652 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7653 }
7654 return 0;
7655 }
7656
7657 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
7658 {
7659 u8 addr[6];
7660 int ret, i, j = 0;
7661 struct fw_port_cmd c;
7662 struct fw_rss_vi_config_cmd rvc;
7663
7664 memset(&c, 0, sizeof(c));
7665 memset(&rvc, 0, sizeof(rvc));
7666
7667 for_each_port(adap, i) {
7668 unsigned int rss_size;
7669 struct port_info *p = adap2pinfo(adap, i);
7670
7671 while ((adap->params.portvec & (1 << j)) == 0)
7672 j++;
7673
7674 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
7675 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7676 FW_PORT_CMD_PORTID_V(j));
7677 c.action_to_len16 = cpu_to_be32(
7678 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
7679 FW_LEN16(c));
7680 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7681 if (ret)
7682 return ret;
7683
7684 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
7685 if (ret < 0)
7686 return ret;
7687
7688 p->viid = ret;
7689 p->tx_chan = j;
7690 p->lport = j;
7691 p->rss_size = rss_size;
7692 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
7693 adap->port[i]->dev_port = j;
7694
7695 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
7696 p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
7697 FW_PORT_CMD_MDIOADDR_G(ret) : -1;
7698 p->port_type = FW_PORT_CMD_PTYPE_G(ret);
7699 p->mod_type = FW_PORT_MOD_TYPE_NA;
7700
7701 rvc.op_to_viid =
7702 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7703 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7704 FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
7705 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7706 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7707 if (ret)
7708 return ret;
7709 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7710
7711 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap));
7712 j++;
7713 }
7714 return 0;
7715 }
7716
7717 /**
7718 * t4_read_cimq_cfg - read CIM queue configuration
7719 * @adap: the adapter
7720 * @base: holds the queue base addresses in bytes
7721 * @size: holds the queue sizes in bytes
7722 * @thres: holds the queue full thresholds in bytes
7723 *
7724 * Returns the current configuration of the CIM queues, starting with
7725 * the IBQs, then the OBQs.
7726 */
7727 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
7728 {
7729 unsigned int i, v;
7730 int cim_num_obq = is_t4(adap->params.chip) ?
7731 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7732
7733 for (i = 0; i < CIM_NUM_IBQ; i++) {
7734 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
7735 QUENUMSELECT_V(i));
7736 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7737 /* value is in 256-byte units */
7738 *base++ = CIMQBASE_G(v) * 256;
7739 *size++ = CIMQSIZE_G(v) * 256;
7740 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
7741 }
7742 for (i = 0; i < cim_num_obq; i++) {
7743 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7744 QUENUMSELECT_V(i));
7745 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7746 /* value is in 256-byte units */
7747 *base++ = CIMQBASE_G(v) * 256;
7748 *size++ = CIMQSIZE_G(v) * 256;
7749 }
7750 }
7751
7752 /**
7753 * t4_read_cim_ibq - read the contents of a CIM inbound queue
7754 * @adap: the adapter
7755 * @qid: the queue index
7756 * @data: where to store the queue contents
7757 * @n: capacity of @data in 32-bit words
7758 *
7759 * Reads the contents of the selected CIM queue starting at address 0 up
7760 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
7761 * error and the number of 32-bit words actually read on success.
7762 */
7763 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7764 {
7765 int i, err, attempts;
7766 unsigned int addr;
7767 const unsigned int nwords = CIM_IBQ_SIZE * 4;
7768
7769 if (qid > 5 || (n & 3))
7770 return -EINVAL;
7771
7772 addr = qid * nwords;
7773 if (n > nwords)
7774 n = nwords;
7775
7776 /* It might take 3-10ms before the IBQ debug read access is allowed.
7777 * Wait for 1 Sec with a delay of 1 usec.
7778 */
7779 attempts = 1000000;
7780
7781 for (i = 0; i < n; i++, addr++) {
7782 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
7783 IBQDBGEN_F);
7784 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
7785 attempts, 1);
7786 if (err)
7787 return err;
7788 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
7789 }
7790 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
7791 return i;
7792 }
7793
7794 /**
7795 * t4_read_cim_obq - read the contents of a CIM outbound queue
7796 * @adap: the adapter
7797 * @qid: the queue index
7798 * @data: where to store the queue contents
7799 * @n: capacity of @data in 32-bit words
7800 *
7801 * Reads the contents of the selected CIM queue starting at address 0 up
7802 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
7803 * error and the number of 32-bit words actually read on success.
7804 */
7805 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7806 {
7807 int i, err;
7808 unsigned int addr, v, nwords;
7809 int cim_num_obq = is_t4(adap->params.chip) ?
7810 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7811
7812 if ((qid > (cim_num_obq - 1)) || (n & 3))
7813 return -EINVAL;
7814
7815 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7816 QUENUMSELECT_V(qid));
7817 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7818
7819 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
7820 nwords = CIMQSIZE_G(v) * 64; /* same */
7821 if (n > nwords)
7822 n = nwords;
7823
7824 for (i = 0; i < n; i++, addr++) {
7825 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
7826 OBQDBGEN_F);
7827 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
7828 2, 1);
7829 if (err)
7830 return err;
7831 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
7832 }
7833 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
7834 return i;
7835 }
7836
7837 /**
7838 * t4_cim_read - read a block from CIM internal address space
7839 * @adap: the adapter
7840 * @addr: the start address within the CIM address space
7841 * @n: number of words to read
7842 * @valp: where to store the result
7843 *
7844 * Reads a block of 4-byte words from the CIM intenal address space.
7845 */
7846 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
7847 unsigned int *valp)
7848 {
7849 int ret = 0;
7850
7851 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
7852 return -EBUSY;
7853
7854 for ( ; !ret && n--; addr += 4) {
7855 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
7856 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
7857 0, 5, 2);
7858 if (!ret)
7859 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
7860 }
7861 return ret;
7862 }
7863
7864 /**
7865 * t4_cim_write - write a block into CIM internal address space
7866 * @adap: the adapter
7867 * @addr: the start address within the CIM address space
7868 * @n: number of words to write
7869 * @valp: set of values to write
7870 *
7871 * Writes a block of 4-byte words into the CIM intenal address space.
7872 */
7873 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
7874 const unsigned int *valp)
7875 {
7876 int ret = 0;
7877
7878 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
7879 return -EBUSY;
7880
7881 for ( ; !ret && n--; addr += 4) {
7882 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
7883 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
7884 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
7885 0, 5, 2);
7886 }
7887 return ret;
7888 }
7889
7890 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
7891 unsigned int val)
7892 {
7893 return t4_cim_write(adap, addr, 1, &val);
7894 }
7895
7896 /**
7897 * t4_cim_read_la - read CIM LA capture buffer
7898 * @adap: the adapter
7899 * @la_buf: where to store the LA data
7900 * @wrptr: the HW write pointer within the capture buffer
7901 *
7902 * Reads the contents of the CIM LA buffer with the most recent entry at
7903 * the end of the returned data and with the entry at @wrptr first.
7904 * We try to leave the LA in the running state we find it in.
7905 */
7906 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
7907 {
7908 int i, ret;
7909 unsigned int cfg, val, idx;
7910
7911 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
7912 if (ret)
7913 return ret;
7914
7915 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
7916 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
7917 if (ret)
7918 return ret;
7919 }
7920
7921 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
7922 if (ret)
7923 goto restart;
7924
7925 idx = UPDBGLAWRPTR_G(val);
7926 if (wrptr)
7927 *wrptr = idx;
7928
7929 for (i = 0; i < adap->params.cim_la_size; i++) {
7930 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
7931 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
7932 if (ret)
7933 break;
7934 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
7935 if (ret)
7936 break;
7937 if (val & UPDBGLARDEN_F) {
7938 ret = -ETIMEDOUT;
7939 break;
7940 }
7941 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
7942 if (ret)
7943 break;
7944 idx = (idx + 1) & UPDBGLARDPTR_M;
7945 }
7946 restart:
7947 if (cfg & UPDBGLAEN_F) {
7948 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
7949 cfg & ~UPDBGLARDEN_F);
7950 if (!ret)
7951 ret = r;
7952 }
7953 return ret;
7954 }
7955
7956 /**
7957 * t4_tp_read_la - read TP LA capture buffer
7958 * @adap: the adapter
7959 * @la_buf: where to store the LA data
7960 * @wrptr: the HW write pointer within the capture buffer
7961 *
7962 * Reads the contents of the TP LA buffer with the most recent entry at
7963 * the end of the returned data and with the entry at @wrptr first.
7964 * We leave the LA in the running state we find it in.
7965 */
7966 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
7967 {
7968 bool last_incomplete;
7969 unsigned int i, cfg, val, idx;
7970
7971 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
7972 if (cfg & DBGLAENABLE_F) /* freeze LA */
7973 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
7974 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
7975
7976 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
7977 idx = DBGLAWPTR_G(val);
7978 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
7979 if (last_incomplete)
7980 idx = (idx + 1) & DBGLARPTR_M;
7981 if (wrptr)
7982 *wrptr = idx;
7983
7984 val &= 0xffff;
7985 val &= ~DBGLARPTR_V(DBGLARPTR_M);
7986 val |= adap->params.tp.la_mask;
7987
7988 for (i = 0; i < TPLA_SIZE; i++) {
7989 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
7990 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
7991 idx = (idx + 1) & DBGLARPTR_M;
7992 }
7993
7994 /* Wipe out last entry if it isn't valid */
7995 if (last_incomplete)
7996 la_buf[TPLA_SIZE - 1] = ~0ULL;
7997
7998 if (cfg & DBGLAENABLE_F) /* restore running state */
7999 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8000 cfg | adap->params.tp.la_mask);
8001 }
8002
8003 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
8004 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
8005 * state for more than the Warning Threshold then we'll issue a warning about
8006 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
8007 * appears to be hung every Warning Repeat second till the situation clears.
8008 * If the situation clears, we'll note that as well.
8009 */
8010 #define SGE_IDMA_WARN_THRESH 1
8011 #define SGE_IDMA_WARN_REPEAT 300
8012
8013 /**
8014 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
8015 * @adapter: the adapter
8016 * @idma: the adapter IDMA Monitor state
8017 *
8018 * Initialize the state of an SGE Ingress DMA Monitor.
8019 */
8020 void t4_idma_monitor_init(struct adapter *adapter,
8021 struct sge_idma_monitor_state *idma)
8022 {
8023 /* Initialize the state variables for detecting an SGE Ingress DMA
8024 * hang. The SGE has internal counters which count up on each clock
8025 * tick whenever the SGE finds its Ingress DMA State Engines in the
8026 * same state they were on the previous clock tick. The clock used is
8027 * the Core Clock so we have a limit on the maximum "time" they can
8028 * record; typically a very small number of seconds. For instance,
8029 * with a 600MHz Core Clock, we can only count up to a bit more than
8030 * 7s. So we'll synthesize a larger counter in order to not run the
8031 * risk of having the "timers" overflow and give us the flexibility to
8032 * maintain a Hung SGE State Machine of our own which operates across
8033 * a longer time frame.
8034 */
8035 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
8036 idma->idma_stalled[0] = 0;
8037 idma->idma_stalled[1] = 0;
8038 }
8039
8040 /**
8041 * t4_idma_monitor - monitor SGE Ingress DMA state
8042 * @adapter: the adapter
8043 * @idma: the adapter IDMA Monitor state
8044 * @hz: number of ticks/second
8045 * @ticks: number of ticks since the last IDMA Monitor call
8046 */
8047 void t4_idma_monitor(struct adapter *adapter,
8048 struct sge_idma_monitor_state *idma,
8049 int hz, int ticks)
8050 {
8051 int i, idma_same_state_cnt[2];
8052
8053 /* Read the SGE Debug Ingress DMA Same State Count registers. These
8054 * are counters inside the SGE which count up on each clock when the
8055 * SGE finds its Ingress DMA State Engines in the same states they
8056 * were in the previous clock. The counters will peg out at
8057 * 0xffffffff without wrapping around so once they pass the 1s
8058 * threshold they'll stay above that till the IDMA state changes.
8059 */
8060 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
8061 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
8062 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8063
8064 for (i = 0; i < 2; i++) {
8065 u32 debug0, debug11;
8066
8067 /* If the Ingress DMA Same State Counter ("timer") is less
8068 * than 1s, then we can reset our synthesized Stall Timer and
8069 * continue. If we have previously emitted warnings about a
8070 * potential stalled Ingress Queue, issue a note indicating
8071 * that the Ingress Queue has resumed forward progress.
8072 */
8073 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8074 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
8075 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
8076 "resumed after %d seconds\n",
8077 i, idma->idma_qid[i],
8078 idma->idma_stalled[i] / hz);
8079 idma->idma_stalled[i] = 0;
8080 continue;
8081 }
8082
8083 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8084 * domain. The first time we get here it'll be because we
8085 * passed the 1s Threshold; each additional time it'll be
8086 * because the RX Timer Callback is being fired on its regular
8087 * schedule.
8088 *
8089 * If the stall is below our Potential Hung Ingress Queue
8090 * Warning Threshold, continue.
8091 */
8092 if (idma->idma_stalled[i] == 0) {
8093 idma->idma_stalled[i] = hz;
8094 idma->idma_warn[i] = 0;
8095 } else {
8096 idma->idma_stalled[i] += ticks;
8097 idma->idma_warn[i] -= ticks;
8098 }
8099
8100 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
8101 continue;
8102
8103 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8104 */
8105 if (idma->idma_warn[i] > 0)
8106 continue;
8107 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
8108
8109 /* Read and save the SGE IDMA State and Queue ID information.
8110 * We do this every time in case it changes across time ...
8111 * can't be too careful ...
8112 */
8113 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
8114 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8115 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8116
8117 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
8118 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8119 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8120
8121 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
8122 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8123 i, idma->idma_qid[i], idma->idma_state[i],
8124 idma->idma_stalled[i] / hz,
8125 debug0, debug11);
8126 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
8127 }
8128 }
Linux kernel - Deliverables
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