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Merge remote-tracking branch 'regulator/for-next'
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / t4fw_api.h
1 /*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2009-2016 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #ifndef _T4FW_INTERFACE_H_
36 #define _T4FW_INTERFACE_H_
37
38 enum fw_retval {
39 FW_SUCCESS = 0, /* completed successfully */
40 FW_EPERM = 1, /* operation not permitted */
41 FW_ENOENT = 2, /* no such file or directory */
42 FW_EIO = 5, /* input/output error; hw bad */
43 FW_ENOEXEC = 8, /* exec format error; inv microcode */
44 FW_EAGAIN = 11, /* try again */
45 FW_ENOMEM = 12, /* out of memory */
46 FW_EFAULT = 14, /* bad address; fw bad */
47 FW_EBUSY = 16, /* resource busy */
48 FW_EEXIST = 17, /* file exists */
49 FW_ENODEV = 19, /* no such device */
50 FW_EINVAL = 22, /* invalid argument */
51 FW_ENOSPC = 28, /* no space left on device */
52 FW_ENOSYS = 38, /* functionality not implemented */
53 FW_ENODATA = 61, /* no data available */
54 FW_EPROTO = 71, /* protocol error */
55 FW_EADDRINUSE = 98, /* address already in use */
56 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
57 FW_ENETDOWN = 100, /* network is down */
58 FW_ENETUNREACH = 101, /* network is unreachable */
59 FW_ENOBUFS = 105, /* no buffer space available */
60 FW_ETIMEDOUT = 110, /* timeout */
61 FW_EINPROGRESS = 115, /* fw internal */
62 FW_SCSI_ABORT_REQUESTED = 128, /* */
63 FW_SCSI_ABORT_TIMEDOUT = 129, /* */
64 FW_SCSI_ABORTED = 130, /* */
65 FW_SCSI_CLOSE_REQUESTED = 131, /* */
66 FW_ERR_LINK_DOWN = 132, /* */
67 FW_RDEV_NOT_READY = 133, /* */
68 FW_ERR_RDEV_LOST = 134, /* */
69 FW_ERR_RDEV_LOGO = 135, /* */
70 FW_FCOE_NO_XCHG = 136, /* */
71 FW_SCSI_RSP_ERR = 137, /* */
72 FW_ERR_RDEV_IMPL_LOGO = 138, /* */
73 FW_SCSI_UNDER_FLOW_ERR = 139, /* */
74 FW_SCSI_OVER_FLOW_ERR = 140, /* */
75 FW_SCSI_DDP_ERR = 141, /* DDP error*/
76 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */
77 };
78
79 #define FW_T4VF_SGE_BASE_ADDR 0x0000
80 #define FW_T4VF_MPS_BASE_ADDR 0x0100
81 #define FW_T4VF_PL_BASE_ADDR 0x0200
82 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240
83 #define FW_T4VF_CIM_BASE_ADDR 0x0300
84
85 enum fw_wr_opcodes {
86 FW_FILTER_WR = 0x02,
87 FW_ULPTX_WR = 0x04,
88 FW_TP_WR = 0x05,
89 FW_ETH_TX_PKT_WR = 0x08,
90 FW_OFLD_CONNECTION_WR = 0x2f,
91 FW_FLOWC_WR = 0x0a,
92 FW_OFLD_TX_DATA_WR = 0x0b,
93 FW_CMD_WR = 0x10,
94 FW_ETH_TX_PKT_VM_WR = 0x11,
95 FW_RI_RES_WR = 0x0c,
96 FW_RI_INIT_WR = 0x0d,
97 FW_RI_RDMA_WRITE_WR = 0x14,
98 FW_RI_SEND_WR = 0x15,
99 FW_RI_RDMA_READ_WR = 0x16,
100 FW_RI_RECV_WR = 0x17,
101 FW_RI_BIND_MW_WR = 0x18,
102 FW_RI_FR_NSMR_WR = 0x19,
103 FW_RI_INV_LSTAG_WR = 0x1a,
104 FW_ISCSI_TX_DATA_WR = 0x45,
105 FW_CRYPTO_LOOKASIDE_WR = 0X6d,
106 FW_LASTC2E_WR = 0x70
107 };
108
109 struct fw_wr_hdr {
110 __be32 hi;
111 __be32 lo;
112 };
113
114 /* work request opcode (hi) */
115 #define FW_WR_OP_S 24
116 #define FW_WR_OP_M 0xff
117 #define FW_WR_OP_V(x) ((x) << FW_WR_OP_S)
118 #define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
119
120 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
121 #define FW_WR_ATOMIC_S 23
122 #define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S)
123
124 /* flush flag (hi) - firmware flushes flushable work request buffered
125 * in the flow context.
126 */
127 #define FW_WR_FLUSH_S 22
128 #define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S)
129
130 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
131 #define FW_WR_COMPL_S 21
132 #define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S)
133 #define FW_WR_COMPL_F FW_WR_COMPL_V(1U)
134
135 /* work request immediate data length (hi) */
136 #define FW_WR_IMMDLEN_S 0
137 #define FW_WR_IMMDLEN_M 0xff
138 #define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S)
139
140 /* egress queue status update to associated ingress queue entry (lo) */
141 #define FW_WR_EQUIQ_S 31
142 #define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S)
143 #define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U)
144
145 /* egress queue status update to egress queue status entry (lo) */
146 #define FW_WR_EQUEQ_S 30
147 #define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S)
148 #define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U)
149
150 /* flow context identifier (lo) */
151 #define FW_WR_FLOWID_S 8
152 #define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S)
153
154 /* length in units of 16-bytes (lo) */
155 #define FW_WR_LEN16_S 0
156 #define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S)
157
158 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B
159 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327
160
161 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
162 enum fw_filter_wr_cookie {
163 FW_FILTER_WR_SUCCESS,
164 FW_FILTER_WR_FLT_ADDED,
165 FW_FILTER_WR_FLT_DELETED,
166 FW_FILTER_WR_SMT_TBL_FULL,
167 FW_FILTER_WR_EINVAL,
168 };
169
170 struct fw_filter_wr {
171 __be32 op_pkd;
172 __be32 len16_pkd;
173 __be64 r3;
174 __be32 tid_to_iq;
175 __be32 del_filter_to_l2tix;
176 __be16 ethtype;
177 __be16 ethtypem;
178 __u8 frag_to_ovlan_vldm;
179 __u8 smac_sel;
180 __be16 rx_chan_rx_rpl_iq;
181 __be32 maci_to_matchtypem;
182 __u8 ptcl;
183 __u8 ptclm;
184 __u8 ttyp;
185 __u8 ttypm;
186 __be16 ivlan;
187 __be16 ivlanm;
188 __be16 ovlan;
189 __be16 ovlanm;
190 __u8 lip[16];
191 __u8 lipm[16];
192 __u8 fip[16];
193 __u8 fipm[16];
194 __be16 lp;
195 __be16 lpm;
196 __be16 fp;
197 __be16 fpm;
198 __be16 r7;
199 __u8 sma[6];
200 };
201
202 #define FW_FILTER_WR_TID_S 12
203 #define FW_FILTER_WR_TID_M 0xfffff
204 #define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S)
205 #define FW_FILTER_WR_TID_G(x) \
206 (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
207
208 #define FW_FILTER_WR_RQTYPE_S 11
209 #define FW_FILTER_WR_RQTYPE_M 0x1
210 #define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S)
211 #define FW_FILTER_WR_RQTYPE_G(x) \
212 (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
213 #define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1U)
214
215 #define FW_FILTER_WR_NOREPLY_S 10
216 #define FW_FILTER_WR_NOREPLY_M 0x1
217 #define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S)
218 #define FW_FILTER_WR_NOREPLY_G(x) \
219 (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
220 #define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1U)
221
222 #define FW_FILTER_WR_IQ_S 0
223 #define FW_FILTER_WR_IQ_M 0x3ff
224 #define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S)
225 #define FW_FILTER_WR_IQ_G(x) \
226 (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
227
228 #define FW_FILTER_WR_DEL_FILTER_S 31
229 #define FW_FILTER_WR_DEL_FILTER_M 0x1
230 #define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S)
231 #define FW_FILTER_WR_DEL_FILTER_G(x) \
232 (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
233 #define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1U)
234
235 #define FW_FILTER_WR_RPTTID_S 25
236 #define FW_FILTER_WR_RPTTID_M 0x1
237 #define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S)
238 #define FW_FILTER_WR_RPTTID_G(x) \
239 (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
240 #define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1U)
241
242 #define FW_FILTER_WR_DROP_S 24
243 #define FW_FILTER_WR_DROP_M 0x1
244 #define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S)
245 #define FW_FILTER_WR_DROP_G(x) \
246 (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
247 #define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1U)
248
249 #define FW_FILTER_WR_DIRSTEER_S 23
250 #define FW_FILTER_WR_DIRSTEER_M 0x1
251 #define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S)
252 #define FW_FILTER_WR_DIRSTEER_G(x) \
253 (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
254 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
255
256 #define FW_FILTER_WR_MASKHASH_S 22
257 #define FW_FILTER_WR_MASKHASH_M 0x1
258 #define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S)
259 #define FW_FILTER_WR_MASKHASH_G(x) \
260 (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
261 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
262
263 #define FW_FILTER_WR_DIRSTEERHASH_S 21
264 #define FW_FILTER_WR_DIRSTEERHASH_M 0x1
265 #define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
266 #define FW_FILTER_WR_DIRSTEERHASH_G(x) \
267 (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
268 #define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1U)
269
270 #define FW_FILTER_WR_LPBK_S 20
271 #define FW_FILTER_WR_LPBK_M 0x1
272 #define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S)
273 #define FW_FILTER_WR_LPBK_G(x) \
274 (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
275 #define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1U)
276
277 #define FW_FILTER_WR_DMAC_S 19
278 #define FW_FILTER_WR_DMAC_M 0x1
279 #define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S)
280 #define FW_FILTER_WR_DMAC_G(x) \
281 (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
282 #define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1U)
283
284 #define FW_FILTER_WR_SMAC_S 18
285 #define FW_FILTER_WR_SMAC_M 0x1
286 #define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S)
287 #define FW_FILTER_WR_SMAC_G(x) \
288 (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
289 #define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1U)
290
291 #define FW_FILTER_WR_INSVLAN_S 17
292 #define FW_FILTER_WR_INSVLAN_M 0x1
293 #define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S)
294 #define FW_FILTER_WR_INSVLAN_G(x) \
295 (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
296 #define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1U)
297
298 #define FW_FILTER_WR_RMVLAN_S 16
299 #define FW_FILTER_WR_RMVLAN_M 0x1
300 #define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S)
301 #define FW_FILTER_WR_RMVLAN_G(x) \
302 (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
303 #define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1U)
304
305 #define FW_FILTER_WR_HITCNTS_S 15
306 #define FW_FILTER_WR_HITCNTS_M 0x1
307 #define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S)
308 #define FW_FILTER_WR_HITCNTS_G(x) \
309 (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
310 #define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1U)
311
312 #define FW_FILTER_WR_TXCHAN_S 13
313 #define FW_FILTER_WR_TXCHAN_M 0x3
314 #define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S)
315 #define FW_FILTER_WR_TXCHAN_G(x) \
316 (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
317
318 #define FW_FILTER_WR_PRIO_S 12
319 #define FW_FILTER_WR_PRIO_M 0x1
320 #define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S)
321 #define FW_FILTER_WR_PRIO_G(x) \
322 (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
323 #define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1U)
324
325 #define FW_FILTER_WR_L2TIX_S 0
326 #define FW_FILTER_WR_L2TIX_M 0xfff
327 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
328 #define FW_FILTER_WR_L2TIX_G(x) \
329 (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
330
331 #define FW_FILTER_WR_FRAG_S 7
332 #define FW_FILTER_WR_FRAG_M 0x1
333 #define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S)
334 #define FW_FILTER_WR_FRAG_G(x) \
335 (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
336 #define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1U)
337
338 #define FW_FILTER_WR_FRAGM_S 6
339 #define FW_FILTER_WR_FRAGM_M 0x1
340 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
341 #define FW_FILTER_WR_FRAGM_G(x) \
342 (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
343 #define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1U)
344
345 #define FW_FILTER_WR_IVLAN_VLD_S 5
346 #define FW_FILTER_WR_IVLAN_VLD_M 0x1
347 #define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S)
348 #define FW_FILTER_WR_IVLAN_VLD_G(x) \
349 (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
350 #define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1U)
351
352 #define FW_FILTER_WR_OVLAN_VLD_S 4
353 #define FW_FILTER_WR_OVLAN_VLD_M 0x1
354 #define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S)
355 #define FW_FILTER_WR_OVLAN_VLD_G(x) \
356 (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
357 #define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1U)
358
359 #define FW_FILTER_WR_IVLAN_VLDM_S 3
360 #define FW_FILTER_WR_IVLAN_VLDM_M 0x1
361 #define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
362 #define FW_FILTER_WR_IVLAN_VLDM_G(x) \
363 (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
364 #define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1U)
365
366 #define FW_FILTER_WR_OVLAN_VLDM_S 2
367 #define FW_FILTER_WR_OVLAN_VLDM_M 0x1
368 #define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
369 #define FW_FILTER_WR_OVLAN_VLDM_G(x) \
370 (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
371 #define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1U)
372
373 #define FW_FILTER_WR_RX_CHAN_S 15
374 #define FW_FILTER_WR_RX_CHAN_M 0x1
375 #define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S)
376 #define FW_FILTER_WR_RX_CHAN_G(x) \
377 (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
378 #define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1U)
379
380 #define FW_FILTER_WR_RX_RPL_IQ_S 0
381 #define FW_FILTER_WR_RX_RPL_IQ_M 0x3ff
382 #define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
383 #define FW_FILTER_WR_RX_RPL_IQ_G(x) \
384 (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
385
386 #define FW_FILTER_WR_MACI_S 23
387 #define FW_FILTER_WR_MACI_M 0x1ff
388 #define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S)
389 #define FW_FILTER_WR_MACI_G(x) \
390 (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
391
392 #define FW_FILTER_WR_MACIM_S 14
393 #define FW_FILTER_WR_MACIM_M 0x1ff
394 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
395 #define FW_FILTER_WR_MACIM_G(x) \
396 (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
397
398 #define FW_FILTER_WR_FCOE_S 13
399 #define FW_FILTER_WR_FCOE_M 0x1
400 #define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S)
401 #define FW_FILTER_WR_FCOE_G(x) \
402 (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
403 #define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1U)
404
405 #define FW_FILTER_WR_FCOEM_S 12
406 #define FW_FILTER_WR_FCOEM_M 0x1
407 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
408 #define FW_FILTER_WR_FCOEM_G(x) \
409 (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
410 #define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1U)
411
412 #define FW_FILTER_WR_PORT_S 9
413 #define FW_FILTER_WR_PORT_M 0x7
414 #define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S)
415 #define FW_FILTER_WR_PORT_G(x) \
416 (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
417
418 #define FW_FILTER_WR_PORTM_S 6
419 #define FW_FILTER_WR_PORTM_M 0x7
420 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
421 #define FW_FILTER_WR_PORTM_G(x) \
422 (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
423
424 #define FW_FILTER_WR_MATCHTYPE_S 3
425 #define FW_FILTER_WR_MATCHTYPE_M 0x7
426 #define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S)
427 #define FW_FILTER_WR_MATCHTYPE_G(x) \
428 (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
429
430 #define FW_FILTER_WR_MATCHTYPEM_S 0
431 #define FW_FILTER_WR_MATCHTYPEM_M 0x7
432 #define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S)
433 #define FW_FILTER_WR_MATCHTYPEM_G(x) \
434 (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
435
436 struct fw_ulptx_wr {
437 __be32 op_to_compl;
438 __be32 flowid_len16;
439 u64 cookie;
440 };
441
442 struct fw_tp_wr {
443 __be32 op_to_immdlen;
444 __be32 flowid_len16;
445 u64 cookie;
446 };
447
448 struct fw_eth_tx_pkt_wr {
449 __be32 op_immdlen;
450 __be32 equiq_to_len16;
451 __be64 r3;
452 };
453
454 struct fw_ofld_connection_wr {
455 __be32 op_compl;
456 __be32 len16_pkd;
457 __u64 cookie;
458 __be64 r2;
459 __be64 r3;
460 struct fw_ofld_connection_le {
461 __be32 version_cpl;
462 __be32 filter;
463 __be32 r1;
464 __be16 lport;
465 __be16 pport;
466 union fw_ofld_connection_leip {
467 struct fw_ofld_connection_le_ipv4 {
468 __be32 pip;
469 __be32 lip;
470 __be64 r0;
471 __be64 r1;
472 __be64 r2;
473 } ipv4;
474 struct fw_ofld_connection_le_ipv6 {
475 __be64 pip_hi;
476 __be64 pip_lo;
477 __be64 lip_hi;
478 __be64 lip_lo;
479 } ipv6;
480 } u;
481 } le;
482 struct fw_ofld_connection_tcb {
483 __be32 t_state_to_astid;
484 __be16 cplrxdataack_cplpassacceptrpl;
485 __be16 rcv_adv;
486 __be32 rcv_nxt;
487 __be32 tx_max;
488 __be64 opt0;
489 __be32 opt2;
490 __be32 r1;
491 __be64 r2;
492 __be64 r3;
493 } tcb;
494 };
495
496 #define FW_OFLD_CONNECTION_WR_VERSION_S 31
497 #define FW_OFLD_CONNECTION_WR_VERSION_M 0x1
498 #define FW_OFLD_CONNECTION_WR_VERSION_V(x) \
499 ((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
500 #define FW_OFLD_CONNECTION_WR_VERSION_G(x) \
501 (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
502 FW_OFLD_CONNECTION_WR_VERSION_M)
503 #define FW_OFLD_CONNECTION_WR_VERSION_F \
504 FW_OFLD_CONNECTION_WR_VERSION_V(1U)
505
506 #define FW_OFLD_CONNECTION_WR_CPL_S 30
507 #define FW_OFLD_CONNECTION_WR_CPL_M 0x1
508 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
509 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
510 (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
511 #define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1U)
512
513 #define FW_OFLD_CONNECTION_WR_T_STATE_S 28
514 #define FW_OFLD_CONNECTION_WR_T_STATE_M 0xf
515 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \
516 ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
517 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \
518 (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
519 FW_OFLD_CONNECTION_WR_T_STATE_M)
520
521 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24
522 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0xf
523 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \
524 ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
525 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \
526 (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
527 FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
528
529 #define FW_OFLD_CONNECTION_WR_ASTID_S 0
530 #define FW_OFLD_CONNECTION_WR_ASTID_M 0xffffff
531 #define FW_OFLD_CONNECTION_WR_ASTID_V(x) \
532 ((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
533 #define FW_OFLD_CONNECTION_WR_ASTID_G(x) \
534 (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
535
536 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15
537 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0x1
538 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \
539 ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
540 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \
541 (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
542 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
543 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \
544 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
545
546 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14
547 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0x1
548 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \
549 ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
550 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \
551 (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
552 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
553 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \
554 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
555
556 enum fw_flowc_mnem {
557 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */
558 FW_FLOWC_MNEM_CH,
559 FW_FLOWC_MNEM_PORT,
560 FW_FLOWC_MNEM_IQID,
561 FW_FLOWC_MNEM_SNDNXT,
562 FW_FLOWC_MNEM_RCVNXT,
563 FW_FLOWC_MNEM_SNDBUF,
564 FW_FLOWC_MNEM_MSS,
565 FW_FLOWC_MNEM_TXDATAPLEN_MAX,
566 FW_FLOWC_MNEM_TCPSTATE,
567 FW_FLOWC_MNEM_EOSTATE,
568 FW_FLOWC_MNEM_SCHEDCLASS,
569 FW_FLOWC_MNEM_DCBPRIO,
570 FW_FLOWC_MNEM_SND_SCALE,
571 FW_FLOWC_MNEM_RCV_SCALE,
572 };
573
574 struct fw_flowc_mnemval {
575 u8 mnemonic;
576 u8 r4[3];
577 __be32 val;
578 };
579
580 struct fw_flowc_wr {
581 __be32 op_to_nparams;
582 __be32 flowid_len16;
583 struct fw_flowc_mnemval mnemval[0];
584 };
585
586 #define FW_FLOWC_WR_NPARAMS_S 0
587 #define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S)
588
589 struct fw_ofld_tx_data_wr {
590 __be32 op_to_immdlen;
591 __be32 flowid_len16;
592 __be32 plen;
593 __be32 tunnel_to_proxy;
594 };
595
596 #define FW_OFLD_TX_DATA_WR_TUNNEL_S 19
597 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
598
599 #define FW_OFLD_TX_DATA_WR_SAVE_S 18
600 #define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
601
602 #define FW_OFLD_TX_DATA_WR_FLUSH_S 17
603 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
604 #define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
605
606 #define FW_OFLD_TX_DATA_WR_URGENT_S 16
607 #define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
608
609 #define FW_OFLD_TX_DATA_WR_MORE_S 15
610 #define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
611
612 #define FW_OFLD_TX_DATA_WR_SHOVE_S 14
613 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
614 #define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
615
616 #define FW_OFLD_TX_DATA_WR_ULPMODE_S 10
617 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
618
619 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6
620 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \
621 ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
622
623 struct fw_cmd_wr {
624 __be32 op_dma;
625 __be32 len16_pkd;
626 __be64 cookie_daddr;
627 };
628
629 #define FW_CMD_WR_DMA_S 17
630 #define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S)
631
632 struct fw_eth_tx_pkt_vm_wr {
633 __be32 op_immdlen;
634 __be32 equiq_to_len16;
635 __be32 r3[2];
636 u8 ethmacdst[6];
637 u8 ethmacsrc[6];
638 __be16 ethtype;
639 __be16 vlantci;
640 };
641
642 #define FW_CMD_MAX_TIMEOUT 10000
643
644 /*
645 * If a host driver does a HELLO and discovers that there's already a MASTER
646 * selected, we may have to wait for that MASTER to finish issuing RESET,
647 * configuration and INITIALIZE commands. Also, there's a possibility that
648 * our own HELLO may get lost if it happens right as the MASTER is issuign a
649 * RESET command, so we need to be willing to make a few retries of our HELLO.
650 */
651 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
652 #define FW_CMD_HELLO_RETRIES 3
653
654
655 enum fw_cmd_opcodes {
656 FW_LDST_CMD = 0x01,
657 FW_RESET_CMD = 0x03,
658 FW_HELLO_CMD = 0x04,
659 FW_BYE_CMD = 0x05,
660 FW_INITIALIZE_CMD = 0x06,
661 FW_CAPS_CONFIG_CMD = 0x07,
662 FW_PARAMS_CMD = 0x08,
663 FW_PFVF_CMD = 0x09,
664 FW_IQ_CMD = 0x10,
665 FW_EQ_MNGT_CMD = 0x11,
666 FW_EQ_ETH_CMD = 0x12,
667 FW_EQ_CTRL_CMD = 0x13,
668 FW_EQ_OFLD_CMD = 0x21,
669 FW_VI_CMD = 0x14,
670 FW_VI_MAC_CMD = 0x15,
671 FW_VI_RXMODE_CMD = 0x16,
672 FW_VI_ENABLE_CMD = 0x17,
673 FW_ACL_MAC_CMD = 0x18,
674 FW_ACL_VLAN_CMD = 0x19,
675 FW_VI_STATS_CMD = 0x1a,
676 FW_PORT_CMD = 0x1b,
677 FW_PORT_STATS_CMD = 0x1c,
678 FW_PORT_LB_STATS_CMD = 0x1d,
679 FW_PORT_TRACE_CMD = 0x1e,
680 FW_PORT_TRACE_MMAP_CMD = 0x1f,
681 FW_RSS_IND_TBL_CMD = 0x20,
682 FW_RSS_GLB_CONFIG_CMD = 0x22,
683 FW_RSS_VI_CONFIG_CMD = 0x23,
684 FW_SCHED_CMD = 0x24,
685 FW_DEVLOG_CMD = 0x25,
686 FW_CLIP_CMD = 0x28,
687 FW_LASTC2E_CMD = 0x40,
688 FW_ERROR_CMD = 0x80,
689 FW_DEBUG_CMD = 0x81,
690 };
691
692 enum fw_cmd_cap {
693 FW_CMD_CAP_PF = 0x01,
694 FW_CMD_CAP_DMAQ = 0x02,
695 FW_CMD_CAP_PORT = 0x04,
696 FW_CMD_CAP_PORTPROMISC = 0x08,
697 FW_CMD_CAP_PORTSTATS = 0x10,
698 FW_CMD_CAP_VF = 0x80,
699 };
700
701 /*
702 * Generic command header flit0
703 */
704 struct fw_cmd_hdr {
705 __be32 hi;
706 __be32 lo;
707 };
708
709 #define FW_CMD_OP_S 24
710 #define FW_CMD_OP_M 0xff
711 #define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S)
712 #define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
713
714 #define FW_CMD_REQUEST_S 23
715 #define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S)
716 #define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U)
717
718 #define FW_CMD_READ_S 22
719 #define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S)
720 #define FW_CMD_READ_F FW_CMD_READ_V(1U)
721
722 #define FW_CMD_WRITE_S 21
723 #define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S)
724 #define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U)
725
726 #define FW_CMD_EXEC_S 20
727 #define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S)
728 #define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U)
729
730 #define FW_CMD_RAMASK_S 20
731 #define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S)
732
733 #define FW_CMD_RETVAL_S 8
734 #define FW_CMD_RETVAL_M 0xff
735 #define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S)
736 #define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
737
738 #define FW_CMD_LEN16_S 0
739 #define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S)
740
741 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
742
743 enum fw_ldst_addrspc {
744 FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
745 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008,
746 FW_LDST_ADDRSPC_SGE_INGC = 0x0009,
747 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a,
748 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
749 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
750 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
751 FW_LDST_ADDRSPC_TP_MIB = 0x0012,
752 FW_LDST_ADDRSPC_MDIO = 0x0018,
753 FW_LDST_ADDRSPC_MPS = 0x0020,
754 FW_LDST_ADDRSPC_FUNC = 0x0028,
755 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
756 };
757
758 enum fw_ldst_mps_fid {
759 FW_LDST_MPS_ATRB,
760 FW_LDST_MPS_RPLC
761 };
762
763 enum fw_ldst_func_access_ctl {
764 FW_LDST_FUNC_ACC_CTL_VIID,
765 FW_LDST_FUNC_ACC_CTL_FID
766 };
767
768 enum fw_ldst_func_mod_index {
769 FW_LDST_FUNC_MPS
770 };
771
772 struct fw_ldst_cmd {
773 __be32 op_to_addrspace;
774 __be32 cycles_to_len16;
775 union fw_ldst {
776 struct fw_ldst_addrval {
777 __be32 addr;
778 __be32 val;
779 } addrval;
780 struct fw_ldst_idctxt {
781 __be32 physid;
782 __be32 msg_ctxtflush;
783 __be32 ctxt_data7;
784 __be32 ctxt_data6;
785 __be32 ctxt_data5;
786 __be32 ctxt_data4;
787 __be32 ctxt_data3;
788 __be32 ctxt_data2;
789 __be32 ctxt_data1;
790 __be32 ctxt_data0;
791 } idctxt;
792 struct fw_ldst_mdio {
793 __be16 paddr_mmd;
794 __be16 raddr;
795 __be16 vctl;
796 __be16 rval;
797 } mdio;
798 struct fw_ldst_cim_rq {
799 u8 req_first64[8];
800 u8 req_second64[8];
801 u8 resp_first64[8];
802 u8 resp_second64[8];
803 __be32 r3[2];
804 } cim_rq;
805 union fw_ldst_mps {
806 struct fw_ldst_mps_rplc {
807 __be16 fid_idx;
808 __be16 rplcpf_pkd;
809 __be32 rplc255_224;
810 __be32 rplc223_192;
811 __be32 rplc191_160;
812 __be32 rplc159_128;
813 __be32 rplc127_96;
814 __be32 rplc95_64;
815 __be32 rplc63_32;
816 __be32 rplc31_0;
817 } rplc;
818 struct fw_ldst_mps_atrb {
819 __be16 fid_mpsid;
820 __be16 r2[3];
821 __be32 r3[2];
822 __be32 r4;
823 __be32 atrb;
824 __be16 vlan[16];
825 } atrb;
826 } mps;
827 struct fw_ldst_func {
828 u8 access_ctl;
829 u8 mod_index;
830 __be16 ctl_id;
831 __be32 offset;
832 __be64 data0;
833 __be64 data1;
834 } func;
835 struct fw_ldst_pcie {
836 u8 ctrl_to_fn;
837 u8 bnum;
838 u8 r;
839 u8 ext_r;
840 u8 select_naccess;
841 u8 pcie_fn;
842 __be16 nset_pkd;
843 __be32 data[12];
844 } pcie;
845 struct fw_ldst_i2c_deprecated {
846 u8 pid_pkd;
847 u8 base;
848 u8 boffset;
849 u8 data;
850 __be32 r9;
851 } i2c_deprecated;
852 struct fw_ldst_i2c {
853 u8 pid;
854 u8 did;
855 u8 boffset;
856 u8 blen;
857 __be32 r9;
858 __u8 data[48];
859 } i2c;
860 struct fw_ldst_le {
861 __be32 index;
862 __be32 r9;
863 u8 val[33];
864 u8 r11[7];
865 } le;
866 } u;
867 };
868
869 #define FW_LDST_CMD_ADDRSPACE_S 0
870 #define FW_LDST_CMD_ADDRSPACE_V(x) ((x) << FW_LDST_CMD_ADDRSPACE_S)
871
872 #define FW_LDST_CMD_MSG_S 31
873 #define FW_LDST_CMD_MSG_V(x) ((x) << FW_LDST_CMD_MSG_S)
874
875 #define FW_LDST_CMD_CTXTFLUSH_S 30
876 #define FW_LDST_CMD_CTXTFLUSH_V(x) ((x) << FW_LDST_CMD_CTXTFLUSH_S)
877 #define FW_LDST_CMD_CTXTFLUSH_F FW_LDST_CMD_CTXTFLUSH_V(1U)
878
879 #define FW_LDST_CMD_PADDR_S 8
880 #define FW_LDST_CMD_PADDR_V(x) ((x) << FW_LDST_CMD_PADDR_S)
881
882 #define FW_LDST_CMD_MMD_S 0
883 #define FW_LDST_CMD_MMD_V(x) ((x) << FW_LDST_CMD_MMD_S)
884
885 #define FW_LDST_CMD_FID_S 15
886 #define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S)
887
888 #define FW_LDST_CMD_IDX_S 0
889 #define FW_LDST_CMD_IDX_V(x) ((x) << FW_LDST_CMD_IDX_S)
890
891 #define FW_LDST_CMD_RPLCPF_S 0
892 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)
893
894 #define FW_LDST_CMD_LC_S 4
895 #define FW_LDST_CMD_LC_V(x) ((x) << FW_LDST_CMD_LC_S)
896 #define FW_LDST_CMD_LC_F FW_LDST_CMD_LC_V(1U)
897
898 #define FW_LDST_CMD_FN_S 0
899 #define FW_LDST_CMD_FN_V(x) ((x) << FW_LDST_CMD_FN_S)
900
901 #define FW_LDST_CMD_NACCESS_S 0
902 #define FW_LDST_CMD_NACCESS_V(x) ((x) << FW_LDST_CMD_NACCESS_S)
903
904 struct fw_reset_cmd {
905 __be32 op_to_write;
906 __be32 retval_len16;
907 __be32 val;
908 __be32 halt_pkd;
909 };
910
911 #define FW_RESET_CMD_HALT_S 31
912 #define FW_RESET_CMD_HALT_M 0x1
913 #define FW_RESET_CMD_HALT_V(x) ((x) << FW_RESET_CMD_HALT_S)
914 #define FW_RESET_CMD_HALT_G(x) \
915 (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M)
916 #define FW_RESET_CMD_HALT_F FW_RESET_CMD_HALT_V(1U)
917
918 enum fw_hellow_cmd {
919 fw_hello_cmd_stage_os = 0x0
920 };
921
922 struct fw_hello_cmd {
923 __be32 op_to_write;
924 __be32 retval_len16;
925 __be32 err_to_clearinit;
926 __be32 fwrev;
927 };
928
929 #define FW_HELLO_CMD_ERR_S 31
930 #define FW_HELLO_CMD_ERR_V(x) ((x) << FW_HELLO_CMD_ERR_S)
931 #define FW_HELLO_CMD_ERR_F FW_HELLO_CMD_ERR_V(1U)
932
933 #define FW_HELLO_CMD_INIT_S 30
934 #define FW_HELLO_CMD_INIT_V(x) ((x) << FW_HELLO_CMD_INIT_S)
935 #define FW_HELLO_CMD_INIT_F FW_HELLO_CMD_INIT_V(1U)
936
937 #define FW_HELLO_CMD_MASTERDIS_S 29
938 #define FW_HELLO_CMD_MASTERDIS_V(x) ((x) << FW_HELLO_CMD_MASTERDIS_S)
939
940 #define FW_HELLO_CMD_MASTERFORCE_S 28
941 #define FW_HELLO_CMD_MASTERFORCE_V(x) ((x) << FW_HELLO_CMD_MASTERFORCE_S)
942
943 #define FW_HELLO_CMD_MBMASTER_S 24
944 #define FW_HELLO_CMD_MBMASTER_M 0xfU
945 #define FW_HELLO_CMD_MBMASTER_V(x) ((x) << FW_HELLO_CMD_MBMASTER_S)
946 #define FW_HELLO_CMD_MBMASTER_G(x) \
947 (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M)
948
949 #define FW_HELLO_CMD_MBASYNCNOTINT_S 23
950 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)
951
952 #define FW_HELLO_CMD_MBASYNCNOT_S 20
953 #define FW_HELLO_CMD_MBASYNCNOT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOT_S)
954
955 #define FW_HELLO_CMD_STAGE_S 17
956 #define FW_HELLO_CMD_STAGE_V(x) ((x) << FW_HELLO_CMD_STAGE_S)
957
958 #define FW_HELLO_CMD_CLEARINIT_S 16
959 #define FW_HELLO_CMD_CLEARINIT_V(x) ((x) << FW_HELLO_CMD_CLEARINIT_S)
960 #define FW_HELLO_CMD_CLEARINIT_F FW_HELLO_CMD_CLEARINIT_V(1U)
961
962 struct fw_bye_cmd {
963 __be32 op_to_write;
964 __be32 retval_len16;
965 __be64 r3;
966 };
967
968 struct fw_initialize_cmd {
969 __be32 op_to_write;
970 __be32 retval_len16;
971 __be64 r3;
972 };
973
974 enum fw_caps_config_hm {
975 FW_CAPS_CONFIG_HM_PCIE = 0x00000001,
976 FW_CAPS_CONFIG_HM_PL = 0x00000002,
977 FW_CAPS_CONFIG_HM_SGE = 0x00000004,
978 FW_CAPS_CONFIG_HM_CIM = 0x00000008,
979 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010,
980 FW_CAPS_CONFIG_HM_TP = 0x00000020,
981 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040,
982 FW_CAPS_CONFIG_HM_PMRX = 0x00000080,
983 FW_CAPS_CONFIG_HM_PMTX = 0x00000100,
984 FW_CAPS_CONFIG_HM_MC = 0x00000200,
985 FW_CAPS_CONFIG_HM_LE = 0x00000400,
986 FW_CAPS_CONFIG_HM_MPS = 0x00000800,
987 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000,
988 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000,
989 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000,
990 FW_CAPS_CONFIG_HM_MI = 0x00008000,
991 FW_CAPS_CONFIG_HM_I2CM = 0x00010000,
992 FW_CAPS_CONFIG_HM_NCSI = 0x00020000,
993 FW_CAPS_CONFIG_HM_SMB = 0x00040000,
994 FW_CAPS_CONFIG_HM_MA = 0x00080000,
995 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000,
996 FW_CAPS_CONFIG_HM_PMU = 0x00200000,
997 FW_CAPS_CONFIG_HM_UART = 0x00400000,
998 FW_CAPS_CONFIG_HM_SF = 0x00800000,
999 };
1000
1001 enum fw_caps_config_nbm {
1002 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001,
1003 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002,
1004 };
1005
1006 enum fw_caps_config_link {
1007 FW_CAPS_CONFIG_LINK_PPP = 0x00000001,
1008 FW_CAPS_CONFIG_LINK_QFC = 0x00000002,
1009 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004,
1010 };
1011
1012 enum fw_caps_config_switch {
1013 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001,
1014 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002,
1015 };
1016
1017 enum fw_caps_config_nic {
1018 FW_CAPS_CONFIG_NIC = 0x00000001,
1019 FW_CAPS_CONFIG_NIC_VM = 0x00000002,
1020 };
1021
1022 enum fw_caps_config_ofld {
1023 FW_CAPS_CONFIG_OFLD = 0x00000001,
1024 };
1025
1026 enum fw_caps_config_rdma {
1027 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001,
1028 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002,
1029 };
1030
1031 enum fw_caps_config_iscsi {
1032 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
1033 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
1034 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
1035 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
1036 };
1037
1038 enum fw_caps_config_fcoe {
1039 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
1040 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
1041 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004,
1042 };
1043
1044 enum fw_memtype_cf {
1045 FW_MEMTYPE_CF_EDC0 = 0x0,
1046 FW_MEMTYPE_CF_EDC1 = 0x1,
1047 FW_MEMTYPE_CF_EXTMEM = 0x2,
1048 FW_MEMTYPE_CF_FLASH = 0x4,
1049 FW_MEMTYPE_CF_INTERNAL = 0x5,
1050 FW_MEMTYPE_CF_EXTMEM1 = 0x6,
1051 };
1052
1053 struct fw_caps_config_cmd {
1054 __be32 op_to_write;
1055 __be32 cfvalid_to_len16;
1056 __be32 r2;
1057 __be32 hwmbitmap;
1058 __be16 nbmcaps;
1059 __be16 linkcaps;
1060 __be16 switchcaps;
1061 __be16 r3;
1062 __be16 niccaps;
1063 __be16 ofldcaps;
1064 __be16 rdmacaps;
1065 __be16 cryptocaps;
1066 __be16 iscsicaps;
1067 __be16 fcoecaps;
1068 __be32 cfcsum;
1069 __be32 finiver;
1070 __be32 finicsum;
1071 };
1072
1073 #define FW_CAPS_CONFIG_CMD_CFVALID_S 27
1074 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)
1075 #define FW_CAPS_CONFIG_CMD_CFVALID_F FW_CAPS_CONFIG_CMD_CFVALID_V(1U)
1076
1077 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S 24
1078 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x) \
1079 ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S)
1080
1081 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S 16
1082 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x) \
1083 ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S)
1084
1085 /*
1086 * params command mnemonics
1087 */
1088 enum fw_params_mnem {
1089 FW_PARAMS_MNEM_DEV = 1, /* device params */
1090 FW_PARAMS_MNEM_PFVF = 2, /* function params */
1091 FW_PARAMS_MNEM_REG = 3, /* limited register access */
1092 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
1093 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */
1094 FW_PARAMS_MNEM_LAST
1095 };
1096
1097 /*
1098 * device parameters
1099 */
1100 enum fw_params_param_dev {
1101 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
1102 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
1103 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
1104 * allocated by the device's
1105 * Lookup Engine
1106 */
1107 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
1108 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04,
1109 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
1110 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
1111 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07,
1112 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
1113 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
1114 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
1115 FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
1116 FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
1117 FW_PARAMS_PARAM_DEV_CF = 0x0D,
1118 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
1119 FW_PARAMS_PARAM_DEV_DIAG = 0x11,
1120 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
1121 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
1122 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
1123 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
1124 };
1125
1126 /*
1127 * physical and virtual function parameters
1128 */
1129 enum fw_params_param_pfvf {
1130 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
1131 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
1132 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
1133 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
1134 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
1135 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
1136 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
1137 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
1138 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
1139 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
1140 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
1141 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
1142 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
1143 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
1144 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
1145 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
1146 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10,
1147 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
1148 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12,
1149 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
1150 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
1151 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
1152 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16,
1153 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17,
1154 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18,
1155 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
1156 FW_PARAMS_PARAM_PFVF_VIID = 0x24,
1157 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25,
1158 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26,
1159 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27,
1160 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28,
1161 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
1162 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
1163 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B,
1164 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C,
1165 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
1166 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
1167 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
1168 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
1169 };
1170
1171 /*
1172 * dma queue parameters
1173 */
1174 enum fw_params_param_dmaq {
1175 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
1176 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
1177 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
1178 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
1179 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
1180 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1181 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
1182 };
1183
1184 enum fw_params_param_dev_phyfw {
1185 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
1186 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
1187 };
1188
1189 enum fw_params_param_dev_diag {
1190 FW_PARAM_DEV_DIAG_TMP = 0x00,
1191 FW_PARAM_DEV_DIAG_VDD = 0x01,
1192 };
1193
1194 enum fw_params_param_dev_fwcache {
1195 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00,
1196 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01,
1197 };
1198
1199 #define FW_PARAMS_MNEM_S 24
1200 #define FW_PARAMS_MNEM_V(x) ((x) << FW_PARAMS_MNEM_S)
1201
1202 #define FW_PARAMS_PARAM_X_S 16
1203 #define FW_PARAMS_PARAM_X_V(x) ((x) << FW_PARAMS_PARAM_X_S)
1204
1205 #define FW_PARAMS_PARAM_Y_S 8
1206 #define FW_PARAMS_PARAM_Y_M 0xffU
1207 #define FW_PARAMS_PARAM_Y_V(x) ((x) << FW_PARAMS_PARAM_Y_S)
1208 #define FW_PARAMS_PARAM_Y_G(x) (((x) >> FW_PARAMS_PARAM_Y_S) &\
1209 FW_PARAMS_PARAM_Y_M)
1210
1211 #define FW_PARAMS_PARAM_Z_S 0
1212 #define FW_PARAMS_PARAM_Z_M 0xffu
1213 #define FW_PARAMS_PARAM_Z_V(x) ((x) << FW_PARAMS_PARAM_Z_S)
1214 #define FW_PARAMS_PARAM_Z_G(x) (((x) >> FW_PARAMS_PARAM_Z_S) &\
1215 FW_PARAMS_PARAM_Z_M)
1216
1217 #define FW_PARAMS_PARAM_XYZ_S 0
1218 #define FW_PARAMS_PARAM_XYZ_V(x) ((x) << FW_PARAMS_PARAM_XYZ_S)
1219
1220 #define FW_PARAMS_PARAM_YZ_S 0
1221 #define FW_PARAMS_PARAM_YZ_V(x) ((x) << FW_PARAMS_PARAM_YZ_S)
1222
1223 struct fw_params_cmd {
1224 __be32 op_to_vfn;
1225 __be32 retval_len16;
1226 struct fw_params_param {
1227 __be32 mnem;
1228 __be32 val;
1229 } param[7];
1230 };
1231
1232 #define FW_PARAMS_CMD_PFN_S 8
1233 #define FW_PARAMS_CMD_PFN_V(x) ((x) << FW_PARAMS_CMD_PFN_S)
1234
1235 #define FW_PARAMS_CMD_VFN_S 0
1236 #define FW_PARAMS_CMD_VFN_V(x) ((x) << FW_PARAMS_CMD_VFN_S)
1237
1238 struct fw_pfvf_cmd {
1239 __be32 op_to_vfn;
1240 __be32 retval_len16;
1241 __be32 niqflint_niq;
1242 __be32 type_to_neq;
1243 __be32 tc_to_nexactf;
1244 __be32 r_caps_to_nethctrl;
1245 __be16 nricq;
1246 __be16 nriqp;
1247 __be32 r4;
1248 };
1249
1250 #define FW_PFVF_CMD_PFN_S 8
1251 #define FW_PFVF_CMD_PFN_V(x) ((x) << FW_PFVF_CMD_PFN_S)
1252
1253 #define FW_PFVF_CMD_VFN_S 0
1254 #define FW_PFVF_CMD_VFN_V(x) ((x) << FW_PFVF_CMD_VFN_S)
1255
1256 #define FW_PFVF_CMD_NIQFLINT_S 20
1257 #define FW_PFVF_CMD_NIQFLINT_M 0xfff
1258 #define FW_PFVF_CMD_NIQFLINT_V(x) ((x) << FW_PFVF_CMD_NIQFLINT_S)
1259 #define FW_PFVF_CMD_NIQFLINT_G(x) \
1260 (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M)
1261
1262 #define FW_PFVF_CMD_NIQ_S 0
1263 #define FW_PFVF_CMD_NIQ_M 0xfffff
1264 #define FW_PFVF_CMD_NIQ_V(x) ((x) << FW_PFVF_CMD_NIQ_S)
1265 #define FW_PFVF_CMD_NIQ_G(x) \
1266 (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M)
1267
1268 #define FW_PFVF_CMD_TYPE_S 31
1269 #define FW_PFVF_CMD_TYPE_M 0x1
1270 #define FW_PFVF_CMD_TYPE_V(x) ((x) << FW_PFVF_CMD_TYPE_S)
1271 #define FW_PFVF_CMD_TYPE_G(x) \
1272 (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M)
1273 #define FW_PFVF_CMD_TYPE_F FW_PFVF_CMD_TYPE_V(1U)
1274
1275 #define FW_PFVF_CMD_CMASK_S 24
1276 #define FW_PFVF_CMD_CMASK_M 0xf
1277 #define FW_PFVF_CMD_CMASK_V(x) ((x) << FW_PFVF_CMD_CMASK_S)
1278 #define FW_PFVF_CMD_CMASK_G(x) \
1279 (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M)
1280
1281 #define FW_PFVF_CMD_PMASK_S 20
1282 #define FW_PFVF_CMD_PMASK_M 0xf
1283 #define FW_PFVF_CMD_PMASK_V(x) ((x) << FW_PFVF_CMD_PMASK_S)
1284 #define FW_PFVF_CMD_PMASK_G(x) \
1285 (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M)
1286
1287 #define FW_PFVF_CMD_NEQ_S 0
1288 #define FW_PFVF_CMD_NEQ_M 0xfffff
1289 #define FW_PFVF_CMD_NEQ_V(x) ((x) << FW_PFVF_CMD_NEQ_S)
1290 #define FW_PFVF_CMD_NEQ_G(x) \
1291 (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M)
1292
1293 #define FW_PFVF_CMD_TC_S 24
1294 #define FW_PFVF_CMD_TC_M 0xff
1295 #define FW_PFVF_CMD_TC_V(x) ((x) << FW_PFVF_CMD_TC_S)
1296 #define FW_PFVF_CMD_TC_G(x) (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)
1297
1298 #define FW_PFVF_CMD_NVI_S 16
1299 #define FW_PFVF_CMD_NVI_M 0xff
1300 #define FW_PFVF_CMD_NVI_V(x) ((x) << FW_PFVF_CMD_NVI_S)
1301 #define FW_PFVF_CMD_NVI_G(x) (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)
1302
1303 #define FW_PFVF_CMD_NEXACTF_S 0
1304 #define FW_PFVF_CMD_NEXACTF_M 0xffff
1305 #define FW_PFVF_CMD_NEXACTF_V(x) ((x) << FW_PFVF_CMD_NEXACTF_S)
1306 #define FW_PFVF_CMD_NEXACTF_G(x) \
1307 (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M)
1308
1309 #define FW_PFVF_CMD_R_CAPS_S 24
1310 #define FW_PFVF_CMD_R_CAPS_M 0xff
1311 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)
1312 #define FW_PFVF_CMD_R_CAPS_G(x) \
1313 (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M)
1314
1315 #define FW_PFVF_CMD_WX_CAPS_S 16
1316 #define FW_PFVF_CMD_WX_CAPS_M 0xff
1317 #define FW_PFVF_CMD_WX_CAPS_V(x) ((x) << FW_PFVF_CMD_WX_CAPS_S)
1318 #define FW_PFVF_CMD_WX_CAPS_G(x) \
1319 (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M)
1320
1321 #define FW_PFVF_CMD_NETHCTRL_S 0
1322 #define FW_PFVF_CMD_NETHCTRL_M 0xffff
1323 #define FW_PFVF_CMD_NETHCTRL_V(x) ((x) << FW_PFVF_CMD_NETHCTRL_S)
1324 #define FW_PFVF_CMD_NETHCTRL_G(x) \
1325 (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M)
1326
1327 enum fw_iq_type {
1328 FW_IQ_TYPE_FL_INT_CAP,
1329 FW_IQ_TYPE_NO_FL_INT_CAP
1330 };
1331
1332 struct fw_iq_cmd {
1333 __be32 op_to_vfn;
1334 __be32 alloc_to_len16;
1335 __be16 physiqid;
1336 __be16 iqid;
1337 __be16 fl0id;
1338 __be16 fl1id;
1339 __be32 type_to_iqandstindex;
1340 __be16 iqdroprss_to_iqesize;
1341 __be16 iqsize;
1342 __be64 iqaddr;
1343 __be32 iqns_to_fl0congen;
1344 __be16 fl0dcaen_to_fl0cidxfthresh;
1345 __be16 fl0size;
1346 __be64 fl0addr;
1347 __be32 fl1cngchmap_to_fl1congen;
1348 __be16 fl1dcaen_to_fl1cidxfthresh;
1349 __be16 fl1size;
1350 __be64 fl1addr;
1351 };
1352
1353 #define FW_IQ_CMD_PFN_S 8
1354 #define FW_IQ_CMD_PFN_V(x) ((x) << FW_IQ_CMD_PFN_S)
1355
1356 #define FW_IQ_CMD_VFN_S 0
1357 #define FW_IQ_CMD_VFN_V(x) ((x) << FW_IQ_CMD_VFN_S)
1358
1359 #define FW_IQ_CMD_ALLOC_S 31
1360 #define FW_IQ_CMD_ALLOC_V(x) ((x) << FW_IQ_CMD_ALLOC_S)
1361 #define FW_IQ_CMD_ALLOC_F FW_IQ_CMD_ALLOC_V(1U)
1362
1363 #define FW_IQ_CMD_FREE_S 30
1364 #define FW_IQ_CMD_FREE_V(x) ((x) << FW_IQ_CMD_FREE_S)
1365 #define FW_IQ_CMD_FREE_F FW_IQ_CMD_FREE_V(1U)
1366
1367 #define FW_IQ_CMD_MODIFY_S 29
1368 #define FW_IQ_CMD_MODIFY_V(x) ((x) << FW_IQ_CMD_MODIFY_S)
1369 #define FW_IQ_CMD_MODIFY_F FW_IQ_CMD_MODIFY_V(1U)
1370
1371 #define FW_IQ_CMD_IQSTART_S 28
1372 #define FW_IQ_CMD_IQSTART_V(x) ((x) << FW_IQ_CMD_IQSTART_S)
1373 #define FW_IQ_CMD_IQSTART_F FW_IQ_CMD_IQSTART_V(1U)
1374
1375 #define FW_IQ_CMD_IQSTOP_S 27
1376 #define FW_IQ_CMD_IQSTOP_V(x) ((x) << FW_IQ_CMD_IQSTOP_S)
1377 #define FW_IQ_CMD_IQSTOP_F FW_IQ_CMD_IQSTOP_V(1U)
1378
1379 #define FW_IQ_CMD_TYPE_S 29
1380 #define FW_IQ_CMD_TYPE_V(x) ((x) << FW_IQ_CMD_TYPE_S)
1381
1382 #define FW_IQ_CMD_IQASYNCH_S 28
1383 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S)
1384
1385 #define FW_IQ_CMD_VIID_S 16
1386 #define FW_IQ_CMD_VIID_V(x) ((x) << FW_IQ_CMD_VIID_S)
1387
1388 #define FW_IQ_CMD_IQANDST_S 15
1389 #define FW_IQ_CMD_IQANDST_V(x) ((x) << FW_IQ_CMD_IQANDST_S)
1390
1391 #define FW_IQ_CMD_IQANUS_S 14
1392 #define FW_IQ_CMD_IQANUS_V(x) ((x) << FW_IQ_CMD_IQANUS_S)
1393
1394 #define FW_IQ_CMD_IQANUD_S 12
1395 #define FW_IQ_CMD_IQANUD_V(x) ((x) << FW_IQ_CMD_IQANUD_S)
1396
1397 #define FW_IQ_CMD_IQANDSTINDEX_S 0
1398 #define FW_IQ_CMD_IQANDSTINDEX_V(x) ((x) << FW_IQ_CMD_IQANDSTINDEX_S)
1399
1400 #define FW_IQ_CMD_IQDROPRSS_S 15
1401 #define FW_IQ_CMD_IQDROPRSS_V(x) ((x) << FW_IQ_CMD_IQDROPRSS_S)
1402 #define FW_IQ_CMD_IQDROPRSS_F FW_IQ_CMD_IQDROPRSS_V(1U)
1403
1404 #define FW_IQ_CMD_IQGTSMODE_S 14
1405 #define FW_IQ_CMD_IQGTSMODE_V(x) ((x) << FW_IQ_CMD_IQGTSMODE_S)
1406 #define FW_IQ_CMD_IQGTSMODE_F FW_IQ_CMD_IQGTSMODE_V(1U)
1407
1408 #define FW_IQ_CMD_IQPCIECH_S 12
1409 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S)
1410
1411 #define FW_IQ_CMD_IQDCAEN_S 11
1412 #define FW_IQ_CMD_IQDCAEN_V(x) ((x) << FW_IQ_CMD_IQDCAEN_S)
1413
1414 #define FW_IQ_CMD_IQDCACPU_S 6
1415 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S)
1416
1417 #define FW_IQ_CMD_IQINTCNTTHRESH_S 4
1418 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x) ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)
1419
1420 #define FW_IQ_CMD_IQO_S 3
1421 #define FW_IQ_CMD_IQO_V(x) ((x) << FW_IQ_CMD_IQO_S)
1422 #define FW_IQ_CMD_IQO_F FW_IQ_CMD_IQO_V(1U)
1423
1424 #define FW_IQ_CMD_IQCPRIO_S 2
1425 #define FW_IQ_CMD_IQCPRIO_V(x) ((x) << FW_IQ_CMD_IQCPRIO_S)
1426
1427 #define FW_IQ_CMD_IQESIZE_S 0
1428 #define FW_IQ_CMD_IQESIZE_V(x) ((x) << FW_IQ_CMD_IQESIZE_S)
1429
1430 #define FW_IQ_CMD_IQNS_S 31
1431 #define FW_IQ_CMD_IQNS_V(x) ((x) << FW_IQ_CMD_IQNS_S)
1432
1433 #define FW_IQ_CMD_IQRO_S 30
1434 #define FW_IQ_CMD_IQRO_V(x) ((x) << FW_IQ_CMD_IQRO_S)
1435
1436 #define FW_IQ_CMD_IQFLINTIQHSEN_S 28
1437 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x) ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)
1438
1439 #define FW_IQ_CMD_IQFLINTCONGEN_S 27
1440 #define FW_IQ_CMD_IQFLINTCONGEN_V(x) ((x) << FW_IQ_CMD_IQFLINTCONGEN_S)
1441 #define FW_IQ_CMD_IQFLINTCONGEN_F FW_IQ_CMD_IQFLINTCONGEN_V(1U)
1442
1443 #define FW_IQ_CMD_IQFLINTISCSIC_S 26
1444 #define FW_IQ_CMD_IQFLINTISCSIC_V(x) ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
1445
1446 #define FW_IQ_CMD_FL0CNGCHMAP_S 20
1447 #define FW_IQ_CMD_FL0CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL0CNGCHMAP_S)
1448
1449 #define FW_IQ_CMD_FL0CACHELOCK_S 15
1450 #define FW_IQ_CMD_FL0CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL0CACHELOCK_S)
1451
1452 #define FW_IQ_CMD_FL0DBP_S 14
1453 #define FW_IQ_CMD_FL0DBP_V(x) ((x) << FW_IQ_CMD_FL0DBP_S)
1454
1455 #define FW_IQ_CMD_FL0DATANS_S 13
1456 #define FW_IQ_CMD_FL0DATANS_V(x) ((x) << FW_IQ_CMD_FL0DATANS_S)
1457
1458 #define FW_IQ_CMD_FL0DATARO_S 12
1459 #define FW_IQ_CMD_FL0DATARO_V(x) ((x) << FW_IQ_CMD_FL0DATARO_S)
1460 #define FW_IQ_CMD_FL0DATARO_F FW_IQ_CMD_FL0DATARO_V(1U)
1461
1462 #define FW_IQ_CMD_FL0CONGCIF_S 11
1463 #define FW_IQ_CMD_FL0CONGCIF_V(x) ((x) << FW_IQ_CMD_FL0CONGCIF_S)
1464 #define FW_IQ_CMD_FL0CONGCIF_F FW_IQ_CMD_FL0CONGCIF_V(1U)
1465
1466 #define FW_IQ_CMD_FL0ONCHIP_S 10
1467 #define FW_IQ_CMD_FL0ONCHIP_V(x) ((x) << FW_IQ_CMD_FL0ONCHIP_S)
1468
1469 #define FW_IQ_CMD_FL0STATUSPGNS_S 9
1470 #define FW_IQ_CMD_FL0STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGNS_S)
1471
1472 #define FW_IQ_CMD_FL0STATUSPGRO_S 8
1473 #define FW_IQ_CMD_FL0STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGRO_S)
1474
1475 #define FW_IQ_CMD_FL0FETCHNS_S 7
1476 #define FW_IQ_CMD_FL0FETCHNS_V(x) ((x) << FW_IQ_CMD_FL0FETCHNS_S)
1477
1478 #define FW_IQ_CMD_FL0FETCHRO_S 6
1479 #define FW_IQ_CMD_FL0FETCHRO_V(x) ((x) << FW_IQ_CMD_FL0FETCHRO_S)
1480 #define FW_IQ_CMD_FL0FETCHRO_F FW_IQ_CMD_FL0FETCHRO_V(1U)
1481
1482 #define FW_IQ_CMD_FL0HOSTFCMODE_S 4
1483 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)
1484
1485 #define FW_IQ_CMD_FL0CPRIO_S 3
1486 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S)
1487
1488 #define FW_IQ_CMD_FL0PADEN_S 2
1489 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S)
1490 #define FW_IQ_CMD_FL0PADEN_F FW_IQ_CMD_FL0PADEN_V(1U)
1491
1492 #define FW_IQ_CMD_FL0PACKEN_S 1
1493 #define FW_IQ_CMD_FL0PACKEN_V(x) ((x) << FW_IQ_CMD_FL0PACKEN_S)
1494 #define FW_IQ_CMD_FL0PACKEN_F FW_IQ_CMD_FL0PACKEN_V(1U)
1495
1496 #define FW_IQ_CMD_FL0CONGEN_S 0
1497 #define FW_IQ_CMD_FL0CONGEN_V(x) ((x) << FW_IQ_CMD_FL0CONGEN_S)
1498 #define FW_IQ_CMD_FL0CONGEN_F FW_IQ_CMD_FL0CONGEN_V(1U)
1499
1500 #define FW_IQ_CMD_FL0DCAEN_S 15
1501 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S)
1502
1503 #define FW_IQ_CMD_FL0DCACPU_S 10
1504 #define FW_IQ_CMD_FL0DCACPU_V(x) ((x) << FW_IQ_CMD_FL0DCACPU_S)
1505
1506 #define FW_IQ_CMD_FL0FBMIN_S 7
1507 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S)
1508
1509 #define FW_IQ_CMD_FL0FBMAX_S 4
1510 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S)
1511
1512 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S 3
1513 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)
1514 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U)
1515
1516 #define FW_IQ_CMD_FL0CIDXFTHRESH_S 0
1517 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)
1518
1519 #define FW_IQ_CMD_FL1CNGCHMAP_S 20
1520 #define FW_IQ_CMD_FL1CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL1CNGCHMAP_S)
1521
1522 #define FW_IQ_CMD_FL1CACHELOCK_S 15
1523 #define FW_IQ_CMD_FL1CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL1CACHELOCK_S)
1524
1525 #define FW_IQ_CMD_FL1DBP_S 14
1526 #define FW_IQ_CMD_FL1DBP_V(x) ((x) << FW_IQ_CMD_FL1DBP_S)
1527
1528 #define FW_IQ_CMD_FL1DATANS_S 13
1529 #define FW_IQ_CMD_FL1DATANS_V(x) ((x) << FW_IQ_CMD_FL1DATANS_S)
1530
1531 #define FW_IQ_CMD_FL1DATARO_S 12
1532 #define FW_IQ_CMD_FL1DATARO_V(x) ((x) << FW_IQ_CMD_FL1DATARO_S)
1533
1534 #define FW_IQ_CMD_FL1CONGCIF_S 11
1535 #define FW_IQ_CMD_FL1CONGCIF_V(x) ((x) << FW_IQ_CMD_FL1CONGCIF_S)
1536
1537 #define FW_IQ_CMD_FL1ONCHIP_S 10
1538 #define FW_IQ_CMD_FL1ONCHIP_V(x) ((x) << FW_IQ_CMD_FL1ONCHIP_S)
1539
1540 #define FW_IQ_CMD_FL1STATUSPGNS_S 9
1541 #define FW_IQ_CMD_FL1STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGNS_S)
1542
1543 #define FW_IQ_CMD_FL1STATUSPGRO_S 8
1544 #define FW_IQ_CMD_FL1STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGRO_S)
1545
1546 #define FW_IQ_CMD_FL1FETCHNS_S 7
1547 #define FW_IQ_CMD_FL1FETCHNS_V(x) ((x) << FW_IQ_CMD_FL1FETCHNS_S)
1548
1549 #define FW_IQ_CMD_FL1FETCHRO_S 6
1550 #define FW_IQ_CMD_FL1FETCHRO_V(x) ((x) << FW_IQ_CMD_FL1FETCHRO_S)
1551
1552 #define FW_IQ_CMD_FL1HOSTFCMODE_S 4
1553 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)
1554
1555 #define FW_IQ_CMD_FL1CPRIO_S 3
1556 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S)
1557
1558 #define FW_IQ_CMD_FL1PADEN_S 2
1559 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S)
1560 #define FW_IQ_CMD_FL1PADEN_F FW_IQ_CMD_FL1PADEN_V(1U)
1561
1562 #define FW_IQ_CMD_FL1PACKEN_S 1
1563 #define FW_IQ_CMD_FL1PACKEN_V(x) ((x) << FW_IQ_CMD_FL1PACKEN_S)
1564 #define FW_IQ_CMD_FL1PACKEN_F FW_IQ_CMD_FL1PACKEN_V(1U)
1565
1566 #define FW_IQ_CMD_FL1CONGEN_S 0
1567 #define FW_IQ_CMD_FL1CONGEN_V(x) ((x) << FW_IQ_CMD_FL1CONGEN_S)
1568 #define FW_IQ_CMD_FL1CONGEN_F FW_IQ_CMD_FL1CONGEN_V(1U)
1569
1570 #define FW_IQ_CMD_FL1DCAEN_S 15
1571 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S)
1572
1573 #define FW_IQ_CMD_FL1DCACPU_S 10
1574 #define FW_IQ_CMD_FL1DCACPU_V(x) ((x) << FW_IQ_CMD_FL1DCACPU_S)
1575
1576 #define FW_IQ_CMD_FL1FBMIN_S 7
1577 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S)
1578
1579 #define FW_IQ_CMD_FL1FBMAX_S 4
1580 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S)
1581
1582 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S 3
1583 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)
1584 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U)
1585
1586 #define FW_IQ_CMD_FL1CIDXFTHRESH_S 0
1587 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)
1588
1589 struct fw_eq_eth_cmd {
1590 __be32 op_to_vfn;
1591 __be32 alloc_to_len16;
1592 __be32 eqid_pkd;
1593 __be32 physeqid_pkd;
1594 __be32 fetchszm_to_iqid;
1595 __be32 dcaen_to_eqsize;
1596 __be64 eqaddr;
1597 __be32 viid_pkd;
1598 __be32 r8_lo;
1599 __be64 r9;
1600 };
1601
1602 #define FW_EQ_ETH_CMD_PFN_S 8
1603 #define FW_EQ_ETH_CMD_PFN_V(x) ((x) << FW_EQ_ETH_CMD_PFN_S)
1604
1605 #define FW_EQ_ETH_CMD_VFN_S 0
1606 #define FW_EQ_ETH_CMD_VFN_V(x) ((x) << FW_EQ_ETH_CMD_VFN_S)
1607
1608 #define FW_EQ_ETH_CMD_ALLOC_S 31
1609 #define FW_EQ_ETH_CMD_ALLOC_V(x) ((x) << FW_EQ_ETH_CMD_ALLOC_S)
1610 #define FW_EQ_ETH_CMD_ALLOC_F FW_EQ_ETH_CMD_ALLOC_V(1U)
1611
1612 #define FW_EQ_ETH_CMD_FREE_S 30
1613 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S)
1614 #define FW_EQ_ETH_CMD_FREE_F FW_EQ_ETH_CMD_FREE_V(1U)
1615
1616 #define FW_EQ_ETH_CMD_MODIFY_S 29
1617 #define FW_EQ_ETH_CMD_MODIFY_V(x) ((x) << FW_EQ_ETH_CMD_MODIFY_S)
1618 #define FW_EQ_ETH_CMD_MODIFY_F FW_EQ_ETH_CMD_MODIFY_V(1U)
1619
1620 #define FW_EQ_ETH_CMD_EQSTART_S 28
1621 #define FW_EQ_ETH_CMD_EQSTART_V(x) ((x) << FW_EQ_ETH_CMD_EQSTART_S)
1622 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U)
1623
1624 #define FW_EQ_ETH_CMD_EQSTOP_S 27
1625 #define FW_EQ_ETH_CMD_EQSTOP_V(x) ((x) << FW_EQ_ETH_CMD_EQSTOP_S)
1626 #define FW_EQ_ETH_CMD_EQSTOP_F FW_EQ_ETH_CMD_EQSTOP_V(1U)
1627
1628 #define FW_EQ_ETH_CMD_EQID_S 0
1629 #define FW_EQ_ETH_CMD_EQID_M 0xfffff
1630 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)
1631 #define FW_EQ_ETH_CMD_EQID_G(x) \
1632 (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M)
1633
1634 #define FW_EQ_ETH_CMD_PHYSEQID_S 0
1635 #define FW_EQ_ETH_CMD_PHYSEQID_M 0xfffff
1636 #define FW_EQ_ETH_CMD_PHYSEQID_V(x) ((x) << FW_EQ_ETH_CMD_PHYSEQID_S)
1637 #define FW_EQ_ETH_CMD_PHYSEQID_G(x) \
1638 (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M)
1639
1640 #define FW_EQ_ETH_CMD_FETCHSZM_S 26
1641 #define FW_EQ_ETH_CMD_FETCHSZM_V(x) ((x) << FW_EQ_ETH_CMD_FETCHSZM_S)
1642 #define FW_EQ_ETH_CMD_FETCHSZM_F FW_EQ_ETH_CMD_FETCHSZM_V(1U)
1643
1644 #define FW_EQ_ETH_CMD_STATUSPGNS_S 25
1645 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)
1646
1647 #define FW_EQ_ETH_CMD_STATUSPGRO_S 24
1648 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)
1649
1650 #define FW_EQ_ETH_CMD_FETCHNS_S 23
1651 #define FW_EQ_ETH_CMD_FETCHNS_V(x) ((x) << FW_EQ_ETH_CMD_FETCHNS_S)
1652
1653 #define FW_EQ_ETH_CMD_FETCHRO_S 22
1654 #define FW_EQ_ETH_CMD_FETCHRO_V(x) ((x) << FW_EQ_ETH_CMD_FETCHRO_S)
1655 #define FW_EQ_ETH_CMD_FETCHRO_F FW_EQ_ETH_CMD_FETCHRO_V(1U)
1656
1657 #define FW_EQ_ETH_CMD_HOSTFCMODE_S 20
1658 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)
1659
1660 #define FW_EQ_ETH_CMD_CPRIO_S 19
1661 #define FW_EQ_ETH_CMD_CPRIO_V(x) ((x) << FW_EQ_ETH_CMD_CPRIO_S)
1662
1663 #define FW_EQ_ETH_CMD_ONCHIP_S 18
1664 #define FW_EQ_ETH_CMD_ONCHIP_V(x) ((x) << FW_EQ_ETH_CMD_ONCHIP_S)
1665
1666 #define FW_EQ_ETH_CMD_PCIECHN_S 16
1667 #define FW_EQ_ETH_CMD_PCIECHN_V(x) ((x) << FW_EQ_ETH_CMD_PCIECHN_S)
1668
1669 #define FW_EQ_ETH_CMD_IQID_S 0
1670 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S)
1671
1672 #define FW_EQ_ETH_CMD_DCAEN_S 31
1673 #define FW_EQ_ETH_CMD_DCAEN_V(x) ((x) << FW_EQ_ETH_CMD_DCAEN_S)
1674
1675 #define FW_EQ_ETH_CMD_DCACPU_S 26
1676 #define FW_EQ_ETH_CMD_DCACPU_V(x) ((x) << FW_EQ_ETH_CMD_DCACPU_S)
1677
1678 #define FW_EQ_ETH_CMD_FBMIN_S 23
1679 #define FW_EQ_ETH_CMD_FBMIN_V(x) ((x) << FW_EQ_ETH_CMD_FBMIN_S)
1680
1681 #define FW_EQ_ETH_CMD_FBMAX_S 20
1682 #define FW_EQ_ETH_CMD_FBMAX_V(x) ((x) << FW_EQ_ETH_CMD_FBMAX_S)
1683
1684 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S 19
1685 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)
1686
1687 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S 16
1688 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)
1689
1690 #define FW_EQ_ETH_CMD_EQSIZE_S 0
1691 #define FW_EQ_ETH_CMD_EQSIZE_V(x) ((x) << FW_EQ_ETH_CMD_EQSIZE_S)
1692
1693 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S 30
1694 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)
1695 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)
1696
1697 #define FW_EQ_ETH_CMD_VIID_S 16
1698 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S)
1699
1700 struct fw_eq_ctrl_cmd {
1701 __be32 op_to_vfn;
1702 __be32 alloc_to_len16;
1703 __be32 cmpliqid_eqid;
1704 __be32 physeqid_pkd;
1705 __be32 fetchszm_to_iqid;
1706 __be32 dcaen_to_eqsize;
1707 __be64 eqaddr;
1708 };
1709
1710 #define FW_EQ_CTRL_CMD_PFN_S 8
1711 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S)
1712
1713 #define FW_EQ_CTRL_CMD_VFN_S 0
1714 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S)
1715
1716 #define FW_EQ_CTRL_CMD_ALLOC_S 31
1717 #define FW_EQ_CTRL_CMD_ALLOC_V(x) ((x) << FW_EQ_CTRL_CMD_ALLOC_S)
1718 #define FW_EQ_CTRL_CMD_ALLOC_F FW_EQ_CTRL_CMD_ALLOC_V(1U)
1719
1720 #define FW_EQ_CTRL_CMD_FREE_S 30
1721 #define FW_EQ_CTRL_CMD_FREE_V(x) ((x) << FW_EQ_CTRL_CMD_FREE_S)
1722 #define FW_EQ_CTRL_CMD_FREE_F FW_EQ_CTRL_CMD_FREE_V(1U)
1723
1724 #define FW_EQ_CTRL_CMD_MODIFY_S 29
1725 #define FW_EQ_CTRL_CMD_MODIFY_V(x) ((x) << FW_EQ_CTRL_CMD_MODIFY_S)
1726 #define FW_EQ_CTRL_CMD_MODIFY_F FW_EQ_CTRL_CMD_MODIFY_V(1U)
1727
1728 #define FW_EQ_CTRL_CMD_EQSTART_S 28
1729 #define FW_EQ_CTRL_CMD_EQSTART_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTART_S)
1730 #define FW_EQ_CTRL_CMD_EQSTART_F FW_EQ_CTRL_CMD_EQSTART_V(1U)
1731
1732 #define FW_EQ_CTRL_CMD_EQSTOP_S 27
1733 #define FW_EQ_CTRL_CMD_EQSTOP_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTOP_S)
1734 #define FW_EQ_CTRL_CMD_EQSTOP_F FW_EQ_CTRL_CMD_EQSTOP_V(1U)
1735
1736 #define FW_EQ_CTRL_CMD_CMPLIQID_S 20
1737 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x) ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
1738
1739 #define FW_EQ_CTRL_CMD_EQID_S 0
1740 #define FW_EQ_CTRL_CMD_EQID_M 0xfffff
1741 #define FW_EQ_CTRL_CMD_EQID_V(x) ((x) << FW_EQ_CTRL_CMD_EQID_S)
1742 #define FW_EQ_CTRL_CMD_EQID_G(x) \
1743 (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M)
1744
1745 #define FW_EQ_CTRL_CMD_PHYSEQID_S 0
1746 #define FW_EQ_CTRL_CMD_PHYSEQID_M 0xfffff
1747 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x) \
1748 (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M)
1749
1750 #define FW_EQ_CTRL_CMD_FETCHSZM_S 26
1751 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S)
1752 #define FW_EQ_CTRL_CMD_FETCHSZM_F FW_EQ_CTRL_CMD_FETCHSZM_V(1U)
1753
1754 #define FW_EQ_CTRL_CMD_STATUSPGNS_S 25
1755 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S)
1756 #define FW_EQ_CTRL_CMD_STATUSPGNS_F FW_EQ_CTRL_CMD_STATUSPGNS_V(1U)
1757
1758 #define FW_EQ_CTRL_CMD_STATUSPGRO_S 24
1759 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S)
1760 #define FW_EQ_CTRL_CMD_STATUSPGRO_F FW_EQ_CTRL_CMD_STATUSPGRO_V(1U)
1761
1762 #define FW_EQ_CTRL_CMD_FETCHNS_S 23
1763 #define FW_EQ_CTRL_CMD_FETCHNS_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHNS_S)
1764 #define FW_EQ_CTRL_CMD_FETCHNS_F FW_EQ_CTRL_CMD_FETCHNS_V(1U)
1765
1766 #define FW_EQ_CTRL_CMD_FETCHRO_S 22
1767 #define FW_EQ_CTRL_CMD_FETCHRO_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHRO_S)
1768 #define FW_EQ_CTRL_CMD_FETCHRO_F FW_EQ_CTRL_CMD_FETCHRO_V(1U)
1769
1770 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S 20
1771 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S)
1772
1773 #define FW_EQ_CTRL_CMD_CPRIO_S 19
1774 #define FW_EQ_CTRL_CMD_CPRIO_V(x) ((x) << FW_EQ_CTRL_CMD_CPRIO_S)
1775
1776 #define FW_EQ_CTRL_CMD_ONCHIP_S 18
1777 #define FW_EQ_CTRL_CMD_ONCHIP_V(x) ((x) << FW_EQ_CTRL_CMD_ONCHIP_S)
1778
1779 #define FW_EQ_CTRL_CMD_PCIECHN_S 16
1780 #define FW_EQ_CTRL_CMD_PCIECHN_V(x) ((x) << FW_EQ_CTRL_CMD_PCIECHN_S)
1781
1782 #define FW_EQ_CTRL_CMD_IQID_S 0
1783 #define FW_EQ_CTRL_CMD_IQID_V(x) ((x) << FW_EQ_CTRL_CMD_IQID_S)
1784
1785 #define FW_EQ_CTRL_CMD_DCAEN_S 31
1786 #define FW_EQ_CTRL_CMD_DCAEN_V(x) ((x) << FW_EQ_CTRL_CMD_DCAEN_S)
1787
1788 #define FW_EQ_CTRL_CMD_DCACPU_S 26
1789 #define FW_EQ_CTRL_CMD_DCACPU_V(x) ((x) << FW_EQ_CTRL_CMD_DCACPU_S)
1790
1791 #define FW_EQ_CTRL_CMD_FBMIN_S 23
1792 #define FW_EQ_CTRL_CMD_FBMIN_V(x) ((x) << FW_EQ_CTRL_CMD_FBMIN_S)
1793
1794 #define FW_EQ_CTRL_CMD_FBMAX_S 20
1795 #define FW_EQ_CTRL_CMD_FBMAX_V(x) ((x) << FW_EQ_CTRL_CMD_FBMAX_S)
1796
1797 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S 19
1798 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x) \
1799 ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S)
1800
1801 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S 16
1802 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S)
1803
1804 #define FW_EQ_CTRL_CMD_EQSIZE_S 0
1805 #define FW_EQ_CTRL_CMD_EQSIZE_V(x) ((x) << FW_EQ_CTRL_CMD_EQSIZE_S)
1806
1807 struct fw_eq_ofld_cmd {
1808 __be32 op_to_vfn;
1809 __be32 alloc_to_len16;
1810 __be32 eqid_pkd;
1811 __be32 physeqid_pkd;
1812 __be32 fetchszm_to_iqid;
1813 __be32 dcaen_to_eqsize;
1814 __be64 eqaddr;
1815 };
1816
1817 #define FW_EQ_OFLD_CMD_PFN_S 8
1818 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S)
1819
1820 #define FW_EQ_OFLD_CMD_VFN_S 0
1821 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S)
1822
1823 #define FW_EQ_OFLD_CMD_ALLOC_S 31
1824 #define FW_EQ_OFLD_CMD_ALLOC_V(x) ((x) << FW_EQ_OFLD_CMD_ALLOC_S)
1825 #define FW_EQ_OFLD_CMD_ALLOC_F FW_EQ_OFLD_CMD_ALLOC_V(1U)
1826
1827 #define FW_EQ_OFLD_CMD_FREE_S 30
1828 #define FW_EQ_OFLD_CMD_FREE_V(x) ((x) << FW_EQ_OFLD_CMD_FREE_S)
1829 #define FW_EQ_OFLD_CMD_FREE_F FW_EQ_OFLD_CMD_FREE_V(1U)
1830
1831 #define FW_EQ_OFLD_CMD_MODIFY_S 29
1832 #define FW_EQ_OFLD_CMD_MODIFY_V(x) ((x) << FW_EQ_OFLD_CMD_MODIFY_S)
1833 #define FW_EQ_OFLD_CMD_MODIFY_F FW_EQ_OFLD_CMD_MODIFY_V(1U)
1834
1835 #define FW_EQ_OFLD_CMD_EQSTART_S 28
1836 #define FW_EQ_OFLD_CMD_EQSTART_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTART_S)
1837 #define FW_EQ_OFLD_CMD_EQSTART_F FW_EQ_OFLD_CMD_EQSTART_V(1U)
1838
1839 #define FW_EQ_OFLD_CMD_EQSTOP_S 27
1840 #define FW_EQ_OFLD_CMD_EQSTOP_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTOP_S)
1841 #define FW_EQ_OFLD_CMD_EQSTOP_F FW_EQ_OFLD_CMD_EQSTOP_V(1U)
1842
1843 #define FW_EQ_OFLD_CMD_EQID_S 0
1844 #define FW_EQ_OFLD_CMD_EQID_M 0xfffff
1845 #define FW_EQ_OFLD_CMD_EQID_V(x) ((x) << FW_EQ_OFLD_CMD_EQID_S)
1846 #define FW_EQ_OFLD_CMD_EQID_G(x) \
1847 (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M)
1848
1849 #define FW_EQ_OFLD_CMD_PHYSEQID_S 0
1850 #define FW_EQ_OFLD_CMD_PHYSEQID_M 0xfffff
1851 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x) \
1852 (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M)
1853
1854 #define FW_EQ_OFLD_CMD_FETCHSZM_S 26
1855 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S)
1856
1857 #define FW_EQ_OFLD_CMD_STATUSPGNS_S 25
1858 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S)
1859
1860 #define FW_EQ_OFLD_CMD_STATUSPGRO_S 24
1861 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S)
1862
1863 #define FW_EQ_OFLD_CMD_FETCHNS_S 23
1864 #define FW_EQ_OFLD_CMD_FETCHNS_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHNS_S)
1865
1866 #define FW_EQ_OFLD_CMD_FETCHRO_S 22
1867 #define FW_EQ_OFLD_CMD_FETCHRO_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHRO_S)
1868 #define FW_EQ_OFLD_CMD_FETCHRO_F FW_EQ_OFLD_CMD_FETCHRO_V(1U)
1869
1870 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S 20
1871 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S)
1872
1873 #define FW_EQ_OFLD_CMD_CPRIO_S 19
1874 #define FW_EQ_OFLD_CMD_CPRIO_V(x) ((x) << FW_EQ_OFLD_CMD_CPRIO_S)
1875
1876 #define FW_EQ_OFLD_CMD_ONCHIP_S 18
1877 #define FW_EQ_OFLD_CMD_ONCHIP_V(x) ((x) << FW_EQ_OFLD_CMD_ONCHIP_S)
1878
1879 #define FW_EQ_OFLD_CMD_PCIECHN_S 16
1880 #define FW_EQ_OFLD_CMD_PCIECHN_V(x) ((x) << FW_EQ_OFLD_CMD_PCIECHN_S)
1881
1882 #define FW_EQ_OFLD_CMD_IQID_S 0
1883 #define FW_EQ_OFLD_CMD_IQID_V(x) ((x) << FW_EQ_OFLD_CMD_IQID_S)
1884
1885 #define FW_EQ_OFLD_CMD_DCAEN_S 31
1886 #define FW_EQ_OFLD_CMD_DCAEN_V(x) ((x) << FW_EQ_OFLD_CMD_DCAEN_S)
1887
1888 #define FW_EQ_OFLD_CMD_DCACPU_S 26
1889 #define FW_EQ_OFLD_CMD_DCACPU_V(x) ((x) << FW_EQ_OFLD_CMD_DCACPU_S)
1890
1891 #define FW_EQ_OFLD_CMD_FBMIN_S 23
1892 #define FW_EQ_OFLD_CMD_FBMIN_V(x) ((x) << FW_EQ_OFLD_CMD_FBMIN_S)
1893
1894 #define FW_EQ_OFLD_CMD_FBMAX_S 20
1895 #define FW_EQ_OFLD_CMD_FBMAX_V(x) ((x) << FW_EQ_OFLD_CMD_FBMAX_S)
1896
1897 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S 19
1898 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x) \
1899 ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S)
1900
1901 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S 16
1902 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S)
1903
1904 #define FW_EQ_OFLD_CMD_EQSIZE_S 0
1905 #define FW_EQ_OFLD_CMD_EQSIZE_V(x) ((x) << FW_EQ_OFLD_CMD_EQSIZE_S)
1906
1907 /*
1908 * Macros for VIID parsing:
1909 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1910 */
1911
1912 #define FW_VIID_PFN_S 8
1913 #define FW_VIID_PFN_M 0x7
1914 #define FW_VIID_PFN_G(x) (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
1915
1916 #define FW_VIID_VIVLD_S 7
1917 #define FW_VIID_VIVLD_M 0x1
1918 #define FW_VIID_VIVLD_G(x) (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M)
1919
1920 #define FW_VIID_VIN_S 0
1921 #define FW_VIID_VIN_M 0x7F
1922 #define FW_VIID_VIN_G(x) (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M)
1923
1924 struct fw_vi_cmd {
1925 __be32 op_to_vfn;
1926 __be32 alloc_to_len16;
1927 __be16 type_viid;
1928 u8 mac[6];
1929 u8 portid_pkd;
1930 u8 nmac;
1931 u8 nmac0[6];
1932 __be16 rsssize_pkd;
1933 u8 nmac1[6];
1934 __be16 idsiiq_pkd;
1935 u8 nmac2[6];
1936 __be16 idseiq_pkd;
1937 u8 nmac3[6];
1938 __be64 r9;
1939 __be64 r10;
1940 };
1941
1942 #define FW_VI_CMD_PFN_S 8
1943 #define FW_VI_CMD_PFN_V(x) ((x) << FW_VI_CMD_PFN_S)
1944
1945 #define FW_VI_CMD_VFN_S 0
1946 #define FW_VI_CMD_VFN_V(x) ((x) << FW_VI_CMD_VFN_S)
1947
1948 #define FW_VI_CMD_ALLOC_S 31
1949 #define FW_VI_CMD_ALLOC_V(x) ((x) << FW_VI_CMD_ALLOC_S)
1950 #define FW_VI_CMD_ALLOC_F FW_VI_CMD_ALLOC_V(1U)
1951
1952 #define FW_VI_CMD_FREE_S 30
1953 #define FW_VI_CMD_FREE_V(x) ((x) << FW_VI_CMD_FREE_S)
1954 #define FW_VI_CMD_FREE_F FW_VI_CMD_FREE_V(1U)
1955
1956 #define FW_VI_CMD_VIID_S 0
1957 #define FW_VI_CMD_VIID_M 0xfff
1958 #define FW_VI_CMD_VIID_V(x) ((x) << FW_VI_CMD_VIID_S)
1959 #define FW_VI_CMD_VIID_G(x) (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M)
1960
1961 #define FW_VI_CMD_PORTID_S 4
1962 #define FW_VI_CMD_PORTID_M 0xf
1963 #define FW_VI_CMD_PORTID_V(x) ((x) << FW_VI_CMD_PORTID_S)
1964 #define FW_VI_CMD_PORTID_G(x) \
1965 (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M)
1966
1967 #define FW_VI_CMD_RSSSIZE_S 0
1968 #define FW_VI_CMD_RSSSIZE_M 0x7ff
1969 #define FW_VI_CMD_RSSSIZE_G(x) \
1970 (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M)
1971
1972 /* Special VI_MAC command index ids */
1973 #define FW_VI_MAC_ADD_MAC 0x3FF
1974 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1975 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD
1976 #define FW_CLS_TCAM_NUM_ENTRIES 336
1977
1978 enum fw_vi_mac_smac {
1979 FW_VI_MAC_MPS_TCAM_ENTRY,
1980 FW_VI_MAC_MPS_TCAM_ONLY,
1981 FW_VI_MAC_SMT_ONLY,
1982 FW_VI_MAC_SMT_AND_MPSTCAM
1983 };
1984
1985 enum fw_vi_mac_result {
1986 FW_VI_MAC_R_SUCCESS,
1987 FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
1988 FW_VI_MAC_R_SMAC_FAIL,
1989 FW_VI_MAC_R_F_ACL_CHECK
1990 };
1991
1992 struct fw_vi_mac_cmd {
1993 __be32 op_to_viid;
1994 __be32 freemacs_to_len16;
1995 union fw_vi_mac {
1996 struct fw_vi_mac_exact {
1997 __be16 valid_to_idx;
1998 u8 macaddr[6];
1999 } exact[7];
2000 struct fw_vi_mac_hash {
2001 __be64 hashvec;
2002 } hash;
2003 } u;
2004 };
2005
2006 #define FW_VI_MAC_CMD_VIID_S 0
2007 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S)
2008
2009 #define FW_VI_MAC_CMD_FREEMACS_S 31
2010 #define FW_VI_MAC_CMD_FREEMACS_V(x) ((x) << FW_VI_MAC_CMD_FREEMACS_S)
2011
2012 #define FW_VI_MAC_CMD_HASHVECEN_S 23
2013 #define FW_VI_MAC_CMD_HASHVECEN_V(x) ((x) << FW_VI_MAC_CMD_HASHVECEN_S)
2014 #define FW_VI_MAC_CMD_HASHVECEN_F FW_VI_MAC_CMD_HASHVECEN_V(1U)
2015
2016 #define FW_VI_MAC_CMD_HASHUNIEN_S 22
2017 #define FW_VI_MAC_CMD_HASHUNIEN_V(x) ((x) << FW_VI_MAC_CMD_HASHUNIEN_S)
2018
2019 #define FW_VI_MAC_CMD_VALID_S 15
2020 #define FW_VI_MAC_CMD_VALID_V(x) ((x) << FW_VI_MAC_CMD_VALID_S)
2021 #define FW_VI_MAC_CMD_VALID_F FW_VI_MAC_CMD_VALID_V(1U)
2022
2023 #define FW_VI_MAC_CMD_PRIO_S 12
2024 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S)
2025
2026 #define FW_VI_MAC_CMD_SMAC_RESULT_S 10
2027 #define FW_VI_MAC_CMD_SMAC_RESULT_M 0x3
2028 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x) ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S)
2029 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x) \
2030 (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M)
2031
2032 #define FW_VI_MAC_CMD_IDX_S 0
2033 #define FW_VI_MAC_CMD_IDX_M 0x3ff
2034 #define FW_VI_MAC_CMD_IDX_V(x) ((x) << FW_VI_MAC_CMD_IDX_S)
2035 #define FW_VI_MAC_CMD_IDX_G(x) \
2036 (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M)
2037
2038 #define FW_RXMODE_MTU_NO_CHG 65535
2039
2040 struct fw_vi_rxmode_cmd {
2041 __be32 op_to_viid;
2042 __be32 retval_len16;
2043 __be32 mtu_to_vlanexen;
2044 __be32 r4_lo;
2045 };
2046
2047 #define FW_VI_RXMODE_CMD_VIID_S 0
2048 #define FW_VI_RXMODE_CMD_VIID_V(x) ((x) << FW_VI_RXMODE_CMD_VIID_S)
2049
2050 #define FW_VI_RXMODE_CMD_MTU_S 16
2051 #define FW_VI_RXMODE_CMD_MTU_M 0xffff
2052 #define FW_VI_RXMODE_CMD_MTU_V(x) ((x) << FW_VI_RXMODE_CMD_MTU_S)
2053
2054 #define FW_VI_RXMODE_CMD_PROMISCEN_S 14
2055 #define FW_VI_RXMODE_CMD_PROMISCEN_M 0x3
2056 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S)
2057
2058 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S 12
2059 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M 0x3
2060 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x) \
2061 ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S)
2062
2063 #define FW_VI_RXMODE_CMD_BROADCASTEN_S 10
2064 #define FW_VI_RXMODE_CMD_BROADCASTEN_M 0x3
2065 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x) \
2066 ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S)
2067
2068 #define FW_VI_RXMODE_CMD_VLANEXEN_S 8
2069 #define FW_VI_RXMODE_CMD_VLANEXEN_M 0x3
2070 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x) ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S)
2071
2072 struct fw_vi_enable_cmd {
2073 __be32 op_to_viid;
2074 __be32 ien_to_len16;
2075 __be16 blinkdur;
2076 __be16 r3;
2077 __be32 r4;
2078 };
2079
2080 #define FW_VI_ENABLE_CMD_VIID_S 0
2081 #define FW_VI_ENABLE_CMD_VIID_V(x) ((x) << FW_VI_ENABLE_CMD_VIID_S)
2082
2083 #define FW_VI_ENABLE_CMD_IEN_S 31
2084 #define FW_VI_ENABLE_CMD_IEN_V(x) ((x) << FW_VI_ENABLE_CMD_IEN_S)
2085
2086 #define FW_VI_ENABLE_CMD_EEN_S 30
2087 #define FW_VI_ENABLE_CMD_EEN_V(x) ((x) << FW_VI_ENABLE_CMD_EEN_S)
2088
2089 #define FW_VI_ENABLE_CMD_LED_S 29
2090 #define FW_VI_ENABLE_CMD_LED_V(x) ((x) << FW_VI_ENABLE_CMD_LED_S)
2091 #define FW_VI_ENABLE_CMD_LED_F FW_VI_ENABLE_CMD_LED_V(1U)
2092
2093 #define FW_VI_ENABLE_CMD_DCB_INFO_S 28
2094 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x) ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S)
2095
2096 /* VI VF stats offset definitions */
2097 #define VI_VF_NUM_STATS 16
2098 enum fw_vi_stats_vf_index {
2099 FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
2100 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
2101 FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
2102 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
2103 FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
2104 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
2105 FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
2106 FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
2107 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
2108 FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
2109 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
2110 FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
2111 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
2112 FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
2113 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
2114 FW_VI_VF_STAT_RX_ERR_FRAMES_IX
2115 };
2116
2117 /* VI PF stats offset definitions */
2118 #define VI_PF_NUM_STATS 17
2119 enum fw_vi_stats_pf_index {
2120 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
2121 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
2122 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
2123 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
2124 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
2125 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
2126 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
2127 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
2128 FW_VI_PF_STAT_RX_BYTES_IX,
2129 FW_VI_PF_STAT_RX_FRAMES_IX,
2130 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
2131 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
2132 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
2133 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
2134 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
2135 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
2136 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
2137 };
2138
2139 struct fw_vi_stats_cmd {
2140 __be32 op_to_viid;
2141 __be32 retval_len16;
2142 union fw_vi_stats {
2143 struct fw_vi_stats_ctl {
2144 __be16 nstats_ix;
2145 __be16 r6;
2146 __be32 r7;
2147 __be64 stat0;
2148 __be64 stat1;
2149 __be64 stat2;
2150 __be64 stat3;
2151 __be64 stat4;
2152 __be64 stat5;
2153 } ctl;
2154 struct fw_vi_stats_pf {
2155 __be64 tx_bcast_bytes;
2156 __be64 tx_bcast_frames;
2157 __be64 tx_mcast_bytes;
2158 __be64 tx_mcast_frames;
2159 __be64 tx_ucast_bytes;
2160 __be64 tx_ucast_frames;
2161 __be64 tx_offload_bytes;
2162 __be64 tx_offload_frames;
2163 __be64 rx_pf_bytes;
2164 __be64 rx_pf_frames;
2165 __be64 rx_bcast_bytes;
2166 __be64 rx_bcast_frames;
2167 __be64 rx_mcast_bytes;
2168 __be64 rx_mcast_frames;
2169 __be64 rx_ucast_bytes;
2170 __be64 rx_ucast_frames;
2171 __be64 rx_err_frames;
2172 } pf;
2173 struct fw_vi_stats_vf {
2174 __be64 tx_bcast_bytes;
2175 __be64 tx_bcast_frames;
2176 __be64 tx_mcast_bytes;
2177 __be64 tx_mcast_frames;
2178 __be64 tx_ucast_bytes;
2179 __be64 tx_ucast_frames;
2180 __be64 tx_drop_frames;
2181 __be64 tx_offload_bytes;
2182 __be64 tx_offload_frames;
2183 __be64 rx_bcast_bytes;
2184 __be64 rx_bcast_frames;
2185 __be64 rx_mcast_bytes;
2186 __be64 rx_mcast_frames;
2187 __be64 rx_ucast_bytes;
2188 __be64 rx_ucast_frames;
2189 __be64 rx_err_frames;
2190 } vf;
2191 } u;
2192 };
2193
2194 #define FW_VI_STATS_CMD_VIID_S 0
2195 #define FW_VI_STATS_CMD_VIID_V(x) ((x) << FW_VI_STATS_CMD_VIID_S)
2196
2197 #define FW_VI_STATS_CMD_NSTATS_S 12
2198 #define FW_VI_STATS_CMD_NSTATS_V(x) ((x) << FW_VI_STATS_CMD_NSTATS_S)
2199
2200 #define FW_VI_STATS_CMD_IX_S 0
2201 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S)
2202
2203 struct fw_acl_mac_cmd {
2204 __be32 op_to_vfn;
2205 __be32 en_to_len16;
2206 u8 nmac;
2207 u8 r3[7];
2208 __be16 r4;
2209 u8 macaddr0[6];
2210 __be16 r5;
2211 u8 macaddr1[6];
2212 __be16 r6;
2213 u8 macaddr2[6];
2214 __be16 r7;
2215 u8 macaddr3[6];
2216 };
2217
2218 #define FW_ACL_MAC_CMD_PFN_S 8
2219 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S)
2220
2221 #define FW_ACL_MAC_CMD_VFN_S 0
2222 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S)
2223
2224 #define FW_ACL_MAC_CMD_EN_S 31
2225 #define FW_ACL_MAC_CMD_EN_V(x) ((x) << FW_ACL_MAC_CMD_EN_S)
2226
2227 struct fw_acl_vlan_cmd {
2228 __be32 op_to_vfn;
2229 __be32 en_to_len16;
2230 u8 nvlan;
2231 u8 dropnovlan_fm;
2232 u8 r3_lo[6];
2233 __be16 vlanid[16];
2234 };
2235
2236 #define FW_ACL_VLAN_CMD_PFN_S 8
2237 #define FW_ACL_VLAN_CMD_PFN_V(x) ((x) << FW_ACL_VLAN_CMD_PFN_S)
2238
2239 #define FW_ACL_VLAN_CMD_VFN_S 0
2240 #define FW_ACL_VLAN_CMD_VFN_V(x) ((x) << FW_ACL_VLAN_CMD_VFN_S)
2241
2242 #define FW_ACL_VLAN_CMD_EN_S 31
2243 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S)
2244
2245 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S 7
2246 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)
2247
2248 #define FW_ACL_VLAN_CMD_FM_S 6
2249 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S)
2250
2251 enum fw_port_cap {
2252 FW_PORT_CAP_SPEED_100M = 0x0001,
2253 FW_PORT_CAP_SPEED_1G = 0x0002,
2254 FW_PORT_CAP_SPEED_25G = 0x0004,
2255 FW_PORT_CAP_SPEED_10G = 0x0008,
2256 FW_PORT_CAP_SPEED_40G = 0x0010,
2257 FW_PORT_CAP_SPEED_100G = 0x0020,
2258 FW_PORT_CAP_FC_RX = 0x0040,
2259 FW_PORT_CAP_FC_TX = 0x0080,
2260 FW_PORT_CAP_ANEG = 0x0100,
2261 FW_PORT_CAP_MDIX = 0x0200,
2262 FW_PORT_CAP_MDIAUTO = 0x0400,
2263 FW_PORT_CAP_FEC = 0x0800,
2264 FW_PORT_CAP_TECHKR = 0x1000,
2265 FW_PORT_CAP_TECHKX4 = 0x2000,
2266 FW_PORT_CAP_802_3_PAUSE = 0x4000,
2267 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
2268 };
2269
2270 enum fw_port_mdi {
2271 FW_PORT_CAP_MDI_UNCHANGED,
2272 FW_PORT_CAP_MDI_AUTO,
2273 FW_PORT_CAP_MDI_F_STRAIGHT,
2274 FW_PORT_CAP_MDI_F_CROSSOVER
2275 };
2276
2277 #define FW_PORT_CAP_MDI_S 9
2278 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)
2279
2280 enum fw_port_action {
2281 FW_PORT_ACTION_L1_CFG = 0x0001,
2282 FW_PORT_ACTION_L2_CFG = 0x0002,
2283 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
2284 FW_PORT_ACTION_L2_PPP_CFG = 0x0004,
2285 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
2286 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006,
2287 FW_PORT_ACTION_DCB_READ_RECV = 0x0007,
2288 FW_PORT_ACTION_DCB_READ_DET = 0x0008,
2289 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
2290 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
2291 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
2292 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
2293 FW_PORT_ACTION_L1_LPBK = 0x0021,
2294 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022,
2295 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023,
2296 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
2297 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
2298 FW_PORT_ACTION_PHY_RESET = 0x0040,
2299 FW_PORT_ACTION_PMA_RESET = 0x0041,
2300 FW_PORT_ACTION_PCS_RESET = 0x0042,
2301 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
2302 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
2303 FW_PORT_ACTION_AN_RESET = 0x0045
2304 };
2305
2306 enum fw_port_l2cfg_ctlbf {
2307 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
2308 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
2309 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
2310 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
2311 FW_PORT_L2_CTLBF_IVLAN = 0x10,
2312 FW_PORT_L2_CTLBF_TXIPG = 0x20
2313 };
2314
2315 enum fw_port_dcb_versions {
2316 FW_PORT_DCB_VER_UNKNOWN,
2317 FW_PORT_DCB_VER_CEE1D0,
2318 FW_PORT_DCB_VER_CEE1D01,
2319 FW_PORT_DCB_VER_IEEE,
2320 FW_PORT_DCB_VER_AUTO = 7
2321 };
2322
2323 enum fw_port_dcb_cfg {
2324 FW_PORT_DCB_CFG_PG = 0x01,
2325 FW_PORT_DCB_CFG_PFC = 0x02,
2326 FW_PORT_DCB_CFG_APPL = 0x04
2327 };
2328
2329 enum fw_port_dcb_cfg_rc {
2330 FW_PORT_DCB_CFG_SUCCESS = 0x0,
2331 FW_PORT_DCB_CFG_ERROR = 0x1
2332 };
2333
2334 enum fw_port_dcb_type {
2335 FW_PORT_DCB_TYPE_PGID = 0x00,
2336 FW_PORT_DCB_TYPE_PGRATE = 0x01,
2337 FW_PORT_DCB_TYPE_PRIORATE = 0x02,
2338 FW_PORT_DCB_TYPE_PFC = 0x03,
2339 FW_PORT_DCB_TYPE_APP_ID = 0x04,
2340 FW_PORT_DCB_TYPE_CONTROL = 0x05,
2341 };
2342
2343 enum fw_port_dcb_feature_state {
2344 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
2345 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
2346 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
2347 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
2348 };
2349
2350 struct fw_port_cmd {
2351 __be32 op_to_portid;
2352 __be32 action_to_len16;
2353 union fw_port {
2354 struct fw_port_l1cfg {
2355 __be32 rcap;
2356 __be32 r;
2357 } l1cfg;
2358 struct fw_port_l2cfg {
2359 __u8 ctlbf;
2360 __u8 ovlan3_to_ivlan0;
2361 __be16 ivlantype;
2362 __be16 txipg_force_pinfo;
2363 __be16 mtu;
2364 __be16 ovlan0mask;
2365 __be16 ovlan0type;
2366 __be16 ovlan1mask;
2367 __be16 ovlan1type;
2368 __be16 ovlan2mask;
2369 __be16 ovlan2type;
2370 __be16 ovlan3mask;
2371 __be16 ovlan3type;
2372 } l2cfg;
2373 struct fw_port_info {
2374 __be32 lstatus_to_modtype;
2375 __be16 pcap;
2376 __be16 acap;
2377 __be16 mtu;
2378 __u8 cbllen;
2379 __u8 auxlinfo;
2380 __u8 dcbxdis_pkd;
2381 __u8 r8_lo;
2382 __be16 lpacap;
2383 __be64 r9;
2384 } info;
2385 struct fw_port_diags {
2386 __u8 diagop;
2387 __u8 r[3];
2388 __be32 diagval;
2389 } diags;
2390 union fw_port_dcb {
2391 struct fw_port_dcb_pgid {
2392 __u8 type;
2393 __u8 apply_pkd;
2394 __u8 r10_lo[2];
2395 __be32 pgid;
2396 __be64 r11;
2397 } pgid;
2398 struct fw_port_dcb_pgrate {
2399 __u8 type;
2400 __u8 apply_pkd;
2401 __u8 r10_lo[5];
2402 __u8 num_tcs_supported;
2403 __u8 pgrate[8];
2404 __u8 tsa[8];
2405 } pgrate;
2406 struct fw_port_dcb_priorate {
2407 __u8 type;
2408 __u8 apply_pkd;
2409 __u8 r10_lo[6];
2410 __u8 strict_priorate[8];
2411 } priorate;
2412 struct fw_port_dcb_pfc {
2413 __u8 type;
2414 __u8 pfcen;
2415 __u8 r10[5];
2416 __u8 max_pfc_tcs;
2417 __be64 r11;
2418 } pfc;
2419 struct fw_port_app_priority {
2420 __u8 type;
2421 __u8 r10[2];
2422 __u8 idx;
2423 __u8 user_prio_map;
2424 __u8 sel_field;
2425 __be16 protocolid;
2426 __be64 r12;
2427 } app_priority;
2428 struct fw_port_dcb_control {
2429 __u8 type;
2430 __u8 all_syncd_pkd;
2431 __be16 dcb_version_to_app_state;
2432 __be32 r11;
2433 __be64 r12;
2434 } control;
2435 } dcb;
2436 } u;
2437 };
2438
2439 #define FW_PORT_CMD_READ_S 22
2440 #define FW_PORT_CMD_READ_V(x) ((x) << FW_PORT_CMD_READ_S)
2441 #define FW_PORT_CMD_READ_F FW_PORT_CMD_READ_V(1U)
2442
2443 #define FW_PORT_CMD_PORTID_S 0
2444 #define FW_PORT_CMD_PORTID_M 0xf
2445 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S)
2446 #define FW_PORT_CMD_PORTID_G(x) \
2447 (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M)
2448
2449 #define FW_PORT_CMD_ACTION_S 16
2450 #define FW_PORT_CMD_ACTION_M 0xffff
2451 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S)
2452 #define FW_PORT_CMD_ACTION_G(x) \
2453 (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M)
2454
2455 #define FW_PORT_CMD_OVLAN3_S 7
2456 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S)
2457
2458 #define FW_PORT_CMD_OVLAN2_S 6
2459 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S)
2460
2461 #define FW_PORT_CMD_OVLAN1_S 5
2462 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S)
2463
2464 #define FW_PORT_CMD_OVLAN0_S 4
2465 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S)
2466
2467 #define FW_PORT_CMD_IVLAN0_S 3
2468 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S)
2469
2470 #define FW_PORT_CMD_TXIPG_S 3
2471 #define FW_PORT_CMD_TXIPG_V(x) ((x) << FW_PORT_CMD_TXIPG_S)
2472
2473 #define FW_PORT_CMD_LSTATUS_S 31
2474 #define FW_PORT_CMD_LSTATUS_M 0x1
2475 #define FW_PORT_CMD_LSTATUS_V(x) ((x) << FW_PORT_CMD_LSTATUS_S)
2476 #define FW_PORT_CMD_LSTATUS_G(x) \
2477 (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M)
2478 #define FW_PORT_CMD_LSTATUS_F FW_PORT_CMD_LSTATUS_V(1U)
2479
2480 #define FW_PORT_CMD_LSPEED_S 24
2481 #define FW_PORT_CMD_LSPEED_M 0x3f
2482 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S)
2483 #define FW_PORT_CMD_LSPEED_G(x) \
2484 (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M)
2485
2486 #define FW_PORT_CMD_TXPAUSE_S 23
2487 #define FW_PORT_CMD_TXPAUSE_V(x) ((x) << FW_PORT_CMD_TXPAUSE_S)
2488 #define FW_PORT_CMD_TXPAUSE_F FW_PORT_CMD_TXPAUSE_V(1U)
2489
2490 #define FW_PORT_CMD_RXPAUSE_S 22
2491 #define FW_PORT_CMD_RXPAUSE_V(x) ((x) << FW_PORT_CMD_RXPAUSE_S)
2492 #define FW_PORT_CMD_RXPAUSE_F FW_PORT_CMD_RXPAUSE_V(1U)
2493
2494 #define FW_PORT_CMD_MDIOCAP_S 21
2495 #define FW_PORT_CMD_MDIOCAP_V(x) ((x) << FW_PORT_CMD_MDIOCAP_S)
2496 #define FW_PORT_CMD_MDIOCAP_F FW_PORT_CMD_MDIOCAP_V(1U)
2497
2498 #define FW_PORT_CMD_MDIOADDR_S 16
2499 #define FW_PORT_CMD_MDIOADDR_M 0x1f
2500 #define FW_PORT_CMD_MDIOADDR_G(x) \
2501 (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M)
2502
2503 #define FW_PORT_CMD_LPTXPAUSE_S 15
2504 #define FW_PORT_CMD_LPTXPAUSE_V(x) ((x) << FW_PORT_CMD_LPTXPAUSE_S)
2505 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U)
2506
2507 #define FW_PORT_CMD_LPRXPAUSE_S 14
2508 #define FW_PORT_CMD_LPRXPAUSE_V(x) ((x) << FW_PORT_CMD_LPRXPAUSE_S)
2509 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U)
2510
2511 #define FW_PORT_CMD_PTYPE_S 8
2512 #define FW_PORT_CMD_PTYPE_M 0x1f
2513 #define FW_PORT_CMD_PTYPE_G(x) \
2514 (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M)
2515
2516 #define FW_PORT_CMD_LINKDNRC_S 5
2517 #define FW_PORT_CMD_LINKDNRC_M 0x7
2518 #define FW_PORT_CMD_LINKDNRC_G(x) \
2519 (((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M)
2520
2521 #define FW_PORT_CMD_MODTYPE_S 0
2522 #define FW_PORT_CMD_MODTYPE_M 0x1f
2523 #define FW_PORT_CMD_MODTYPE_V(x) ((x) << FW_PORT_CMD_MODTYPE_S)
2524 #define FW_PORT_CMD_MODTYPE_G(x) \
2525 (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M)
2526
2527 #define FW_PORT_CMD_DCBXDIS_S 7
2528 #define FW_PORT_CMD_DCBXDIS_V(x) ((x) << FW_PORT_CMD_DCBXDIS_S)
2529 #define FW_PORT_CMD_DCBXDIS_F FW_PORT_CMD_DCBXDIS_V(1U)
2530
2531 #define FW_PORT_CMD_APPLY_S 7
2532 #define FW_PORT_CMD_APPLY_V(x) ((x) << FW_PORT_CMD_APPLY_S)
2533 #define FW_PORT_CMD_APPLY_F FW_PORT_CMD_APPLY_V(1U)
2534
2535 #define FW_PORT_CMD_ALL_SYNCD_S 7
2536 #define FW_PORT_CMD_ALL_SYNCD_V(x) ((x) << FW_PORT_CMD_ALL_SYNCD_S)
2537 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U)
2538
2539 #define FW_PORT_CMD_DCB_VERSION_S 12
2540 #define FW_PORT_CMD_DCB_VERSION_M 0x7
2541 #define FW_PORT_CMD_DCB_VERSION_G(x) \
2542 (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M)
2543
2544 enum fw_port_type {
2545 FW_PORT_TYPE_FIBER_XFI,
2546 FW_PORT_TYPE_FIBER_XAUI,
2547 FW_PORT_TYPE_BT_SGMII,
2548 FW_PORT_TYPE_BT_XFI,
2549 FW_PORT_TYPE_BT_XAUI,
2550 FW_PORT_TYPE_KX4,
2551 FW_PORT_TYPE_CX4,
2552 FW_PORT_TYPE_KX,
2553 FW_PORT_TYPE_KR,
2554 FW_PORT_TYPE_SFP,
2555 FW_PORT_TYPE_BP_AP,
2556 FW_PORT_TYPE_BP4_AP,
2557 FW_PORT_TYPE_QSFP_10G,
2558 FW_PORT_TYPE_QSA,
2559 FW_PORT_TYPE_QSFP,
2560 FW_PORT_TYPE_BP40_BA,
2561 FW_PORT_TYPE_KR4_100G,
2562 FW_PORT_TYPE_CR4_QSFP,
2563 FW_PORT_TYPE_CR_QSFP,
2564 FW_PORT_TYPE_CR2_QSFP,
2565 FW_PORT_TYPE_SFP28,
2566
2567 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M
2568 };
2569
2570 enum fw_port_module_type {
2571 FW_PORT_MOD_TYPE_NA,
2572 FW_PORT_MOD_TYPE_LR,
2573 FW_PORT_MOD_TYPE_SR,
2574 FW_PORT_MOD_TYPE_ER,
2575 FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
2576 FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
2577 FW_PORT_MOD_TYPE_LRM,
2578 FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_M - 3,
2579 FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_M - 2,
2580 FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_M - 1,
2581
2582 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M
2583 };
2584
2585 enum fw_port_mod_sub_type {
2586 FW_PORT_MOD_SUB_TYPE_NA,
2587 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
2588 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
2589 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
2590 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
2591 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
2592 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
2593
2594 /* The following will never been in the VPD. They are TWINAX cable
2595 * lengths decoded from SFP+ module i2c PROMs. These should
2596 * almost certainly go somewhere else ...
2597 */
2598 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
2599 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
2600 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
2601 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
2602 };
2603
2604 enum fw_port_stats_tx_index {
2605 FW_STAT_TX_PORT_BYTES_IX = 0,
2606 FW_STAT_TX_PORT_FRAMES_IX,
2607 FW_STAT_TX_PORT_BCAST_IX,
2608 FW_STAT_TX_PORT_MCAST_IX,
2609 FW_STAT_TX_PORT_UCAST_IX,
2610 FW_STAT_TX_PORT_ERROR_IX,
2611 FW_STAT_TX_PORT_64B_IX,
2612 FW_STAT_TX_PORT_65B_127B_IX,
2613 FW_STAT_TX_PORT_128B_255B_IX,
2614 FW_STAT_TX_PORT_256B_511B_IX,
2615 FW_STAT_TX_PORT_512B_1023B_IX,
2616 FW_STAT_TX_PORT_1024B_1518B_IX,
2617 FW_STAT_TX_PORT_1519B_MAX_IX,
2618 FW_STAT_TX_PORT_DROP_IX,
2619 FW_STAT_TX_PORT_PAUSE_IX,
2620 FW_STAT_TX_PORT_PPP0_IX,
2621 FW_STAT_TX_PORT_PPP1_IX,
2622 FW_STAT_TX_PORT_PPP2_IX,
2623 FW_STAT_TX_PORT_PPP3_IX,
2624 FW_STAT_TX_PORT_PPP4_IX,
2625 FW_STAT_TX_PORT_PPP5_IX,
2626 FW_STAT_TX_PORT_PPP6_IX,
2627 FW_STAT_TX_PORT_PPP7_IX,
2628 FW_NUM_PORT_TX_STATS
2629 };
2630
2631 enum fw_port_stat_rx_index {
2632 FW_STAT_RX_PORT_BYTES_IX = 0,
2633 FW_STAT_RX_PORT_FRAMES_IX,
2634 FW_STAT_RX_PORT_BCAST_IX,
2635 FW_STAT_RX_PORT_MCAST_IX,
2636 FW_STAT_RX_PORT_UCAST_IX,
2637 FW_STAT_RX_PORT_MTU_ERROR_IX,
2638 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
2639 FW_STAT_RX_PORT_CRC_ERROR_IX,
2640 FW_STAT_RX_PORT_LEN_ERROR_IX,
2641 FW_STAT_RX_PORT_SYM_ERROR_IX,
2642 FW_STAT_RX_PORT_64B_IX,
2643 FW_STAT_RX_PORT_65B_127B_IX,
2644 FW_STAT_RX_PORT_128B_255B_IX,
2645 FW_STAT_RX_PORT_256B_511B_IX,
2646 FW_STAT_RX_PORT_512B_1023B_IX,
2647 FW_STAT_RX_PORT_1024B_1518B_IX,
2648 FW_STAT_RX_PORT_1519B_MAX_IX,
2649 FW_STAT_RX_PORT_PAUSE_IX,
2650 FW_STAT_RX_PORT_PPP0_IX,
2651 FW_STAT_RX_PORT_PPP1_IX,
2652 FW_STAT_RX_PORT_PPP2_IX,
2653 FW_STAT_RX_PORT_PPP3_IX,
2654 FW_STAT_RX_PORT_PPP4_IX,
2655 FW_STAT_RX_PORT_PPP5_IX,
2656 FW_STAT_RX_PORT_PPP6_IX,
2657 FW_STAT_RX_PORT_PPP7_IX,
2658 FW_STAT_RX_PORT_LESS_64B_IX,
2659 FW_STAT_RX_PORT_MAC_ERROR_IX,
2660 FW_NUM_PORT_RX_STATS
2661 };
2662
2663 /* port stats */
2664 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS)
2665
2666 struct fw_port_stats_cmd {
2667 __be32 op_to_portid;
2668 __be32 retval_len16;
2669 union fw_port_stats {
2670 struct fw_port_stats_ctl {
2671 u8 nstats_bg_bm;
2672 u8 tx_ix;
2673 __be16 r6;
2674 __be32 r7;
2675 __be64 stat0;
2676 __be64 stat1;
2677 __be64 stat2;
2678 __be64 stat3;
2679 __be64 stat4;
2680 __be64 stat5;
2681 } ctl;
2682 struct fw_port_stats_all {
2683 __be64 tx_bytes;
2684 __be64 tx_frames;
2685 __be64 tx_bcast;
2686 __be64 tx_mcast;
2687 __be64 tx_ucast;
2688 __be64 tx_error;
2689 __be64 tx_64b;
2690 __be64 tx_65b_127b;
2691 __be64 tx_128b_255b;
2692 __be64 tx_256b_511b;
2693 __be64 tx_512b_1023b;
2694 __be64 tx_1024b_1518b;
2695 __be64 tx_1519b_max;
2696 __be64 tx_drop;
2697 __be64 tx_pause;
2698 __be64 tx_ppp0;
2699 __be64 tx_ppp1;
2700 __be64 tx_ppp2;
2701 __be64 tx_ppp3;
2702 __be64 tx_ppp4;
2703 __be64 tx_ppp5;
2704 __be64 tx_ppp6;
2705 __be64 tx_ppp7;
2706 __be64 rx_bytes;
2707 __be64 rx_frames;
2708 __be64 rx_bcast;
2709 __be64 rx_mcast;
2710 __be64 rx_ucast;
2711 __be64 rx_mtu_error;
2712 __be64 rx_mtu_crc_error;
2713 __be64 rx_crc_error;
2714 __be64 rx_len_error;
2715 __be64 rx_sym_error;
2716 __be64 rx_64b;
2717 __be64 rx_65b_127b;
2718 __be64 rx_128b_255b;
2719 __be64 rx_256b_511b;
2720 __be64 rx_512b_1023b;
2721 __be64 rx_1024b_1518b;
2722 __be64 rx_1519b_max;
2723 __be64 rx_pause;
2724 __be64 rx_ppp0;
2725 __be64 rx_ppp1;
2726 __be64 rx_ppp2;
2727 __be64 rx_ppp3;
2728 __be64 rx_ppp4;
2729 __be64 rx_ppp5;
2730 __be64 rx_ppp6;
2731 __be64 rx_ppp7;
2732 __be64 rx_less_64b;
2733 __be64 rx_bg_drop;
2734 __be64 rx_bg_trunc;
2735 } all;
2736 } u;
2737 };
2738
2739 /* port loopback stats */
2740 #define FW_NUM_LB_STATS 16
2741 enum fw_port_lb_stats_index {
2742 FW_STAT_LB_PORT_BYTES_IX,
2743 FW_STAT_LB_PORT_FRAMES_IX,
2744 FW_STAT_LB_PORT_BCAST_IX,
2745 FW_STAT_LB_PORT_MCAST_IX,
2746 FW_STAT_LB_PORT_UCAST_IX,
2747 FW_STAT_LB_PORT_ERROR_IX,
2748 FW_STAT_LB_PORT_64B_IX,
2749 FW_STAT_LB_PORT_65B_127B_IX,
2750 FW_STAT_LB_PORT_128B_255B_IX,
2751 FW_STAT_LB_PORT_256B_511B_IX,
2752 FW_STAT_LB_PORT_512B_1023B_IX,
2753 FW_STAT_LB_PORT_1024B_1518B_IX,
2754 FW_STAT_LB_PORT_1519B_MAX_IX,
2755 FW_STAT_LB_PORT_DROP_FRAMES_IX
2756 };
2757
2758 struct fw_port_lb_stats_cmd {
2759 __be32 op_to_lbport;
2760 __be32 retval_len16;
2761 union fw_port_lb_stats {
2762 struct fw_port_lb_stats_ctl {
2763 u8 nstats_bg_bm;
2764 u8 ix_pkd;
2765 __be16 r6;
2766 __be32 r7;
2767 __be64 stat0;
2768 __be64 stat1;
2769 __be64 stat2;
2770 __be64 stat3;
2771 __be64 stat4;
2772 __be64 stat5;
2773 } ctl;
2774 struct fw_port_lb_stats_all {
2775 __be64 tx_bytes;
2776 __be64 tx_frames;
2777 __be64 tx_bcast;
2778 __be64 tx_mcast;
2779 __be64 tx_ucast;
2780 __be64 tx_error;
2781 __be64 tx_64b;
2782 __be64 tx_65b_127b;
2783 __be64 tx_128b_255b;
2784 __be64 tx_256b_511b;
2785 __be64 tx_512b_1023b;
2786 __be64 tx_1024b_1518b;
2787 __be64 tx_1519b_max;
2788 __be64 rx_lb_drop;
2789 __be64 rx_lb_trunc;
2790 } all;
2791 } u;
2792 };
2793
2794 struct fw_rss_ind_tbl_cmd {
2795 __be32 op_to_viid;
2796 __be32 retval_len16;
2797 __be16 niqid;
2798 __be16 startidx;
2799 __be32 r3;
2800 __be32 iq0_to_iq2;
2801 __be32 iq3_to_iq5;
2802 __be32 iq6_to_iq8;
2803 __be32 iq9_to_iq11;
2804 __be32 iq12_to_iq14;
2805 __be32 iq15_to_iq17;
2806 __be32 iq18_to_iq20;
2807 __be32 iq21_to_iq23;
2808 __be32 iq24_to_iq26;
2809 __be32 iq27_to_iq29;
2810 __be32 iq30_iq31;
2811 __be32 r15_lo;
2812 };
2813
2814 #define FW_RSS_IND_TBL_CMD_VIID_S 0
2815 #define FW_RSS_IND_TBL_CMD_VIID_V(x) ((x) << FW_RSS_IND_TBL_CMD_VIID_S)
2816
2817 #define FW_RSS_IND_TBL_CMD_IQ0_S 20
2818 #define FW_RSS_IND_TBL_CMD_IQ0_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ0_S)
2819
2820 #define FW_RSS_IND_TBL_CMD_IQ1_S 10
2821 #define FW_RSS_IND_TBL_CMD_IQ1_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ1_S)
2822
2823 #define FW_RSS_IND_TBL_CMD_IQ2_S 0
2824 #define FW_RSS_IND_TBL_CMD_IQ2_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ2_S)
2825
2826 struct fw_rss_glb_config_cmd {
2827 __be32 op_to_write;
2828 __be32 retval_len16;
2829 union fw_rss_glb_config {
2830 struct fw_rss_glb_config_manual {
2831 __be32 mode_pkd;
2832 __be32 r3;
2833 __be64 r4;
2834 __be64 r5;
2835 } manual;
2836 struct fw_rss_glb_config_basicvirtual {
2837 __be32 mode_pkd;
2838 __be32 synmapen_to_hashtoeplitz;
2839 __be64 r8;
2840 __be64 r9;
2841 } basicvirtual;
2842 } u;
2843 };
2844
2845 #define FW_RSS_GLB_CONFIG_CMD_MODE_S 28
2846 #define FW_RSS_GLB_CONFIG_CMD_MODE_M 0xf
2847 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)
2848 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \
2849 (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M)
2850
2851 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
2852 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2853
2854 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S 8
2855 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x) \
2856 ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S)
2857 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F \
2858 FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U)
2859
2860 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S 7
2861 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x) \
2862 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S)
2863 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F \
2864 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U)
2865
2866 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S 6
2867 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x) \
2868 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S)
2869 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F \
2870 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U)
2871
2872 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S 5
2873 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x) \
2874 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S)
2875 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F \
2876 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U)
2877
2878 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S 4
2879 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x) \
2880 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S)
2881 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F \
2882 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U)
2883
2884 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S 3
2885 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x) \
2886 ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S)
2887 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F \
2888 FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U)
2889
2890 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S 2
2891 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x) \
2892 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S)
2893 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F \
2894 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U)
2895
2896 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S 1
2897 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x) \
2898 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S)
2899 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F \
2900 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U)
2901
2902 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S 0
2903 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \
2904 ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S)
2905 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F \
2906 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U)
2907
2908 struct fw_rss_vi_config_cmd {
2909 __be32 op_to_viid;
2910 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
2911 __be32 retval_len16;
2912 union fw_rss_vi_config {
2913 struct fw_rss_vi_config_manual {
2914 __be64 r3;
2915 __be64 r4;
2916 __be64 r5;
2917 } manual;
2918 struct fw_rss_vi_config_basicvirtual {
2919 __be32 r6;
2920 __be32 defaultq_to_udpen;
2921 __be64 r9;
2922 __be64 r10;
2923 } basicvirtual;
2924 } u;
2925 };
2926
2927 #define FW_RSS_VI_CONFIG_CMD_VIID_S 0
2928 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)
2929
2930 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S 16
2931 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M 0x3ff
2932 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x) \
2933 ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S)
2934 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x) \
2935 (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \
2936 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M)
2937
2938 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S 4
2939 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x) \
2940 ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S)
2941 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F \
2942 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U)
2943
2944 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S 3
2945 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x) \
2946 ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S)
2947 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F \
2948 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U)
2949
2950 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S 2
2951 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x) \
2952 ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S)
2953 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F \
2954 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U)
2955
2956 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S 1
2957 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x) \
2958 ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S)
2959 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F \
2960 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U)
2961
2962 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S 0
2963 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)
2964 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U)
2965
2966 enum fw_sched_sc {
2967 FW_SCHED_SC_PARAMS = 1,
2968 };
2969
2970 struct fw_sched_cmd {
2971 __be32 op_to_write;
2972 __be32 retval_len16;
2973 union fw_sched {
2974 struct fw_sched_config {
2975 __u8 sc;
2976 __u8 type;
2977 __u8 minmaxen;
2978 __u8 r3[5];
2979 __u8 nclasses[4];
2980 __be32 r4;
2981 } config;
2982 struct fw_sched_params {
2983 __u8 sc;
2984 __u8 type;
2985 __u8 level;
2986 __u8 mode;
2987 __u8 unit;
2988 __u8 rate;
2989 __u8 ch;
2990 __u8 cl;
2991 __be32 min;
2992 __be32 max;
2993 __be16 weight;
2994 __be16 pktsize;
2995 __be16 burstsize;
2996 __be16 r4;
2997 } params;
2998 } u;
2999 };
3000
3001 struct fw_clip_cmd {
3002 __be32 op_to_write;
3003 __be32 alloc_to_len16;
3004 __be64 ip_hi;
3005 __be64 ip_lo;
3006 __be32 r4[2];
3007 };
3008
3009 #define FW_CLIP_CMD_ALLOC_S 31
3010 #define FW_CLIP_CMD_ALLOC_V(x) ((x) << FW_CLIP_CMD_ALLOC_S)
3011 #define FW_CLIP_CMD_ALLOC_F FW_CLIP_CMD_ALLOC_V(1U)
3012
3013 #define FW_CLIP_CMD_FREE_S 30
3014 #define FW_CLIP_CMD_FREE_V(x) ((x) << FW_CLIP_CMD_FREE_S)
3015 #define FW_CLIP_CMD_FREE_F FW_CLIP_CMD_FREE_V(1U)
3016
3017 enum fw_error_type {
3018 FW_ERROR_TYPE_EXCEPTION = 0x0,
3019 FW_ERROR_TYPE_HWMODULE = 0x1,
3020 FW_ERROR_TYPE_WR = 0x2,
3021 FW_ERROR_TYPE_ACL = 0x3,
3022 };
3023
3024 struct fw_error_cmd {
3025 __be32 op_to_type;
3026 __be32 len16_pkd;
3027 union fw_error {
3028 struct fw_error_exception {
3029 __be32 info[6];
3030 } exception;
3031 struct fw_error_hwmodule {
3032 __be32 regaddr;
3033 __be32 regval;
3034 } hwmodule;
3035 struct fw_error_wr {
3036 __be16 cidx;
3037 __be16 pfn_vfn;
3038 __be32 eqid;
3039 u8 wrhdr[16];
3040 } wr;
3041 struct fw_error_acl {
3042 __be16 cidx;
3043 __be16 pfn_vfn;
3044 __be32 eqid;
3045 __be16 mv_pkd;
3046 u8 val[6];
3047 __be64 r4;
3048 } acl;
3049 } u;
3050 };
3051
3052 struct fw_debug_cmd {
3053 __be32 op_type;
3054 __be32 len16_pkd;
3055 union fw_debug {
3056 struct fw_debug_assert {
3057 __be32 fcid;
3058 __be32 line;
3059 __be32 x;
3060 __be32 y;
3061 u8 filename_0_7[8];
3062 u8 filename_8_15[8];
3063 __be64 r3;
3064 } assert;
3065 struct fw_debug_prt {
3066 __be16 dprtstridx;
3067 __be16 r3[3];
3068 __be32 dprtstrparam0;
3069 __be32 dprtstrparam1;
3070 __be32 dprtstrparam2;
3071 __be32 dprtstrparam3;
3072 } prt;
3073 } u;
3074 };
3075
3076 #define FW_DEBUG_CMD_TYPE_S 0
3077 #define FW_DEBUG_CMD_TYPE_M 0xff
3078 #define FW_DEBUG_CMD_TYPE_G(x) \
3079 (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
3080
3081 #define PCIE_FW_ERR_S 31
3082 #define PCIE_FW_ERR_V(x) ((x) << PCIE_FW_ERR_S)
3083 #define PCIE_FW_ERR_F PCIE_FW_ERR_V(1U)
3084
3085 #define PCIE_FW_INIT_S 30
3086 #define PCIE_FW_INIT_V(x) ((x) << PCIE_FW_INIT_S)
3087 #define PCIE_FW_INIT_F PCIE_FW_INIT_V(1U)
3088
3089 #define PCIE_FW_HALT_S 29
3090 #define PCIE_FW_HALT_V(x) ((x) << PCIE_FW_HALT_S)
3091 #define PCIE_FW_HALT_F PCIE_FW_HALT_V(1U)
3092
3093 #define PCIE_FW_EVAL_S 24
3094 #define PCIE_FW_EVAL_M 0x7
3095 #define PCIE_FW_EVAL_G(x) (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)
3096
3097 #define PCIE_FW_MASTER_VLD_S 15
3098 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S)
3099 #define PCIE_FW_MASTER_VLD_F PCIE_FW_MASTER_VLD_V(1U)
3100
3101 #define PCIE_FW_MASTER_S 12
3102 #define PCIE_FW_MASTER_M 0x7
3103 #define PCIE_FW_MASTER_V(x) ((x) << PCIE_FW_MASTER_S)
3104 #define PCIE_FW_MASTER_G(x) (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)
3105
3106 struct fw_hdr {
3107 u8 ver;
3108 u8 chip; /* terminator chip type */
3109 __be16 len512; /* bin length in units of 512-bytes */
3110 __be32 fw_ver; /* firmware version */
3111 __be32 tp_microcode_ver;
3112 u8 intfver_nic;
3113 u8 intfver_vnic;
3114 u8 intfver_ofld;
3115 u8 intfver_ri;
3116 u8 intfver_iscsipdu;
3117 u8 intfver_iscsi;
3118 u8 intfver_fcoepdu;
3119 u8 intfver_fcoe;
3120 __u32 reserved2;
3121 __u32 reserved3;
3122 __u32 reserved4;
3123 __be32 flags;
3124 __be32 reserved6[23];
3125 };
3126
3127 enum fw_hdr_chip {
3128 FW_HDR_CHIP_T4,
3129 FW_HDR_CHIP_T5,
3130 FW_HDR_CHIP_T6
3131 };
3132
3133 #define FW_HDR_FW_VER_MAJOR_S 24
3134 #define FW_HDR_FW_VER_MAJOR_M 0xff
3135 #define FW_HDR_FW_VER_MAJOR_V(x) \
3136 ((x) << FW_HDR_FW_VER_MAJOR_S)
3137 #define FW_HDR_FW_VER_MAJOR_G(x) \
3138 (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M)
3139
3140 #define FW_HDR_FW_VER_MINOR_S 16
3141 #define FW_HDR_FW_VER_MINOR_M 0xff
3142 #define FW_HDR_FW_VER_MINOR_V(x) \
3143 ((x) << FW_HDR_FW_VER_MINOR_S)
3144 #define FW_HDR_FW_VER_MINOR_G(x) \
3145 (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M)
3146
3147 #define FW_HDR_FW_VER_MICRO_S 8
3148 #define FW_HDR_FW_VER_MICRO_M 0xff
3149 #define FW_HDR_FW_VER_MICRO_V(x) \
3150 ((x) << FW_HDR_FW_VER_MICRO_S)
3151 #define FW_HDR_FW_VER_MICRO_G(x) \
3152 (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M)
3153
3154 #define FW_HDR_FW_VER_BUILD_S 0
3155 #define FW_HDR_FW_VER_BUILD_M 0xff
3156 #define FW_HDR_FW_VER_BUILD_V(x) \
3157 ((x) << FW_HDR_FW_VER_BUILD_S)
3158 #define FW_HDR_FW_VER_BUILD_G(x) \
3159 (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M)
3160
3161 enum fw_hdr_intfver {
3162 FW_HDR_INTFVER_NIC = 0x00,
3163 FW_HDR_INTFVER_VNIC = 0x00,
3164 FW_HDR_INTFVER_OFLD = 0x00,
3165 FW_HDR_INTFVER_RI = 0x00,
3166 FW_HDR_INTFVER_ISCSIPDU = 0x00,
3167 FW_HDR_INTFVER_ISCSI = 0x00,
3168 FW_HDR_INTFVER_FCOEPDU = 0x00,
3169 FW_HDR_INTFVER_FCOE = 0x00,
3170 };
3171
3172 enum fw_hdr_flags {
3173 FW_HDR_FLAGS_RESET_HALT = 0x00000001,
3174 };
3175
3176 /* length of the formatting string */
3177 #define FW_DEVLOG_FMT_LEN 192
3178
3179 /* maximum number of the formatting string parameters */
3180 #define FW_DEVLOG_FMT_PARAMS_NUM 8
3181
3182 /* priority levels */
3183 enum fw_devlog_level {
3184 FW_DEVLOG_LEVEL_EMERG = 0x0,
3185 FW_DEVLOG_LEVEL_CRIT = 0x1,
3186 FW_DEVLOG_LEVEL_ERR = 0x2,
3187 FW_DEVLOG_LEVEL_NOTICE = 0x3,
3188 FW_DEVLOG_LEVEL_INFO = 0x4,
3189 FW_DEVLOG_LEVEL_DEBUG = 0x5,
3190 FW_DEVLOG_LEVEL_MAX = 0x5,
3191 };
3192
3193 /* facilities that may send a log message */
3194 enum fw_devlog_facility {
3195 FW_DEVLOG_FACILITY_CORE = 0x00,
3196 FW_DEVLOG_FACILITY_CF = 0x01,
3197 FW_DEVLOG_FACILITY_SCHED = 0x02,
3198 FW_DEVLOG_FACILITY_TIMER = 0x04,
3199 FW_DEVLOG_FACILITY_RES = 0x06,
3200 FW_DEVLOG_FACILITY_HW = 0x08,
3201 FW_DEVLOG_FACILITY_FLR = 0x10,
3202 FW_DEVLOG_FACILITY_DMAQ = 0x12,
3203 FW_DEVLOG_FACILITY_PHY = 0x14,
3204 FW_DEVLOG_FACILITY_MAC = 0x16,
3205 FW_DEVLOG_FACILITY_PORT = 0x18,
3206 FW_DEVLOG_FACILITY_VI = 0x1A,
3207 FW_DEVLOG_FACILITY_FILTER = 0x1C,
3208 FW_DEVLOG_FACILITY_ACL = 0x1E,
3209 FW_DEVLOG_FACILITY_TM = 0x20,
3210 FW_DEVLOG_FACILITY_QFC = 0x22,
3211 FW_DEVLOG_FACILITY_DCB = 0x24,
3212 FW_DEVLOG_FACILITY_ETH = 0x26,
3213 FW_DEVLOG_FACILITY_OFLD = 0x28,
3214 FW_DEVLOG_FACILITY_RI = 0x2A,
3215 FW_DEVLOG_FACILITY_ISCSI = 0x2C,
3216 FW_DEVLOG_FACILITY_FCOE = 0x2E,
3217 FW_DEVLOG_FACILITY_FOISCSI = 0x30,
3218 FW_DEVLOG_FACILITY_FOFCOE = 0x32,
3219 FW_DEVLOG_FACILITY_CHNET = 0x34,
3220 FW_DEVLOG_FACILITY_MAX = 0x34,
3221 };
3222
3223 /* log message format */
3224 struct fw_devlog_e {
3225 __be64 timestamp;
3226 __be32 seqno;
3227 __be16 reserved1;
3228 __u8 level;
3229 __u8 facility;
3230 __u8 fmt[FW_DEVLOG_FMT_LEN];
3231 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM];
3232 __be32 reserved3[4];
3233 };
3234
3235 struct fw_devlog_cmd {
3236 __be32 op_to_write;
3237 __be32 retval_len16;
3238 __u8 level;
3239 __u8 r2[7];
3240 __be32 memtype_devlog_memaddr16_devlog;
3241 __be32 memsize_devlog;
3242 __be32 r3[2];
3243 };
3244
3245 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28
3246 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M 0xf
3247 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x) \
3248 (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \
3249 FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M)
3250
3251 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S 0
3252 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M 0xfffffff
3253 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x) \
3254 (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \
3255 FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M)
3256
3257 /* P C I E F W P F 7 R E G I S T E R */
3258
3259 /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to
3260 * access the "devlog" which needing to contact firmware. The encoding is
3261 * mostly the same as that returned by the DEVLOG command except for the size
3262 * which is encoded as the number of entries in multiples-1 of 128 here rather
3263 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128
3264 * and 15 means 2048. This of course in turn constrains the allowed values
3265 * for the devlog size ...
3266 */
3267 #define PCIE_FW_PF_DEVLOG 7
3268
3269 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28
3270 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf
3271 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \
3272 ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S)
3273 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \
3274 (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \
3275 PCIE_FW_PF_DEVLOG_NENTRIES128_M)
3276
3277 #define PCIE_FW_PF_DEVLOG_ADDR16_S 4
3278 #define PCIE_FW_PF_DEVLOG_ADDR16_M 0xffffff
3279 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x) ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S)
3280 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \
3281 (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M)
3282
3283 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S 0
3284 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0xf
3285 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x) ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S)
3286 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \
3287 (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M)
3288
3289 #define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr))
3290
3291 struct fw_crypto_lookaside_wr {
3292 __be32 op_to_cctx_size;
3293 __be32 len16_pkd;
3294 __be32 session_id;
3295 __be32 rx_chid_to_rx_q_id;
3296 __be32 key_addr;
3297 __be32 pld_size_hash_size;
3298 __be64 cookie;
3299 };
3300
3301 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24
3302 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff
3303 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \
3304 ((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S)
3305 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \
3306 (((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \
3307 FW_CRYPTO_LOOKASIDE_WR_OPCODE_M)
3308
3309 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23
3310 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1
3311 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \
3312 ((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S)
3313 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \
3314 (((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \
3315 FW_CRYPTO_LOOKASIDE_WR_COMPL_M)
3316 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U)
3317
3318 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15
3319 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff
3320 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \
3321 ((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S)
3322 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \
3323 (((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \
3324 FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M)
3325
3326 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5
3327 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3
3328 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \
3329 ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S)
3330 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \
3331 (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \
3332 FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M)
3333
3334 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0
3335 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f
3336 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \
3337 ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S)
3338 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \
3339 (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \
3340 FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M)
3341
3342 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0
3343 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff
3344 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \
3345 ((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S)
3346 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \
3347 (((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \
3348 FW_CRYPTO_LOOKASIDE_WR_LEN16_M)
3349
3350 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29
3351 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3
3352 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \
3353 ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S)
3354 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \
3355 (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \
3356 FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M)
3357
3358 #define FW_CRYPTO_LOOKASIDE_WR_LCB_S 27
3359 #define FW_CRYPTO_LOOKASIDE_WR_LCB_M 0x3
3360 #define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \
3361 ((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S)
3362 #define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \
3363 (((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M)
3364
3365 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25
3366 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3
3367 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \
3368 ((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S)
3369 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \
3370 (((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \
3371 FW_CRYPTO_LOOKASIDE_WR_PHASH_M)
3372
3373 #define FW_CRYPTO_LOOKASIDE_WR_IV_S 23
3374 #define FW_CRYPTO_LOOKASIDE_WR_IV_M 0x3
3375 #define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \
3376 ((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S)
3377 #define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \
3378 (((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M)
3379
3380 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10
3381 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3
3382 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \
3383 ((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S)
3384 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \
3385 (((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \
3386 FW_CRYPTO_LOOKASIDE_WR_TX_CH_M)
3387
3388 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0
3389 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff
3390 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \
3391 ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S)
3392 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \
3393 (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \
3394 FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M)
3395
3396 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24
3397 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff
3398 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \
3399 ((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S)
3400 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \
3401 (((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \
3402 FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M)
3403
3404 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17
3405 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f
3406 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \
3407 ((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S)
3408 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \
3409 (((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \
3410 FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M)
3411
3412 #endif /* _T4FW_INTERFACE_H_ */
Linux kernel - Deliverables
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