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arm/xen: fix SMP guests boot
[deliverable/linux.git] / drivers / net / ethernet / hisilicon / hix5hd2_gmac.c
1 /* Copyright (c) 2014 Linaro Ltd.
2 * Copyright (c) 2014 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/etherdevice.h>
13 #include <linux/platform_device.h>
14 #include <linux/of_net.h>
15 #include <linux/of_mdio.h>
16 #include <linux/clk.h>
17 #include <linux/circ_buf.h>
18
19 #define STATION_ADDR_LOW 0x0000
20 #define STATION_ADDR_HIGH 0x0004
21 #define MAC_DUPLEX_HALF_CTRL 0x0008
22 #define MAX_FRM_SIZE 0x003c
23 #define PORT_MODE 0x0040
24 #define PORT_EN 0x0044
25 #define BITS_TX_EN BIT(2)
26 #define BITS_RX_EN BIT(1)
27 #define REC_FILT_CONTROL 0x0064
28 #define BIT_CRC_ERR_PASS BIT(5)
29 #define BIT_PAUSE_FRM_PASS BIT(4)
30 #define BIT_VLAN_DROP_EN BIT(3)
31 #define BIT_BC_DROP_EN BIT(2)
32 #define BIT_MC_MATCH_EN BIT(1)
33 #define BIT_UC_MATCH_EN BIT(0)
34 #define PORT_MC_ADDR_LOW 0x0068
35 #define PORT_MC_ADDR_HIGH 0x006C
36 #define CF_CRC_STRIP 0x01b0
37 #define MODE_CHANGE_EN 0x01b4
38 #define BIT_MODE_CHANGE_EN BIT(0)
39 #define COL_SLOT_TIME 0x01c0
40 #define RECV_CONTROL 0x01e0
41 #define BIT_STRIP_PAD_EN BIT(3)
42 #define BIT_RUNT_PKT_EN BIT(4)
43 #define CONTROL_WORD 0x0214
44 #define MDIO_SINGLE_CMD 0x03c0
45 #define MDIO_SINGLE_DATA 0x03c4
46 #define MDIO_CTRL 0x03cc
47 #define MDIO_RDATA_STATUS 0x03d0
48
49 #define MDIO_START BIT(20)
50 #define MDIO_R_VALID BIT(0)
51 #define MDIO_READ (BIT(17) | MDIO_START)
52 #define MDIO_WRITE (BIT(16) | MDIO_START)
53
54 #define RX_FQ_START_ADDR 0x0500
55 #define RX_FQ_DEPTH 0x0504
56 #define RX_FQ_WR_ADDR 0x0508
57 #define RX_FQ_RD_ADDR 0x050c
58 #define RX_FQ_VLDDESC_CNT 0x0510
59 #define RX_FQ_ALEMPTY_TH 0x0514
60 #define RX_FQ_REG_EN 0x0518
61 #define BITS_RX_FQ_START_ADDR_EN BIT(2)
62 #define BITS_RX_FQ_DEPTH_EN BIT(1)
63 #define BITS_RX_FQ_RD_ADDR_EN BIT(0)
64 #define RX_FQ_ALFULL_TH 0x051c
65 #define RX_BQ_START_ADDR 0x0520
66 #define RX_BQ_DEPTH 0x0524
67 #define RX_BQ_WR_ADDR 0x0528
68 #define RX_BQ_RD_ADDR 0x052c
69 #define RX_BQ_FREE_DESC_CNT 0x0530
70 #define RX_BQ_ALEMPTY_TH 0x0534
71 #define RX_BQ_REG_EN 0x0538
72 #define BITS_RX_BQ_START_ADDR_EN BIT(2)
73 #define BITS_RX_BQ_DEPTH_EN BIT(1)
74 #define BITS_RX_BQ_WR_ADDR_EN BIT(0)
75 #define RX_BQ_ALFULL_TH 0x053c
76 #define TX_BQ_START_ADDR 0x0580
77 #define TX_BQ_DEPTH 0x0584
78 #define TX_BQ_WR_ADDR 0x0588
79 #define TX_BQ_RD_ADDR 0x058c
80 #define TX_BQ_VLDDESC_CNT 0x0590
81 #define TX_BQ_ALEMPTY_TH 0x0594
82 #define TX_BQ_REG_EN 0x0598
83 #define BITS_TX_BQ_START_ADDR_EN BIT(2)
84 #define BITS_TX_BQ_DEPTH_EN BIT(1)
85 #define BITS_TX_BQ_RD_ADDR_EN BIT(0)
86 #define TX_BQ_ALFULL_TH 0x059c
87 #define TX_RQ_START_ADDR 0x05a0
88 #define TX_RQ_DEPTH 0x05a4
89 #define TX_RQ_WR_ADDR 0x05a8
90 #define TX_RQ_RD_ADDR 0x05ac
91 #define TX_RQ_FREE_DESC_CNT 0x05b0
92 #define TX_RQ_ALEMPTY_TH 0x05b4
93 #define TX_RQ_REG_EN 0x05b8
94 #define BITS_TX_RQ_START_ADDR_EN BIT(2)
95 #define BITS_TX_RQ_DEPTH_EN BIT(1)
96 #define BITS_TX_RQ_WR_ADDR_EN BIT(0)
97 #define TX_RQ_ALFULL_TH 0x05bc
98 #define RAW_PMU_INT 0x05c0
99 #define ENA_PMU_INT 0x05c4
100 #define STATUS_PMU_INT 0x05c8
101 #define MAC_FIFO_ERR_IN BIT(30)
102 #define TX_RQ_IN_TIMEOUT_INT BIT(29)
103 #define RX_BQ_IN_TIMEOUT_INT BIT(28)
104 #define TXOUTCFF_FULL_INT BIT(27)
105 #define TXOUTCFF_EMPTY_INT BIT(26)
106 #define TXCFF_FULL_INT BIT(25)
107 #define TXCFF_EMPTY_INT BIT(24)
108 #define RXOUTCFF_FULL_INT BIT(23)
109 #define RXOUTCFF_EMPTY_INT BIT(22)
110 #define RXCFF_FULL_INT BIT(21)
111 #define RXCFF_EMPTY_INT BIT(20)
112 #define TX_RQ_IN_INT BIT(19)
113 #define TX_BQ_OUT_INT BIT(18)
114 #define RX_BQ_IN_INT BIT(17)
115 #define RX_FQ_OUT_INT BIT(16)
116 #define TX_RQ_EMPTY_INT BIT(15)
117 #define TX_RQ_FULL_INT BIT(14)
118 #define TX_RQ_ALEMPTY_INT BIT(13)
119 #define TX_RQ_ALFULL_INT BIT(12)
120 #define TX_BQ_EMPTY_INT BIT(11)
121 #define TX_BQ_FULL_INT BIT(10)
122 #define TX_BQ_ALEMPTY_INT BIT(9)
123 #define TX_BQ_ALFULL_INT BIT(8)
124 #define RX_BQ_EMPTY_INT BIT(7)
125 #define RX_BQ_FULL_INT BIT(6)
126 #define RX_BQ_ALEMPTY_INT BIT(5)
127 #define RX_BQ_ALFULL_INT BIT(4)
128 #define RX_FQ_EMPTY_INT BIT(3)
129 #define RX_FQ_FULL_INT BIT(2)
130 #define RX_FQ_ALEMPTY_INT BIT(1)
131 #define RX_FQ_ALFULL_INT BIT(0)
132
133 #define DEF_INT_MASK (RX_BQ_IN_INT | RX_BQ_IN_TIMEOUT_INT | \
134 TX_RQ_IN_INT | TX_RQ_IN_TIMEOUT_INT)
135
136 #define DESC_WR_RD_ENA 0x05cc
137 #define IN_QUEUE_TH 0x05d8
138 #define OUT_QUEUE_TH 0x05dc
139 #define QUEUE_TX_BQ_SHIFT 16
140 #define RX_BQ_IN_TIMEOUT_TH 0x05e0
141 #define TX_RQ_IN_TIMEOUT_TH 0x05e4
142 #define STOP_CMD 0x05e8
143 #define BITS_TX_STOP BIT(1)
144 #define BITS_RX_STOP BIT(0)
145 #define FLUSH_CMD 0x05eC
146 #define BITS_TX_FLUSH_CMD BIT(5)
147 #define BITS_RX_FLUSH_CMD BIT(4)
148 #define BITS_TX_FLUSH_FLAG_DOWN BIT(3)
149 #define BITS_TX_FLUSH_FLAG_UP BIT(2)
150 #define BITS_RX_FLUSH_FLAG_DOWN BIT(1)
151 #define BITS_RX_FLUSH_FLAG_UP BIT(0)
152 #define RX_CFF_NUM_REG 0x05f0
153 #define PMU_FSM_REG 0x05f8
154 #define RX_FIFO_PKT_IN_NUM 0x05fc
155 #define RX_FIFO_PKT_OUT_NUM 0x0600
156
157 #define RGMII_SPEED_1000 0x2c
158 #define RGMII_SPEED_100 0x2f
159 #define RGMII_SPEED_10 0x2d
160 #define MII_SPEED_100 0x0f
161 #define MII_SPEED_10 0x0d
162 #define GMAC_SPEED_1000 0x05
163 #define GMAC_SPEED_100 0x01
164 #define GMAC_SPEED_10 0x00
165 #define GMAC_FULL_DUPLEX BIT(4)
166
167 #define RX_BQ_INT_THRESHOLD 0x01
168 #define TX_RQ_INT_THRESHOLD 0x01
169 #define RX_BQ_IN_TIMEOUT 0x10000
170 #define TX_RQ_IN_TIMEOUT 0x50000
171
172 #define MAC_MAX_FRAME_SIZE 1600
173 #define DESC_SIZE 32
174 #define RX_DESC_NUM 1024
175 #define TX_DESC_NUM 1024
176
177 #define DESC_VLD_FREE 0
178 #define DESC_VLD_BUSY 0x80000000
179 #define DESC_FL_MID 0
180 #define DESC_FL_LAST 0x20000000
181 #define DESC_FL_FIRST 0x40000000
182 #define DESC_FL_FULL 0x60000000
183 #define DESC_DATA_LEN_OFF 16
184 #define DESC_BUFF_LEN_OFF 0
185 #define DESC_DATA_MASK 0x7ff
186
187 /* DMA descriptor ring helpers */
188 #define dma_ring_incr(n, s) (((n) + 1) & ((s) - 1))
189 #define dma_cnt(n) ((n) >> 5)
190 #define dma_byte(n) ((n) << 5)
191
192 struct hix5hd2_desc {
193 __le32 buff_addr;
194 __le32 cmd;
195 } __aligned(32);
196
197 struct hix5hd2_desc_sw {
198 struct hix5hd2_desc *desc;
199 dma_addr_t phys_addr;
200 unsigned int count;
201 unsigned int size;
202 };
203
204 #define QUEUE_NUMS 4
205 struct hix5hd2_priv {
206 struct hix5hd2_desc_sw pool[QUEUE_NUMS];
207 #define rx_fq pool[0]
208 #define rx_bq pool[1]
209 #define tx_bq pool[2]
210 #define tx_rq pool[3]
211
212 void __iomem *base;
213 void __iomem *ctrl_base;
214
215 struct sk_buff *tx_skb[TX_DESC_NUM];
216 struct sk_buff *rx_skb[RX_DESC_NUM];
217
218 struct device *dev;
219 struct net_device *netdev;
220
221 struct device_node *phy_node;
222 phy_interface_t phy_mode;
223
224 unsigned int speed;
225 unsigned int duplex;
226
227 struct clk *clk;
228 struct mii_bus *bus;
229 struct napi_struct napi;
230 struct work_struct tx_timeout_task;
231 };
232
233 static void hix5hd2_config_port(struct net_device *dev, u32 speed, u32 duplex)
234 {
235 struct hix5hd2_priv *priv = netdev_priv(dev);
236 u32 val;
237
238 priv->speed = speed;
239 priv->duplex = duplex;
240
241 switch (priv->phy_mode) {
242 case PHY_INTERFACE_MODE_RGMII:
243 if (speed == SPEED_1000)
244 val = RGMII_SPEED_1000;
245 else if (speed == SPEED_100)
246 val = RGMII_SPEED_100;
247 else
248 val = RGMII_SPEED_10;
249 break;
250 case PHY_INTERFACE_MODE_MII:
251 if (speed == SPEED_100)
252 val = MII_SPEED_100;
253 else
254 val = MII_SPEED_10;
255 break;
256 default:
257 netdev_warn(dev, "not supported mode\n");
258 val = MII_SPEED_10;
259 break;
260 }
261
262 if (duplex)
263 val |= GMAC_FULL_DUPLEX;
264 writel_relaxed(val, priv->ctrl_base);
265
266 writel_relaxed(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN);
267 if (speed == SPEED_1000)
268 val = GMAC_SPEED_1000;
269 else if (speed == SPEED_100)
270 val = GMAC_SPEED_100;
271 else
272 val = GMAC_SPEED_10;
273 writel_relaxed(val, priv->base + PORT_MODE);
274 writel_relaxed(0, priv->base + MODE_CHANGE_EN);
275 writel_relaxed(duplex, priv->base + MAC_DUPLEX_HALF_CTRL);
276 }
277
278 static void hix5hd2_set_desc_depth(struct hix5hd2_priv *priv, int rx, int tx)
279 {
280 writel_relaxed(BITS_RX_FQ_DEPTH_EN, priv->base + RX_FQ_REG_EN);
281 writel_relaxed(rx << 3, priv->base + RX_FQ_DEPTH);
282 writel_relaxed(0, priv->base + RX_FQ_REG_EN);
283
284 writel_relaxed(BITS_RX_BQ_DEPTH_EN, priv->base + RX_BQ_REG_EN);
285 writel_relaxed(rx << 3, priv->base + RX_BQ_DEPTH);
286 writel_relaxed(0, priv->base + RX_BQ_REG_EN);
287
288 writel_relaxed(BITS_TX_BQ_DEPTH_EN, priv->base + TX_BQ_REG_EN);
289 writel_relaxed(tx << 3, priv->base + TX_BQ_DEPTH);
290 writel_relaxed(0, priv->base + TX_BQ_REG_EN);
291
292 writel_relaxed(BITS_TX_RQ_DEPTH_EN, priv->base + TX_RQ_REG_EN);
293 writel_relaxed(tx << 3, priv->base + TX_RQ_DEPTH);
294 writel_relaxed(0, priv->base + TX_RQ_REG_EN);
295 }
296
297 static void hix5hd2_set_rx_fq(struct hix5hd2_priv *priv, dma_addr_t phy_addr)
298 {
299 writel_relaxed(BITS_RX_FQ_START_ADDR_EN, priv->base + RX_FQ_REG_EN);
300 writel_relaxed(phy_addr, priv->base + RX_FQ_START_ADDR);
301 writel_relaxed(0, priv->base + RX_FQ_REG_EN);
302 }
303
304 static void hix5hd2_set_rx_bq(struct hix5hd2_priv *priv, dma_addr_t phy_addr)
305 {
306 writel_relaxed(BITS_RX_BQ_START_ADDR_EN, priv->base + RX_BQ_REG_EN);
307 writel_relaxed(phy_addr, priv->base + RX_BQ_START_ADDR);
308 writel_relaxed(0, priv->base + RX_BQ_REG_EN);
309 }
310
311 static void hix5hd2_set_tx_bq(struct hix5hd2_priv *priv, dma_addr_t phy_addr)
312 {
313 writel_relaxed(BITS_TX_BQ_START_ADDR_EN, priv->base + TX_BQ_REG_EN);
314 writel_relaxed(phy_addr, priv->base + TX_BQ_START_ADDR);
315 writel_relaxed(0, priv->base + TX_BQ_REG_EN);
316 }
317
318 static void hix5hd2_set_tx_rq(struct hix5hd2_priv *priv, dma_addr_t phy_addr)
319 {
320 writel_relaxed(BITS_TX_RQ_START_ADDR_EN, priv->base + TX_RQ_REG_EN);
321 writel_relaxed(phy_addr, priv->base + TX_RQ_START_ADDR);
322 writel_relaxed(0, priv->base + TX_RQ_REG_EN);
323 }
324
325 static void hix5hd2_set_desc_addr(struct hix5hd2_priv *priv)
326 {
327 hix5hd2_set_rx_fq(priv, priv->rx_fq.phys_addr);
328 hix5hd2_set_rx_bq(priv, priv->rx_bq.phys_addr);
329 hix5hd2_set_tx_rq(priv, priv->tx_rq.phys_addr);
330 hix5hd2_set_tx_bq(priv, priv->tx_bq.phys_addr);
331 }
332
333 static void hix5hd2_hw_init(struct hix5hd2_priv *priv)
334 {
335 u32 val;
336
337 /* disable and clear all interrupts */
338 writel_relaxed(0, priv->base + ENA_PMU_INT);
339 writel_relaxed(~0, priv->base + RAW_PMU_INT);
340
341 writel_relaxed(BIT_CRC_ERR_PASS, priv->base + REC_FILT_CONTROL);
342 writel_relaxed(MAC_MAX_FRAME_SIZE, priv->base + CONTROL_WORD);
343 writel_relaxed(0, priv->base + COL_SLOT_TIME);
344
345 val = RX_BQ_INT_THRESHOLD | TX_RQ_INT_THRESHOLD << QUEUE_TX_BQ_SHIFT;
346 writel_relaxed(val, priv->base + IN_QUEUE_TH);
347
348 writel_relaxed(RX_BQ_IN_TIMEOUT, priv->base + RX_BQ_IN_TIMEOUT_TH);
349 writel_relaxed(TX_RQ_IN_TIMEOUT, priv->base + TX_RQ_IN_TIMEOUT_TH);
350
351 hix5hd2_set_desc_depth(priv, RX_DESC_NUM, TX_DESC_NUM);
352 hix5hd2_set_desc_addr(priv);
353 }
354
355 static void hix5hd2_irq_enable(struct hix5hd2_priv *priv)
356 {
357 writel_relaxed(DEF_INT_MASK, priv->base + ENA_PMU_INT);
358 }
359
360 static void hix5hd2_irq_disable(struct hix5hd2_priv *priv)
361 {
362 writel_relaxed(0, priv->base + ENA_PMU_INT);
363 }
364
365 static void hix5hd2_port_enable(struct hix5hd2_priv *priv)
366 {
367 writel_relaxed(0xf, priv->base + DESC_WR_RD_ENA);
368 writel_relaxed(BITS_RX_EN | BITS_TX_EN, priv->base + PORT_EN);
369 }
370
371 static void hix5hd2_port_disable(struct hix5hd2_priv *priv)
372 {
373 writel_relaxed(~(u32)(BITS_RX_EN | BITS_TX_EN), priv->base + PORT_EN);
374 writel_relaxed(0, priv->base + DESC_WR_RD_ENA);
375 }
376
377 static void hix5hd2_hw_set_mac_addr(struct net_device *dev)
378 {
379 struct hix5hd2_priv *priv = netdev_priv(dev);
380 unsigned char *mac = dev->dev_addr;
381 u32 val;
382
383 val = mac[1] | (mac[0] << 8);
384 writel_relaxed(val, priv->base + STATION_ADDR_HIGH);
385
386 val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
387 writel_relaxed(val, priv->base + STATION_ADDR_LOW);
388 }
389
390 static int hix5hd2_net_set_mac_address(struct net_device *dev, void *p)
391 {
392 int ret;
393
394 ret = eth_mac_addr(dev, p);
395 if (!ret)
396 hix5hd2_hw_set_mac_addr(dev);
397
398 return ret;
399 }
400
401 static void hix5hd2_adjust_link(struct net_device *dev)
402 {
403 struct hix5hd2_priv *priv = netdev_priv(dev);
404 struct phy_device *phy = dev->phydev;
405
406 if ((priv->speed != phy->speed) || (priv->duplex != phy->duplex)) {
407 hix5hd2_config_port(dev, phy->speed, phy->duplex);
408 phy_print_status(phy);
409 }
410 }
411
412 static void hix5hd2_rx_refill(struct hix5hd2_priv *priv)
413 {
414 struct hix5hd2_desc *desc;
415 struct sk_buff *skb;
416 u32 start, end, num, pos, i;
417 u32 len = MAC_MAX_FRAME_SIZE;
418 dma_addr_t addr;
419
420 /* software write pointer */
421 start = dma_cnt(readl_relaxed(priv->base + RX_FQ_WR_ADDR));
422 /* logic read pointer */
423 end = dma_cnt(readl_relaxed(priv->base + RX_FQ_RD_ADDR));
424 num = CIRC_SPACE(start, end, RX_DESC_NUM);
425
426 for (i = 0, pos = start; i < num; i++) {
427 if (priv->rx_skb[pos]) {
428 break;
429 } else {
430 skb = netdev_alloc_skb_ip_align(priv->netdev, len);
431 if (unlikely(skb == NULL))
432 break;
433 }
434
435 addr = dma_map_single(priv->dev, skb->data, len, DMA_FROM_DEVICE);
436 if (dma_mapping_error(priv->dev, addr)) {
437 dev_kfree_skb_any(skb);
438 break;
439 }
440
441 desc = priv->rx_fq.desc + pos;
442 desc->buff_addr = cpu_to_le32(addr);
443 priv->rx_skb[pos] = skb;
444 desc->cmd = cpu_to_le32(DESC_VLD_FREE |
445 (len - 1) << DESC_BUFF_LEN_OFF);
446 pos = dma_ring_incr(pos, RX_DESC_NUM);
447 }
448
449 /* ensure desc updated */
450 wmb();
451
452 if (pos != start)
453 writel_relaxed(dma_byte(pos), priv->base + RX_FQ_WR_ADDR);
454 }
455
456 static int hix5hd2_rx(struct net_device *dev, int limit)
457 {
458 struct hix5hd2_priv *priv = netdev_priv(dev);
459 struct sk_buff *skb;
460 struct hix5hd2_desc *desc;
461 dma_addr_t addr;
462 u32 start, end, num, pos, i, len;
463
464 /* software read pointer */
465 start = dma_cnt(readl_relaxed(priv->base + RX_BQ_RD_ADDR));
466 /* logic write pointer */
467 end = dma_cnt(readl_relaxed(priv->base + RX_BQ_WR_ADDR));
468 num = CIRC_CNT(end, start, RX_DESC_NUM);
469 if (num > limit)
470 num = limit;
471
472 /* ensure get updated desc */
473 rmb();
474 for (i = 0, pos = start; i < num; i++) {
475 skb = priv->rx_skb[pos];
476 if (unlikely(!skb)) {
477 netdev_err(dev, "inconsistent rx_skb\n");
478 break;
479 }
480 priv->rx_skb[pos] = NULL;
481
482 desc = priv->rx_bq.desc + pos;
483 len = (le32_to_cpu(desc->cmd) >> DESC_DATA_LEN_OFF) &
484 DESC_DATA_MASK;
485 addr = le32_to_cpu(desc->buff_addr);
486 dma_unmap_single(priv->dev, addr, MAC_MAX_FRAME_SIZE,
487 DMA_FROM_DEVICE);
488
489 skb_put(skb, len);
490 if (skb->len > MAC_MAX_FRAME_SIZE) {
491 netdev_err(dev, "rcv len err, len = %d\n", skb->len);
492 dev->stats.rx_errors++;
493 dev->stats.rx_length_errors++;
494 dev_kfree_skb_any(skb);
495 goto next;
496 }
497
498 skb->protocol = eth_type_trans(skb, dev);
499 napi_gro_receive(&priv->napi, skb);
500 dev->stats.rx_packets++;
501 dev->stats.rx_bytes += skb->len;
502 next:
503 pos = dma_ring_incr(pos, RX_DESC_NUM);
504 }
505
506 if (pos != start)
507 writel_relaxed(dma_byte(pos), priv->base + RX_BQ_RD_ADDR);
508
509 hix5hd2_rx_refill(priv);
510
511 return num;
512 }
513
514 static void hix5hd2_xmit_reclaim(struct net_device *dev)
515 {
516 struct sk_buff *skb;
517 struct hix5hd2_desc *desc;
518 struct hix5hd2_priv *priv = netdev_priv(dev);
519 unsigned int bytes_compl = 0, pkts_compl = 0;
520 u32 start, end, num, pos, i;
521 dma_addr_t addr;
522
523 netif_tx_lock(dev);
524
525 /* software read */
526 start = dma_cnt(readl_relaxed(priv->base + TX_RQ_RD_ADDR));
527 /* logic write */
528 end = dma_cnt(readl_relaxed(priv->base + TX_RQ_WR_ADDR));
529 num = CIRC_CNT(end, start, TX_DESC_NUM);
530
531 for (i = 0, pos = start; i < num; i++) {
532 skb = priv->tx_skb[pos];
533 if (unlikely(!skb)) {
534 netdev_err(dev, "inconsistent tx_skb\n");
535 break;
536 }
537
538 pkts_compl++;
539 bytes_compl += skb->len;
540 desc = priv->tx_rq.desc + pos;
541 addr = le32_to_cpu(desc->buff_addr);
542 dma_unmap_single(priv->dev, addr, skb->len, DMA_TO_DEVICE);
543 priv->tx_skb[pos] = NULL;
544 dev_consume_skb_any(skb);
545 pos = dma_ring_incr(pos, TX_DESC_NUM);
546 }
547
548 if (pos != start)
549 writel_relaxed(dma_byte(pos), priv->base + TX_RQ_RD_ADDR);
550
551 netif_tx_unlock(dev);
552
553 if (pkts_compl || bytes_compl)
554 netdev_completed_queue(dev, pkts_compl, bytes_compl);
555
556 if (unlikely(netif_queue_stopped(priv->netdev)) && pkts_compl)
557 netif_wake_queue(priv->netdev);
558 }
559
560 static int hix5hd2_poll(struct napi_struct *napi, int budget)
561 {
562 struct hix5hd2_priv *priv = container_of(napi,
563 struct hix5hd2_priv, napi);
564 struct net_device *dev = priv->netdev;
565 int work_done = 0, task = budget;
566 int ints, num;
567
568 do {
569 hix5hd2_xmit_reclaim(dev);
570 num = hix5hd2_rx(dev, task);
571 work_done += num;
572 task -= num;
573 if ((work_done >= budget) || (num == 0))
574 break;
575
576 ints = readl_relaxed(priv->base + RAW_PMU_INT);
577 writel_relaxed(ints, priv->base + RAW_PMU_INT);
578 } while (ints & DEF_INT_MASK);
579
580 if (work_done < budget) {
581 napi_complete(napi);
582 hix5hd2_irq_enable(priv);
583 }
584
585 return work_done;
586 }
587
588 static irqreturn_t hix5hd2_interrupt(int irq, void *dev_id)
589 {
590 struct net_device *dev = (struct net_device *)dev_id;
591 struct hix5hd2_priv *priv = netdev_priv(dev);
592 int ints = readl_relaxed(priv->base + RAW_PMU_INT);
593
594 writel_relaxed(ints, priv->base + RAW_PMU_INT);
595 if (likely(ints & DEF_INT_MASK)) {
596 hix5hd2_irq_disable(priv);
597 napi_schedule(&priv->napi);
598 }
599
600 return IRQ_HANDLED;
601 }
602
603 static int hix5hd2_net_xmit(struct sk_buff *skb, struct net_device *dev)
604 {
605 struct hix5hd2_priv *priv = netdev_priv(dev);
606 struct hix5hd2_desc *desc;
607 dma_addr_t addr;
608 u32 pos;
609
610 /* software write pointer */
611 pos = dma_cnt(readl_relaxed(priv->base + TX_BQ_WR_ADDR));
612 if (unlikely(priv->tx_skb[pos])) {
613 dev->stats.tx_dropped++;
614 dev->stats.tx_fifo_errors++;
615 netif_stop_queue(dev);
616 return NETDEV_TX_BUSY;
617 }
618
619 addr = dma_map_single(priv->dev, skb->data, skb->len, DMA_TO_DEVICE);
620 if (dma_mapping_error(priv->dev, addr)) {
621 dev_kfree_skb_any(skb);
622 return NETDEV_TX_OK;
623 }
624
625 desc = priv->tx_bq.desc + pos;
626 desc->buff_addr = cpu_to_le32(addr);
627 priv->tx_skb[pos] = skb;
628 desc->cmd = cpu_to_le32(DESC_VLD_BUSY | DESC_FL_FULL |
629 (skb->len & DESC_DATA_MASK) << DESC_DATA_LEN_OFF |
630 (skb->len & DESC_DATA_MASK) << DESC_BUFF_LEN_OFF);
631
632 /* ensure desc updated */
633 wmb();
634
635 pos = dma_ring_incr(pos, TX_DESC_NUM);
636 writel_relaxed(dma_byte(pos), priv->base + TX_BQ_WR_ADDR);
637
638 netif_trans_update(dev);
639 dev->stats.tx_packets++;
640 dev->stats.tx_bytes += skb->len;
641 netdev_sent_queue(dev, skb->len);
642
643 return NETDEV_TX_OK;
644 }
645
646 static void hix5hd2_free_dma_desc_rings(struct hix5hd2_priv *priv)
647 {
648 struct hix5hd2_desc *desc;
649 dma_addr_t addr;
650 int i;
651
652 for (i = 0; i < RX_DESC_NUM; i++) {
653 struct sk_buff *skb = priv->rx_skb[i];
654 if (skb == NULL)
655 continue;
656
657 desc = priv->rx_fq.desc + i;
658 addr = le32_to_cpu(desc->buff_addr);
659 dma_unmap_single(priv->dev, addr,
660 MAC_MAX_FRAME_SIZE, DMA_FROM_DEVICE);
661 dev_kfree_skb_any(skb);
662 priv->rx_skb[i] = NULL;
663 }
664
665 for (i = 0; i < TX_DESC_NUM; i++) {
666 struct sk_buff *skb = priv->tx_skb[i];
667 if (skb == NULL)
668 continue;
669
670 desc = priv->tx_rq.desc + i;
671 addr = le32_to_cpu(desc->buff_addr);
672 dma_unmap_single(priv->dev, addr, skb->len, DMA_TO_DEVICE);
673 dev_kfree_skb_any(skb);
674 priv->tx_skb[i] = NULL;
675 }
676 }
677
678 static int hix5hd2_net_open(struct net_device *dev)
679 {
680 struct hix5hd2_priv *priv = netdev_priv(dev);
681 struct phy_device *phy;
682 int ret;
683
684 ret = clk_prepare_enable(priv->clk);
685 if (ret < 0) {
686 netdev_err(dev, "failed to enable clk %d\n", ret);
687 return ret;
688 }
689
690 phy = of_phy_connect(dev, priv->phy_node,
691 &hix5hd2_adjust_link, 0, priv->phy_mode);
692 if (!phy)
693 return -ENODEV;
694
695 phy_start(phy);
696 hix5hd2_hw_init(priv);
697 hix5hd2_rx_refill(priv);
698
699 netdev_reset_queue(dev);
700 netif_start_queue(dev);
701 napi_enable(&priv->napi);
702
703 hix5hd2_port_enable(priv);
704 hix5hd2_irq_enable(priv);
705
706 return 0;
707 }
708
709 static int hix5hd2_net_close(struct net_device *dev)
710 {
711 struct hix5hd2_priv *priv = netdev_priv(dev);
712
713 hix5hd2_port_disable(priv);
714 hix5hd2_irq_disable(priv);
715 napi_disable(&priv->napi);
716 netif_stop_queue(dev);
717 hix5hd2_free_dma_desc_rings(priv);
718
719 if (dev->phydev) {
720 phy_stop(dev->phydev);
721 phy_disconnect(dev->phydev);
722 }
723
724 clk_disable_unprepare(priv->clk);
725
726 return 0;
727 }
728
729 static void hix5hd2_tx_timeout_task(struct work_struct *work)
730 {
731 struct hix5hd2_priv *priv;
732
733 priv = container_of(work, struct hix5hd2_priv, tx_timeout_task);
734 hix5hd2_net_close(priv->netdev);
735 hix5hd2_net_open(priv->netdev);
736 }
737
738 static void hix5hd2_net_timeout(struct net_device *dev)
739 {
740 struct hix5hd2_priv *priv = netdev_priv(dev);
741
742 schedule_work(&priv->tx_timeout_task);
743 }
744
745 static const struct net_device_ops hix5hd2_netdev_ops = {
746 .ndo_open = hix5hd2_net_open,
747 .ndo_stop = hix5hd2_net_close,
748 .ndo_start_xmit = hix5hd2_net_xmit,
749 .ndo_tx_timeout = hix5hd2_net_timeout,
750 .ndo_set_mac_address = hix5hd2_net_set_mac_address,
751 };
752
753 static struct ethtool_ops hix5hd2_ethtools_ops = {
754 .get_link = ethtool_op_get_link,
755 .get_link_ksettings = phy_ethtool_get_link_ksettings,
756 .set_link_ksettings = phy_ethtool_set_link_ksettings,
757 };
758
759 static int hix5hd2_mdio_wait_ready(struct mii_bus *bus)
760 {
761 struct hix5hd2_priv *priv = bus->priv;
762 void __iomem *base = priv->base;
763 int i, timeout = 10000;
764
765 for (i = 0; readl_relaxed(base + MDIO_SINGLE_CMD) & MDIO_START; i++) {
766 if (i == timeout)
767 return -ETIMEDOUT;
768 usleep_range(10, 20);
769 }
770
771 return 0;
772 }
773
774 static int hix5hd2_mdio_read(struct mii_bus *bus, int phy, int reg)
775 {
776 struct hix5hd2_priv *priv = bus->priv;
777 void __iomem *base = priv->base;
778 int val, ret;
779
780 ret = hix5hd2_mdio_wait_ready(bus);
781 if (ret < 0)
782 goto out;
783
784 writel_relaxed(MDIO_READ | phy << 8 | reg, base + MDIO_SINGLE_CMD);
785 ret = hix5hd2_mdio_wait_ready(bus);
786 if (ret < 0)
787 goto out;
788
789 val = readl_relaxed(base + MDIO_RDATA_STATUS);
790 if (val & MDIO_R_VALID) {
791 dev_err(bus->parent, "SMI bus read not valid\n");
792 ret = -ENODEV;
793 goto out;
794 }
795
796 val = readl_relaxed(priv->base + MDIO_SINGLE_DATA);
797 ret = (val >> 16) & 0xFFFF;
798 out:
799 return ret;
800 }
801
802 static int hix5hd2_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
803 {
804 struct hix5hd2_priv *priv = bus->priv;
805 void __iomem *base = priv->base;
806 int ret;
807
808 ret = hix5hd2_mdio_wait_ready(bus);
809 if (ret < 0)
810 goto out;
811
812 writel_relaxed(val, base + MDIO_SINGLE_DATA);
813 writel_relaxed(MDIO_WRITE | phy << 8 | reg, base + MDIO_SINGLE_CMD);
814 ret = hix5hd2_mdio_wait_ready(bus);
815 out:
816 return ret;
817 }
818
819 static void hix5hd2_destroy_hw_desc_queue(struct hix5hd2_priv *priv)
820 {
821 int i;
822
823 for (i = 0; i < QUEUE_NUMS; i++) {
824 if (priv->pool[i].desc) {
825 dma_free_coherent(priv->dev, priv->pool[i].size,
826 priv->pool[i].desc,
827 priv->pool[i].phys_addr);
828 priv->pool[i].desc = NULL;
829 }
830 }
831 }
832
833 static int hix5hd2_init_hw_desc_queue(struct hix5hd2_priv *priv)
834 {
835 struct device *dev = priv->dev;
836 struct hix5hd2_desc *virt_addr;
837 dma_addr_t phys_addr;
838 int size, i;
839
840 priv->rx_fq.count = RX_DESC_NUM;
841 priv->rx_bq.count = RX_DESC_NUM;
842 priv->tx_bq.count = TX_DESC_NUM;
843 priv->tx_rq.count = TX_DESC_NUM;
844
845 for (i = 0; i < QUEUE_NUMS; i++) {
846 size = priv->pool[i].count * sizeof(struct hix5hd2_desc);
847 virt_addr = dma_alloc_coherent(dev, size, &phys_addr,
848 GFP_KERNEL);
849 if (virt_addr == NULL)
850 goto error_free_pool;
851
852 memset(virt_addr, 0, size);
853 priv->pool[i].size = size;
854 priv->pool[i].desc = virt_addr;
855 priv->pool[i].phys_addr = phys_addr;
856 }
857 return 0;
858
859 error_free_pool:
860 hix5hd2_destroy_hw_desc_queue(priv);
861
862 return -ENOMEM;
863 }
864
865 static int hix5hd2_dev_probe(struct platform_device *pdev)
866 {
867 struct device *dev = &pdev->dev;
868 struct device_node *node = dev->of_node;
869 struct net_device *ndev;
870 struct hix5hd2_priv *priv;
871 struct resource *res;
872 struct mii_bus *bus;
873 const char *mac_addr;
874 int ret;
875
876 ndev = alloc_etherdev(sizeof(struct hix5hd2_priv));
877 if (!ndev)
878 return -ENOMEM;
879
880 platform_set_drvdata(pdev, ndev);
881
882 priv = netdev_priv(ndev);
883 priv->dev = dev;
884 priv->netdev = ndev;
885
886 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
887 priv->base = devm_ioremap_resource(dev, res);
888 if (IS_ERR(priv->base)) {
889 ret = PTR_ERR(priv->base);
890 goto out_free_netdev;
891 }
892
893 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
894 priv->ctrl_base = devm_ioremap_resource(dev, res);
895 if (IS_ERR(priv->ctrl_base)) {
896 ret = PTR_ERR(priv->ctrl_base);
897 goto out_free_netdev;
898 }
899
900 priv->clk = devm_clk_get(&pdev->dev, NULL);
901 if (IS_ERR(priv->clk)) {
902 netdev_err(ndev, "failed to get clk\n");
903 ret = -ENODEV;
904 goto out_free_netdev;
905 }
906
907 ret = clk_prepare_enable(priv->clk);
908 if (ret < 0) {
909 netdev_err(ndev, "failed to enable clk %d\n", ret);
910 goto out_free_netdev;
911 }
912
913 bus = mdiobus_alloc();
914 if (bus == NULL) {
915 ret = -ENOMEM;
916 goto out_free_netdev;
917 }
918
919 bus->priv = priv;
920 bus->name = "hix5hd2_mii_bus";
921 bus->read = hix5hd2_mdio_read;
922 bus->write = hix5hd2_mdio_write;
923 bus->parent = &pdev->dev;
924 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev));
925 priv->bus = bus;
926
927 ret = of_mdiobus_register(bus, node);
928 if (ret)
929 goto err_free_mdio;
930
931 priv->phy_mode = of_get_phy_mode(node);
932 if (priv->phy_mode < 0) {
933 netdev_err(ndev, "not find phy-mode\n");
934 ret = -EINVAL;
935 goto err_mdiobus;
936 }
937
938 priv->phy_node = of_parse_phandle(node, "phy-handle", 0);
939 if (!priv->phy_node) {
940 netdev_err(ndev, "not find phy-handle\n");
941 ret = -EINVAL;
942 goto err_mdiobus;
943 }
944
945 ndev->irq = platform_get_irq(pdev, 0);
946 if (ndev->irq <= 0) {
947 netdev_err(ndev, "No irq resource\n");
948 ret = -EINVAL;
949 goto out_phy_node;
950 }
951
952 ret = devm_request_irq(dev, ndev->irq, hix5hd2_interrupt,
953 0, pdev->name, ndev);
954 if (ret) {
955 netdev_err(ndev, "devm_request_irq failed\n");
956 goto out_phy_node;
957 }
958
959 mac_addr = of_get_mac_address(node);
960 if (mac_addr)
961 ether_addr_copy(ndev->dev_addr, mac_addr);
962 if (!is_valid_ether_addr(ndev->dev_addr)) {
963 eth_hw_addr_random(ndev);
964 netdev_warn(ndev, "using random MAC address %pM\n",
965 ndev->dev_addr);
966 }
967
968 INIT_WORK(&priv->tx_timeout_task, hix5hd2_tx_timeout_task);
969 ndev->watchdog_timeo = 6 * HZ;
970 ndev->priv_flags |= IFF_UNICAST_FLT;
971 ndev->netdev_ops = &hix5hd2_netdev_ops;
972 ndev->ethtool_ops = &hix5hd2_ethtools_ops;
973 SET_NETDEV_DEV(ndev, dev);
974
975 ret = hix5hd2_init_hw_desc_queue(priv);
976 if (ret)
977 goto out_phy_node;
978
979 netif_napi_add(ndev, &priv->napi, hix5hd2_poll, NAPI_POLL_WEIGHT);
980 ret = register_netdev(priv->netdev);
981 if (ret) {
982 netdev_err(ndev, "register_netdev failed!");
983 goto out_destroy_queue;
984 }
985
986 clk_disable_unprepare(priv->clk);
987
988 return ret;
989
990 out_destroy_queue:
991 netif_napi_del(&priv->napi);
992 hix5hd2_destroy_hw_desc_queue(priv);
993 out_phy_node:
994 of_node_put(priv->phy_node);
995 err_mdiobus:
996 mdiobus_unregister(bus);
997 err_free_mdio:
998 mdiobus_free(bus);
999 out_free_netdev:
1000 free_netdev(ndev);
1001
1002 return ret;
1003 }
1004
1005 static int hix5hd2_dev_remove(struct platform_device *pdev)
1006 {
1007 struct net_device *ndev = platform_get_drvdata(pdev);
1008 struct hix5hd2_priv *priv = netdev_priv(ndev);
1009
1010 netif_napi_del(&priv->napi);
1011 unregister_netdev(ndev);
1012 mdiobus_unregister(priv->bus);
1013 mdiobus_free(priv->bus);
1014
1015 hix5hd2_destroy_hw_desc_queue(priv);
1016 of_node_put(priv->phy_node);
1017 cancel_work_sync(&priv->tx_timeout_task);
1018 free_netdev(ndev);
1019
1020 return 0;
1021 }
1022
1023 static const struct of_device_id hix5hd2_of_match[] = {
1024 {.compatible = "hisilicon,hix5hd2-gmac",},
1025 {},
1026 };
1027
1028 MODULE_DEVICE_TABLE(of, hix5hd2_of_match);
1029
1030 static struct platform_driver hix5hd2_dev_driver = {
1031 .driver = {
1032 .name = "hix5hd2-gmac",
1033 .of_match_table = hix5hd2_of_match,
1034 },
1035 .probe = hix5hd2_dev_probe,
1036 .remove = hix5hd2_dev_remove,
1037 };
1038
1039 module_platform_driver(hix5hd2_dev_driver);
1040
1041 MODULE_DESCRIPTION("HISILICON HIX5HD2 Ethernet driver");
1042 MODULE_LICENSE("GPL v2");
1043 MODULE_ALIAS("platform:hix5hd2-gmac");
Linux kernel - Deliverables
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