1 /* Intel(R) Ethernet Switch Host Interface Driver
2 * Copyright(c) 2013 - 2016 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
16 * Contact Information:
17 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
18 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
21 #ifndef _FM10K_TYPE_H_
22 #define _FM10K_TYPE_H_
24 /* forward declaration */
27 #include <linux/types.h>
28 #include <asm/byteorder.h>
29 #include <linux/etherdevice.h>
31 #include "fm10k_mbx.h"
33 #define FM10K_DEV_ID_PF 0x15A4
34 #define FM10K_DEV_ID_VF 0x15A5
36 #define FM10K_MAX_QUEUES 256
37 #define FM10K_MAX_QUEUES_PF 128
38 #define FM10K_MAX_QUEUES_POOL 16
40 #define FM10K_48_BIT_MASK 0x0000FFFFFFFFFFFFull
41 #define FM10K_STAT_VALID 0x80000000
44 #define FM10K_PCIE_LINK_CAP 0x7C
45 #define FM10K_PCIE_LINK_STATUS 0x82
46 #define FM10K_PCIE_LINK_WIDTH 0x3F0
47 #define FM10K_PCIE_LINK_WIDTH_1 0x10
48 #define FM10K_PCIE_LINK_WIDTH_2 0x20
49 #define FM10K_PCIE_LINK_WIDTH_4 0x40
50 #define FM10K_PCIE_LINK_WIDTH_8 0x80
51 #define FM10K_PCIE_LINK_SPEED 0xF
52 #define FM10K_PCIE_LINK_SPEED_2500 0x1
53 #define FM10K_PCIE_LINK_SPEED_5000 0x2
54 #define FM10K_PCIE_LINK_SPEED_8000 0x3
56 /* PCIe payload size */
57 #define FM10K_PCIE_DEV_CAP 0x74
58 #define FM10K_PCIE_DEV_CAP_PAYLOAD 0x07
59 #define FM10K_PCIE_DEV_CAP_PAYLOAD_128 0x00
60 #define FM10K_PCIE_DEV_CAP_PAYLOAD_256 0x01
61 #define FM10K_PCIE_DEV_CAP_PAYLOAD_512 0x02
62 #define FM10K_PCIE_DEV_CTRL 0x78
63 #define FM10K_PCIE_DEV_CTRL_PAYLOAD 0xE0
64 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_128 0x00
65 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_256 0x20
66 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_512 0x40
68 /* PCIe MSI-X Capability info */
69 #define FM10K_PCI_MSIX_MSG_CTRL 0xB2
70 #define FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK 0x7FF
71 #define FM10K_MAX_MSIX_VECTORS 256
72 #define FM10K_MAX_VECTORS_PF 256
73 #define FM10K_MAX_VECTORS_POOL 32
75 /* PCIe SR-IOV Info */
76 #define FM10K_PCIE_SRIOV_CTRL 0x190
77 #define FM10K_PCIE_SRIOV_CTRL_VFARI 0x10
79 #define FM10K_ERR_PARAM -2
80 #define FM10K_ERR_NO_RESOURCES -3
81 #define FM10K_ERR_REQUESTS_PENDING -4
82 #define FM10K_ERR_RESET_REQUESTED -5
83 #define FM10K_ERR_DMA_PENDING -6
84 #define FM10K_ERR_RESET_FAILED -7
85 #define FM10K_ERR_INVALID_MAC_ADDR -8
86 #define FM10K_ERR_INVALID_VALUE -9
87 #define FM10K_NOT_IMPLEMENTED 0x7FFFFFFF
89 /* Start of PF registers */
90 #define FM10K_CTRL 0x0000
91 #define FM10K_CTRL_BAR4_ALLOWED 0x00000004
93 #define FM10K_CTRL_EXT 0x0001
94 #define FM10K_GCR 0x0003
95 #define FM10K_GCR_EXT 0x0005
97 /* Interrupt control registers */
98 #define FM10K_EICR 0x0006
99 #define FM10K_EICR_FAULT_MASK 0x0000003F
100 #define FM10K_EICR_MAILBOX 0x00000040
101 #define FM10K_EICR_SWITCHREADY 0x00000080
102 #define FM10K_EICR_SWITCHNOTREADY 0x00000100
103 #define FM10K_EICR_SWITCHINTERRUPT 0x00000200
104 #define FM10K_EICR_VFLR 0x00000800
105 #define FM10K_EICR_MAXHOLDTIME 0x00001000
106 #define FM10K_EIMR 0x0007
107 #define FM10K_EIMR_PCA_FAULT 0x00000001
108 #define FM10K_EIMR_THI_FAULT 0x00000010
109 #define FM10K_EIMR_FUM_FAULT 0x00000400
110 #define FM10K_EIMR_MAILBOX 0x00001000
111 #define FM10K_EIMR_SWITCHREADY 0x00004000
112 #define FM10K_EIMR_SWITCHNOTREADY 0x00010000
113 #define FM10K_EIMR_SWITCHINTERRUPT 0x00040000
114 #define FM10K_EIMR_SRAMERROR 0x00100000
115 #define FM10K_EIMR_VFLR 0x00400000
116 #define FM10K_EIMR_MAXHOLDTIME 0x01000000
117 #define FM10K_EIMR_ALL 0x55555555
118 #define FM10K_EIMR_DISABLE(NAME) ((FM10K_EIMR_ ## NAME) << 0)
119 #define FM10K_EIMR_ENABLE(NAME) ((FM10K_EIMR_ ## NAME) << 1)
120 #define FM10K_FAULT_ADDR_LO 0x0
121 #define FM10K_FAULT_ADDR_HI 0x1
122 #define FM10K_FAULT_SPECINFO 0x2
123 #define FM10K_FAULT_FUNC 0x3
124 #define FM10K_FAULT_SIZE 0x4
125 #define FM10K_FAULT_FUNC_VALID 0x00008000
126 #define FM10K_FAULT_FUNC_PF 0x00004000
127 #define FM10K_FAULT_FUNC_VF_MASK 0x00003F00
128 #define FM10K_FAULT_FUNC_VF_SHIFT 8
129 #define FM10K_FAULT_FUNC_TYPE_MASK 0x000000FF
131 #define FM10K_PCA_FAULT 0x0008
132 #define FM10K_THI_FAULT 0x0010
133 #define FM10K_FUM_FAULT 0x001C
135 /* Rx queue timeout indicator */
136 #define FM10K_MAXHOLDQ(_n) ((_n) + 0x0020)
138 /* Switch Manager info */
139 #define FM10K_SM_AREA(_n) ((_n) + 0x0028)
141 /* GLORT mapping registers */
142 #define FM10K_DGLORTMAP(_n) ((_n) + 0x0030)
143 #define FM10K_DGLORT_COUNT 8
144 #define FM10K_DGLORTMAP_MASK_SHIFT 16
145 #define FM10K_DGLORTMAP_ANY 0x00000000
146 #define FM10K_DGLORTMAP_NONE 0x0000FFFF
147 #define FM10K_DGLORTMAP_ZERO 0xFFFF0000
148 #define FM10K_DGLORTDEC(_n) ((_n) + 0x0038)
149 #define FM10K_DGLORTDEC_VSILENGTH_SHIFT 4
150 #define FM10K_DGLORTDEC_VSIBASE_SHIFT 7
151 #define FM10K_DGLORTDEC_PCLENGTH_SHIFT 14
152 #define FM10K_DGLORTDEC_QBASE_SHIFT 16
153 #define FM10K_DGLORTDEC_RSSLENGTH_SHIFT 24
154 #define FM10K_DGLORTDEC_INNERRSS_ENABLE 0x08000000
155 #define FM10K_TUNNEL_CFG 0x0040
156 #define FM10K_TUNNEL_CFG_NVGRE_SHIFT 16
157 #define FM10K_SWPRI_MAP(_n) ((_n) + 0x0050)
158 #define FM10K_SWPRI_MAX 16
159 #define FM10K_RSSRK(_n, _m) (((_n) * 0x10) + (_m) + 0x0800)
160 #define FM10K_RSSRK_SIZE 10
161 #define FM10K_RSSRK_ENTRIES_PER_REG 4
162 #define FM10K_RETA(_n, _m) (((_n) * 0x20) + (_m) + 0x1000)
163 #define FM10K_RETA_SIZE 32
164 #define FM10K_RETA_ENTRIES_PER_REG 4
165 #define FM10K_MAX_RSS_INDICES 128
167 /* Rate limiting registers */
168 #define FM10K_TC_CREDIT(_n) ((_n) + 0x2000)
169 #define FM10K_TC_CREDIT_CREDIT_MASK 0x001FFFFF
170 #define FM10K_TC_MAXCREDIT(_n) ((_n) + 0x2040)
171 #define FM10K_TC_MAXCREDIT_64K 0x00010000
172 #define FM10K_TC_RATE(_n) ((_n) + 0x2080)
173 #define FM10K_TC_RATE_QUANTA_MASK 0x0000FFFF
174 #define FM10K_TC_RATE_INTERVAL_4US_GEN1 0x00020000
175 #define FM10K_TC_RATE_INTERVAL_4US_GEN2 0x00040000
176 #define FM10K_TC_RATE_INTERVAL_4US_GEN3 0x00080000
178 /* DMA control registers */
179 #define FM10K_DMA_CTRL 0x20C3
180 #define FM10K_DMA_CTRL_TX_ENABLE 0x00000001
181 #define FM10K_DMA_CTRL_TX_ACTIVE 0x00000008
182 #define FM10K_DMA_CTRL_RX_ENABLE 0x00000010
183 #define FM10K_DMA_CTRL_RX_ACTIVE 0x00000080
184 #define FM10K_DMA_CTRL_RX_DESC_SIZE 0x00000100
185 #define FM10K_DMA_CTRL_MINMSS_64 0x00008000
186 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3 0x04800000
187 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2 0x04000000
188 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1 0x03800000
189 #define FM10K_DMA_CTRL_DATAPATH_RESET 0x20000000
190 #define FM10K_DMA_CTRL_32_DESC 0x00000000
192 #define FM10K_DMA_CTRL2 0x20C4
193 #define FM10K_DMA_CTRL2_SWITCH_READY 0x00002000
195 /* TSO flags configuration
196 * First packet contains all flags except for fin and psh
197 * Middle packet contains only urg and ack
198 * Last packet contains urg, ack, fin, and psh
200 #define FM10K_TSO_FLAGS_LOW 0x00300FF6
201 #define FM10K_TSO_FLAGS_HI 0x00000039
202 #define FM10K_DTXTCPFLGL 0x20C5
203 #define FM10K_DTXTCPFLGH 0x20C6
205 #define FM10K_TPH_CTRL 0x20C7
206 #define FM10K_MRQC(_n) ((_n) + 0x2100)
207 #define FM10K_MRQC_TCP_IPV4 0x00000001
208 #define FM10K_MRQC_IPV4 0x00000002
209 #define FM10K_MRQC_IPV6 0x00000010
210 #define FM10K_MRQC_TCP_IPV6 0x00000020
211 #define FM10K_MRQC_UDP_IPV4 0x00000040
212 #define FM10K_MRQC_UDP_IPV6 0x00000080
214 #define FM10K_TQMAP(_n) ((_n) + 0x2800)
215 #define FM10K_TQMAP_TABLE_SIZE 2048
216 #define FM10K_RQMAP(_n) ((_n) + 0x3000)
218 /* Hardware Statistics */
219 #define FM10K_STATS_TIMEOUT 0x3800
220 #define FM10K_STATS_UR 0x3801
221 #define FM10K_STATS_CA 0x3802
222 #define FM10K_STATS_UM 0x3803
223 #define FM10K_STATS_XEC 0x3804
224 #define FM10K_STATS_VLAN_DROP 0x3805
225 #define FM10K_STATS_LOOPBACK_DROP 0x3806
226 #define FM10K_STATS_NODESC_DROP 0x3807
228 /* PCIe state registers */
229 #define FM10K_PHYADDR 0x381C
231 /* Rx ring registers */
232 #define FM10K_RDBAL(_n) ((0x40 * (_n)) + 0x4000)
233 #define FM10K_RDBAH(_n) ((0x40 * (_n)) + 0x4001)
234 #define FM10K_RDLEN(_n) ((0x40 * (_n)) + 0x4002)
235 #define FM10K_TPH_RXCTRL(_n) ((0x40 * (_n)) + 0x4003)
236 #define FM10K_TPH_RXCTRL_DESC_TPHEN 0x00000020
237 #define FM10K_TPH_RXCTRL_DESC_RROEN 0x00000200
238 #define FM10K_TPH_RXCTRL_DATA_WROEN 0x00002000
239 #define FM10K_TPH_RXCTRL_HDR_WROEN 0x00008000
240 #define FM10K_RDH(_n) ((0x40 * (_n)) + 0x4004)
241 #define FM10K_RDT(_n) ((0x40 * (_n)) + 0x4005)
242 #define FM10K_RXQCTL(_n) ((0x40 * (_n)) + 0x4006)
243 #define FM10K_RXQCTL_ENABLE 0x00000001
244 #define FM10K_RXQCTL_PF 0x000000FC
245 #define FM10K_RXQCTL_VF_SHIFT 2
246 #define FM10K_RXQCTL_VF 0x00000100
247 #define FM10K_RXQCTL_ID_MASK (FM10K_RXQCTL_PF | FM10K_RXQCTL_VF)
248 #define FM10K_RXDCTL(_n) ((0x40 * (_n)) + 0x4007)
249 #define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY 0x00000001
250 #define FM10K_RXDCTL_DROP_ON_EMPTY 0x00000200
251 #define FM10K_RXINT(_n) ((0x40 * (_n)) + 0x4008)
252 #define FM10K_SRRCTL(_n) ((0x40 * (_n)) + 0x4009)
253 #define FM10K_SRRCTL_BSIZEPKT_SHIFT 8 /* shift _right_ */
254 #define FM10K_SRRCTL_LOOPBACK_SUPPRESS 0x40000000
255 #define FM10K_SRRCTL_BUFFER_CHAINING_EN 0x80000000
258 #define FM10K_QPRC(_n) ((0x40 * (_n)) + 0x400A)
259 #define FM10K_QPRDC(_n) ((0x40 * (_n)) + 0x400B)
260 #define FM10K_QBRC_L(_n) ((0x40 * (_n)) + 0x400C)
261 #define FM10K_QBRC_H(_n) ((0x40 * (_n)) + 0x400D)
263 /* Rx GLORT register */
264 #define FM10K_RX_SGLORT(_n) ((0x40 * (_n)) + 0x400E)
266 /* Tx ring registers */
267 #define FM10K_TDBAL(_n) ((0x40 * (_n)) + 0x8000)
268 #define FM10K_TDBAH(_n) ((0x40 * (_n)) + 0x8001)
269 #define FM10K_TDLEN(_n) ((0x40 * (_n)) + 0x8002)
270 /* When fist initialized, VFs need to know the Interrupt Throttle Rate (ITR)
271 * scale which is based on the PCIe speed but the speed information in the PCI
272 * configuration space may not be accurate. The PF already knows the ITR scale
273 * but there is no defined method to pass that information from the PF to the
274 * VF. This is accomplished during VF initialization by temporarily co-opting
275 * the yet-to-be-used TDLEN register to have the PF store the ITR shift for
276 * the VF to retrieve before the VF needs to use the TDLEN register for its
277 * intended purpose, i.e. before the Tx resources are allocated.
279 #define FM10K_TDLEN_ITR_SCALE_SHIFT 9
280 #define FM10K_TDLEN_ITR_SCALE_MASK 0x00000E00
281 #define FM10K_TDLEN_ITR_SCALE_GEN1 2
282 #define FM10K_TDLEN_ITR_SCALE_GEN2 1
283 #define FM10K_TDLEN_ITR_SCALE_GEN3 0
284 #define FM10K_TPH_TXCTRL(_n) ((0x40 * (_n)) + 0x8003)
285 #define FM10K_TPH_TXCTRL_DESC_TPHEN 0x00000020
286 #define FM10K_TPH_TXCTRL_DESC_RROEN 0x00000200
287 #define FM10K_TPH_TXCTRL_DESC_WROEN 0x00000800
288 #define FM10K_TPH_TXCTRL_DATA_RROEN 0x00002000
289 #define FM10K_TDH(_n) ((0x40 * (_n)) + 0x8004)
290 #define FM10K_TDT(_n) ((0x40 * (_n)) + 0x8005)
291 #define FM10K_TXDCTL(_n) ((0x40 * (_n)) + 0x8006)
292 #define FM10K_TXDCTL_ENABLE 0x00004000
293 #define FM10K_TXDCTL_MAX_TIME_SHIFT 16
294 #define FM10K_TXQCTL(_n) ((0x40 * (_n)) + 0x8007)
295 #define FM10K_TXQCTL_PF 0x0000003F
296 #define FM10K_TXQCTL_VF 0x00000040
297 #define FM10K_TXQCTL_ID_MASK (FM10K_TXQCTL_PF | FM10K_TXQCTL_VF)
298 #define FM10K_TXQCTL_PC_SHIFT 7
299 #define FM10K_TXQCTL_PC_MASK 0x00000380
300 #define FM10K_TXQCTL_TC_SHIFT 10
301 #define FM10K_TXQCTL_VID_SHIFT 16
302 #define FM10K_TXQCTL_VID_MASK 0x0FFF0000
303 #define FM10K_TXQCTL_UNLIMITED_BW 0x10000000
304 #define FM10K_TXINT(_n) ((0x40 * (_n)) + 0x8008)
307 #define FM10K_QPTC(_n) ((0x40 * (_n)) + 0x8009)
308 #define FM10K_QBTC_L(_n) ((0x40 * (_n)) + 0x800A)
309 #define FM10K_QBTC_H(_n) ((0x40 * (_n)) + 0x800B)
311 /* Tx Push registers */
312 #define FM10K_TQDLOC(_n) ((0x40 * (_n)) + 0x800C)
313 #define FM10K_TQDLOC_BASE_32_DESC 0x08
314 #define FM10K_TQDLOC_SIZE_32_DESC 0x00050000
316 /* Tx GLORT registers */
317 #define FM10K_TX_SGLORT(_n) ((0x40 * (_n)) + 0x800D)
318 #define FM10K_PFVTCTL(_n) ((0x40 * (_n)) + 0x800E)
319 #define FM10K_PFVTCTL_FTAG_DESC_ENABLE 0x00000001
321 /* Interrupt moderation and control registers */
322 #define FM10K_INT_MAP(_n) ((_n) + 0x10080)
323 #define FM10K_INT_MAP_TIMER0 0x00000000
324 #define FM10K_INT_MAP_TIMER1 0x00000100
325 #define FM10K_INT_MAP_IMMEDIATE 0x00000200
326 #define FM10K_INT_MAP_DISABLE 0x00000300
327 #define FM10K_MSIX_VECTOR_MASK(_n) ((0x4 * (_n)) + 0x11003)
328 #define FM10K_INT_CTRL 0x12000
329 #define FM10K_INT_CTRL_ENABLEMODERATOR 0x00000400
330 #define FM10K_ITR(_n) ((_n) + 0x12400)
331 #define FM10K_ITR_INTERVAL1_SHIFT 12
332 #define FM10K_ITR_PENDING2 0x10000000
333 #define FM10K_ITR_AUTOMASK 0x20000000
334 #define FM10K_ITR_MASK_SET 0x40000000
335 #define FM10K_ITR_MASK_CLEAR 0x80000000
336 #define FM10K_ITR2(_n) ((0x2 * (_n)) + 0x12800)
337 #define FM10K_ITR_REG_COUNT 768
338 #define FM10K_ITR_REG_COUNT_PF 256
340 /* Switch manager interrupt registers */
341 #define FM10K_IP 0x13000
342 #define FM10K_IP_NOTINRESET 0x00000100
345 #define FM10K_VLAN_TABLE(_n, _m) ((0x80 * (_n)) + (_m) + 0x14000)
346 #define FM10K_VLAN_TABLE_SIZE 128
348 /* VLAN specific message offsets */
349 #define FM10K_VLAN_TABLE_VID_MAX 4096
350 #define FM10K_VLAN_TABLE_VSI_MAX 64
351 #define FM10K_VLAN_LENGTH_SHIFT 16
352 #define FM10K_VLAN_CLEAR BIT(15)
353 #define FM10K_VLAN_OVERRIDE FM10K_VLAN_CLEAR
354 #define FM10K_VLAN_ALL \
355 ((FM10K_VLAN_TABLE_VID_MAX - 1) << FM10K_VLAN_LENGTH_SHIFT)
357 /* VF FLR event notification registers */
358 #define FM10K_PFVFLRE(_n) ((0x1 * (_n)) + 0x18844)
359 #define FM10K_PFVFLREC(_n) ((0x1 * (_n)) + 0x18846)
361 /* Defines for size of uncacheable memories */
362 #define FM10K_UC_ADDR_START 0x000000 /* start of standard regs */
363 #define FM10K_UC_ADDR_END 0x100000 /* end of standard regs */
364 #define FM10K_UC_ADDR_SIZE (FM10K_UC_ADDR_END - FM10K_UC_ADDR_START)
366 /* Define timeouts for resets and disables */
367 #define FM10K_QUEUE_DISABLE_TIMEOUT 100
368 #define FM10K_RESET_TIMEOUT 150
370 /* Maximum supported combined inner and outer header length for encapsulation */
371 #define FM10K_TUNNEL_HEADER_LENGTH 184
374 #define FM10K_VFCTRL 0x00000
375 #define FM10K_VFCTRL_RST 0x00000008
376 #define FM10K_VFINT_MAP 0x00030
377 #define FM10K_VFSYSTIME 0x00040
378 #define FM10K_VFITR(_n) ((_n) + 0x00060)
380 enum fm10k_int_source
{
381 fm10k_int_mailbox
= 0,
382 fm10k_int_pcie_fault
= 1,
383 fm10k_int_switch_up_down
= 2,
384 fm10k_int_switch_event
= 3,
387 fm10k_int_max_hold_time
= 6,
388 fm10k_int_sources_max_pf
391 /* PCIe bus speeds */
392 enum fm10k_bus_speed
{
393 fm10k_bus_speed_unknown
= 0,
394 fm10k_bus_speed_2500
= 2500,
395 fm10k_bus_speed_5000
= 5000,
396 fm10k_bus_speed_8000
= 8000,
397 fm10k_bus_speed_reserved
400 /* PCIe bus widths */
401 enum fm10k_bus_width
{
402 fm10k_bus_width_unknown
= 0,
403 fm10k_bus_width_pcie_x1
= 1,
404 fm10k_bus_width_pcie_x2
= 2,
405 fm10k_bus_width_pcie_x4
= 4,
406 fm10k_bus_width_pcie_x8
= 8,
407 fm10k_bus_width_reserved
410 /* PCIe payload sizes */
411 enum fm10k_bus_payload
{
412 fm10k_bus_payload_unknown
= 0,
413 fm10k_bus_payload_128
= 1,
414 fm10k_bus_payload_256
= 2,
415 fm10k_bus_payload_512
= 3,
416 fm10k_bus_payload_reserved
420 struct fm10k_bus_info
{
421 enum fm10k_bus_speed speed
;
422 enum fm10k_bus_width width
;
423 enum fm10k_bus_payload payload
;
426 /* Statistics related declarations */
427 struct fm10k_hw_stat
{
433 struct fm10k_hw_stats_q
{
434 struct fm10k_hw_stat tx_bytes
;
435 struct fm10k_hw_stat tx_packets
;
436 #define tx_stats_idx tx_packets.base_h
437 struct fm10k_hw_stat rx_bytes
;
438 struct fm10k_hw_stat rx_packets
;
439 #define rx_stats_idx rx_packets.base_h
440 struct fm10k_hw_stat rx_drops
;
443 struct fm10k_hw_stats
{
444 struct fm10k_hw_stat timeout
;
445 #define stats_idx timeout.base_h
446 struct fm10k_hw_stat ur
;
447 struct fm10k_hw_stat ca
;
448 struct fm10k_hw_stat um
;
449 struct fm10k_hw_stat xec
;
450 struct fm10k_hw_stat vlan_drop
;
451 struct fm10k_hw_stat loopback_drop
;
452 struct fm10k_hw_stat nodesc_drop
;
453 struct fm10k_hw_stats_q q
[FM10K_MAX_QUEUES_PF
];
456 /* Establish DGLORT feature priority */
457 enum fm10k_dglortdec_idx
{
458 fm10k_dglort_default
= 0,
459 fm10k_dglort_vf_rsvd0
= 1,
460 fm10k_dglort_vf_rss
= 2,
461 fm10k_dglort_pf_rsvd0
= 3,
462 fm10k_dglort_pf_queue
= 4,
463 fm10k_dglort_pf_vsi
= 5,
464 fm10k_dglort_pf_rsvd1
= 6,
465 fm10k_dglort_pf_rss
= 7
468 struct fm10k_dglort_cfg
{
469 u16 glort
; /* GLORT base */
470 u16 queue_b
; /* Base value for queue */
471 u8 vsi_b
; /* Base value for VSI */
472 u8 idx
; /* index of DGLORTDEC entry */
473 u8 rss_l
; /* RSS indices */
474 u8 pc_l
; /* Priority Class indices */
475 u8 vsi_l
; /* Number of bits from GLORT used to determine VSI */
476 u8 queue_l
; /* Number of bits from GLORT used to determine queue */
477 u8 shared_l
; /* Ignored bits from GLORT resulting in shared VSI */
478 u8 inner_rss
; /* Boolean value if inner header is used for RSS */
481 enum fm10k_pca_fault
{
492 enum fm10k_thi_fault
{
498 enum fm10k_fum_fault
{
515 u64 address
; /* Address at the time fault was detected */
516 u32 specinfo
; /* Extra info on this fault (fault dependent) */
517 u8 type
; /* Fault value dependent on subunit */
518 u8 func
; /* Function number of the fault */
521 struct fm10k_mac_ops
{
522 /* basic bring-up and tear-down */
523 s32 (*reset_hw
)(struct fm10k_hw
*);
524 s32 (*init_hw
)(struct fm10k_hw
*);
525 s32 (*start_hw
)(struct fm10k_hw
*);
526 s32 (*stop_hw
)(struct fm10k_hw
*);
527 s32 (*get_bus_info
)(struct fm10k_hw
*);
528 s32 (*get_host_state
)(struct fm10k_hw
*, bool *);
529 s32 (*request_lport_map
)(struct fm10k_hw
*);
530 s32 (*update_vlan
)(struct fm10k_hw
*, u32
, u8
, bool);
531 s32 (*read_mac_addr
)(struct fm10k_hw
*);
532 s32 (*update_uc_addr
)(struct fm10k_hw
*, u16
, const u8
*,
534 s32 (*update_mc_addr
)(struct fm10k_hw
*, u16
, const u8
*, u16
, bool);
535 s32 (*update_xcast_mode
)(struct fm10k_hw
*, u16
, u8
);
536 void (*update_int_moderator
)(struct fm10k_hw
*);
537 s32 (*update_lport_state
)(struct fm10k_hw
*, u16
, u16
, bool);
538 void (*update_hw_stats
)(struct fm10k_hw
*, struct fm10k_hw_stats
*);
539 void (*rebind_hw_stats
)(struct fm10k_hw
*, struct fm10k_hw_stats
*);
540 s32 (*configure_dglort_map
)(struct fm10k_hw
*,
541 struct fm10k_dglort_cfg
*);
542 void (*set_dma_mask
)(struct fm10k_hw
*, u64
);
543 s32 (*get_fault
)(struct fm10k_hw
*, int, struct fm10k_fault
*);
546 enum fm10k_mac_type
{
547 fm10k_mac_unknown
= 0,
553 struct fm10k_mac_info
{
554 struct fm10k_mac_ops ops
;
555 enum fm10k_mac_type type
;
557 u8 perm_addr
[ETH_ALEN
];
559 u16 max_msix_vectors
;
566 u64 reset_while_pending
;
569 struct fm10k_swapi_table_info
{
574 struct fm10k_swapi_info
{
576 struct fm10k_swapi_table_info mac
;
577 struct fm10k_swapi_table_info nexthop
;
578 struct fm10k_swapi_table_info ffu
;
581 enum fm10k_xcast_modes
{
582 FM10K_XCAST_MODE_ALLMULTI
= 0,
583 FM10K_XCAST_MODE_MULTI
= 1,
584 FM10K_XCAST_MODE_PROMISC
= 2,
585 FM10K_XCAST_MODE_NONE
= 3,
586 FM10K_XCAST_MODE_DISABLE
= 4
589 #define FM10K_VF_TC_MAX 100000 /* 100,000 Mb/s aka 100Gb/s */
590 #define FM10K_VF_TC_MIN 1 /* 1 Mb/s is the slowest rate */
592 struct fm10k_vf_info
{
593 /* mbx must be first field in struct unless all default IOV message
594 * handlers are redone as the assumption is that vf_info starts
595 * at the same offset as the mailbox
597 struct fm10k_mbx_info mbx
; /* PF side of VF mailbox */
598 int rate
; /* Tx BW cap as defined by OS */
599 u16 glort
; /* resource tag for this VF */
600 u16 sw_vid
; /* Switch API assigned VLAN */
601 u16 pf_vid
; /* PF assigned Default VLAN */
602 u8 mac
[ETH_ALEN
]; /* PF Default MAC address */
603 u8 vsi
; /* VSI identifier */
604 u8 vf_idx
; /* which VF this is */
605 u8 vf_flags
; /* flags indicating what modes
606 * are supported for the port
610 #define FM10K_VF_FLAG_ALLMULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_ALLMULTI))
611 #define FM10K_VF_FLAG_MULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_MULTI))
612 #define FM10K_VF_FLAG_PROMISC_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_PROMISC))
613 #define FM10K_VF_FLAG_NONE_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_NONE))
614 #define FM10K_VF_FLAG_CAPABLE(vf_info) ((vf_info)->vf_flags & (u8)0xF)
615 #define FM10K_VF_FLAG_ENABLED(vf_info) ((vf_info)->vf_flags >> 4)
616 #define FM10K_VF_FLAG_SET_MODE(mode) ((u8)0x10 << (mode))
617 #define FM10K_VF_FLAG_SET_MODE_NONE \
618 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_NONE)
619 #define FM10K_VF_FLAG_MULTI_ENABLED \
620 (FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_ALLMULTI) | \
621 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_MULTI) | \
622 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_PROMISC))
624 struct fm10k_iov_ops
{
625 /* IOV related bring-up and tear-down */
626 s32 (*assign_resources
)(struct fm10k_hw
*, u16
, u16
);
627 s32 (*configure_tc
)(struct fm10k_hw
*, u16
, int);
628 s32 (*assign_int_moderator
)(struct fm10k_hw
*, u16
);
629 s32 (*assign_default_mac_vlan
)(struct fm10k_hw
*,
630 struct fm10k_vf_info
*);
631 s32 (*reset_resources
)(struct fm10k_hw
*,
632 struct fm10k_vf_info
*);
633 s32 (*set_lport
)(struct fm10k_hw
*, struct fm10k_vf_info
*, u16
, u8
);
634 void (*reset_lport
)(struct fm10k_hw
*, struct fm10k_vf_info
*);
635 void (*update_stats
)(struct fm10k_hw
*, struct fm10k_hw_stats_q
*, u16
);
638 struct fm10k_iov_info
{
639 struct fm10k_iov_ops ops
;
651 enum fm10k_mac_type mac
;
652 s32 (*get_invariants
)(struct fm10k_hw
*);
653 const struct fm10k_mac_ops
*mac_ops
;
654 const struct fm10k_iov_ops
*iov_ops
;
658 u32 __iomem
*hw_addr
;
660 struct fm10k_mac_info mac
;
661 struct fm10k_bus_info bus
;
662 struct fm10k_bus_info bus_caps
;
663 struct fm10k_iov_info iov
;
664 struct fm10k_mbx_info mbx
;
665 struct fm10k_swapi_info swapi
;
668 u16 subsystem_device_id
;
669 u16 subsystem_vendor_id
;
673 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
674 #define FM10K_REQ_TX_DESCRIPTOR_MULTIPLE 8
675 #define FM10K_REQ_RX_DESCRIPTOR_MULTIPLE 8
677 /* Transmit Descriptor */
678 struct fm10k_tx_desc
{
679 __le64 buffer_addr
; /* Address of the descriptor's data buffer */
680 __le16 buflen
; /* Length of data to be DMAed */
681 __le16 vlan
; /* VLAN_ID and VPRI to be inserted in FTAG */
682 __le16 mss
; /* MSS for segmentation offload */
683 u8 hdrlen
; /* Header size for segmentation offload */
684 u8 flags
; /* Status and offload request flags */
687 /* Transmit Descriptor Cache Structure */
688 struct fm10k_tx_desc_cache
{
689 struct fm10k_tx_desc tx_desc
[256];
692 #define FM10K_TXD_FLAG_INT 0x01
693 #define FM10K_TXD_FLAG_TIME 0x02
694 #define FM10K_TXD_FLAG_CSUM 0x04
695 #define FM10K_TXD_FLAG_FTAG 0x10
696 #define FM10K_TXD_FLAG_RS 0x20
697 #define FM10K_TXD_FLAG_LAST 0x40
698 #define FM10K_TXD_FLAG_DONE 0x80
700 /* These macros are meant to enable optimal placement of the RS and INT
701 * bits. It will point us to the last descriptor in the cache for either the
702 * start of the packet, or the end of the packet. If the index is actually
703 * at the start of the FIFO it will point to the offset for the last index
704 * in the FIFO to prevent an unnecessary write.
706 #define FM10K_TXD_WB_FIFO_SIZE 4
708 /* Receive Descriptor - 32B */
709 union fm10k_rx_desc
{
711 __le64 pkt_addr
; /* Packet buffer address */
712 __le64 hdr_addr
; /* Header buffer address */
713 __le64 reserved
; /* Empty space, RSS hash */
715 } q
; /* Read, Writeback, 64b quad-words */
717 __le32 data
; /* RSS and header data */
718 __le32 rss
; /* RSS Hash */
721 __le32 glort
; /* sglort/dglort */
722 } d
; /* Writeback, 32b double-words */
724 __le16 pkt_info
; /* RSS, Pkt type */
725 __le16 hdr_info
; /* Splithdr, hdrlen, xC */
728 __le16 status
; /* status/error */
729 __le16 csum_err
; /* checksum or extended error value */
730 __le16 length
; /* Packet length */
731 __le16 vlan
; /* VLAN tag */
734 } w
; /* Writeback, 16b words */
737 #define FM10K_RXD_RSSTYPE_MASK 0x000F
738 enum fm10k_rdesc_rss_type
{
739 FM10K_RSSTYPE_NONE
= 0x0,
740 FM10K_RSSTYPE_IPV4_TCP
= 0x1,
741 FM10K_RSSTYPE_IPV4
= 0x2,
742 FM10K_RSSTYPE_IPV6_TCP
= 0x3,
744 FM10K_RSSTYPE_IPV6
= 0x5,
746 FM10K_RSSTYPE_IPV4_UDP
= 0x7,
747 FM10K_RSSTYPE_IPV6_UDP
= 0x8
748 /* Reserved 0x9 - 0xF */
751 #define FM10K_RXD_HDR_INFO_XC_MASK 0x0006
752 enum fm10k_rxdesc_xc
{
753 FM10K_XC_UNICAST
= 0x0,
754 FM10K_XC_MULTICAST
= 0x4,
755 FM10K_XC_BROADCAST
= 0x6
758 #define FM10K_RXD_STATUS_DD 0x0001 /* Descriptor done */
759 #define FM10K_RXD_STATUS_EOP 0x0002 /* End of packet */
760 #define FM10K_RXD_STATUS_L4CS 0x0010 /* Indicates an L4 csum */
761 #define FM10K_RXD_STATUS_L4CS2 0x0040 /* Inner header L4 csum */
762 #define FM10K_RXD_STATUS_L4E2 0x0800 /* Inner header L4 csum err */
763 #define FM10K_RXD_STATUS_IPE2 0x1000 /* Inner header IPv4 csum err */
764 #define FM10K_RXD_STATUS_RXE 0x2000 /* Generic Rx error */
765 #define FM10K_RXD_STATUS_L4E 0x4000 /* L4 csum error */
766 #define FM10K_RXD_STATUS_IPE 0x8000 /* IPv4 csum error */
768 #define FM10K_RXD_ERR_SWITCH_ERROR 0x0001 /* Switch found bad packet */
769 #define FM10K_RXD_ERR_NO_DESCRIPTOR 0x0002 /* No descriptor available */
770 #define FM10K_RXD_ERR_PP_ERROR 0x0004 /* RAM error during processing */
771 #define FM10K_RXD_ERR_SWITCH_READY 0x0008 /* Link transition mid-packet */
772 #define FM10K_RXD_ERR_TOO_BIG 0x0010 /* Pkt too big for single buf */
775 __be16 swpri_type_user
;
781 #endif /* _FM10K_TYPE_H */