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Merge branch 'for-4.9/block' into for-next
[deliverable/linux.git] / drivers / net / ethernet / intel / i40evf / i40e_adminq_cmd.h
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_ADMINQ_CMD_H_
28 #define _I40E_ADMINQ_CMD_H_
29
30 /* This header file defines the i40e Admin Queue commands and is shared between
31 * i40e Firmware and Software.
32 *
33 * This file needs to comply with the Linux Kernel coding style.
34 */
35
36 #define I40E_FW_API_VERSION_MAJOR 0x0001
37 #define I40E_FW_API_VERSION_MINOR 0x0005
38
39 struct i40e_aq_desc {
40 __le16 flags;
41 __le16 opcode;
42 __le16 datalen;
43 __le16 retval;
44 __le32 cookie_high;
45 __le32 cookie_low;
46 union {
47 struct {
48 __le32 param0;
49 __le32 param1;
50 __le32 param2;
51 __le32 param3;
52 } internal;
53 struct {
54 __le32 param0;
55 __le32 param1;
56 __le32 addr_high;
57 __le32 addr_low;
58 } external;
59 u8 raw[16];
60 } params;
61 };
62
63 /* Flags sub-structure
64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
66 */
67
68 /* command flags and offsets*/
69 #define I40E_AQ_FLAG_DD_SHIFT 0
70 #define I40E_AQ_FLAG_CMP_SHIFT 1
71 #define I40E_AQ_FLAG_ERR_SHIFT 2
72 #define I40E_AQ_FLAG_VFE_SHIFT 3
73 #define I40E_AQ_FLAG_LB_SHIFT 9
74 #define I40E_AQ_FLAG_RD_SHIFT 10
75 #define I40E_AQ_FLAG_VFC_SHIFT 11
76 #define I40E_AQ_FLAG_BUF_SHIFT 12
77 #define I40E_AQ_FLAG_SI_SHIFT 13
78 #define I40E_AQ_FLAG_EI_SHIFT 14
79 #define I40E_AQ_FLAG_FE_SHIFT 15
80
81 #define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
82 #define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
83 #define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
84 #define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
85 #define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
86 #define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
87 #define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
88 #define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
89 #define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
90 #define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
91 #define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
92
93 /* error codes */
94 enum i40e_admin_queue_err {
95 I40E_AQ_RC_OK = 0, /* success */
96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
97 I40E_AQ_RC_ENOENT = 2, /* No such element */
98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
100 I40E_AQ_RC_EIO = 5, /* I/O error */
101 I40E_AQ_RC_ENXIO = 6, /* No such resource */
102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
103 I40E_AQ_RC_EAGAIN = 8, /* Try again */
104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
105 I40E_AQ_RC_EACCES = 10, /* Permission denied */
106 I40E_AQ_RC_EFAULT = 11, /* Bad address */
107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
108 I40E_AQ_RC_EEXIST = 13, /* object already exists */
109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
117 I40E_AQ_RC_EFBIG = 22, /* File too large */
118 };
119
120 /* Admin Queue command opcodes */
121 enum i40e_admin_queue_opc {
122 /* aq commands */
123 i40e_aqc_opc_get_version = 0x0001,
124 i40e_aqc_opc_driver_version = 0x0002,
125 i40e_aqc_opc_queue_shutdown = 0x0003,
126 i40e_aqc_opc_set_pf_context = 0x0004,
127
128 /* resource ownership */
129 i40e_aqc_opc_request_resource = 0x0008,
130 i40e_aqc_opc_release_resource = 0x0009,
131
132 i40e_aqc_opc_list_func_capabilities = 0x000A,
133 i40e_aqc_opc_list_dev_capabilities = 0x000B,
134
135 /* LAA */
136 i40e_aqc_opc_mac_address_read = 0x0107,
137 i40e_aqc_opc_mac_address_write = 0x0108,
138
139 /* PXE */
140 i40e_aqc_opc_clear_pxe_mode = 0x0110,
141
142 /* internal switch commands */
143 i40e_aqc_opc_get_switch_config = 0x0200,
144 i40e_aqc_opc_add_statistics = 0x0201,
145 i40e_aqc_opc_remove_statistics = 0x0202,
146 i40e_aqc_opc_set_port_parameters = 0x0203,
147 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
148 i40e_aqc_opc_set_switch_config = 0x0205,
149 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
150 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
151
152 i40e_aqc_opc_add_vsi = 0x0210,
153 i40e_aqc_opc_update_vsi_parameters = 0x0211,
154 i40e_aqc_opc_get_vsi_parameters = 0x0212,
155
156 i40e_aqc_opc_add_pv = 0x0220,
157 i40e_aqc_opc_update_pv_parameters = 0x0221,
158 i40e_aqc_opc_get_pv_parameters = 0x0222,
159
160 i40e_aqc_opc_add_veb = 0x0230,
161 i40e_aqc_opc_update_veb_parameters = 0x0231,
162 i40e_aqc_opc_get_veb_parameters = 0x0232,
163
164 i40e_aqc_opc_delete_element = 0x0243,
165
166 i40e_aqc_opc_add_macvlan = 0x0250,
167 i40e_aqc_opc_remove_macvlan = 0x0251,
168 i40e_aqc_opc_add_vlan = 0x0252,
169 i40e_aqc_opc_remove_vlan = 0x0253,
170 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
171 i40e_aqc_opc_add_tag = 0x0255,
172 i40e_aqc_opc_remove_tag = 0x0256,
173 i40e_aqc_opc_add_multicast_etag = 0x0257,
174 i40e_aqc_opc_remove_multicast_etag = 0x0258,
175 i40e_aqc_opc_update_tag = 0x0259,
176 i40e_aqc_opc_add_control_packet_filter = 0x025A,
177 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
178 i40e_aqc_opc_add_cloud_filters = 0x025C,
179 i40e_aqc_opc_remove_cloud_filters = 0x025D,
180
181 i40e_aqc_opc_add_mirror_rule = 0x0260,
182 i40e_aqc_opc_delete_mirror_rule = 0x0261,
183
184 /* DCB commands */
185 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
186 i40e_aqc_opc_dcb_updated = 0x0302,
187
188 /* TX scheduler */
189 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
190 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
191 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
192 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
193 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
194 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
195
196 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
197 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
198 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
199 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
200 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
201 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
202 i40e_aqc_opc_query_port_ets_config = 0x0419,
203 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
204 i40e_aqc_opc_suspend_port_tx = 0x041B,
205 i40e_aqc_opc_resume_port_tx = 0x041C,
206 i40e_aqc_opc_configure_partition_bw = 0x041D,
207
208 /* phy commands*/
209 i40e_aqc_opc_get_phy_abilities = 0x0600,
210 i40e_aqc_opc_set_phy_config = 0x0601,
211 i40e_aqc_opc_set_mac_config = 0x0603,
212 i40e_aqc_opc_set_link_restart_an = 0x0605,
213 i40e_aqc_opc_get_link_status = 0x0607,
214 i40e_aqc_opc_set_phy_int_mask = 0x0613,
215 i40e_aqc_opc_get_local_advt_reg = 0x0614,
216 i40e_aqc_opc_set_local_advt_reg = 0x0615,
217 i40e_aqc_opc_get_partner_advt = 0x0616,
218 i40e_aqc_opc_set_lb_modes = 0x0618,
219 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
220 i40e_aqc_opc_set_phy_debug = 0x0622,
221 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
222 i40e_aqc_opc_run_phy_activity = 0x0626,
223
224 /* NVM commands */
225 i40e_aqc_opc_nvm_read = 0x0701,
226 i40e_aqc_opc_nvm_erase = 0x0702,
227 i40e_aqc_opc_nvm_update = 0x0703,
228 i40e_aqc_opc_nvm_config_read = 0x0704,
229 i40e_aqc_opc_nvm_config_write = 0x0705,
230 i40e_aqc_opc_oem_post_update = 0x0720,
231 i40e_aqc_opc_thermal_sensor = 0x0721,
232
233 /* virtualization commands */
234 i40e_aqc_opc_send_msg_to_pf = 0x0801,
235 i40e_aqc_opc_send_msg_to_vf = 0x0802,
236 i40e_aqc_opc_send_msg_to_peer = 0x0803,
237
238 /* alternate structure */
239 i40e_aqc_opc_alternate_write = 0x0900,
240 i40e_aqc_opc_alternate_write_indirect = 0x0901,
241 i40e_aqc_opc_alternate_read = 0x0902,
242 i40e_aqc_opc_alternate_read_indirect = 0x0903,
243 i40e_aqc_opc_alternate_write_done = 0x0904,
244 i40e_aqc_opc_alternate_set_mode = 0x0905,
245 i40e_aqc_opc_alternate_clear_port = 0x0906,
246
247 /* LLDP commands */
248 i40e_aqc_opc_lldp_get_mib = 0x0A00,
249 i40e_aqc_opc_lldp_update_mib = 0x0A01,
250 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
251 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
252 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
253 i40e_aqc_opc_lldp_stop = 0x0A05,
254 i40e_aqc_opc_lldp_start = 0x0A06,
255
256 /* Tunnel commands */
257 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
258 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
259 i40e_aqc_opc_set_rss_key = 0x0B02,
260 i40e_aqc_opc_set_rss_lut = 0x0B03,
261 i40e_aqc_opc_get_rss_key = 0x0B04,
262 i40e_aqc_opc_get_rss_lut = 0x0B05,
263
264 /* Async Events */
265 i40e_aqc_opc_event_lan_overflow = 0x1001,
266
267 /* OEM commands */
268 i40e_aqc_opc_oem_parameter_change = 0xFE00,
269 i40e_aqc_opc_oem_device_status_change = 0xFE01,
270 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
271 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
272
273 /* debug commands */
274 i40e_aqc_opc_debug_read_reg = 0xFF03,
275 i40e_aqc_opc_debug_write_reg = 0xFF04,
276 i40e_aqc_opc_debug_modify_reg = 0xFF07,
277 i40e_aqc_opc_debug_dump_internals = 0xFF08,
278 };
279
280 /* command structures and indirect data structures */
281
282 /* Structure naming conventions:
283 * - no suffix for direct command descriptor structures
284 * - _data for indirect sent data
285 * - _resp for indirect return data (data which is both will use _data)
286 * - _completion for direct return data
287 * - _element_ for repeated elements (may also be _data or _resp)
288 *
289 * Command structures are expected to overlay the params.raw member of the basic
290 * descriptor, and as such cannot exceed 16 bytes in length.
291 */
292
293 /* This macro is used to generate a compilation error if a structure
294 * is not exactly the correct length. It gives a divide by zero error if the
295 * structure is not of the correct size, otherwise it creates an enum that is
296 * never used.
297 */
298 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
299 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
300
301 /* This macro is used extensively to ensure that command structures are 16
302 * bytes in length as they have to map to the raw array of that size.
303 */
304 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
305
306 /* internal (0x00XX) commands */
307
308 /* Get version (direct 0x0001) */
309 struct i40e_aqc_get_version {
310 __le32 rom_ver;
311 __le32 fw_build;
312 __le16 fw_major;
313 __le16 fw_minor;
314 __le16 api_major;
315 __le16 api_minor;
316 };
317
318 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
319
320 /* Send driver version (indirect 0x0002) */
321 struct i40e_aqc_driver_version {
322 u8 driver_major_ver;
323 u8 driver_minor_ver;
324 u8 driver_build_ver;
325 u8 driver_subbuild_ver;
326 u8 reserved[4];
327 __le32 address_high;
328 __le32 address_low;
329 };
330
331 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
332
333 /* Queue Shutdown (direct 0x0003) */
334 struct i40e_aqc_queue_shutdown {
335 __le32 driver_unloading;
336 #define I40E_AQ_DRIVER_UNLOADING 0x1
337 u8 reserved[12];
338 };
339
340 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
341
342 /* Set PF context (0x0004, direct) */
343 struct i40e_aqc_set_pf_context {
344 u8 pf_id;
345 u8 reserved[15];
346 };
347
348 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
349
350 /* Request resource ownership (direct 0x0008)
351 * Release resource ownership (direct 0x0009)
352 */
353 #define I40E_AQ_RESOURCE_NVM 1
354 #define I40E_AQ_RESOURCE_SDP 2
355 #define I40E_AQ_RESOURCE_ACCESS_READ 1
356 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
357 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
358 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
359
360 struct i40e_aqc_request_resource {
361 __le16 resource_id;
362 __le16 access_type;
363 __le32 timeout;
364 __le32 resource_number;
365 u8 reserved[4];
366 };
367
368 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
369
370 /* Get function capabilities (indirect 0x000A)
371 * Get device capabilities (indirect 0x000B)
372 */
373 struct i40e_aqc_list_capabilites {
374 u8 command_flags;
375 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
376 u8 pf_index;
377 u8 reserved[2];
378 __le32 count;
379 __le32 addr_high;
380 __le32 addr_low;
381 };
382
383 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
384
385 struct i40e_aqc_list_capabilities_element_resp {
386 __le16 id;
387 u8 major_rev;
388 u8 minor_rev;
389 __le32 number;
390 __le32 logical_id;
391 __le32 phys_id;
392 u8 reserved[16];
393 };
394
395 /* list of caps */
396
397 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
398 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
399 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
400 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
401 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
402 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
403 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
404 #define I40E_AQ_CAP_ID_SRIOV 0x0012
405 #define I40E_AQ_CAP_ID_VF 0x0013
406 #define I40E_AQ_CAP_ID_VMDQ 0x0014
407 #define I40E_AQ_CAP_ID_8021QBG 0x0015
408 #define I40E_AQ_CAP_ID_8021QBR 0x0016
409 #define I40E_AQ_CAP_ID_VSI 0x0017
410 #define I40E_AQ_CAP_ID_DCB 0x0018
411 #define I40E_AQ_CAP_ID_FCOE 0x0021
412 #define I40E_AQ_CAP_ID_ISCSI 0x0022
413 #define I40E_AQ_CAP_ID_RSS 0x0040
414 #define I40E_AQ_CAP_ID_RXQ 0x0041
415 #define I40E_AQ_CAP_ID_TXQ 0x0042
416 #define I40E_AQ_CAP_ID_MSIX 0x0043
417 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
418 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
419 #define I40E_AQ_CAP_ID_1588 0x0046
420 #define I40E_AQ_CAP_ID_IWARP 0x0051
421 #define I40E_AQ_CAP_ID_LED 0x0061
422 #define I40E_AQ_CAP_ID_SDP 0x0062
423 #define I40E_AQ_CAP_ID_MDIO 0x0063
424 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
425 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
426 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
427 #define I40E_AQ_CAP_ID_CEM 0x00F2
428
429 /* Set CPPM Configuration (direct 0x0103) */
430 struct i40e_aqc_cppm_configuration {
431 __le16 command_flags;
432 #define I40E_AQ_CPPM_EN_LTRC 0x0800
433 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
434 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
435 #define I40E_AQ_CPPM_EN_HPTC 0x4000
436 #define I40E_AQ_CPPM_EN_DMARC 0x8000
437 __le16 ttlx;
438 __le32 dmacr;
439 __le16 dmcth;
440 u8 hptc;
441 u8 reserved;
442 __le32 pfltrc;
443 };
444
445 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
446
447 /* Set ARP Proxy command / response (indirect 0x0104) */
448 struct i40e_aqc_arp_proxy_data {
449 __le16 command_flags;
450 #define I40E_AQ_ARP_INIT_IPV4 0x0008
451 #define I40E_AQ_ARP_UNSUP_CTL 0x0010
452 #define I40E_AQ_ARP_ENA 0x0020
453 #define I40E_AQ_ARP_ADD_IPV4 0x0040
454 #define I40E_AQ_ARP_DEL_IPV4 0x0080
455 __le16 table_id;
456 __le32 pfpm_proxyfc;
457 __le32 ip_addr;
458 u8 mac_addr[6];
459 u8 reserved[2];
460 };
461
462 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
463
464 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
465 struct i40e_aqc_ns_proxy_data {
466 __le16 table_idx_mac_addr_0;
467 __le16 table_idx_mac_addr_1;
468 __le16 table_idx_ipv6_0;
469 __le16 table_idx_ipv6_1;
470 __le16 control;
471 #define I40E_AQ_NS_PROXY_ADD_0 0x0100
472 #define I40E_AQ_NS_PROXY_DEL_0 0x0200
473 #define I40E_AQ_NS_PROXY_ADD_1 0x0400
474 #define I40E_AQ_NS_PROXY_DEL_1 0x0800
475 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
476 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
477 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
478 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
479 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
480 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
481 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
482 u8 mac_addr_0[6];
483 u8 mac_addr_1[6];
484 u8 local_mac_addr[6];
485 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
486 u8 ipv6_addr_1[16];
487 };
488
489 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
490
491 /* Manage LAA Command (0x0106) - obsolete */
492 struct i40e_aqc_mng_laa {
493 __le16 command_flags;
494 #define I40E_AQ_LAA_FLAG_WR 0x8000
495 u8 reserved[2];
496 __le32 sal;
497 __le16 sah;
498 u8 reserved2[6];
499 };
500
501 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
502
503 /* Manage MAC Address Read Command (indirect 0x0107) */
504 struct i40e_aqc_mac_address_read {
505 __le16 command_flags;
506 #define I40E_AQC_LAN_ADDR_VALID 0x10
507 #define I40E_AQC_SAN_ADDR_VALID 0x20
508 #define I40E_AQC_PORT_ADDR_VALID 0x40
509 #define I40E_AQC_WOL_ADDR_VALID 0x80
510 #define I40E_AQC_MC_MAG_EN_VALID 0x100
511 #define I40E_AQC_ADDR_VALID_MASK 0x1F0
512 u8 reserved[6];
513 __le32 addr_high;
514 __le32 addr_low;
515 };
516
517 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
518
519 struct i40e_aqc_mac_address_read_data {
520 u8 pf_lan_mac[6];
521 u8 pf_san_mac[6];
522 u8 port_mac[6];
523 u8 pf_wol_mac[6];
524 };
525
526 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
527
528 /* Manage MAC Address Write Command (0x0108) */
529 struct i40e_aqc_mac_address_write {
530 __le16 command_flags;
531 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
532 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
533 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
534 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
535 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
536
537 __le16 mac_sah;
538 __le32 mac_sal;
539 u8 reserved[8];
540 };
541
542 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
543
544 /* PXE commands (0x011x) */
545
546 /* Clear PXE Command and response (direct 0x0110) */
547 struct i40e_aqc_clear_pxe {
548 u8 rx_cnt;
549 u8 reserved[15];
550 };
551
552 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
553
554 /* Switch configuration commands (0x02xx) */
555
556 /* Used by many indirect commands that only pass an seid and a buffer in the
557 * command
558 */
559 struct i40e_aqc_switch_seid {
560 __le16 seid;
561 u8 reserved[6];
562 __le32 addr_high;
563 __le32 addr_low;
564 };
565
566 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
567
568 /* Get Switch Configuration command (indirect 0x0200)
569 * uses i40e_aqc_switch_seid for the descriptor
570 */
571 struct i40e_aqc_get_switch_config_header_resp {
572 __le16 num_reported;
573 __le16 num_total;
574 u8 reserved[12];
575 };
576
577 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
578
579 struct i40e_aqc_switch_config_element_resp {
580 u8 element_type;
581 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
582 #define I40E_AQ_SW_ELEM_TYPE_PF 2
583 #define I40E_AQ_SW_ELEM_TYPE_VF 3
584 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
585 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
586 #define I40E_AQ_SW_ELEM_TYPE_PV 16
587 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
588 #define I40E_AQ_SW_ELEM_TYPE_PA 18
589 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
590 u8 revision;
591 #define I40E_AQ_SW_ELEM_REV_1 1
592 __le16 seid;
593 __le16 uplink_seid;
594 __le16 downlink_seid;
595 u8 reserved[3];
596 u8 connection_type;
597 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
598 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
599 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
600 __le16 scheduler_id;
601 __le16 element_info;
602 };
603
604 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
605
606 /* Get Switch Configuration (indirect 0x0200)
607 * an array of elements are returned in the response buffer
608 * the first in the array is the header, remainder are elements
609 */
610 struct i40e_aqc_get_switch_config_resp {
611 struct i40e_aqc_get_switch_config_header_resp header;
612 struct i40e_aqc_switch_config_element_resp element[1];
613 };
614
615 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
616
617 /* Add Statistics (direct 0x0201)
618 * Remove Statistics (direct 0x0202)
619 */
620 struct i40e_aqc_add_remove_statistics {
621 __le16 seid;
622 __le16 vlan;
623 __le16 stat_index;
624 u8 reserved[10];
625 };
626
627 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
628
629 /* Set Port Parameters command (direct 0x0203) */
630 struct i40e_aqc_set_port_parameters {
631 __le16 command_flags;
632 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
633 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
634 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
635 __le16 bad_frame_vsi;
636 __le16 default_seid; /* reserved for command */
637 u8 reserved[10];
638 };
639
640 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
641
642 /* Get Switch Resource Allocation (indirect 0x0204) */
643 struct i40e_aqc_get_switch_resource_alloc {
644 u8 num_entries; /* reserved for command */
645 u8 reserved[7];
646 __le32 addr_high;
647 __le32 addr_low;
648 };
649
650 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
651
652 /* expect an array of these structs in the response buffer */
653 struct i40e_aqc_switch_resource_alloc_element_resp {
654 u8 resource_type;
655 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
656 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
657 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
658 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
659 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
660 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
661 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
662 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
663 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
664 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
665 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
666 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
667 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
668 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
669 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
670 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
671 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
672 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
673 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
674 u8 reserved1;
675 __le16 guaranteed;
676 __le16 total;
677 __le16 used;
678 __le16 total_unalloced;
679 u8 reserved2[6];
680 };
681
682 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
683
684 /* Set Switch Configuration (direct 0x0205) */
685 struct i40e_aqc_set_switch_config {
686 __le16 flags;
687 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
688 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
689 __le16 valid_flags;
690 u8 reserved[12];
691 };
692
693 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
694
695 /* Read Receive control registers (direct 0x0206)
696 * Write Receive control registers (direct 0x0207)
697 * used for accessing Rx control registers that can be
698 * slow and need special handling when under high Rx load
699 */
700 struct i40e_aqc_rx_ctl_reg_read_write {
701 __le32 reserved1;
702 __le32 address;
703 __le32 reserved2;
704 __le32 value;
705 };
706
707 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
708
709 /* Add VSI (indirect 0x0210)
710 * this indirect command uses struct i40e_aqc_vsi_properties_data
711 * as the indirect buffer (128 bytes)
712 *
713 * Update VSI (indirect 0x211)
714 * uses the same data structure as Add VSI
715 *
716 * Get VSI (indirect 0x0212)
717 * uses the same completion and data structure as Add VSI
718 */
719 struct i40e_aqc_add_get_update_vsi {
720 __le16 uplink_seid;
721 u8 connection_type;
722 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
723 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
724 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
725 u8 reserved1;
726 u8 vf_id;
727 u8 reserved2;
728 __le16 vsi_flags;
729 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
730 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
731 #define I40E_AQ_VSI_TYPE_VF 0x0
732 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
733 #define I40E_AQ_VSI_TYPE_PF 0x2
734 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
735 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
736 __le32 addr_high;
737 __le32 addr_low;
738 };
739
740 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
741
742 struct i40e_aqc_add_get_update_vsi_completion {
743 __le16 seid;
744 __le16 vsi_number;
745 __le16 vsi_used;
746 __le16 vsi_free;
747 __le32 addr_high;
748 __le32 addr_low;
749 };
750
751 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
752
753 struct i40e_aqc_vsi_properties_data {
754 /* first 96 byte are written by SW */
755 __le16 valid_sections;
756 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
757 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
758 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
759 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
760 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
761 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
762 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
763 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
764 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
765 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
766 /* switch section */
767 __le16 switch_id; /* 12bit id combined with flags below */
768 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
769 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
770 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
771 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
772 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
773 u8 sw_reserved[2];
774 /* security section */
775 u8 sec_flags;
776 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
777 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
778 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
779 u8 sec_reserved;
780 /* VLAN section */
781 __le16 pvid; /* VLANS include priority bits */
782 __le16 fcoe_pvid;
783 u8 port_vlan_flags;
784 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
785 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
786 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
787 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
788 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
789 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
790 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
791 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
792 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
793 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
794 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
795 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
796 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
797 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
798 u8 pvlan_reserved[3];
799 /* ingress egress up sections */
800 __le32 ingress_table; /* bitmap, 3 bits per up */
801 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
802 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
803 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
804 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
805 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
806 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
807 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
808 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
809 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
810 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
811 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
812 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
813 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
814 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
815 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
816 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
817 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
818 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
819 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
820 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
821 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
822 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
823 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
824 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
825 __le32 egress_table; /* same defines as for ingress table */
826 /* cascaded PV section */
827 __le16 cas_pv_tag;
828 u8 cas_pv_flags;
829 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
830 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
831 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
832 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
833 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
834 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
835 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
836 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
837 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
838 u8 cas_pv_reserved;
839 /* queue mapping section */
840 __le16 mapping_flags;
841 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
842 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
843 __le16 queue_mapping[16];
844 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
845 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
846 __le16 tc_mapping[8];
847 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
848 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
849 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
850 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
851 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
852 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
853 /* queueing option section */
854 u8 queueing_opt_flags;
855 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
856 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
857 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
858 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
859 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
860 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
861 u8 queueing_opt_reserved[3];
862 /* scheduler section */
863 u8 up_enable_bits;
864 u8 sched_reserved;
865 /* outer up section */
866 __le32 outer_up_table; /* same structure and defines as ingress tbl */
867 u8 cmd_reserved[8];
868 /* last 32 bytes are written by FW */
869 __le16 qs_handle[8];
870 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
871 __le16 stat_counter_idx;
872 __le16 sched_id;
873 u8 resp_reserved[12];
874 };
875
876 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
877
878 /* Add Port Virtualizer (direct 0x0220)
879 * also used for update PV (direct 0x0221) but only flags are used
880 * (IS_CTRL_PORT only works on add PV)
881 */
882 struct i40e_aqc_add_update_pv {
883 __le16 command_flags;
884 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
885 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
886 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
887 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
888 __le16 uplink_seid;
889 __le16 connected_seid;
890 u8 reserved[10];
891 };
892
893 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
894
895 struct i40e_aqc_add_update_pv_completion {
896 /* reserved for update; for add also encodes error if rc == ENOSPC */
897 __le16 pv_seid;
898 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
899 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
900 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
901 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
902 u8 reserved[14];
903 };
904
905 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
906
907 /* Get PV Params (direct 0x0222)
908 * uses i40e_aqc_switch_seid for the descriptor
909 */
910
911 struct i40e_aqc_get_pv_params_completion {
912 __le16 seid;
913 __le16 default_stag;
914 __le16 pv_flags; /* same flags as add_pv */
915 #define I40E_AQC_GET_PV_PV_TYPE 0x1
916 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
917 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
918 u8 reserved[8];
919 __le16 default_port_seid;
920 };
921
922 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
923
924 /* Add VEB (direct 0x0230) */
925 struct i40e_aqc_add_veb {
926 __le16 uplink_seid;
927 __le16 downlink_seid;
928 __le16 veb_flags;
929 #define I40E_AQC_ADD_VEB_FLOATING 0x1
930 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
931 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
932 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
933 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
934 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
935 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
936 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
937 u8 enable_tcs;
938 u8 reserved[9];
939 };
940
941 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
942
943 struct i40e_aqc_add_veb_completion {
944 u8 reserved[6];
945 __le16 switch_seid;
946 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
947 __le16 veb_seid;
948 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
949 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
950 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
951 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
952 __le16 statistic_index;
953 __le16 vebs_used;
954 __le16 vebs_free;
955 };
956
957 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
958
959 /* Get VEB Parameters (direct 0x0232)
960 * uses i40e_aqc_switch_seid for the descriptor
961 */
962 struct i40e_aqc_get_veb_parameters_completion {
963 __le16 seid;
964 __le16 switch_id;
965 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
966 __le16 statistic_index;
967 __le16 vebs_used;
968 __le16 vebs_free;
969 u8 reserved[4];
970 };
971
972 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
973
974 /* Delete Element (direct 0x0243)
975 * uses the generic i40e_aqc_switch_seid
976 */
977
978 /* Add MAC-VLAN (indirect 0x0250) */
979
980 /* used for the command for most vlan commands */
981 struct i40e_aqc_macvlan {
982 __le16 num_addresses;
983 __le16 seid[3];
984 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
985 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
986 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
987 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
988 __le32 addr_high;
989 __le32 addr_low;
990 };
991
992 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
993
994 /* indirect data for command and response */
995 struct i40e_aqc_add_macvlan_element_data {
996 u8 mac_addr[6];
997 __le16 vlan_tag;
998 __le16 flags;
999 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1000 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1001 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1002 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1003 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1004 __le16 queue_number;
1005 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1006 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1007 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1008 /* response section */
1009 u8 match_method;
1010 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1011 #define I40E_AQC_MM_HASH_MATCH 0x02
1012 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1013 u8 reserved1[3];
1014 };
1015
1016 struct i40e_aqc_add_remove_macvlan_completion {
1017 __le16 perfect_mac_used;
1018 __le16 perfect_mac_free;
1019 __le16 unicast_hash_free;
1020 __le16 multicast_hash_free;
1021 __le32 addr_high;
1022 __le32 addr_low;
1023 };
1024
1025 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1026
1027 /* Remove MAC-VLAN (indirect 0x0251)
1028 * uses i40e_aqc_macvlan for the descriptor
1029 * data points to an array of num_addresses of elements
1030 */
1031
1032 struct i40e_aqc_remove_macvlan_element_data {
1033 u8 mac_addr[6];
1034 __le16 vlan_tag;
1035 u8 flags;
1036 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1037 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1038 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1039 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1040 u8 reserved[3];
1041 /* reply section */
1042 u8 error_code;
1043 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1044 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1045 u8 reply_reserved[3];
1046 };
1047
1048 /* Add VLAN (indirect 0x0252)
1049 * Remove VLAN (indirect 0x0253)
1050 * use the generic i40e_aqc_macvlan for the command
1051 */
1052 struct i40e_aqc_add_remove_vlan_element_data {
1053 __le16 vlan_tag;
1054 u8 vlan_flags;
1055 /* flags for add VLAN */
1056 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1057 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1058 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1059 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1060 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1061 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1062 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1063 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1064 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1065 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1066 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1067 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1068 /* flags for remove VLAN */
1069 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1070 u8 reserved;
1071 u8 result;
1072 /* flags for add VLAN */
1073 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1074 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1075 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1076 /* flags for remove VLAN */
1077 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1078 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1079 u8 reserved1[3];
1080 };
1081
1082 struct i40e_aqc_add_remove_vlan_completion {
1083 u8 reserved[4];
1084 __le16 vlans_used;
1085 __le16 vlans_free;
1086 __le32 addr_high;
1087 __le32 addr_low;
1088 };
1089
1090 /* Set VSI Promiscuous Modes (direct 0x0254) */
1091 struct i40e_aqc_set_vsi_promiscuous_modes {
1092 __le16 promiscuous_flags;
1093 __le16 valid_flags;
1094 /* flags used for both fields above */
1095 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1096 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1097 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1098 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1099 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1100 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1101 __le16 seid;
1102 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1103 __le16 vlan_tag;
1104 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1105 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1106 u8 reserved[8];
1107 };
1108
1109 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1110
1111 /* Add S/E-tag command (direct 0x0255)
1112 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1113 */
1114 struct i40e_aqc_add_tag {
1115 __le16 flags;
1116 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1117 __le16 seid;
1118 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1119 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1120 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1121 __le16 tag;
1122 __le16 queue_number;
1123 u8 reserved[8];
1124 };
1125
1126 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1127
1128 struct i40e_aqc_add_remove_tag_completion {
1129 u8 reserved[12];
1130 __le16 tags_used;
1131 __le16 tags_free;
1132 };
1133
1134 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1135
1136 /* Remove S/E-tag command (direct 0x0256)
1137 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1138 */
1139 struct i40e_aqc_remove_tag {
1140 __le16 seid;
1141 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1142 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1143 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1144 __le16 tag;
1145 u8 reserved[12];
1146 };
1147
1148 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1149
1150 /* Add multicast E-Tag (direct 0x0257)
1151 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1152 * and no external data
1153 */
1154 struct i40e_aqc_add_remove_mcast_etag {
1155 __le16 pv_seid;
1156 __le16 etag;
1157 u8 num_unicast_etags;
1158 u8 reserved[3];
1159 __le32 addr_high; /* address of array of 2-byte s-tags */
1160 __le32 addr_low;
1161 };
1162
1163 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1164
1165 struct i40e_aqc_add_remove_mcast_etag_completion {
1166 u8 reserved[4];
1167 __le16 mcast_etags_used;
1168 __le16 mcast_etags_free;
1169 __le32 addr_high;
1170 __le32 addr_low;
1171
1172 };
1173
1174 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1175
1176 /* Update S/E-Tag (direct 0x0259) */
1177 struct i40e_aqc_update_tag {
1178 __le16 seid;
1179 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1180 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1181 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1182 __le16 old_tag;
1183 __le16 new_tag;
1184 u8 reserved[10];
1185 };
1186
1187 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1188
1189 struct i40e_aqc_update_tag_completion {
1190 u8 reserved[12];
1191 __le16 tags_used;
1192 __le16 tags_free;
1193 };
1194
1195 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1196
1197 /* Add Control Packet filter (direct 0x025A)
1198 * Remove Control Packet filter (direct 0x025B)
1199 * uses the i40e_aqc_add_oveb_cloud,
1200 * and the generic direct completion structure
1201 */
1202 struct i40e_aqc_add_remove_control_packet_filter {
1203 u8 mac[6];
1204 __le16 etype;
1205 __le16 flags;
1206 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1207 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1208 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1209 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1210 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1211 __le16 seid;
1212 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1213 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1214 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1215 __le16 queue;
1216 u8 reserved[2];
1217 };
1218
1219 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1220
1221 struct i40e_aqc_add_remove_control_packet_filter_completion {
1222 __le16 mac_etype_used;
1223 __le16 etype_used;
1224 __le16 mac_etype_free;
1225 __le16 etype_free;
1226 u8 reserved[8];
1227 };
1228
1229 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1230
1231 /* Add Cloud filters (indirect 0x025C)
1232 * Remove Cloud filters (indirect 0x025D)
1233 * uses the i40e_aqc_add_remove_cloud_filters,
1234 * and the generic indirect completion structure
1235 */
1236 struct i40e_aqc_add_remove_cloud_filters {
1237 u8 num_filters;
1238 u8 reserved;
1239 __le16 seid;
1240 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1241 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1242 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1243 u8 reserved2[4];
1244 __le32 addr_high;
1245 __le32 addr_low;
1246 };
1247
1248 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1249
1250 struct i40e_aqc_add_remove_cloud_filters_element_data {
1251 u8 outer_mac[6];
1252 u8 inner_mac[6];
1253 __le16 inner_vlan;
1254 union {
1255 struct {
1256 u8 reserved[12];
1257 u8 data[4];
1258 } v4;
1259 struct {
1260 u8 data[16];
1261 } v6;
1262 } ipaddr;
1263 __le16 flags;
1264 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1265 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1266 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1267 /* 0x0000 reserved */
1268 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1269 /* 0x0002 reserved */
1270 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1271 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1272 /* 0x0005 reserved */
1273 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1274 /* 0x0007 reserved */
1275 /* 0x0008 reserved */
1276 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1277 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1278 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1279 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1280
1281 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1282 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1283 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1284 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1285 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1286
1287 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1288 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1289 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1290 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1291 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1292 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1293 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1294 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1295
1296 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1297 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1298 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1299
1300 __le32 tenant_id;
1301 u8 reserved[4];
1302 __le16 queue_number;
1303 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1304 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1305 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1306 u8 reserved2[14];
1307 /* response section */
1308 u8 allocation_result;
1309 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1310 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1311 u8 response_reserved[7];
1312 };
1313
1314 struct i40e_aqc_remove_cloud_filters_completion {
1315 __le16 perfect_ovlan_used;
1316 __le16 perfect_ovlan_free;
1317 __le16 vlan_used;
1318 __le16 vlan_free;
1319 __le32 addr_high;
1320 __le32 addr_low;
1321 };
1322
1323 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1324
1325 /* Add Mirror Rule (indirect or direct 0x0260)
1326 * Delete Mirror Rule (indirect or direct 0x0261)
1327 * note: some rule types (4,5) do not use an external buffer.
1328 * take care to set the flags correctly.
1329 */
1330 struct i40e_aqc_add_delete_mirror_rule {
1331 __le16 seid;
1332 __le16 rule_type;
1333 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1334 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1335 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1336 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1337 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1338 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1339 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1340 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1341 __le16 num_entries;
1342 __le16 destination; /* VSI for add, rule id for delete */
1343 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1344 __le32 addr_low;
1345 };
1346
1347 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1348
1349 struct i40e_aqc_add_delete_mirror_rule_completion {
1350 u8 reserved[2];
1351 __le16 rule_id; /* only used on add */
1352 __le16 mirror_rules_used;
1353 __le16 mirror_rules_free;
1354 __le32 addr_high;
1355 __le32 addr_low;
1356 };
1357
1358 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1359
1360 /* DCB 0x03xx*/
1361
1362 /* PFC Ignore (direct 0x0301)
1363 * the command and response use the same descriptor structure
1364 */
1365 struct i40e_aqc_pfc_ignore {
1366 u8 tc_bitmap;
1367 u8 command_flags; /* unused on response */
1368 #define I40E_AQC_PFC_IGNORE_SET 0x80
1369 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1370 u8 reserved[14];
1371 };
1372
1373 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1374
1375 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1376 * with no parameters
1377 */
1378
1379 /* TX scheduler 0x04xx */
1380
1381 /* Almost all the indirect commands use
1382 * this generic struct to pass the SEID in param0
1383 */
1384 struct i40e_aqc_tx_sched_ind {
1385 __le16 vsi_seid;
1386 u8 reserved[6];
1387 __le32 addr_high;
1388 __le32 addr_low;
1389 };
1390
1391 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1392
1393 /* Several commands respond with a set of queue set handles */
1394 struct i40e_aqc_qs_handles_resp {
1395 __le16 qs_handles[8];
1396 };
1397
1398 /* Configure VSI BW limits (direct 0x0400) */
1399 struct i40e_aqc_configure_vsi_bw_limit {
1400 __le16 vsi_seid;
1401 u8 reserved[2];
1402 __le16 credit;
1403 u8 reserved1[2];
1404 u8 max_credit; /* 0-3, limit = 2^max */
1405 u8 reserved2[7];
1406 };
1407
1408 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1409
1410 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1411 * responds with i40e_aqc_qs_handles_resp
1412 */
1413 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1414 u8 tc_valid_bits;
1415 u8 reserved[15];
1416 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1417
1418 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1419 __le16 tc_bw_max[2];
1420 u8 reserved1[28];
1421 };
1422
1423 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1424
1425 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1426 * responds with i40e_aqc_qs_handles_resp
1427 */
1428 struct i40e_aqc_configure_vsi_tc_bw_data {
1429 u8 tc_valid_bits;
1430 u8 reserved[3];
1431 u8 tc_bw_credits[8];
1432 u8 reserved1[4];
1433 __le16 qs_handles[8];
1434 };
1435
1436 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1437
1438 /* Query vsi bw configuration (indirect 0x0408) */
1439 struct i40e_aqc_query_vsi_bw_config_resp {
1440 u8 tc_valid_bits;
1441 u8 tc_suspended_bits;
1442 u8 reserved[14];
1443 __le16 qs_handles[8];
1444 u8 reserved1[4];
1445 __le16 port_bw_limit;
1446 u8 reserved2[2];
1447 u8 max_bw; /* 0-3, limit = 2^max */
1448 u8 reserved3[23];
1449 };
1450
1451 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1452
1453 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1454 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1455 u8 tc_valid_bits;
1456 u8 reserved[3];
1457 u8 share_credits[8];
1458 __le16 credits[8];
1459
1460 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1461 __le16 tc_bw_max[2];
1462 };
1463
1464 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1465
1466 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1467 struct i40e_aqc_configure_switching_comp_bw_limit {
1468 __le16 seid;
1469 u8 reserved[2];
1470 __le16 credit;
1471 u8 reserved1[2];
1472 u8 max_bw; /* 0-3, limit = 2^max */
1473 u8 reserved2[7];
1474 };
1475
1476 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1477
1478 /* Enable Physical Port ETS (indirect 0x0413)
1479 * Modify Physical Port ETS (indirect 0x0414)
1480 * Disable Physical Port ETS (indirect 0x0415)
1481 */
1482 struct i40e_aqc_configure_switching_comp_ets_data {
1483 u8 reserved[4];
1484 u8 tc_valid_bits;
1485 u8 seepage;
1486 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1487 u8 tc_strict_priority_flags;
1488 u8 reserved1[17];
1489 u8 tc_bw_share_credits[8];
1490 u8 reserved2[96];
1491 };
1492
1493 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1494
1495 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1496 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1497 u8 tc_valid_bits;
1498 u8 reserved[15];
1499 __le16 tc_bw_credit[8];
1500
1501 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1502 __le16 tc_bw_max[2];
1503 u8 reserved1[28];
1504 };
1505
1506 I40E_CHECK_STRUCT_LEN(0x40,
1507 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1508
1509 /* Configure Switching Component Bandwidth Allocation per Tc
1510 * (indirect 0x0417)
1511 */
1512 struct i40e_aqc_configure_switching_comp_bw_config_data {
1513 u8 tc_valid_bits;
1514 u8 reserved[2];
1515 u8 absolute_credits; /* bool */
1516 u8 tc_bw_share_credits[8];
1517 u8 reserved1[20];
1518 };
1519
1520 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1521
1522 /* Query Switching Component Configuration (indirect 0x0418) */
1523 struct i40e_aqc_query_switching_comp_ets_config_resp {
1524 u8 tc_valid_bits;
1525 u8 reserved[35];
1526 __le16 port_bw_limit;
1527 u8 reserved1[2];
1528 u8 tc_bw_max; /* 0-3, limit = 2^max */
1529 u8 reserved2[23];
1530 };
1531
1532 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1533
1534 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1535 struct i40e_aqc_query_port_ets_config_resp {
1536 u8 reserved[4];
1537 u8 tc_valid_bits;
1538 u8 reserved1;
1539 u8 tc_strict_priority_bits;
1540 u8 reserved2;
1541 u8 tc_bw_share_credits[8];
1542 __le16 tc_bw_limits[8];
1543
1544 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1545 __le16 tc_bw_max[2];
1546 u8 reserved3[32];
1547 };
1548
1549 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1550
1551 /* Query Switching Component Bandwidth Allocation per Traffic Type
1552 * (indirect 0x041A)
1553 */
1554 struct i40e_aqc_query_switching_comp_bw_config_resp {
1555 u8 tc_valid_bits;
1556 u8 reserved[2];
1557 u8 absolute_credits_enable; /* bool */
1558 u8 tc_bw_share_credits[8];
1559 __le16 tc_bw_limits[8];
1560
1561 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1562 __le16 tc_bw_max[2];
1563 };
1564
1565 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1566
1567 /* Suspend/resume port TX traffic
1568 * (direct 0x041B and 0x041C) uses the generic SEID struct
1569 */
1570
1571 /* Configure partition BW
1572 * (indirect 0x041D)
1573 */
1574 struct i40e_aqc_configure_partition_bw_data {
1575 __le16 pf_valid_bits;
1576 u8 min_bw[16]; /* guaranteed bandwidth */
1577 u8 max_bw[16]; /* bandwidth limit */
1578 };
1579
1580 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1581
1582 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1583
1584 /* set in param0 for get phy abilities to report qualified modules */
1585 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1586 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1587
1588 enum i40e_aq_phy_type {
1589 I40E_PHY_TYPE_SGMII = 0x0,
1590 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1591 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1592 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1593 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1594 I40E_PHY_TYPE_XAUI = 0x5,
1595 I40E_PHY_TYPE_XFI = 0x6,
1596 I40E_PHY_TYPE_SFI = 0x7,
1597 I40E_PHY_TYPE_XLAUI = 0x8,
1598 I40E_PHY_TYPE_XLPPI = 0x9,
1599 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1600 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1601 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1602 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1603 I40E_PHY_TYPE_100BASE_TX = 0x11,
1604 I40E_PHY_TYPE_1000BASE_T = 0x12,
1605 I40E_PHY_TYPE_10GBASE_T = 0x13,
1606 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1607 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1608 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1609 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1610 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1611 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1612 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1613 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1614 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1615 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1616 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1617 I40E_PHY_TYPE_MAX
1618 };
1619
1620 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1621 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1622 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1623 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1624 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1625
1626 enum i40e_aq_link_speed {
1627 I40E_LINK_SPEED_UNKNOWN = 0,
1628 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT),
1629 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT),
1630 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT),
1631 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT),
1632 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT)
1633 };
1634
1635 struct i40e_aqc_module_desc {
1636 u8 oui[3];
1637 u8 reserved1;
1638 u8 part_number[16];
1639 u8 revision[4];
1640 u8 reserved2[8];
1641 };
1642
1643 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1644
1645 struct i40e_aq_get_phy_abilities_resp {
1646 __le32 phy_type; /* bitmap using the above enum for offsets */
1647 u8 link_speed; /* bitmap using the above enum bit patterns */
1648 u8 abilities;
1649 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1650 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1651 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1652 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1653 #define I40E_AQ_PHY_AN_ENABLED 0x10
1654 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1655 __le16 eee_capability;
1656 #define I40E_AQ_EEE_100BASE_TX 0x0002
1657 #define I40E_AQ_EEE_1000BASE_T 0x0004
1658 #define I40E_AQ_EEE_10GBASE_T 0x0008
1659 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1660 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1661 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1662 __le32 eeer_val;
1663 u8 d3_lpan;
1664 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1665 u8 reserved[3];
1666 u8 phy_id[4];
1667 u8 module_type[3];
1668 u8 qualified_module_count;
1669 #define I40E_AQ_PHY_MAX_QMS 16
1670 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1671 };
1672
1673 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1674
1675 /* Set PHY Config (direct 0x0601) */
1676 struct i40e_aq_set_phy_config { /* same bits as above in all */
1677 __le32 phy_type;
1678 u8 link_speed;
1679 u8 abilities;
1680 /* bits 0-2 use the values from get_phy_abilities_resp */
1681 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1682 #define I40E_AQ_PHY_ENABLE_AN 0x10
1683 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1684 __le16 eee_capability;
1685 __le32 eeer;
1686 u8 low_power_ctrl;
1687 u8 reserved[3];
1688 };
1689
1690 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1691
1692 /* Set MAC Config command data structure (direct 0x0603) */
1693 struct i40e_aq_set_mac_config {
1694 __le16 max_frame_size;
1695 u8 params;
1696 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1697 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1698 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1699 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1700 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1701 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1702 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1703 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1704 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1705 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1706 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1707 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1708 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1709 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1710 u8 tx_timer_priority; /* bitmap */
1711 __le16 tx_timer_value;
1712 __le16 fc_refresh_threshold;
1713 u8 reserved[8];
1714 };
1715
1716 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1717
1718 /* Restart Auto-Negotiation (direct 0x605) */
1719 struct i40e_aqc_set_link_restart_an {
1720 u8 command;
1721 #define I40E_AQ_PHY_RESTART_AN 0x02
1722 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1723 u8 reserved[15];
1724 };
1725
1726 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1727
1728 /* Get Link Status cmd & response data structure (direct 0x0607) */
1729 struct i40e_aqc_get_link_status {
1730 __le16 command_flags; /* only field set on command */
1731 #define I40E_AQ_LSE_MASK 0x3
1732 #define I40E_AQ_LSE_NOP 0x0
1733 #define I40E_AQ_LSE_DISABLE 0x2
1734 #define I40E_AQ_LSE_ENABLE 0x3
1735 /* only response uses this flag */
1736 #define I40E_AQ_LSE_IS_ENABLED 0x1
1737 u8 phy_type; /* i40e_aq_phy_type */
1738 u8 link_speed; /* i40e_aq_link_speed */
1739 u8 link_info;
1740 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1741 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1742 #define I40E_AQ_LINK_FAULT 0x02
1743 #define I40E_AQ_LINK_FAULT_TX 0x04
1744 #define I40E_AQ_LINK_FAULT_RX 0x08
1745 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1746 #define I40E_AQ_LINK_UP_PORT 0x20
1747 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1748 #define I40E_AQ_SIGNAL_DETECT 0x80
1749 u8 an_info;
1750 #define I40E_AQ_AN_COMPLETED 0x01
1751 #define I40E_AQ_LP_AN_ABILITY 0x02
1752 #define I40E_AQ_PD_FAULT 0x04
1753 #define I40E_AQ_FEC_EN 0x08
1754 #define I40E_AQ_PHY_LOW_POWER 0x10
1755 #define I40E_AQ_LINK_PAUSE_TX 0x20
1756 #define I40E_AQ_LINK_PAUSE_RX 0x40
1757 #define I40E_AQ_QUALIFIED_MODULE 0x80
1758 u8 ext_info;
1759 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1760 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1761 #define I40E_AQ_LINK_TX_SHIFT 0x02
1762 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1763 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1764 #define I40E_AQ_LINK_TX_DRAINED 0x01
1765 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1766 #define I40E_AQ_LINK_FORCED_40G 0x10
1767 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1768 __le16 max_frame_size;
1769 u8 config;
1770 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1771 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1772 u8 external_power_ability;
1773 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
1774 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
1775 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
1776 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
1777 u8 reserved[4];
1778 };
1779
1780 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1781
1782 /* Set event mask command (direct 0x613) */
1783 struct i40e_aqc_set_phy_int_mask {
1784 u8 reserved[8];
1785 __le16 event_mask;
1786 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1787 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1788 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1789 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1790 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1791 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1792 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1793 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1794 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1795 u8 reserved1[6];
1796 };
1797
1798 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1799
1800 /* Get Local AN advt register (direct 0x0614)
1801 * Set Local AN advt register (direct 0x0615)
1802 * Get Link Partner AN advt register (direct 0x0616)
1803 */
1804 struct i40e_aqc_an_advt_reg {
1805 __le32 local_an_reg0;
1806 __le16 local_an_reg1;
1807 u8 reserved[10];
1808 };
1809
1810 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1811
1812 /* Set Loopback mode (0x0618) */
1813 struct i40e_aqc_set_lb_mode {
1814 __le16 lb_mode;
1815 #define I40E_AQ_LB_PHY_LOCAL 0x01
1816 #define I40E_AQ_LB_PHY_REMOTE 0x02
1817 #define I40E_AQ_LB_MAC_LOCAL 0x04
1818 u8 reserved[14];
1819 };
1820
1821 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1822
1823 /* Set PHY Debug command (0x0622) */
1824 struct i40e_aqc_set_phy_debug {
1825 u8 command_flags;
1826 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1827 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1828 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1829 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1830 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1831 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1832 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1833 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1834 u8 reserved[15];
1835 };
1836
1837 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1838
1839 enum i40e_aq_phy_reg_type {
1840 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1841 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1842 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1843 };
1844
1845 /* Run PHY Activity (0x0626) */
1846 struct i40e_aqc_run_phy_activity {
1847 __le16 activity_id;
1848 u8 flags;
1849 u8 reserved1;
1850 __le32 control;
1851 __le32 data;
1852 u8 reserved2[4];
1853 };
1854
1855 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1856
1857 /* NVM Read command (indirect 0x0701)
1858 * NVM Erase commands (direct 0x0702)
1859 * NVM Update commands (indirect 0x0703)
1860 */
1861 struct i40e_aqc_nvm_update {
1862 u8 command_flags;
1863 #define I40E_AQ_NVM_LAST_CMD 0x01
1864 #define I40E_AQ_NVM_FLASH_ONLY 0x80
1865 u8 module_pointer;
1866 __le16 length;
1867 __le32 offset;
1868 __le32 addr_high;
1869 __le32 addr_low;
1870 };
1871
1872 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1873
1874 /* NVM Config Read (indirect 0x0704) */
1875 struct i40e_aqc_nvm_config_read {
1876 __le16 cmd_flags;
1877 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1878 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
1879 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
1880 __le16 element_count;
1881 __le16 element_id; /* Feature/field ID */
1882 __le16 element_id_msw; /* MSWord of field ID */
1883 __le32 address_high;
1884 __le32 address_low;
1885 };
1886
1887 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1888
1889 /* NVM Config Write (indirect 0x0705) */
1890 struct i40e_aqc_nvm_config_write {
1891 __le16 cmd_flags;
1892 __le16 element_count;
1893 u8 reserved[4];
1894 __le32 address_high;
1895 __le32 address_low;
1896 };
1897
1898 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1899
1900 /* Used for 0x0704 as well as for 0x0705 commands */
1901 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
1902 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
1903 BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1904 #define I40E_AQ_ANVM_FEATURE 0
1905 #define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT)
1906 struct i40e_aqc_nvm_config_data_feature {
1907 __le16 feature_id;
1908 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
1909 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
1910 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
1911 __le16 feature_options;
1912 __le16 feature_selection;
1913 };
1914
1915 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1916
1917 struct i40e_aqc_nvm_config_data_immediate_field {
1918 __le32 field_id;
1919 __le32 field_value;
1920 __le16 field_options;
1921 __le16 reserved;
1922 };
1923
1924 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1925
1926 /* OEM Post Update (indirect 0x0720)
1927 * no command data struct used
1928 */
1929 struct i40e_aqc_nvm_oem_post_update {
1930 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
1931 u8 sel_data;
1932 u8 reserved[7];
1933 };
1934
1935 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1936
1937 struct i40e_aqc_nvm_oem_post_update_buffer {
1938 u8 str_len;
1939 u8 dev_addr;
1940 __le16 eeprom_addr;
1941 u8 data[36];
1942 };
1943
1944 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1945
1946 /* Thermal Sensor (indirect 0x0721)
1947 * read or set thermal sensor configs and values
1948 * takes a sensor and command specific data buffer, not detailed here
1949 */
1950 struct i40e_aqc_thermal_sensor {
1951 u8 sensor_action;
1952 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
1953 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
1954 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
1955 u8 reserved[7];
1956 __le32 addr_high;
1957 __le32 addr_low;
1958 };
1959
1960 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
1961
1962 /* Send to PF command (indirect 0x0801) id is only used by PF
1963 * Send to VF command (indirect 0x0802) id is only used by PF
1964 * Send to Peer PF command (indirect 0x0803)
1965 */
1966 struct i40e_aqc_pf_vf_message {
1967 __le32 id;
1968 u8 reserved[4];
1969 __le32 addr_high;
1970 __le32 addr_low;
1971 };
1972
1973 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1974
1975 /* Alternate structure */
1976
1977 /* Direct write (direct 0x0900)
1978 * Direct read (direct 0x0902)
1979 */
1980 struct i40e_aqc_alternate_write {
1981 __le32 address0;
1982 __le32 data0;
1983 __le32 address1;
1984 __le32 data1;
1985 };
1986
1987 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1988
1989 /* Indirect write (indirect 0x0901)
1990 * Indirect read (indirect 0x0903)
1991 */
1992
1993 struct i40e_aqc_alternate_ind_write {
1994 __le32 address;
1995 __le32 length;
1996 __le32 addr_high;
1997 __le32 addr_low;
1998 };
1999
2000 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2001
2002 /* Done alternate write (direct 0x0904)
2003 * uses i40e_aq_desc
2004 */
2005 struct i40e_aqc_alternate_write_done {
2006 __le16 cmd_flags;
2007 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2008 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2009 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2010 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2011 u8 reserved[14];
2012 };
2013
2014 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2015
2016 /* Set OEM mode (direct 0x0905) */
2017 struct i40e_aqc_alternate_set_mode {
2018 __le32 mode;
2019 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2020 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2021 u8 reserved[12];
2022 };
2023
2024 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2025
2026 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2027
2028 /* async events 0x10xx */
2029
2030 /* Lan Queue Overflow Event (direct, 0x1001) */
2031 struct i40e_aqc_lan_overflow {
2032 __le32 prtdcb_rupto;
2033 __le32 otx_ctl;
2034 u8 reserved[8];
2035 };
2036
2037 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2038
2039 /* Get LLDP MIB (indirect 0x0A00) */
2040 struct i40e_aqc_lldp_get_mib {
2041 u8 type;
2042 u8 reserved1;
2043 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2044 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2045 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2046 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2047 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2048 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2049 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2050 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2051 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2052 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2053 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2054 __le16 local_len;
2055 __le16 remote_len;
2056 u8 reserved2[2];
2057 __le32 addr_high;
2058 __le32 addr_low;
2059 };
2060
2061 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2062
2063 /* Configure LLDP MIB Change Event (direct 0x0A01)
2064 * also used for the event (with type in the command field)
2065 */
2066 struct i40e_aqc_lldp_update_mib {
2067 u8 command;
2068 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2069 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2070 u8 reserved[7];
2071 __le32 addr_high;
2072 __le32 addr_low;
2073 };
2074
2075 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2076
2077 /* Add LLDP TLV (indirect 0x0A02)
2078 * Delete LLDP TLV (indirect 0x0A04)
2079 */
2080 struct i40e_aqc_lldp_add_tlv {
2081 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2082 u8 reserved1[1];
2083 __le16 len;
2084 u8 reserved2[4];
2085 __le32 addr_high;
2086 __le32 addr_low;
2087 };
2088
2089 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2090
2091 /* Update LLDP TLV (indirect 0x0A03) */
2092 struct i40e_aqc_lldp_update_tlv {
2093 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2094 u8 reserved;
2095 __le16 old_len;
2096 __le16 new_offset;
2097 __le16 new_len;
2098 __le32 addr_high;
2099 __le32 addr_low;
2100 };
2101
2102 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2103
2104 /* Stop LLDP (direct 0x0A05) */
2105 struct i40e_aqc_lldp_stop {
2106 u8 command;
2107 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2108 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2109 u8 reserved[15];
2110 };
2111
2112 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2113
2114 /* Start LLDP (direct 0x0A06) */
2115
2116 struct i40e_aqc_lldp_start {
2117 u8 command;
2118 #define I40E_AQ_LLDP_AGENT_START 0x1
2119 u8 reserved[15];
2120 };
2121
2122 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2123
2124 /* Apply MIB changes (0x0A07)
2125 * uses the generic struc as it contains no data
2126 */
2127
2128 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2129 struct i40e_aqc_add_udp_tunnel {
2130 __le16 udp_port;
2131 u8 reserved0[3];
2132 u8 protocol_type;
2133 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2134 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2135 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2136 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2137 u8 reserved1[10];
2138 };
2139
2140 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2141
2142 struct i40e_aqc_add_udp_tunnel_completion {
2143 __le16 udp_port;
2144 u8 filter_entry_index;
2145 u8 multiple_pfs;
2146 #define I40E_AQC_SINGLE_PF 0x0
2147 #define I40E_AQC_MULTIPLE_PFS 0x1
2148 u8 total_filters;
2149 u8 reserved[11];
2150 };
2151
2152 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2153
2154 /* remove UDP Tunnel command (0x0B01) */
2155 struct i40e_aqc_remove_udp_tunnel {
2156 u8 reserved[2];
2157 u8 index; /* 0 to 15 */
2158 u8 reserved2[13];
2159 };
2160
2161 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2162
2163 struct i40e_aqc_del_udp_tunnel_completion {
2164 __le16 udp_port;
2165 u8 index; /* 0 to 15 */
2166 u8 multiple_pfs;
2167 u8 total_filters_used;
2168 u8 reserved1[11];
2169 };
2170
2171 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2172
2173 struct i40e_aqc_get_set_rss_key {
2174 #define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15)
2175 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2176 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2177 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2178 __le16 vsi_id;
2179 u8 reserved[6];
2180 __le32 addr_high;
2181 __le32 addr_low;
2182 };
2183
2184 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2185
2186 struct i40e_aqc_get_set_rss_key_data {
2187 u8 standard_rss_key[0x28];
2188 u8 extended_hash_key[0xc];
2189 };
2190
2191 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2192
2193 struct i40e_aqc_get_set_rss_lut {
2194 #define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15)
2195 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2196 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2197 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2198 __le16 vsi_id;
2199 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2200 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \
2201 BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2202
2203 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2204 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2205 __le16 flags;
2206 u8 reserved[4];
2207 __le32 addr_high;
2208 __le32 addr_low;
2209 };
2210
2211 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2212
2213 /* tunnel key structure 0x0B10 */
2214
2215 struct i40e_aqc_tunnel_key_structure_A0 {
2216 __le16 key1_off;
2217 __le16 key1_len;
2218 __le16 key2_off;
2219 __le16 key2_len;
2220 __le16 flags;
2221 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2222 /* response flags */
2223 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2224 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2225 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2226 u8 resreved[6];
2227 };
2228
2229 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0);
2230
2231 struct i40e_aqc_tunnel_key_structure {
2232 u8 key1_off;
2233 u8 key2_off;
2234 u8 key1_len; /* 0 to 15 */
2235 u8 key2_len; /* 0 to 15 */
2236 u8 flags;
2237 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2238 /* response flags */
2239 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2240 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2241 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2242 u8 network_key_index;
2243 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2244 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2245 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2246 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2247 u8 reserved[10];
2248 };
2249
2250 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2251
2252 /* OEM mode commands (direct 0xFE0x) */
2253 struct i40e_aqc_oem_param_change {
2254 __le32 param_type;
2255 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2256 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2257 #define I40E_AQ_OEM_PARAM_MAC 2
2258 __le32 param_value1;
2259 __le16 param_value2;
2260 u8 reserved[6];
2261 };
2262
2263 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2264
2265 struct i40e_aqc_oem_state_change {
2266 __le32 state;
2267 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2268 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2269 u8 reserved[12];
2270 };
2271
2272 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2273
2274 /* Initialize OCSD (0xFE02, direct) */
2275 struct i40e_aqc_opc_oem_ocsd_initialize {
2276 u8 type_status;
2277 u8 reserved1[3];
2278 __le32 ocsd_memory_block_addr_high;
2279 __le32 ocsd_memory_block_addr_low;
2280 __le32 requested_update_interval;
2281 };
2282
2283 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2284
2285 /* Initialize OCBB (0xFE03, direct) */
2286 struct i40e_aqc_opc_oem_ocbb_initialize {
2287 u8 type_status;
2288 u8 reserved1[3];
2289 __le32 ocbb_memory_block_addr_high;
2290 __le32 ocbb_memory_block_addr_low;
2291 u8 reserved2[4];
2292 };
2293
2294 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2295
2296 /* debug commands */
2297
2298 /* get device id (0xFF00) uses the generic structure */
2299
2300 /* set test more (0xFF01, internal) */
2301
2302 struct i40e_acq_set_test_mode {
2303 u8 mode;
2304 #define I40E_AQ_TEST_PARTIAL 0
2305 #define I40E_AQ_TEST_FULL 1
2306 #define I40E_AQ_TEST_NVM 2
2307 u8 reserved[3];
2308 u8 command;
2309 #define I40E_AQ_TEST_OPEN 0
2310 #define I40E_AQ_TEST_CLOSE 1
2311 #define I40E_AQ_TEST_INC 2
2312 u8 reserved2[3];
2313 __le32 address_high;
2314 __le32 address_low;
2315 };
2316
2317 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2318
2319 /* Debug Read Register command (0xFF03)
2320 * Debug Write Register command (0xFF04)
2321 */
2322 struct i40e_aqc_debug_reg_read_write {
2323 __le32 reserved;
2324 __le32 address;
2325 __le32 value_high;
2326 __le32 value_low;
2327 };
2328
2329 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2330
2331 /* Scatter/gather Reg Read (indirect 0xFF05)
2332 * Scatter/gather Reg Write (indirect 0xFF06)
2333 */
2334
2335 /* i40e_aq_desc is used for the command */
2336 struct i40e_aqc_debug_reg_sg_element_data {
2337 __le32 address;
2338 __le32 value;
2339 };
2340
2341 /* Debug Modify register (direct 0xFF07) */
2342 struct i40e_aqc_debug_modify_reg {
2343 __le32 address;
2344 __le32 value;
2345 __le32 clear_mask;
2346 __le32 set_mask;
2347 };
2348
2349 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2350
2351 /* dump internal data (0xFF08, indirect) */
2352
2353 #define I40E_AQ_CLUSTER_ID_AUX 0
2354 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2355 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2356 #define I40E_AQ_CLUSTER_ID_HMC 3
2357 #define I40E_AQ_CLUSTER_ID_MAC0 4
2358 #define I40E_AQ_CLUSTER_ID_MAC1 5
2359 #define I40E_AQ_CLUSTER_ID_MAC2 6
2360 #define I40E_AQ_CLUSTER_ID_MAC3 7
2361 #define I40E_AQ_CLUSTER_ID_DCB 8
2362 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2363 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2364 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2365
2366 struct i40e_aqc_debug_dump_internals {
2367 u8 cluster_id;
2368 u8 table_id;
2369 __le16 data_size;
2370 __le32 idx;
2371 __le32 address_high;
2372 __le32 address_low;
2373 };
2374
2375 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2376
2377 struct i40e_aqc_debug_modify_internals {
2378 u8 cluster_id;
2379 u8 cluster_specific_params[7];
2380 __le32 address_high;
2381 __le32 address_low;
2382 };
2383
2384 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2385
2386 #endif /* _I40E_ADMINQ_CMD_H_ */
Linux kernel - Deliverables
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