drivers/net/ethernet/intel/igb/igb.h

   1 /* Intel(R) Gigabit Ethernet Linux driver
   2  * Copyright(c) 2007-2014 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, see <http://www.gnu.org/licenses/>.
  15  *
  16  * The full GNU General Public License is included in this distribution in
  17  * the file called "COPYING".
  18  *
  19  * Contact Information:
  20  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  */
  23
  24 /* Linux PRO/1000 Ethernet Driver main header file */
  25
  26 #ifndef _IGB_H_
  27 #define _IGB_H_
  28
  29 #include "e1000_mac.h"
  30 #include "e1000_82575.h"
  31
  32 #include <linux/timecounter.h>
  33 #include <linux/net_tstamp.h>
  34 #include <linux/ptp_clock_kernel.h>
  35 #include <linux/bitops.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <linux/pci.h>
  40 #include <linux/mdio.h>
  41
  42 struct igb_adapter;
  43
  44 #define E1000_PCS_CFG_IGN_SD    1
  45
  46 /* Interrupt defines */
  47 #define IGB_START_ITR           648 /* ~6000 ints/sec */
  48 #define IGB_4K_ITR              980
  49 #define IGB_20K_ITR             196
  50 #define IGB_70K_ITR             56
  51
  52 /* TX/RX descriptor defines */
  53 #define IGB_DEFAULT_TXD         256
  54 #define IGB_DEFAULT_TX_WORK     128
  55 #define IGB_MIN_TXD             80
  56 #define IGB_MAX_TXD             4096
  57
  58 #define IGB_DEFAULT_RXD         256
  59 #define IGB_MIN_RXD             80
  60 #define IGB_MAX_RXD             4096
  61
  62 #define IGB_DEFAULT_ITR         3 /* dynamic */
  63 #define IGB_MAX_ITR_USECS       10000
  64 #define IGB_MIN_ITR_USECS       10
  65 #define NON_Q_VECTORS           1
  66 #define MAX_Q_VECTORS           8
  67 #define MAX_MSIX_ENTRIES        10
  68
  69 /* Transmit and receive queues */
  70 #define IGB_MAX_RX_QUEUES       8
  71 #define IGB_MAX_RX_QUEUES_82575 4
  72 #define IGB_MAX_RX_QUEUES_I211  2
  73 #define IGB_MAX_TX_QUEUES       8
  74 #define IGB_MAX_VF_MC_ENTRIES   30
  75 #define IGB_MAX_VF_FUNCTIONS    8
  76 #define IGB_MAX_VFTA_ENTRIES    128
  77 #define IGB_82576_VF_DEV_ID     0x10CA
  78 #define IGB_I350_VF_DEV_ID      0x1520
  79
  80 /* NVM version defines */
  81 #define IGB_MAJOR_MASK          0xF000
  82 #define IGB_MINOR_MASK          0x0FF0
  83 #define IGB_BUILD_MASK          0x000F
  84 #define IGB_COMB_VER_MASK       0x00FF
  85 #define IGB_MAJOR_SHIFT         12
  86 #define IGB_MINOR_SHIFT         4
  87 #define IGB_COMB_VER_SHFT       8
  88 #define IGB_NVM_VER_INVALID     0xFFFF
  89 #define IGB_ETRACK_SHIFT        16
  90 #define NVM_ETRACK_WORD         0x0042
  91 #define NVM_COMB_VER_OFF        0x0083
  92 #define NVM_COMB_VER_PTR        0x003d
  93
  94 /* Transmit and receive latency (for PTP timestamps) */
  95 #define IGB_I210_TX_LATENCY_10          9542
  96 #define IGB_I210_TX_LATENCY_100         1024
  97 #define IGB_I210_TX_LATENCY_1000        178
  98 #define IGB_I210_RX_LATENCY_10          20662
  99 #define IGB_I210_RX_LATENCY_100         2213
 100 #define IGB_I210_RX_LATENCY_1000        448
 101
 102 struct vf_data_storage {
 103         unsigned char vf_mac_addresses[ETH_ALEN];
 104         u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
 105         u16 num_vf_mc_hashes;
 106         u32 flags;
 107         unsigned long last_nack;
 108         u16 pf_vlan; /* When set, guest VLAN config not allowed. */
 109         u16 pf_qos;
 110         u16 tx_rate;
 111         bool spoofchk_enabled;
 112 };
 113
 114 #define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
 115 #define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
 116 #define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
 117 #define IGB_VF_FLAG_PF_SET_MAC     0x00000008 /* PF has set MAC address */
 118
 119 /* RX descriptor control thresholds.
 120  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 121  *           descriptors available in its onboard memory.
 122  *           Setting this to 0 disables RX descriptor prefetch.
 123  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 124  *           available in host memory.
 125  *           If PTHRESH is 0, this should also be 0.
 126  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 127  *           descriptors until either it has this many to write back, or the
 128  *           ITR timer expires.
 129  */
 130 #define IGB_RX_PTHRESH  ((hw->mac.type == e1000_i354) ? 12 : 8)
 131 #define IGB_RX_HTHRESH  8
 132 #define IGB_TX_PTHRESH  ((hw->mac.type == e1000_i354) ? 20 : 8)
 133 #define IGB_TX_HTHRESH  1
 134 #define IGB_RX_WTHRESH  ((hw->mac.type == e1000_82576 && \
 135                           (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4)
 136 #define IGB_TX_WTHRESH  ((hw->mac.type == e1000_82576 && \
 137                           (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16)
 138
 139 /* this is the size past which hardware will drop packets when setting LPE=0 */
 140 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
 141
 142 /* Supported Rx Buffer Sizes */
 143 #define IGB_RXBUFFER_256        256
 144 #define IGB_RXBUFFER_2048       2048
 145 #define IGB_RX_HDR_LEN          IGB_RXBUFFER_256
 146 #define IGB_RX_BUFSZ            IGB_RXBUFFER_2048
 147
 148 /* How many Rx Buffers do we bundle into one write to the hardware ? */
 149 #define IGB_RX_BUFFER_WRITE     16 /* Must be power of 2 */
 150
 151 #define AUTO_ALL_MODES          0
 152 #define IGB_EEPROM_APME         0x0400
 153
 154 #ifndef IGB_MASTER_SLAVE
 155 /* Switch to override PHY master/slave setting */
 156 #define IGB_MASTER_SLAVE        e1000_ms_hw_default
 157 #endif
 158
 159 #define IGB_MNG_VLAN_NONE       -1
 160
 161 enum igb_tx_flags {
 162         /* cmd_type flags */
 163         IGB_TX_FLAGS_VLAN       = 0x01,
 164         IGB_TX_FLAGS_TSO        = 0x02,
 165         IGB_TX_FLAGS_TSTAMP     = 0x04,
 166
 167         /* olinfo flags */
 168         IGB_TX_FLAGS_IPV4       = 0x10,
 169         IGB_TX_FLAGS_CSUM       = 0x20,
 170 };
 171
 172 /* VLAN info */
 173 #define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
 174 #define IGB_TX_FLAGS_VLAN_SHIFT 16
 175
 176 /* The largest size we can write to the descriptor is 65535.  In order to
 177  * maintain a power of two alignment we have to limit ourselves to 32K.
 178  */
 179 #define IGB_MAX_TXD_PWR 15
 180 #define IGB_MAX_DATA_PER_TXD    (1u << IGB_MAX_TXD_PWR)
 181
 182 /* Tx Descriptors needed, worst case */
 183 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
 184 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
 185
 186 /* EEPROM byte offsets */
 187 #define IGB_SFF_8472_SWAP               0x5C
 188 #define IGB_SFF_8472_COMP               0x5E
 189
 190 /* Bitmasks */
 191 #define IGB_SFF_ADDRESSING_MODE         0x4
 192 #define IGB_SFF_8472_UNSUP              0x00
 193
 194 /* wrapper around a pointer to a socket buffer,
 195  * so a DMA handle can be stored along with the buffer
 196  */
 197 struct igb_tx_buffer {
 198         union e1000_adv_tx_desc *next_to_watch;
 199         unsigned long time_stamp;
 200         struct sk_buff *skb;
 201         unsigned int bytecount;
 202         u16 gso_segs;
 203         __be16 protocol;
 204
 205         DEFINE_DMA_UNMAP_ADDR(dma);
 206         DEFINE_DMA_UNMAP_LEN(len);
 207         u32 tx_flags;
 208 };
 209
 210 struct igb_rx_buffer {
 211         dma_addr_t dma;
 212         struct page *page;
 213         unsigned int page_offset;
 214 };
 215
 216 struct igb_tx_queue_stats {
 217         u64 packets;
 218         u64 bytes;
 219         u64 restart_queue;
 220         u64 restart_queue2;
 221 };
 222
 223 struct igb_rx_queue_stats {
 224         u64 packets;
 225         u64 bytes;
 226         u64 drops;
 227         u64 csum_err;
 228         u64 alloc_failed;
 229 };
 230
 231 struct igb_ring_container {
 232         struct igb_ring *ring;          /* pointer to linked list of rings */
 233         unsigned int total_bytes;       /* total bytes processed this int */
 234         unsigned int total_packets;     /* total packets processed this int */
 235         u16 work_limit;                 /* total work allowed per interrupt */
 236         u8 count;                       /* total number of rings in vector */
 237         u8 itr;                         /* current ITR setting for ring */
 238 };
 239
 240 struct igb_ring {
 241         struct igb_q_vector *q_vector;  /* backlink to q_vector */
 242         struct net_device *netdev;      /* back pointer to net_device */
 243         struct device *dev;             /* device pointer for dma mapping */
 244         union {                         /* array of buffer info structs */
 245                 struct igb_tx_buffer *tx_buffer_info;
 246                 struct igb_rx_buffer *rx_buffer_info;
 247         };
 248         void *desc;                     /* descriptor ring memory */
 249         unsigned long flags;            /* ring specific flags */
 250         void __iomem *tail;             /* pointer to ring tail register */
 251         dma_addr_t dma;                 /* phys address of the ring */
 252         unsigned int  size;             /* length of desc. ring in bytes */
 253
 254         u16 count;                      /* number of desc. in the ring */
 255         u8 queue_index;                 /* logical index of the ring*/
 256         u8 reg_idx;                     /* physical index of the ring */
 257
 258         /* everything past this point are written often */
 259         u16 next_to_clean;
 260         u16 next_to_use;
 261         u16 next_to_alloc;
 262
 263         union {
 264                 /* TX */
 265                 struct {
 266                         struct igb_tx_queue_stats tx_stats;
 267                         struct u64_stats_sync tx_syncp;
 268                         struct u64_stats_sync tx_syncp2;
 269                 };
 270                 /* RX */
 271                 struct {
 272                         struct sk_buff *skb;
 273                         struct igb_rx_queue_stats rx_stats;
 274                         struct u64_stats_sync rx_syncp;
 275                 };
 276         };
 277 } ____cacheline_internodealigned_in_smp;
 278
 279 struct igb_q_vector {
 280         struct igb_adapter *adapter;    /* backlink */
 281         int cpu;                        /* CPU for DCA */
 282         u32 eims_value;                 /* EIMS mask value */
 283
 284         u16 itr_val;
 285         u8 set_itr;
 286         void __iomem *itr_register;
 287
 288         struct igb_ring_container rx, tx;
 289
 290         struct napi_struct napi;
 291         struct rcu_head rcu;    /* to avoid race with update stats on free */
 292         char name[IFNAMSIZ + 9];
 293
 294         /* for dynamic allocation of rings associated with this q_vector */
 295         struct igb_ring ring[0] ____cacheline_internodealigned_in_smp;
 296 };
 297
 298 enum e1000_ring_flags_t {
 299         IGB_RING_FLAG_RX_SCTP_CSUM,
 300         IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
 301         IGB_RING_FLAG_TX_CTX_IDX,
 302         IGB_RING_FLAG_TX_DETECT_HANG
 303 };
 304
 305 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
 306
 307 #define IGB_RX_DESC(R, i)       \
 308         (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
 309 #define IGB_TX_DESC(R, i)       \
 310         (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
 311 #define IGB_TX_CTXTDESC(R, i)   \
 312         (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
 313
 314 /* igb_test_staterr - tests bits within Rx descriptor status and error fields */
 315 static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
 316                                       const u32 stat_err_bits)
 317 {
 318         return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
 319 }
 320
 321 /* igb_desc_unused - calculate if we have unused descriptors */
 322 static inline int igb_desc_unused(struct igb_ring *ring)
 323 {
 324         if (ring->next_to_clean > ring->next_to_use)
 325                 return ring->next_to_clean - ring->next_to_use - 1;
 326
 327         return ring->count + ring->next_to_clean - ring->next_to_use - 1;
 328 }
 329
 330 #ifdef CONFIG_IGB_HWMON
 331
 332 #define IGB_HWMON_TYPE_LOC      0
 333 #define IGB_HWMON_TYPE_TEMP     1
 334 #define IGB_HWMON_TYPE_CAUTION  2
 335 #define IGB_HWMON_TYPE_MAX      3
 336
 337 struct hwmon_attr {
 338         struct device_attribute dev_attr;
 339         struct e1000_hw *hw;
 340         struct e1000_thermal_diode_data *sensor;
 341         char name[12];
 342         };
 343
 344 struct hwmon_buff {
 345         struct attribute_group group;
 346         const struct attribute_group *groups[2];
 347         struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1];
 348         struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4];
 349         unsigned int n_hwmon;
 350         };
 351 #endif
 352
 353 /* The number of L2 ether-type filter registers, Index 3 is reserved
 354  * for PTP 1588 timestamp
 355  */
 356 #define MAX_ETYPE_FILTER        (4 - 1)
 357 /* ETQF filter list: one static filter per filter consumer. This is
 358  * to avoid filter collisions later. Add new filters here!!
 359  *
 360  * Current filters:             Filter 3
 361  */
 362 #define IGB_ETQF_FILTER_1588    3
 363
 364 #define IGB_N_EXTTS     2
 365 #define IGB_N_PEROUT    2
 366 #define IGB_N_SDP       4
 367 #define IGB_RETA_SIZE   128
 368
 369 enum igb_filter_match_flags {
 370         IGB_FILTER_FLAG_ETHER_TYPE = 0x1,
 371         IGB_FILTER_FLAG_VLAN_TCI   = 0x2,
 372 };
 373
 374 #define IGB_MAX_RXNFC_FILTERS 16
 375
 376 /* RX network flow classification data structure */
 377 struct igb_nfc_input {
 378         /* Byte layout in order, all values with MSB first:
 379          * match_flags - 1 byte
 380          * etype - 2 bytes
 381          * vlan_tci - 2 bytes
 382          */
 383         u8 match_flags;
 384         __be16 etype;
 385         __be16 vlan_tci;
 386 };
 387
 388 struct igb_nfc_filter {
 389         struct hlist_node nfc_node;
 390         struct igb_nfc_input filter;
 391         u16 etype_reg_index;
 392         u16 sw_idx;
 393         u16 action;
 394 };
 395
 396 /* board specific private data structure */
 397 struct igb_adapter {
 398         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 399
 400         struct net_device *netdev;
 401
 402         unsigned long state;
 403         unsigned int flags;
 404
 405         unsigned int num_q_vectors;
 406         struct msix_entry msix_entries[MAX_MSIX_ENTRIES];
 407
 408         /* Interrupt Throttle Rate */
 409         u32 rx_itr_setting;
 410         u32 tx_itr_setting;
 411         u16 tx_itr;
 412         u16 rx_itr;
 413
 414         /* TX */
 415         u16 tx_work_limit;
 416         u32 tx_timeout_count;
 417         int num_tx_queues;
 418         struct igb_ring *tx_ring[16];
 419
 420         /* RX */
 421         int num_rx_queues;
 422         struct igb_ring *rx_ring[16];
 423
 424         u32 max_frame_size;
 425         u32 min_frame_size;
 426
 427         struct timer_list watchdog_timer;
 428         struct timer_list phy_info_timer;
 429
 430         u16 mng_vlan_id;
 431         u32 bd_number;
 432         u32 wol;
 433         u32 en_mng_pt;
 434         u16 link_speed;
 435         u16 link_duplex;
 436
 437         u8 __iomem *io_addr; /* Mainly for iounmap use */
 438
 439         struct work_struct reset_task;
 440         struct work_struct watchdog_task;
 441         bool fc_autoneg;
 442         u8  tx_timeout_factor;
 443         struct timer_list blink_timer;
 444         unsigned long led_status;
 445
 446         /* OS defined structs */
 447         struct pci_dev *pdev;
 448
 449         spinlock_t stats64_lock;
 450         struct rtnl_link_stats64 stats64;
 451
 452         /* structs defined in e1000_hw.h */
 453         struct e1000_hw hw;
 454         struct e1000_hw_stats stats;
 455         struct e1000_phy_info phy_info;
 456
 457         u32 test_icr;
 458         struct igb_ring test_tx_ring;
 459         struct igb_ring test_rx_ring;
 460
 461         int msg_enable;
 462
 463         struct igb_q_vector *q_vector[MAX_Q_VECTORS];
 464         u32 eims_enable_mask;
 465         u32 eims_other;
 466
 467         /* to not mess up cache alignment, always add to the bottom */
 468         u16 tx_ring_count;
 469         u16 rx_ring_count;
 470         unsigned int vfs_allocated_count;
 471         struct vf_data_storage *vf_data;
 472         int vf_rate_link_speed;
 473         u32 rss_queues;
 474         u32 wvbr;
 475         u32 *shadow_vfta;
 476
 477         struct ptp_clock *ptp_clock;
 478         struct ptp_clock_info ptp_caps;
 479         struct delayed_work ptp_overflow_work;
 480         struct work_struct ptp_tx_work;
 481         struct sk_buff *ptp_tx_skb;
 482         struct hwtstamp_config tstamp_config;
 483         unsigned long ptp_tx_start;
 484         unsigned long last_rx_ptp_check;
 485         unsigned long last_rx_timestamp;
 486         unsigned int ptp_flags;
 487         spinlock_t tmreg_lock;
 488         struct cyclecounter cc;
 489         struct timecounter tc;
 490         u32 tx_hwtstamp_timeouts;
 491         u32 rx_hwtstamp_cleared;
 492
 493         struct ptp_pin_desc sdp_config[IGB_N_SDP];
 494         struct {
 495                 struct timespec64 start;
 496                 struct timespec64 period;
 497         } perout[IGB_N_PEROUT];
 498
 499         char fw_version[32];
 500 #ifdef CONFIG_IGB_HWMON
 501         struct hwmon_buff *igb_hwmon_buff;
 502         bool ets;
 503 #endif
 504         struct i2c_algo_bit_data i2c_algo;
 505         struct i2c_adapter i2c_adap;
 506         struct i2c_client *i2c_client;
 507         u32 rss_indir_tbl_init;
 508         u8 rss_indir_tbl[IGB_RETA_SIZE];
 509
 510         unsigned long link_check_timeout;
 511         int copper_tries;
 512         struct e1000_info ei;
 513         u16 eee_advert;
 514
 515         /* RX network flow classification support */
 516         struct hlist_head nfc_filter_list;
 517         unsigned int nfc_filter_count;
 518         /* lock for RX network flow classification filter */
 519         spinlock_t nfc_lock;
 520         bool etype_bitmap[MAX_ETYPE_FILTER];
 521 };
 522
 523 /* flags controlling PTP/1588 function */
 524 #define IGB_PTP_ENABLED         BIT(0)
 525 #define IGB_PTP_OVERFLOW_CHECK  BIT(1)
 526
 527 #define IGB_FLAG_HAS_MSI                BIT(0)
 528 #define IGB_FLAG_DCA_ENABLED            BIT(1)
 529 #define IGB_FLAG_QUAD_PORT_A            BIT(2)
 530 #define IGB_FLAG_QUEUE_PAIRS            BIT(3)
 531 #define IGB_FLAG_DMAC                   BIT(4)
 532 #define IGB_FLAG_RSS_FIELD_IPV4_UDP     BIT(6)
 533 #define IGB_FLAG_RSS_FIELD_IPV6_UDP     BIT(7)
 534 #define IGB_FLAG_WOL_SUPPORTED          BIT(8)
 535 #define IGB_FLAG_NEED_LINK_UPDATE       BIT(9)
 536 #define IGB_FLAG_MEDIA_RESET            BIT(10)
 537 #define IGB_FLAG_MAS_CAPABLE            BIT(11)
 538 #define IGB_FLAG_MAS_ENABLE             BIT(12)
 539 #define IGB_FLAG_HAS_MSIX               BIT(13)
 540 #define IGB_FLAG_EEE                    BIT(14)
 541 #define IGB_FLAG_VLAN_PROMISC           BIT(15)
 542
 543 /* Media Auto Sense */
 544 #define IGB_MAS_ENABLE_0                0X0001
 545 #define IGB_MAS_ENABLE_1                0X0002
 546 #define IGB_MAS_ENABLE_2                0X0004
 547 #define IGB_MAS_ENABLE_3                0X0008
 548
 549 /* DMA Coalescing defines */
 550 #define IGB_MIN_TXPBSIZE        20408
 551 #define IGB_TX_BUF_4096         4096
 552 #define IGB_DMCTLX_DCFLUSH_DIS  0x80000000  /* Disable DMA Coal Flush */
 553
 554 #define IGB_82576_TSYNC_SHIFT   19
 555 #define IGB_TS_HDR_LEN          16
 556 enum e1000_state_t {
 557         __IGB_TESTING,
 558         __IGB_RESETTING,
 559         __IGB_DOWN,
 560         __IGB_PTP_TX_IN_PROGRESS,
 561 };
 562
 563 enum igb_boards {
 564         board_82575,
 565 };
 566
 567 extern char igb_driver_name[];
 568 extern char igb_driver_version[];
 569
 570 int igb_open(struct net_device *netdev);
 571 int igb_close(struct net_device *netdev);
 572 int igb_up(struct igb_adapter *);
 573 void igb_down(struct igb_adapter *);
 574 void igb_reinit_locked(struct igb_adapter *);
 575 void igb_reset(struct igb_adapter *);
 576 int igb_reinit_queues(struct igb_adapter *);
 577 void igb_write_rss_indir_tbl(struct igb_adapter *);
 578 int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
 579 int igb_setup_tx_resources(struct igb_ring *);
 580 int igb_setup_rx_resources(struct igb_ring *);
 581 void igb_free_tx_resources(struct igb_ring *);
 582 void igb_free_rx_resources(struct igb_ring *);
 583 void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
 584 void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
 585 void igb_setup_tctl(struct igb_adapter *);
 586 void igb_setup_rctl(struct igb_adapter *);
 587 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
 588 void igb_unmap_and_free_tx_resource(struct igb_ring *, struct igb_tx_buffer *);
 589 void igb_alloc_rx_buffers(struct igb_ring *, u16);
 590 void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
 591 bool igb_has_link(struct igb_adapter *adapter);
 592 void igb_set_ethtool_ops(struct net_device *);
 593 void igb_power_up_link(struct igb_adapter *);
 594 void igb_set_fw_version(struct igb_adapter *);
 595 void igb_ptp_init(struct igb_adapter *adapter);
 596 void igb_ptp_stop(struct igb_adapter *adapter);
 597 void igb_ptp_reset(struct igb_adapter *adapter);
 598 void igb_ptp_suspend(struct igb_adapter *adapter);
 599 void igb_ptp_rx_hang(struct igb_adapter *adapter);
 600 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb);
 601 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, unsigned char *va,
 602                          struct sk_buff *skb);
 603 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
 604 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
 605 void igb_set_flag_queue_pairs(struct igb_adapter *, const u32);
 606 #ifdef CONFIG_IGB_HWMON
 607 void igb_sysfs_exit(struct igb_adapter *adapter);
 608 int igb_sysfs_init(struct igb_adapter *adapter);
 609 #endif
 610 static inline s32 igb_reset_phy(struct e1000_hw *hw)
 611 {
 612         if (hw->phy.ops.reset)
 613                 return hw->phy.ops.reset(hw);
 614
 615         return 0;
 616 }
 617
 618 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
 619 {
 620         if (hw->phy.ops.read_reg)
 621                 return hw->phy.ops.read_reg(hw, offset, data);
 622
 623         return 0;
 624 }
 625
 626 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
 627 {
 628         if (hw->phy.ops.write_reg)
 629                 return hw->phy.ops.write_reg(hw, offset, data);
 630
 631         return 0;
 632 }
 633
 634 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
 635 {
 636         if (hw->phy.ops.get_phy_info)
 637                 return hw->phy.ops.get_phy_info(hw);
 638
 639         return 0;
 640 }
 641
 642 static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
 643 {
 644         return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
 645 }
 646
 647 int igb_add_filter(struct igb_adapter *adapter,
 648                    struct igb_nfc_filter *input);
 649 int igb_erase_filter(struct igb_adapter *adapter,
 650                      struct igb_nfc_filter *input);
 651
 652 #endif /* _IGB_H_ */