1 /* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
3 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, see <http://www.gnu.org/licenses/>.
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/pci.h>
21 #include <linux/ptp_classify.h>
25 #define INCVALUE_MASK 0x7fffffff
26 #define ISGN 0x80000000
28 /* The 82580 timesync updates the system timer every 8ns by 8ns,
29 * and this update value cannot be reprogrammed.
31 * Neither the 82576 nor the 82580 offer registers wide enough to hold
32 * nanoseconds time values for very long. For the 82580, SYSTIM always
33 * counts nanoseconds, but the upper 24 bits are not available. The
34 * frequency is adjusted by changing the 32 bit fractional nanoseconds
37 * For the 82576, the SYSTIM register time unit is affect by the
38 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
39 * field are needed to provide the nominal 16 nanosecond period,
40 * leaving 19 bits for fractional nanoseconds.
42 * We scale the NIC clock cycle by a large factor so that relatively
43 * small clock corrections can be added or subtracted at each clock
44 * tick. The drawbacks of a large factor are a) that the clock
45 * register overflows more quickly (not such a big deal) and b) that
46 * the increment per tick has to fit into 24 bits. As a result we
47 * need to use a shift of 19 so we can fit a value of 16 into the
52 * +--------------+ +---+---+------+
53 * 82576 | 32 | | 8 | 5 | 19 |
54 * +--------------+ +---+---+------+
55 * \________ 45 bits _______/ fract
57 * +----------+---+ +--------------+
58 * 82580 | 24 | 8 | | 32 |
59 * +----------+---+ +--------------+
60 * reserved \______ 40 bits _____/
63 * The 45 bit 82576 SYSTIM overflows every
64 * 2^45 * 10^-9 / 3600 = 9.77 hours.
66 * The 40 bit 82580 SYSTIM overflows every
67 * 2^40 * 10^-9 / 60 = 18.3 minutes.
70 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9)
71 #define IGB_PTP_TX_TIMEOUT (HZ * 15)
72 #define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT)
73 #define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
74 #define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT)
75 #define IGB_NBITS_82580 40
77 static void igb_ptp_tx_hwtstamp(struct igb_adapter
*adapter
);
79 /* SYSTIM read access for the 82576 */
80 static cycle_t
igb_ptp_read_82576(const struct cyclecounter
*cc
)
82 struct igb_adapter
*igb
= container_of(cc
, struct igb_adapter
, cc
);
83 struct e1000_hw
*hw
= &igb
->hw
;
87 lo
= rd32(E1000_SYSTIML
);
88 hi
= rd32(E1000_SYSTIMH
);
90 val
= ((u64
) hi
) << 32;
96 /* SYSTIM read access for the 82580 */
97 static cycle_t
igb_ptp_read_82580(const struct cyclecounter
*cc
)
99 struct igb_adapter
*igb
= container_of(cc
, struct igb_adapter
, cc
);
100 struct e1000_hw
*hw
= &igb
->hw
;
104 /* The timestamp latches on lowest register read. For the 82580
105 * the lowest register is SYSTIMR instead of SYSTIML. However we only
106 * need to provide nanosecond resolution, so we just ignore it.
109 lo
= rd32(E1000_SYSTIML
);
110 hi
= rd32(E1000_SYSTIMH
);
112 val
= ((u64
) hi
) << 32;
118 /* SYSTIM read access for I210/I211 */
119 static void igb_ptp_read_i210(struct igb_adapter
*adapter
,
120 struct timespec64
*ts
)
122 struct e1000_hw
*hw
= &adapter
->hw
;
125 /* The timestamp latches on lowest register read. For I210/I211, the
126 * lowest register is SYSTIMR. Since we only need to provide nanosecond
127 * resolution, we can ignore it.
130 nsec
= rd32(E1000_SYSTIML
);
131 sec
= rd32(E1000_SYSTIMH
);
137 static void igb_ptp_write_i210(struct igb_adapter
*adapter
,
138 const struct timespec64
*ts
)
140 struct e1000_hw
*hw
= &adapter
->hw
;
142 /* Writing the SYSTIMR register is not necessary as it only provides
143 * sub-nanosecond resolution.
145 wr32(E1000_SYSTIML
, ts
->tv_nsec
);
146 wr32(E1000_SYSTIMH
, (u32
)ts
->tv_sec
);
150 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
151 * @adapter: board private structure
152 * @hwtstamps: timestamp structure to update
153 * @systim: unsigned 64bit system time value.
155 * We need to convert the system time value stored in the RX/TXSTMP registers
156 * into a hwtstamp which can be used by the upper level timestamping functions.
158 * The 'tmreg_lock' spinlock is used to protect the consistency of the
159 * system time value. This is needed because reading the 64 bit time
160 * value involves reading two (or three) 32 bit registers. The first
161 * read latches the value. Ditto for writing.
163 * In addition, here have extended the system time with an overflow
164 * counter in software.
166 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter
*adapter
,
167 struct skb_shared_hwtstamps
*hwtstamps
,
173 switch (adapter
->hw
.mac
.type
) {
178 spin_lock_irqsave(&adapter
->tmreg_lock
, flags
);
180 ns
= timecounter_cyc2time(&adapter
->tc
, systim
);
182 spin_unlock_irqrestore(&adapter
->tmreg_lock
, flags
);
184 memset(hwtstamps
, 0, sizeof(*hwtstamps
));
185 hwtstamps
->hwtstamp
= ns_to_ktime(ns
);
189 memset(hwtstamps
, 0, sizeof(*hwtstamps
));
190 /* Upper 32 bits contain s, lower 32 bits contain ns. */
191 hwtstamps
->hwtstamp
= ktime_set(systim
>> 32,
192 systim
& 0xFFFFFFFF);
199 /* PTP clock operations */
200 static int igb_ptp_adjfreq_82576(struct ptp_clock_info
*ptp
, s32 ppb
)
202 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
204 struct e1000_hw
*hw
= &igb
->hw
;
215 rate
= div_u64(rate
, 1953125);
217 incvalue
= 16 << IGB_82576_TSYNC_SHIFT
;
224 wr32(E1000_TIMINCA
, INCPERIOD_82576
| (incvalue
& INCVALUE_82576_MASK
));
229 static int igb_ptp_adjfreq_82580(struct ptp_clock_info
*ptp
, s32 ppb
)
231 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
233 struct e1000_hw
*hw
= &igb
->hw
;
244 rate
= div_u64(rate
, 1953125);
246 inca
= rate
& INCVALUE_MASK
;
250 wr32(E1000_TIMINCA
, inca
);
255 static int igb_ptp_adjtime_82576(struct ptp_clock_info
*ptp
, s64 delta
)
257 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
261 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
262 timecounter_adjtime(&igb
->tc
, delta
);
263 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
268 static int igb_ptp_adjtime_i210(struct ptp_clock_info
*ptp
, s64 delta
)
270 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
273 struct timespec64 now
, then
= ns_to_timespec64(delta
);
275 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
277 igb_ptp_read_i210(igb
, &now
);
278 now
= timespec64_add(now
, then
);
279 igb_ptp_write_i210(igb
, (const struct timespec64
*)&now
);
281 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
286 static int igb_ptp_gettime_82576(struct ptp_clock_info
*ptp
,
287 struct timespec64
*ts
)
289 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
294 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
296 ns
= timecounter_read(&igb
->tc
);
298 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
300 *ts
= ns_to_timespec64(ns
);
305 static int igb_ptp_gettime_i210(struct ptp_clock_info
*ptp
,
306 struct timespec64
*ts
)
308 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
312 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
314 igb_ptp_read_i210(igb
, ts
);
316 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
321 static int igb_ptp_settime_82576(struct ptp_clock_info
*ptp
,
322 const struct timespec64
*ts
)
324 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
329 ns
= timespec64_to_ns(ts
);
331 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
333 timecounter_init(&igb
->tc
, &igb
->cc
, ns
);
335 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
340 static int igb_ptp_settime_i210(struct ptp_clock_info
*ptp
,
341 const struct timespec64
*ts
)
343 struct igb_adapter
*igb
= container_of(ptp
, struct igb_adapter
,
347 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
349 igb_ptp_write_i210(igb
, ts
);
351 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
356 static void igb_pin_direction(int pin
, int input
, u32
*ctrl
, u32
*ctrl_ext
)
358 u32
*ptr
= pin
< 2 ? ctrl
: ctrl_ext
;
359 static const u32 mask
[IGB_N_SDP
] = {
362 E1000_CTRL_EXT_SDP2_DIR
,
363 E1000_CTRL_EXT_SDP3_DIR
,
372 static void igb_pin_extts(struct igb_adapter
*igb
, int chan
, int pin
)
374 static const u32 aux0_sel_sdp
[IGB_N_SDP
] = {
375 AUX0_SEL_SDP0
, AUX0_SEL_SDP1
, AUX0_SEL_SDP2
, AUX0_SEL_SDP3
,
377 static const u32 aux1_sel_sdp
[IGB_N_SDP
] = {
378 AUX1_SEL_SDP0
, AUX1_SEL_SDP1
, AUX1_SEL_SDP2
, AUX1_SEL_SDP3
,
380 static const u32 ts_sdp_en
[IGB_N_SDP
] = {
381 TS_SDP0_EN
, TS_SDP1_EN
, TS_SDP2_EN
, TS_SDP3_EN
,
383 struct e1000_hw
*hw
= &igb
->hw
;
384 u32 ctrl
, ctrl_ext
, tssdp
= 0;
386 ctrl
= rd32(E1000_CTRL
);
387 ctrl_ext
= rd32(E1000_CTRL_EXT
);
388 tssdp
= rd32(E1000_TSSDP
);
390 igb_pin_direction(pin
, 1, &ctrl
, &ctrl_ext
);
392 /* Make sure this pin is not enabled as an output. */
393 tssdp
&= ~ts_sdp_en
[pin
];
396 tssdp
&= ~AUX1_SEL_SDP3
;
397 tssdp
|= aux1_sel_sdp
[pin
] | AUX1_TS_SDP_EN
;
399 tssdp
&= ~AUX0_SEL_SDP3
;
400 tssdp
|= aux0_sel_sdp
[pin
] | AUX0_TS_SDP_EN
;
403 wr32(E1000_TSSDP
, tssdp
);
404 wr32(E1000_CTRL
, ctrl
);
405 wr32(E1000_CTRL_EXT
, ctrl_ext
);
408 static void igb_pin_perout(struct igb_adapter
*igb
, int chan
, int pin
, int freq
)
410 static const u32 aux0_sel_sdp
[IGB_N_SDP
] = {
411 AUX0_SEL_SDP0
, AUX0_SEL_SDP1
, AUX0_SEL_SDP2
, AUX0_SEL_SDP3
,
413 static const u32 aux1_sel_sdp
[IGB_N_SDP
] = {
414 AUX1_SEL_SDP0
, AUX1_SEL_SDP1
, AUX1_SEL_SDP2
, AUX1_SEL_SDP3
,
416 static const u32 ts_sdp_en
[IGB_N_SDP
] = {
417 TS_SDP0_EN
, TS_SDP1_EN
, TS_SDP2_EN
, TS_SDP3_EN
,
419 static const u32 ts_sdp_sel_tt0
[IGB_N_SDP
] = {
420 TS_SDP0_SEL_TT0
, TS_SDP1_SEL_TT0
,
421 TS_SDP2_SEL_TT0
, TS_SDP3_SEL_TT0
,
423 static const u32 ts_sdp_sel_tt1
[IGB_N_SDP
] = {
424 TS_SDP0_SEL_TT1
, TS_SDP1_SEL_TT1
,
425 TS_SDP2_SEL_TT1
, TS_SDP3_SEL_TT1
,
427 static const u32 ts_sdp_sel_fc0
[IGB_N_SDP
] = {
428 TS_SDP0_SEL_FC0
, TS_SDP1_SEL_FC0
,
429 TS_SDP2_SEL_FC0
, TS_SDP3_SEL_FC0
,
431 static const u32 ts_sdp_sel_fc1
[IGB_N_SDP
] = {
432 TS_SDP0_SEL_FC1
, TS_SDP1_SEL_FC1
,
433 TS_SDP2_SEL_FC1
, TS_SDP3_SEL_FC1
,
435 static const u32 ts_sdp_sel_clr
[IGB_N_SDP
] = {
436 TS_SDP0_SEL_FC1
, TS_SDP1_SEL_FC1
,
437 TS_SDP2_SEL_FC1
, TS_SDP3_SEL_FC1
,
439 struct e1000_hw
*hw
= &igb
->hw
;
440 u32 ctrl
, ctrl_ext
, tssdp
= 0;
442 ctrl
= rd32(E1000_CTRL
);
443 ctrl_ext
= rd32(E1000_CTRL_EXT
);
444 tssdp
= rd32(E1000_TSSDP
);
446 igb_pin_direction(pin
, 0, &ctrl
, &ctrl_ext
);
448 /* Make sure this pin is not enabled as an input. */
449 if ((tssdp
& AUX0_SEL_SDP3
) == aux0_sel_sdp
[pin
])
450 tssdp
&= ~AUX0_TS_SDP_EN
;
452 if ((tssdp
& AUX1_SEL_SDP3
) == aux1_sel_sdp
[pin
])
453 tssdp
&= ~AUX1_TS_SDP_EN
;
455 tssdp
&= ~ts_sdp_sel_clr
[pin
];
458 tssdp
|= ts_sdp_sel_fc1
[pin
];
460 tssdp
|= ts_sdp_sel_fc0
[pin
];
463 tssdp
|= ts_sdp_sel_tt1
[pin
];
465 tssdp
|= ts_sdp_sel_tt0
[pin
];
467 tssdp
|= ts_sdp_en
[pin
];
469 wr32(E1000_TSSDP
, tssdp
);
470 wr32(E1000_CTRL
, ctrl
);
471 wr32(E1000_CTRL_EXT
, ctrl_ext
);
474 static int igb_ptp_feature_enable_i210(struct ptp_clock_info
*ptp
,
475 struct ptp_clock_request
*rq
, int on
)
477 struct igb_adapter
*igb
=
478 container_of(ptp
, struct igb_adapter
, ptp_caps
);
479 struct e1000_hw
*hw
= &igb
->hw
;
480 u32 tsauxc
, tsim
, tsauxc_mask
, tsim_mask
, trgttiml
, trgttimh
, freqout
;
482 struct timespec64 ts
;
483 int use_freq
= 0, pin
= -1;
487 case PTP_CLK_REQ_EXTTS
:
489 pin
= ptp_find_pin(igb
->ptp_clock
, PTP_PF_EXTTS
,
494 if (rq
->extts
.index
== 1) {
495 tsauxc_mask
= TSAUXC_EN_TS1
;
496 tsim_mask
= TSINTR_AUTT1
;
498 tsauxc_mask
= TSAUXC_EN_TS0
;
499 tsim_mask
= TSINTR_AUTT0
;
501 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
502 tsauxc
= rd32(E1000_TSAUXC
);
503 tsim
= rd32(E1000_TSIM
);
505 igb_pin_extts(igb
, rq
->extts
.index
, pin
);
506 tsauxc
|= tsauxc_mask
;
509 tsauxc
&= ~tsauxc_mask
;
512 wr32(E1000_TSAUXC
, tsauxc
);
513 wr32(E1000_TSIM
, tsim
);
514 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
517 case PTP_CLK_REQ_PEROUT
:
519 pin
= ptp_find_pin(igb
->ptp_clock
, PTP_PF_PEROUT
,
524 ts
.tv_sec
= rq
->perout
.period
.sec
;
525 ts
.tv_nsec
= rq
->perout
.period
.nsec
;
526 ns
= timespec64_to_ns(&ts
);
528 if (on
&& ((ns
<= 70000000LL) || (ns
== 125000000LL) ||
529 (ns
== 250000000LL) || (ns
== 500000000LL))) {
534 ts
= ns_to_timespec64(ns
);
535 if (rq
->perout
.index
== 1) {
537 tsauxc_mask
= TSAUXC_EN_CLK1
| TSAUXC_ST1
;
540 tsauxc_mask
= TSAUXC_EN_TT1
;
541 tsim_mask
= TSINTR_TT1
;
543 trgttiml
= E1000_TRGTTIML1
;
544 trgttimh
= E1000_TRGTTIMH1
;
545 freqout
= E1000_FREQOUT1
;
548 tsauxc_mask
= TSAUXC_EN_CLK0
| TSAUXC_ST0
;
551 tsauxc_mask
= TSAUXC_EN_TT0
;
552 tsim_mask
= TSINTR_TT0
;
554 trgttiml
= E1000_TRGTTIML0
;
555 trgttimh
= E1000_TRGTTIMH0
;
556 freqout
= E1000_FREQOUT0
;
558 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
559 tsauxc
= rd32(E1000_TSAUXC
);
560 tsim
= rd32(E1000_TSIM
);
561 if (rq
->perout
.index
== 1) {
562 tsauxc
&= ~(TSAUXC_EN_TT1
| TSAUXC_EN_CLK1
| TSAUXC_ST1
);
565 tsauxc
&= ~(TSAUXC_EN_TT0
| TSAUXC_EN_CLK0
| TSAUXC_ST0
);
569 int i
= rq
->perout
.index
;
570 igb_pin_perout(igb
, i
, pin
, use_freq
);
571 igb
->perout
[i
].start
.tv_sec
= rq
->perout
.start
.sec
;
572 igb
->perout
[i
].start
.tv_nsec
= rq
->perout
.start
.nsec
;
573 igb
->perout
[i
].period
.tv_sec
= ts
.tv_sec
;
574 igb
->perout
[i
].period
.tv_nsec
= ts
.tv_nsec
;
575 wr32(trgttimh
, rq
->perout
.start
.sec
);
576 wr32(trgttiml
, rq
->perout
.start
.nsec
);
579 tsauxc
|= tsauxc_mask
;
582 wr32(E1000_TSAUXC
, tsauxc
);
583 wr32(E1000_TSIM
, tsim
);
584 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
587 case PTP_CLK_REQ_PPS
:
588 spin_lock_irqsave(&igb
->tmreg_lock
, flags
);
589 tsim
= rd32(E1000_TSIM
);
591 tsim
|= TSINTR_SYS_WRAP
;
593 tsim
&= ~TSINTR_SYS_WRAP
;
594 wr32(E1000_TSIM
, tsim
);
595 spin_unlock_irqrestore(&igb
->tmreg_lock
, flags
);
602 static int igb_ptp_feature_enable(struct ptp_clock_info
*ptp
,
603 struct ptp_clock_request
*rq
, int on
)
608 static int igb_ptp_verify_pin(struct ptp_clock_info
*ptp
, unsigned int pin
,
609 enum ptp_pin_function func
, unsigned int chan
)
624 * @work: pointer to work struct
626 * This work function polls the TSYNCTXCTL valid bit to determine when a
627 * timestamp has been taken for the current stored skb.
629 static void igb_ptp_tx_work(struct work_struct
*work
)
631 struct igb_adapter
*adapter
= container_of(work
, struct igb_adapter
,
633 struct e1000_hw
*hw
= &adapter
->hw
;
636 if (!adapter
->ptp_tx_skb
)
639 if (time_is_before_jiffies(adapter
->ptp_tx_start
+
640 IGB_PTP_TX_TIMEOUT
)) {
641 dev_kfree_skb_any(adapter
->ptp_tx_skb
);
642 adapter
->ptp_tx_skb
= NULL
;
643 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS
, &adapter
->state
);
644 adapter
->tx_hwtstamp_timeouts
++;
645 dev_warn(&adapter
->pdev
->dev
, "clearing Tx timestamp hang\n");
649 tsynctxctl
= rd32(E1000_TSYNCTXCTL
);
650 if (tsynctxctl
& E1000_TSYNCTXCTL_VALID
)
651 igb_ptp_tx_hwtstamp(adapter
);
653 /* reschedule to check later */
654 schedule_work(&adapter
->ptp_tx_work
);
657 static void igb_ptp_overflow_check(struct work_struct
*work
)
659 struct igb_adapter
*igb
=
660 container_of(work
, struct igb_adapter
, ptp_overflow_work
.work
);
661 struct timespec64 ts
;
663 igb
->ptp_caps
.gettime64(&igb
->ptp_caps
, &ts
);
665 pr_debug("igb overflow check at %lld.%09lu\n",
666 (long long) ts
.tv_sec
, ts
.tv_nsec
);
668 schedule_delayed_work(&igb
->ptp_overflow_work
,
669 IGB_SYSTIM_OVERFLOW_PERIOD
);
673 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
674 * @adapter: private network adapter structure
676 * This watchdog task is scheduled to detect error case where hardware has
677 * dropped an Rx packet that was timestamped when the ring is full. The
678 * particular error is rare but leaves the device in a state unable to timestamp
679 * any future packets.
681 void igb_ptp_rx_hang(struct igb_adapter
*adapter
)
683 struct e1000_hw
*hw
= &adapter
->hw
;
684 u32 tsyncrxctl
= rd32(E1000_TSYNCRXCTL
);
685 unsigned long rx_event
;
687 /* Other hardware uses per-packet timestamps */
688 if (hw
->mac
.type
!= e1000_82576
)
691 /* If we don't have a valid timestamp in the registers, just update the
692 * timeout counter and exit
694 if (!(tsyncrxctl
& E1000_TSYNCRXCTL_VALID
)) {
695 adapter
->last_rx_ptp_check
= jiffies
;
699 /* Determine the most recent watchdog or rx_timestamp event */
700 rx_event
= adapter
->last_rx_ptp_check
;
701 if (time_after(adapter
->last_rx_timestamp
, rx_event
))
702 rx_event
= adapter
->last_rx_timestamp
;
704 /* Only need to read the high RXSTMP register to clear the lock */
705 if (time_is_before_jiffies(rx_event
+ 5 * HZ
)) {
707 adapter
->last_rx_ptp_check
= jiffies
;
708 adapter
->rx_hwtstamp_cleared
++;
709 dev_warn(&adapter
->pdev
->dev
, "clearing Rx timestamp hang\n");
714 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
715 * @adapter: Board private structure.
717 * If we were asked to do hardware stamping and such a time stamp is
718 * available, then it must have been for this skb here because we only
719 * allow only one such packet into the queue.
721 static void igb_ptp_tx_hwtstamp(struct igb_adapter
*adapter
)
723 struct e1000_hw
*hw
= &adapter
->hw
;
724 struct skb_shared_hwtstamps shhwtstamps
;
728 regval
= rd32(E1000_TXSTMPL
);
729 regval
|= (u64
)rd32(E1000_TXSTMPH
) << 32;
731 igb_ptp_systim_to_hwtstamp(adapter
, &shhwtstamps
, regval
);
732 /* adjust timestamp for the TX latency based on link speed */
733 if (adapter
->hw
.mac
.type
== e1000_i210
) {
734 switch (adapter
->link_speed
) {
736 adjust
= IGB_I210_TX_LATENCY_10
;
739 adjust
= IGB_I210_TX_LATENCY_100
;
742 adjust
= IGB_I210_TX_LATENCY_1000
;
747 shhwtstamps
.hwtstamp
=
748 ktime_add_ns(shhwtstamps
.hwtstamp
, adjust
);
750 skb_tstamp_tx(adapter
->ptp_tx_skb
, &shhwtstamps
);
751 dev_kfree_skb_any(adapter
->ptp_tx_skb
);
752 adapter
->ptp_tx_skb
= NULL
;
753 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS
, &adapter
->state
);
757 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
758 * @q_vector: Pointer to interrupt specific structure
759 * @va: Pointer to address containing Rx buffer
760 * @skb: Buffer containing timestamp and packet
762 * This function is meant to retrieve a timestamp from the first buffer of an
763 * incoming frame. The value is stored in little endian format starting on
766 void igb_ptp_rx_pktstamp(struct igb_q_vector
*q_vector
,
770 __le64
*regval
= (__le64
*)va
;
771 struct igb_adapter
*adapter
= q_vector
->adapter
;
774 /* The timestamp is recorded in little endian format.
776 * Field: Reserved Reserved SYSTIML SYSTIMH
778 igb_ptp_systim_to_hwtstamp(adapter
, skb_hwtstamps(skb
),
779 le64_to_cpu(regval
[1]));
781 /* adjust timestamp for the RX latency based on link speed */
782 if (adapter
->hw
.mac
.type
== e1000_i210
) {
783 switch (adapter
->link_speed
) {
785 adjust
= IGB_I210_RX_LATENCY_10
;
788 adjust
= IGB_I210_RX_LATENCY_100
;
791 adjust
= IGB_I210_RX_LATENCY_1000
;
795 skb_hwtstamps(skb
)->hwtstamp
=
796 ktime_sub_ns(skb_hwtstamps(skb
)->hwtstamp
, adjust
);
800 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
801 * @q_vector: Pointer to interrupt specific structure
802 * @skb: Buffer containing timestamp and packet
804 * This function is meant to retrieve a timestamp from the internal registers
805 * of the adapter and store it in the skb.
807 void igb_ptp_rx_rgtstamp(struct igb_q_vector
*q_vector
,
810 struct igb_adapter
*adapter
= q_vector
->adapter
;
811 struct e1000_hw
*hw
= &adapter
->hw
;
815 /* If this bit is set, then the RX registers contain the time stamp. No
816 * other packet will be time stamped until we read these registers, so
817 * read the registers to make them available again. Because only one
818 * packet can be time stamped at a time, we know that the register
819 * values must belong to this one here and therefore we don't need to
820 * compare any of the additional attributes stored for it.
822 * If nothing went wrong, then it should have a shared tx_flags that we
823 * can turn into a skb_shared_hwtstamps.
825 if (!(rd32(E1000_TSYNCRXCTL
) & E1000_TSYNCRXCTL_VALID
))
828 regval
= rd32(E1000_RXSTMPL
);
829 regval
|= (u64
)rd32(E1000_RXSTMPH
) << 32;
831 igb_ptp_systim_to_hwtstamp(adapter
, skb_hwtstamps(skb
), regval
);
833 /* adjust timestamp for the RX latency based on link speed */
834 if (adapter
->hw
.mac
.type
== e1000_i210
) {
835 switch (adapter
->link_speed
) {
837 adjust
= IGB_I210_RX_LATENCY_10
;
840 adjust
= IGB_I210_RX_LATENCY_100
;
843 adjust
= IGB_I210_RX_LATENCY_1000
;
847 skb_hwtstamps(skb
)->hwtstamp
=
848 ktime_sub_ns(skb_hwtstamps(skb
)->hwtstamp
, adjust
);
850 /* Update the last_rx_timestamp timer in order to enable watchdog check
851 * for error case of latched timestamp on a dropped packet.
853 adapter
->last_rx_timestamp
= jiffies
;
857 * igb_ptp_get_ts_config - get hardware time stamping config
861 * Get the hwtstamp_config settings to return to the user. Rather than attempt
862 * to deconstruct the settings from the registers, just return a shadow copy
863 * of the last known settings.
865 int igb_ptp_get_ts_config(struct net_device
*netdev
, struct ifreq
*ifr
)
867 struct igb_adapter
*adapter
= netdev_priv(netdev
);
868 struct hwtstamp_config
*config
= &adapter
->tstamp_config
;
870 return copy_to_user(ifr
->ifr_data
, config
, sizeof(*config
)) ?
875 * igb_ptp_set_timestamp_mode - setup hardware for timestamping
876 * @adapter: networking device structure
877 * @config: hwtstamp configuration
879 * Outgoing time stamping can be enabled and disabled. Play nice and
880 * disable it when requested, although it shouldn't case any overhead
881 * when no packet needs it. At most one packet in the queue may be
882 * marked for time stamping, otherwise it would be impossible to tell
883 * for sure to which packet the hardware time stamp belongs.
885 * Incoming time stamping has to be configured via the hardware
886 * filters. Not all combinations are supported, in particular event
887 * type has to be specified. Matching the kind of event packet is
888 * not supported, with the exception of "all V2 events regardless of
891 static int igb_ptp_set_timestamp_mode(struct igb_adapter
*adapter
,
892 struct hwtstamp_config
*config
)
894 struct e1000_hw
*hw
= &adapter
->hw
;
895 u32 tsync_tx_ctl
= E1000_TSYNCTXCTL_ENABLED
;
896 u32 tsync_rx_ctl
= E1000_TSYNCRXCTL_ENABLED
;
897 u32 tsync_rx_cfg
= 0;
902 /* reserved for future extensions */
906 switch (config
->tx_type
) {
907 case HWTSTAMP_TX_OFF
:
915 switch (config
->rx_filter
) {
916 case HWTSTAMP_FILTER_NONE
:
919 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
920 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_L4_V1
;
921 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE
;
924 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
925 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_L4_V1
;
926 tsync_rx_cfg
= E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE
;
929 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
930 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
931 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
932 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
933 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
934 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
935 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
936 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
937 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
938 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_EVENT_V2
;
939 config
->rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
943 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
944 case HWTSTAMP_FILTER_ALL
:
945 /* 82576 cannot timestamp all packets, which it needs to do to
946 * support both V1 Sync and Delay_Req messages
948 if (hw
->mac
.type
!= e1000_82576
) {
949 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_ALL
;
950 config
->rx_filter
= HWTSTAMP_FILTER_ALL
;
955 config
->rx_filter
= HWTSTAMP_FILTER_NONE
;
959 if (hw
->mac
.type
== e1000_82575
) {
960 if (tsync_rx_ctl
| tsync_tx_ctl
)
965 /* Per-packet timestamping only works if all packets are
966 * timestamped, so enable timestamping in all packets as
967 * long as one Rx filter was configured.
969 if ((hw
->mac
.type
>= e1000_82580
) && tsync_rx_ctl
) {
970 tsync_rx_ctl
= E1000_TSYNCRXCTL_ENABLED
;
971 tsync_rx_ctl
|= E1000_TSYNCRXCTL_TYPE_ALL
;
972 config
->rx_filter
= HWTSTAMP_FILTER_ALL
;
976 if ((hw
->mac
.type
== e1000_i210
) ||
977 (hw
->mac
.type
== e1000_i211
)) {
978 regval
= rd32(E1000_RXPBS
);
979 regval
|= E1000_RXPBS_CFG_TS_EN
;
980 wr32(E1000_RXPBS
, regval
);
984 /* enable/disable TX */
985 regval
= rd32(E1000_TSYNCTXCTL
);
986 regval
&= ~E1000_TSYNCTXCTL_ENABLED
;
987 regval
|= tsync_tx_ctl
;
988 wr32(E1000_TSYNCTXCTL
, regval
);
990 /* enable/disable RX */
991 regval
= rd32(E1000_TSYNCRXCTL
);
992 regval
&= ~(E1000_TSYNCRXCTL_ENABLED
| E1000_TSYNCRXCTL_TYPE_MASK
);
993 regval
|= tsync_rx_ctl
;
994 wr32(E1000_TSYNCRXCTL
, regval
);
996 /* define which PTP packets are time stamped */
997 wr32(E1000_TSYNCRXCFG
, tsync_rx_cfg
);
999 /* define ethertype filter for timestamped packets */
1002 (E1000_ETQF_FILTER_ENABLE
| /* enable filter */
1003 E1000_ETQF_1588
| /* enable timestamping */
1004 ETH_P_1588
)); /* 1588 eth protocol type */
1006 wr32(E1000_ETQF(3), 0);
1008 /* L4 Queue Filter[3]: filter by destination port and protocol */
1010 u32 ftqf
= (IPPROTO_UDP
/* UDP */
1011 | E1000_FTQF_VF_BP
/* VF not compared */
1012 | E1000_FTQF_1588_TIME_STAMP
/* Enable Timestamping */
1013 | E1000_FTQF_MASK
); /* mask all inputs */
1014 ftqf
&= ~E1000_FTQF_MASK_PROTO_BP
; /* enable protocol check */
1016 wr32(E1000_IMIR(3), htons(PTP_EV_PORT
));
1017 wr32(E1000_IMIREXT(3),
1018 (E1000_IMIREXT_SIZE_BP
| E1000_IMIREXT_CTRL_BP
));
1019 if (hw
->mac
.type
== e1000_82576
) {
1020 /* enable source port check */
1021 wr32(E1000_SPQF(3), htons(PTP_EV_PORT
));
1022 ftqf
&= ~E1000_FTQF_MASK_SOURCE_PORT_BP
;
1024 wr32(E1000_FTQF(3), ftqf
);
1026 wr32(E1000_FTQF(3), E1000_FTQF_MASK
);
1030 /* clear TX/RX time stamp registers, just to be sure */
1031 regval
= rd32(E1000_TXSTMPL
);
1032 regval
= rd32(E1000_TXSTMPH
);
1033 regval
= rd32(E1000_RXSTMPL
);
1034 regval
= rd32(E1000_RXSTMPH
);
1040 * igb_ptp_set_ts_config - set hardware time stamping config
1045 int igb_ptp_set_ts_config(struct net_device
*netdev
, struct ifreq
*ifr
)
1047 struct igb_adapter
*adapter
= netdev_priv(netdev
);
1048 struct hwtstamp_config config
;
1051 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
1054 err
= igb_ptp_set_timestamp_mode(adapter
, &config
);
1058 /* save these settings for future reference */
1059 memcpy(&adapter
->tstamp_config
, &config
,
1060 sizeof(adapter
->tstamp_config
));
1062 return copy_to_user(ifr
->ifr_data
, &config
, sizeof(config
)) ?
1067 * igb_ptp_init - Initialize PTP functionality
1068 * @adapter: Board private structure
1070 * This function is called at device probe to initialize the PTP
1073 void igb_ptp_init(struct igb_adapter
*adapter
)
1075 struct e1000_hw
*hw
= &adapter
->hw
;
1076 struct net_device
*netdev
= adapter
->netdev
;
1079 switch (hw
->mac
.type
) {
1081 snprintf(adapter
->ptp_caps
.name
, 16, "%pm", netdev
->dev_addr
);
1082 adapter
->ptp_caps
.owner
= THIS_MODULE
;
1083 adapter
->ptp_caps
.max_adj
= 999999881;
1084 adapter
->ptp_caps
.n_ext_ts
= 0;
1085 adapter
->ptp_caps
.pps
= 0;
1086 adapter
->ptp_caps
.adjfreq
= igb_ptp_adjfreq_82576
;
1087 adapter
->ptp_caps
.adjtime
= igb_ptp_adjtime_82576
;
1088 adapter
->ptp_caps
.gettime64
= igb_ptp_gettime_82576
;
1089 adapter
->ptp_caps
.settime64
= igb_ptp_settime_82576
;
1090 adapter
->ptp_caps
.enable
= igb_ptp_feature_enable
;
1091 adapter
->cc
.read
= igb_ptp_read_82576
;
1092 adapter
->cc
.mask
= CYCLECOUNTER_MASK(64);
1093 adapter
->cc
.mult
= 1;
1094 adapter
->cc
.shift
= IGB_82576_TSYNC_SHIFT
;
1095 adapter
->ptp_flags
|= IGB_PTP_OVERFLOW_CHECK
;
1100 snprintf(adapter
->ptp_caps
.name
, 16, "%pm", netdev
->dev_addr
);
1101 adapter
->ptp_caps
.owner
= THIS_MODULE
;
1102 adapter
->ptp_caps
.max_adj
= 62499999;
1103 adapter
->ptp_caps
.n_ext_ts
= 0;
1104 adapter
->ptp_caps
.pps
= 0;
1105 adapter
->ptp_caps
.adjfreq
= igb_ptp_adjfreq_82580
;
1106 adapter
->ptp_caps
.adjtime
= igb_ptp_adjtime_82576
;
1107 adapter
->ptp_caps
.gettime64
= igb_ptp_gettime_82576
;
1108 adapter
->ptp_caps
.settime64
= igb_ptp_settime_82576
;
1109 adapter
->ptp_caps
.enable
= igb_ptp_feature_enable
;
1110 adapter
->cc
.read
= igb_ptp_read_82580
;
1111 adapter
->cc
.mask
= CYCLECOUNTER_MASK(IGB_NBITS_82580
);
1112 adapter
->cc
.mult
= 1;
1113 adapter
->cc
.shift
= 0;
1114 adapter
->ptp_flags
|= IGB_PTP_OVERFLOW_CHECK
;
1118 for (i
= 0; i
< IGB_N_SDP
; i
++) {
1119 struct ptp_pin_desc
*ppd
= &adapter
->sdp_config
[i
];
1121 snprintf(ppd
->name
, sizeof(ppd
->name
), "SDP%d", i
);
1123 ppd
->func
= PTP_PF_NONE
;
1125 snprintf(adapter
->ptp_caps
.name
, 16, "%pm", netdev
->dev_addr
);
1126 adapter
->ptp_caps
.owner
= THIS_MODULE
;
1127 adapter
->ptp_caps
.max_adj
= 62499999;
1128 adapter
->ptp_caps
.n_ext_ts
= IGB_N_EXTTS
;
1129 adapter
->ptp_caps
.n_per_out
= IGB_N_PEROUT
;
1130 adapter
->ptp_caps
.n_pins
= IGB_N_SDP
;
1131 adapter
->ptp_caps
.pps
= 1;
1132 adapter
->ptp_caps
.pin_config
= adapter
->sdp_config
;
1133 adapter
->ptp_caps
.adjfreq
= igb_ptp_adjfreq_82580
;
1134 adapter
->ptp_caps
.adjtime
= igb_ptp_adjtime_i210
;
1135 adapter
->ptp_caps
.gettime64
= igb_ptp_gettime_i210
;
1136 adapter
->ptp_caps
.settime64
= igb_ptp_settime_i210
;
1137 adapter
->ptp_caps
.enable
= igb_ptp_feature_enable_i210
;
1138 adapter
->ptp_caps
.verify
= igb_ptp_verify_pin
;
1141 adapter
->ptp_clock
= NULL
;
1145 spin_lock_init(&adapter
->tmreg_lock
);
1146 INIT_WORK(&adapter
->ptp_tx_work
, igb_ptp_tx_work
);
1148 if (adapter
->ptp_flags
& IGB_PTP_OVERFLOW_CHECK
)
1149 INIT_DELAYED_WORK(&adapter
->ptp_overflow_work
,
1150 igb_ptp_overflow_check
);
1152 adapter
->tstamp_config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
1153 adapter
->tstamp_config
.tx_type
= HWTSTAMP_TX_OFF
;
1155 igb_ptp_reset(adapter
);
1157 adapter
->ptp_clock
= ptp_clock_register(&adapter
->ptp_caps
,
1158 &adapter
->pdev
->dev
);
1159 if (IS_ERR(adapter
->ptp_clock
)) {
1160 adapter
->ptp_clock
= NULL
;
1161 dev_err(&adapter
->pdev
->dev
, "ptp_clock_register failed\n");
1163 dev_info(&adapter
->pdev
->dev
, "added PHC on %s\n",
1164 adapter
->netdev
->name
);
1165 adapter
->ptp_flags
|= IGB_PTP_ENABLED
;
1170 * igb_ptp_suspend - Disable PTP work items and prepare for suspend
1171 * @adapter: Board private structure
1173 * This function stops the overflow check work and PTP Tx timestamp work, and
1174 * will prepare the device for OS suspend.
1176 void igb_ptp_suspend(struct igb_adapter
*adapter
)
1178 if (!(adapter
->ptp_flags
& IGB_PTP_ENABLED
))
1181 if (adapter
->ptp_flags
& IGB_PTP_OVERFLOW_CHECK
)
1182 cancel_delayed_work_sync(&adapter
->ptp_overflow_work
);
1184 cancel_work_sync(&adapter
->ptp_tx_work
);
1185 if (adapter
->ptp_tx_skb
) {
1186 dev_kfree_skb_any(adapter
->ptp_tx_skb
);
1187 adapter
->ptp_tx_skb
= NULL
;
1188 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS
, &adapter
->state
);
1193 * igb_ptp_stop - Disable PTP device and stop the overflow check.
1194 * @adapter: Board private structure.
1196 * This function stops the PTP support and cancels the delayed work.
1198 void igb_ptp_stop(struct igb_adapter
*adapter
)
1200 igb_ptp_suspend(adapter
);
1202 if (adapter
->ptp_clock
) {
1203 ptp_clock_unregister(adapter
->ptp_clock
);
1204 dev_info(&adapter
->pdev
->dev
, "removed PHC on %s\n",
1205 adapter
->netdev
->name
);
1206 adapter
->ptp_flags
&= ~IGB_PTP_ENABLED
;
1211 * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
1212 * @adapter: Board private structure.
1214 * This function handles the reset work required to re-enable the PTP device.
1216 void igb_ptp_reset(struct igb_adapter
*adapter
)
1218 struct e1000_hw
*hw
= &adapter
->hw
;
1219 unsigned long flags
;
1221 /* reset the tstamp_config */
1222 igb_ptp_set_timestamp_mode(adapter
, &adapter
->tstamp_config
);
1224 spin_lock_irqsave(&adapter
->tmreg_lock
, flags
);
1226 switch (adapter
->hw
.mac
.type
) {
1228 /* Dial the nominal frequency. */
1229 wr32(E1000_TIMINCA
, INCPERIOD_82576
| INCVALUE_82576
);
1236 wr32(E1000_TSAUXC
, 0x0);
1237 wr32(E1000_TSSDP
, 0x0);
1238 wr32(E1000_TSIM
, TSYNC_INTERRUPTS
);
1239 wr32(E1000_IMS
, E1000_IMS_TS
);
1242 /* No work to do. */
1246 /* Re-initialize the timer. */
1247 if ((hw
->mac
.type
== e1000_i210
) || (hw
->mac
.type
== e1000_i211
)) {
1248 struct timespec64 ts
= ktime_to_timespec64(ktime_get_real());
1250 igb_ptp_write_i210(adapter
, &ts
);
1252 timecounter_init(&adapter
->tc
, &adapter
->cc
,
1253 ktime_to_ns(ktime_get_real()));
1256 spin_unlock_irqrestore(&adapter
->tmreg_lock
, flags
);
1260 if (adapter
->ptp_flags
& IGB_PTP_OVERFLOW_CHECK
)
1261 schedule_delayed_work(&adapter
->ptp_overflow_work
,
1262 IGB_SYSTIM_OVERFLOW_PERIOD
);