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[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_82599.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2016 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/pci.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
32
33 #include "ixgbe.h"
34 #include "ixgbe_phy.h"
35 #include "ixgbe_mbx.h"
36
37 #define IXGBE_82599_MAX_TX_QUEUES 128
38 #define IXGBE_82599_MAX_RX_QUEUES 128
39 #define IXGBE_82599_RAR_ENTRIES 128
40 #define IXGBE_82599_MC_TBL_SIZE 128
41 #define IXGBE_82599_VFT_TBL_SIZE 128
42 #define IXGBE_82599_RX_PB_SIZE 512
43
44 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
47 static void
48 ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *, ixgbe_link_speed);
49 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg_wait_to_complete);
52 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw);
53 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete);
55 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
56 ixgbe_link_speed speed,
57 bool autoneg_wait_to_complete);
58 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
59 ixgbe_link_speed speed,
60 bool autoneg_wait_to_complete);
61 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
62 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
63 u8 dev_addr, u8 *data);
64 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
65 u8 dev_addr, u8 data);
66 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw);
67 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
68
69 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
70 {
71 u32 fwsm, manc, factps;
72
73 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
74 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
75 return false;
76
77 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
78 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
79 return false;
80
81 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw));
82 if (factps & IXGBE_FACTPS_MNGCG)
83 return false;
84
85 return true;
86 }
87
88 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
89 {
90 struct ixgbe_mac_info *mac = &hw->mac;
91
92 /* enable the laser control functions for SFP+ fiber
93 * and MNG not enabled
94 */
95 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
96 !ixgbe_mng_enabled(hw)) {
97 mac->ops.disable_tx_laser =
98 &ixgbe_disable_tx_laser_multispeed_fiber;
99 mac->ops.enable_tx_laser =
100 &ixgbe_enable_tx_laser_multispeed_fiber;
101 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
102 } else {
103 mac->ops.disable_tx_laser = NULL;
104 mac->ops.enable_tx_laser = NULL;
105 mac->ops.flap_tx_laser = NULL;
106 }
107
108 if (hw->phy.multispeed_fiber) {
109 /* Set up dual speed SFP+ support */
110 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
111 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599;
112 mac->ops.set_rate_select_speed =
113 ixgbe_set_hard_rate_select_speed;
114 } else {
115 if ((mac->ops.get_media_type(hw) ==
116 ixgbe_media_type_backplane) &&
117 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
118 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
119 !ixgbe_verify_lesm_fw_enabled_82599(hw))
120 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
121 else
122 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
123 }
124 }
125
126 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
127 {
128 s32 ret_val;
129 u16 list_offset, data_offset, data_value;
130
131 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
132 ixgbe_init_mac_link_ops_82599(hw);
133
134 hw->phy.ops.reset = NULL;
135
136 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
137 &data_offset);
138 if (ret_val)
139 return ret_val;
140
141 /* PHY config will finish before releasing the semaphore */
142 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
143 IXGBE_GSSR_MAC_CSR_SM);
144 if (ret_val)
145 return IXGBE_ERR_SWFW_SYNC;
146
147 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
148 goto setup_sfp_err;
149 while (data_value != 0xffff) {
150 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
151 IXGBE_WRITE_FLUSH(hw);
152 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
153 goto setup_sfp_err;
154 }
155
156 /* Release the semaphore */
157 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
158 /*
159 * Delay obtaining semaphore again to allow FW access,
160 * semaphore_delay is in ms usleep_range needs us.
161 */
162 usleep_range(hw->eeprom.semaphore_delay * 1000,
163 hw->eeprom.semaphore_delay * 2000);
164
165 /* Restart DSP and set SFI mode */
166 ret_val = hw->mac.ops.prot_autoc_write(hw,
167 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
168 false);
169
170 if (ret_val) {
171 hw_dbg(hw, " sfp module setup not complete\n");
172 return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
173 }
174 }
175
176 return 0;
177
178 setup_sfp_err:
179 /* Release the semaphore */
180 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
181 /* Delay obtaining semaphore again to allow FW access,
182 * semaphore_delay is in ms usleep_range needs us.
183 */
184 usleep_range(hw->eeprom.semaphore_delay * 1000,
185 hw->eeprom.semaphore_delay * 2000);
186 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
187 return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
188 }
189
190 /**
191 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
192 * @hw: pointer to hardware structure
193 * @locked: Return the if we locked for this read.
194 * @reg_val: Value we read from AUTOC
195 *
196 * For this part (82599) we need to wrap read-modify-writes with a possible
197 * FW/SW lock. It is assumed this lock will be freed with the next
198 * prot_autoc_write_82599(). Note, that locked can only be true in cases
199 * where this function doesn't return an error.
200 **/
201 static s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked,
202 u32 *reg_val)
203 {
204 s32 ret_val;
205
206 *locked = false;
207 /* If LESM is on then we need to hold the SW/FW semaphore. */
208 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
209 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
210 IXGBE_GSSR_MAC_CSR_SM);
211 if (ret_val)
212 return IXGBE_ERR_SWFW_SYNC;
213
214 *locked = true;
215 }
216
217 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
218 return 0;
219 }
220
221 /**
222 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
223 * @hw: pointer to hardware structure
224 * @reg_val: value to write to AUTOC
225 * @locked: bool to indicate whether the SW/FW lock was already taken by
226 * previous proc_autoc_read_82599.
227 *
228 * This part (82599) may need to hold a the SW/FW lock around all writes to
229 * AUTOC. Likewise after a write we need to do a pipeline reset.
230 **/
231 static s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
232 {
233 s32 ret_val = 0;
234
235 /* Blocked by MNG FW so bail */
236 if (ixgbe_check_reset_blocked(hw))
237 goto out;
238
239 /* We only need to get the lock if:
240 * - We didn't do it already (in the read part of a read-modify-write)
241 * - LESM is enabled.
242 */
243 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
244 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
245 IXGBE_GSSR_MAC_CSR_SM);
246 if (ret_val)
247 return IXGBE_ERR_SWFW_SYNC;
248
249 locked = true;
250 }
251
252 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
253 ret_val = ixgbe_reset_pipeline_82599(hw);
254
255 out:
256 /* Free the SW/FW semaphore as we either grabbed it here or
257 * already had it when this function was called.
258 */
259 if (locked)
260 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
261
262 return ret_val;
263 }
264
265 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
266 {
267 struct ixgbe_mac_info *mac = &hw->mac;
268
269 ixgbe_init_mac_link_ops_82599(hw);
270
271 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
272 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
273 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
274 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
275 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
276 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
277 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
278
279 return 0;
280 }
281
282 /**
283 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
284 * @hw: pointer to hardware structure
285 *
286 * Initialize any function pointers that were not able to be
287 * set during get_invariants because the PHY/SFP type was
288 * not known. Perform the SFP init if necessary.
289 *
290 **/
291 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
292 {
293 struct ixgbe_mac_info *mac = &hw->mac;
294 struct ixgbe_phy_info *phy = &hw->phy;
295 s32 ret_val;
296 u32 esdp;
297
298 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
299 /* Store flag indicating I2C bus access control unit. */
300 hw->phy.qsfp_shared_i2c_bus = true;
301
302 /* Initialize access to QSFP+ I2C bus */
303 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
304 esdp |= IXGBE_ESDP_SDP0_DIR;
305 esdp &= ~IXGBE_ESDP_SDP1_DIR;
306 esdp &= ~IXGBE_ESDP_SDP0;
307 esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
308 esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
309 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
310 IXGBE_WRITE_FLUSH(hw);
311
312 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599;
313 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599;
314 }
315
316 /* Identify the PHY or SFP module */
317 ret_val = phy->ops.identify(hw);
318
319 /* Setup function pointers based on detected SFP module and speeds */
320 ixgbe_init_mac_link_ops_82599(hw);
321
322 /* If copper media, overwrite with copper function pointers */
323 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
324 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
325 mac->ops.get_link_capabilities =
326 &ixgbe_get_copper_link_capabilities_generic;
327 }
328
329 /* Set necessary function pointers based on phy type */
330 switch (hw->phy.type) {
331 case ixgbe_phy_tn:
332 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
333 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
334 phy->ops.get_firmware_version =
335 &ixgbe_get_phy_firmware_version_tnx;
336 break;
337 default:
338 break;
339 }
340
341 return ret_val;
342 }
343
344 /**
345 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
346 * @hw: pointer to hardware structure
347 * @speed: pointer to link speed
348 * @autoneg: true when autoneg or autotry is enabled
349 *
350 * Determines the link capabilities by reading the AUTOC register.
351 **/
352 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
353 ixgbe_link_speed *speed,
354 bool *autoneg)
355 {
356 u32 autoc = 0;
357
358 /* Determine 1G link capabilities off of SFP+ type */
359 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
360 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
361 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
362 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
363 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
364 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
365 *speed = IXGBE_LINK_SPEED_1GB_FULL;
366 *autoneg = true;
367 return 0;
368 }
369
370 /*
371 * Determine link capabilities based on the stored value of AUTOC,
372 * which represents EEPROM defaults. If AUTOC value has not been
373 * stored, use the current register value.
374 */
375 if (hw->mac.orig_link_settings_stored)
376 autoc = hw->mac.orig_autoc;
377 else
378 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
379
380 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
381 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
382 *speed = IXGBE_LINK_SPEED_1GB_FULL;
383 *autoneg = false;
384 break;
385
386 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
387 *speed = IXGBE_LINK_SPEED_10GB_FULL;
388 *autoneg = false;
389 break;
390
391 case IXGBE_AUTOC_LMS_1G_AN:
392 *speed = IXGBE_LINK_SPEED_1GB_FULL;
393 *autoneg = true;
394 break;
395
396 case IXGBE_AUTOC_LMS_10G_SERIAL:
397 *speed = IXGBE_LINK_SPEED_10GB_FULL;
398 *autoneg = false;
399 break;
400
401 case IXGBE_AUTOC_LMS_KX4_KX_KR:
402 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
403 *speed = IXGBE_LINK_SPEED_UNKNOWN;
404 if (autoc & IXGBE_AUTOC_KR_SUPP)
405 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
406 if (autoc & IXGBE_AUTOC_KX4_SUPP)
407 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
408 if (autoc & IXGBE_AUTOC_KX_SUPP)
409 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
410 *autoneg = true;
411 break;
412
413 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
414 *speed = IXGBE_LINK_SPEED_100_FULL;
415 if (autoc & IXGBE_AUTOC_KR_SUPP)
416 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
417 if (autoc & IXGBE_AUTOC_KX4_SUPP)
418 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
419 if (autoc & IXGBE_AUTOC_KX_SUPP)
420 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
421 *autoneg = true;
422 break;
423
424 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
425 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
426 *autoneg = false;
427 break;
428
429 default:
430 return IXGBE_ERR_LINK_SETUP;
431 }
432
433 if (hw->phy.multispeed_fiber) {
434 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
435 IXGBE_LINK_SPEED_1GB_FULL;
436
437 /* QSFP must not enable auto-negotiation */
438 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
439 *autoneg = false;
440 else
441 *autoneg = true;
442 }
443
444 return 0;
445 }
446
447 /**
448 * ixgbe_get_media_type_82599 - Get media type
449 * @hw: pointer to hardware structure
450 *
451 * Returns the media type (fiber, copper, backplane)
452 **/
453 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
454 {
455 /* Detect if there is a copper PHY attached. */
456 switch (hw->phy.type) {
457 case ixgbe_phy_cu_unknown:
458 case ixgbe_phy_tn:
459 return ixgbe_media_type_copper;
460
461 default:
462 break;
463 }
464
465 switch (hw->device_id) {
466 case IXGBE_DEV_ID_82599_KX4:
467 case IXGBE_DEV_ID_82599_KX4_MEZZ:
468 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
469 case IXGBE_DEV_ID_82599_KR:
470 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
471 case IXGBE_DEV_ID_82599_XAUI_LOM:
472 /* Default device ID is mezzanine card KX/KX4 */
473 return ixgbe_media_type_backplane;
474
475 case IXGBE_DEV_ID_82599_SFP:
476 case IXGBE_DEV_ID_82599_SFP_FCOE:
477 case IXGBE_DEV_ID_82599_SFP_EM:
478 case IXGBE_DEV_ID_82599_SFP_SF2:
479 case IXGBE_DEV_ID_82599_SFP_SF_QP:
480 case IXGBE_DEV_ID_82599EN_SFP:
481 return ixgbe_media_type_fiber;
482
483 case IXGBE_DEV_ID_82599_CX4:
484 return ixgbe_media_type_cx4;
485
486 case IXGBE_DEV_ID_82599_T3_LOM:
487 return ixgbe_media_type_copper;
488
489 case IXGBE_DEV_ID_82599_LS:
490 return ixgbe_media_type_fiber_lco;
491
492 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
493 return ixgbe_media_type_fiber_qsfp;
494
495 default:
496 return ixgbe_media_type_unknown;
497 }
498 }
499
500 /**
501 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
502 * @hw: pointer to hardware structure
503 *
504 * Disables link, should be called during D3 power down sequence.
505 *
506 **/
507 static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
508 {
509 u32 autoc2_reg;
510 u16 ee_ctrl_2 = 0;
511
512 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
513
514 if (!ixgbe_mng_present(hw) && !hw->wol_enabled &&
515 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
516 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
517 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
518 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
519 }
520 }
521
522 /**
523 * ixgbe_start_mac_link_82599 - Setup MAC link settings
524 * @hw: pointer to hardware structure
525 * @autoneg_wait_to_complete: true when waiting for completion is needed
526 *
527 * Configures link settings based on values in the ixgbe_hw struct.
528 * Restarts the link. Performs autonegotiation if needed.
529 **/
530 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
531 bool autoneg_wait_to_complete)
532 {
533 u32 autoc_reg;
534 u32 links_reg;
535 u32 i;
536 s32 status = 0;
537 bool got_lock = false;
538
539 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
540 status = hw->mac.ops.acquire_swfw_sync(hw,
541 IXGBE_GSSR_MAC_CSR_SM);
542 if (status)
543 return status;
544
545 got_lock = true;
546 }
547
548 /* Restart link */
549 ixgbe_reset_pipeline_82599(hw);
550
551 if (got_lock)
552 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
553
554 /* Only poll for autoneg to complete if specified to do so */
555 if (autoneg_wait_to_complete) {
556 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
557 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
558 IXGBE_AUTOC_LMS_KX4_KX_KR ||
559 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
560 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
561 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
562 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
563 links_reg = 0; /* Just in case Autoneg time = 0 */
564 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
565 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
566 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
567 break;
568 msleep(100);
569 }
570 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
571 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
572 hw_dbg(hw, "Autoneg did not complete.\n");
573 }
574 }
575 }
576
577 /* Add delay to filter out noises during initial link setup */
578 msleep(50);
579
580 return status;
581 }
582
583 /**
584 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
585 * @hw: pointer to hardware structure
586 *
587 * The base drivers may require better control over SFP+ module
588 * PHY states. This includes selectively shutting down the Tx
589 * laser on the PHY, effectively halting physical link.
590 **/
591 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
592 {
593 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
594
595 /* Blocked by MNG FW so bail */
596 if (ixgbe_check_reset_blocked(hw))
597 return;
598
599 /* Disable tx laser; allow 100us to go dark per spec */
600 esdp_reg |= IXGBE_ESDP_SDP3;
601 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
602 IXGBE_WRITE_FLUSH(hw);
603 udelay(100);
604 }
605
606 /**
607 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
608 * @hw: pointer to hardware structure
609 *
610 * The base drivers may require better control over SFP+ module
611 * PHY states. This includes selectively turning on the Tx
612 * laser on the PHY, effectively starting physical link.
613 **/
614 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
615 {
616 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
617
618 /* Enable tx laser; allow 100ms to light up */
619 esdp_reg &= ~IXGBE_ESDP_SDP3;
620 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
621 IXGBE_WRITE_FLUSH(hw);
622 msleep(100);
623 }
624
625 /**
626 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
627 * @hw: pointer to hardware structure
628 *
629 * When the driver changes the link speeds that it can support,
630 * it sets autotry_restart to true to indicate that we need to
631 * initiate a new autotry session with the link partner. To do
632 * so, we set the speed then disable and re-enable the tx laser, to
633 * alert the link partner that it also needs to restart autotry on its
634 * end. This is consistent with true clause 37 autoneg, which also
635 * involves a loss of signal.
636 **/
637 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
638 {
639 /* Blocked by MNG FW so bail */
640 if (ixgbe_check_reset_blocked(hw))
641 return;
642
643 if (hw->mac.autotry_restart) {
644 ixgbe_disable_tx_laser_multispeed_fiber(hw);
645 ixgbe_enable_tx_laser_multispeed_fiber(hw);
646 hw->mac.autotry_restart = false;
647 }
648 }
649
650 /**
651 * ixgbe_set_hard_rate_select_speed - Set module link speed
652 * @hw: pointer to hardware structure
653 * @speed: link speed to set
654 *
655 * Set module link speed via RS0/RS1 rate select pins.
656 */
657 static void
658 ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed)
659 {
660 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
661
662 switch (speed) {
663 case IXGBE_LINK_SPEED_10GB_FULL:
664 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
665 break;
666 case IXGBE_LINK_SPEED_1GB_FULL:
667 esdp_reg &= ~IXGBE_ESDP_SDP5;
668 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
669 break;
670 default:
671 hw_dbg(hw, "Invalid fixed module speed\n");
672 return;
673 }
674
675 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
676 IXGBE_WRITE_FLUSH(hw);
677 }
678
679 /**
680 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
681 * @hw: pointer to hardware structure
682 * @speed: new link speed
683 * @autoneg_wait_to_complete: true when waiting for completion is needed
684 *
685 * Implements the Intel SmartSpeed algorithm.
686 **/
687 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
688 ixgbe_link_speed speed,
689 bool autoneg_wait_to_complete)
690 {
691 s32 status = 0;
692 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
693 s32 i, j;
694 bool link_up = false;
695 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
696
697 /* Set autoneg_advertised value based on input link speed */
698 hw->phy.autoneg_advertised = 0;
699
700 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
701 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
702
703 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
704 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
705
706 if (speed & IXGBE_LINK_SPEED_100_FULL)
707 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
708
709 /*
710 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
711 * autoneg advertisement if link is unable to be established at the
712 * highest negotiated rate. This can sometimes happen due to integrity
713 * issues with the physical media connection.
714 */
715
716 /* First, try to get link with full advertisement */
717 hw->phy.smart_speed_active = false;
718 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
719 status = ixgbe_setup_mac_link_82599(hw, speed,
720 autoneg_wait_to_complete);
721 if (status != 0)
722 goto out;
723
724 /*
725 * Wait for the controller to acquire link. Per IEEE 802.3ap,
726 * Section 73.10.2, we may have to wait up to 500ms if KR is
727 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
728 * Table 9 in the AN MAS.
729 */
730 for (i = 0; i < 5; i++) {
731 mdelay(100);
732
733 /* If we have link, just jump out */
734 status = hw->mac.ops.check_link(hw, &link_speed,
735 &link_up, false);
736 if (status != 0)
737 goto out;
738
739 if (link_up)
740 goto out;
741 }
742 }
743
744 /*
745 * We didn't get link. If we advertised KR plus one of KX4/KX
746 * (or BX4/BX), then disable KR and try again.
747 */
748 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
749 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
750 goto out;
751
752 /* Turn SmartSpeed on to disable KR support */
753 hw->phy.smart_speed_active = true;
754 status = ixgbe_setup_mac_link_82599(hw, speed,
755 autoneg_wait_to_complete);
756 if (status != 0)
757 goto out;
758
759 /*
760 * Wait for the controller to acquire link. 600ms will allow for
761 * the AN link_fail_inhibit_timer as well for multiple cycles of
762 * parallel detect, both 10g and 1g. This allows for the maximum
763 * connect attempts as defined in the AN MAS table 73-7.
764 */
765 for (i = 0; i < 6; i++) {
766 mdelay(100);
767
768 /* If we have link, just jump out */
769 status = hw->mac.ops.check_link(hw, &link_speed,
770 &link_up, false);
771 if (status != 0)
772 goto out;
773
774 if (link_up)
775 goto out;
776 }
777
778 /* We didn't get link. Turn SmartSpeed back off. */
779 hw->phy.smart_speed_active = false;
780 status = ixgbe_setup_mac_link_82599(hw, speed,
781 autoneg_wait_to_complete);
782
783 out:
784 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
785 hw_dbg(hw, "Smartspeed has downgraded the link speed from the maximum advertised\n");
786 return status;
787 }
788
789 /**
790 * ixgbe_setup_mac_link_82599 - Set MAC link speed
791 * @hw: pointer to hardware structure
792 * @speed: new link speed
793 * @autoneg_wait_to_complete: true when waiting for completion is needed
794 *
795 * Set the link speed in the AUTOC register and restarts link.
796 **/
797 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
798 ixgbe_link_speed speed,
799 bool autoneg_wait_to_complete)
800 {
801 bool autoneg = false;
802 s32 status;
803 u32 pma_pmd_1g, link_mode, links_reg, i;
804 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
805 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
806 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
807
808 /* holds the value of AUTOC register at this current point in time */
809 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
810 /* holds the cached value of AUTOC register */
811 u32 orig_autoc = 0;
812 /* temporary variable used for comparison purposes */
813 u32 autoc = current_autoc;
814
815 /* Check to see if speed passed in is supported. */
816 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities,
817 &autoneg);
818 if (status)
819 return status;
820
821 speed &= link_capabilities;
822
823 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
824 return IXGBE_ERR_LINK_SETUP;
825
826 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
827 if (hw->mac.orig_link_settings_stored)
828 orig_autoc = hw->mac.orig_autoc;
829 else
830 orig_autoc = autoc;
831
832 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
833 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
834
835 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
836 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
837 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
838 /* Set KX4/KX/KR support according to speed requested */
839 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
840 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
841 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
842 autoc |= IXGBE_AUTOC_KX4_SUPP;
843 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
844 (hw->phy.smart_speed_active == false))
845 autoc |= IXGBE_AUTOC_KR_SUPP;
846 }
847 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
848 autoc |= IXGBE_AUTOC_KX_SUPP;
849 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
850 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
851 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
852 /* Switch from 1G SFI to 10G SFI if requested */
853 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
854 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
855 autoc &= ~IXGBE_AUTOC_LMS_MASK;
856 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
857 }
858 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
859 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
860 /* Switch from 10G SFI to 1G SFI if requested */
861 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
862 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
863 autoc &= ~IXGBE_AUTOC_LMS_MASK;
864 if (autoneg)
865 autoc |= IXGBE_AUTOC_LMS_1G_AN;
866 else
867 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
868 }
869 }
870
871 if (autoc != current_autoc) {
872 /* Restart link */
873 status = hw->mac.ops.prot_autoc_write(hw, autoc, false);
874 if (status)
875 return status;
876
877 /* Only poll for autoneg to complete if specified to do so */
878 if (autoneg_wait_to_complete) {
879 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
880 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
881 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
882 links_reg = 0; /*Just in case Autoneg time=0*/
883 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
884 links_reg =
885 IXGBE_READ_REG(hw, IXGBE_LINKS);
886 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
887 break;
888 msleep(100);
889 }
890 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
891 status =
892 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
893 hw_dbg(hw, "Autoneg did not complete.\n");
894 }
895 }
896 }
897
898 /* Add delay to filter out noises during initial link setup */
899 msleep(50);
900 }
901
902 return status;
903 }
904
905 /**
906 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
907 * @hw: pointer to hardware structure
908 * @speed: new link speed
909 * @autoneg_wait_to_complete: true if waiting is needed to complete
910 *
911 * Restarts link on PHY and MAC based on settings passed in.
912 **/
913 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
914 ixgbe_link_speed speed,
915 bool autoneg_wait_to_complete)
916 {
917 s32 status;
918
919 /* Setup the PHY according to input speed */
920 status = hw->phy.ops.setup_link_speed(hw, speed,
921 autoneg_wait_to_complete);
922 /* Set up MAC */
923 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
924
925 return status;
926 }
927
928 /**
929 * ixgbe_reset_hw_82599 - Perform hardware reset
930 * @hw: pointer to hardware structure
931 *
932 * Resets the hardware by resetting the transmit and receive units, masks
933 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
934 * reset.
935 **/
936 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
937 {
938 ixgbe_link_speed link_speed;
939 s32 status;
940 u32 ctrl, i, autoc, autoc2;
941 u32 curr_lms;
942 bool link_up = false;
943
944 /* Call adapter stop to disable tx/rx and clear interrupts */
945 status = hw->mac.ops.stop_adapter(hw);
946 if (status)
947 return status;
948
949 /* flush pending Tx transactions */
950 ixgbe_clear_tx_pending(hw);
951
952 /* PHY ops must be identified and initialized prior to reset */
953
954 /* Identify PHY and related function pointers */
955 status = hw->phy.ops.init(hw);
956
957 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
958 return status;
959
960 /* Setup SFP module if there is one present. */
961 if (hw->phy.sfp_setup_needed) {
962 status = hw->mac.ops.setup_sfp(hw);
963 hw->phy.sfp_setup_needed = false;
964 }
965
966 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
967 return status;
968
969 /* Reset PHY */
970 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
971 hw->phy.ops.reset(hw);
972
973 /* remember AUTOC from before we reset */
974 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
975
976 mac_reset_top:
977 /*
978 * Issue global reset to the MAC. Needs to be SW reset if link is up.
979 * If link reset is used when link is up, it might reset the PHY when
980 * mng is using it. If link is down or the flag to force full link
981 * reset is set, then perform link reset.
982 */
983 ctrl = IXGBE_CTRL_LNK_RST;
984 if (!hw->force_full_reset) {
985 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
986 if (link_up)
987 ctrl = IXGBE_CTRL_RST;
988 }
989
990 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
991 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
992 IXGBE_WRITE_FLUSH(hw);
993 usleep_range(1000, 1200);
994
995 /* Poll for reset bit to self-clear indicating reset is complete */
996 for (i = 0; i < 10; i++) {
997 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
998 if (!(ctrl & IXGBE_CTRL_RST_MASK))
999 break;
1000 udelay(1);
1001 }
1002
1003 if (ctrl & IXGBE_CTRL_RST_MASK) {
1004 status = IXGBE_ERR_RESET_FAILED;
1005 hw_dbg(hw, "Reset polling failed to complete.\n");
1006 }
1007
1008 msleep(50);
1009
1010 /*
1011 * Double resets are required for recovery from certain error
1012 * conditions. Between resets, it is necessary to stall to allow time
1013 * for any pending HW events to complete.
1014 */
1015 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1016 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1017 goto mac_reset_top;
1018 }
1019
1020 /*
1021 * Store the original AUTOC/AUTOC2 values if they have not been
1022 * stored off yet. Otherwise restore the stored original
1023 * values since the reset operation sets back to defaults.
1024 */
1025 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1026 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1027
1028 /* Enable link if disabled in NVM */
1029 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1030 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1031 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1032 IXGBE_WRITE_FLUSH(hw);
1033 }
1034
1035 if (hw->mac.orig_link_settings_stored == false) {
1036 hw->mac.orig_autoc = autoc;
1037 hw->mac.orig_autoc2 = autoc2;
1038 hw->mac.orig_link_settings_stored = true;
1039 } else {
1040
1041 /* If MNG FW is running on a multi-speed device that
1042 * doesn't autoneg with out driver support we need to
1043 * leave LMS in the state it was before we MAC reset.
1044 * Likewise if we support WoL we don't want change the
1045 * LMS state either.
1046 */
1047 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
1048 hw->wol_enabled)
1049 hw->mac.orig_autoc =
1050 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1051 curr_lms;
1052
1053 if (autoc != hw->mac.orig_autoc) {
1054 status = hw->mac.ops.prot_autoc_write(hw,
1055 hw->mac.orig_autoc,
1056 false);
1057 if (status)
1058 return status;
1059 }
1060
1061 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1062 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1063 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1064 autoc2 |= (hw->mac.orig_autoc2 &
1065 IXGBE_AUTOC2_UPPER_MASK);
1066 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1067 }
1068 }
1069
1070 /* Store the permanent mac address */
1071 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1072
1073 /*
1074 * Store MAC address from RAR0, clear receive address registers, and
1075 * clear the multicast table. Also reset num_rar_entries to 128,
1076 * since we modify this value when programming the SAN MAC address.
1077 */
1078 hw->mac.num_rar_entries = 128;
1079 hw->mac.ops.init_rx_addrs(hw);
1080
1081 /* Store the permanent SAN mac address */
1082 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1083
1084 /* Add the SAN MAC address to the RAR only if it's a valid address */
1085 if (is_valid_ether_addr(hw->mac.san_addr)) {
1086 /* Save the SAN MAC RAR index */
1087 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1088
1089 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
1090 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1091
1092 /* clear VMDq pool/queue selection for this RAR */
1093 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
1094 IXGBE_CLEAR_VMDQ_ALL);
1095
1096 /* Reserve the last RAR for the SAN MAC address */
1097 hw->mac.num_rar_entries--;
1098 }
1099
1100 /* Store the alternative WWNN/WWPN prefix */
1101 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1102 &hw->mac.wwpn_prefix);
1103
1104 return status;
1105 }
1106
1107 /**
1108 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
1109 * @hw: pointer to hardware structure
1110 * @fdircmd: current value of FDIRCMD register
1111 */
1112 static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)
1113 {
1114 int i;
1115
1116 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1117 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1118 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1119 return 0;
1120 udelay(10);
1121 }
1122
1123 return IXGBE_ERR_FDIR_CMD_INCOMPLETE;
1124 }
1125
1126 /**
1127 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1128 * @hw: pointer to hardware structure
1129 **/
1130 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1131 {
1132 int i;
1133 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1134 u32 fdircmd;
1135 s32 err;
1136
1137 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1138
1139 /*
1140 * Before starting reinitialization process,
1141 * FDIRCMD.CMD must be zero.
1142 */
1143 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1144 if (err) {
1145 hw_dbg(hw, "Flow Director previous command did not complete, aborting table re-initialization.\n");
1146 return err;
1147 }
1148
1149 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1150 IXGBE_WRITE_FLUSH(hw);
1151 /*
1152 * 82599 adapters flow director init flow cannot be restarted,
1153 * Workaround 82599 silicon errata by performing the following steps
1154 * before re-writing the FDIRCTRL control register with the same value.
1155 * - write 1 to bit 8 of FDIRCMD register &
1156 * - write 0 to bit 8 of FDIRCMD register
1157 */
1158 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1159 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1160 IXGBE_FDIRCMD_CLEARHT));
1161 IXGBE_WRITE_FLUSH(hw);
1162 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1163 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1164 ~IXGBE_FDIRCMD_CLEARHT));
1165 IXGBE_WRITE_FLUSH(hw);
1166 /*
1167 * Clear FDIR Hash register to clear any leftover hashes
1168 * waiting to be programmed.
1169 */
1170 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1171 IXGBE_WRITE_FLUSH(hw);
1172
1173 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1174 IXGBE_WRITE_FLUSH(hw);
1175
1176 /* Poll init-done after we write FDIRCTRL register */
1177 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1178 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1179 IXGBE_FDIRCTRL_INIT_DONE)
1180 break;
1181 usleep_range(1000, 2000);
1182 }
1183 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1184 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1185 return IXGBE_ERR_FDIR_REINIT_FAILED;
1186 }
1187
1188 /* Clear FDIR statistics registers (read to clear) */
1189 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1190 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1191 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1192 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1193 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1194
1195 return 0;
1196 }
1197
1198 /**
1199 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1200 * @hw: pointer to hardware structure
1201 * @fdirctrl: value to write to flow director control register
1202 **/
1203 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1204 {
1205 int i;
1206
1207 /* Prime the keys for hashing */
1208 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1209 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1210
1211 /*
1212 * Poll init-done after we write the register. Estimated times:
1213 * 10G: PBALLOC = 11b, timing is 60us
1214 * 1G: PBALLOC = 11b, timing is 600us
1215 * 100M: PBALLOC = 11b, timing is 6ms
1216 *
1217 * Multiple these timings by 4 if under full Rx load
1218 *
1219 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1220 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1221 * this might not finish in our poll time, but we can live with that
1222 * for now.
1223 */
1224 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1225 IXGBE_WRITE_FLUSH(hw);
1226 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1227 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1228 IXGBE_FDIRCTRL_INIT_DONE)
1229 break;
1230 usleep_range(1000, 2000);
1231 }
1232
1233 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1234 hw_dbg(hw, "Flow Director poll time exceeded!\n");
1235 }
1236
1237 /**
1238 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1239 * @hw: pointer to hardware structure
1240 * @fdirctrl: value to write to flow director control register, initially
1241 * contains just the value of the Rx packet buffer allocation
1242 **/
1243 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1244 {
1245 /*
1246 * Continue setup of fdirctrl register bits:
1247 * Move the flexible bytes to use the ethertype - shift 6 words
1248 * Set the maximum length per hash bucket to 0xA filters
1249 * Send interrupt when 64 filters are left
1250 */
1251 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1252 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1253 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1254
1255 /* write hashes and fdirctrl register, poll for completion */
1256 ixgbe_fdir_enable_82599(hw, fdirctrl);
1257
1258 return 0;
1259 }
1260
1261 /**
1262 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1263 * @hw: pointer to hardware structure
1264 * @fdirctrl: value to write to flow director control register, initially
1265 * contains just the value of the Rx packet buffer allocation
1266 **/
1267 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1268 {
1269 /*
1270 * Continue setup of fdirctrl register bits:
1271 * Turn perfect match filtering on
1272 * Initialize the drop queue
1273 * Move the flexible bytes to use the ethertype - shift 6 words
1274 * Set the maximum length per hash bucket to 0xA filters
1275 * Send interrupt when 64 (0x4 * 16) filters are left
1276 */
1277 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1278 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1279 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1280 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1281 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1282
1283 /* write hashes and fdirctrl register, poll for completion */
1284 ixgbe_fdir_enable_82599(hw, fdirctrl);
1285
1286 return 0;
1287 }
1288
1289 /*
1290 * These defines allow us to quickly generate all of the necessary instructions
1291 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1292 * for values 0 through 15
1293 */
1294 #define IXGBE_ATR_COMMON_HASH_KEY \
1295 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1296 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1297 do { \
1298 u32 n = (_n); \
1299 if (IXGBE_ATR_COMMON_HASH_KEY & BIT(n)) \
1300 common_hash ^= lo_hash_dword >> n; \
1301 else if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n)) \
1302 bucket_hash ^= lo_hash_dword >> n; \
1303 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & BIT(n)) \
1304 sig_hash ^= lo_hash_dword << (16 - n); \
1305 if (IXGBE_ATR_COMMON_HASH_KEY & BIT(n + 16)) \
1306 common_hash ^= hi_hash_dword >> n; \
1307 else if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n + 16)) \
1308 bucket_hash ^= hi_hash_dword >> n; \
1309 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & BIT(n + 16)) \
1310 sig_hash ^= hi_hash_dword << (16 - n); \
1311 } while (0)
1312
1313 /**
1314 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1315 * @stream: input bitstream to compute the hash on
1316 *
1317 * This function is almost identical to the function above but contains
1318 * several optomizations such as unwinding all of the loops, letting the
1319 * compiler work out all of the conditional ifs since the keys are static
1320 * defines, and computing two keys at once since the hashed dword stream
1321 * will be the same for both keys.
1322 **/
1323 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1324 union ixgbe_atr_hash_dword common)
1325 {
1326 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1327 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1328
1329 /* record the flow_vm_vlan bits as they are a key part to the hash */
1330 flow_vm_vlan = ntohl(input.dword);
1331
1332 /* generate common hash dword */
1333 hi_hash_dword = ntohl(common.dword);
1334
1335 /* low dword is word swapped version of common */
1336 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1337
1338 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1339 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1340
1341 /* Process bits 0 and 16 */
1342 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1343
1344 /*
1345 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1346 * delay this because bit 0 of the stream should not be processed
1347 * so we do not add the vlan until after bit 0 was processed
1348 */
1349 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1350
1351 /* Process remaining 30 bit of the key */
1352 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1353 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1354 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1355 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1356 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1357 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1358 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1359 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1360 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1361 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1362 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1363 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1364 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1365 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1366 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1367
1368 /* combine common_hash result with signature and bucket hashes */
1369 bucket_hash ^= common_hash;
1370 bucket_hash &= IXGBE_ATR_HASH_MASK;
1371
1372 sig_hash ^= common_hash << 16;
1373 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1374
1375 /* return completed signature hash */
1376 return sig_hash ^ bucket_hash;
1377 }
1378
1379 /**
1380 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1381 * @hw: pointer to hardware structure
1382 * @input: unique input dword
1383 * @common: compressed common input dword
1384 * @queue: queue index to direct traffic to
1385 *
1386 * Note that the tunnel bit in input must not be set when the hardware
1387 * tunneling support does not exist.
1388 **/
1389 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1390 union ixgbe_atr_hash_dword input,
1391 union ixgbe_atr_hash_dword common,
1392 u8 queue)
1393 {
1394 u64 fdirhashcmd;
1395 u8 flow_type;
1396 bool tunnel;
1397 u32 fdircmd;
1398
1399 /*
1400 * Get the flow_type in order to program FDIRCMD properly
1401 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1402 */
1403 tunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK);
1404 flow_type = input.formatted.flow_type &
1405 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1);
1406 switch (flow_type) {
1407 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1408 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1409 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1410 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1411 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1412 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1413 break;
1414 default:
1415 hw_dbg(hw, " Error on flow type input\n");
1416 return IXGBE_ERR_CONFIG;
1417 }
1418
1419 /* configure FDIRCMD register */
1420 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1421 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1422 fdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1423 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1424 if (tunnel)
1425 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
1426
1427 /*
1428 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1429 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1430 */
1431 fdirhashcmd = (u64)fdircmd << 32;
1432 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1433 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1434
1435 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1436
1437 return 0;
1438 }
1439
1440 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1441 do { \
1442 u32 n = (_n); \
1443 if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n)) \
1444 bucket_hash ^= lo_hash_dword >> n; \
1445 if (IXGBE_ATR_BUCKET_HASH_KEY & BIT(n + 16)) \
1446 bucket_hash ^= hi_hash_dword >> n; \
1447 } while (0)
1448
1449 /**
1450 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1451 * @atr_input: input bitstream to compute the hash on
1452 * @input_mask: mask for the input bitstream
1453 *
1454 * This function serves two main purposes. First it applys the input_mask
1455 * to the atr_input resulting in a cleaned up atr_input data stream.
1456 * Secondly it computes the hash and stores it in the bkt_hash field at
1457 * the end of the input byte stream. This way it will be available for
1458 * future use without needing to recompute the hash.
1459 **/
1460 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1461 union ixgbe_atr_input *input_mask)
1462 {
1463
1464 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1465 u32 bucket_hash = 0, hi_dword = 0;
1466 int i;
1467
1468 /* Apply masks to input data */
1469 for (i = 0; i <= 10; i++)
1470 input->dword_stream[i] &= input_mask->dword_stream[i];
1471
1472 /* record the flow_vm_vlan bits as they are a key part to the hash */
1473 flow_vm_vlan = ntohl(input->dword_stream[0]);
1474
1475 /* generate common hash dword */
1476 for (i = 1; i <= 10; i++)
1477 hi_dword ^= input->dword_stream[i];
1478 hi_hash_dword = ntohl(hi_dword);
1479
1480 /* low dword is word swapped version of common */
1481 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1482
1483 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1484 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1485
1486 /* Process bits 0 and 16 */
1487 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1488
1489 /*
1490 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1491 * delay this because bit 0 of the stream should not be processed
1492 * so we do not add the vlan until after bit 0 was processed
1493 */
1494 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1495
1496 /* Process remaining 30 bit of the key */
1497 for (i = 1; i <= 15; i++)
1498 IXGBE_COMPUTE_BKT_HASH_ITERATION(i);
1499
1500 /*
1501 * Limit hash to 13 bits since max bucket count is 8K.
1502 * Store result at the end of the input stream.
1503 */
1504 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1505 }
1506
1507 /**
1508 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1509 * @input_mask: mask to be bit swapped
1510 *
1511 * The source and destination port masks for flow director are bit swapped
1512 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1513 * generate a correctly swapped value we need to bit swap the mask and that
1514 * is what is accomplished by this function.
1515 **/
1516 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1517 {
1518 u32 mask = ntohs(input_mask->formatted.dst_port);
1519
1520 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1521 mask |= ntohs(input_mask->formatted.src_port);
1522 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1523 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1524 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1525 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1526 }
1527
1528 /*
1529 * These two macros are meant to address the fact that we have registers
1530 * that are either all or in part big-endian. As a result on big-endian
1531 * systems we will end up byte swapping the value to little-endian before
1532 * it is byte swapped again and written to the hardware in the original
1533 * big-endian format.
1534 */
1535 #define IXGBE_STORE_AS_BE32(_value) \
1536 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1537 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1538
1539 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1540 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1541
1542 #define IXGBE_STORE_AS_BE16(_value) \
1543 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1544
1545 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1546 union ixgbe_atr_input *input_mask)
1547 {
1548 /* mask IPv6 since it is currently not supported */
1549 u32 fdirm = IXGBE_FDIRM_DIPv6;
1550 u32 fdirtcpm;
1551
1552 /*
1553 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1554 * are zero, then assume a full mask for that field. Also assume that
1555 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1556 * cannot be masked out in this implementation.
1557 *
1558 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1559 * point in time.
1560 */
1561
1562 /* verify bucket hash is cleared on hash generation */
1563 if (input_mask->formatted.bkt_hash)
1564 hw_dbg(hw, " bucket hash should always be 0 in mask\n");
1565
1566 /* Program FDIRM and verify partial masks */
1567 switch (input_mask->formatted.vm_pool & 0x7F) {
1568 case 0x0:
1569 fdirm |= IXGBE_FDIRM_POOL;
1570 case 0x7F:
1571 break;
1572 default:
1573 hw_dbg(hw, " Error on vm pool mask\n");
1574 return IXGBE_ERR_CONFIG;
1575 }
1576
1577 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1578 case 0x0:
1579 fdirm |= IXGBE_FDIRM_L4P;
1580 if (input_mask->formatted.dst_port ||
1581 input_mask->formatted.src_port) {
1582 hw_dbg(hw, " Error on src/dst port mask\n");
1583 return IXGBE_ERR_CONFIG;
1584 }
1585 case IXGBE_ATR_L4TYPE_MASK:
1586 break;
1587 default:
1588 hw_dbg(hw, " Error on flow type mask\n");
1589 return IXGBE_ERR_CONFIG;
1590 }
1591
1592 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) {
1593 case 0x0000:
1594 /* mask VLAN ID, fall through to mask VLAN priority */
1595 fdirm |= IXGBE_FDIRM_VLANID;
1596 case 0x0FFF:
1597 /* mask VLAN priority */
1598 fdirm |= IXGBE_FDIRM_VLANP;
1599 break;
1600 case 0xE000:
1601 /* mask VLAN ID only, fall through */
1602 fdirm |= IXGBE_FDIRM_VLANID;
1603 case 0xEFFF:
1604 /* no VLAN fields masked */
1605 break;
1606 default:
1607 hw_dbg(hw, " Error on VLAN mask\n");
1608 return IXGBE_ERR_CONFIG;
1609 }
1610
1611 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1612 case 0x0000:
1613 /* Mask Flex Bytes, fall through */
1614 fdirm |= IXGBE_FDIRM_FLEX;
1615 case 0xFFFF:
1616 break;
1617 default:
1618 hw_dbg(hw, " Error on flexible byte mask\n");
1619 return IXGBE_ERR_CONFIG;
1620 }
1621
1622 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1623 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1624
1625 /* store the TCP/UDP port masks, bit reversed from port layout */
1626 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1627
1628 /* write both the same so that UDP and TCP use the same mask */
1629 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1630 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1631
1632 /* also use it for SCTP */
1633 switch (hw->mac.type) {
1634 case ixgbe_mac_X550:
1635 case ixgbe_mac_X550EM_x:
1636 case ixgbe_mac_x550em_a:
1637 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
1638 break;
1639 default:
1640 break;
1641 }
1642
1643 /* store source and destination IP masks (big-enian) */
1644 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1645 ~input_mask->formatted.src_ip[0]);
1646 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1647 ~input_mask->formatted.dst_ip[0]);
1648
1649 return 0;
1650 }
1651
1652 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1653 union ixgbe_atr_input *input,
1654 u16 soft_id, u8 queue)
1655 {
1656 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1657 s32 err;
1658
1659 /* currently IPv6 is not supported, must be programmed with 0 */
1660 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1661 input->formatted.src_ip[0]);
1662 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1663 input->formatted.src_ip[1]);
1664 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1665 input->formatted.src_ip[2]);
1666
1667 /* record the source address (big-endian) */
1668 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1669
1670 /* record the first 32 bits of the destination address (big-endian) */
1671 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1672
1673 /* record source and destination port (little-endian)*/
1674 fdirport = ntohs(input->formatted.dst_port);
1675 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1676 fdirport |= ntohs(input->formatted.src_port);
1677 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1678
1679 /* record vlan (little-endian) and flex_bytes(big-endian) */
1680 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1681 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1682 fdirvlan |= ntohs(input->formatted.vlan_id);
1683 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1684
1685 /* configure FDIRHASH register */
1686 fdirhash = input->formatted.bkt_hash;
1687 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1688 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1689
1690 /*
1691 * flush all previous writes to make certain registers are
1692 * programmed prior to issuing the command
1693 */
1694 IXGBE_WRITE_FLUSH(hw);
1695
1696 /* configure FDIRCMD register */
1697 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1698 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1699 if (queue == IXGBE_FDIR_DROP_QUEUE)
1700 fdircmd |= IXGBE_FDIRCMD_DROP;
1701 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1702 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1703 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1704
1705 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1706 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1707 if (err) {
1708 hw_dbg(hw, "Flow Director command did not complete!\n");
1709 return err;
1710 }
1711
1712 return 0;
1713 }
1714
1715 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1716 union ixgbe_atr_input *input,
1717 u16 soft_id)
1718 {
1719 u32 fdirhash;
1720 u32 fdircmd;
1721 s32 err;
1722
1723 /* configure FDIRHASH register */
1724 fdirhash = input->formatted.bkt_hash;
1725 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1726 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1727
1728 /* flush hash to HW */
1729 IXGBE_WRITE_FLUSH(hw);
1730
1731 /* Query if filter is present */
1732 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1733
1734 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1735 if (err) {
1736 hw_dbg(hw, "Flow Director command did not complete!\n");
1737 return err;
1738 }
1739
1740 /* if filter exists in hardware then remove it */
1741 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1742 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1743 IXGBE_WRITE_FLUSH(hw);
1744 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1745 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1746 }
1747
1748 return 0;
1749 }
1750
1751 /**
1752 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1753 * @hw: pointer to hardware structure
1754 * @reg: analog register to read
1755 * @val: read value
1756 *
1757 * Performs read operation to Omer analog register specified.
1758 **/
1759 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1760 {
1761 u32 core_ctl;
1762
1763 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1764 (reg << 8));
1765 IXGBE_WRITE_FLUSH(hw);
1766 udelay(10);
1767 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1768 *val = (u8)core_ctl;
1769
1770 return 0;
1771 }
1772
1773 /**
1774 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1775 * @hw: pointer to hardware structure
1776 * @reg: atlas register to write
1777 * @val: value to write
1778 *
1779 * Performs write operation to Omer analog register specified.
1780 **/
1781 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1782 {
1783 u32 core_ctl;
1784
1785 core_ctl = (reg << 8) | val;
1786 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1787 IXGBE_WRITE_FLUSH(hw);
1788 udelay(10);
1789
1790 return 0;
1791 }
1792
1793 /**
1794 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1795 * @hw: pointer to hardware structure
1796 *
1797 * Starts the hardware using the generic start_hw function
1798 * and the generation start_hw function.
1799 * Then performs revision-specific operations, if any.
1800 **/
1801 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1802 {
1803 s32 ret_val = 0;
1804
1805 ret_val = ixgbe_start_hw_generic(hw);
1806 if (ret_val)
1807 return ret_val;
1808
1809 ret_val = ixgbe_start_hw_gen2(hw);
1810 if (ret_val)
1811 return ret_val;
1812
1813 /* We need to run link autotry after the driver loads */
1814 hw->mac.autotry_restart = true;
1815
1816 if (ret_val)
1817 return ret_val;
1818
1819 return ixgbe_verify_fw_version_82599(hw);
1820 }
1821
1822 /**
1823 * ixgbe_identify_phy_82599 - Get physical layer module
1824 * @hw: pointer to hardware structure
1825 *
1826 * Determines the physical layer module found on the current adapter.
1827 * If PHY already detected, maintains current PHY type in hw struct,
1828 * otherwise executes the PHY detection routine.
1829 **/
1830 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1831 {
1832 s32 status;
1833
1834 /* Detect PHY if not unknown - returns success if already detected. */
1835 status = ixgbe_identify_phy_generic(hw);
1836 if (status) {
1837 /* 82599 10GBASE-T requires an external PHY */
1838 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1839 return status;
1840 status = ixgbe_identify_module_generic(hw);
1841 }
1842
1843 /* Set PHY type none if no PHY detected */
1844 if (hw->phy.type == ixgbe_phy_unknown) {
1845 hw->phy.type = ixgbe_phy_none;
1846 status = 0;
1847 }
1848
1849 /* Return error if SFP module has been detected but is not supported */
1850 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1851 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1852
1853 return status;
1854 }
1855
1856 /**
1857 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1858 * @hw: pointer to hardware structure
1859 * @regval: register value to write to RXCTRL
1860 *
1861 * Enables the Rx DMA unit for 82599
1862 **/
1863 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1864 {
1865 /*
1866 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1867 * If traffic is incoming before we enable the Rx unit, it could hang
1868 * the Rx DMA unit. Therefore, make sure the security engine is
1869 * completely disabled prior to enabling the Rx unit.
1870 */
1871 hw->mac.ops.disable_rx_buff(hw);
1872
1873 if (regval & IXGBE_RXCTRL_RXEN)
1874 hw->mac.ops.enable_rx(hw);
1875 else
1876 hw->mac.ops.disable_rx(hw);
1877
1878 hw->mac.ops.enable_rx_buff(hw);
1879
1880 return 0;
1881 }
1882
1883 /**
1884 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1885 * @hw: pointer to hardware structure
1886 *
1887 * Verifies that installed the firmware version is 0.6 or higher
1888 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
1889 *
1890 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
1891 * if the FW version is not supported.
1892 **/
1893 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
1894 {
1895 s32 status = IXGBE_ERR_EEPROM_VERSION;
1896 u16 fw_offset, fw_ptp_cfg_offset;
1897 u16 offset;
1898 u16 fw_version = 0;
1899
1900 /* firmware check is only necessary for SFI devices */
1901 if (hw->phy.media_type != ixgbe_media_type_fiber)
1902 return 0;
1903
1904 /* get the offset to the Firmware Module block */
1905 offset = IXGBE_FW_PTR;
1906 if (hw->eeprom.ops.read(hw, offset, &fw_offset))
1907 goto fw_version_err;
1908
1909 if (fw_offset == 0 || fw_offset == 0xFFFF)
1910 return IXGBE_ERR_EEPROM_VERSION;
1911
1912 /* get the offset to the Pass Through Patch Configuration block */
1913 offset = fw_offset + IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR;
1914 if (hw->eeprom.ops.read(hw, offset, &fw_ptp_cfg_offset))
1915 goto fw_version_err;
1916
1917 if (fw_ptp_cfg_offset == 0 || fw_ptp_cfg_offset == 0xFFFF)
1918 return IXGBE_ERR_EEPROM_VERSION;
1919
1920 /* get the firmware version */
1921 offset = fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4;
1922 if (hw->eeprom.ops.read(hw, offset, &fw_version))
1923 goto fw_version_err;
1924
1925 if (fw_version > 0x5)
1926 status = 0;
1927
1928 return status;
1929
1930 fw_version_err:
1931 hw_err(hw, "eeprom read at offset %d failed\n", offset);
1932 return IXGBE_ERR_EEPROM_VERSION;
1933 }
1934
1935 /**
1936 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
1937 * @hw: pointer to hardware structure
1938 *
1939 * Returns true if the LESM FW module is present and enabled. Otherwise
1940 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
1941 **/
1942 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
1943 {
1944 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
1945 s32 status;
1946
1947 /* get the offset to the Firmware Module block */
1948 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
1949
1950 if (status || fw_offset == 0 || fw_offset == 0xFFFF)
1951 return false;
1952
1953 /* get the offset to the LESM Parameters block */
1954 status = hw->eeprom.ops.read(hw, (fw_offset +
1955 IXGBE_FW_LESM_PARAMETERS_PTR),
1956 &fw_lesm_param_offset);
1957
1958 if (status ||
1959 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF)
1960 return false;
1961
1962 /* get the lesm state word */
1963 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
1964 IXGBE_FW_LESM_STATE_1),
1965 &fw_lesm_state);
1966
1967 if (!status && (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
1968 return true;
1969
1970 return false;
1971 }
1972
1973 /**
1974 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
1975 * fastest available method
1976 *
1977 * @hw: pointer to hardware structure
1978 * @offset: offset of word in EEPROM to read
1979 * @words: number of words
1980 * @data: word(s) read from the EEPROM
1981 *
1982 * Retrieves 16 bit word(s) read from EEPROM
1983 **/
1984 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
1985 u16 words, u16 *data)
1986 {
1987 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1988
1989 /* If EEPROM is detected and can be addressed using 14 bits,
1990 * use EERD otherwise use bit bang
1991 */
1992 if (eeprom->type == ixgbe_eeprom_spi &&
1993 offset + (words - 1) <= IXGBE_EERD_MAX_ADDR)
1994 return ixgbe_read_eerd_buffer_generic(hw, offset, words, data);
1995
1996 return ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, words,
1997 data);
1998 }
1999
2000 /**
2001 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2002 * fastest available method
2003 *
2004 * @hw: pointer to hardware structure
2005 * @offset: offset of word in the EEPROM to read
2006 * @data: word read from the EEPROM
2007 *
2008 * Reads a 16 bit word from the EEPROM
2009 **/
2010 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2011 u16 offset, u16 *data)
2012 {
2013 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2014
2015 /*
2016 * If EEPROM is detected and can be addressed using 14 bits,
2017 * use EERD otherwise use bit bang
2018 */
2019 if (eeprom->type == ixgbe_eeprom_spi && offset <= IXGBE_EERD_MAX_ADDR)
2020 return ixgbe_read_eerd_generic(hw, offset, data);
2021
2022 return ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2023 }
2024
2025 /**
2026 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2027 *
2028 * @hw: pointer to hardware structure
2029 *
2030 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2031 * full pipeline reset. Note - We must hold the SW/FW semaphore before writing
2032 * to AUTOC, so this function assumes the semaphore is held.
2033 **/
2034 static s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2035 {
2036 s32 ret_val;
2037 u32 anlp1_reg = 0;
2038 u32 i, autoc_reg, autoc2_reg;
2039
2040 /* Enable link if disabled in NVM */
2041 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2042 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2043 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2044 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2045 IXGBE_WRITE_FLUSH(hw);
2046 }
2047
2048 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2049 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2050
2051 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2052 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
2053 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT));
2054
2055 /* Wait for AN to leave state 0 */
2056 for (i = 0; i < 10; i++) {
2057 usleep_range(4000, 8000);
2058 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2059 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2060 break;
2061 }
2062
2063 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2064 hw_dbg(hw, "auto negotiation not completed\n");
2065 ret_val = IXGBE_ERR_RESET_FAILED;
2066 goto reset_pipeline_out;
2067 }
2068
2069 ret_val = 0;
2070
2071 reset_pipeline_out:
2072 /* Write AUTOC register with original LMS field and Restart_AN */
2073 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2074 IXGBE_WRITE_FLUSH(hw);
2075
2076 return ret_val;
2077 }
2078
2079 /**
2080 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2081 * @hw: pointer to hardware structure
2082 * @byte_offset: byte offset to read
2083 * @data: value read
2084 *
2085 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2086 * a specified device address.
2087 **/
2088 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2089 u8 dev_addr, u8 *data)
2090 {
2091 u32 esdp;
2092 s32 status;
2093 s32 timeout = 200;
2094
2095 if (hw->phy.qsfp_shared_i2c_bus == true) {
2096 /* Acquire I2C bus ownership. */
2097 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2098 esdp |= IXGBE_ESDP_SDP0;
2099 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2100 IXGBE_WRITE_FLUSH(hw);
2101
2102 while (timeout) {
2103 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2104 if (esdp & IXGBE_ESDP_SDP1)
2105 break;
2106
2107 usleep_range(5000, 10000);
2108 timeout--;
2109 }
2110
2111 if (!timeout) {
2112 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n");
2113 status = IXGBE_ERR_I2C;
2114 goto release_i2c_access;
2115 }
2116 }
2117
2118 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2119
2120 release_i2c_access:
2121 if (hw->phy.qsfp_shared_i2c_bus == true) {
2122 /* Release I2C bus ownership. */
2123 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2124 esdp &= ~IXGBE_ESDP_SDP0;
2125 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2126 IXGBE_WRITE_FLUSH(hw);
2127 }
2128
2129 return status;
2130 }
2131
2132 /**
2133 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2134 * @hw: pointer to hardware structure
2135 * @byte_offset: byte offset to write
2136 * @data: value to write
2137 *
2138 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2139 * a specified device address.
2140 **/
2141 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2142 u8 dev_addr, u8 data)
2143 {
2144 u32 esdp;
2145 s32 status;
2146 s32 timeout = 200;
2147
2148 if (hw->phy.qsfp_shared_i2c_bus == true) {
2149 /* Acquire I2C bus ownership. */
2150 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2151 esdp |= IXGBE_ESDP_SDP0;
2152 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2153 IXGBE_WRITE_FLUSH(hw);
2154
2155 while (timeout) {
2156 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2157 if (esdp & IXGBE_ESDP_SDP1)
2158 break;
2159
2160 usleep_range(5000, 10000);
2161 timeout--;
2162 }
2163
2164 if (!timeout) {
2165 hw_dbg(hw, "Driver can't access resource, acquiring I2C bus timeout.\n");
2166 status = IXGBE_ERR_I2C;
2167 goto release_i2c_access;
2168 }
2169 }
2170
2171 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2172
2173 release_i2c_access:
2174 if (hw->phy.qsfp_shared_i2c_bus == true) {
2175 /* Release I2C bus ownership. */
2176 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2177 esdp &= ~IXGBE_ESDP_SDP0;
2178 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2179 IXGBE_WRITE_FLUSH(hw);
2180 }
2181
2182 return status;
2183 }
2184
2185 static const struct ixgbe_mac_operations mac_ops_82599 = {
2186 .init_hw = &ixgbe_init_hw_generic,
2187 .reset_hw = &ixgbe_reset_hw_82599,
2188 .start_hw = &ixgbe_start_hw_82599,
2189 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2190 .get_media_type = &ixgbe_get_media_type_82599,
2191 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2192 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
2193 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
2194 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2195 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2196 .get_device_caps = &ixgbe_get_device_caps_generic,
2197 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2198 .stop_adapter = &ixgbe_stop_adapter_generic,
2199 .get_bus_info = &ixgbe_get_bus_info_generic,
2200 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2201 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2202 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2203 .stop_link_on_d3 = &ixgbe_stop_mac_link_on_d3_82599,
2204 .setup_link = &ixgbe_setup_mac_link_82599,
2205 .set_rxpba = &ixgbe_set_rxpba_generic,
2206 .check_link = &ixgbe_check_mac_link_generic,
2207 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2208 .led_on = &ixgbe_led_on_generic,
2209 .led_off = &ixgbe_led_off_generic,
2210 .blink_led_start = &ixgbe_blink_led_start_generic,
2211 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2212 .set_rar = &ixgbe_set_rar_generic,
2213 .clear_rar = &ixgbe_clear_rar_generic,
2214 .set_vmdq = &ixgbe_set_vmdq_generic,
2215 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
2216 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2217 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2218 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2219 .enable_mc = &ixgbe_enable_mc_generic,
2220 .disable_mc = &ixgbe_disable_mc_generic,
2221 .clear_vfta = &ixgbe_clear_vfta_generic,
2222 .set_vfta = &ixgbe_set_vfta_generic,
2223 .fc_enable = &ixgbe_fc_enable_generic,
2224 .setup_fc = ixgbe_setup_fc_generic,
2225 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
2226 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2227 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2228 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2229 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2230 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2231 .release_swfw_sync = &ixgbe_release_swfw_sync,
2232 .init_swfw_sync = NULL,
2233 .get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic,
2234 .init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic,
2235 .prot_autoc_read = &prot_autoc_read_82599,
2236 .prot_autoc_write = &prot_autoc_write_82599,
2237 .enable_rx = &ixgbe_enable_rx_generic,
2238 .disable_rx = &ixgbe_disable_rx_generic,
2239 };
2240
2241 static const struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2242 .init_params = &ixgbe_init_eeprom_params_generic,
2243 .read = &ixgbe_read_eeprom_82599,
2244 .read_buffer = &ixgbe_read_eeprom_buffer_82599,
2245 .write = &ixgbe_write_eeprom_generic,
2246 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
2247 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2248 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2249 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2250 };
2251
2252 static const struct ixgbe_phy_operations phy_ops_82599 = {
2253 .identify = &ixgbe_identify_phy_82599,
2254 .identify_sfp = &ixgbe_identify_module_generic,
2255 .init = &ixgbe_init_phy_ops_82599,
2256 .reset = &ixgbe_reset_phy_generic,
2257 .read_reg = &ixgbe_read_phy_reg_generic,
2258 .write_reg = &ixgbe_write_phy_reg_generic,
2259 .setup_link = &ixgbe_setup_phy_link_generic,
2260 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2261 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2262 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2263 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
2264 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2265 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2266 .check_overtemp = &ixgbe_tn_check_overtemp,
2267 };
2268
2269 const struct ixgbe_info ixgbe_82599_info = {
2270 .mac = ixgbe_mac_82599EB,
2271 .get_invariants = &ixgbe_get_invariants_82599,
2272 .mac_ops = &mac_ops_82599,
2273 .eeprom_ops = &eeprom_ops_82599,
2274 .phy_ops = &phy_ops_82599,
2275 .mbx_ops = &mbx_ops_generic,
2276 .mvals = ixgbe_mvals_8259X,
2277 };
Linux kernel - Deliverables
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