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Merge remote-tracking branch 'iommu/next'
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_ethtool.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2016 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /* ethtool support for ixgbe */
30
31 #include <linux/interrupt.h>
32 #include <linux/types.h>
33 #include <linux/module.h>
34 #include <linux/slab.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/ethtool.h>
38 #include <linux/vmalloc.h>
39 #include <linux/highmem.h>
40 #include <linux/uaccess.h>
41
42 #include "ixgbe.h"
43 #include "ixgbe_phy.h"
44
45
46 #define IXGBE_ALL_RAR_ENTRIES 16
47
48 enum {NETDEV_STATS, IXGBE_STATS};
49
50 struct ixgbe_stats {
51 char stat_string[ETH_GSTRING_LEN];
52 int type;
53 int sizeof_stat;
54 int stat_offset;
55 };
56
57 #define IXGBE_STAT(m) IXGBE_STATS, \
58 sizeof(((struct ixgbe_adapter *)0)->m), \
59 offsetof(struct ixgbe_adapter, m)
60 #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
61 sizeof(((struct rtnl_link_stats64 *)0)->m), \
62 offsetof(struct rtnl_link_stats64, m)
63
64 static const struct ixgbe_stats ixgbe_gstrings_stats[] = {
65 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
66 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
67 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
68 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
69 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
70 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
71 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
72 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
73 {"lsc_int", IXGBE_STAT(lsc_int)},
74 {"tx_busy", IXGBE_STAT(tx_busy)},
75 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
76 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
77 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
78 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
79 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
80 {"multicast", IXGBE_NETDEV_STAT(multicast)},
81 {"broadcast", IXGBE_STAT(stats.bprc)},
82 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
83 {"collisions", IXGBE_NETDEV_STAT(collisions)},
84 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
85 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
86 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
87 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
88 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
89 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
90 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
91 {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
92 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
93 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
94 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
95 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
96 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
97 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
98 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
99 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
100 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
101 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
102 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
103 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
104 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
105 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
106 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
107 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
108 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
109 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
110 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
111 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
112 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
113 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
114 #ifdef IXGBE_FCOE
115 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
116 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
117 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
118 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
119 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)},
120 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)},
121 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
122 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
123 #endif /* IXGBE_FCOE */
124 };
125
126 /* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so
127 * we set the num_rx_queues to evaluate to num_tx_queues. This is
128 * used because we do not have a good way to get the max number of
129 * rx queues with CONFIG_RPS disabled.
130 */
131 #define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues
132
133 #define IXGBE_QUEUE_STATS_LEN ( \
134 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \
135 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
136 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
137 #define IXGBE_PB_STATS_LEN ( \
138 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
139 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
140 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
141 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
142 / sizeof(u64))
143 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
144 IXGBE_PB_STATS_LEN + \
145 IXGBE_QUEUE_STATS_LEN)
146
147 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
148 "Register test (offline)", "Eeprom test (offline)",
149 "Interrupt test (offline)", "Loopback test (offline)",
150 "Link test (on/offline)"
151 };
152 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
153
154 /* currently supported speeds for 10G */
155 #define ADVRTSD_MSK_10G (SUPPORTED_10000baseT_Full | \
156 SUPPORTED_10000baseKX4_Full | \
157 SUPPORTED_10000baseKR_Full)
158
159 #define ixgbe_isbackplane(type) ((type) == ixgbe_media_type_backplane)
160
161 static u32 ixgbe_get_supported_10gtypes(struct ixgbe_hw *hw)
162 {
163 if (!ixgbe_isbackplane(hw->phy.media_type))
164 return SUPPORTED_10000baseT_Full;
165
166 switch (hw->device_id) {
167 case IXGBE_DEV_ID_82598:
168 case IXGBE_DEV_ID_82599_KX4:
169 case IXGBE_DEV_ID_82599_KX4_MEZZ:
170 case IXGBE_DEV_ID_X550EM_X_KX4:
171 return SUPPORTED_10000baseKX4_Full;
172 case IXGBE_DEV_ID_82598_BX:
173 case IXGBE_DEV_ID_82599_KR:
174 case IXGBE_DEV_ID_X550EM_X_KR:
175 return SUPPORTED_10000baseKR_Full;
176 default:
177 return SUPPORTED_10000baseKX4_Full |
178 SUPPORTED_10000baseKR_Full;
179 }
180 }
181
182 static int ixgbe_get_settings(struct net_device *netdev,
183 struct ethtool_cmd *ecmd)
184 {
185 struct ixgbe_adapter *adapter = netdev_priv(netdev);
186 struct ixgbe_hw *hw = &adapter->hw;
187 ixgbe_link_speed supported_link;
188 bool autoneg = false;
189
190 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
191
192 /* set the supported link speeds */
193 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
194 ecmd->supported |= ixgbe_get_supported_10gtypes(hw);
195 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
196 ecmd->supported |= (ixgbe_isbackplane(hw->phy.media_type)) ?
197 SUPPORTED_1000baseKX_Full :
198 SUPPORTED_1000baseT_Full;
199 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
200 ecmd->supported |= ixgbe_isbackplane(hw->phy.media_type) ?
201 SUPPORTED_1000baseKX_Full :
202 SUPPORTED_1000baseT_Full;
203
204 /* default advertised speed if phy.autoneg_advertised isn't set */
205 ecmd->advertising = ecmd->supported;
206 /* set the advertised speeds */
207 if (hw->phy.autoneg_advertised) {
208 ecmd->advertising = 0;
209 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
210 ecmd->advertising |= ADVERTISED_100baseT_Full;
211 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
212 ecmd->advertising |= ecmd->supported & ADVRTSD_MSK_10G;
213 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) {
214 if (ecmd->supported & SUPPORTED_1000baseKX_Full)
215 ecmd->advertising |= ADVERTISED_1000baseKX_Full;
216 else
217 ecmd->advertising |= ADVERTISED_1000baseT_Full;
218 }
219 } else {
220 if (hw->phy.multispeed_fiber && !autoneg) {
221 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
222 ecmd->advertising = ADVERTISED_10000baseT_Full;
223 }
224 }
225
226 if (autoneg) {
227 ecmd->supported |= SUPPORTED_Autoneg;
228 ecmd->advertising |= ADVERTISED_Autoneg;
229 ecmd->autoneg = AUTONEG_ENABLE;
230 } else
231 ecmd->autoneg = AUTONEG_DISABLE;
232
233 ecmd->transceiver = XCVR_EXTERNAL;
234
235 /* Determine the remaining settings based on the PHY type. */
236 switch (adapter->hw.phy.type) {
237 case ixgbe_phy_tn:
238 case ixgbe_phy_aq:
239 case ixgbe_phy_x550em_ext_t:
240 case ixgbe_phy_cu_unknown:
241 ecmd->supported |= SUPPORTED_TP;
242 ecmd->advertising |= ADVERTISED_TP;
243 ecmd->port = PORT_TP;
244 break;
245 case ixgbe_phy_qt:
246 ecmd->supported |= SUPPORTED_FIBRE;
247 ecmd->advertising |= ADVERTISED_FIBRE;
248 ecmd->port = PORT_FIBRE;
249 break;
250 case ixgbe_phy_nl:
251 case ixgbe_phy_sfp_passive_tyco:
252 case ixgbe_phy_sfp_passive_unknown:
253 case ixgbe_phy_sfp_ftl:
254 case ixgbe_phy_sfp_avago:
255 case ixgbe_phy_sfp_intel:
256 case ixgbe_phy_sfp_unknown:
257 case ixgbe_phy_qsfp_passive_unknown:
258 case ixgbe_phy_qsfp_active_unknown:
259 case ixgbe_phy_qsfp_intel:
260 case ixgbe_phy_qsfp_unknown:
261 /* SFP+ devices, further checking needed */
262 switch (adapter->hw.phy.sfp_type) {
263 case ixgbe_sfp_type_da_cu:
264 case ixgbe_sfp_type_da_cu_core0:
265 case ixgbe_sfp_type_da_cu_core1:
266 ecmd->supported |= SUPPORTED_FIBRE;
267 ecmd->advertising |= ADVERTISED_FIBRE;
268 ecmd->port = PORT_DA;
269 break;
270 case ixgbe_sfp_type_sr:
271 case ixgbe_sfp_type_lr:
272 case ixgbe_sfp_type_srlr_core0:
273 case ixgbe_sfp_type_srlr_core1:
274 case ixgbe_sfp_type_1g_sx_core0:
275 case ixgbe_sfp_type_1g_sx_core1:
276 case ixgbe_sfp_type_1g_lx_core0:
277 case ixgbe_sfp_type_1g_lx_core1:
278 ecmd->supported |= SUPPORTED_FIBRE;
279 ecmd->advertising |= ADVERTISED_FIBRE;
280 ecmd->port = PORT_FIBRE;
281 break;
282 case ixgbe_sfp_type_not_present:
283 ecmd->supported |= SUPPORTED_FIBRE;
284 ecmd->advertising |= ADVERTISED_FIBRE;
285 ecmd->port = PORT_NONE;
286 break;
287 case ixgbe_sfp_type_1g_cu_core0:
288 case ixgbe_sfp_type_1g_cu_core1:
289 ecmd->supported |= SUPPORTED_TP;
290 ecmd->advertising |= ADVERTISED_TP;
291 ecmd->port = PORT_TP;
292 break;
293 case ixgbe_sfp_type_unknown:
294 default:
295 ecmd->supported |= SUPPORTED_FIBRE;
296 ecmd->advertising |= ADVERTISED_FIBRE;
297 ecmd->port = PORT_OTHER;
298 break;
299 }
300 break;
301 case ixgbe_phy_xaui:
302 ecmd->supported |= SUPPORTED_FIBRE;
303 ecmd->advertising |= ADVERTISED_FIBRE;
304 ecmd->port = PORT_NONE;
305 break;
306 case ixgbe_phy_unknown:
307 case ixgbe_phy_generic:
308 case ixgbe_phy_sfp_unsupported:
309 default:
310 ecmd->supported |= SUPPORTED_FIBRE;
311 ecmd->advertising |= ADVERTISED_FIBRE;
312 ecmd->port = PORT_OTHER;
313 break;
314 }
315
316 if (netif_carrier_ok(netdev)) {
317 switch (adapter->link_speed) {
318 case IXGBE_LINK_SPEED_10GB_FULL:
319 ethtool_cmd_speed_set(ecmd, SPEED_10000);
320 break;
321 case IXGBE_LINK_SPEED_2_5GB_FULL:
322 ethtool_cmd_speed_set(ecmd, SPEED_2500);
323 break;
324 case IXGBE_LINK_SPEED_1GB_FULL:
325 ethtool_cmd_speed_set(ecmd, SPEED_1000);
326 break;
327 case IXGBE_LINK_SPEED_100_FULL:
328 ethtool_cmd_speed_set(ecmd, SPEED_100);
329 break;
330 default:
331 break;
332 }
333 ecmd->duplex = DUPLEX_FULL;
334 } else {
335 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
336 ecmd->duplex = DUPLEX_UNKNOWN;
337 }
338
339 return 0;
340 }
341
342 static int ixgbe_set_settings(struct net_device *netdev,
343 struct ethtool_cmd *ecmd)
344 {
345 struct ixgbe_adapter *adapter = netdev_priv(netdev);
346 struct ixgbe_hw *hw = &adapter->hw;
347 u32 advertised, old;
348 s32 err = 0;
349
350 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
351 (hw->phy.multispeed_fiber)) {
352 /*
353 * this function does not support duplex forcing, but can
354 * limit the advertising of the adapter to the specified speed
355 */
356 if (ecmd->advertising & ~ecmd->supported)
357 return -EINVAL;
358
359 /* only allow one speed at a time if no autoneg */
360 if (!ecmd->autoneg && hw->phy.multispeed_fiber) {
361 if (ecmd->advertising ==
362 (ADVERTISED_10000baseT_Full |
363 ADVERTISED_1000baseT_Full))
364 return -EINVAL;
365 }
366
367 old = hw->phy.autoneg_advertised;
368 advertised = 0;
369 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
370 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
371
372 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
373 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
374
375 if (ecmd->advertising & ADVERTISED_100baseT_Full)
376 advertised |= IXGBE_LINK_SPEED_100_FULL;
377
378 if (old == advertised)
379 return err;
380 /* this sets the link speed and restarts auto-neg */
381 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
382 usleep_range(1000, 2000);
383
384 hw->mac.autotry_restart = true;
385 err = hw->mac.ops.setup_link(hw, advertised, true);
386 if (err) {
387 e_info(probe, "setup link failed with code %d\n", err);
388 hw->mac.ops.setup_link(hw, old, true);
389 }
390 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
391 } else {
392 /* in this case we currently only support 10Gb/FULL */
393 u32 speed = ethtool_cmd_speed(ecmd);
394 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
395 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
396 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
397 return -EINVAL;
398 }
399
400 return err;
401 }
402
403 static void ixgbe_get_pauseparam(struct net_device *netdev,
404 struct ethtool_pauseparam *pause)
405 {
406 struct ixgbe_adapter *adapter = netdev_priv(netdev);
407 struct ixgbe_hw *hw = &adapter->hw;
408
409 if (ixgbe_device_supports_autoneg_fc(hw) &&
410 !hw->fc.disable_fc_autoneg)
411 pause->autoneg = 1;
412 else
413 pause->autoneg = 0;
414
415 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
416 pause->rx_pause = 1;
417 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
418 pause->tx_pause = 1;
419 } else if (hw->fc.current_mode == ixgbe_fc_full) {
420 pause->rx_pause = 1;
421 pause->tx_pause = 1;
422 }
423 }
424
425 static int ixgbe_set_pauseparam(struct net_device *netdev,
426 struct ethtool_pauseparam *pause)
427 {
428 struct ixgbe_adapter *adapter = netdev_priv(netdev);
429 struct ixgbe_hw *hw = &adapter->hw;
430 struct ixgbe_fc_info fc = hw->fc;
431
432 /* 82598 does no support link flow control with DCB enabled */
433 if ((hw->mac.type == ixgbe_mac_82598EB) &&
434 (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
435 return -EINVAL;
436
437 /* some devices do not support autoneg of link flow control */
438 if ((pause->autoneg == AUTONEG_ENABLE) &&
439 !ixgbe_device_supports_autoneg_fc(hw))
440 return -EINVAL;
441
442 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
443
444 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
445 fc.requested_mode = ixgbe_fc_full;
446 else if (pause->rx_pause && !pause->tx_pause)
447 fc.requested_mode = ixgbe_fc_rx_pause;
448 else if (!pause->rx_pause && pause->tx_pause)
449 fc.requested_mode = ixgbe_fc_tx_pause;
450 else
451 fc.requested_mode = ixgbe_fc_none;
452
453 /* if the thing changed then we'll update and use new autoneg */
454 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
455 hw->fc = fc;
456 if (netif_running(netdev))
457 ixgbe_reinit_locked(adapter);
458 else
459 ixgbe_reset(adapter);
460 }
461
462 return 0;
463 }
464
465 static u32 ixgbe_get_msglevel(struct net_device *netdev)
466 {
467 struct ixgbe_adapter *adapter = netdev_priv(netdev);
468 return adapter->msg_enable;
469 }
470
471 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
472 {
473 struct ixgbe_adapter *adapter = netdev_priv(netdev);
474 adapter->msg_enable = data;
475 }
476
477 static int ixgbe_get_regs_len(struct net_device *netdev)
478 {
479 #define IXGBE_REGS_LEN 1139
480 return IXGBE_REGS_LEN * sizeof(u32);
481 }
482
483 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
484
485 static void ixgbe_get_regs(struct net_device *netdev,
486 struct ethtool_regs *regs, void *p)
487 {
488 struct ixgbe_adapter *adapter = netdev_priv(netdev);
489 struct ixgbe_hw *hw = &adapter->hw;
490 u32 *regs_buff = p;
491 u8 i;
492
493 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
494
495 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
496 hw->device_id;
497
498 /* General Registers */
499 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
500 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
501 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
502 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
503 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
504 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
505 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
506 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
507
508 /* NVM Register */
509 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
510 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
511 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA(hw));
512 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
513 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
514 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
515 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
516 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
517 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
518 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC(hw));
519
520 /* Interrupt */
521 /* don't read EICR because it can clear interrupt causes, instead
522 * read EICS which is a shadow but doesn't clear EICR */
523 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
524 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
525 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
526 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
527 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
528 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
529 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
530 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
531 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
532 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
533 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
534 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
535
536 /* Flow Control */
537 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
538 for (i = 0; i < 4; i++)
539 regs_buff[31 + i] = IXGBE_READ_REG(hw, IXGBE_FCTTV(i));
540 for (i = 0; i < 8; i++) {
541 switch (hw->mac.type) {
542 case ixgbe_mac_82598EB:
543 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
544 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
545 break;
546 case ixgbe_mac_82599EB:
547 case ixgbe_mac_X540:
548 case ixgbe_mac_X550:
549 case ixgbe_mac_X550EM_x:
550 case ixgbe_mac_x550em_a:
551 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
552 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
553 break;
554 default:
555 break;
556 }
557 }
558 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
559 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
560
561 /* Receive DMA */
562 for (i = 0; i < 64; i++)
563 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
564 for (i = 0; i < 64; i++)
565 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
566 for (i = 0; i < 64; i++)
567 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
568 for (i = 0; i < 64; i++)
569 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
570 for (i = 0; i < 64; i++)
571 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
572 for (i = 0; i < 64; i++)
573 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
574 for (i = 0; i < 16; i++)
575 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
576 for (i = 0; i < 16; i++)
577 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
578 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
579 for (i = 0; i < 8; i++)
580 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
581 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
582 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
583
584 /* Receive */
585 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
586 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
587 for (i = 0; i < 16; i++)
588 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
589 for (i = 0; i < 16; i++)
590 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
591 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
592 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
593 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
594 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
595 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
596 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
597 for (i = 0; i < 8; i++)
598 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
599 for (i = 0; i < 8; i++)
600 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
601 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
602
603 /* Transmit */
604 for (i = 0; i < 32; i++)
605 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
606 for (i = 0; i < 32; i++)
607 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
608 for (i = 0; i < 32; i++)
609 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
610 for (i = 0; i < 32; i++)
611 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
612 for (i = 0; i < 32; i++)
613 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
614 for (i = 0; i < 32; i++)
615 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
616 for (i = 0; i < 32; i++)
617 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
618 for (i = 0; i < 32; i++)
619 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
620 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
621 for (i = 0; i < 16; i++)
622 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
623 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
624 for (i = 0; i < 8; i++)
625 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
626 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
627
628 /* Wake Up */
629 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
630 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
631 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
632 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
633 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
634 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
635 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
636 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
637 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
638
639 /* DCB */
640 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */
641 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */
642
643 switch (hw->mac.type) {
644 case ixgbe_mac_82598EB:
645 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
646 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
647 for (i = 0; i < 8; i++)
648 regs_buff[833 + i] =
649 IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
650 for (i = 0; i < 8; i++)
651 regs_buff[841 + i] =
652 IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
653 for (i = 0; i < 8; i++)
654 regs_buff[849 + i] =
655 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
656 for (i = 0; i < 8; i++)
657 regs_buff[857 + i] =
658 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
659 break;
660 case ixgbe_mac_82599EB:
661 case ixgbe_mac_X540:
662 case ixgbe_mac_X550:
663 case ixgbe_mac_X550EM_x:
664 case ixgbe_mac_x550em_a:
665 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
666 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS);
667 for (i = 0; i < 8; i++)
668 regs_buff[833 + i] =
669 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i));
670 for (i = 0; i < 8; i++)
671 regs_buff[841 + i] =
672 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i));
673 for (i = 0; i < 8; i++)
674 regs_buff[849 + i] =
675 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i));
676 for (i = 0; i < 8; i++)
677 regs_buff[857 + i] =
678 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i));
679 break;
680 default:
681 break;
682 }
683
684 for (i = 0; i < 8; i++)
685 regs_buff[865 + i] =
686 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */
687 for (i = 0; i < 8; i++)
688 regs_buff[873 + i] =
689 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */
690
691 /* Statistics */
692 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
693 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
694 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
695 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
696 for (i = 0; i < 8; i++)
697 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
698 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
699 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
700 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
701 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
702 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
703 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
704 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
705 for (i = 0; i < 8; i++)
706 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
707 for (i = 0; i < 8; i++)
708 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
709 for (i = 0; i < 8; i++)
710 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
711 for (i = 0; i < 8; i++)
712 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
713 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
714 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
715 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
716 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
717 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
718 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
719 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
720 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
721 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
722 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
723 regs_buff[942] = (u32)IXGBE_GET_STAT(adapter, gorc);
724 regs_buff[943] = (u32)(IXGBE_GET_STAT(adapter, gorc) >> 32);
725 regs_buff[944] = (u32)IXGBE_GET_STAT(adapter, gotc);
726 regs_buff[945] = (u32)(IXGBE_GET_STAT(adapter, gotc) >> 32);
727 for (i = 0; i < 8; i++)
728 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
729 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
730 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
731 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
732 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
733 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
734 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
735 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
736 regs_buff[961] = (u32)IXGBE_GET_STAT(adapter, tor);
737 regs_buff[962] = (u32)(IXGBE_GET_STAT(adapter, tor) >> 32);
738 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
739 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
740 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
741 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
742 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
743 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
744 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
745 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
746 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
747 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
748 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
749 for (i = 0; i < 16; i++)
750 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
751 for (i = 0; i < 16; i++)
752 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
753 for (i = 0; i < 16; i++)
754 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
755 for (i = 0; i < 16; i++)
756 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
757
758 /* MAC */
759 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
760 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
761 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
762 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
763 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
764 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
765 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
766 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
767 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
768 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
769 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
770 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
771 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
772 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
773 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
774 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
775 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
776 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
777 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
778 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
779 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
780 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
781 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
782 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
783 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
784 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
785 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
786 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
787 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
788 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
789 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
790 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
791 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
792
793 /* Diagnostic */
794 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
795 for (i = 0; i < 8; i++)
796 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
797 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
798 for (i = 0; i < 4; i++)
799 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
800 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
801 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
802 for (i = 0; i < 8; i++)
803 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
804 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
805 for (i = 0; i < 4; i++)
806 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
807 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
808 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
809 for (i = 0; i < 4; i++)
810 regs_buff[1102 + i] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA(i));
811 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
812 for (i = 0; i < 4; i++)
813 regs_buff[1107 + i] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA(i));
814 for (i = 0; i < 8; i++)
815 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
816 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
817 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
818 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
819 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
820 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
821 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
822 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
823 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
824 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
825
826 /* 82599 X540 specific registers */
827 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
828
829 /* 82599 X540 specific DCB registers */
830 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
831 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC);
832 for (i = 0; i < 4; i++)
833 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i));
834 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM);
835 /* same as RTTQCNRM */
836 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD);
837 /* same as RTTQCNRR */
838
839 /* X540 specific DCB registers */
840 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR);
841 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG);
842 }
843
844 static int ixgbe_get_eeprom_len(struct net_device *netdev)
845 {
846 struct ixgbe_adapter *adapter = netdev_priv(netdev);
847 return adapter->hw.eeprom.word_size * 2;
848 }
849
850 static int ixgbe_get_eeprom(struct net_device *netdev,
851 struct ethtool_eeprom *eeprom, u8 *bytes)
852 {
853 struct ixgbe_adapter *adapter = netdev_priv(netdev);
854 struct ixgbe_hw *hw = &adapter->hw;
855 u16 *eeprom_buff;
856 int first_word, last_word, eeprom_len;
857 int ret_val = 0;
858 u16 i;
859
860 if (eeprom->len == 0)
861 return -EINVAL;
862
863 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
864
865 first_word = eeprom->offset >> 1;
866 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
867 eeprom_len = last_word - first_word + 1;
868
869 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
870 if (!eeprom_buff)
871 return -ENOMEM;
872
873 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
874 eeprom_buff);
875
876 /* Device's eeprom is always little-endian, word addressable */
877 for (i = 0; i < eeprom_len; i++)
878 le16_to_cpus(&eeprom_buff[i]);
879
880 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
881 kfree(eeprom_buff);
882
883 return ret_val;
884 }
885
886 static int ixgbe_set_eeprom(struct net_device *netdev,
887 struct ethtool_eeprom *eeprom, u8 *bytes)
888 {
889 struct ixgbe_adapter *adapter = netdev_priv(netdev);
890 struct ixgbe_hw *hw = &adapter->hw;
891 u16 *eeprom_buff;
892 void *ptr;
893 int max_len, first_word, last_word, ret_val = 0;
894 u16 i;
895
896 if (eeprom->len == 0)
897 return -EINVAL;
898
899 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
900 return -EINVAL;
901
902 max_len = hw->eeprom.word_size * 2;
903
904 first_word = eeprom->offset >> 1;
905 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
906 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
907 if (!eeprom_buff)
908 return -ENOMEM;
909
910 ptr = eeprom_buff;
911
912 if (eeprom->offset & 1) {
913 /*
914 * need read/modify/write of first changed EEPROM word
915 * only the second byte of the word is being modified
916 */
917 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]);
918 if (ret_val)
919 goto err;
920
921 ptr++;
922 }
923 if ((eeprom->offset + eeprom->len) & 1) {
924 /*
925 * need read/modify/write of last changed EEPROM word
926 * only the first byte of the word is being modified
927 */
928 ret_val = hw->eeprom.ops.read(hw, last_word,
929 &eeprom_buff[last_word - first_word]);
930 if (ret_val)
931 goto err;
932 }
933
934 /* Device's eeprom is always little-endian, word addressable */
935 for (i = 0; i < last_word - first_word + 1; i++)
936 le16_to_cpus(&eeprom_buff[i]);
937
938 memcpy(ptr, bytes, eeprom->len);
939
940 for (i = 0; i < last_word - first_word + 1; i++)
941 cpu_to_le16s(&eeprom_buff[i]);
942
943 ret_val = hw->eeprom.ops.write_buffer(hw, first_word,
944 last_word - first_word + 1,
945 eeprom_buff);
946
947 /* Update the checksum */
948 if (ret_val == 0)
949 hw->eeprom.ops.update_checksum(hw);
950
951 err:
952 kfree(eeprom_buff);
953 return ret_val;
954 }
955
956 static void ixgbe_get_drvinfo(struct net_device *netdev,
957 struct ethtool_drvinfo *drvinfo)
958 {
959 struct ixgbe_adapter *adapter = netdev_priv(netdev);
960 u32 nvm_track_id;
961
962 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
963 strlcpy(drvinfo->version, ixgbe_driver_version,
964 sizeof(drvinfo->version));
965
966 nvm_track_id = (adapter->eeprom_verh << 16) |
967 adapter->eeprom_verl;
968 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x",
969 nvm_track_id);
970
971 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
972 sizeof(drvinfo->bus_info));
973 }
974
975 static void ixgbe_get_ringparam(struct net_device *netdev,
976 struct ethtool_ringparam *ring)
977 {
978 struct ixgbe_adapter *adapter = netdev_priv(netdev);
979 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
980 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
981
982 ring->rx_max_pending = IXGBE_MAX_RXD;
983 ring->tx_max_pending = IXGBE_MAX_TXD;
984 ring->rx_pending = rx_ring->count;
985 ring->tx_pending = tx_ring->count;
986 }
987
988 static int ixgbe_set_ringparam(struct net_device *netdev,
989 struct ethtool_ringparam *ring)
990 {
991 struct ixgbe_adapter *adapter = netdev_priv(netdev);
992 struct ixgbe_ring *temp_ring;
993 int i, err = 0;
994 u32 new_rx_count, new_tx_count;
995
996 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
997 return -EINVAL;
998
999 new_tx_count = clamp_t(u32, ring->tx_pending,
1000 IXGBE_MIN_TXD, IXGBE_MAX_TXD);
1001 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
1002
1003 new_rx_count = clamp_t(u32, ring->rx_pending,
1004 IXGBE_MIN_RXD, IXGBE_MAX_RXD);
1005 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
1006
1007 if ((new_tx_count == adapter->tx_ring_count) &&
1008 (new_rx_count == adapter->rx_ring_count)) {
1009 /* nothing to do */
1010 return 0;
1011 }
1012
1013 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
1014 usleep_range(1000, 2000);
1015
1016 if (!netif_running(adapter->netdev)) {
1017 for (i = 0; i < adapter->num_tx_queues; i++)
1018 adapter->tx_ring[i]->count = new_tx_count;
1019 for (i = 0; i < adapter->num_rx_queues; i++)
1020 adapter->rx_ring[i]->count = new_rx_count;
1021 adapter->tx_ring_count = new_tx_count;
1022 adapter->rx_ring_count = new_rx_count;
1023 goto clear_reset;
1024 }
1025
1026 /* allocate temporary buffer to store rings in */
1027 i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues);
1028 temp_ring = vmalloc(i * sizeof(struct ixgbe_ring));
1029
1030 if (!temp_ring) {
1031 err = -ENOMEM;
1032 goto clear_reset;
1033 }
1034
1035 ixgbe_down(adapter);
1036
1037 /*
1038 * Setup new Tx resources and free the old Tx resources in that order.
1039 * We can then assign the new resources to the rings via a memcpy.
1040 * The advantage to this approach is that we are guaranteed to still
1041 * have resources even in the case of an allocation failure.
1042 */
1043 if (new_tx_count != adapter->tx_ring_count) {
1044 for (i = 0; i < adapter->num_tx_queues; i++) {
1045 memcpy(&temp_ring[i], adapter->tx_ring[i],
1046 sizeof(struct ixgbe_ring));
1047
1048 temp_ring[i].count = new_tx_count;
1049 err = ixgbe_setup_tx_resources(&temp_ring[i]);
1050 if (err) {
1051 while (i) {
1052 i--;
1053 ixgbe_free_tx_resources(&temp_ring[i]);
1054 }
1055 goto err_setup;
1056 }
1057 }
1058
1059 for (i = 0; i < adapter->num_tx_queues; i++) {
1060 ixgbe_free_tx_resources(adapter->tx_ring[i]);
1061
1062 memcpy(adapter->tx_ring[i], &temp_ring[i],
1063 sizeof(struct ixgbe_ring));
1064 }
1065
1066 adapter->tx_ring_count = new_tx_count;
1067 }
1068
1069 /* Repeat the process for the Rx rings if needed */
1070 if (new_rx_count != adapter->rx_ring_count) {
1071 for (i = 0; i < adapter->num_rx_queues; i++) {
1072 memcpy(&temp_ring[i], adapter->rx_ring[i],
1073 sizeof(struct ixgbe_ring));
1074
1075 temp_ring[i].count = new_rx_count;
1076 err = ixgbe_setup_rx_resources(&temp_ring[i]);
1077 if (err) {
1078 while (i) {
1079 i--;
1080 ixgbe_free_rx_resources(&temp_ring[i]);
1081 }
1082 goto err_setup;
1083 }
1084
1085 }
1086
1087 for (i = 0; i < adapter->num_rx_queues; i++) {
1088 ixgbe_free_rx_resources(adapter->rx_ring[i]);
1089
1090 memcpy(adapter->rx_ring[i], &temp_ring[i],
1091 sizeof(struct ixgbe_ring));
1092 }
1093
1094 adapter->rx_ring_count = new_rx_count;
1095 }
1096
1097 err_setup:
1098 ixgbe_up(adapter);
1099 vfree(temp_ring);
1100 clear_reset:
1101 clear_bit(__IXGBE_RESETTING, &adapter->state);
1102 return err;
1103 }
1104
1105 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
1106 {
1107 switch (sset) {
1108 case ETH_SS_TEST:
1109 return IXGBE_TEST_LEN;
1110 case ETH_SS_STATS:
1111 return IXGBE_STATS_LEN;
1112 default:
1113 return -EOPNOTSUPP;
1114 }
1115 }
1116
1117 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
1118 struct ethtool_stats *stats, u64 *data)
1119 {
1120 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1121 struct rtnl_link_stats64 temp;
1122 const struct rtnl_link_stats64 *net_stats;
1123 unsigned int start;
1124 struct ixgbe_ring *ring;
1125 int i, j;
1126 char *p = NULL;
1127
1128 ixgbe_update_stats(adapter);
1129 net_stats = dev_get_stats(netdev, &temp);
1130 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1131 switch (ixgbe_gstrings_stats[i].type) {
1132 case NETDEV_STATS:
1133 p = (char *) net_stats +
1134 ixgbe_gstrings_stats[i].stat_offset;
1135 break;
1136 case IXGBE_STATS:
1137 p = (char *) adapter +
1138 ixgbe_gstrings_stats[i].stat_offset;
1139 break;
1140 default:
1141 data[i] = 0;
1142 continue;
1143 }
1144
1145 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
1146 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1147 }
1148 for (j = 0; j < netdev->num_tx_queues; j++) {
1149 ring = adapter->tx_ring[j];
1150 if (!ring) {
1151 data[i] = 0;
1152 data[i+1] = 0;
1153 i += 2;
1154 #ifdef BP_EXTENDED_STATS
1155 data[i] = 0;
1156 data[i+1] = 0;
1157 data[i+2] = 0;
1158 i += 3;
1159 #endif
1160 continue;
1161 }
1162
1163 do {
1164 start = u64_stats_fetch_begin_irq(&ring->syncp);
1165 data[i] = ring->stats.packets;
1166 data[i+1] = ring->stats.bytes;
1167 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1168 i += 2;
1169 #ifdef BP_EXTENDED_STATS
1170 data[i] = ring->stats.yields;
1171 data[i+1] = ring->stats.misses;
1172 data[i+2] = ring->stats.cleaned;
1173 i += 3;
1174 #endif
1175 }
1176 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
1177 ring = adapter->rx_ring[j];
1178 if (!ring) {
1179 data[i] = 0;
1180 data[i+1] = 0;
1181 i += 2;
1182 #ifdef BP_EXTENDED_STATS
1183 data[i] = 0;
1184 data[i+1] = 0;
1185 data[i+2] = 0;
1186 i += 3;
1187 #endif
1188 continue;
1189 }
1190
1191 do {
1192 start = u64_stats_fetch_begin_irq(&ring->syncp);
1193 data[i] = ring->stats.packets;
1194 data[i+1] = ring->stats.bytes;
1195 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1196 i += 2;
1197 #ifdef BP_EXTENDED_STATS
1198 data[i] = ring->stats.yields;
1199 data[i+1] = ring->stats.misses;
1200 data[i+2] = ring->stats.cleaned;
1201 i += 3;
1202 #endif
1203 }
1204
1205 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1206 data[i++] = adapter->stats.pxontxc[j];
1207 data[i++] = adapter->stats.pxofftxc[j];
1208 }
1209 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1210 data[i++] = adapter->stats.pxonrxc[j];
1211 data[i++] = adapter->stats.pxoffrxc[j];
1212 }
1213 }
1214
1215 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
1216 u8 *data)
1217 {
1218 char *p = (char *)data;
1219 int i;
1220
1221 switch (stringset) {
1222 case ETH_SS_TEST:
1223 for (i = 0; i < IXGBE_TEST_LEN; i++) {
1224 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN);
1225 data += ETH_GSTRING_LEN;
1226 }
1227 break;
1228 case ETH_SS_STATS:
1229 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1230 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1231 ETH_GSTRING_LEN);
1232 p += ETH_GSTRING_LEN;
1233 }
1234 for (i = 0; i < netdev->num_tx_queues; i++) {
1235 sprintf(p, "tx_queue_%u_packets", i);
1236 p += ETH_GSTRING_LEN;
1237 sprintf(p, "tx_queue_%u_bytes", i);
1238 p += ETH_GSTRING_LEN;
1239 #ifdef BP_EXTENDED_STATS
1240 sprintf(p, "tx_queue_%u_bp_napi_yield", i);
1241 p += ETH_GSTRING_LEN;
1242 sprintf(p, "tx_queue_%u_bp_misses", i);
1243 p += ETH_GSTRING_LEN;
1244 sprintf(p, "tx_queue_%u_bp_cleaned", i);
1245 p += ETH_GSTRING_LEN;
1246 #endif /* BP_EXTENDED_STATS */
1247 }
1248 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) {
1249 sprintf(p, "rx_queue_%u_packets", i);
1250 p += ETH_GSTRING_LEN;
1251 sprintf(p, "rx_queue_%u_bytes", i);
1252 p += ETH_GSTRING_LEN;
1253 #ifdef BP_EXTENDED_STATS
1254 sprintf(p, "rx_queue_%u_bp_poll_yield", i);
1255 p += ETH_GSTRING_LEN;
1256 sprintf(p, "rx_queue_%u_bp_misses", i);
1257 p += ETH_GSTRING_LEN;
1258 sprintf(p, "rx_queue_%u_bp_cleaned", i);
1259 p += ETH_GSTRING_LEN;
1260 #endif /* BP_EXTENDED_STATS */
1261 }
1262 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1263 sprintf(p, "tx_pb_%u_pxon", i);
1264 p += ETH_GSTRING_LEN;
1265 sprintf(p, "tx_pb_%u_pxoff", i);
1266 p += ETH_GSTRING_LEN;
1267 }
1268 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1269 sprintf(p, "rx_pb_%u_pxon", i);
1270 p += ETH_GSTRING_LEN;
1271 sprintf(p, "rx_pb_%u_pxoff", i);
1272 p += ETH_GSTRING_LEN;
1273 }
1274 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1275 break;
1276 }
1277 }
1278
1279 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1280 {
1281 struct ixgbe_hw *hw = &adapter->hw;
1282 bool link_up;
1283 u32 link_speed = 0;
1284
1285 if (ixgbe_removed(hw->hw_addr)) {
1286 *data = 1;
1287 return 1;
1288 }
1289 *data = 0;
1290
1291 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1292 if (link_up)
1293 return *data;
1294 else
1295 *data = 1;
1296 return *data;
1297 }
1298
1299 /* ethtool register test data */
1300 struct ixgbe_reg_test {
1301 u16 reg;
1302 u8 array_len;
1303 u8 test_type;
1304 u32 mask;
1305 u32 write;
1306 };
1307
1308 /* In the hardware, registers are laid out either singly, in arrays
1309 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1310 * most tests take place on arrays or single registers (handled
1311 * as a single-element array) and special-case the tables.
1312 * Table tests are always pattern tests.
1313 *
1314 * We also make provision for some required setup steps by specifying
1315 * registers to be written without any read-back testing.
1316 */
1317
1318 #define PATTERN_TEST 1
1319 #define SET_READ_TEST 2
1320 #define WRITE_NO_TEST 3
1321 #define TABLE32_TEST 4
1322 #define TABLE64_TEST_LO 5
1323 #define TABLE64_TEST_HI 6
1324
1325 /* default 82599 register test */
1326 static const struct ixgbe_reg_test reg_test_82599[] = {
1327 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1328 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1329 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1330 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1331 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1332 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1333 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1334 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1335 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1336 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1337 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1338 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1339 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1340 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1341 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1342 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1343 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1344 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1345 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1346 { .reg = 0 }
1347 };
1348
1349 /* default 82598 register test */
1350 static const struct ixgbe_reg_test reg_test_82598[] = {
1351 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1352 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1353 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1354 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1355 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1356 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1357 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1358 /* Enable all four RX queues before testing. */
1359 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1360 /* RDH is read-only for 82598, only test RDT. */
1361 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1362 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1363 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1364 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1365 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1366 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1367 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1368 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1369 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1370 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1371 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1372 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1373 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1374 { .reg = 0 }
1375 };
1376
1377 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1378 u32 mask, u32 write)
1379 {
1380 u32 pat, val, before;
1381 static const u32 test_pattern[] = {
1382 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1383
1384 if (ixgbe_removed(adapter->hw.hw_addr)) {
1385 *data = 1;
1386 return true;
1387 }
1388 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1389 before = ixgbe_read_reg(&adapter->hw, reg);
1390 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write);
1391 val = ixgbe_read_reg(&adapter->hw, reg);
1392 if (val != (test_pattern[pat] & write & mask)) {
1393 e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1394 reg, val, (test_pattern[pat] & write & mask));
1395 *data = reg;
1396 ixgbe_write_reg(&adapter->hw, reg, before);
1397 return true;
1398 }
1399 ixgbe_write_reg(&adapter->hw, reg, before);
1400 }
1401 return false;
1402 }
1403
1404 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1405 u32 mask, u32 write)
1406 {
1407 u32 val, before;
1408
1409 if (ixgbe_removed(adapter->hw.hw_addr)) {
1410 *data = 1;
1411 return true;
1412 }
1413 before = ixgbe_read_reg(&adapter->hw, reg);
1414 ixgbe_write_reg(&adapter->hw, reg, write & mask);
1415 val = ixgbe_read_reg(&adapter->hw, reg);
1416 if ((write & mask) != (val & mask)) {
1417 e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1418 reg, (val & mask), (write & mask));
1419 *data = reg;
1420 ixgbe_write_reg(&adapter->hw, reg, before);
1421 return true;
1422 }
1423 ixgbe_write_reg(&adapter->hw, reg, before);
1424 return false;
1425 }
1426
1427 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1428 {
1429 const struct ixgbe_reg_test *test;
1430 u32 value, before, after;
1431 u32 i, toggle;
1432
1433 if (ixgbe_removed(adapter->hw.hw_addr)) {
1434 e_err(drv, "Adapter removed - register test blocked\n");
1435 *data = 1;
1436 return 1;
1437 }
1438 switch (adapter->hw.mac.type) {
1439 case ixgbe_mac_82598EB:
1440 toggle = 0x7FFFF3FF;
1441 test = reg_test_82598;
1442 break;
1443 case ixgbe_mac_82599EB:
1444 case ixgbe_mac_X540:
1445 case ixgbe_mac_X550:
1446 case ixgbe_mac_X550EM_x:
1447 case ixgbe_mac_x550em_a:
1448 toggle = 0x7FFFF30F;
1449 test = reg_test_82599;
1450 break;
1451 default:
1452 *data = 1;
1453 return 1;
1454 }
1455
1456 /*
1457 * Because the status register is such a special case,
1458 * we handle it separately from the rest of the register
1459 * tests. Some bits are read-only, some toggle, and some
1460 * are writeable on newer MACs.
1461 */
1462 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS);
1463 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle);
1464 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle);
1465 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle;
1466 if (value != after) {
1467 e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1468 after, value);
1469 *data = 1;
1470 return 1;
1471 }
1472 /* restore previous status */
1473 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before);
1474
1475 /*
1476 * Perform the remainder of the register test, looping through
1477 * the test table until we either fail or reach the null entry.
1478 */
1479 while (test->reg) {
1480 for (i = 0; i < test->array_len; i++) {
1481 bool b = false;
1482
1483 switch (test->test_type) {
1484 case PATTERN_TEST:
1485 b = reg_pattern_test(adapter, data,
1486 test->reg + (i * 0x40),
1487 test->mask,
1488 test->write);
1489 break;
1490 case SET_READ_TEST:
1491 b = reg_set_and_check(adapter, data,
1492 test->reg + (i * 0x40),
1493 test->mask,
1494 test->write);
1495 break;
1496 case WRITE_NO_TEST:
1497 ixgbe_write_reg(&adapter->hw,
1498 test->reg + (i * 0x40),
1499 test->write);
1500 break;
1501 case TABLE32_TEST:
1502 b = reg_pattern_test(adapter, data,
1503 test->reg + (i * 4),
1504 test->mask,
1505 test->write);
1506 break;
1507 case TABLE64_TEST_LO:
1508 b = reg_pattern_test(adapter, data,
1509 test->reg + (i * 8),
1510 test->mask,
1511 test->write);
1512 break;
1513 case TABLE64_TEST_HI:
1514 b = reg_pattern_test(adapter, data,
1515 (test->reg + 4) + (i * 8),
1516 test->mask,
1517 test->write);
1518 break;
1519 }
1520 if (b)
1521 return 1;
1522 }
1523 test++;
1524 }
1525
1526 *data = 0;
1527 return 0;
1528 }
1529
1530 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1531 {
1532 struct ixgbe_hw *hw = &adapter->hw;
1533 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1534 *data = 1;
1535 else
1536 *data = 0;
1537 return *data;
1538 }
1539
1540 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1541 {
1542 struct net_device *netdev = (struct net_device *) data;
1543 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1544
1545 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1546
1547 return IRQ_HANDLED;
1548 }
1549
1550 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1551 {
1552 struct net_device *netdev = adapter->netdev;
1553 u32 mask, i = 0, shared_int = true;
1554 u32 irq = adapter->pdev->irq;
1555
1556 *data = 0;
1557
1558 /* Hook up test interrupt handler just for this test */
1559 if (adapter->msix_entries) {
1560 /* NOTE: we don't test MSI-X interrupts here, yet */
1561 return 0;
1562 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1563 shared_int = false;
1564 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
1565 netdev)) {
1566 *data = 1;
1567 return -1;
1568 }
1569 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
1570 netdev->name, netdev)) {
1571 shared_int = false;
1572 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
1573 netdev->name, netdev)) {
1574 *data = 1;
1575 return -1;
1576 }
1577 e_info(hw, "testing %s interrupt\n", shared_int ?
1578 "shared" : "unshared");
1579
1580 /* Disable all the interrupts */
1581 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1582 IXGBE_WRITE_FLUSH(&adapter->hw);
1583 usleep_range(10000, 20000);
1584
1585 /* Test each interrupt */
1586 for (; i < 10; i++) {
1587 /* Interrupt to test */
1588 mask = BIT(i);
1589
1590 if (!shared_int) {
1591 /*
1592 * Disable the interrupts to be reported in
1593 * the cause register and then force the same
1594 * interrupt and see if one gets posted. If
1595 * an interrupt was posted to the bus, the
1596 * test failed.
1597 */
1598 adapter->test_icr = 0;
1599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1600 ~mask & 0x00007FFF);
1601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1602 ~mask & 0x00007FFF);
1603 IXGBE_WRITE_FLUSH(&adapter->hw);
1604 usleep_range(10000, 20000);
1605
1606 if (adapter->test_icr & mask) {
1607 *data = 3;
1608 break;
1609 }
1610 }
1611
1612 /*
1613 * Enable the interrupt to be reported in the cause
1614 * register and then force the same interrupt and see
1615 * if one gets posted. If an interrupt was not posted
1616 * to the bus, the test failed.
1617 */
1618 adapter->test_icr = 0;
1619 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1620 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1621 IXGBE_WRITE_FLUSH(&adapter->hw);
1622 usleep_range(10000, 20000);
1623
1624 if (!(adapter->test_icr & mask)) {
1625 *data = 4;
1626 break;
1627 }
1628
1629 if (!shared_int) {
1630 /*
1631 * Disable the other interrupts to be reported in
1632 * the cause register and then force the other
1633 * interrupts and see if any get posted. If
1634 * an interrupt was posted to the bus, the
1635 * test failed.
1636 */
1637 adapter->test_icr = 0;
1638 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1639 ~mask & 0x00007FFF);
1640 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1641 ~mask & 0x00007FFF);
1642 IXGBE_WRITE_FLUSH(&adapter->hw);
1643 usleep_range(10000, 20000);
1644
1645 if (adapter->test_icr) {
1646 *data = 5;
1647 break;
1648 }
1649 }
1650 }
1651
1652 /* Disable all the interrupts */
1653 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1654 IXGBE_WRITE_FLUSH(&adapter->hw);
1655 usleep_range(10000, 20000);
1656
1657 /* Unhook test interrupt handler */
1658 free_irq(irq, netdev);
1659
1660 return *data;
1661 }
1662
1663 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1664 {
1665 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1666 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1667 struct ixgbe_hw *hw = &adapter->hw;
1668 u32 reg_ctl;
1669
1670 /* shut down the DMA engines now so they can be reinitialized later */
1671
1672 /* first Rx */
1673 hw->mac.ops.disable_rx(hw);
1674 ixgbe_disable_rx_queue(adapter, rx_ring);
1675
1676 /* now Tx */
1677 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
1678 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1679 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1680
1681 switch (hw->mac.type) {
1682 case ixgbe_mac_82599EB:
1683 case ixgbe_mac_X540:
1684 case ixgbe_mac_X550:
1685 case ixgbe_mac_X550EM_x:
1686 case ixgbe_mac_x550em_a:
1687 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1688 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1689 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1690 break;
1691 default:
1692 break;
1693 }
1694
1695 ixgbe_reset(adapter);
1696
1697 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1698 ixgbe_free_rx_resources(&adapter->test_rx_ring);
1699 }
1700
1701 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1702 {
1703 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1704 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1705 struct ixgbe_hw *hw = &adapter->hw;
1706 u32 rctl, reg_data;
1707 int ret_val;
1708 int err;
1709
1710 /* Setup Tx descriptor ring and Tx buffers */
1711 tx_ring->count = IXGBE_DEFAULT_TXD;
1712 tx_ring->queue_index = 0;
1713 tx_ring->dev = &adapter->pdev->dev;
1714 tx_ring->netdev = adapter->netdev;
1715 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1716
1717 err = ixgbe_setup_tx_resources(tx_ring);
1718 if (err)
1719 return 1;
1720
1721 switch (adapter->hw.mac.type) {
1722 case ixgbe_mac_82599EB:
1723 case ixgbe_mac_X540:
1724 case ixgbe_mac_X550:
1725 case ixgbe_mac_X550EM_x:
1726 case ixgbe_mac_x550em_a:
1727 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1728 reg_data |= IXGBE_DMATXCTL_TE;
1729 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1730 break;
1731 default:
1732 break;
1733 }
1734
1735 ixgbe_configure_tx_ring(adapter, tx_ring);
1736
1737 /* Setup Rx Descriptor ring and Rx buffers */
1738 rx_ring->count = IXGBE_DEFAULT_RXD;
1739 rx_ring->queue_index = 0;
1740 rx_ring->dev = &adapter->pdev->dev;
1741 rx_ring->netdev = adapter->netdev;
1742 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1743
1744 err = ixgbe_setup_rx_resources(rx_ring);
1745 if (err) {
1746 ret_val = 4;
1747 goto err_nomem;
1748 }
1749
1750 hw->mac.ops.disable_rx(hw);
1751
1752 ixgbe_configure_rx_ring(adapter, rx_ring);
1753
1754 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1755 rctl |= IXGBE_RXCTRL_DMBYPS;
1756 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1757
1758 hw->mac.ops.enable_rx(hw);
1759
1760 return 0;
1761
1762 err_nomem:
1763 ixgbe_free_desc_rings(adapter);
1764 return ret_val;
1765 }
1766
1767 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1768 {
1769 struct ixgbe_hw *hw = &adapter->hw;
1770 u32 reg_data;
1771
1772
1773 /* Setup MAC loopback */
1774 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1775 reg_data |= IXGBE_HLREG0_LPBK;
1776 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
1777
1778 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1779 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1780 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
1781
1782 /* X540 and X550 needs to set the MACC.FLU bit to force link up */
1783 switch (adapter->hw.mac.type) {
1784 case ixgbe_mac_X540:
1785 case ixgbe_mac_X550:
1786 case ixgbe_mac_X550EM_x:
1787 case ixgbe_mac_x550em_a:
1788 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
1789 reg_data |= IXGBE_MACC_FLU;
1790 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
1791 break;
1792 default:
1793 if (hw->mac.orig_autoc) {
1794 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU;
1795 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1796 } else {
1797 return 10;
1798 }
1799 }
1800 IXGBE_WRITE_FLUSH(hw);
1801 usleep_range(10000, 20000);
1802
1803 /* Disable Atlas Tx lanes; re-enabled in reset path */
1804 if (hw->mac.type == ixgbe_mac_82598EB) {
1805 u8 atlas;
1806
1807 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1808 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1809 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1810
1811 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1812 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1813 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1814
1815 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1816 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1817 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1818
1819 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1820 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1821 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1822 }
1823
1824 return 0;
1825 }
1826
1827 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1828 {
1829 u32 reg_data;
1830
1831 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1832 reg_data &= ~IXGBE_HLREG0_LPBK;
1833 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1834 }
1835
1836 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1837 unsigned int frame_size)
1838 {
1839 memset(skb->data, 0xFF, frame_size);
1840 frame_size >>= 1;
1841 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1);
1842 memset(&skb->data[frame_size + 10], 0xBE, 1);
1843 memset(&skb->data[frame_size + 12], 0xAF, 1);
1844 }
1845
1846 static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer,
1847 unsigned int frame_size)
1848 {
1849 unsigned char *data;
1850 bool match = true;
1851
1852 frame_size >>= 1;
1853
1854 data = kmap(rx_buffer->page) + rx_buffer->page_offset;
1855
1856 if (data[3] != 0xFF ||
1857 data[frame_size + 10] != 0xBE ||
1858 data[frame_size + 12] != 0xAF)
1859 match = false;
1860
1861 kunmap(rx_buffer->page);
1862
1863 return match;
1864 }
1865
1866 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
1867 struct ixgbe_ring *tx_ring,
1868 unsigned int size)
1869 {
1870 union ixgbe_adv_rx_desc *rx_desc;
1871 struct ixgbe_rx_buffer *rx_buffer;
1872 struct ixgbe_tx_buffer *tx_buffer;
1873 u16 rx_ntc, tx_ntc, count = 0;
1874
1875 /* initialize next to clean and descriptor values */
1876 rx_ntc = rx_ring->next_to_clean;
1877 tx_ntc = tx_ring->next_to_clean;
1878 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
1879
1880 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) {
1881 /* check Rx buffer */
1882 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc];
1883
1884 /* sync Rx buffer for CPU read */
1885 dma_sync_single_for_cpu(rx_ring->dev,
1886 rx_buffer->dma,
1887 ixgbe_rx_bufsz(rx_ring),
1888 DMA_FROM_DEVICE);
1889
1890 /* verify contents of skb */
1891 if (ixgbe_check_lbtest_frame(rx_buffer, size))
1892 count++;
1893
1894 /* sync Rx buffer for device write */
1895 dma_sync_single_for_device(rx_ring->dev,
1896 rx_buffer->dma,
1897 ixgbe_rx_bufsz(rx_ring),
1898 DMA_FROM_DEVICE);
1899
1900 /* unmap buffer on Tx side */
1901 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc];
1902 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
1903
1904 /* increment Rx/Tx next to clean counters */
1905 rx_ntc++;
1906 if (rx_ntc == rx_ring->count)
1907 rx_ntc = 0;
1908 tx_ntc++;
1909 if (tx_ntc == tx_ring->count)
1910 tx_ntc = 0;
1911
1912 /* fetch next descriptor */
1913 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
1914 }
1915
1916 netdev_tx_reset_queue(txring_txq(tx_ring));
1917
1918 /* re-map buffers to ring, store next to clean values */
1919 ixgbe_alloc_rx_buffers(rx_ring, count);
1920 rx_ring->next_to_clean = rx_ntc;
1921 tx_ring->next_to_clean = tx_ntc;
1922
1923 return count;
1924 }
1925
1926 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1927 {
1928 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1929 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1930 int i, j, lc, good_cnt, ret_val = 0;
1931 unsigned int size = 1024;
1932 netdev_tx_t tx_ret_val;
1933 struct sk_buff *skb;
1934 u32 flags_orig = adapter->flags;
1935
1936 /* DCB can modify the frames on Tx */
1937 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
1938
1939 /* allocate test skb */
1940 skb = alloc_skb(size, GFP_KERNEL);
1941 if (!skb)
1942 return 11;
1943
1944 /* place data into test skb */
1945 ixgbe_create_lbtest_frame(skb, size);
1946 skb_put(skb, size);
1947
1948 /*
1949 * Calculate the loop count based on the largest descriptor ring
1950 * The idea is to wrap the largest ring a number of times using 64
1951 * send/receive pairs during each loop
1952 */
1953
1954 if (rx_ring->count <= tx_ring->count)
1955 lc = ((tx_ring->count / 64) * 2) + 1;
1956 else
1957 lc = ((rx_ring->count / 64) * 2) + 1;
1958
1959 for (j = 0; j <= lc; j++) {
1960 /* reset count of good packets */
1961 good_cnt = 0;
1962
1963 /* place 64 packets on the transmit queue*/
1964 for (i = 0; i < 64; i++) {
1965 skb_get(skb);
1966 tx_ret_val = ixgbe_xmit_frame_ring(skb,
1967 adapter,
1968 tx_ring);
1969 if (tx_ret_val == NETDEV_TX_OK)
1970 good_cnt++;
1971 }
1972
1973 if (good_cnt != 64) {
1974 ret_val = 12;
1975 break;
1976 }
1977
1978 /* allow 200 milliseconds for packets to go from Tx to Rx */
1979 msleep(200);
1980
1981 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
1982 if (good_cnt != 64) {
1983 ret_val = 13;
1984 break;
1985 }
1986 }
1987
1988 /* free the original skb */
1989 kfree_skb(skb);
1990 adapter->flags = flags_orig;
1991
1992 return ret_val;
1993 }
1994
1995 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1996 {
1997 *data = ixgbe_setup_desc_rings(adapter);
1998 if (*data)
1999 goto out;
2000 *data = ixgbe_setup_loopback_test(adapter);
2001 if (*data)
2002 goto err_loopback;
2003 *data = ixgbe_run_loopback_test(adapter);
2004 ixgbe_loopback_cleanup(adapter);
2005
2006 err_loopback:
2007 ixgbe_free_desc_rings(adapter);
2008 out:
2009 return *data;
2010 }
2011
2012 static void ixgbe_diag_test(struct net_device *netdev,
2013 struct ethtool_test *eth_test, u64 *data)
2014 {
2015 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2016 bool if_running = netif_running(netdev);
2017
2018 if (ixgbe_removed(adapter->hw.hw_addr)) {
2019 e_err(hw, "Adapter removed - test blocked\n");
2020 data[0] = 1;
2021 data[1] = 1;
2022 data[2] = 1;
2023 data[3] = 1;
2024 data[4] = 1;
2025 eth_test->flags |= ETH_TEST_FL_FAILED;
2026 return;
2027 }
2028 set_bit(__IXGBE_TESTING, &adapter->state);
2029 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
2030 struct ixgbe_hw *hw = &adapter->hw;
2031
2032 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2033 int i;
2034 for (i = 0; i < adapter->num_vfs; i++) {
2035 if (adapter->vfinfo[i].clear_to_send) {
2036 netdev_warn(netdev, "offline diagnostic is not supported when VFs are present\n");
2037 data[0] = 1;
2038 data[1] = 1;
2039 data[2] = 1;
2040 data[3] = 1;
2041 data[4] = 1;
2042 eth_test->flags |= ETH_TEST_FL_FAILED;
2043 clear_bit(__IXGBE_TESTING,
2044 &adapter->state);
2045 goto skip_ol_tests;
2046 }
2047 }
2048 }
2049
2050 /* Offline tests */
2051 e_info(hw, "offline testing starting\n");
2052
2053 /* Link test performed before hardware reset so autoneg doesn't
2054 * interfere with test result
2055 */
2056 if (ixgbe_link_test(adapter, &data[4]))
2057 eth_test->flags |= ETH_TEST_FL_FAILED;
2058
2059 if (if_running)
2060 /* indicate we're in test mode */
2061 ixgbe_close(netdev);
2062 else
2063 ixgbe_reset(adapter);
2064
2065 e_info(hw, "register testing starting\n");
2066 if (ixgbe_reg_test(adapter, &data[0]))
2067 eth_test->flags |= ETH_TEST_FL_FAILED;
2068
2069 ixgbe_reset(adapter);
2070 e_info(hw, "eeprom testing starting\n");
2071 if (ixgbe_eeprom_test(adapter, &data[1]))
2072 eth_test->flags |= ETH_TEST_FL_FAILED;
2073
2074 ixgbe_reset(adapter);
2075 e_info(hw, "interrupt testing starting\n");
2076 if (ixgbe_intr_test(adapter, &data[2]))
2077 eth_test->flags |= ETH_TEST_FL_FAILED;
2078
2079 /* If SRIOV or VMDq is enabled then skip MAC
2080 * loopback diagnostic. */
2081 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
2082 IXGBE_FLAG_VMDQ_ENABLED)) {
2083 e_info(hw, "Skip MAC loopback diagnostic in VT mode\n");
2084 data[3] = 0;
2085 goto skip_loopback;
2086 }
2087
2088 ixgbe_reset(adapter);
2089 e_info(hw, "loopback testing starting\n");
2090 if (ixgbe_loopback_test(adapter, &data[3]))
2091 eth_test->flags |= ETH_TEST_FL_FAILED;
2092
2093 skip_loopback:
2094 ixgbe_reset(adapter);
2095
2096 /* clear testing bit and return adapter to previous state */
2097 clear_bit(__IXGBE_TESTING, &adapter->state);
2098 if (if_running)
2099 ixgbe_open(netdev);
2100 else if (hw->mac.ops.disable_tx_laser)
2101 hw->mac.ops.disable_tx_laser(hw);
2102 } else {
2103 e_info(hw, "online testing starting\n");
2104
2105 /* Online tests */
2106 if (ixgbe_link_test(adapter, &data[4]))
2107 eth_test->flags |= ETH_TEST_FL_FAILED;
2108
2109 /* Offline tests aren't run; pass by default */
2110 data[0] = 0;
2111 data[1] = 0;
2112 data[2] = 0;
2113 data[3] = 0;
2114
2115 clear_bit(__IXGBE_TESTING, &adapter->state);
2116 }
2117
2118 skip_ol_tests:
2119 msleep_interruptible(4 * 1000);
2120 }
2121
2122 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
2123 struct ethtool_wolinfo *wol)
2124 {
2125 struct ixgbe_hw *hw = &adapter->hw;
2126 int retval = 0;
2127
2128 /* WOL not supported for all devices */
2129 if (!ixgbe_wol_supported(adapter, hw->device_id,
2130 hw->subsystem_device_id)) {
2131 retval = 1;
2132 wol->supported = 0;
2133 }
2134
2135 return retval;
2136 }
2137
2138 static void ixgbe_get_wol(struct net_device *netdev,
2139 struct ethtool_wolinfo *wol)
2140 {
2141 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2142
2143 wol->supported = WAKE_UCAST | WAKE_MCAST |
2144 WAKE_BCAST | WAKE_MAGIC;
2145 wol->wolopts = 0;
2146
2147 if (ixgbe_wol_exclusion(adapter, wol) ||
2148 !device_can_wakeup(&adapter->pdev->dev))
2149 return;
2150
2151 if (adapter->wol & IXGBE_WUFC_EX)
2152 wol->wolopts |= WAKE_UCAST;
2153 if (adapter->wol & IXGBE_WUFC_MC)
2154 wol->wolopts |= WAKE_MCAST;
2155 if (adapter->wol & IXGBE_WUFC_BC)
2156 wol->wolopts |= WAKE_BCAST;
2157 if (adapter->wol & IXGBE_WUFC_MAG)
2158 wol->wolopts |= WAKE_MAGIC;
2159 }
2160
2161 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2162 {
2163 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2164
2165 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
2166 return -EOPNOTSUPP;
2167
2168 if (ixgbe_wol_exclusion(adapter, wol))
2169 return wol->wolopts ? -EOPNOTSUPP : 0;
2170
2171 adapter->wol = 0;
2172
2173 if (wol->wolopts & WAKE_UCAST)
2174 adapter->wol |= IXGBE_WUFC_EX;
2175 if (wol->wolopts & WAKE_MCAST)
2176 adapter->wol |= IXGBE_WUFC_MC;
2177 if (wol->wolopts & WAKE_BCAST)
2178 adapter->wol |= IXGBE_WUFC_BC;
2179 if (wol->wolopts & WAKE_MAGIC)
2180 adapter->wol |= IXGBE_WUFC_MAG;
2181
2182 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2183
2184 return 0;
2185 }
2186
2187 static int ixgbe_nway_reset(struct net_device *netdev)
2188 {
2189 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2190
2191 if (netif_running(netdev))
2192 ixgbe_reinit_locked(adapter);
2193
2194 return 0;
2195 }
2196
2197 static int ixgbe_set_phys_id(struct net_device *netdev,
2198 enum ethtool_phys_id_state state)
2199 {
2200 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2201 struct ixgbe_hw *hw = &adapter->hw;
2202
2203 switch (state) {
2204 case ETHTOOL_ID_ACTIVE:
2205 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2206 return 2;
2207
2208 case ETHTOOL_ID_ON:
2209 hw->mac.ops.led_on(hw, hw->bus.func);
2210 break;
2211
2212 case ETHTOOL_ID_OFF:
2213 hw->mac.ops.led_off(hw, hw->bus.func);
2214 break;
2215
2216 case ETHTOOL_ID_INACTIVE:
2217 /* Restore LED settings */
2218 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2219 break;
2220 }
2221
2222 return 0;
2223 }
2224
2225 static int ixgbe_get_coalesce(struct net_device *netdev,
2226 struct ethtool_coalesce *ec)
2227 {
2228 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2229
2230 /* only valid if in constant ITR mode */
2231 if (adapter->rx_itr_setting <= 1)
2232 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2233 else
2234 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2235
2236 /* if in mixed tx/rx queues per vector mode, report only rx settings */
2237 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2238 return 0;
2239
2240 /* only valid if in constant ITR mode */
2241 if (adapter->tx_itr_setting <= 1)
2242 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2243 else
2244 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2245
2246 return 0;
2247 }
2248
2249 /*
2250 * this function must be called before setting the new value of
2251 * rx_itr_setting
2252 */
2253 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)
2254 {
2255 struct net_device *netdev = adapter->netdev;
2256
2257 /* nothing to do if LRO or RSC are not enabled */
2258 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||
2259 !(netdev->features & NETIF_F_LRO))
2260 return false;
2261
2262 /* check the feature flag value and enable RSC if necessary */
2263 if (adapter->rx_itr_setting == 1 ||
2264 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
2265 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
2266 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
2267 e_info(probe, "rx-usecs value high enough to re-enable RSC\n");
2268 return true;
2269 }
2270 /* if interrupt rate is too high then disable RSC */
2271 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2272 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2273 e_info(probe, "rx-usecs set too low, disabling RSC\n");
2274 return true;
2275 }
2276 return false;
2277 }
2278
2279 static int ixgbe_set_coalesce(struct net_device *netdev,
2280 struct ethtool_coalesce *ec)
2281 {
2282 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2283 struct ixgbe_q_vector *q_vector;
2284 int i;
2285 u16 tx_itr_param, rx_itr_param, tx_itr_prev;
2286 bool need_reset = false;
2287
2288 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) {
2289 /* reject Tx specific changes in case of mixed RxTx vectors */
2290 if (ec->tx_coalesce_usecs)
2291 return -EINVAL;
2292 tx_itr_prev = adapter->rx_itr_setting;
2293 } else {
2294 tx_itr_prev = adapter->tx_itr_setting;
2295 }
2296
2297 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
2298 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
2299 return -EINVAL;
2300
2301 if (ec->rx_coalesce_usecs > 1)
2302 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2303 else
2304 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2305
2306 if (adapter->rx_itr_setting == 1)
2307 rx_itr_param = IXGBE_20K_ITR;
2308 else
2309 rx_itr_param = adapter->rx_itr_setting;
2310
2311 if (ec->tx_coalesce_usecs > 1)
2312 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2313 else
2314 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2315
2316 if (adapter->tx_itr_setting == 1)
2317 tx_itr_param = IXGBE_12K_ITR;
2318 else
2319 tx_itr_param = adapter->tx_itr_setting;
2320
2321 /* mixed Rx/Tx */
2322 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2323 adapter->tx_itr_setting = adapter->rx_itr_setting;
2324
2325 /* detect ITR changes that require update of TXDCTL.WTHRESH */
2326 if ((adapter->tx_itr_setting != 1) &&
2327 (adapter->tx_itr_setting < IXGBE_100K_ITR)) {
2328 if ((tx_itr_prev == 1) ||
2329 (tx_itr_prev >= IXGBE_100K_ITR))
2330 need_reset = true;
2331 } else {
2332 if ((tx_itr_prev != 1) &&
2333 (tx_itr_prev < IXGBE_100K_ITR))
2334 need_reset = true;
2335 }
2336
2337 /* check the old value and enable RSC if necessary */
2338 need_reset |= ixgbe_update_rsc(adapter);
2339
2340 for (i = 0; i < adapter->num_q_vectors; i++) {
2341 q_vector = adapter->q_vector[i];
2342 if (q_vector->tx.count && !q_vector->rx.count)
2343 /* tx only */
2344 q_vector->itr = tx_itr_param;
2345 else
2346 /* rx only or mixed */
2347 q_vector->itr = rx_itr_param;
2348 ixgbe_write_eitr(q_vector);
2349 }
2350
2351 /*
2352 * do reset here at the end to make sure EITR==0 case is handled
2353 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2354 * also locks in RSC enable/disable which requires reset
2355 */
2356 if (need_reset)
2357 ixgbe_do_reset(netdev);
2358
2359 return 0;
2360 }
2361
2362 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2363 struct ethtool_rxnfc *cmd)
2364 {
2365 union ixgbe_atr_input *mask = &adapter->fdir_mask;
2366 struct ethtool_rx_flow_spec *fsp =
2367 (struct ethtool_rx_flow_spec *)&cmd->fs;
2368 struct hlist_node *node2;
2369 struct ixgbe_fdir_filter *rule = NULL;
2370
2371 /* report total rule count */
2372 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2373
2374 hlist_for_each_entry_safe(rule, node2,
2375 &adapter->fdir_filter_list, fdir_node) {
2376 if (fsp->location <= rule->sw_idx)
2377 break;
2378 }
2379
2380 if (!rule || fsp->location != rule->sw_idx)
2381 return -EINVAL;
2382
2383 /* fill out the flow spec entry */
2384
2385 /* set flow type field */
2386 switch (rule->filter.formatted.flow_type) {
2387 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2388 fsp->flow_type = TCP_V4_FLOW;
2389 break;
2390 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2391 fsp->flow_type = UDP_V4_FLOW;
2392 break;
2393 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2394 fsp->flow_type = SCTP_V4_FLOW;
2395 break;
2396 case IXGBE_ATR_FLOW_TYPE_IPV4:
2397 fsp->flow_type = IP_USER_FLOW;
2398 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2399 fsp->h_u.usr_ip4_spec.proto = 0;
2400 fsp->m_u.usr_ip4_spec.proto = 0;
2401 break;
2402 default:
2403 return -EINVAL;
2404 }
2405
2406 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2407 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2408 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2409 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2410 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2411 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2412 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2413 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2414 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2415 fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2416 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2417 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2418 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2419 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2420 fsp->flow_type |= FLOW_EXT;
2421
2422 /* record action */
2423 if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2424 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2425 else
2426 fsp->ring_cookie = rule->action;
2427
2428 return 0;
2429 }
2430
2431 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2432 struct ethtool_rxnfc *cmd,
2433 u32 *rule_locs)
2434 {
2435 struct hlist_node *node2;
2436 struct ixgbe_fdir_filter *rule;
2437 int cnt = 0;
2438
2439 /* report total rule count */
2440 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2441
2442 hlist_for_each_entry_safe(rule, node2,
2443 &adapter->fdir_filter_list, fdir_node) {
2444 if (cnt == cmd->rule_cnt)
2445 return -EMSGSIZE;
2446 rule_locs[cnt] = rule->sw_idx;
2447 cnt++;
2448 }
2449
2450 cmd->rule_cnt = cnt;
2451
2452 return 0;
2453 }
2454
2455 static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,
2456 struct ethtool_rxnfc *cmd)
2457 {
2458 cmd->data = 0;
2459
2460 /* Report default options for RSS on ixgbe */
2461 switch (cmd->flow_type) {
2462 case TCP_V4_FLOW:
2463 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2464 /* fallthrough */
2465 case UDP_V4_FLOW:
2466 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2467 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2468 /* fallthrough */
2469 case SCTP_V4_FLOW:
2470 case AH_ESP_V4_FLOW:
2471 case AH_V4_FLOW:
2472 case ESP_V4_FLOW:
2473 case IPV4_FLOW:
2474 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2475 break;
2476 case TCP_V6_FLOW:
2477 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2478 /* fallthrough */
2479 case UDP_V6_FLOW:
2480 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2481 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2482 /* fallthrough */
2483 case SCTP_V6_FLOW:
2484 case AH_ESP_V6_FLOW:
2485 case AH_V6_FLOW:
2486 case ESP_V6_FLOW:
2487 case IPV6_FLOW:
2488 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2489 break;
2490 default:
2491 return -EINVAL;
2492 }
2493
2494 return 0;
2495 }
2496
2497 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2498 u32 *rule_locs)
2499 {
2500 struct ixgbe_adapter *adapter = netdev_priv(dev);
2501 int ret = -EOPNOTSUPP;
2502
2503 switch (cmd->cmd) {
2504 case ETHTOOL_GRXRINGS:
2505 cmd->data = adapter->num_rx_queues;
2506 ret = 0;
2507 break;
2508 case ETHTOOL_GRXCLSRLCNT:
2509 cmd->rule_cnt = adapter->fdir_filter_count;
2510 ret = 0;
2511 break;
2512 case ETHTOOL_GRXCLSRULE:
2513 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2514 break;
2515 case ETHTOOL_GRXCLSRLALL:
2516 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
2517 break;
2518 case ETHTOOL_GRXFH:
2519 ret = ixgbe_get_rss_hash_opts(adapter, cmd);
2520 break;
2521 default:
2522 break;
2523 }
2524
2525 return ret;
2526 }
2527
2528 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2529 struct ixgbe_fdir_filter *input,
2530 u16 sw_idx)
2531 {
2532 struct ixgbe_hw *hw = &adapter->hw;
2533 struct hlist_node *node2;
2534 struct ixgbe_fdir_filter *rule, *parent;
2535 int err = -EINVAL;
2536
2537 parent = NULL;
2538 rule = NULL;
2539
2540 hlist_for_each_entry_safe(rule, node2,
2541 &adapter->fdir_filter_list, fdir_node) {
2542 /* hash found, or no matching entry */
2543 if (rule->sw_idx >= sw_idx)
2544 break;
2545 parent = rule;
2546 }
2547
2548 /* if there is an old rule occupying our place remove it */
2549 if (rule && (rule->sw_idx == sw_idx)) {
2550 if (!input || (rule->filter.formatted.bkt_hash !=
2551 input->filter.formatted.bkt_hash)) {
2552 err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2553 &rule->filter,
2554 sw_idx);
2555 }
2556
2557 hlist_del(&rule->fdir_node);
2558 kfree(rule);
2559 adapter->fdir_filter_count--;
2560 }
2561
2562 /*
2563 * If no input this was a delete, err should be 0 if a rule was
2564 * successfully found and removed from the list else -EINVAL
2565 */
2566 if (!input)
2567 return err;
2568
2569 /* initialize node and set software index */
2570 INIT_HLIST_NODE(&input->fdir_node);
2571
2572 /* add filter to the list */
2573 if (parent)
2574 hlist_add_behind(&input->fdir_node, &parent->fdir_node);
2575 else
2576 hlist_add_head(&input->fdir_node,
2577 &adapter->fdir_filter_list);
2578
2579 /* update counts */
2580 adapter->fdir_filter_count++;
2581
2582 return 0;
2583 }
2584
2585 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2586 u8 *flow_type)
2587 {
2588 switch (fsp->flow_type & ~FLOW_EXT) {
2589 case TCP_V4_FLOW:
2590 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2591 break;
2592 case UDP_V4_FLOW:
2593 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2594 break;
2595 case SCTP_V4_FLOW:
2596 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2597 break;
2598 case IP_USER_FLOW:
2599 switch (fsp->h_u.usr_ip4_spec.proto) {
2600 case IPPROTO_TCP:
2601 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2602 break;
2603 case IPPROTO_UDP:
2604 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2605 break;
2606 case IPPROTO_SCTP:
2607 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2608 break;
2609 case 0:
2610 if (!fsp->m_u.usr_ip4_spec.proto) {
2611 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2612 break;
2613 }
2614 default:
2615 return 0;
2616 }
2617 break;
2618 default:
2619 return 0;
2620 }
2621
2622 return 1;
2623 }
2624
2625 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2626 struct ethtool_rxnfc *cmd)
2627 {
2628 struct ethtool_rx_flow_spec *fsp =
2629 (struct ethtool_rx_flow_spec *)&cmd->fs;
2630 struct ixgbe_hw *hw = &adapter->hw;
2631 struct ixgbe_fdir_filter *input;
2632 union ixgbe_atr_input mask;
2633 u8 queue;
2634 int err;
2635
2636 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2637 return -EOPNOTSUPP;
2638
2639 /* ring_cookie is a masked into a set of queues and ixgbe pools or
2640 * we use the drop index.
2641 */
2642 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
2643 queue = IXGBE_FDIR_DROP_QUEUE;
2644 } else {
2645 u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie);
2646 u8 vf = ethtool_get_flow_spec_ring_vf(fsp->ring_cookie);
2647
2648 if (!vf && (ring >= adapter->num_rx_queues))
2649 return -EINVAL;
2650 else if (vf &&
2651 ((vf > adapter->num_vfs) ||
2652 ring >= adapter->num_rx_queues_per_pool))
2653 return -EINVAL;
2654
2655 /* Map the ring onto the absolute queue index */
2656 if (!vf)
2657 queue = adapter->rx_ring[ring]->reg_idx;
2658 else
2659 queue = ((vf - 1) *
2660 adapter->num_rx_queues_per_pool) + ring;
2661 }
2662
2663 /* Don't allow indexes to exist outside of available space */
2664 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2665 e_err(drv, "Location out of range\n");
2666 return -EINVAL;
2667 }
2668
2669 input = kzalloc(sizeof(*input), GFP_ATOMIC);
2670 if (!input)
2671 return -ENOMEM;
2672
2673 memset(&mask, 0, sizeof(union ixgbe_atr_input));
2674
2675 /* set SW index */
2676 input->sw_idx = fsp->location;
2677
2678 /* record flow type */
2679 if (!ixgbe_flowspec_to_flow_type(fsp,
2680 &input->filter.formatted.flow_type)) {
2681 e_err(drv, "Unrecognized flow type\n");
2682 goto err_out;
2683 }
2684
2685 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2686 IXGBE_ATR_L4TYPE_MASK;
2687
2688 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2689 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2690
2691 /* Copy input into formatted structures */
2692 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2693 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2694 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2695 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2696 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2697 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2698 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2699 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2700
2701 if (fsp->flow_type & FLOW_EXT) {
2702 input->filter.formatted.vm_pool =
2703 (unsigned char)ntohl(fsp->h_ext.data[1]);
2704 mask.formatted.vm_pool =
2705 (unsigned char)ntohl(fsp->m_ext.data[1]);
2706 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2707 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2708 input->filter.formatted.flex_bytes =
2709 fsp->h_ext.vlan_etype;
2710 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2711 }
2712
2713 /* determine if we need to drop or route the packet */
2714 if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2715 input->action = IXGBE_FDIR_DROP_QUEUE;
2716 else
2717 input->action = fsp->ring_cookie;
2718
2719 spin_lock(&adapter->fdir_perfect_lock);
2720
2721 if (hlist_empty(&adapter->fdir_filter_list)) {
2722 /* save mask and program input mask into HW */
2723 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2724 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2725 if (err) {
2726 e_err(drv, "Error writing mask\n");
2727 goto err_out_w_lock;
2728 }
2729 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2730 e_err(drv, "Only one mask supported per port\n");
2731 goto err_out_w_lock;
2732 }
2733
2734 /* apply mask and compute/store hash */
2735 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2736
2737 /* program filters to filter memory */
2738 err = ixgbe_fdir_write_perfect_filter_82599(hw,
2739 &input->filter, input->sw_idx, queue);
2740 if (err)
2741 goto err_out_w_lock;
2742
2743 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2744
2745 spin_unlock(&adapter->fdir_perfect_lock);
2746
2747 return err;
2748 err_out_w_lock:
2749 spin_unlock(&adapter->fdir_perfect_lock);
2750 err_out:
2751 kfree(input);
2752 return -EINVAL;
2753 }
2754
2755 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2756 struct ethtool_rxnfc *cmd)
2757 {
2758 struct ethtool_rx_flow_spec *fsp =
2759 (struct ethtool_rx_flow_spec *)&cmd->fs;
2760 int err;
2761
2762 spin_lock(&adapter->fdir_perfect_lock);
2763 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2764 spin_unlock(&adapter->fdir_perfect_lock);
2765
2766 return err;
2767 }
2768
2769 #define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \
2770 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2771 static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,
2772 struct ethtool_rxnfc *nfc)
2773 {
2774 u32 flags2 = adapter->flags2;
2775
2776 /*
2777 * RSS does not support anything other than hashing
2778 * to queues on src and dst IPs and ports
2779 */
2780 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2781 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2782 return -EINVAL;
2783
2784 switch (nfc->flow_type) {
2785 case TCP_V4_FLOW:
2786 case TCP_V6_FLOW:
2787 if (!(nfc->data & RXH_IP_SRC) ||
2788 !(nfc->data & RXH_IP_DST) ||
2789 !(nfc->data & RXH_L4_B_0_1) ||
2790 !(nfc->data & RXH_L4_B_2_3))
2791 return -EINVAL;
2792 break;
2793 case UDP_V4_FLOW:
2794 if (!(nfc->data & RXH_IP_SRC) ||
2795 !(nfc->data & RXH_IP_DST))
2796 return -EINVAL;
2797 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2798 case 0:
2799 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2800 break;
2801 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2802 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2803 break;
2804 default:
2805 return -EINVAL;
2806 }
2807 break;
2808 case UDP_V6_FLOW:
2809 if (!(nfc->data & RXH_IP_SRC) ||
2810 !(nfc->data & RXH_IP_DST))
2811 return -EINVAL;
2812 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2813 case 0:
2814 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2815 break;
2816 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2817 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2818 break;
2819 default:
2820 return -EINVAL;
2821 }
2822 break;
2823 case AH_ESP_V4_FLOW:
2824 case AH_V4_FLOW:
2825 case ESP_V4_FLOW:
2826 case SCTP_V4_FLOW:
2827 case AH_ESP_V6_FLOW:
2828 case AH_V6_FLOW:
2829 case ESP_V6_FLOW:
2830 case SCTP_V6_FLOW:
2831 if (!(nfc->data & RXH_IP_SRC) ||
2832 !(nfc->data & RXH_IP_DST) ||
2833 (nfc->data & RXH_L4_B_0_1) ||
2834 (nfc->data & RXH_L4_B_2_3))
2835 return -EINVAL;
2836 break;
2837 default:
2838 return -EINVAL;
2839 }
2840
2841 /* if we changed something we need to update flags */
2842 if (flags2 != adapter->flags2) {
2843 struct ixgbe_hw *hw = &adapter->hw;
2844 u32 mrqc;
2845 unsigned int pf_pool = adapter->num_vfs;
2846
2847 if ((hw->mac.type >= ixgbe_mac_X550) &&
2848 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2849 mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool));
2850 else
2851 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2852
2853 if ((flags2 & UDP_RSS_FLAGS) &&
2854 !(adapter->flags2 & UDP_RSS_FLAGS))
2855 e_warn(drv, "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2856
2857 adapter->flags2 = flags2;
2858
2859 /* Perform hash on these packet types */
2860 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2861 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2862 | IXGBE_MRQC_RSS_FIELD_IPV6
2863 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2864
2865 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2866 IXGBE_MRQC_RSS_FIELD_IPV6_UDP);
2867
2868 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2869 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2870
2871 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2872 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2873
2874 if ((hw->mac.type >= ixgbe_mac_X550) &&
2875 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2876 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc);
2877 else
2878 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2879 }
2880
2881 return 0;
2882 }
2883
2884 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2885 {
2886 struct ixgbe_adapter *adapter = netdev_priv(dev);
2887 int ret = -EOPNOTSUPP;
2888
2889 switch (cmd->cmd) {
2890 case ETHTOOL_SRXCLSRLINS:
2891 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
2892 break;
2893 case ETHTOOL_SRXCLSRLDEL:
2894 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
2895 break;
2896 case ETHTOOL_SRXFH:
2897 ret = ixgbe_set_rss_hash_opt(adapter, cmd);
2898 break;
2899 default:
2900 break;
2901 }
2902
2903 return ret;
2904 }
2905
2906 static int ixgbe_rss_indir_tbl_max(struct ixgbe_adapter *adapter)
2907 {
2908 if (adapter->hw.mac.type < ixgbe_mac_X550)
2909 return 16;
2910 else
2911 return 64;
2912 }
2913
2914 static u32 ixgbe_get_rxfh_key_size(struct net_device *netdev)
2915 {
2916 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2917
2918 return sizeof(adapter->rss_key);
2919 }
2920
2921 static u32 ixgbe_rss_indir_size(struct net_device *netdev)
2922 {
2923 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2924
2925 return ixgbe_rss_indir_tbl_entries(adapter);
2926 }
2927
2928 static void ixgbe_get_reta(struct ixgbe_adapter *adapter, u32 *indir)
2929 {
2930 int i, reta_size = ixgbe_rss_indir_tbl_entries(adapter);
2931
2932 for (i = 0; i < reta_size; i++)
2933 indir[i] = adapter->rss_indir_tbl[i];
2934 }
2935
2936 static int ixgbe_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
2937 u8 *hfunc)
2938 {
2939 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2940
2941 if (hfunc)
2942 *hfunc = ETH_RSS_HASH_TOP;
2943
2944 if (indir)
2945 ixgbe_get_reta(adapter, indir);
2946
2947 if (key)
2948 memcpy(key, adapter->rss_key, ixgbe_get_rxfh_key_size(netdev));
2949
2950 return 0;
2951 }
2952
2953 static int ixgbe_set_rxfh(struct net_device *netdev, const u32 *indir,
2954 const u8 *key, const u8 hfunc)
2955 {
2956 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2957 int i;
2958 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
2959
2960 if (hfunc)
2961 return -EINVAL;
2962
2963 /* Fill out the redirection table */
2964 if (indir) {
2965 int max_queues = min_t(int, adapter->num_rx_queues,
2966 ixgbe_rss_indir_tbl_max(adapter));
2967
2968 /*Allow at least 2 queues w/ SR-IOV.*/
2969 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2970 (max_queues < 2))
2971 max_queues = 2;
2972
2973 /* Verify user input. */
2974 for (i = 0; i < reta_entries; i++)
2975 if (indir[i] >= max_queues)
2976 return -EINVAL;
2977
2978 for (i = 0; i < reta_entries; i++)
2979 adapter->rss_indir_tbl[i] = indir[i];
2980 }
2981
2982 /* Fill out the rss hash key */
2983 if (key)
2984 memcpy(adapter->rss_key, key, ixgbe_get_rxfh_key_size(netdev));
2985
2986 ixgbe_store_reta(adapter);
2987
2988 return 0;
2989 }
2990
2991 static int ixgbe_get_ts_info(struct net_device *dev,
2992 struct ethtool_ts_info *info)
2993 {
2994 struct ixgbe_adapter *adapter = netdev_priv(dev);
2995
2996 /* we always support timestamping disabled */
2997 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE);
2998
2999 switch (adapter->hw.mac.type) {
3000 case ixgbe_mac_X550:
3001 case ixgbe_mac_X550EM_x:
3002 case ixgbe_mac_x550em_a:
3003 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL);
3004 /* fallthrough */
3005 case ixgbe_mac_X540:
3006 case ixgbe_mac_82599EB:
3007 info->so_timestamping =
3008 SOF_TIMESTAMPING_TX_SOFTWARE |
3009 SOF_TIMESTAMPING_RX_SOFTWARE |
3010 SOF_TIMESTAMPING_SOFTWARE |
3011 SOF_TIMESTAMPING_TX_HARDWARE |
3012 SOF_TIMESTAMPING_RX_HARDWARE |
3013 SOF_TIMESTAMPING_RAW_HARDWARE;
3014
3015 if (adapter->ptp_clock)
3016 info->phc_index = ptp_clock_index(adapter->ptp_clock);
3017 else
3018 info->phc_index = -1;
3019
3020 info->tx_types =
3021 BIT(HWTSTAMP_TX_OFF) |
3022 BIT(HWTSTAMP_TX_ON);
3023
3024 info->rx_filters |=
3025 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
3026 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
3027 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT);
3028 break;
3029 default:
3030 return ethtool_op_get_ts_info(dev, info);
3031 }
3032 return 0;
3033 }
3034
3035 static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter)
3036 {
3037 unsigned int max_combined;
3038 u8 tcs = netdev_get_num_tc(adapter->netdev);
3039
3040 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3041 /* We only support one q_vector without MSI-X */
3042 max_combined = 1;
3043 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3044 /* SR-IOV currently only allows one queue on the PF */
3045 max_combined = 1;
3046 } else if (tcs > 1) {
3047 /* For DCB report channels per traffic class */
3048 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3049 /* 8 TC w/ 4 queues per TC */
3050 max_combined = 4;
3051 } else if (tcs > 4) {
3052 /* 8 TC w/ 8 queues per TC */
3053 max_combined = 8;
3054 } else {
3055 /* 4 TC w/ 16 queues per TC */
3056 max_combined = 16;
3057 }
3058 } else if (adapter->atr_sample_rate) {
3059 /* support up to 64 queues with ATR */
3060 max_combined = IXGBE_MAX_FDIR_INDICES;
3061 } else {
3062 /* support up to 16 queues with RSS */
3063 max_combined = ixgbe_max_rss_indices(adapter);
3064 }
3065
3066 return max_combined;
3067 }
3068
3069 static void ixgbe_get_channels(struct net_device *dev,
3070 struct ethtool_channels *ch)
3071 {
3072 struct ixgbe_adapter *adapter = netdev_priv(dev);
3073
3074 /* report maximum channels */
3075 ch->max_combined = ixgbe_max_channels(adapter);
3076
3077 /* report info for other vector */
3078 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3079 ch->max_other = NON_Q_VECTORS;
3080 ch->other_count = NON_Q_VECTORS;
3081 }
3082
3083 /* record RSS queues */
3084 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices;
3085
3086 /* nothing else to report if RSS is disabled */
3087 if (ch->combined_count == 1)
3088 return;
3089
3090 /* we do not support ATR queueing if SR-IOV is enabled */
3091 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3092 return;
3093
3094 /* same thing goes for being DCB enabled */
3095 if (netdev_get_num_tc(dev) > 1)
3096 return;
3097
3098 /* if ATR is disabled we can exit */
3099 if (!adapter->atr_sample_rate)
3100 return;
3101
3102 /* report flow director queues as maximum channels */
3103 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices;
3104 }
3105
3106 static int ixgbe_set_channels(struct net_device *dev,
3107 struct ethtool_channels *ch)
3108 {
3109 struct ixgbe_adapter *adapter = netdev_priv(dev);
3110 unsigned int count = ch->combined_count;
3111 u8 max_rss_indices = ixgbe_max_rss_indices(adapter);
3112
3113 /* verify they are not requesting separate vectors */
3114 if (!count || ch->rx_count || ch->tx_count)
3115 return -EINVAL;
3116
3117 /* verify other_count has not changed */
3118 if (ch->other_count != NON_Q_VECTORS)
3119 return -EINVAL;
3120
3121 /* verify the number of channels does not exceed hardware limits */
3122 if (count > ixgbe_max_channels(adapter))
3123 return -EINVAL;
3124
3125 /* update feature limits from largest to smallest supported values */
3126 adapter->ring_feature[RING_F_FDIR].limit = count;
3127
3128 /* cap RSS limit */
3129 if (count > max_rss_indices)
3130 count = max_rss_indices;
3131 adapter->ring_feature[RING_F_RSS].limit = count;
3132
3133 #ifdef IXGBE_FCOE
3134 /* cap FCoE limit at 8 */
3135 if (count > IXGBE_FCRETA_SIZE)
3136 count = IXGBE_FCRETA_SIZE;
3137 adapter->ring_feature[RING_F_FCOE].limit = count;
3138
3139 #endif
3140 /* use setup TC to update any traffic class queue mapping */
3141 return ixgbe_setup_tc(dev, netdev_get_num_tc(dev));
3142 }
3143
3144 static int ixgbe_get_module_info(struct net_device *dev,
3145 struct ethtool_modinfo *modinfo)
3146 {
3147 struct ixgbe_adapter *adapter = netdev_priv(dev);
3148 struct ixgbe_hw *hw = &adapter->hw;
3149 s32 status;
3150 u8 sff8472_rev, addr_mode;
3151 bool page_swap = false;
3152
3153 /* Check whether we support SFF-8472 or not */
3154 status = hw->phy.ops.read_i2c_eeprom(hw,
3155 IXGBE_SFF_SFF_8472_COMP,
3156 &sff8472_rev);
3157 if (status)
3158 return -EIO;
3159
3160 /* addressing mode is not supported */
3161 status = hw->phy.ops.read_i2c_eeprom(hw,
3162 IXGBE_SFF_SFF_8472_SWAP,
3163 &addr_mode);
3164 if (status)
3165 return -EIO;
3166
3167 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
3168 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
3169 page_swap = true;
3170 }
3171
3172 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
3173 /* We have a SFP, but it does not support SFF-8472 */
3174 modinfo->type = ETH_MODULE_SFF_8079;
3175 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
3176 } else {
3177 /* We have a SFP which supports a revision of SFF-8472. */
3178 modinfo->type = ETH_MODULE_SFF_8472;
3179 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3180 }
3181
3182 return 0;
3183 }
3184
3185 static int ixgbe_get_module_eeprom(struct net_device *dev,
3186 struct ethtool_eeprom *ee,
3187 u8 *data)
3188 {
3189 struct ixgbe_adapter *adapter = netdev_priv(dev);
3190 struct ixgbe_hw *hw = &adapter->hw;
3191 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
3192 u8 databyte = 0xFF;
3193 int i = 0;
3194
3195 if (ee->len == 0)
3196 return -EINVAL;
3197
3198 for (i = ee->offset; i < ee->offset + ee->len; i++) {
3199 /* I2C reads can take long time */
3200 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3201 return -EBUSY;
3202
3203 if (i < ETH_MODULE_SFF_8079_LEN)
3204 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
3205 else
3206 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
3207
3208 if (status)
3209 return -EIO;
3210
3211 data[i - ee->offset] = databyte;
3212 }
3213
3214 return 0;
3215 }
3216
3217 static const struct ethtool_ops ixgbe_ethtool_ops = {
3218 .get_settings = ixgbe_get_settings,
3219 .set_settings = ixgbe_set_settings,
3220 .get_drvinfo = ixgbe_get_drvinfo,
3221 .get_regs_len = ixgbe_get_regs_len,
3222 .get_regs = ixgbe_get_regs,
3223 .get_wol = ixgbe_get_wol,
3224 .set_wol = ixgbe_set_wol,
3225 .nway_reset = ixgbe_nway_reset,
3226 .get_link = ethtool_op_get_link,
3227 .get_eeprom_len = ixgbe_get_eeprom_len,
3228 .get_eeprom = ixgbe_get_eeprom,
3229 .set_eeprom = ixgbe_set_eeprom,
3230 .get_ringparam = ixgbe_get_ringparam,
3231 .set_ringparam = ixgbe_set_ringparam,
3232 .get_pauseparam = ixgbe_get_pauseparam,
3233 .set_pauseparam = ixgbe_set_pauseparam,
3234 .get_msglevel = ixgbe_get_msglevel,
3235 .set_msglevel = ixgbe_set_msglevel,
3236 .self_test = ixgbe_diag_test,
3237 .get_strings = ixgbe_get_strings,
3238 .set_phys_id = ixgbe_set_phys_id,
3239 .get_sset_count = ixgbe_get_sset_count,
3240 .get_ethtool_stats = ixgbe_get_ethtool_stats,
3241 .get_coalesce = ixgbe_get_coalesce,
3242 .set_coalesce = ixgbe_set_coalesce,
3243 .get_rxnfc = ixgbe_get_rxnfc,
3244 .set_rxnfc = ixgbe_set_rxnfc,
3245 .get_rxfh_indir_size = ixgbe_rss_indir_size,
3246 .get_rxfh_key_size = ixgbe_get_rxfh_key_size,
3247 .get_rxfh = ixgbe_get_rxfh,
3248 .set_rxfh = ixgbe_set_rxfh,
3249 .get_channels = ixgbe_get_channels,
3250 .set_channels = ixgbe_set_channels,
3251 .get_ts_info = ixgbe_get_ts_info,
3252 .get_module_info = ixgbe_get_module_info,
3253 .get_module_eeprom = ixgbe_get_module_eeprom,
3254 };
3255
3256 void ixgbe_set_ethtool_ops(struct net_device *netdev)
3257 {
3258 netdev->ethtool_ops = &ixgbe_ethtool_ops;
3259 }
Linux kernel - Deliverables
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