drivers/net/ethernet/intel/ixgbe/ixgbe_type.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2016 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #ifndef _IXGBE_TYPE_H_
  30 #define _IXGBE_TYPE_H_
  31
  32 #include <linux/types.h>
  33 #include <linux/mdio.h>
  34 #include <linux/netdevice.h>
  35
  36 /* Device IDs */
  37 #define IXGBE_DEV_ID_82598               0x10B6
  38 #define IXGBE_DEV_ID_82598_BX            0x1508
  39 #define IXGBE_DEV_ID_82598AF_DUAL_PORT   0x10C6
  40 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
  41 #define IXGBE_DEV_ID_82598EB_SFP_LOM     0x10DB
  42 #define IXGBE_DEV_ID_82598AT             0x10C8
  43 #define IXGBE_DEV_ID_82598AT2            0x150B
  44 #define IXGBE_DEV_ID_82598EB_CX4         0x10DD
  45 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
  46 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT  0x10F1
  47 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM      0x10E1
  48 #define IXGBE_DEV_ID_82598EB_XF_LR       0x10F4
  49 #define IXGBE_DEV_ID_82599_KX4           0x10F7
  50 #define IXGBE_DEV_ID_82599_KX4_MEZZ      0x1514
  51 #define IXGBE_DEV_ID_82599_KR            0x1517
  52 #define IXGBE_DEV_ID_82599_T3_LOM        0x151C
  53 #define IXGBE_DEV_ID_82599_CX4           0x10F9
  54 #define IXGBE_DEV_ID_82599_SFP           0x10FB
  55 #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE       0x152a
  56 #define IXGBE_DEV_ID_82599_SFP_FCOE      0x1529
  57 #define IXGBE_SUBDEV_ID_82599_SFP        0x11A9
  58 #define IXGBE_SUBDEV_ID_82599_SFP_WOL0   0x1071
  59 #define IXGBE_SUBDEV_ID_82599_RNDC       0x1F72
  60 #define IXGBE_SUBDEV_ID_82599_560FLR     0x17D0
  61 #define IXGBE_SUBDEV_ID_82599_SP_560FLR  0x211B
  62 #define IXGBE_SUBDEV_ID_82599_LOM_SNAP6         0x2159
  63 #define IXGBE_SUBDEV_ID_82599_SFP_1OCP          0x000D
  64 #define IXGBE_SUBDEV_ID_82599_SFP_2OCP          0x0008
  65 #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1      0x8976
  66 #define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2      0x06EE
  67 #define IXGBE_SUBDEV_ID_82599_ECNA_DP    0x0470
  68 #define IXGBE_DEV_ID_82599_SFP_EM        0x1507
  69 #define IXGBE_DEV_ID_82599_SFP_SF2       0x154D
  70 #define IXGBE_DEV_ID_82599EN_SFP         0x1557
  71 #define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001
  72 #define IXGBE_DEV_ID_82599_XAUI_LOM      0x10FC
  73 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
  74 #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ  0x000C
  75 #define IXGBE_DEV_ID_82599_LS            0x154F
  76 #define IXGBE_DEV_ID_X540T               0x1528
  77 #define IXGBE_DEV_ID_82599_SFP_SF_QP     0x154A
  78 #define IXGBE_DEV_ID_82599_QSFP_SF_QP    0x1558
  79 #define IXGBE_DEV_ID_X540T1              0x1560
  80
  81 #define IXGBE_DEV_ID_X550T              0x1563
  82 #define IXGBE_DEV_ID_X550T1             0x15D1
  83 #define IXGBE_DEV_ID_X550EM_X_KX4       0x15AA
  84 #define IXGBE_DEV_ID_X550EM_X_KR        0x15AB
  85 #define IXGBE_DEV_ID_X550EM_X_SFP       0x15AC
  86 #define IXGBE_DEV_ID_X550EM_X_10G_T     0x15AD
  87 #define IXGBE_DEV_ID_X550EM_X_1G_T      0x15AE
  88 #define IXGBE_DEV_ID_X550EM_A_KR        0x15C2
  89 #define IXGBE_DEV_ID_X550EM_A_KR_L      0x15C3
  90 #define IXGBE_DEV_ID_X550EM_A_SFP_N     0x15C4
  91 #define IXGBE_DEV_ID_X550EM_A_SGMII     0x15C6
  92 #define IXGBE_DEV_ID_X550EM_A_SGMII_L   0x15C7
  93 #define IXGBE_DEV_ID_X550EM_A_SFP       0x15CE
  94
  95 /* VF Device IDs */
  96 #define IXGBE_DEV_ID_82599_VF           0x10ED
  97 #define IXGBE_DEV_ID_X540_VF            0x1515
  98 #define IXGBE_DEV_ID_X550_VF            0x1565
  99 #define IXGBE_DEV_ID_X550EM_X_VF        0x15A8
 100 #define IXGBE_DEV_ID_X550EM_A_VF        0x15C5
 101
 102 #define IXGBE_CAT(r, m) IXGBE_##r##_##m
 103
 104 #define IXGBE_BY_MAC(_hw, r)    ((_hw)->mvals[IXGBE_CAT(r, IDX)])
 105
 106 /* General Registers */
 107 #define IXGBE_CTRL      0x00000
 108 #define IXGBE_STATUS    0x00008
 109 #define IXGBE_CTRL_EXT  0x00018
 110 #define IXGBE_ESDP      0x00020
 111 #define IXGBE_EODSDP    0x00028
 112
 113 #define IXGBE_I2CCTL_8259X      0x00028
 114 #define IXGBE_I2CCTL_X540       IXGBE_I2CCTL_8259X
 115 #define IXGBE_I2CCTL_X550       0x15F5C
 116 #define IXGBE_I2CCTL_X550EM_x   IXGBE_I2CCTL_X550
 117 #define IXGBE_I2CCTL_X550EM_a   IXGBE_I2CCTL_X550
 118 #define IXGBE_I2CCTL(_hw)       IXGBE_BY_MAC((_hw), I2CCTL)
 119
 120 #define IXGBE_LEDCTL    0x00200
 121 #define IXGBE_FRTIMER   0x00048
 122 #define IXGBE_TCPTIMER  0x0004C
 123 #define IXGBE_CORESPARE 0x00600
 124 #define IXGBE_EXVET     0x05078
 125
 126 /* NVM Registers */
 127 #define IXGBE_EEC_8259X         0x10010
 128 #define IXGBE_EEC_X540          IXGBE_EEC_8259X
 129 #define IXGBE_EEC_X550          IXGBE_EEC_8259X
 130 #define IXGBE_EEC_X550EM_x      IXGBE_EEC_8259X
 131 #define IXGBE_EEC_X550EM_a      0x15FF8
 132 #define IXGBE_EEC(_hw)          IXGBE_BY_MAC((_hw), EEC)
 133 #define IXGBE_EERD      0x10014
 134 #define IXGBE_EEWR      0x10018
 135 #define IXGBE_FLA_8259X         0x1001C
 136 #define IXGBE_FLA_X540          IXGBE_FLA_8259X
 137 #define IXGBE_FLA_X550          IXGBE_FLA_8259X
 138 #define IXGBE_FLA_X550EM_x      IXGBE_FLA_8259X
 139 #define IXGBE_FLA_X550EM_a      0x15F68
 140 #define IXGBE_FLA(_hw)          IXGBE_BY_MAC((_hw), FLA)
 141 #define IXGBE_EEMNGCTL  0x10110
 142 #define IXGBE_EEMNGDATA 0x10114
 143 #define IXGBE_FLMNGCTL  0x10118
 144 #define IXGBE_FLMNGDATA 0x1011C
 145 #define IXGBE_FLMNGCNT  0x10120
 146 #define IXGBE_FLOP      0x1013C
 147 #define IXGBE_GRC_8259X         0x10200
 148 #define IXGBE_GRC_X540          IXGBE_GRC_8259X
 149 #define IXGBE_GRC_X550          IXGBE_GRC_8259X
 150 #define IXGBE_GRC_X550EM_x      IXGBE_GRC_8259X
 151 #define IXGBE_GRC_X550EM_a      0x15F64
 152 #define IXGBE_GRC(_hw)          IXGBE_BY_MAC((_hw), GRC)
 153
 154 /* General Receive Control */
 155 #define IXGBE_GRC_MNG  0x00000001 /* Manageability Enable */
 156 #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
 157
 158 #define IXGBE_VPDDIAG0  0x10204
 159 #define IXGBE_VPDDIAG1  0x10208
 160
 161 /* I2CCTL Bit Masks */
 162 #define IXGBE_I2C_CLK_IN_8259X          0x00000001
 163 #define IXGBE_I2C_CLK_IN_X540           IXGBE_I2C_CLK_IN_8259X
 164 #define IXGBE_I2C_CLK_IN_X550           0x00004000
 165 #define IXGBE_I2C_CLK_IN_X550EM_x       IXGBE_I2C_CLK_IN_X550
 166 #define IXGBE_I2C_CLK_IN_X550EM_a       IXGBE_I2C_CLK_IN_X550
 167 #define IXGBE_I2C_CLK_IN(_hw)           IXGBE_BY_MAC((_hw), I2C_CLK_IN)
 168
 169 #define IXGBE_I2C_CLK_OUT_8259X         0x00000002
 170 #define IXGBE_I2C_CLK_OUT_X540          IXGBE_I2C_CLK_OUT_8259X
 171 #define IXGBE_I2C_CLK_OUT_X550          0x00000200
 172 #define IXGBE_I2C_CLK_OUT_X550EM_x      IXGBE_I2C_CLK_OUT_X550
 173 #define IXGBE_I2C_CLK_OUT_X550EM_a      IXGBE_I2C_CLK_OUT_X550
 174 #define IXGBE_I2C_CLK_OUT(_hw)          IXGBE_BY_MAC((_hw), I2C_CLK_OUT)
 175
 176 #define IXGBE_I2C_DATA_IN_8259X         0x00000004
 177 #define IXGBE_I2C_DATA_IN_X540          IXGBE_I2C_DATA_IN_8259X
 178 #define IXGBE_I2C_DATA_IN_X550          0x00001000
 179 #define IXGBE_I2C_DATA_IN_X550EM_x      IXGBE_I2C_DATA_IN_X550
 180 #define IXGBE_I2C_DATA_IN_X550EM_a      IXGBE_I2C_DATA_IN_X550
 181 #define IXGBE_I2C_DATA_IN(_hw)          IXGBE_BY_MAC((_hw), I2C_DATA_IN)
 182
 183 #define IXGBE_I2C_DATA_OUT_8259X        0x00000008
 184 #define IXGBE_I2C_DATA_OUT_X540         IXGBE_I2C_DATA_OUT_8259X
 185 #define IXGBE_I2C_DATA_OUT_X550         0x00000400
 186 #define IXGBE_I2C_DATA_OUT_X550EM_x     IXGBE_I2C_DATA_OUT_X550
 187 #define IXGBE_I2C_DATA_OUT_X550EM_a     IXGBE_I2C_DATA_OUT_X550
 188 #define IXGBE_I2C_DATA_OUT(_hw)         IXGBE_BY_MAC((_hw), I2C_DATA_OUT)
 189
 190 #define IXGBE_I2C_DATA_OE_N_EN_8259X    0
 191 #define IXGBE_I2C_DATA_OE_N_EN_X540     IXGBE_I2C_DATA_OE_N_EN_8259X
 192 #define IXGBE_I2C_DATA_OE_N_EN_X550     0x00000800
 193 #define IXGBE_I2C_DATA_OE_N_EN_X550EM_x IXGBE_I2C_DATA_OE_N_EN_X550
 194 #define IXGBE_I2C_DATA_OE_N_EN_X550EM_a IXGBE_I2C_DATA_OE_N_EN_X550
 195 #define IXGBE_I2C_DATA_OE_N_EN(_hw)     IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN)
 196
 197 #define IXGBE_I2C_BB_EN_8259X           0
 198 #define IXGBE_I2C_BB_EN_X540            IXGBE_I2C_BB_EN_8259X
 199 #define IXGBE_I2C_BB_EN_X550            0x00000100
 200 #define IXGBE_I2C_BB_EN_X550EM_x        IXGBE_I2C_BB_EN_X550
 201 #define IXGBE_I2C_BB_EN_X550EM_a        IXGBE_I2C_BB_EN_X550
 202 #define IXGBE_I2C_BB_EN(_hw)            IXGBE_BY_MAC((_hw), I2C_BB_EN)
 203
 204 #define IXGBE_I2C_CLK_OE_N_EN_8259X     0
 205 #define IXGBE_I2C_CLK_OE_N_EN_X540      IXGBE_I2C_CLK_OE_N_EN_8259X
 206 #define IXGBE_I2C_CLK_OE_N_EN_X550      0x00002000
 207 #define IXGBE_I2C_CLK_OE_N_EN_X550EM_x  IXGBE_I2C_CLK_OE_N_EN_X550
 208 #define IXGBE_I2C_CLK_OE_N_EN_X550EM_a  IXGBE_I2C_CLK_OE_N_EN_X550
 209 #define IXGBE_I2C_CLK_OE_N_EN(_hw)       IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN)
 210
 211 #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT      500
 212
 213 #define IXGBE_I2C_THERMAL_SENSOR_ADDR   0xF8
 214 #define IXGBE_EMC_INTERNAL_DATA         0x00
 215 #define IXGBE_EMC_INTERNAL_THERM_LIMIT  0x20
 216 #define IXGBE_EMC_DIODE1_DATA           0x01
 217 #define IXGBE_EMC_DIODE1_THERM_LIMIT    0x19
 218 #define IXGBE_EMC_DIODE2_DATA           0x23
 219 #define IXGBE_EMC_DIODE2_THERM_LIMIT    0x1A
 220
 221 #define IXGBE_MAX_SENSORS               3
 222
 223 struct ixgbe_thermal_diode_data {
 224         u8 location;
 225         u8 temp;
 226         u8 caution_thresh;
 227         u8 max_op_thresh;
 228 };
 229
 230 struct ixgbe_thermal_sensor_data {
 231         struct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS];
 232 };
 233
 234 /* Interrupt Registers */
 235 #define IXGBE_EICR      0x00800
 236 #define IXGBE_EICS      0x00808
 237 #define IXGBE_EIMS      0x00880
 238 #define IXGBE_EIMC      0x00888
 239 #define IXGBE_EIAC      0x00810
 240 #define IXGBE_EIAM      0x00890
 241 #define IXGBE_EICS_EX(_i)   (0x00A90 + (_i) * 4)
 242 #define IXGBE_EIMS_EX(_i)   (0x00AA0 + (_i) * 4)
 243 #define IXGBE_EIMC_EX(_i)   (0x00AB0 + (_i) * 4)
 244 #define IXGBE_EIAM_EX(_i)   (0x00AD0 + (_i) * 4)
 245 /*
 246  * 82598 EITR is 16 bits but set the limits based on the max
 247  * supported by all ixgbe hardware.  82599 EITR is only 12 bits,
 248  * with the lower 3 always zero.
 249  */
 250 #define IXGBE_MAX_INT_RATE 488281
 251 #define IXGBE_MIN_INT_RATE 956
 252 #define IXGBE_MAX_EITR     0x00000FF8
 253 #define IXGBE_MIN_EITR     8
 254 #define IXGBE_EITR(_i)  (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
 255                          (0x012300 + (((_i) - 24) * 4)))
 256 #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
 257 #define IXGBE_EITR_LLI_MOD      0x00008000
 258 #define IXGBE_EITR_CNT_WDIS     0x80000000
 259 #define IXGBE_IVAR(_i)  (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
 260 #define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
 261 #define IXGBE_EITRSEL   0x00894
 262 #define IXGBE_MSIXT     0x00000 /* MSI-X Table. 0x0000 - 0x01C */
 263 #define IXGBE_MSIXPBA   0x02000 /* MSI-X Pending bit array */
 264 #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
 265 #define IXGBE_GPIE      0x00898
 266
 267 /* Flow Control Registers */
 268 #define IXGBE_FCADBUL   0x03210
 269 #define IXGBE_FCADBUH   0x03214
 270 #define IXGBE_FCAMACL   0x04328
 271 #define IXGBE_FCAMACH   0x0432C
 272 #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
 273 #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
 274 #define IXGBE_PFCTOP    0x03008
 275 #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
 276 #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
 277 #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
 278 #define IXGBE_FCRTV     0x032A0
 279 #define IXGBE_FCCFG     0x03D00
 280 #define IXGBE_TFCS      0x0CE00
 281
 282 /* Receive DMA Registers */
 283 #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
 284                          (0x0D000 + (((_i) - 64) * 0x40)))
 285 #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
 286                          (0x0D004 + (((_i) - 64) * 0x40)))
 287 #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
 288                          (0x0D008 + (((_i) - 64) * 0x40)))
 289 #define IXGBE_RDH(_i)   (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
 290                          (0x0D010 + (((_i) - 64) * 0x40)))
 291 #define IXGBE_RDT(_i)   (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
 292                          (0x0D018 + (((_i) - 64) * 0x40)))
 293 #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
 294                          (0x0D028 + (((_i) - 64) * 0x40)))
 295 #define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
 296                          (0x0D02C + (((_i) - 64) * 0x40)))
 297 #define IXGBE_RSCDBU     0x03028
 298 #define IXGBE_RDDCC      0x02F20
 299 #define IXGBE_RXMEMWRAP  0x03190
 300 #define IXGBE_STARCTRL   0x03024
 301 /*
 302  * Split and Replication Receive Control Registers
 303  * 00-15 : 0x02100 + n*4
 304  * 16-64 : 0x01014 + n*0x40
 305  * 64-127: 0x0D014 + (n-64)*0x40
 306  */
 307 #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
 308                           (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
 309                           (0x0D014 + (((_i) - 64) * 0x40))))
 310 /*
 311  * Rx DCA Control Register:
 312  * 00-15 : 0x02200 + n*4
 313  * 16-64 : 0x0100C + n*0x40
 314  * 64-127: 0x0D00C + (n-64)*0x40
 315  */
 316 #define IXGBE_DCA_RXCTRL(_i)    (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
 317                                  (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
 318                                  (0x0D00C + (((_i) - 64) * 0x40))))
 319 #define IXGBE_RDRXCTL           0x02F00
 320 #define IXGBE_RXPBSIZE(_i)      (0x03C00 + ((_i) * 4))
 321                                              /* 8 of these 0x03C00 - 0x03C1C */
 322 #define IXGBE_RXCTRL    0x03000
 323 #define IXGBE_DROPEN    0x03D04
 324 #define IXGBE_RXPBSIZE_SHIFT 10
 325
 326 /* Receive Registers */
 327 #define IXGBE_RXCSUM    0x05000
 328 #define IXGBE_RFCTL     0x05008
 329 #define IXGBE_DRECCCTL  0x02F08
 330 #define IXGBE_DRECCCTL_DISABLE 0
 331 /* Multicast Table Array - 128 entries */
 332 #define IXGBE_MTA(_i)   (0x05200 + ((_i) * 4))
 333 #define IXGBE_RAL(_i)   (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
 334                          (0x0A200 + ((_i) * 8)))
 335 #define IXGBE_RAH(_i)   (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
 336                          (0x0A204 + ((_i) * 8)))
 337 #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
 338 #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
 339 /* Packet split receive type */
 340 #define IXGBE_PSRTYPE(_i)    (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
 341                               (0x0EA00 + ((_i) * 4)))
 342 /* array of 4096 1-bit vlan filters */
 343 #define IXGBE_VFTA(_i)  (0x0A000 + ((_i) * 4))
 344 /*array of 4096 4-bit vlan vmdq indices */
 345 #define IXGBE_VFTAVIND(_j, _i)  (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
 346 #define IXGBE_FCTRL     0x05080
 347 #define IXGBE_VLNCTRL   0x05088
 348 #define IXGBE_MCSTCTRL  0x05090
 349 #define IXGBE_MRQC      0x05818
 350 #define IXGBE_SAQF(_i)  (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
 351 #define IXGBE_DAQF(_i)  (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
 352 #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
 353 #define IXGBE_FTQF(_i)  (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
 354 #define IXGBE_ETQF(_i)  (0x05128 + ((_i) * 4)) /* EType Queue Filter */
 355 #define IXGBE_ETQS(_i)  (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
 356 #define IXGBE_SYNQF     0x0EC30 /* SYN Packet Queue Filter */
 357 #define IXGBE_RQTC      0x0EC70
 358 #define IXGBE_MTQC      0x08120
 359 #define IXGBE_VLVF(_i)  (0x0F100 + ((_i) * 4))  /* 64 of these (0-63) */
 360 #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4))  /* 128 of these (0-127) */
 361 #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4))  /* 64 of these (0-63) */
 362 #define IXGBE_PFFLPL    0x050B0
 363 #define IXGBE_PFFLPH    0x050B4
 364 #define IXGBE_VT_CTL         0x051B0
 365 #define IXGBE_PFMAILBOX(_i)  (0x04B00 + (4 * (_i))) /* 64 total */
 366 #define IXGBE_PFMBMEM(_i)    (0x13000 + (64 * (_i))) /* 64 Mailboxes, 16 DW each */
 367 #define IXGBE_PFMBICR(_i)    (0x00710 + (4 * (_i))) /* 4 total */
 368 #define IXGBE_PFMBIMR(_i)    (0x00720 + (4 * (_i))) /* 4 total */
 369 #define IXGBE_VFRE(_i)       (0x051E0 + ((_i) * 4))
 370 #define IXGBE_VFTE(_i)       (0x08110 + ((_i) * 4))
 371 #define IXGBE_VMECM(_i)      (0x08790 + ((_i) * 4))
 372 #define IXGBE_QDE            0x2F04
 373 #define IXGBE_VMTXSW(_i)     (0x05180 + ((_i) * 4)) /* 2 total */
 374 #define IXGBE_VMOLR(_i)      (0x0F000 + ((_i) * 4)) /* 64 total */
 375 #define IXGBE_UTA(_i)        (0x0F400 + ((_i) * 4))
 376 #define IXGBE_MRCTL(_i)      (0x0F600 + ((_i) * 4))
 377 #define IXGBE_VMRVLAN(_i)    (0x0F610 + ((_i) * 4))
 378 #define IXGBE_VMRVM(_i)      (0x0F630 + ((_i) * 4))
 379 #define IXGBE_WQBR_RX(_i)    (0x2FB0 + ((_i) * 4)) /* 4 total */
 380 #define IXGBE_WQBR_TX(_i)    (0x8130 + ((_i) * 4)) /* 4 total */
 381 #define IXGBE_L34T_IMIR(_i)  (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
 382 #define IXGBE_RXFECCERR0         0x051B8
 383 #define IXGBE_LLITHRESH 0x0EC90
 384 #define IXGBE_IMIR(_i)  (0x05A80 + ((_i) * 4))  /* 8 of these (0-7) */
 385 #define IXGBE_IMIREXT(_i)       (0x05AA0 + ((_i) * 4))  /* 8 of these (0-7) */
 386 #define IXGBE_IMIRVP    0x05AC0
 387 #define IXGBE_VMD_CTL   0x0581C
 388 #define IXGBE_RETA(_i)  (0x05C00 + ((_i) * 4))  /* 32 of these (0-31) */
 389 #define IXGBE_ERETA(_i) (0x0EE80 + ((_i) * 4))  /* 96 of these (0-95) */
 390 #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4))  /* 10 of these (0-9) */
 391
 392 /* Registers for setting up RSS on X550 with SRIOV
 393  * _p - pool number (0..63)
 394  * _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA)
 395  */
 396 #define IXGBE_PFVFMRQC(_p)      (0x03400 + ((_p) * 4))
 397 #define IXGBE_PFVFRSSRK(_i, _p) (0x018000 + ((_i) * 4) + ((_p) * 0x40))
 398 #define IXGBE_PFVFRETA(_i, _p)  (0x019000 + ((_i) * 4) + ((_p) * 0x40))
 399
 400 /* Flow Director registers */
 401 #define IXGBE_FDIRCTRL  0x0EE00
 402 #define IXGBE_FDIRHKEY  0x0EE68
 403 #define IXGBE_FDIRSKEY  0x0EE6C
 404 #define IXGBE_FDIRDIP4M 0x0EE3C
 405 #define IXGBE_FDIRSIP4M 0x0EE40
 406 #define IXGBE_FDIRTCPM  0x0EE44
 407 #define IXGBE_FDIRUDPM  0x0EE48
 408 #define IXGBE_FDIRSCTPM 0x0EE78
 409 #define IXGBE_FDIRIP6M  0x0EE74
 410 #define IXGBE_FDIRM     0x0EE70
 411
 412 /* Flow Director Stats registers */
 413 #define IXGBE_FDIRFREE  0x0EE38
 414 #define IXGBE_FDIRLEN   0x0EE4C
 415 #define IXGBE_FDIRUSTAT 0x0EE50
 416 #define IXGBE_FDIRFSTAT 0x0EE54
 417 #define IXGBE_FDIRMATCH 0x0EE58
 418 #define IXGBE_FDIRMISS  0x0EE5C
 419
 420 /* Flow Director Programming registers */
 421 #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
 422 #define IXGBE_FDIRIPSA      0x0EE18
 423 #define IXGBE_FDIRIPDA      0x0EE1C
 424 #define IXGBE_FDIRPORT      0x0EE20
 425 #define IXGBE_FDIRVLAN      0x0EE24
 426 #define IXGBE_FDIRHASH      0x0EE28
 427 #define IXGBE_FDIRCMD       0x0EE2C
 428
 429 /* Transmit DMA registers */
 430 #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
 431 #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
 432 #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
 433 #define IXGBE_TDH(_i)   (0x06010 + ((_i) * 0x40))
 434 #define IXGBE_TDT(_i)   (0x06018 + ((_i) * 0x40))
 435 #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
 436 #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
 437 #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
 438 #define IXGBE_DTXCTL    0x07E00
 439
 440 #define IXGBE_DMATXCTL      0x04A80
 441 #define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
 442 #define IXGBE_PFDTXGSWC     0x08220
 443 #define IXGBE_DTXMXSZRQ     0x08100
 444 #define IXGBE_DTXTCPFLGL    0x04A88
 445 #define IXGBE_DTXTCPFLGH    0x04A8C
 446 #define IXGBE_LBDRPEN       0x0CA00
 447 #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
 448
 449 #define IXGBE_DMATXCTL_TE       0x1 /* Transmit Enable */
 450 #define IXGBE_DMATXCTL_NS       0x2 /* No Snoop LSO hdr buffer */
 451 #define IXGBE_DMATXCTL_GDV      0x8 /* Global Double VLAN */
 452 #define IXGBE_DMATXCTL_MDP_EN   0x20 /* Bit 5 */
 453 #define IXGBE_DMATXCTL_MBINTEN  0x40 /* Bit 6 */
 454 #define IXGBE_DMATXCTL_VT_SHIFT 16  /* VLAN EtherType */
 455
 456 #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
 457
 458 /* Anti-spoofing defines */
 459 #define IXGBE_SPOOF_MACAS_MASK          0xFF
 460 #define IXGBE_SPOOF_VLANAS_MASK         0xFF00
 461 #define IXGBE_SPOOF_VLANAS_SHIFT        8
 462 #define IXGBE_SPOOF_ETHERTYPEAS         0xFF000000
 463 #define IXGBE_SPOOF_ETHERTYPEAS_SHIFT   16
 464 #define IXGBE_PFVFSPOOF_REG_COUNT       8
 465
 466 #define IXGBE_DCA_TXCTRL(_i)    (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
 467 /* Tx DCA Control register : 128 of these (0-127) */
 468 #define IXGBE_DCA_TXCTRL_82599(_i)  (0x0600C + ((_i) * 0x40))
 469 #define IXGBE_TIPG      0x0CB00
 470 #define IXGBE_TXPBSIZE(_i)      (0x0CC00 + ((_i) * 4)) /* 8 of these */
 471 #define IXGBE_MNGTXMAP  0x0CD10
 472 #define IXGBE_TIPG_FIBER_DEFAULT 3
 473 #define IXGBE_TXPBSIZE_SHIFT    10
 474
 475 /* Wake up registers */
 476 #define IXGBE_WUC       0x05800
 477 #define IXGBE_WUFC      0x05808
 478 #define IXGBE_WUS       0x05810
 479 #define IXGBE_IPAV      0x05838
 480 #define IXGBE_IP4AT     0x05840 /* IPv4 table 0x5840-0x5858 */
 481 #define IXGBE_IP6AT     0x05880 /* IPv6 table 0x5880-0x588F */
 482
 483 #define IXGBE_WUPL      0x05900
 484 #define IXGBE_WUPM      0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
 485 #define IXGBE_VXLANCTRL 0x0000507C /* Rx filter VXLAN UDPPORT Register */
 486 #define IXGBE_FHFT(_n)  (0x09000 + ((_n) * 0x100)) /* Flex host filter table */
 487 #define IXGBE_FHFT_EXT(_n)      (0x09800 + ((_n) * 0x100)) /* Ext Flexible Host
 488                                                             * Filter Table */
 489
 490 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX         4
 491 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX     2
 492
 493 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
 494 #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX  128
 495 #define IXGBE_FHFT_LENGTH_OFFSET        0xFC  /* Length byte in FHFT */
 496 #define IXGBE_FHFT_LENGTH_MASK          0x0FF /* Length in lower byte */
 497
 498 /* Definitions for power management and wakeup registers */
 499 /* Wake Up Control */
 500 #define IXGBE_WUC_PME_EN     0x00000002 /* PME Enable */
 501 #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
 502 #define IXGBE_WUC_WKEN       0x00000010 /* Enable PE_WAKE_N pin assertion  */
 503
 504 /* Wake Up Filter Control */
 505 #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
 506 #define IXGBE_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
 507 #define IXGBE_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
 508 #define IXGBE_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
 509 #define IXGBE_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
 510 #define IXGBE_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
 511 #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
 512 #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
 513 #define IXGBE_WUFC_MNG  0x00000100 /* Directed Mgmt Packet Wakeup Enable */
 514
 515 #define IXGBE_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */
 516 #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
 517 #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
 518 #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
 519 #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
 520 #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
 521 #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
 522 #define IXGBE_WUFC_FLX_FILTERS     0x000F0000 /* Mask for 4 flex filters */
 523 #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
 524 #define IXGBE_WUFC_ALL_FILTERS     0x003F00FF /* Mask for all wakeup filters */
 525 #define IXGBE_WUFC_FLX_OFFSET      16 /* Offset to the Flexible Filters bits */
 526
 527 /* Wake Up Status */
 528 #define IXGBE_WUS_LNKC  IXGBE_WUFC_LNKC
 529 #define IXGBE_WUS_MAG   IXGBE_WUFC_MAG
 530 #define IXGBE_WUS_EX    IXGBE_WUFC_EX
 531 #define IXGBE_WUS_MC    IXGBE_WUFC_MC
 532 #define IXGBE_WUS_BC    IXGBE_WUFC_BC
 533 #define IXGBE_WUS_ARP   IXGBE_WUFC_ARP
 534 #define IXGBE_WUS_IPV4  IXGBE_WUFC_IPV4
 535 #define IXGBE_WUS_IPV6  IXGBE_WUFC_IPV6
 536 #define IXGBE_WUS_MNG   IXGBE_WUFC_MNG
 537 #define IXGBE_WUS_FLX0  IXGBE_WUFC_FLX0
 538 #define IXGBE_WUS_FLX1  IXGBE_WUFC_FLX1
 539 #define IXGBE_WUS_FLX2  IXGBE_WUFC_FLX2
 540 #define IXGBE_WUS_FLX3  IXGBE_WUFC_FLX3
 541 #define IXGBE_WUS_FLX4  IXGBE_WUFC_FLX4
 542 #define IXGBE_WUS_FLX5  IXGBE_WUFC_FLX5
 543 #define IXGBE_WUS_FLX_FILTERS  IXGBE_WUFC_FLX_FILTERS
 544
 545 /* Wake Up Packet Length */
 546 #define IXGBE_WUPL_LENGTH_MASK 0xFFFF
 547
 548 /* DCB registers */
 549 #define MAX_TRAFFIC_CLASS        8
 550 #define X540_TRAFFIC_CLASS       4
 551 #define DEF_TRAFFIC_CLASS        1
 552 #define IXGBE_RMCS      0x03D00
 553 #define IXGBE_DPMCS     0x07F40
 554 #define IXGBE_PDPMCS    0x0CD00
 555 #define IXGBE_RUPPBMR   0x050A0
 556 #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
 557 #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
 558 #define IXGBE_TDTQ2TCCR(_i)     (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
 559 #define IXGBE_TDTQ2TCSR(_i)     (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
 560 #define IXGBE_TDPT2TCCR(_i)     (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
 561 #define IXGBE_TDPT2TCSR(_i)     (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
 562
 563 /* Security Control Registers */
 564 #define IXGBE_SECTXCTRL         0x08800
 565 #define IXGBE_SECTXSTAT         0x08804
 566 #define IXGBE_SECTXBUFFAF       0x08808
 567 #define IXGBE_SECTXMINIFG       0x08810
 568 #define IXGBE_SECRXCTRL         0x08D00
 569 #define IXGBE_SECRXSTAT         0x08D04
 570
 571 /* Security Bit Fields and Masks */
 572 #define IXGBE_SECTXCTRL_SECTX_DIS       0x00000001
 573 #define IXGBE_SECTXCTRL_TX_DIS          0x00000002
 574 #define IXGBE_SECTXCTRL_STORE_FORWARD   0x00000004
 575
 576 #define IXGBE_SECTXSTAT_SECTX_RDY       0x00000001
 577 #define IXGBE_SECTXSTAT_ECC_TXERR       0x00000002
 578
 579 #define IXGBE_SECRXCTRL_SECRX_DIS       0x00000001
 580 #define IXGBE_SECRXCTRL_RX_DIS          0x00000002
 581
 582 #define IXGBE_SECRXSTAT_SECRX_RDY       0x00000001
 583 #define IXGBE_SECRXSTAT_ECC_RXERR       0x00000002
 584
 585 /* LinkSec (MacSec) Registers */
 586 #define IXGBE_LSECTXCAP         0x08A00
 587 #define IXGBE_LSECRXCAP         0x08F00
 588 #define IXGBE_LSECTXCTRL        0x08A04
 589 #define IXGBE_LSECTXSCL         0x08A08 /* SCI Low */
 590 #define IXGBE_LSECTXSCH         0x08A0C /* SCI High */
 591 #define IXGBE_LSECTXSA          0x08A10
 592 #define IXGBE_LSECTXPN0         0x08A14
 593 #define IXGBE_LSECTXPN1         0x08A18
 594 #define IXGBE_LSECTXKEY0(_n)    (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
 595 #define IXGBE_LSECTXKEY1(_n)    (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
 596 #define IXGBE_LSECRXCTRL        0x08F04
 597 #define IXGBE_LSECRXSCL         0x08F08
 598 #define IXGBE_LSECRXSCH         0x08F0C
 599 #define IXGBE_LSECRXSA(_i)      (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
 600 #define IXGBE_LSECRXPN(_i)      (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
 601 #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
 602 #define IXGBE_LSECTXUT          0x08A3C /* OutPktsUntagged */
 603 #define IXGBE_LSECTXPKTE        0x08A40 /* OutPktsEncrypted */
 604 #define IXGBE_LSECTXPKTP        0x08A44 /* OutPktsProtected */
 605 #define IXGBE_LSECTXOCTE        0x08A48 /* OutOctetsEncrypted */
 606 #define IXGBE_LSECTXOCTP        0x08A4C /* OutOctetsProtected */
 607 #define IXGBE_LSECRXUT          0x08F40 /* InPktsUntagged/InPktsNoTag */
 608 #define IXGBE_LSECRXOCTD        0x08F44 /* InOctetsDecrypted */
 609 #define IXGBE_LSECRXOCTV        0x08F48 /* InOctetsValidated */
 610 #define IXGBE_LSECRXBAD         0x08F4C /* InPktsBadTag */
 611 #define IXGBE_LSECRXNOSCI       0x08F50 /* InPktsNoSci */
 612 #define IXGBE_LSECRXUNSCI       0x08F54 /* InPktsUnknownSci */
 613 #define IXGBE_LSECRXUNCH        0x08F58 /* InPktsUnchecked */
 614 #define IXGBE_LSECRXDELAY       0x08F5C /* InPktsDelayed */
 615 #define IXGBE_LSECRXLATE        0x08F60 /* InPktsLate */
 616 #define IXGBE_LSECRXOK(_n)      (0x08F64 + (0x04 * (_n))) /* InPktsOk */
 617 #define IXGBE_LSECRXINV(_n)     (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
 618 #define IXGBE_LSECRXNV(_n)      (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
 619 #define IXGBE_LSECRXUNSA        0x08F7C /* InPktsUnusedSa */
 620 #define IXGBE_LSECRXNUSA        0x08F80 /* InPktsNotUsingSa */
 621
 622 /* LinkSec (MacSec) Bit Fields and Masks */
 623 #define IXGBE_LSECTXCAP_SUM_MASK        0x00FF0000
 624 #define IXGBE_LSECTXCAP_SUM_SHIFT       16
 625 #define IXGBE_LSECRXCAP_SUM_MASK        0x00FF0000
 626 #define IXGBE_LSECRXCAP_SUM_SHIFT       16
 627
 628 #define IXGBE_LSECTXCTRL_EN_MASK        0x00000003
 629 #define IXGBE_LSECTXCTRL_DISABLE        0x0
 630 #define IXGBE_LSECTXCTRL_AUTH           0x1
 631 #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT   0x2
 632 #define IXGBE_LSECTXCTRL_AISCI          0x00000020
 633 #define IXGBE_LSECTXCTRL_PNTHRSH_MASK   0xFFFFFF00
 634 #define IXGBE_LSECTXCTRL_RSV_MASK       0x000000D8
 635
 636 #define IXGBE_LSECRXCTRL_EN_MASK        0x0000000C
 637 #define IXGBE_LSECRXCTRL_EN_SHIFT       2
 638 #define IXGBE_LSECRXCTRL_DISABLE        0x0
 639 #define IXGBE_LSECRXCTRL_CHECK          0x1
 640 #define IXGBE_LSECRXCTRL_STRICT         0x2
 641 #define IXGBE_LSECRXCTRL_DROP           0x3
 642 #define IXGBE_LSECRXCTRL_PLSH           0x00000040
 643 #define IXGBE_LSECRXCTRL_RP             0x00000080
 644 #define IXGBE_LSECRXCTRL_RSV_MASK       0xFFFFFF33
 645
 646 /* IpSec Registers */
 647 #define IXGBE_IPSTXIDX          0x08900
 648 #define IXGBE_IPSTXSALT         0x08904
 649 #define IXGBE_IPSTXKEY(_i)      (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
 650 #define IXGBE_IPSRXIDX          0x08E00
 651 #define IXGBE_IPSRXIPADDR(_i)   (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
 652 #define IXGBE_IPSRXSPI          0x08E14
 653 #define IXGBE_IPSRXIPIDX        0x08E18
 654 #define IXGBE_IPSRXKEY(_i)      (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
 655 #define IXGBE_IPSRXSALT         0x08E2C
 656 #define IXGBE_IPSRXMOD          0x08E30
 657
 658 #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE    0x4
 659
 660 /* DCB registers */
 661 #define IXGBE_RTRPCS      0x02430
 662 #define IXGBE_RTTDCS      0x04900
 663 #define IXGBE_RTTDCS_ARBDIS     0x00000040 /* DCB arbiter disable */
 664 #define IXGBE_RTTPCS      0x0CD00
 665 #define IXGBE_RTRUP2TC    0x03020
 666 #define IXGBE_RTTUP2TC    0x0C800
 667 #define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
 668 #define IXGBE_TXLLQ(_i)   (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */
 669 #define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
 670 #define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
 671 #define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
 672 #define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
 673 #define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
 674 #define IXGBE_RTTDQSEL    0x04904
 675 #define IXGBE_RTTDT1C     0x04908
 676 #define IXGBE_RTTDT1S     0x0490C
 677 #define IXGBE_RTTQCNCR    0x08B00
 678 #define IXGBE_RTTQCNTG    0x04A90
 679 #define IXGBE_RTTBCNRD    0x0498C
 680 #define IXGBE_RTTQCNRR    0x0498C
 681 #define IXGBE_RTTDTECC    0x04990
 682 #define IXGBE_RTTDTECC_NO_BCN   0x00000100
 683 #define IXGBE_RTTBCNRC    0x04984
 684 #define IXGBE_RTTBCNRC_RS_ENA   0x80000000
 685 #define IXGBE_RTTBCNRC_RF_DEC_MASK      0x00003FFF
 686 #define IXGBE_RTTBCNRC_RF_INT_SHIFT     14
 687 #define IXGBE_RTTBCNRC_RF_INT_MASK      \
 688         (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
 689 #define IXGBE_RTTBCNRM    0x04980
 690 #define IXGBE_RTTQCNRM    0x04980
 691
 692 /* FCoE Direct DMA Context */
 693 #define IXGBE_FCDDC(_i, _j)     (0x20000 + ((_i) * 0x4) + ((_j) * 0x10))
 694 /* FCoE DMA Context Registers */
 695 #define IXGBE_FCPTRL    0x02410 /* FC User Desc. PTR Low */
 696 #define IXGBE_FCPTRH    0x02414 /* FC USer Desc. PTR High */
 697 #define IXGBE_FCBUFF    0x02418 /* FC Buffer Control */
 698 #define IXGBE_FCDMARW   0x02420 /* FC Receive DMA RW */
 699 #define IXGBE_FCINVST0  0x03FC0 /* FC Invalid DMA Context Status Reg 0 */
 700 #define IXGBE_FCINVST(_i)       (IXGBE_FCINVST0 + ((_i) * 4))
 701 #define IXGBE_FCBUFF_VALID      BIT(0)    /* DMA Context Valid */
 702 #define IXGBE_FCBUFF_BUFFSIZE   (3u << 3) /* User Buffer Size */
 703 #define IXGBE_FCBUFF_WRCONTX    BIT(7)    /* 0: Initiator, 1: Target */
 704 #define IXGBE_FCBUFF_BUFFCNT    0x0000ff00 /* Number of User Buffers */
 705 #define IXGBE_FCBUFF_OFFSET     0xffff0000 /* User Buffer Offset */
 706 #define IXGBE_FCBUFF_BUFFSIZE_SHIFT  3
 707 #define IXGBE_FCBUFF_BUFFCNT_SHIFT   8
 708 #define IXGBE_FCBUFF_OFFSET_SHIFT    16
 709 #define IXGBE_FCDMARW_WE        BIT(14)   /* Write enable */
 710 #define IXGBE_FCDMARW_RE        BIT(15)   /* Read enable */
 711 #define IXGBE_FCDMARW_FCOESEL   0x000001ff  /* FC X_ID: 11 bits */
 712 #define IXGBE_FCDMARW_LASTSIZE  0xffff0000  /* Last User Buffer Size */
 713 #define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
 714
 715 /* FCoE SOF/EOF */
 716 #define IXGBE_TEOFF     0x04A94 /* Tx FC EOF */
 717 #define IXGBE_TSOFF     0x04A98 /* Tx FC SOF */
 718 #define IXGBE_REOFF     0x05158 /* Rx FC EOF */
 719 #define IXGBE_RSOFF     0x051F8 /* Rx FC SOF */
 720 /* FCoE Direct Filter Context */
 721 #define IXGBE_FCDFC(_i, _j)     (0x28000 + ((_i) * 0x4) + ((_j) * 0x10))
 722 #define IXGBE_FCDFCD(_i)        (0x30000 + ((_i) * 0x4))
 723 /* FCoE Filter Context Registers */
 724 #define IXGBE_FCFLT     0x05108 /* FC FLT Context */
 725 #define IXGBE_FCFLTRW   0x05110 /* FC Filter RW Control */
 726 #define IXGBE_FCPARAM   0x051d8 /* FC Offset Parameter */
 727 #define IXGBE_FCFLT_VALID       BIT(0)   /* Filter Context Valid */
 728 #define IXGBE_FCFLT_FIRST       BIT(1)   /* Filter First */
 729 #define IXGBE_FCFLT_SEQID       0x00ff0000 /* Sequence ID */
 730 #define IXGBE_FCFLT_SEQCNT      0xff000000 /* Sequence Count */
 731 #define IXGBE_FCFLTRW_RVALDT    BIT(13)  /* Fast Re-Validation */
 732 #define IXGBE_FCFLTRW_WE        BIT(14)  /* Write Enable */
 733 #define IXGBE_FCFLTRW_RE        BIT(15)  /* Read Enable */
 734 /* FCoE Receive Control */
 735 #define IXGBE_FCRXCTRL  0x05100 /* FC Receive Control */
 736 #define IXGBE_FCRXCTRL_FCOELLI  BIT(0)   /* Low latency interrupt */
 737 #define IXGBE_FCRXCTRL_SAVBAD   BIT(1)   /* Save Bad Frames */
 738 #define IXGBE_FCRXCTRL_FRSTRDH  BIT(2)   /* EN 1st Read Header */
 739 #define IXGBE_FCRXCTRL_LASTSEQH BIT(3)   /* EN Last Header in Seq */
 740 #define IXGBE_FCRXCTRL_ALLH     BIT(4)   /* EN All Headers */
 741 #define IXGBE_FCRXCTRL_FRSTSEQH BIT(5)   /* EN 1st Seq. Header */
 742 #define IXGBE_FCRXCTRL_ICRC     BIT(6)   /* Ignore Bad FC CRC */
 743 #define IXGBE_FCRXCTRL_FCCRCBO  BIT(7)   /* FC CRC Byte Ordering */
 744 #define IXGBE_FCRXCTRL_FCOEVER  0x00000f00 /* FCoE Version: 4 bits */
 745 #define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
 746 /* FCoE Redirection */
 747 #define IXGBE_FCRECTL   0x0ED00 /* FC Redirection Control */
 748 #define IXGBE_FCRETA0   0x0ED10 /* FC Redirection Table 0 */
 749 #define IXGBE_FCRETA(_i)        (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
 750 #define IXGBE_FCRECTL_ENA       0x1        /* FCoE Redir Table Enable */
 751 #define IXGBE_FCRETA_SIZE       8          /* Max entries in FCRETA */
 752 #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
 753 #define IXGBE_FCRETA_SIZE_X550  32 /* Max entries in FCRETA */
 754 /* Higher 7 bits for the queue index */
 755 #define IXGBE_FCRETA_ENTRY_HIGH_MASK    0x007F0000
 756 #define IXGBE_FCRETA_ENTRY_HIGH_SHIFT   16
 757
 758 /* Stats registers */
 759 #define IXGBE_CRCERRS   0x04000
 760 #define IXGBE_ILLERRC   0x04004
 761 #define IXGBE_ERRBC     0x04008
 762 #define IXGBE_MSPDC     0x04010
 763 #define IXGBE_MPC(_i)   (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
 764 #define IXGBE_MLFC      0x04034
 765 #define IXGBE_MRFC      0x04038
 766 #define IXGBE_RLEC      0x04040
 767 #define IXGBE_LXONTXC   0x03F60
 768 #define IXGBE_LXONRXC   0x0CF60
 769 #define IXGBE_LXOFFTXC  0x03F68
 770 #define IXGBE_LXOFFRXC  0x0CF68
 771 #define IXGBE_LXONRXCNT 0x041A4
 772 #define IXGBE_LXOFFRXCNT 0x041A8
 773 #define IXGBE_PXONRXCNT(_i)     (0x04140 + ((_i) * 4)) /* 8 of these */
 774 #define IXGBE_PXOFFRXCNT(_i)    (0x04160 + ((_i) * 4)) /* 8 of these */
 775 #define IXGBE_PXON2OFFCNT(_i)   (0x03240 + ((_i) * 4)) /* 8 of these */
 776 #define IXGBE_PXONTXC(_i)       (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
 777 #define IXGBE_PXONRXC(_i)       (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
 778 #define IXGBE_PXOFFTXC(_i)      (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
 779 #define IXGBE_PXOFFRXC(_i)      (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
 780 #define IXGBE_PRC64     0x0405C
 781 #define IXGBE_PRC127    0x04060
 782 #define IXGBE_PRC255    0x04064
 783 #define IXGBE_PRC511    0x04068
 784 #define IXGBE_PRC1023   0x0406C
 785 #define IXGBE_PRC1522   0x04070
 786 #define IXGBE_GPRC      0x04074
 787 #define IXGBE_BPRC      0x04078
 788 #define IXGBE_MPRC      0x0407C
 789 #define IXGBE_GPTC      0x04080
 790 #define IXGBE_GORCL     0x04088
 791 #define IXGBE_GORCH     0x0408C
 792 #define IXGBE_GOTCL     0x04090
 793 #define IXGBE_GOTCH     0x04094
 794 #define IXGBE_RNBC(_i)  (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
 795 #define IXGBE_RUC       0x040A4
 796 #define IXGBE_RFC       0x040A8
 797 #define IXGBE_ROC       0x040AC
 798 #define IXGBE_RJC       0x040B0
 799 #define IXGBE_MNGPRC    0x040B4
 800 #define IXGBE_MNGPDC    0x040B8
 801 #define IXGBE_MNGPTC    0x0CF90
 802 #define IXGBE_TORL      0x040C0
 803 #define IXGBE_TORH      0x040C4
 804 #define IXGBE_TPR       0x040D0
 805 #define IXGBE_TPT       0x040D4
 806 #define IXGBE_PTC64     0x040D8
 807 #define IXGBE_PTC127    0x040DC
 808 #define IXGBE_PTC255    0x040E0
 809 #define IXGBE_PTC511    0x040E4
 810 #define IXGBE_PTC1023   0x040E8
 811 #define IXGBE_PTC1522   0x040EC
 812 #define IXGBE_MPTC      0x040F0
 813 #define IXGBE_BPTC      0x040F4
 814 #define IXGBE_XEC       0x04120
 815 #define IXGBE_SSVPC     0x08780
 816
 817 #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
 818 #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
 819                          (0x08600 + ((_i) * 4)))
 820 #define IXGBE_TQSM(_i)  (0x08600 + ((_i) * 4))
 821
 822 #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
 823 #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
 824 #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
 825 #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
 826 #define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
 827 #define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */
 828 #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
 829 #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
 830 #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
 831 #define IXGBE_FCCRC     0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */
 832 #define IXGBE_FCOERPDC  0x0241C /* FCoE Rx Packets Dropped Count */
 833 #define IXGBE_FCLAST    0x02424 /* FCoE Last Error Count */
 834 #define IXGBE_FCOEPRC   0x02428 /* Number of FCoE Packets Received */
 835 #define IXGBE_FCOEDWRC  0x0242C /* Number of FCoE DWords Received */
 836 #define IXGBE_FCOEPTC   0x08784 /* Number of FCoE Packets Transmitted */
 837 #define IXGBE_FCOEDWTC  0x08788 /* Number of FCoE DWords Transmitted */
 838 #define IXGBE_O2BGPTC   0x041C4
 839 #define IXGBE_O2BSPC    0x087B0
 840 #define IXGBE_B2OSPC    0x041C0
 841 #define IXGBE_B2OGPRC   0x02F90
 842 #define IXGBE_PCRC8ECL  0x0E810
 843 #define IXGBE_PCRC8ECH  0x0E811
 844 #define IXGBE_PCRC8ECH_MASK     0x1F
 845 #define IXGBE_LDPCECL   0x0E820
 846 #define IXGBE_LDPCECH   0x0E821
 847
 848 /* MII clause 22/28 definitions */
 849 #define IXGBE_MDIO_PHY_LOW_POWER_MODE   0x0800
 850
 851 #define IXGBE_MDIO_XENPAK_LASI_STATUS   0x9005 /* XENPAK LASI Status register */
 852 #define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM 0x1 /* Link Status Alarm change */
 853
 854 #define IXGBE_MDIO_AUTO_NEG_LINK_STATUS 0x4 /* Indicates if link is up */
 855
 856 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK  0x7 /* Speed/Duplex Mask */
 857 #define IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK 0x6 /* Speed Mask */
 858 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF 0x0 /* 10Mb/s Half Duplex */
 859 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL 0x1 /* 10Mb/s Full Duplex */
 860 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF 0x2 /* 100Mb/s H Duplex */
 861 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL 0x3 /* 100Mb/s F Duplex */
 862 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF 0x4 /* 1Gb/s Half Duplex */
 863 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL 0x5 /* 1Gb/s Full Duplex */
 864 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF 0x6 /* 10Gb/s Half Duplex */
 865 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL 0x7 /* 10Gb/s Full Duplex */
 866 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB   0x4 /* 1Gb/s */
 867 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB  0x6 /* 10Gb/s */
 868
 869 #define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG    0x20    /* 10G Control Reg */
 870 #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
 871 #define IXGBE_MII_AUTONEG_XNP_TX_REG            0x17    /* 1G XNP Transmit */
 872 #define IXGBE_MII_AUTONEG_ADVERTISE_REG         0x10    /* 100M Advertisement */
 873 #define IXGBE_MII_10GBASE_T_ADVERTISE           0x1000  /* full duplex, bit:12*/
 874 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX     0x4000  /* full duplex, bit:14*/
 875 #define IXGBE_MII_1GBASE_T_ADVERTISE            0x8000  /* full duplex, bit:15*/
 876 #define IXGBE_MII_2_5GBASE_T_ADVERTISE          0x0400
 877 #define IXGBE_MII_5GBASE_T_ADVERTISE            0x0800
 878 #define IXGBE_MII_100BASE_T_ADVERTISE           0x0100  /* full duplex, bit:8 */
 879 #define IXGBE_MII_100BASE_T_ADVERTISE_HALF      0x0080  /* half duplex, bit:7 */
 880 #define IXGBE_MII_RESTART                       0x200
 881 #define IXGBE_MII_AUTONEG_COMPLETE              0x20
 882 #define IXGBE_MII_AUTONEG_LINK_UP               0x04
 883 #define IXGBE_MII_AUTONEG_REG                   0x0
 884
 885 /* Management */
 886 #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
 887 #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
 888 #define IXGBE_MANC      0x05820
 889 #define IXGBE_MFVAL     0x05824
 890 #define IXGBE_MANC2H    0x05860
 891 #define IXGBE_MDEF(_i)  (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
 892 #define IXGBE_MIPAF     0x058B0
 893 #define IXGBE_MMAL(_i)  (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
 894 #define IXGBE_MMAH(_i)  (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
 895 #define IXGBE_FTFT      0x09400 /* 0x9400-0x97FC */
 896 #define IXGBE_METF(_i)  (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
 897 #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
 898 #define IXGBE_LSWFW     0x15014
 899
 900 /* Management Bit Fields and Masks */
 901 #define IXGBE_MANC_RCV_TCO_EN   0x00020000 /* Rcv TCO packet enable */
 902
 903 /* Firmware Semaphore Register */
 904 #define IXGBE_FWSM_MODE_MASK    0xE
 905 #define IXGBE_FWSM_FW_MODE_PT   0x4
 906
 907 /* ARC Subsystem registers */
 908 #define IXGBE_HICR      0x15F00
 909 #define IXGBE_FWSTS     0x15F0C
 910 #define IXGBE_HSMC0R    0x15F04
 911 #define IXGBE_HSMC1R    0x15F08
 912 #define IXGBE_SWSR      0x15F10
 913 #define IXGBE_HFDR      0x15FE8
 914 #define IXGBE_FLEX_MNG  0x15800 /* 0x15800 - 0x15EFC */
 915
 916 #define IXGBE_HICR_EN              0x01  /* Enable bit - RO */
 917 /* Driver sets this bit when done to put command in RAM */
 918 #define IXGBE_HICR_C               0x02
 919 #define IXGBE_HICR_SV              0x04  /* Status Validity */
 920 #define IXGBE_HICR_FW_RESET_ENABLE 0x40
 921 #define IXGBE_HICR_FW_RESET        0x80
 922
 923 /* PCI-E registers */
 924 #define IXGBE_GCR       0x11000
 925 #define IXGBE_GTV       0x11004
 926 #define IXGBE_FUNCTAG   0x11008
 927 #define IXGBE_GLT       0x1100C
 928 #define IXGBE_GSCL_1    0x11010
 929 #define IXGBE_GSCL_2    0x11014
 930 #define IXGBE_GSCL_3    0x11018
 931 #define IXGBE_GSCL_4    0x1101C
 932 #define IXGBE_GSCN_0    0x11020
 933 #define IXGBE_GSCN_1    0x11024
 934 #define IXGBE_GSCN_2    0x11028
 935 #define IXGBE_GSCN_3    0x1102C
 936 #define IXGBE_FACTPS_8259X      0x10150
 937 #define IXGBE_FACTPS_X540       IXGBE_FACTPS_8259X
 938 #define IXGBE_FACTPS_X550       IXGBE_FACTPS_8259X
 939 #define IXGBE_FACTPS_X550EM_x   IXGBE_FACTPS_8259X
 940 #define IXGBE_FACTPS_X550EM_a   0x15FEC
 941 #define IXGBE_FACTPS(_hw)       IXGBE_BY_MAC((_hw), FACTPS)
 942
 943 #define IXGBE_PCIEANACTL  0x11040
 944 #define IXGBE_SWSM_8259X        0x10140
 945 #define IXGBE_SWSM_X540         IXGBE_SWSM_8259X
 946 #define IXGBE_SWSM_X550         IXGBE_SWSM_8259X
 947 #define IXGBE_SWSM_X550EM_x     IXGBE_SWSM_8259X
 948 #define IXGBE_SWSM_X550EM_a     0x15F70
 949 #define IXGBE_SWSM(_hw)         IXGBE_BY_MAC((_hw), SWSM)
 950 #define IXGBE_FWSM_8259X        0x10148
 951 #define IXGBE_FWSM_X540         IXGBE_FWSM_8259X
 952 #define IXGBE_FWSM_X550         IXGBE_FWSM_8259X
 953 #define IXGBE_FWSM_X550EM_x     IXGBE_FWSM_8259X
 954 #define IXGBE_FWSM_X550EM_a     0x15F74
 955 #define IXGBE_FWSM(_hw)         IXGBE_BY_MAC((_hw), FWSM)
 956 #define IXGBE_GSSR      0x10160
 957 #define IXGBE_MREVID    0x11064
 958 #define IXGBE_DCA_ID    0x11070
 959 #define IXGBE_DCA_CTRL  0x11074
 960 #define IXGBE_SWFW_SYNC_8259X           IXGBE_GSSR
 961 #define IXGBE_SWFW_SYNC_X540            IXGBE_SWFW_SYNC_8259X
 962 #define IXGBE_SWFW_SYNC_X550            IXGBE_SWFW_SYNC_8259X
 963 #define IXGBE_SWFW_SYNC_X550EM_x        IXGBE_SWFW_SYNC_8259X
 964 #define IXGBE_SWFW_SYNC_X550EM_a        0x15F78
 965 #define IXGBE_SWFW_SYNC(_hw)            IXGBE_BY_MAC((_hw), SWFW_SYNC)
 966
 967 /* PCIe registers 82599-specific */
 968 #define IXGBE_GCR_EXT           0x11050
 969 #define IXGBE_GSCL_5_82599      0x11030
 970 #define IXGBE_GSCL_6_82599      0x11034
 971 #define IXGBE_GSCL_7_82599      0x11038
 972 #define IXGBE_GSCL_8_82599      0x1103C
 973 #define IXGBE_PHYADR_82599      0x11040
 974 #define IXGBE_PHYDAT_82599      0x11044
 975 #define IXGBE_PHYCTL_82599      0x11048
 976 #define IXGBE_PBACLR_82599      0x11068
 977
 978 #define IXGBE_CIAA_8259X        0x11088
 979 #define IXGBE_CIAA_X540         IXGBE_CIAA_8259X
 980 #define IXGBE_CIAA_X550         0x11508
 981 #define IXGBE_CIAA_X550EM_x     IXGBE_CIAA_X550
 982 #define IXGBE_CIAA_X550EM_a     IXGBE_CIAA_X550
 983 #define IXGBE_CIAA(_hw)         IXGBE_BY_MAC((_hw), CIAA)
 984
 985 #define IXGBE_CIAD_8259X        0x1108C
 986 #define IXGBE_CIAD_X540         IXGBE_CIAD_8259X
 987 #define IXGBE_CIAD_X550         0x11510
 988 #define IXGBE_CIAD_X550EM_x     IXGBE_CIAD_X550
 989 #define IXGBE_CIAD_X550EM_a     IXGBE_CIAD_X550
 990 #define IXGBE_CIAD(_hw)         IXGBE_BY_MAC((_hw), CIAD)
 991
 992 #define IXGBE_PICAUSE           0x110B0
 993 #define IXGBE_PIENA             0x110B8
 994 #define IXGBE_CDQ_MBR_82599     0x110B4
 995 #define IXGBE_PCIESPARE         0x110BC
 996 #define IXGBE_MISC_REG_82599    0x110F0
 997 #define IXGBE_ECC_CTRL_0_82599  0x11100
 998 #define IXGBE_ECC_CTRL_1_82599  0x11104
 999 #define IXGBE_ECC_STATUS_82599  0x110E0
1000 #define IXGBE_BAR_CTRL_82599    0x110F4
1001
1002 /* PCI Express Control */
1003 #define IXGBE_GCR_CMPL_TMOUT_MASK       0x0000F000
1004 #define IXGBE_GCR_CMPL_TMOUT_10ms       0x00001000
1005 #define IXGBE_GCR_CMPL_TMOUT_RESEND     0x00010000
1006 #define IXGBE_GCR_CAP_VER2              0x00040000
1007
1008 #define IXGBE_GCR_EXT_MSIX_EN           0x80000000
1009 #define IXGBE_GCR_EXT_BUFFERS_CLEAR     0x40000000
1010 #define IXGBE_GCR_EXT_VT_MODE_16        0x00000001
1011 #define IXGBE_GCR_EXT_VT_MODE_32        0x00000002
1012 #define IXGBE_GCR_EXT_VT_MODE_64        0x00000003
1013 #define IXGBE_GCR_EXT_SRIOV             (IXGBE_GCR_EXT_MSIX_EN | \
1014                                          IXGBE_GCR_EXT_VT_MODE_64)
1015
1016 /* Time Sync Registers */
1017 #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
1018 #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
1019 #define IXGBE_RXSTMPL    0x051E8 /* Rx timestamp Low - RO */
1020 #define IXGBE_RXSTMPH    0x051A4 /* Rx timestamp High - RO */
1021 #define IXGBE_RXSATRL    0x051A0 /* Rx timestamp attribute low - RO */
1022 #define IXGBE_RXSATRH    0x051A8 /* Rx timestamp attribute high - RO */
1023 #define IXGBE_RXMTRL     0x05120 /* RX message type register low - RW */
1024 #define IXGBE_TXSTMPL    0x08C04 /* Tx timestamp value Low - RO */
1025 #define IXGBE_TXSTMPH    0x08C08 /* Tx timestamp value High - RO */
1026 #define IXGBE_SYSTIML    0x08C0C /* System time register Low - RO */
1027 #define IXGBE_SYSTIMH    0x08C10 /* System time register High - RO */
1028 #define IXGBE_SYSTIMR    0x08C58 /* System time register Residue - RO */
1029 #define IXGBE_TIMINCA    0x08C14 /* Increment attributes register - RW */
1030 #define IXGBE_TIMADJL    0x08C18 /* Time Adjustment Offset register Low - RW */
1031 #define IXGBE_TIMADJH    0x08C1C /* Time Adjustment Offset register High - RW */
1032 #define IXGBE_TSAUXC     0x08C20 /* TimeSync Auxiliary Control register - RW */
1033 #define IXGBE_TRGTTIML0  0x08C24 /* Target Time Register 0 Low - RW */
1034 #define IXGBE_TRGTTIMH0  0x08C28 /* Target Time Register 0 High - RW */
1035 #define IXGBE_TRGTTIML1  0x08C2C /* Target Time Register 1 Low - RW */
1036 #define IXGBE_TRGTTIMH1  0x08C30 /* Target Time Register 1 High - RW */
1037 #define IXGBE_CLKTIML    0x08C34 /* Clock Out Time Register Low - RW */
1038 #define IXGBE_CLKTIMH    0x08C38 /* Clock Out Time Register High - RW */
1039 #define IXGBE_FREQOUT0   0x08C34 /* Frequency Out 0 Control register - RW */
1040 #define IXGBE_FREQOUT1   0x08C38 /* Frequency Out 1 Control register - RW */
1041 #define IXGBE_AUXSTMPL0  0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
1042 #define IXGBE_AUXSTMPH0  0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
1043 #define IXGBE_AUXSTMPL1  0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
1044 #define IXGBE_AUXSTMPH1  0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
1045 #define IXGBE_TSIM       0x08C68 /* TimeSync Interrupt Mask Register - RW */
1046
1047 /* Diagnostic Registers */
1048 #define IXGBE_RDSTATCTL   0x02C20
1049 #define IXGBE_RDSTAT(_i)  (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
1050 #define IXGBE_RDHMPN      0x02F08
1051 #define IXGBE_RIC_DW(_i)  (0x02F10 + ((_i) * 4))
1052 #define IXGBE_RDPROBE     0x02F20
1053 #define IXGBE_RDMAM       0x02F30
1054 #define IXGBE_RDMAD       0x02F34
1055 #define IXGBE_TDSTATCTL   0x07C20
1056 #define IXGBE_TDSTAT(_i)  (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
1057 #define IXGBE_TDHMPN      0x07F08
1058 #define IXGBE_TDHMPN2     0x082FC
1059 #define IXGBE_TXDESCIC    0x082CC
1060 #define IXGBE_TIC_DW(_i)  (0x07F10 + ((_i) * 4))
1061 #define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
1062 #define IXGBE_TDPROBE     0x07F20
1063 #define IXGBE_TXBUFCTRL   0x0C600
1064 #define IXGBE_TXBUFDATA(_i) (0x0C610 + ((_i) * 4)) /* 4 of these (0-3) */
1065 #define IXGBE_RXBUFCTRL   0x03600
1066 #define IXGBE_RXBUFDATA(_i) (0x03610 + ((_i) * 4)) /* 4 of these (0-3) */
1067 #define IXGBE_PCIE_DIAG(_i)     (0x11090 + ((_i) * 4)) /* 8 of these */
1068 #define IXGBE_RFVAL     0x050A4
1069 #define IXGBE_MDFTC1    0x042B8
1070 #define IXGBE_MDFTC2    0x042C0
1071 #define IXGBE_MDFTFIFO1 0x042C4
1072 #define IXGBE_MDFTFIFO2 0x042C8
1073 #define IXGBE_MDFTS     0x042CC
1074 #define IXGBE_RXDATAWRPTR(_i)   (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
1075 #define IXGBE_RXDESCWRPTR(_i)   (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
1076 #define IXGBE_RXDATARDPTR(_i)   (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
1077 #define IXGBE_RXDESCRDPTR(_i)   (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
1078 #define IXGBE_TXDATAWRPTR(_i)   (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
1079 #define IXGBE_TXDESCWRPTR(_i)   (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
1080 #define IXGBE_TXDATARDPTR(_i)   (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
1081 #define IXGBE_TXDESCRDPTR(_i)   (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
1082 #define IXGBE_PCIEECCCTL 0x1106C
1083 #define IXGBE_RXWRPTR(_i)       (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/
1084 #define IXGBE_RXUSED(_i)        (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/
1085 #define IXGBE_RXRDPTR(_i)       (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/
1086 #define IXGBE_RXRDWRPTR(_i)     (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/
1087 #define IXGBE_TXWRPTR(_i)       (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/
1088 #define IXGBE_TXUSED(_i)        (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/
1089 #define IXGBE_TXRDPTR(_i)       (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/
1090 #define IXGBE_TXRDWRPTR(_i)     (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/
1091 #define IXGBE_PCIEECCCTL0 0x11100
1092 #define IXGBE_PCIEECCCTL1 0x11104
1093 #define IXGBE_RXDBUECC  0x03F70
1094 #define IXGBE_TXDBUECC  0x0CF70
1095 #define IXGBE_RXDBUEST 0x03F74
1096 #define IXGBE_TXDBUEST 0x0CF74
1097 #define IXGBE_PBTXECC   0x0C300
1098 #define IXGBE_PBRXECC   0x03300
1099 #define IXGBE_GHECCR    0x110B0
1100
1101 /* MAC Registers */
1102 #define IXGBE_PCS1GCFIG 0x04200
1103 #define IXGBE_PCS1GLCTL 0x04208
1104 #define IXGBE_PCS1GLSTA 0x0420C
1105 #define IXGBE_PCS1GDBG0 0x04210
1106 #define IXGBE_PCS1GDBG1 0x04214
1107 #define IXGBE_PCS1GANA  0x04218
1108 #define IXGBE_PCS1GANLP 0x0421C
1109 #define IXGBE_PCS1GANNP 0x04220
1110 #define IXGBE_PCS1GANLPNP 0x04224
1111 #define IXGBE_HLREG0    0x04240
1112 #define IXGBE_HLREG1    0x04244
1113 #define IXGBE_PAP       0x04248
1114 #define IXGBE_MACA      0x0424C
1115 #define IXGBE_APAE      0x04250
1116 #define IXGBE_ARD       0x04254
1117 #define IXGBE_AIS       0x04258
1118 #define IXGBE_MSCA      0x0425C
1119 #define IXGBE_MSRWD     0x04260
1120 #define IXGBE_MLADD     0x04264
1121 #define IXGBE_MHADD     0x04268
1122 #define IXGBE_MAXFRS    0x04268
1123 #define IXGBE_TREG      0x0426C
1124 #define IXGBE_PCSS1     0x04288
1125 #define IXGBE_PCSS2     0x0428C
1126 #define IXGBE_XPCSS     0x04290
1127 #define IXGBE_MFLCN     0x04294
1128 #define IXGBE_SERDESC   0x04298
1129 #define IXGBE_MAC_SGMII_BUSY 0x04298
1130 #define IXGBE_MACS      0x0429C
1131 #define IXGBE_AUTOC     0x042A0
1132 #define IXGBE_LINKS     0x042A4
1133 #define IXGBE_LINKS2    0x04324
1134 #define IXGBE_AUTOC2    0x042A8
1135 #define IXGBE_AUTOC3    0x042AC
1136 #define IXGBE_ANLP1     0x042B0
1137 #define IXGBE_ANLP2     0x042B4
1138 #define IXGBE_MACC      0x04330
1139 #define IXGBE_ATLASCTL  0x04800
1140 #define IXGBE_MMNGC     0x042D0
1141 #define IXGBE_ANLPNP1   0x042D4
1142 #define IXGBE_ANLPNP2   0x042D8
1143 #define IXGBE_KRPCSFC   0x042E0
1144 #define IXGBE_KRPCSS    0x042E4
1145 #define IXGBE_FECS1     0x042E8
1146 #define IXGBE_FECS2     0x042EC
1147 #define IXGBE_SMADARCTL 0x14F10
1148 #define IXGBE_MPVC      0x04318
1149 #define IXGBE_SGMIIC    0x04314
1150
1151 /* Statistics Registers */
1152 #define IXGBE_RXNFGPC      0x041B0
1153 #define IXGBE_RXNFGBCL     0x041B4
1154 #define IXGBE_RXNFGBCH     0x041B8
1155 #define IXGBE_RXDGPC       0x02F50
1156 #define IXGBE_RXDGBCL      0x02F54
1157 #define IXGBE_RXDGBCH      0x02F58
1158 #define IXGBE_RXDDGPC      0x02F5C
1159 #define IXGBE_RXDDGBCL     0x02F60
1160 #define IXGBE_RXDDGBCH     0x02F64
1161 #define IXGBE_RXLPBKGPC    0x02F68
1162 #define IXGBE_RXLPBKGBCL   0x02F6C
1163 #define IXGBE_RXLPBKGBCH   0x02F70
1164 #define IXGBE_RXDLPBKGPC   0x02F74
1165 #define IXGBE_RXDLPBKGBCL  0x02F78
1166 #define IXGBE_RXDLPBKGBCH  0x02F7C
1167 #define IXGBE_TXDGPC       0x087A0
1168 #define IXGBE_TXDGBCL      0x087A4
1169 #define IXGBE_TXDGBCH      0x087A8
1170
1171 #define IXGBE_RXDSTATCTRL 0x02F40
1172
1173 /* Copper Pond 2 link timeout */
1174 #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
1175
1176 /* Omer CORECTL */
1177 #define IXGBE_CORECTL           0x014F00
1178 /* BARCTRL */
1179 #define IXGBE_BARCTRL               0x110F4
1180 #define IXGBE_BARCTRL_FLSIZE        0x0700
1181 #define IXGBE_BARCTRL_FLSIZE_SHIFT  8
1182 #define IXGBE_BARCTRL_CSRSIZE       0x2000
1183
1184 /* RSCCTL Bit Masks */
1185 #define IXGBE_RSCCTL_RSCEN          0x01
1186 #define IXGBE_RSCCTL_MAXDESC_1      0x00
1187 #define IXGBE_RSCCTL_MAXDESC_4      0x04
1188 #define IXGBE_RSCCTL_MAXDESC_8      0x08
1189 #define IXGBE_RSCCTL_MAXDESC_16     0x0C
1190
1191 /* RSCDBU Bit Masks */
1192 #define IXGBE_RSCDBU_RSCSMALDIS_MASK    0x0000007F
1193 #define IXGBE_RSCDBU_RSCACKDIS          0x00000080
1194
1195 /* RDRXCTL Bit Masks */
1196 #define IXGBE_RDRXCTL_RDMTS_1_2     0x00000000 /* Rx Desc Min Threshold Size */
1197 #define IXGBE_RDRXCTL_CRCSTRIP      0x00000002 /* CRC Strip */
1198 #define IXGBE_RDRXCTL_PSP           0x00000004 /* Pad small packet */
1199 #define IXGBE_RDRXCTL_MVMEN         0x00000020
1200 #define IXGBE_RDRXCTL_DMAIDONE      0x00000008 /* DMA init cycle done */
1201 #define IXGBE_RDRXCTL_AGGDIS        0x00010000 /* Aggregation disable */
1202 #define IXGBE_RDRXCTL_RSCFRSTSIZE   0x003E0000 /* RSC First packet size */
1203 #define IXGBE_RDRXCTL_RSCLLIDIS     0x00800000 /* Disable RSC compl on LLI */
1204 #define IXGBE_RDRXCTL_RSCACKC       0x02000000 /* must set 1 when RSC enabled */
1205 #define IXGBE_RDRXCTL_FCOE_WRFIX    0x04000000 /* must set 1 when RSC enabled */
1206 #define IXGBE_RDRXCTL_MBINTEN       0x10000000
1207 #define IXGBE_RDRXCTL_MDP_EN        0x20000000
1208
1209 /* RQTC Bit Masks and Shifts */
1210 #define IXGBE_RQTC_SHIFT_TC(_i)     ((_i) * 4)
1211 #define IXGBE_RQTC_TC0_MASK         (0x7 << 0)
1212 #define IXGBE_RQTC_TC1_MASK         (0x7 << 4)
1213 #define IXGBE_RQTC_TC2_MASK         (0x7 << 8)
1214 #define IXGBE_RQTC_TC3_MASK         (0x7 << 12)
1215 #define IXGBE_RQTC_TC4_MASK         (0x7 << 16)
1216 #define IXGBE_RQTC_TC5_MASK         (0x7 << 20)
1217 #define IXGBE_RQTC_TC6_MASK         (0x7 << 24)
1218 #define IXGBE_RQTC_TC7_MASK         (0x7 << 28)
1219
1220 /* PSRTYPE.RQPL Bit masks and shift */
1221 #define IXGBE_PSRTYPE_RQPL_MASK     0x7
1222 #define IXGBE_PSRTYPE_RQPL_SHIFT    29
1223
1224 /* CTRL Bit Masks */
1225 #define IXGBE_CTRL_GIO_DIS      0x00000004 /* Global IO Master Disable bit */
1226 #define IXGBE_CTRL_LNK_RST      0x00000008 /* Link Reset. Resets everything. */
1227 #define IXGBE_CTRL_RST          0x04000000 /* Reset (SW) */
1228 #define IXGBE_CTRL_RST_MASK     (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
1229
1230 /* FACTPS */
1231 #define IXGBE_FACTPS_MNGCG      0x20000000 /* Manageblility Clock Gated */
1232 #define IXGBE_FACTPS_LFS        0x40000000 /* LAN Function Select */
1233
1234 /* MHADD Bit Masks */
1235 #define IXGBE_MHADD_MFS_MASK    0xFFFF0000
1236 #define IXGBE_MHADD_MFS_SHIFT   16
1237
1238 /* Extended Device Control */
1239 #define IXGBE_CTRL_EXT_PFRSTD   0x00004000 /* Physical Function Reset Done */
1240 #define IXGBE_CTRL_EXT_NS_DIS   0x00010000 /* No Snoop disable */
1241 #define IXGBE_CTRL_EXT_RO_DIS   0x00020000 /* Relaxed Ordering disable */
1242 #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1243
1244 /* Direct Cache Access (DCA) definitions */
1245 #define IXGBE_DCA_CTRL_DCA_ENABLE  0x00000000 /* DCA Enable */
1246 #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
1247
1248 #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
1249 #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
1250
1251 #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
1252 #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599  0xFF000000 /* Rx CPUID Mask */
1253 #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
1254 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */
1255 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */
1256 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */
1257 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */
1258 #define IXGBE_DCA_RXCTRL_DATA_WRO_EN BIT(13) /* Rx wr data Relax Order */
1259 #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN BIT(15) /* Rx wr header RO */
1260
1261 #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
1262 #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599  0xFF000000 /* Tx CPUID Mask */
1263 #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
1264 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */
1265 #define IXGBE_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */
1266 #define IXGBE_DCA_TXCTRL_DESC_WRO_EN BIT(11) /* Tx Desc writeback RO bit */
1267 #define IXGBE_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */
1268 #define IXGBE_DCA_MAX_QUEUES_82598   16 /* DCA regs only on 16 queues */
1269
1270 /* MSCA Bit Masks */
1271 #define IXGBE_MSCA_NP_ADDR_MASK      0x0000FFFF /* MDI Address (new protocol) */
1272 #define IXGBE_MSCA_NP_ADDR_SHIFT     0
1273 #define IXGBE_MSCA_DEV_TYPE_MASK     0x001F0000 /* Device Type (new protocol) */
1274 #define IXGBE_MSCA_DEV_TYPE_SHIFT    16 /* Register Address (old protocol */
1275 #define IXGBE_MSCA_PHY_ADDR_MASK     0x03E00000 /* PHY Address mask */
1276 #define IXGBE_MSCA_PHY_ADDR_SHIFT    21 /* PHY Address shift*/
1277 #define IXGBE_MSCA_OP_CODE_MASK      0x0C000000 /* OP CODE mask */
1278 #define IXGBE_MSCA_OP_CODE_SHIFT     26 /* OP CODE shift */
1279 #define IXGBE_MSCA_ADDR_CYCLE        0x00000000 /* OP CODE 00 (addr cycle) */
1280 #define IXGBE_MSCA_WRITE             0x04000000 /* OP CODE 01 (write) */
1281 #define IXGBE_MSCA_READ              0x0C000000 /* OP CODE 11 (read) */
1282 #define IXGBE_MSCA_READ_AUTOINC      0x08000000 /* OP CODE 10 (read, auto inc)*/
1283 #define IXGBE_MSCA_ST_CODE_MASK      0x30000000 /* ST Code mask */
1284 #define IXGBE_MSCA_ST_CODE_SHIFT     28 /* ST Code shift */
1285 #define IXGBE_MSCA_NEW_PROTOCOL      0x00000000 /* ST CODE 00 (new protocol) */
1286 #define IXGBE_MSCA_OLD_PROTOCOL      0x10000000 /* ST CODE 01 (old protocol) */
1287 #define IXGBE_MSCA_MDI_COMMAND       0x40000000 /* Initiate MDI command */
1288 #define IXGBE_MSCA_MDI_IN_PROG_EN    0x80000000 /* MDI in progress enable */
1289
1290 /* MSRWD bit masks */
1291 #define IXGBE_MSRWD_WRITE_DATA_MASK     0x0000FFFF
1292 #define IXGBE_MSRWD_WRITE_DATA_SHIFT    0
1293 #define IXGBE_MSRWD_READ_DATA_MASK      0xFFFF0000
1294 #define IXGBE_MSRWD_READ_DATA_SHIFT     16
1295
1296 /* Atlas registers */
1297 #define IXGBE_ATLAS_PDN_LPBK    0x24
1298 #define IXGBE_ATLAS_PDN_10G     0xB
1299 #define IXGBE_ATLAS_PDN_1G      0xC
1300 #define IXGBE_ATLAS_PDN_AN      0xD
1301
1302 /* Atlas bit masks */
1303 #define IXGBE_ATLASCTL_WRITE_CMD        0x00010000
1304 #define IXGBE_ATLAS_PDN_TX_REG_EN       0x10
1305 #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL   0xF0
1306 #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL    0xF0
1307 #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL    0xF0
1308
1309 /* Omer bit masks */
1310 #define IXGBE_CORECTL_WRITE_CMD         0x00010000
1311
1312 /* MDIO definitions */
1313
1314 #define IXGBE_MDIO_ZERO_DEV_TYPE                0x0
1315 #define IXGBE_MDIO_PMA_PMD_DEV_TYPE             0x1
1316 #define IXGBE_MDIO_PCS_DEV_TYPE         0x3
1317 #define IXGBE_MDIO_PHY_XS_DEV_TYPE              0x4
1318 #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE            0x7
1319 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE   0x1E   /* Device 30 */
1320 #define IXGBE_TWINAX_DEV                        1
1321
1322 #define IXGBE_MDIO_COMMAND_TIMEOUT     100 /* PHY Timeout for 1 GB mode */
1323
1324 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL      0x0    /* VS1 Control Reg */
1325 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS       0x1    /* VS1 Status Reg */
1326 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS  0x0008 /* 1 = Link Up */
1327 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
1328 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED    0x0018
1329 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED     0x0010
1330
1331 #define IXGBE_MDIO_AUTO_NEG_CONTROL     0x0 /* AUTO_NEG Control Reg */
1332 #define IXGBE_MDIO_AUTO_NEG_STATUS      0x1 /* AUTO_NEG Status Reg */
1333 #define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT 0xC800 /* AUTO_NEG Vendor Status Reg */
1334 #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM  0xCC00 /* AUTO_NEG Vendor TX Reg */
1335 #define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01 /* AUTO_NEG Vendor Tx Reg */
1336 #define IXGBE_MDIO_AUTO_NEG_VEN_LSC     0x1 /* AUTO_NEG Vendor Tx LSC */
1337 #define IXGBE_MDIO_AUTO_NEG_ADVT        0x10 /* AUTO_NEG Advt Reg */
1338 #define IXGBE_MDIO_AUTO_NEG_LP          0x13 /* AUTO_NEG LP Status Reg */
1339 #define IXGBE_MDIO_AUTO_NEG_EEE_ADVT    0x3C /* AUTO_NEG EEE Advt Reg */
1340
1341 #define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE        0x0800 /* Set low power mode */
1342 #define IXGBE_AUTO_NEG_LP_STATUS        0xE820 /* AUTO NEG Rx LP Status Reg */
1343 #define IXGBE_AUTO_NEG_LP_1000BASE_CAP  0x8000 /* AUTO NEG Rx LP 1000BaseT */
1344 #define IXGBE_MDIO_TX_VENDOR_ALARMS_3   0xCC02 /* Vendor Alarms 3 Reg */
1345 #define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK 0x3 /* PHY Reset Complete Mask */
1346 #define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479 /* Global Resv Provisioning 10 Reg */
1347 #define IXGBE_MDIO_POWER_UP_STALL       0x8000 /* Power Up Stall */
1348 #define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK     0xFF00 /* int std mask */
1349 #define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG     0xFC00 /* chip std int flag */
1350 #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK     0xFF01 /* int chip-wide mask */
1351 #define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG     0xFC01 /* int chip-wide mask */
1352 #define IXGBE_MDIO_GLOBAL_ALARM_1               0xCC00 /* Global alarm 1 */
1353 #define IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT       0x0010 /* device fault */
1354 #define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL     0x4000 /* high temp failure */
1355 #define IXGBE_MDIO_GLOBAL_FAULT_MSG             0xC850 /* global fault msg */
1356 #define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP      0x8007 /* high temp failure */
1357 #define IXGBE_MDIO_GLOBAL_INT_MASK              0xD400 /* Global int mask */
1358 /* autoneg vendor alarm int enable */
1359 #define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN     0x1000
1360 #define IXGBE_MDIO_GLOBAL_ALARM_1_INT           0x4 /* int in Global alarm 1 */
1361 #define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN        0x1 /* vendor alarm int enable */
1362 #define IXGBE_MDIO_GLOBAL_STD_ALM2_INT          0x200 /* vendor alarm2 int mask */
1363 #define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN        0x4000 /* int high temp enable */
1364 #define IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN      0x0010 /*int dev fault enable */
1365
1366 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
1367 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
1368 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Stat Reg */
1369 #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK     0xD401 /* PHY TX Vendor LASI */
1370 #define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN       0x1 /* PHY TX Vendor LASI enable */
1371 #define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR      0x9 /* Standard Tx Dis Reg */
1372 #define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE        0x0001 /* PMD Global Tx Dis */
1373
1374 /* MII clause 22/28 definitions */
1375 #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
1376 #define IXGBE_MII_AUTONEG_XNP_TX_REG             0x17   /* 1G XNP Transmit */
1377 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX      0x4000 /* full duplex, bit:14*/
1378 #define IXGBE_MII_1GBASE_T_ADVERTISE             0x8000 /* full duplex, bit:15*/
1379 #define IXGBE_MII_AUTONEG_REG                    0x0
1380
1381 #define IXGBE_PHY_REVISION_MASK        0xFFFFFFF0
1382 #define IXGBE_MAX_PHY_ADDR             32
1383
1384 /* PHY IDs*/
1385 #define TN1010_PHY_ID    0x00A19410
1386 #define TNX_FW_REV       0xB
1387 #define X540_PHY_ID      0x01540200
1388 #define X550_PHY_ID      0x01540220
1389 #define X557_PHY_ID      0x01540240
1390 #define QT2022_PHY_ID    0x0043A400
1391 #define ATH_PHY_ID       0x03429050
1392 #define AQ_FW_REV        0x20
1393
1394 /* PHY Types */
1395 #define IXGBE_M88E1145_E_PHY_ID  0x01410CD0
1396
1397 /* Special PHY Init Routine */
1398 #define IXGBE_PHY_INIT_OFFSET_NL 0x002B
1399 #define IXGBE_PHY_INIT_END_NL    0xFFFF
1400 #define IXGBE_CONTROL_MASK_NL    0xF000
1401 #define IXGBE_DATA_MASK_NL       0x0FFF
1402 #define IXGBE_CONTROL_SHIFT_NL   12
1403 #define IXGBE_DELAY_NL           0
1404 #define IXGBE_DATA_NL            1
1405 #define IXGBE_CONTROL_NL         0x000F
1406 #define IXGBE_CONTROL_EOL_NL     0x0FFF
1407 #define IXGBE_CONTROL_SOL_NL     0x0000
1408
1409 /* General purpose Interrupt Enable */
1410 #define IXGBE_SDP0_GPIEN_8259X          0x00000001 /* SDP0 */
1411 #define IXGBE_SDP1_GPIEN_8259X          0x00000002 /* SDP1 */
1412 #define IXGBE_SDP2_GPIEN_8259X          0x00000004 /* SDP2 */
1413 #define IXGBE_SDP0_GPIEN_X540           0x00000002 /* SDP0 on X540 and X550 */
1414 #define IXGBE_SDP1_GPIEN_X540           0x00000004 /* SDP1 on X540 and X550 */
1415 #define IXGBE_SDP2_GPIEN_X540           0x00000008 /* SDP2 on X540 and X550 */
1416 #define IXGBE_SDP0_GPIEN_X550           IXGBE_SDP0_GPIEN_X540
1417 #define IXGBE_SDP1_GPIEN_X550           IXGBE_SDP1_GPIEN_X540
1418 #define IXGBE_SDP2_GPIEN_X550           IXGBE_SDP2_GPIEN_X540
1419 #define IXGBE_SDP0_GPIEN_X550EM_x       IXGBE_SDP0_GPIEN_X540
1420 #define IXGBE_SDP1_GPIEN_X550EM_x       IXGBE_SDP1_GPIEN_X540
1421 #define IXGBE_SDP2_GPIEN_X550EM_x       IXGBE_SDP2_GPIEN_X540
1422 #define IXGBE_SDP0_GPIEN_X550EM_a       IXGBE_SDP0_GPIEN_X540
1423 #define IXGBE_SDP1_GPIEN_X550EM_a       IXGBE_SDP1_GPIEN_X540
1424 #define IXGBE_SDP2_GPIEN_X550EM_a       IXGBE_SDP2_GPIEN_X540
1425 #define IXGBE_SDP0_GPIEN(_hw)           IXGBE_BY_MAC((_hw), SDP0_GPIEN)
1426 #define IXGBE_SDP1_GPIEN(_hw)           IXGBE_BY_MAC((_hw), SDP1_GPIEN)
1427 #define IXGBE_SDP2_GPIEN(_hw)           IXGBE_BY_MAC((_hw), SDP2_GPIEN)
1428
1429 #define IXGBE_GPIE_MSIX_MODE     0x00000010 /* MSI-X mode */
1430 #define IXGBE_GPIE_OCD           0x00000020 /* Other Clear Disable */
1431 #define IXGBE_GPIE_EIMEN         0x00000040 /* Immediate Interrupt Enable */
1432 #define IXGBE_GPIE_EIAME         0x40000000
1433 #define IXGBE_GPIE_PBA_SUPPORT   0x80000000
1434 #define IXGBE_GPIE_RSC_DELAY_SHIFT 11
1435 #define IXGBE_GPIE_VTMODE_MASK   0x0000C000 /* VT Mode Mask */
1436 #define IXGBE_GPIE_VTMODE_16     0x00004000 /* 16 VFs 8 queues per VF */
1437 #define IXGBE_GPIE_VTMODE_32     0x00008000 /* 32 VFs 4 queues per VF */
1438 #define IXGBE_GPIE_VTMODE_64     0x0000C000 /* 64 VFs 2 queues per VF */
1439
1440 /* Packet Buffer Initialization */
1441 #define IXGBE_TXPBSIZE_20KB     0x00005000 /* 20KB Packet Buffer */
1442 #define IXGBE_TXPBSIZE_40KB     0x0000A000 /* 40KB Packet Buffer */
1443 #define IXGBE_RXPBSIZE_48KB     0x0000C000 /* 48KB Packet Buffer */
1444 #define IXGBE_RXPBSIZE_64KB     0x00010000 /* 64KB Packet Buffer */
1445 #define IXGBE_RXPBSIZE_80KB     0x00014000 /* 80KB Packet Buffer */
1446 #define IXGBE_RXPBSIZE_128KB    0x00020000 /* 128KB Packet Buffer */
1447 #define IXGBE_RXPBSIZE_MAX      0x00080000 /* 512KB Packet Buffer*/
1448 #define IXGBE_TXPBSIZE_MAX      0x00028000 /* 160KB Packet Buffer*/
1449
1450 #define IXGBE_TXPKT_SIZE_MAX    0xA        /* Max Tx Packet size  */
1451 #define IXGBE_MAX_PB            8
1452
1453 /* Packet buffer allocation strategies */
1454 enum {
1455         PBA_STRATEGY_EQUAL      = 0,    /* Distribute PB space equally */
1456 #define PBA_STRATEGY_EQUAL      PBA_STRATEGY_EQUAL
1457         PBA_STRATEGY_WEIGHTED   = 1,    /* Weight front half of TCs */
1458 #define PBA_STRATEGY_WEIGHTED   PBA_STRATEGY_WEIGHTED
1459 };
1460
1461 /* Transmit Flow Control status */
1462 #define IXGBE_TFCS_TXOFF         0x00000001
1463 #define IXGBE_TFCS_TXOFF0        0x00000100
1464 #define IXGBE_TFCS_TXOFF1        0x00000200
1465 #define IXGBE_TFCS_TXOFF2        0x00000400
1466 #define IXGBE_TFCS_TXOFF3        0x00000800
1467 #define IXGBE_TFCS_TXOFF4        0x00001000
1468 #define IXGBE_TFCS_TXOFF5        0x00002000
1469 #define IXGBE_TFCS_TXOFF6        0x00004000
1470 #define IXGBE_TFCS_TXOFF7        0x00008000
1471
1472 /* TCP Timer */
1473 #define IXGBE_TCPTIMER_KS            0x00000100
1474 #define IXGBE_TCPTIMER_COUNT_ENABLE  0x00000200
1475 #define IXGBE_TCPTIMER_COUNT_FINISH  0x00000400
1476 #define IXGBE_TCPTIMER_LOOP          0x00000800
1477 #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
1478
1479 /* HLREG0 Bit Masks */
1480 #define IXGBE_HLREG0_TXCRCEN      0x00000001   /* bit  0 */
1481 #define IXGBE_HLREG0_RXCRCSTRP    0x00000002   /* bit  1 */
1482 #define IXGBE_HLREG0_JUMBOEN      0x00000004   /* bit  2 */
1483 #define IXGBE_HLREG0_TXPADEN      0x00000400   /* bit 10 */
1484 #define IXGBE_HLREG0_TXPAUSEEN    0x00001000   /* bit 12 */
1485 #define IXGBE_HLREG0_RXPAUSEEN    0x00004000   /* bit 14 */
1486 #define IXGBE_HLREG0_LPBK         0x00008000   /* bit 15 */
1487 #define IXGBE_HLREG0_MDCSPD       0x00010000   /* bit 16 */
1488 #define IXGBE_HLREG0_CONTMDC      0x00020000   /* bit 17 */
1489 #define IXGBE_HLREG0_CTRLFLTR     0x00040000   /* bit 18 */
1490 #define IXGBE_HLREG0_PREPEND      0x00F00000   /* bits 20-23 */
1491 #define IXGBE_HLREG0_PRIPAUSEEN   0x01000000   /* bit 24 */
1492 #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000   /* bits 25-26 */
1493 #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000   /* bit 27 */
1494 #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000   /* bit 28 */
1495
1496 /* VMD_CTL bitmasks */
1497 #define IXGBE_VMD_CTL_VMDQ_EN     0x00000001
1498 #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
1499
1500 /* VT_CTL bitmasks */
1501 #define IXGBE_VT_CTL_DIS_DEFPL  0x20000000 /* disable default pool */
1502 #define IXGBE_VT_CTL_REPLEN     0x40000000 /* replication enabled */
1503 #define IXGBE_VT_CTL_VT_ENABLE  0x00000001  /* Enable VT Mode */
1504 #define IXGBE_VT_CTL_POOL_SHIFT 7
1505 #define IXGBE_VT_CTL_POOL_MASK  (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
1506
1507 /* VMOLR bitmasks */
1508 #define IXGBE_VMOLR_AUPE        0x01000000 /* accept untagged packets */
1509 #define IXGBE_VMOLR_ROMPE       0x02000000 /* accept packets in MTA tbl */
1510 #define IXGBE_VMOLR_ROPE        0x04000000 /* accept packets in UC tbl */
1511 #define IXGBE_VMOLR_BAM         0x08000000 /* accept broadcast packets */
1512 #define IXGBE_VMOLR_MPE         0x10000000 /* multicast promiscuous */
1513
1514 /* VFRE bitmask */
1515 #define IXGBE_VFRE_ENABLE_ALL   0xFFFFFFFF
1516
1517 #define IXGBE_VF_INIT_TIMEOUT   200 /* Number of retries to clear RSTI */
1518
1519 /* RDHMPN and TDHMPN bitmasks */
1520 #define IXGBE_RDHMPN_RDICADDR       0x007FF800
1521 #define IXGBE_RDHMPN_RDICRDREQ      0x00800000
1522 #define IXGBE_RDHMPN_RDICADDR_SHIFT 11
1523 #define IXGBE_TDHMPN_TDICADDR       0x003FF800
1524 #define IXGBE_TDHMPN_TDICRDREQ      0x00800000
1525 #define IXGBE_TDHMPN_TDICADDR_SHIFT 11
1526
1527 #define IXGBE_RDMAM_MEM_SEL_SHIFT   13
1528 #define IXGBE_RDMAM_DWORD_SHIFT     9
1529 #define IXGBE_RDMAM_DESC_COMP_FIFO  1
1530 #define IXGBE_RDMAM_DFC_CMD_FIFO    2
1531 #define IXGBE_RDMAM_TCN_STATUS_RAM  4
1532 #define IXGBE_RDMAM_WB_COLL_FIFO    5
1533 #define IXGBE_RDMAM_QSC_CNT_RAM     6
1534 #define IXGBE_RDMAM_QSC_QUEUE_CNT   8
1535 #define IXGBE_RDMAM_QSC_QUEUE_RAM   0xA
1536 #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE     135
1537 #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT     4
1538 #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE      48
1539 #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT      7
1540 #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE    256
1541 #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT    9
1542 #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE      8
1543 #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT      4
1544 #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE       64
1545 #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT       4
1546 #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE     32
1547 #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT     4
1548 #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE     128
1549 #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT     8
1550
1551 #define IXGBE_TXDESCIC_READY        0x80000000
1552
1553 /* Receive Checksum Control */
1554 #define IXGBE_RXCSUM_IPPCSE     0x00001000   /* IP payload checksum enable */
1555 #define IXGBE_RXCSUM_PCSD       0x00002000   /* packet checksum disabled */
1556
1557 /* FCRTL Bit Masks */
1558 #define IXGBE_FCRTL_XONE        0x80000000  /* XON enable */
1559 #define IXGBE_FCRTH_FCEN        0x80000000  /* Packet buffer fc enable */
1560
1561 /* PAP bit masks*/
1562 #define IXGBE_PAP_TXPAUSECNT_MASK   0x0000FFFF /* Pause counter mask */
1563
1564 /* RMCS Bit Masks */
1565 #define IXGBE_RMCS_RRM          0x00000002 /* Receive Recycle Mode enable */
1566 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */
1567 #define IXGBE_RMCS_RAC          0x00000004
1568 #define IXGBE_RMCS_DFP          IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
1569 #define IXGBE_RMCS_TFCE_802_3X         0x00000008 /* Tx Priority FC ena */
1570 #define IXGBE_RMCS_TFCE_PRIORITY       0x00000010 /* Tx Priority FC ena */
1571 #define IXGBE_RMCS_ARBDIS       0x00000040 /* Arbitration disable bit */
1572
1573 /* FCCFG Bit Masks */
1574 #define IXGBE_FCCFG_TFCE_802_3X         0x00000008 /* Tx link FC enable */
1575 #define IXGBE_FCCFG_TFCE_PRIORITY       0x00000010 /* Tx priority FC enable */
1576
1577 /* Interrupt register bitmasks */
1578
1579 /* Extended Interrupt Cause Read */
1580 #define IXGBE_EICR_RTX_QUEUE    0x0000FFFF /* RTx Queue Interrupt */
1581 #define IXGBE_EICR_FLOW_DIR     0x00010000 /* FDir Exception */
1582 #define IXGBE_EICR_RX_MISS      0x00020000 /* Packet Buffer Overrun */
1583 #define IXGBE_EICR_PCI          0x00040000 /* PCI Exception */
1584 #define IXGBE_EICR_MAILBOX      0x00080000 /* VF to PF Mailbox Interrupt */
1585 #define IXGBE_EICR_LSC          0x00100000 /* Link Status Change */
1586 #define IXGBE_EICR_LINKSEC      0x00200000 /* PN Threshold */
1587 #define IXGBE_EICR_MNG          0x00400000 /* Manageability Event Interrupt */
1588 #define IXGBE_EICR_TS           0x00800000 /* Thermal Sensor Event */
1589 #define IXGBE_EICR_TIMESYNC     0x01000000 /* Timesync Event */
1590 #define IXGBE_EICR_GPI_SDP0_8259X       0x01000000 /* Gen Purpose INT on SDP0 */
1591 #define IXGBE_EICR_GPI_SDP1_8259X       0x02000000 /* Gen Purpose INT on SDP1 */
1592 #define IXGBE_EICR_GPI_SDP2_8259X       0x04000000 /* Gen Purpose INT on SDP2 */
1593 #define IXGBE_EICR_GPI_SDP0_X540        0x02000000
1594 #define IXGBE_EICR_GPI_SDP1_X540        0x04000000
1595 #define IXGBE_EICR_GPI_SDP2_X540        0x08000000
1596 #define IXGBE_EICR_GPI_SDP0_X550        IXGBE_EICR_GPI_SDP0_X540
1597 #define IXGBE_EICR_GPI_SDP1_X550        IXGBE_EICR_GPI_SDP1_X540
1598 #define IXGBE_EICR_GPI_SDP2_X550        IXGBE_EICR_GPI_SDP2_X540
1599 #define IXGBE_EICR_GPI_SDP0_X550EM_x    IXGBE_EICR_GPI_SDP0_X540
1600 #define IXGBE_EICR_GPI_SDP1_X550EM_x    IXGBE_EICR_GPI_SDP1_X540
1601 #define IXGBE_EICR_GPI_SDP2_X550EM_x    IXGBE_EICR_GPI_SDP2_X540
1602 #define IXGBE_EICR_GPI_SDP0_X550EM_a    IXGBE_EICR_GPI_SDP0_X540
1603 #define IXGBE_EICR_GPI_SDP1_X550EM_a    IXGBE_EICR_GPI_SDP1_X540
1604 #define IXGBE_EICR_GPI_SDP2_X550EM_a    IXGBE_EICR_GPI_SDP2_X540
1605 #define IXGBE_EICR_GPI_SDP0(_hw)        IXGBE_BY_MAC((_hw), EICR_GPI_SDP0)
1606 #define IXGBE_EICR_GPI_SDP1(_hw)        IXGBE_BY_MAC((_hw), EICR_GPI_SDP1)
1607 #define IXGBE_EICR_GPI_SDP2(_hw)        IXGBE_BY_MAC((_hw), EICR_GPI_SDP2)
1608
1609 #define IXGBE_EICR_ECC          0x10000000 /* ECC Error */
1610 #define IXGBE_EICR_PBUR         0x10000000 /* Packet Buffer Handler Error */
1611 #define IXGBE_EICR_DHER         0x20000000 /* Descriptor Handler Error */
1612 #define IXGBE_EICR_TCP_TIMER    0x40000000 /* TCP Timer */
1613 #define IXGBE_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
1614
1615 /* Extended Interrupt Cause Set */
1616 #define IXGBE_EICS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1617 #define IXGBE_EICS_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
1618 #define IXGBE_EICS_RX_MISS      IXGBE_EICR_RX_MISS   /* Pkt Buffer Overrun */
1619 #define IXGBE_EICS_PCI          IXGBE_EICR_PCI       /* PCI Exception */
1620 #define IXGBE_EICS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1621 #define IXGBE_EICS_LSC          IXGBE_EICR_LSC       /* Link Status Change */
1622 #define IXGBE_EICS_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
1623 #define IXGBE_EICS_TIMESYNC     IXGBE_EICR_TIMESYNC  /* Timesync Event */
1624 #define IXGBE_EICS_GPI_SDP0(_hw)        IXGBE_EICR_GPI_SDP0(_hw)
1625 #define IXGBE_EICS_GPI_SDP1(_hw)        IXGBE_EICR_GPI_SDP1(_hw)
1626 #define IXGBE_EICS_GPI_SDP2(_hw)        IXGBE_EICR_GPI_SDP2(_hw)
1627 #define IXGBE_EICS_ECC          IXGBE_EICR_ECC       /* ECC Error */
1628 #define IXGBE_EICS_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Err */
1629 #define IXGBE_EICS_DHER         IXGBE_EICR_DHER      /* Desc Handler Error */
1630 #define IXGBE_EICS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1631 #define IXGBE_EICS_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
1632
1633 /* Extended Interrupt Mask Set */
1634 #define IXGBE_EIMS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1635 #define IXGBE_EIMS_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
1636 #define IXGBE_EIMS_RX_MISS      IXGBE_EICR_RX_MISS   /* Packet Buffer Overrun */
1637 #define IXGBE_EIMS_PCI          IXGBE_EICR_PCI       /* PCI Exception */
1638 #define IXGBE_EIMS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1639 #define IXGBE_EIMS_LSC          IXGBE_EICR_LSC       /* Link Status Change */
1640 #define IXGBE_EIMS_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
1641 #define IXGBE_EIMS_TS           IXGBE_EICR_TS        /* Thermel Sensor Event */
1642 #define IXGBE_EIMS_TIMESYNC     IXGBE_EICR_TIMESYNC  /* Timesync Event */
1643 #define IXGBE_EIMS_GPI_SDP0(_hw)        IXGBE_EICR_GPI_SDP0(_hw)
1644 #define IXGBE_EIMS_GPI_SDP1(_hw)        IXGBE_EICR_GPI_SDP1(_hw)
1645 #define IXGBE_EIMS_GPI_SDP2(_hw)        IXGBE_EICR_GPI_SDP2(_hw)
1646 #define IXGBE_EIMS_ECC          IXGBE_EICR_ECC       /* ECC Error */
1647 #define IXGBE_EIMS_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Err */
1648 #define IXGBE_EIMS_DHER         IXGBE_EICR_DHER      /* Descr Handler Error */
1649 #define IXGBE_EIMS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1650 #define IXGBE_EIMS_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
1651
1652 /* Extended Interrupt Mask Clear */
1653 #define IXGBE_EIMC_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1654 #define IXGBE_EIMC_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
1655 #define IXGBE_EIMC_RX_MISS      IXGBE_EICR_RX_MISS   /* Packet Buffer Overrun */
1656 #define IXGBE_EIMC_PCI          IXGBE_EICR_PCI       /* PCI Exception */
1657 #define IXGBE_EIMC_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
1658 #define IXGBE_EIMC_LSC          IXGBE_EICR_LSC       /* Link Status Change */
1659 #define IXGBE_EIMC_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
1660 #define IXGBE_EIMC_TIMESYNC     IXGBE_EICR_TIMESYNC  /* Timesync Event */
1661 #define IXGBE_EIMC_GPI_SDP0(_hw)        IXGBE_EICR_GPI_SDP0(_hw)
1662 #define IXGBE_EIMC_GPI_SDP1(_hw)        IXGBE_EICR_GPI_SDP1(_hw)
1663 #define IXGBE_EIMC_GPI_SDP2(_hw)        IXGBE_EICR_GPI_SDP2(_hw)
1664 #define IXGBE_EIMC_ECC          IXGBE_EICR_ECC       /* ECC Error */
1665 #define IXGBE_EIMC_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Err */
1666 #define IXGBE_EIMC_DHER         IXGBE_EICR_DHER      /* Desc Handler Err */
1667 #define IXGBE_EIMC_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
1668 #define IXGBE_EIMC_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
1669
1670 #define IXGBE_EIMS_ENABLE_MASK ( \
1671                                 IXGBE_EIMS_RTX_QUEUE       | \
1672                                 IXGBE_EIMS_LSC             | \
1673                                 IXGBE_EIMS_TCP_TIMER       | \
1674                                 IXGBE_EIMS_OTHER)
1675
1676 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
1677 #define IXGBE_IMIR_PORT_IM_EN     0x00010000  /* TCP port enable */
1678 #define IXGBE_IMIR_PORT_BP        0x00020000  /* TCP port check bypass */
1679 #define IXGBE_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */
1680 #define IXGBE_IMIREXT_CTRL_URG    0x00002000  /* Check URG bit in header */
1681 #define IXGBE_IMIREXT_CTRL_ACK    0x00004000  /* Check ACK bit in header */
1682 #define IXGBE_IMIREXT_CTRL_PSH    0x00008000  /* Check PSH bit in header */
1683 #define IXGBE_IMIREXT_CTRL_RST    0x00010000  /* Check RST bit in header */
1684 #define IXGBE_IMIREXT_CTRL_SYN    0x00020000  /* Check SYN bit in header */
1685 #define IXGBE_IMIREXT_CTRL_FIN    0x00040000  /* Check FIN bit in header */
1686 #define IXGBE_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of control bits */
1687 #define IXGBE_IMIR_SIZE_BP_82599  0x00001000 /* Packet size bypass */
1688 #define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
1689 #define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
1690 #define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
1691 #define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
1692 #define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
1693 #define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
1694 #define IXGBE_IMIR_CTRL_BP_82599  0x00080000 /* Bypass check of control bits */
1695 #define IXGBE_IMIR_LLI_EN_82599   0x00100000 /* Enables low latency Int */
1696 #define IXGBE_IMIR_RX_QUEUE_MASK_82599  0x0000007F /* Rx Queue Mask */
1697 #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
1698 #define IXGBE_IMIRVP_PRIORITY_MASK      0x00000007 /* VLAN priority mask */
1699 #define IXGBE_IMIRVP_PRIORITY_EN        0x00000008 /* VLAN priority enable */
1700
1701 #define IXGBE_MAX_FTQF_FILTERS          128
1702 #define IXGBE_FTQF_PROTOCOL_MASK        0x00000003
1703 #define IXGBE_FTQF_PROTOCOL_TCP         0x00000000
1704 #define IXGBE_FTQF_PROTOCOL_UDP         0x00000001
1705 #define IXGBE_FTQF_PROTOCOL_SCTP        2
1706 #define IXGBE_FTQF_PRIORITY_MASK        0x00000007
1707 #define IXGBE_FTQF_PRIORITY_SHIFT       2
1708 #define IXGBE_FTQF_POOL_MASK            0x0000003F
1709 #define IXGBE_FTQF_POOL_SHIFT           8
1710 #define IXGBE_FTQF_5TUPLE_MASK_MASK     0x0000001F
1711 #define IXGBE_FTQF_5TUPLE_MASK_SHIFT    25
1712 #define IXGBE_FTQF_SOURCE_ADDR_MASK     0x1E
1713 #define IXGBE_FTQF_DEST_ADDR_MASK       0x1D
1714 #define IXGBE_FTQF_SOURCE_PORT_MASK     0x1B
1715 #define IXGBE_FTQF_DEST_PORT_MASK       0x17
1716 #define IXGBE_FTQF_PROTOCOL_COMP_MASK   0x0F
1717 #define IXGBE_FTQF_POOL_MASK_EN         0x40000000
1718 #define IXGBE_FTQF_QUEUE_ENABLE         0x80000000
1719
1720 /* Interrupt clear mask */
1721 #define IXGBE_IRQ_CLEAR_MASK    0xFFFFFFFF
1722
1723 /* Interrupt Vector Allocation Registers */
1724 #define IXGBE_IVAR_REG_NUM      25
1725 #define IXGBE_IVAR_REG_NUM_82599       64
1726 #define IXGBE_IVAR_TXRX_ENTRY   96
1727 #define IXGBE_IVAR_RX_ENTRY     64
1728 #define IXGBE_IVAR_RX_QUEUE(_i)    (0 + (_i))
1729 #define IXGBE_IVAR_TX_QUEUE(_i)    (64 + (_i))
1730 #define IXGBE_IVAR_TX_ENTRY     32
1731
1732 #define IXGBE_IVAR_TCP_TIMER_INDEX       96 /* 0 based index */
1733 #define IXGBE_IVAR_OTHER_CAUSES_INDEX    97 /* 0 based index */
1734
1735 #define IXGBE_MSIX_VECTOR(_i)   (0 + (_i))
1736
1737 #define IXGBE_IVAR_ALLOC_VAL    0x80 /* Interrupt Allocation valid */
1738
1739 /* ETYPE Queue Filter/Select Bit Masks */
1740 #define IXGBE_MAX_ETQF_FILTERS  8
1741 #define IXGBE_ETQF_FCOE         0x08000000 /* bit 27 */
1742 #define IXGBE_ETQF_BCN          0x10000000 /* bit 28 */
1743 #define IXGBE_ETQF_TX_ANTISPOOF 0x20000000 /* bit 29 */
1744 #define IXGBE_ETQF_1588         0x40000000 /* bit 30 */
1745 #define IXGBE_ETQF_FILTER_EN    0x80000000 /* bit 31 */
1746 #define IXGBE_ETQF_POOL_ENABLE   BIT(26) /* bit 26 */
1747 #define IXGBE_ETQF_POOL_SHIFT           20
1748
1749 #define IXGBE_ETQS_RX_QUEUE     0x007F0000 /* bits 22:16 */
1750 #define IXGBE_ETQS_RX_QUEUE_SHIFT       16
1751 #define IXGBE_ETQS_LLI          0x20000000 /* bit 29 */
1752 #define IXGBE_ETQS_QUEUE_EN     0x80000000 /* bit 31 */
1753
1754 /*
1755  * ETQF filter list: one static filter per filter consumer. This is
1756  *                   to avoid filter collisions later. Add new filters
1757  *                   here!!
1758  *
1759  * Current filters:
1760  *    EAPOL 802.1x (0x888e): Filter 0
1761  *    FCoE (0x8906):         Filter 2
1762  *    1588 (0x88f7):         Filter 3
1763  *    FIP  (0x8914):         Filter 4
1764  *    LLDP (0x88CC):         Filter 5
1765  *    LACP (0x8809):         Filter 6
1766  *    FC   (0x8808):         Filter 7
1767  */
1768 #define IXGBE_ETQF_FILTER_EAPOL          0
1769 #define IXGBE_ETQF_FILTER_FCOE           2
1770 #define IXGBE_ETQF_FILTER_1588           3
1771 #define IXGBE_ETQF_FILTER_FIP            4
1772 #define IXGBE_ETQF_FILTER_LLDP           5
1773 #define IXGBE_ETQF_FILTER_LACP           6
1774 #define IXGBE_ETQF_FILTER_FC             7
1775
1776 /* VLAN Control Bit Masks */
1777 #define IXGBE_VLNCTRL_VET       0x0000FFFF  /* bits 0-15 */
1778 #define IXGBE_VLNCTRL_CFI       0x10000000  /* bit 28 */
1779 #define IXGBE_VLNCTRL_CFIEN     0x20000000  /* bit 29 */
1780 #define IXGBE_VLNCTRL_VFE       0x40000000  /* bit 30 */
1781 #define IXGBE_VLNCTRL_VME       0x80000000  /* bit 31 */
1782
1783 /* VLAN pool filtering masks */
1784 #define IXGBE_VLVF_VIEN         0x80000000  /* filter is valid */
1785 #define IXGBE_VLVF_ENTRIES      64
1786 #define IXGBE_VLVF_VLANID_MASK  0x00000FFF
1787
1788 /* Per VF Port VLAN insertion rules */
1789 #define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
1790 #define IXGBE_VMVIR_VLANA_NEVER   0x80000000 /* Never insert VLAN tag */
1791
1792 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.1q protocol */
1793
1794 /* STATUS Bit Masks */
1795 #define IXGBE_STATUS_LAN_ID         0x0000000C /* LAN ID */
1796 #define IXGBE_STATUS_LAN_ID_SHIFT   2          /* LAN ID Shift*/
1797 #define IXGBE_STATUS_GIO            0x00080000 /* GIO Master Enable Status */
1798
1799 #define IXGBE_STATUS_LAN_ID_0   0x00000000 /* LAN ID 0 */
1800 #define IXGBE_STATUS_LAN_ID_1   0x00000004 /* LAN ID 1 */
1801
1802 /* ESDP Bit Masks */
1803 #define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */
1804 #define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */
1805 #define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
1806 #define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
1807 #define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
1808 #define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
1809 #define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
1810 #define IXGBE_ESDP_SDP0_DIR     0x00000100 /* SDP0 IO direction */
1811 #define IXGBE_ESDP_SDP1_DIR     0x00000200 /* SDP1 IO direction */
1812 #define IXGBE_ESDP_SDP4_DIR     0x00000004 /* SDP4 IO direction */
1813 #define IXGBE_ESDP_SDP5_DIR     0x00002000 /* SDP5 IO direction */
1814 #define IXGBE_ESDP_SDP0_NATIVE  0x00010000 /* SDP0 Native Function */
1815 #define IXGBE_ESDP_SDP1_NATIVE  0x00020000 /* SDP1 IO mode */
1816
1817 /* LEDCTL Bit Masks */
1818 #define IXGBE_LED_IVRT_BASE      0x00000040
1819 #define IXGBE_LED_BLINK_BASE     0x00000080
1820 #define IXGBE_LED_MODE_MASK_BASE 0x0000000F
1821 #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
1822 #define IXGBE_LED_MODE_SHIFT(_i) (8 * (_i))
1823 #define IXGBE_LED_IVRT(_i)       IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1824 #define IXGBE_LED_BLINK(_i)      IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
1825 #define IXGBE_LED_MODE_MASK(_i)  IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
1826
1827 /* LED modes */
1828 #define IXGBE_LED_LINK_UP       0x0
1829 #define IXGBE_LED_LINK_10G      0x1
1830 #define IXGBE_LED_MAC           0x2
1831 #define IXGBE_LED_FILTER        0x3
1832 #define IXGBE_LED_LINK_ACTIVE   0x4
1833 #define IXGBE_LED_LINK_1G       0x5
1834 #define IXGBE_LED_ON            0xE
1835 #define IXGBE_LED_OFF           0xF
1836
1837 /* AUTOC Bit Masks */
1838 #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
1839 #define IXGBE_AUTOC_KX4_SUPP    0x80000000
1840 #define IXGBE_AUTOC_KX_SUPP     0x40000000
1841 #define IXGBE_AUTOC_PAUSE       0x30000000
1842 #define IXGBE_AUTOC_ASM_PAUSE   0x20000000
1843 #define IXGBE_AUTOC_SYM_PAUSE   0x10000000
1844 #define IXGBE_AUTOC_RF          0x08000000
1845 #define IXGBE_AUTOC_PD_TMR      0x06000000
1846 #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
1847 #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
1848 #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
1849 #define IXGBE_AUTOC_FECA        0x00040000
1850 #define IXGBE_AUTOC_FECR        0x00020000
1851 #define IXGBE_AUTOC_KR_SUPP     0x00010000
1852 #define IXGBE_AUTOC_AN_RESTART  0x00001000
1853 #define IXGBE_AUTOC_FLU         0x00000001
1854 #define IXGBE_AUTOC_LMS_SHIFT   13
1855 #define IXGBE_AUTOC_LMS_10G_SERIAL      (0x3 << IXGBE_AUTOC_LMS_SHIFT)
1856 #define IXGBE_AUTOC_LMS_KX4_KX_KR       (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1857 #define IXGBE_AUTOC_LMS_SGMII_1G_100M   (0x5 << IXGBE_AUTOC_LMS_SHIFT)
1858 #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1859 #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1860 #define IXGBE_AUTOC_LMS_MASK            (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1861 #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN   (0x0 << IXGBE_AUTOC_LMS_SHIFT)
1862 #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN  (0x1 << IXGBE_AUTOC_LMS_SHIFT)
1863 #define IXGBE_AUTOC_LMS_1G_AN           (0x2 << IXGBE_AUTOC_LMS_SHIFT)
1864 #define IXGBE_AUTOC_LMS_KX4_AN          (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1865 #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN    (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1866 #define IXGBE_AUTOC_LMS_ATTACH_TYPE     (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1867
1868 #define IXGBE_AUTOC_1G_PMA_PMD_MASK    0x00000200
1869 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT   9
1870 #define IXGBE_AUTOC_10G_PMA_PMD_MASK   0x00000180
1871 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT  7
1872 #define IXGBE_AUTOC_10G_XAUI   (0u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1873 #define IXGBE_AUTOC_10G_KX4    (1u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1874 #define IXGBE_AUTOC_10G_CX4    (2u << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1875 #define IXGBE_AUTOC_1G_BX      (0u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1876 #define IXGBE_AUTOC_1G_KX      (1u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1877 #define IXGBE_AUTOC_1G_SFI     (0u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1878 #define IXGBE_AUTOC_1G_KX_BX   (1u << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1879
1880 #define IXGBE_AUTOC2_UPPER_MASK  0xFFFF0000
1881 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK  0x00030000
1882 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1883 #define IXGBE_AUTOC2_10G_KR  (0u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1884 #define IXGBE_AUTOC2_10G_XFI (1u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1885 #define IXGBE_AUTOC2_10G_SFI (2u << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1886 #define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK  0x50000000
1887 #define IXGBE_AUTOC2_LINK_DISABLE_MASK        0x70000000
1888
1889 #define IXGBE_MACC_FLU       0x00000001
1890 #define IXGBE_MACC_FSV_10G   0x00030000
1891 #define IXGBE_MACC_FS        0x00040000
1892 #define IXGBE_MAC_RX2TX_LPBK 0x00000002
1893
1894 /* Veto Bit definition */
1895 #define IXGBE_MMNGC_MNG_VETO  0x00000001
1896
1897 /* LINKS Bit Masks */
1898 #define IXGBE_LINKS_KX_AN_COMP  0x80000000
1899 #define IXGBE_LINKS_UP          0x40000000
1900 #define IXGBE_LINKS_SPEED       0x20000000
1901 #define IXGBE_LINKS_MODE        0x18000000
1902 #define IXGBE_LINKS_RX_MODE     0x06000000
1903 #define IXGBE_LINKS_TX_MODE     0x01800000
1904 #define IXGBE_LINKS_XGXS_EN     0x00400000
1905 #define IXGBE_LINKS_SGMII_EN    0x02000000
1906 #define IXGBE_LINKS_PCS_1G_EN   0x00200000
1907 #define IXGBE_LINKS_1G_AN_EN    0x00100000
1908 #define IXGBE_LINKS_KX_AN_IDLE  0x00080000
1909 #define IXGBE_LINKS_1G_SYNC     0x00040000
1910 #define IXGBE_LINKS_10G_ALIGN   0x00020000
1911 #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
1912 #define IXGBE_LINKS_TL_FAULT    0x00001000
1913 #define IXGBE_LINKS_SIGNAL      0x00000F00
1914
1915 #define IXGBE_LINKS_SPEED_NON_STD   0x08000000
1916 #define IXGBE_LINKS_SPEED_82599     0x30000000
1917 #define IXGBE_LINKS_SPEED_10G_82599 0x30000000
1918 #define IXGBE_LINKS_SPEED_1G_82599  0x20000000
1919 #define IXGBE_LINKS_SPEED_100_82599 0x10000000
1920 #define IXGBE_LINK_UP_TIME      90 /* 9.0 Seconds */
1921 #define IXGBE_AUTO_NEG_TIME     45 /* 4.5 Seconds */
1922
1923 #define IXGBE_LINKS2_AN_SUPPORTED   0x00000040
1924
1925 /* PCS1GLSTA Bit Masks */
1926 #define IXGBE_PCS1GLSTA_LINK_OK         1
1927 #define IXGBE_PCS1GLSTA_SYNK_OK         0x10
1928 #define IXGBE_PCS1GLSTA_AN_COMPLETE     0x10000
1929 #define IXGBE_PCS1GLSTA_AN_PAGE_RX      0x20000
1930 #define IXGBE_PCS1GLSTA_AN_TIMED_OUT    0x40000
1931 #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
1932 #define IXGBE_PCS1GLSTA_AN_ERROR_RWS    0x100000
1933
1934 #define IXGBE_PCS1GANA_SYM_PAUSE        0x80
1935 #define IXGBE_PCS1GANA_ASM_PAUSE        0x100
1936
1937 /* PCS1GLCTL Bit Masks */
1938 #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN  0x00040000 /* PCS 1G autoneg to en */
1939 #define IXGBE_PCS1GLCTL_FLV_LINK_UP     1
1940 #define IXGBE_PCS1GLCTL_FORCE_LINK      0x20
1941 #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH  0x40
1942 #define IXGBE_PCS1GLCTL_AN_ENABLE       0x10000
1943 #define IXGBE_PCS1GLCTL_AN_RESTART      0x20000
1944
1945 /* ANLP1 Bit Masks */
1946 #define IXGBE_ANLP1_PAUSE               0x0C00
1947 #define IXGBE_ANLP1_SYM_PAUSE           0x0400
1948 #define IXGBE_ANLP1_ASM_PAUSE           0x0800
1949 #define IXGBE_ANLP1_AN_STATE_MASK       0x000f0000
1950
1951 /* SW Semaphore Register bitmasks */
1952 #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1953 #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1954 #define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
1955 #define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
1956
1957 /* SW_FW_SYNC/GSSR definitions */
1958 #define IXGBE_GSSR_EEP_SM               0x0001
1959 #define IXGBE_GSSR_PHY0_SM              0x0002
1960 #define IXGBE_GSSR_PHY1_SM              0x0004
1961 #define IXGBE_GSSR_MAC_CSR_SM           0x0008
1962 #define IXGBE_GSSR_FLASH_SM             0x0010
1963 #define IXGBE_GSSR_NVM_UPDATE_SM        0x0200
1964 #define IXGBE_GSSR_SW_MNG_SM            0x0400
1965 #define IXGBE_GSSR_TOKEN_SM     0x40000000 /* SW bit for shared access */
1966 #define IXGBE_GSSR_SHARED_I2C_SM        0x1806 /* Wait for both phys & I2Cs */
1967 #define IXGBE_GSSR_I2C_MASK             0x1800
1968 #define IXGBE_GSSR_NVM_PHY_MASK         0xF
1969
1970 /* FW Status register bitmask */
1971 #define IXGBE_FWSTS_FWRI    0x00000200 /* Firmware Reset Indication */
1972
1973 /* EEC Register */
1974 #define IXGBE_EEC_SK        0x00000001 /* EEPROM Clock */
1975 #define IXGBE_EEC_CS        0x00000002 /* EEPROM Chip Select */
1976 #define IXGBE_EEC_DI        0x00000004 /* EEPROM Data In */
1977 #define IXGBE_EEC_DO        0x00000008 /* EEPROM Data Out */
1978 #define IXGBE_EEC_FWE_MASK  0x00000030 /* FLASH Write Enable */
1979 #define IXGBE_EEC_FWE_DIS   0x00000010 /* Disable FLASH writes */
1980 #define IXGBE_EEC_FWE_EN    0x00000020 /* Enable FLASH writes */
1981 #define IXGBE_EEC_FWE_SHIFT 4
1982 #define IXGBE_EEC_REQ       0x00000040 /* EEPROM Access Request */
1983 #define IXGBE_EEC_GNT       0x00000080 /* EEPROM Access Grant */
1984 #define IXGBE_EEC_PRES      0x00000100 /* EEPROM Present */
1985 #define IXGBE_EEC_ARD       0x00000200 /* EEPROM Auto Read Done */
1986 #define IXGBE_EEC_FLUP      0x00800000 /* Flash update command */
1987 #define IXGBE_EEC_SEC1VAL   0x02000000 /* Sector 1 Valid */
1988 #define IXGBE_EEC_FLUDONE   0x04000000 /* Flash update done */
1989 /* EEPROM Addressing bits based on type (0-small, 1-large) */
1990 #define IXGBE_EEC_ADDR_SIZE 0x00000400
1991 #define IXGBE_EEC_SIZE      0x00007800 /* EEPROM Size */
1992 #define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */
1993
1994 #define IXGBE_EEC_SIZE_SHIFT          11
1995 #define IXGBE_EEPROM_WORD_SIZE_SHIFT  6
1996 #define IXGBE_EEPROM_OPCODE_BITS      8
1997
1998 /* Part Number String Length */
1999 #define IXGBE_PBANUM_LENGTH 11
2000
2001 /* Checksum and EEPROM pointers */
2002 #define IXGBE_PBANUM_PTR_GUARD          0xFAFA
2003 #define IXGBE_EEPROM_CHECKSUM           0x3F
2004 #define IXGBE_EEPROM_SUM                0xBABA
2005 #define IXGBE_EEPROM_CTRL_4             0x45
2006 #define IXGBE_EE_CTRL_4_INST_ID         0x10
2007 #define IXGBE_EE_CTRL_4_INST_ID_SHIFT   4
2008 #define IXGBE_PCIE_ANALOG_PTR           0x03
2009 #define IXGBE_ATLAS0_CONFIG_PTR         0x04
2010 #define IXGBE_PHY_PTR                   0x04
2011 #define IXGBE_ATLAS1_CONFIG_PTR         0x05
2012 #define IXGBE_OPTION_ROM_PTR            0x05
2013 #define IXGBE_PCIE_GENERAL_PTR          0x06
2014 #define IXGBE_PCIE_CONFIG0_PTR          0x07
2015 #define IXGBE_PCIE_CONFIG1_PTR          0x08
2016 #define IXGBE_CORE0_PTR                 0x09
2017 #define IXGBE_CORE1_PTR                 0x0A
2018 #define IXGBE_MAC0_PTR                  0x0B
2019 #define IXGBE_MAC1_PTR                  0x0C
2020 #define IXGBE_CSR0_CONFIG_PTR           0x0D
2021 #define IXGBE_CSR1_CONFIG_PTR           0x0E
2022 #define IXGBE_PCIE_ANALOG_PTR_X550      0x02
2023 #define IXGBE_SHADOW_RAM_SIZE_X550      0x4000
2024 #define IXGBE_IXGBE_PCIE_GENERAL_SIZE   0x24
2025 #define IXGBE_PCIE_CONFIG_SIZE          0x08
2026 #define IXGBE_EEPROM_LAST_WORD          0x41
2027 #define IXGBE_FW_PTR                    0x0F
2028 #define IXGBE_PBANUM0_PTR               0x15
2029 #define IXGBE_PBANUM1_PTR               0x16
2030 #define IXGBE_FREE_SPACE_PTR            0X3E
2031
2032 /* External Thermal Sensor Config */
2033 #define IXGBE_ETS_CFG                   0x26
2034 #define IXGBE_ETS_LTHRES_DELTA_MASK     0x07C0
2035 #define IXGBE_ETS_LTHRES_DELTA_SHIFT    6
2036 #define IXGBE_ETS_TYPE_MASK             0x0038
2037 #define IXGBE_ETS_TYPE_SHIFT            3
2038 #define IXGBE_ETS_TYPE_EMC              0x000
2039 #define IXGBE_ETS_TYPE_EMC_SHIFTED      0x000
2040 #define IXGBE_ETS_NUM_SENSORS_MASK      0x0007
2041 #define IXGBE_ETS_DATA_LOC_MASK         0x3C00
2042 #define IXGBE_ETS_DATA_LOC_SHIFT        10
2043 #define IXGBE_ETS_DATA_INDEX_MASK       0x0300
2044 #define IXGBE_ETS_DATA_INDEX_SHIFT      8
2045 #define IXGBE_ETS_DATA_HTHRESH_MASK     0x00FF
2046
2047 #define IXGBE_SAN_MAC_ADDR_PTR  0x28
2048 #define IXGBE_DEVICE_CAPS       0x2C
2049 #define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
2050 #define IXGBE_PCIE_MSIX_82599_CAPS  0x72
2051 #define IXGBE_MAX_MSIX_VECTORS_82599    0x40
2052 #define IXGBE_PCIE_MSIX_82598_CAPS  0x62
2053 #define IXGBE_MAX_MSIX_VECTORS_82598    0x13
2054
2055 /* MSI-X capability fields masks */
2056 #define IXGBE_PCIE_MSIX_TBL_SZ_MASK     0x7FF
2057
2058 /* Legacy EEPROM word offsets */
2059 #define IXGBE_ISCSI_BOOT_CAPS           0x0033
2060 #define IXGBE_ISCSI_SETUP_PORT_0        0x0030
2061 #define IXGBE_ISCSI_SETUP_PORT_1        0x0034
2062
2063 /* EEPROM Commands - SPI */
2064 #define IXGBE_EEPROM_MAX_RETRY_SPI      5000 /* Max wait 5ms for RDY signal */
2065 #define IXGBE_EEPROM_STATUS_RDY_SPI     0x01
2066 #define IXGBE_EEPROM_READ_OPCODE_SPI    0x03  /* EEPROM read opcode */
2067 #define IXGBE_EEPROM_WRITE_OPCODE_SPI   0x02  /* EEPROM write opcode */
2068 #define IXGBE_EEPROM_A8_OPCODE_SPI      0x08  /* opcode bit-3 = addr bit-8 */
2069 #define IXGBE_EEPROM_WREN_OPCODE_SPI    0x06  /* EEPROM set Write Ena latch */
2070 /* EEPROM reset Write Enable latch */
2071 #define IXGBE_EEPROM_WRDI_OPCODE_SPI    0x04
2072 #define IXGBE_EEPROM_RDSR_OPCODE_SPI    0x05  /* EEPROM read Status reg */
2073 #define IXGBE_EEPROM_WRSR_OPCODE_SPI    0x01  /* EEPROM write Status reg */
2074 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20  /* EEPROM ERASE 4KB */
2075 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI  0xD8  /* EEPROM ERASE 64KB */
2076 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI  0xDB  /* EEPROM ERASE 256B */
2077
2078 /* EEPROM Read Register */
2079 #define IXGBE_EEPROM_RW_REG_DATA   16 /* data offset in EEPROM read reg */
2080 #define IXGBE_EEPROM_RW_REG_DONE   2  /* Offset to READ done bit */
2081 #define IXGBE_EEPROM_RW_REG_START  1  /* First bit to start operation */
2082 #define IXGBE_EEPROM_RW_ADDR_SHIFT 2  /* Shift to the address bits */
2083 #define IXGBE_NVM_POLL_WRITE       1  /* Flag for polling for write complete */
2084 #define IXGBE_NVM_POLL_READ        0  /* Flag for polling for read complete */
2085
2086 #define NVM_INIT_CTRL_3                 0x38
2087 #define NVM_INIT_CTRL_3_LPLU            0x8
2088 #define NVM_INIT_CTRL_3_D10GMP_PORT0    0x40
2089 #define NVM_INIT_CTRL_3_D10GMP_PORT1    0x100
2090
2091 #define IXGBE_EEPROM_PAGE_SIZE_MAX       128
2092 #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */
2093 #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */
2094
2095 #define IXGBE_EEPROM_CTRL_2     1 /* EEPROM CTRL word 2 */
2096 #define IXGBE_EEPROM_CCD_BIT    2 /* EEPROM Core Clock Disable bit */
2097
2098 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
2099 #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
2100 #endif
2101
2102 #ifndef IXGBE_EERD_EEWR_ATTEMPTS
2103 /* Number of 5 microseconds we wait for EERD read and
2104  * EERW write to complete */
2105 #define IXGBE_EERD_EEWR_ATTEMPTS 100000
2106 #endif
2107
2108 #ifndef IXGBE_FLUDONE_ATTEMPTS
2109 /* # attempts we wait for flush update to complete */
2110 #define IXGBE_FLUDONE_ATTEMPTS 20000
2111 #endif
2112
2113 #define IXGBE_PCIE_CTRL2                 0x5   /* PCIe Control 2 Offset */
2114 #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE    0x8   /* Dummy Function Enable */
2115 #define IXGBE_PCIE_CTRL2_LAN_DISABLE     0x2   /* LAN PCI Disable */
2116 #define IXGBE_PCIE_CTRL2_DISABLE_SELECT  0x1   /* LAN Disable Select */
2117
2118 #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET  0x0
2119 #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET  0x3
2120 #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP  0x1
2121 #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS  0x2
2122 #define IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR       BIT(7)
2123 #define IXGBE_FW_LESM_PARAMETERS_PTR     0x2
2124 #define IXGBE_FW_LESM_STATE_1            0x1
2125 #define IXGBE_FW_LESM_STATE_ENABLED      0x8000 /* LESM Enable bit */
2126 #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR   0x4
2127 #define IXGBE_FW_PATCH_VERSION_4         0x7
2128 #define IXGBE_FCOE_IBA_CAPS_BLK_PTR         0x33 /* iSCSI/FCOE block */
2129 #define IXGBE_FCOE_IBA_CAPS_FCOE            0x20 /* FCOE flags */
2130 #define IXGBE_ISCSI_FCOE_BLK_PTR            0x17 /* iSCSI/FCOE block */
2131 #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET       0x0  /* FCOE flags */
2132 #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE       0x1  /* FCOE flags enable bit */
2133 #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR      0x27 /* Alt. SAN MAC block */
2134 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET  0x0 /* Alt. SAN MAC capability */
2135 #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
2136 #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
2137 #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET  0x7 /* Alt. WWNN prefix offset */
2138 #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET  0x8 /* Alt. WWPN prefix offset */
2139 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC  0x0 /* Alt. SAN MAC exists */
2140 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN  0x1 /* Alt. WWN base exists */
2141
2142 #define IXGBE_DEVICE_CAPS_WOL_PORT0_1  0x4 /* WoL supported on ports 0 & 1 */
2143 #define IXGBE_DEVICE_CAPS_WOL_PORT0    0x8 /* WoL supported on port 0 */
2144 #define IXGBE_DEVICE_CAPS_WOL_MASK     0xC /* Mask for WoL capabilities */
2145
2146 /* PCI Bus Info */
2147 #define IXGBE_PCI_DEVICE_STATUS   0xAA
2148 #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING   0x0020
2149 #define IXGBE_PCI_LINK_STATUS     0xB2
2150 #define IXGBE_PCI_DEVICE_CONTROL2 0xC8
2151 #define IXGBE_PCI_LINK_WIDTH      0x3F0
2152 #define IXGBE_PCI_LINK_WIDTH_1    0x10
2153 #define IXGBE_PCI_LINK_WIDTH_2    0x20
2154 #define IXGBE_PCI_LINK_WIDTH_4    0x40
2155 #define IXGBE_PCI_LINK_WIDTH_8    0x80
2156 #define IXGBE_PCI_LINK_SPEED      0xF
2157 #define IXGBE_PCI_LINK_SPEED_2500 0x1
2158 #define IXGBE_PCI_LINK_SPEED_5000 0x2
2159 #define IXGBE_PCI_LINK_SPEED_8000 0x3
2160 #define IXGBE_PCI_HEADER_TYPE_REGISTER  0x0E
2161 #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
2162 #define IXGBE_PCI_DEVICE_CONTROL2_16ms  0x0005
2163
2164 #define IXGBE_PCIDEVCTRL2_TIMEO_MASK    0xf
2165 #define IXGBE_PCIDEVCTRL2_16_32ms_def   0x0
2166 #define IXGBE_PCIDEVCTRL2_50_100us      0x1
2167 #define IXGBE_PCIDEVCTRL2_1_2ms         0x2
2168 #define IXGBE_PCIDEVCTRL2_16_32ms       0x5
2169 #define IXGBE_PCIDEVCTRL2_65_130ms      0x6
2170 #define IXGBE_PCIDEVCTRL2_260_520ms     0x9
2171 #define IXGBE_PCIDEVCTRL2_1_2s          0xa
2172 #define IXGBE_PCIDEVCTRL2_4_8s          0xd
2173 #define IXGBE_PCIDEVCTRL2_17_34s        0xe
2174
2175 /* Number of 100 microseconds we wait for PCI Express master disable */
2176 #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT        800
2177
2178 /* RAH */
2179 #define IXGBE_RAH_VIND_MASK     0x003C0000
2180 #define IXGBE_RAH_VIND_SHIFT    18
2181 #define IXGBE_RAH_AV            0x80000000
2182 #define IXGBE_CLEAR_VMDQ_ALL    0xFFFFFFFF
2183
2184 /* Header split receive */
2185 #define IXGBE_RFCTL_ISCSI_DIS       0x00000001
2186 #define IXGBE_RFCTL_ISCSI_DWC_MASK  0x0000003E
2187 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
2188 #define IXGBE_RFCTL_RSC_DIS             0x00000020
2189 #define IXGBE_RFCTL_NFSW_DIS        0x00000040
2190 #define IXGBE_RFCTL_NFSR_DIS        0x00000080
2191 #define IXGBE_RFCTL_NFS_VER_MASK    0x00000300
2192 #define IXGBE_RFCTL_NFS_VER_SHIFT   8
2193 #define IXGBE_RFCTL_NFS_VER_2       0
2194 #define IXGBE_RFCTL_NFS_VER_3       1
2195 #define IXGBE_RFCTL_NFS_VER_4       2
2196 #define IXGBE_RFCTL_IPV6_DIS        0x00000400
2197 #define IXGBE_RFCTL_IPV6_XSUM_DIS   0x00000800
2198 #define IXGBE_RFCTL_IPFRSP_DIS      0x00004000
2199 #define IXGBE_RFCTL_IPV6_EX_DIS     0x00010000
2200 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
2201
2202 /* Transmit Config masks */
2203 #define IXGBE_TXDCTL_ENABLE     0x02000000 /* Enable specific Tx Queue */
2204 #define IXGBE_TXDCTL_SWFLSH     0x04000000 /* Tx Desc. write-back flushing */
2205 #define IXGBE_TXDCTL_WTHRESH_SHIFT      16 /* shift to WTHRESH bits */
2206 /* Enable short packet padding to 64 bytes */
2207 #define IXGBE_TX_PAD_ENABLE     0x00000400
2208 #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004  /* Allow jumbo frames */
2209 /* This allows for 16K packets + 4k for vlan */
2210 #define IXGBE_MAX_FRAME_SZ      0x40040000
2211
2212 #define IXGBE_TDWBAL_HEAD_WB_ENABLE   0x1      /* Tx head write-back enable */
2213 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2      /* Tx seq# write-back enable */
2214
2215 /* Receive Config masks */
2216 #define IXGBE_RXCTRL_RXEN       0x00000001  /* Enable Receiver */
2217 #define IXGBE_RXCTRL_DMBYPS     0x00000002  /* Descriptor Monitor Bypass */
2218 #define IXGBE_RXDCTL_ENABLE     0x02000000  /* Enable specific Rx Queue */
2219 #define IXGBE_RXDCTL_SWFLSH     0x04000000  /* Rx Desc. write-back flushing */
2220 #define IXGBE_RXDCTL_RLPMLMASK  0x00003FFF  /* Only supported on the X540 */
2221 #define IXGBE_RXDCTL_RLPML_EN   0x00008000
2222 #define IXGBE_RXDCTL_VME        0x40000000  /* VLAN mode enable */
2223
2224 #define IXGBE_TSAUXC_EN_CLK   0x00000004
2225 #define IXGBE_TSAUXC_SYNCLK   0x00000008
2226 #define IXGBE_TSAUXC_SDP0_INT 0x00000040
2227 #define IXGBE_TSAUXC_DISABLE_SYSTIME    0x80000000
2228
2229 #define IXGBE_TSYNCTXCTL_VALID          0x00000001 /* Tx timestamp valid */
2230 #define IXGBE_TSYNCTXCTL_ENABLED        0x00000010 /* Tx timestamping enabled */
2231
2232 #define IXGBE_TSYNCRXCTL_VALID          0x00000001 /* Rx timestamp valid */
2233 #define IXGBE_TSYNCRXCTL_TYPE_MASK      0x0000000E /* Rx type mask */
2234 #define IXGBE_TSYNCRXCTL_TYPE_L2_V2     0x00
2235 #define IXGBE_TSYNCRXCTL_TYPE_L4_V1     0x02
2236 #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2  0x04
2237 #define IXGBE_TSYNCRXCTL_TYPE_ALL       0x08
2238 #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2  0x0A
2239 #define IXGBE_TSYNCRXCTL_ENABLED        0x00000010 /* Rx Timestamping enabled */
2240 #define IXGBE_TSYNCRXCTL_TSIP_UT_EN     0x00800000 /* Rx Timestamp in Packet */
2241
2242 #define IXGBE_TSIM_TXTS                 0x00000002
2243
2244 #define IXGBE_RXMTRL_V1_CTRLT_MASK      0x000000FF
2245 #define IXGBE_RXMTRL_V1_SYNC_MSG        0x00
2246 #define IXGBE_RXMTRL_V1_DELAY_REQ_MSG   0x01
2247 #define IXGBE_RXMTRL_V1_FOLLOWUP_MSG    0x02
2248 #define IXGBE_RXMTRL_V1_DELAY_RESP_MSG  0x03
2249 #define IXGBE_RXMTRL_V1_MGMT_MSG        0x04
2250
2251 #define IXGBE_RXMTRL_V2_MSGID_MASK              0x0000FF00
2252 #define IXGBE_RXMTRL_V2_SYNC_MSG                0x0000
2253 #define IXGBE_RXMTRL_V2_DELAY_REQ_MSG           0x0100
2254 #define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG          0x0200
2255 #define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG         0x0300
2256 #define IXGBE_RXMTRL_V2_FOLLOWUP_MSG            0x0800
2257 #define IXGBE_RXMTRL_V2_DELAY_RESP_MSG          0x0900
2258 #define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG     0x0A00
2259 #define IXGBE_RXMTRL_V2_ANNOUNCE_MSG            0x0B00
2260 #define IXGBE_RXMTRL_V2_SIGNALING_MSG           0x0C00
2261 #define IXGBE_RXMTRL_V2_MGMT_MSG                0x0D00
2262
2263 #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
2264 #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
2265 #define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
2266 #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
2267 #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
2268 #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
2269 /* Receive Priority Flow Control Enable */
2270 #define IXGBE_FCTRL_RPFCE 0x00004000
2271 #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
2272 #define IXGBE_MFLCN_PMCF        0x00000001 /* Pass MAC Control Frames */
2273 #define IXGBE_MFLCN_DPF         0x00000002 /* Discard Pause Frame */
2274 #define IXGBE_MFLCN_RPFCE       0x00000004 /* Receive Priority FC Enable */
2275 #define IXGBE_MFLCN_RFCE        0x00000008 /* Receive FC Enable */
2276 #define IXGBE_MFLCN_RPFCE_MASK  0x00000FF4 /* Receive FC Mask */
2277
2278 #define IXGBE_MFLCN_RPFCE_SHIFT          4
2279
2280 /* Multiple Receive Queue Control */
2281 #define IXGBE_MRQC_RSSEN                 0x00000001  /* RSS Enable */
2282 #define IXGBE_MRQC_MRQE_MASK                    0xF /* Bits 3:0 */
2283 #define IXGBE_MRQC_RT8TCEN               0x00000002 /* 8 TC no RSS */
2284 #define IXGBE_MRQC_RT4TCEN               0x00000003 /* 4 TC no RSS */
2285 #define IXGBE_MRQC_RTRSS8TCEN            0x00000004 /* 8 TC w/ RSS */
2286 #define IXGBE_MRQC_RTRSS4TCEN            0x00000005 /* 4 TC w/ RSS */
2287 #define IXGBE_MRQC_VMDQEN                0x00000008 /* VMDq2 64 pools no RSS */
2288 #define IXGBE_MRQC_VMDQRSS32EN           0x0000000A /* VMDq2 32 pools w/ RSS */
2289 #define IXGBE_MRQC_VMDQRSS64EN           0x0000000B /* VMDq2 64 pools w/ RSS */
2290 #define IXGBE_MRQC_VMDQRT8TCEN           0x0000000C /* VMDq2/RT 16 pool 8 TC */
2291 #define IXGBE_MRQC_VMDQRT4TCEN           0x0000000D /* VMDq2/RT 32 pool 4 TC */
2292 #define IXGBE_MRQC_RSS_FIELD_MASK        0xFFFF0000
2293 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP    0x00010000
2294 #define IXGBE_MRQC_RSS_FIELD_IPV4        0x00020000
2295 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
2296 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX     0x00080000
2297 #define IXGBE_MRQC_RSS_FIELD_IPV6        0x00100000
2298 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP    0x00200000
2299 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP    0x00400000
2300 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP    0x00800000
2301 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
2302 #define IXGBE_MRQC_MULTIPLE_RSS          0x00002000
2303 #define IXGBE_MRQC_L3L4TXSWEN            0x00008000
2304
2305 #define IXGBE_FWSM_TS_ENABLED   0x1
2306
2307 /* Queue Drop Enable */
2308 #define IXGBE_QDE_ENABLE        0x00000001
2309 #define IXGBE_QDE_HIDE_VLAN     0x00000002
2310 #define IXGBE_QDE_IDX_MASK      0x00007F00
2311 #define IXGBE_QDE_IDX_SHIFT     8
2312 #define IXGBE_QDE_WRITE         0x00010000
2313
2314 #define IXGBE_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
2315 #define IXGBE_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
2316 #define IXGBE_TXD_CMD_EOP    0x01000000 /* End of Packet */
2317 #define IXGBE_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
2318 #define IXGBE_TXD_CMD_IC     0x04000000 /* Insert Checksum */
2319 #define IXGBE_TXD_CMD_RS     0x08000000 /* Report Status */
2320 #define IXGBE_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
2321 #define IXGBE_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
2322 #define IXGBE_TXD_STAT_DD    0x00000001 /* Descriptor Done */
2323
2324 #define IXGBE_RXDADV_IPSEC_STATUS_SECP                  0x00020000
2325 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL       0x08000000
2326 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH         0x10000000
2327 #define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED            0x18000000
2328 #define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK               0x18000000
2329 /* Multiple Transmit Queue Command Register */
2330 #define IXGBE_MTQC_RT_ENA       0x1 /* DCB Enable */
2331 #define IXGBE_MTQC_VT_ENA       0x2 /* VMDQ2 Enable */
2332 #define IXGBE_MTQC_64Q_1PB      0x0 /* 64 queues 1 pack buffer */
2333 #define IXGBE_MTQC_32VF         0x8 /* 4 TX Queues per pool w/32VF's */
2334 #define IXGBE_MTQC_64VF         0x4 /* 2 TX Queues per pool w/64VF's */
2335 #define IXGBE_MTQC_8TC_8TQ      0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
2336 #define IXGBE_MTQC_4TC_4TQ      0x8 /* 4 TC if RT_ENA or 4 TQ if VT_ENA */
2337
2338 /* Receive Descriptor bit definitions */
2339 #define IXGBE_RXD_STAT_DD       0x01    /* Descriptor Done */
2340 #define IXGBE_RXD_STAT_EOP      0x02    /* End of Packet */
2341 #define IXGBE_RXD_STAT_FLM      0x04    /* FDir Match */
2342 #define IXGBE_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
2343 #define IXGBE_RXDADV_NEXTP_MASK   0x000FFFF0 /* Next Descriptor Index */
2344 #define IXGBE_RXDADV_NEXTP_SHIFT  0x00000004
2345 #define IXGBE_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
2346 #define IXGBE_RXD_STAT_L4CS     0x20    /* L4 xsum calculated */
2347 #define IXGBE_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
2348 #define IXGBE_RXD_STAT_PIF      0x80    /* passed in-exact filter */
2349 #define IXGBE_RXD_STAT_CRCV     0x100   /* Speculative CRC Valid */
2350 #define IXGBE_RXD_STAT_OUTERIPCS  0x100 /* Cloud IP xsum calculated */
2351 #define IXGBE_RXD_STAT_VEXT     0x200   /* 1st VLAN found */
2352 #define IXGBE_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */
2353 #define IXGBE_RXD_STAT_DYNINT   0x800   /* Pkt caused INT via DYNINT */
2354 #define IXGBE_RXD_STAT_LLINT    0x800   /* Pkt caused Low Latency Interrupt */
2355 #define IXGBE_RXD_STAT_TSIP     0x08000 /* Time Stamp in packet buffer */
2356 #define IXGBE_RXD_STAT_TS       0x10000 /* Time Stamp */
2357 #define IXGBE_RXD_STAT_SECP     0x20000 /* Security Processing */
2358 #define IXGBE_RXD_STAT_LB       0x40000 /* Loopback Status */
2359 #define IXGBE_RXD_STAT_ACK      0x8000  /* ACK Packet indication */
2360 #define IXGBE_RXD_ERR_CE        0x01    /* CRC Error */
2361 #define IXGBE_RXD_ERR_LE        0x02    /* Length Error */
2362 #define IXGBE_RXD_ERR_PE        0x08    /* Packet Error */
2363 #define IXGBE_RXD_ERR_OSE       0x10    /* Oversize Error */
2364 #define IXGBE_RXD_ERR_USE       0x20    /* Undersize Error */
2365 #define IXGBE_RXD_ERR_TCPE      0x40    /* TCP/UDP Checksum Error */
2366 #define IXGBE_RXD_ERR_IPE       0x80    /* IP Checksum Error */
2367 #define IXGBE_RXDADV_ERR_MASK           0xfff00000 /* RDESC.ERRORS mask */
2368 #define IXGBE_RXDADV_ERR_SHIFT          20         /* RDESC.ERRORS shift */
2369 #define IXGBE_RXDADV_ERR_OUTERIPER      0x04000000 /* CRC IP Header error */
2370 #define IXGBE_RXDADV_ERR_FCEOFE         0x80000000 /* FCoEFe/IPE */
2371 #define IXGBE_RXDADV_ERR_FCERR          0x00700000 /* FCERR/FDIRERR */
2372 #define IXGBE_RXDADV_ERR_FDIR_LEN       0x00100000 /* FDIR Length error */
2373 #define IXGBE_RXDADV_ERR_FDIR_DROP      0x00200000 /* FDIR Drop error */
2374 #define IXGBE_RXDADV_ERR_FDIR_COLL      0x00400000 /* FDIR Collision error */
2375 #define IXGBE_RXDADV_ERR_HBO    0x00800000 /*Header Buffer Overflow */
2376 #define IXGBE_RXDADV_ERR_CE     0x01000000 /* CRC Error */
2377 #define IXGBE_RXDADV_ERR_LE     0x02000000 /* Length Error */
2378 #define IXGBE_RXDADV_ERR_PE     0x08000000 /* Packet Error */
2379 #define IXGBE_RXDADV_ERR_OSE    0x10000000 /* Oversize Error */
2380 #define IXGBE_RXDADV_ERR_USE    0x20000000 /* Undersize Error */
2381 #define IXGBE_RXDADV_ERR_TCPE   0x40000000 /* TCP/UDP Checksum Error */
2382 #define IXGBE_RXDADV_ERR_IPE    0x80000000 /* IP Checksum Error */
2383 #define IXGBE_RXD_VLAN_ID_MASK  0x0FFF  /* VLAN ID is in lower 12 bits */
2384 #define IXGBE_RXD_PRI_MASK      0xE000  /* Priority is in upper 3 bits */
2385 #define IXGBE_RXD_PRI_SHIFT     13
2386 #define IXGBE_RXD_CFI_MASK      0x1000  /* CFI is bit 12 */
2387 #define IXGBE_RXD_CFI_SHIFT     12
2388
2389 #define IXGBE_RXDADV_STAT_DD            IXGBE_RXD_STAT_DD  /* Done */
2390 #define IXGBE_RXDADV_STAT_EOP           IXGBE_RXD_STAT_EOP /* End of Packet */
2391 #define IXGBE_RXDADV_STAT_FLM           IXGBE_RXD_STAT_FLM /* FDir Match */
2392 #define IXGBE_RXDADV_STAT_VP            IXGBE_RXD_STAT_VP  /* IEEE VLAN Pkt */
2393 #define IXGBE_RXDADV_STAT_MASK          0x000fffff /* Stat/NEXTP: bit 0-19 */
2394 #define IXGBE_RXDADV_STAT_FCEOFS        0x00000040 /* FCoE EOF/SOF Stat */
2395 #define IXGBE_RXDADV_STAT_FCSTAT        0x00000030 /* FCoE Pkt Stat */
2396 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
2397 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP  0x00000010 /* 01: Ctxt w/o DDP */
2398 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
2399 #define IXGBE_RXDADV_STAT_FCSTAT_DDP    0x00000030 /* 11: Ctxt w/ DDP */
2400 #define IXGBE_RXDADV_STAT_TS            0x00010000 /* IEEE 1588 Time Stamp */
2401
2402 /* PSRTYPE bit definitions */
2403 #define IXGBE_PSRTYPE_TCPHDR    0x00000010
2404 #define IXGBE_PSRTYPE_UDPHDR    0x00000020
2405 #define IXGBE_PSRTYPE_IPV4HDR   0x00000100
2406 #define IXGBE_PSRTYPE_IPV6HDR   0x00000200
2407 #define IXGBE_PSRTYPE_L2HDR     0x00001000
2408
2409 /* SRRCTL bit definitions */
2410 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT     10     /* so many KBs */
2411 #define IXGBE_SRRCTL_RDMTS_SHIFT        22
2412 #define IXGBE_SRRCTL_RDMTS_MASK         0x01C00000
2413 #define IXGBE_SRRCTL_DROP_EN            0x10000000
2414 #define IXGBE_SRRCTL_BSIZEPKT_MASK      0x0000007F
2415 #define IXGBE_SRRCTL_BSIZEHDR_MASK      0x00003F00
2416 #define IXGBE_SRRCTL_DESCTYPE_LEGACY    0x00000000
2417 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
2418 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT  0x04000000
2419 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
2420 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
2421 #define IXGBE_SRRCTL_DESCTYPE_MASK      0x0E000000
2422
2423 #define IXGBE_RXDPS_HDRSTAT_HDRSP       0x00008000
2424 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
2425
2426 #define IXGBE_RXDADV_RSSTYPE_MASK       0x0000000F
2427 #define IXGBE_RXDADV_PKTTYPE_MASK       0x0000FFF0
2428 #define IXGBE_RXDADV_PKTTYPE_MASK_EX    0x0001FFF0
2429 #define IXGBE_RXDADV_HDRBUFLEN_MASK     0x00007FE0
2430 #define IXGBE_RXDADV_RSCCNT_MASK        0x001E0000
2431 #define IXGBE_RXDADV_RSCCNT_SHIFT       17
2432 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT    5
2433 #define IXGBE_RXDADV_SPLITHEADER_EN     0x00001000
2434 #define IXGBE_RXDADV_SPH                0x8000
2435
2436 /* RSS Hash results */
2437 #define IXGBE_RXDADV_RSSTYPE_NONE       0x00000000
2438 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP   0x00000001
2439 #define IXGBE_RXDADV_RSSTYPE_IPV4       0x00000002
2440 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP   0x00000003
2441 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX    0x00000004
2442 #define IXGBE_RXDADV_RSSTYPE_IPV6       0x00000005
2443 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
2444 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP   0x00000007
2445 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP   0x00000008
2446 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
2447
2448 /* RSS Packet Types as indicated in the receive descriptor. */
2449 #define IXGBE_RXDADV_PKTTYPE_NONE       0x00000000
2450 #define IXGBE_RXDADV_PKTTYPE_IPV4       0x00000010 /* IPv4 hdr present */
2451 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX    0x00000020 /* IPv4 hdr + extensions */
2452 #define IXGBE_RXDADV_PKTTYPE_IPV6       0x00000040 /* IPv6 hdr present */
2453 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX    0x00000080 /* IPv6 hdr + extensions */
2454 #define IXGBE_RXDADV_PKTTYPE_TCP        0x00000100 /* TCP hdr present */
2455 #define IXGBE_RXDADV_PKTTYPE_UDP        0x00000200 /* UDP hdr present */
2456 #define IXGBE_RXDADV_PKTTYPE_SCTP       0x00000400 /* SCTP hdr present */
2457 #define IXGBE_RXDADV_PKTTYPE_NFS        0x00000800 /* NFS hdr present */
2458 #define IXGBE_RXDADV_PKTTYPE_VXLAN      0x00000800 /* VXLAN hdr present */
2459 #define IXGBE_RXDADV_PKTTYPE_TUNNEL     0x00010000 /* Tunnel type */
2460 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP  0x00001000 /* IPSec ESP */
2461 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH   0x00002000 /* IPSec AH */
2462 #define IXGBE_RXDADV_PKTTYPE_LINKSEC    0x00004000 /* LinkSec Encap */
2463 #define IXGBE_RXDADV_PKTTYPE_ETQF       0x00008000 /* PKTTYPE is ETQF index */
2464 #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK  0x00000070 /* ETQF has 8 indices */
2465 #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4          /* Right-shift 4 bits */
2466
2467 /* Security Processing bit Indication */
2468 #define IXGBE_RXDADV_LNKSEC_STATUS_SECP         0x00020000
2469 #define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH   0x08000000
2470 #define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR  0x10000000
2471 #define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK      0x18000000
2472 #define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG       0x18000000
2473
2474 /* Masks to determine if packets should be dropped due to frame errors */
2475 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
2476                                       IXGBE_RXD_ERR_CE | \
2477                                       IXGBE_RXD_ERR_LE | \
2478                                       IXGBE_RXD_ERR_PE | \
2479                                       IXGBE_RXD_ERR_OSE | \
2480                                       IXGBE_RXD_ERR_USE)
2481
2482 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
2483                                       IXGBE_RXDADV_ERR_CE | \
2484                                       IXGBE_RXDADV_ERR_LE | \
2485                                       IXGBE_RXDADV_ERR_PE | \
2486                                       IXGBE_RXDADV_ERR_OSE | \
2487                                       IXGBE_RXDADV_ERR_USE)
2488
2489 /* Multicast bit mask */
2490 #define IXGBE_MCSTCTRL_MFE      0x4
2491
2492 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2493 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE  8
2494 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE  8
2495 #define IXGBE_REQ_TX_BUFFER_GRANULARITY   1024
2496
2497 /* Vlan-specific macros */
2498 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK  0x0FFF /* VLAN ID in lower 12 bits */
2499 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK   0xE000 /* Priority in upper 3 bits */
2500 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT  0x000D /* Priority in upper 3 of 16 */
2501 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT  IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
2502
2503 /* SR-IOV specific macros */
2504 #define IXGBE_MBVFICR_INDEX(vf_number)   (vf_number >> 4)
2505 #define IXGBE_MBVFICR(_i)               (0x00710 + ((_i) * 4))
2506 #define IXGBE_VFLRE(_i)         ((((_i) & 1) ? 0x001C0 : 0x00600))
2507 #define IXGBE_VFLREC(_i)                (0x00700 + ((_i) * 4))
2508 /* Translated register #defines */
2509 #define IXGBE_PVFTDH(P)         (0x06010 + (0x40 * (P)))
2510 #define IXGBE_PVFTDT(P)         (0x06018 + (0x40 * (P)))
2511 #define IXGBE_PVFTDWBAL(P)      (0x06038 + (0x40 * (P)))
2512 #define IXGBE_PVFTDWBAH(P)      (0x0603C + (0x40 * (P)))
2513
2514 #define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \
2515                 (IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index)))
2516 #define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \
2517                 (IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))
2518
2519 #define IXGBE_PVFTDHN(q_per_pool, vf_number, vf_q_index) \
2520                 (IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index)))
2521 #define IXGBE_PVFTDTN(q_per_pool, vf_number, vf_q_index) \
2522                 (IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index)))
2523
2524 enum ixgbe_fdir_pballoc_type {
2525         IXGBE_FDIR_PBALLOC_NONE = 0,
2526         IXGBE_FDIR_PBALLOC_64K  = 1,
2527         IXGBE_FDIR_PBALLOC_128K = 2,
2528         IXGBE_FDIR_PBALLOC_256K = 3,
2529 };
2530 #define IXGBE_FDIR_PBALLOC_SIZE_SHIFT           16
2531
2532 /* Flow Director register values */
2533 #define IXGBE_FDIRCTRL_PBALLOC_64K              0x00000001
2534 #define IXGBE_FDIRCTRL_PBALLOC_128K             0x00000002
2535 #define IXGBE_FDIRCTRL_PBALLOC_256K             0x00000003
2536 #define IXGBE_FDIRCTRL_INIT_DONE                0x00000008
2537 #define IXGBE_FDIRCTRL_PERFECT_MATCH            0x00000010
2538 #define IXGBE_FDIRCTRL_REPORT_STATUS            0x00000020
2539 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS     0x00000080
2540 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT             8
2541 #define IXGBE_FDIRCTRL_FLEX_SHIFT               16
2542 #define IXGBE_FDIRCTRL_DROP_NO_MATCH            0x00008000
2543 #define IXGBE_FDIRCTRL_FILTERMODE_SHIFT         21
2544 #define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN       0x0001 /* bit 23:21, 001b */
2545 #define IXGBE_FDIRCTRL_FILTERMODE_CLOUD         0x0002 /* bit 23:21, 010b */
2546 #define IXGBE_FDIRCTRL_SEARCHLIM                0x00800000
2547 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT         24
2548 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK         0xF0000000
2549 #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT        28
2550
2551 #define IXGBE_FDIRTCPM_DPORTM_SHIFT             16
2552 #define IXGBE_FDIRUDPM_DPORTM_SHIFT             16
2553 #define IXGBE_FDIRIP6M_DIPM_SHIFT               16
2554 #define IXGBE_FDIRM_VLANID                      0x00000001
2555 #define IXGBE_FDIRM_VLANP                       0x00000002
2556 #define IXGBE_FDIRM_POOL                        0x00000004
2557 #define IXGBE_FDIRM_L4P                         0x00000008
2558 #define IXGBE_FDIRM_FLEX                        0x00000010
2559 #define IXGBE_FDIRM_DIPv6                       0x00000020
2560
2561 #define IXGBE_FDIRFREE_FREE_MASK                0xFFFF
2562 #define IXGBE_FDIRFREE_FREE_SHIFT               0
2563 #define IXGBE_FDIRFREE_COLL_MASK                0x7FFF0000
2564 #define IXGBE_FDIRFREE_COLL_SHIFT               16
2565 #define IXGBE_FDIRLEN_MAXLEN_MASK               0x3F
2566 #define IXGBE_FDIRLEN_MAXLEN_SHIFT              0
2567 #define IXGBE_FDIRLEN_MAXHASH_MASK              0x7FFF0000
2568 #define IXGBE_FDIRLEN_MAXHASH_SHIFT             16
2569 #define IXGBE_FDIRUSTAT_ADD_MASK                0xFFFF
2570 #define IXGBE_FDIRUSTAT_ADD_SHIFT               0
2571 #define IXGBE_FDIRUSTAT_REMOVE_MASK             0xFFFF0000
2572 #define IXGBE_FDIRUSTAT_REMOVE_SHIFT            16
2573 #define IXGBE_FDIRFSTAT_FADD_MASK               0x00FF
2574 #define IXGBE_FDIRFSTAT_FADD_SHIFT              0
2575 #define IXGBE_FDIRFSTAT_FREMOVE_MASK            0xFF00
2576 #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT           8
2577 #define IXGBE_FDIRPORT_DESTINATION_SHIFT        16
2578 #define IXGBE_FDIRVLAN_FLEX_SHIFT               16
2579 #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT       15
2580 #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT       16
2581
2582 #define IXGBE_FDIRCMD_CMD_MASK                  0x00000003
2583 #define IXGBE_FDIRCMD_CMD_ADD_FLOW              0x00000001
2584 #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW           0x00000002
2585 #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT        0x00000003
2586 #define IXGBE_FDIRCMD_FILTER_VALID              0x00000004
2587 #define IXGBE_FDIRCMD_FILTER_UPDATE             0x00000008
2588 #define IXGBE_FDIRCMD_IPv6DMATCH                0x00000010
2589 #define IXGBE_FDIRCMD_L4TYPE_UDP                0x00000020
2590 #define IXGBE_FDIRCMD_L4TYPE_TCP                0x00000040
2591 #define IXGBE_FDIRCMD_L4TYPE_SCTP               0x00000060
2592 #define IXGBE_FDIRCMD_IPV6                      0x00000080
2593 #define IXGBE_FDIRCMD_CLEARHT                   0x00000100
2594 #define IXGBE_FDIRCMD_DROP                      0x00000200
2595 #define IXGBE_FDIRCMD_INT                       0x00000400
2596 #define IXGBE_FDIRCMD_LAST                      0x00000800
2597 #define IXGBE_FDIRCMD_COLLISION                 0x00001000
2598 #define IXGBE_FDIRCMD_QUEUE_EN                  0x00008000
2599 #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT           5
2600 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT            16
2601 #define IXGBE_FDIRCMD_RX_TUNNEL_FILTER_SHIFT    23
2602 #define IXGBE_FDIRCMD_VT_POOL_SHIFT             24
2603 #define IXGBE_FDIR_INIT_DONE_POLL               10
2604 #define IXGBE_FDIRCMD_CMD_POLL                  10
2605 #define IXGBE_FDIRCMD_TUNNEL_FILTER             0x00800000
2606
2607 #define IXGBE_FDIR_DROP_QUEUE                   127
2608
2609 /* Manageablility Host Interface defines */
2610 #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH  1792 /* Num of bytes in range */
2611 #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */
2612 #define IXGBE_HI_COMMAND_TIMEOUT        500 /* Process HI command limit */
2613 #define IXGBE_HI_FLASH_ERASE_TIMEOUT    1000 /* Process Erase command limit */
2614 #define IXGBE_HI_FLASH_UPDATE_TIMEOUT   5000 /* Process Update command limit */
2615 #define IXGBE_HI_FLASH_APPLY_TIMEOUT    0 /* Process Apply command limit */
2616
2617 /* CEM Support */
2618 #define FW_CEM_HDR_LEN                  0x4
2619 #define FW_CEM_CMD_DRIVER_INFO          0xDD
2620 #define FW_CEM_CMD_DRIVER_INFO_LEN      0x5
2621 #define FW_CEM_CMD_RESERVED             0x0
2622 #define FW_CEM_UNUSED_VER               0x0
2623 #define FW_CEM_MAX_RETRIES              3
2624 #define FW_CEM_RESP_STATUS_SUCCESS      0x1
2625 #define FW_READ_SHADOW_RAM_CMD          0x31
2626 #define FW_READ_SHADOW_RAM_LEN          0x6
2627 #define FW_WRITE_SHADOW_RAM_CMD         0x33
2628 #define FW_WRITE_SHADOW_RAM_LEN         0xA /* 8 plus 1 WORD to write */
2629 #define FW_SHADOW_RAM_DUMP_CMD          0x36
2630 #define FW_SHADOW_RAM_DUMP_LEN          0
2631 #define FW_DEFAULT_CHECKSUM             0xFF /* checksum always 0xFF */
2632 #define FW_NVM_DATA_OFFSET              3
2633 #define FW_MAX_READ_BUFFER_SIZE         1024
2634 #define FW_DISABLE_RXEN_CMD             0xDE
2635 #define FW_DISABLE_RXEN_LEN             0x1
2636 #define FW_PHY_MGMT_REQ_CMD             0x20
2637 #define FW_PHY_TOKEN_REQ_CMD            0x0A
2638 #define FW_PHY_TOKEN_REQ_LEN            2
2639 #define FW_PHY_TOKEN_REQ                0
2640 #define FW_PHY_TOKEN_REL                1
2641 #define FW_PHY_TOKEN_OK                 1
2642 #define FW_PHY_TOKEN_RETRY              0x80
2643 #define FW_PHY_TOKEN_DELAY              5       /* milliseconds */
2644 #define FW_PHY_TOKEN_WAIT               5       /* seconds */
2645 #define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY)
2646 #define FW_INT_PHY_REQ_CMD              0xB
2647 #define FW_INT_PHY_REQ_LEN              10
2648 #define FW_INT_PHY_REQ_READ             0
2649 #define FW_INT_PHY_REQ_WRITE            1
2650
2651 /* Host Interface Command Structures */
2652 struct ixgbe_hic_hdr {
2653         u8 cmd;
2654         u8 buf_len;
2655         union {
2656                 u8 cmd_resv;
2657                 u8 ret_status;
2658         } cmd_or_resp;
2659         u8 checksum;
2660 };
2661
2662 struct ixgbe_hic_hdr2_req {
2663         u8 cmd;
2664         u8 buf_lenh;
2665         u8 buf_lenl;
2666         u8 checksum;
2667 };
2668
2669 struct ixgbe_hic_hdr2_rsp {
2670         u8 cmd;
2671         u8 buf_lenl;
2672         u8 buf_lenh_status;     /* 7-5: high bits of buf_len, 4-0: status */
2673         u8 checksum;
2674 };
2675
2676 union ixgbe_hic_hdr2 {
2677         struct ixgbe_hic_hdr2_req req;
2678         struct ixgbe_hic_hdr2_rsp rsp;
2679 };
2680
2681 struct ixgbe_hic_drv_info {
2682         struct ixgbe_hic_hdr hdr;
2683         u8 port_num;
2684         u8 ver_sub;
2685         u8 ver_build;
2686         u8 ver_min;
2687         u8 ver_maj;
2688         u8 pad; /* end spacing to ensure length is mult. of dword */
2689         u16 pad2; /* end spacing to ensure length is mult. of dword2 */
2690 };
2691
2692 /* These need to be dword aligned */
2693 struct ixgbe_hic_read_shadow_ram {
2694         union ixgbe_hic_hdr2 hdr;
2695         u32 address;
2696         u16 length;
2697         u16 pad2;
2698         u16 data;
2699         u16 pad3;
2700 };
2701
2702 struct ixgbe_hic_write_shadow_ram {
2703         union ixgbe_hic_hdr2 hdr;
2704         __be32 address;
2705         __be16 length;
2706         u16 pad2;
2707         u16 data;
2708         u16 pad3;
2709 };
2710
2711 struct ixgbe_hic_disable_rxen {
2712         struct ixgbe_hic_hdr hdr;
2713         u8  port_number;
2714         u8  pad2;
2715         u16 pad3;
2716 };
2717
2718 struct ixgbe_hic_phy_token_req {
2719         struct ixgbe_hic_hdr hdr;
2720         u8 port_number;
2721         u8 command_type;
2722         u16 pad;
2723 };
2724
2725 struct ixgbe_hic_internal_phy_req {
2726         struct ixgbe_hic_hdr hdr;
2727         u8 port_number;
2728         u8 command_type;
2729         __be16 address;
2730         u16 rsv1;
2731         __be32 write_data;
2732         u16 pad;
2733 } __packed;
2734
2735 struct ixgbe_hic_internal_phy_resp {
2736         struct ixgbe_hic_hdr hdr;
2737         __be32 read_data;
2738 };
2739
2740 /* Transmit Descriptor - Advanced */
2741 union ixgbe_adv_tx_desc {
2742         struct {
2743                 __le64 buffer_addr;      /* Address of descriptor's data buf */
2744                 __le32 cmd_type_len;
2745                 __le32 olinfo_status;
2746         } read;
2747         struct {
2748                 __le64 rsvd;       /* Reserved */
2749                 __le32 nxtseq_seed;
2750                 __le32 status;
2751         } wb;
2752 };
2753
2754 /* Receive Descriptor - Advanced */
2755 union ixgbe_adv_rx_desc {
2756         struct {
2757                 __le64 pkt_addr; /* Packet buffer address */
2758                 __le64 hdr_addr; /* Header buffer address */
2759         } read;
2760         struct {
2761                 struct {
2762                         union {
2763                                 __le32 data;
2764                                 struct {
2765                                         __le16 pkt_info; /* RSS, Pkt type */
2766                                         __le16 hdr_info; /* Splithdr, hdrlen */
2767                                 } hs_rss;
2768                         } lo_dword;
2769                         union {
2770                                 __le32 rss; /* RSS Hash */
2771                                 struct {
2772                                         __le16 ip_id; /* IP id */
2773                                         __le16 csum; /* Packet Checksum */
2774                                 } csum_ip;
2775                         } hi_dword;
2776                 } lower;
2777                 struct {
2778                         __le32 status_error; /* ext status/error */
2779                         __le16 length; /* Packet length */
2780                         __le16 vlan; /* VLAN tag */
2781                 } upper;
2782         } wb;  /* writeback */
2783 };
2784
2785 /* Context descriptors */
2786 struct ixgbe_adv_tx_context_desc {
2787         __le32 vlan_macip_lens;
2788         __le32 seqnum_seed;
2789         __le32 type_tucmd_mlhl;
2790         __le32 mss_l4len_idx;
2791 };
2792
2793 /* Adv Transmit Descriptor Config Masks */
2794 #define IXGBE_ADVTXD_DTALEN_MASK      0x0000FFFF /* Data buf length(bytes) */
2795 #define IXGBE_ADVTXD_MAC_LINKSEC      0x00040000 /* Insert LinkSec */
2796 #define IXGBE_ADVTXD_MAC_TSTAMP       0x00080000 /* IEEE 1588 Time Stamp */
2797 #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK   0x000003FF /* IPSec SA index */
2798 #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK    0x000001FF /* IPSec ESP length */
2799 #define IXGBE_ADVTXD_DTYP_MASK  0x00F00000 /* DTYP mask */
2800 #define IXGBE_ADVTXD_DTYP_CTXT  0x00200000 /* Advanced Context Desc */
2801 #define IXGBE_ADVTXD_DTYP_DATA  0x00300000 /* Advanced Data Descriptor */
2802 #define IXGBE_ADVTXD_DCMD_EOP   IXGBE_TXD_CMD_EOP  /* End of Packet */
2803 #define IXGBE_ADVTXD_DCMD_IFCS  IXGBE_TXD_CMD_IFCS /* Insert FCS */
2804 #define IXGBE_ADVTXD_DCMD_RS    IXGBE_TXD_CMD_RS   /* Report Status */
2805 #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000    /* DDP hdr type or iSCSI */
2806 #define IXGBE_ADVTXD_DCMD_DEXT  IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
2807 #define IXGBE_ADVTXD_DCMD_VLE   IXGBE_TXD_CMD_VLE  /* VLAN pkt enable */
2808 #define IXGBE_ADVTXD_DCMD_TSE   0x80000000 /* TCP Seg enable */
2809 #define IXGBE_ADVTXD_STAT_DD    IXGBE_TXD_STAT_DD  /* Descriptor Done */
2810 #define IXGBE_ADVTXD_STAT_SN_CRC      0x00000002 /* NXTSEQ/SEED pres in WB */
2811 #define IXGBE_ADVTXD_STAT_RSV   0x0000000C /* STA Reserved */
2812 #define IXGBE_ADVTXD_IDX_SHIFT  4 /* Adv desc Index shift */
2813 #define IXGBE_ADVTXD_CC         0x00000080 /* Check Context */
2814 #define IXGBE_ADVTXD_POPTS_SHIFT      8  /* Adv desc POPTS shift */
2815 #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
2816                                  IXGBE_ADVTXD_POPTS_SHIFT)
2817 #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
2818                                  IXGBE_ADVTXD_POPTS_SHIFT)
2819 #define IXGBE_ADVTXD_POPTS_ISCO_1ST  0x00000000 /* 1st TSO of iSCSI PDU */
2820 #define IXGBE_ADVTXD_POPTS_ISCO_MDL  0x00000800 /* Middle TSO of iSCSI PDU */
2821 #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
2822 #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */
2823 #define IXGBE_ADVTXD_POPTS_RSV       0x00002000 /* POPTS Reserved */
2824 #define IXGBE_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */
2825 #define IXGBE_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
2826 #define IXGBE_ADVTXD_VLAN_SHIFT      16  /* Adv ctxt vlan tag shift */
2827 #define IXGBE_ADVTXD_TUCMD_IPV4      0x00000400  /* IP Packet Type: 1=IPv4 */
2828 #define IXGBE_ADVTXD_TUCMD_IPV6      0x00000000  /* IP Packet Type: 0=IPv6 */
2829 #define IXGBE_ADVTXD_TUCMD_L4T_UDP   0x00000000  /* L4 Packet TYPE of UDP */
2830 #define IXGBE_ADVTXD_TUCMD_L4T_TCP   0x00000800  /* L4 Packet TYPE of TCP */
2831 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP  0x00001000  /* L4 Packet TYPE of SCTP */
2832 #define IXGBE_ADVTXD_TUCMD_L4T_RSV     0x00001800 /* RSV L4 Packet TYPE */
2833 #define IXGBE_ADVTXD_TUCMD_MKRREQ    0x00002000 /*Req requires Markers and CRC*/
2834 #define IXGBE_ADVTXD_POPTS_IPSEC      0x00000400 /* IPSec offload request */
2835 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
2836 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
2837 #define IXGBE_ADVTXT_TUCMD_FCOE      0x00008000       /* FCoE Frame Type */
2838 #define IXGBE_ADVTXD_FCOEF_SOF       (BIT(2) << 10) /* FC SOF index */
2839 #define IXGBE_ADVTXD_FCOEF_PARINC    (BIT(3) << 10) /* Rel_Off in F_CTL */
2840 #define IXGBE_ADVTXD_FCOEF_ORIE      (BIT(4) << 10) /* Orientation: End */
2841 #define IXGBE_ADVTXD_FCOEF_ORIS      (BIT(5) << 10) /* Orientation: Start */
2842 #define IXGBE_ADVTXD_FCOEF_EOF_N     (0u << 10)  /* 00: EOFn */
2843 #define IXGBE_ADVTXD_FCOEF_EOF_T     (1u << 10)  /* 01: EOFt */
2844 #define IXGBE_ADVTXD_FCOEF_EOF_NI    (2u << 10)  /* 10: EOFni */
2845 #define IXGBE_ADVTXD_FCOEF_EOF_A     (3u << 10)  /* 11: EOFa */
2846 #define IXGBE_ADVTXD_FCOEF_EOF_MASK  (3u << 10)  /* FC EOF index */
2847 #define IXGBE_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
2848 #define IXGBE_ADVTXD_MSS_SHIFT       16  /* Adv ctxt MSS shift */
2849
2850 /* Autonegotiation advertised speeds */
2851 typedef u32 ixgbe_autoneg_advertised;
2852 /* Link speed */
2853 typedef u32 ixgbe_link_speed;
2854 #define IXGBE_LINK_SPEED_UNKNOWN        0
2855 #define IXGBE_LINK_SPEED_100_FULL       0x0008
2856 #define IXGBE_LINK_SPEED_1GB_FULL       0x0020
2857 #define IXGBE_LINK_SPEED_2_5GB_FULL     0x0400
2858 #define IXGBE_LINK_SPEED_5GB_FULL       0x0800
2859 #define IXGBE_LINK_SPEED_10GB_FULL      0x0080
2860 #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
2861                                         IXGBE_LINK_SPEED_10GB_FULL)
2862 #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
2863                                         IXGBE_LINK_SPEED_1GB_FULL | \
2864                                         IXGBE_LINK_SPEED_10GB_FULL)
2865
2866 /* Flow Control Data Sheet defined values
2867  * Calculation and defines taken from 802.1bb Annex O
2868  */
2869
2870 /* BitTimes (BT) conversion */
2871 #define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
2872 #define IXGBE_B2BT(BT) (BT * 8)
2873
2874 /* Calculate Delay to respond to PFC */
2875 #define IXGBE_PFC_D     672
2876
2877 /* Calculate Cable Delay */
2878 #define IXGBE_CABLE_DC  5556 /* Delay Copper */
2879 #define IXGBE_CABLE_DO  5000 /* Delay Optical */
2880
2881 /* Calculate Interface Delay X540 */
2882 #define IXGBE_PHY_DC    25600   /* Delay 10G BASET */
2883 #define IXGBE_MAC_DC    8192    /* Delay Copper XAUI interface */
2884 #define IXGBE_XAUI_DC   (2 * 2048) /* Delay Copper Phy */
2885
2886 #define IXGBE_ID_X540   (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)
2887
2888 /* Calculate Interface Delay 82598, 82599 */
2889 #define IXGBE_PHY_D     12800
2890 #define IXGBE_MAC_D     4096
2891 #define IXGBE_XAUI_D    (2 * 1024)
2892
2893 #define IXGBE_ID        (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)
2894
2895 /* Calculate Delay incurred from higher layer */
2896 #define IXGBE_HD        6144
2897
2898 /* Calculate PCI Bus delay for low thresholds */
2899 #define IXGBE_PCI_DELAY 10000
2900
2901 /* Calculate X540 delay value in bit times */
2902 #define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \
2903                         ((36 * \
2904                           (IXGBE_B2BT(_max_frame_link) + \
2905                            IXGBE_PFC_D + \
2906                            (2 * IXGBE_CABLE_DC) + \
2907                            (2 * IXGBE_ID_X540) + \
2908                            IXGBE_HD) / 25 + 1) + \
2909                          2 * IXGBE_B2BT(_max_frame_tc))
2910
2911 /* Calculate 82599, 82598 delay value in bit times */
2912 #define IXGBE_DV(_max_frame_link, _max_frame_tc) \
2913                         ((36 * \
2914                           (IXGBE_B2BT(_max_frame_link) + \
2915                            IXGBE_PFC_D + \
2916                            (2 * IXGBE_CABLE_DC) + \
2917                            (2 * IXGBE_ID) + \
2918                            IXGBE_HD) / 25 + 1) + \
2919                          2 * IXGBE_B2BT(_max_frame_tc))
2920
2921 /* Calculate low threshold delay values */
2922 #define IXGBE_LOW_DV_X540(_max_frame_tc) \
2923                         (2 * IXGBE_B2BT(_max_frame_tc) + \
2924                         (36 * IXGBE_PCI_DELAY / 25) + 1)
2925 #define IXGBE_LOW_DV(_max_frame_tc) \
2926                         (2 * IXGBE_LOW_DV_X540(_max_frame_tc))
2927
2928 /* Software ATR hash keys */
2929 #define IXGBE_ATR_BUCKET_HASH_KEY    0x3DAD14E2
2930 #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
2931
2932 /* Software ATR input stream values and masks */
2933 #define IXGBE_ATR_HASH_MASK             0x7fff
2934 #define IXGBE_ATR_L4TYPE_MASK           0x3
2935 #define IXGBE_ATR_L4TYPE_UDP            0x1
2936 #define IXGBE_ATR_L4TYPE_TCP            0x2
2937 #define IXGBE_ATR_L4TYPE_SCTP           0x3
2938 #define IXGBE_ATR_L4TYPE_IPV6_MASK      0x4
2939 #define IXGBE_ATR_L4TYPE_TUNNEL_MASK    0x10
2940 enum ixgbe_atr_flow_type {
2941         IXGBE_ATR_FLOW_TYPE_IPV4   = 0x0,
2942         IXGBE_ATR_FLOW_TYPE_UDPV4  = 0x1,
2943         IXGBE_ATR_FLOW_TYPE_TCPV4  = 0x2,
2944         IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
2945         IXGBE_ATR_FLOW_TYPE_IPV6   = 0x4,
2946         IXGBE_ATR_FLOW_TYPE_UDPV6  = 0x5,
2947         IXGBE_ATR_FLOW_TYPE_TCPV6  = 0x6,
2948         IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
2949 };
2950
2951 /* Flow Director ATR input struct. */
2952 union ixgbe_atr_input {
2953         /*
2954          * Byte layout in order, all values with MSB first:
2955          *
2956          * vm_pool    - 1 byte
2957          * flow_type  - 1 byte
2958          * vlan_id    - 2 bytes
2959          * src_ip     - 16 bytes
2960          * dst_ip     - 16 bytes
2961          * src_port   - 2 bytes
2962          * dst_port   - 2 bytes
2963          * flex_bytes - 2 bytes
2964          * bkt_hash   - 2 bytes
2965          */
2966         struct {
2967                 u8     vm_pool;
2968                 u8     flow_type;
2969                 __be16 vlan_id;
2970                 __be32 dst_ip[4];
2971                 __be32 src_ip[4];
2972                 __be16 src_port;
2973                 __be16 dst_port;
2974                 __be16 flex_bytes;
2975                 __be16 bkt_hash;
2976         } formatted;
2977         __be32 dword_stream[11];
2978 };
2979
2980 /* Flow Director compressed ATR hash input struct */
2981 union ixgbe_atr_hash_dword {
2982         struct {
2983                 u8 vm_pool;
2984                 u8 flow_type;
2985                 __be16 vlan_id;
2986         } formatted;
2987         __be32 ip;
2988         struct {
2989                 __be16 src;
2990                 __be16 dst;
2991         } port;
2992         __be16 flex_bytes;
2993         __be32 dword;
2994 };
2995
2996 #define IXGBE_MVALS_INIT(m)             \
2997         IXGBE_CAT(EEC, m),              \
2998         IXGBE_CAT(FLA, m),              \
2999         IXGBE_CAT(GRC, m),              \
3000         IXGBE_CAT(FACTPS, m),           \
3001         IXGBE_CAT(SWSM, m),             \
3002         IXGBE_CAT(SWFW_SYNC, m),        \
3003         IXGBE_CAT(FWSM, m),             \
3004         IXGBE_CAT(SDP0_GPIEN, m),       \
3005         IXGBE_CAT(SDP1_GPIEN, m),       \
3006         IXGBE_CAT(SDP2_GPIEN, m),       \
3007         IXGBE_CAT(EICR_GPI_SDP0, m),    \
3008         IXGBE_CAT(EICR_GPI_SDP1, m),    \
3009         IXGBE_CAT(EICR_GPI_SDP2, m),    \
3010         IXGBE_CAT(CIAA, m),             \
3011         IXGBE_CAT(CIAD, m),             \
3012         IXGBE_CAT(I2C_CLK_IN, m),       \
3013         IXGBE_CAT(I2C_CLK_OUT, m),      \
3014         IXGBE_CAT(I2C_DATA_IN, m),      \
3015         IXGBE_CAT(I2C_DATA_OUT, m),     \
3016         IXGBE_CAT(I2C_DATA_OE_N_EN, m), \
3017         IXGBE_CAT(I2C_BB_EN, m),        \
3018         IXGBE_CAT(I2C_CLK_OE_N_EN, m),  \
3019         IXGBE_CAT(I2CCTL, m)
3020
3021 enum ixgbe_mvals {
3022         IXGBE_MVALS_INIT(IDX),
3023         IXGBE_MVALS_IDX_LIMIT
3024 };
3025
3026 enum ixgbe_eeprom_type {
3027         ixgbe_eeprom_uninitialized = 0,
3028         ixgbe_eeprom_spi,
3029         ixgbe_flash,
3030         ixgbe_eeprom_none /* No NVM support */
3031 };
3032
3033 enum ixgbe_mac_type {
3034         ixgbe_mac_unknown = 0,
3035         ixgbe_mac_82598EB,
3036         ixgbe_mac_82599EB,
3037         ixgbe_mac_X540,
3038         ixgbe_mac_X550,
3039         ixgbe_mac_X550EM_x,
3040         ixgbe_mac_x550em_a,
3041         ixgbe_num_macs
3042 };
3043
3044 enum ixgbe_phy_type {
3045         ixgbe_phy_unknown = 0,
3046         ixgbe_phy_none,
3047         ixgbe_phy_tn,
3048         ixgbe_phy_aq,
3049         ixgbe_phy_x550em_kr,
3050         ixgbe_phy_x550em_kx4,
3051         ixgbe_phy_x550em_ext_t,
3052         ixgbe_phy_cu_unknown,
3053         ixgbe_phy_qt,
3054         ixgbe_phy_xaui,
3055         ixgbe_phy_nl,
3056         ixgbe_phy_sfp_passive_tyco,
3057         ixgbe_phy_sfp_passive_unknown,
3058         ixgbe_phy_sfp_active_unknown,
3059         ixgbe_phy_sfp_avago,
3060         ixgbe_phy_sfp_ftl,
3061         ixgbe_phy_sfp_ftl_active,
3062         ixgbe_phy_sfp_unknown,
3063         ixgbe_phy_sfp_intel,
3064         ixgbe_phy_qsfp_passive_unknown,
3065         ixgbe_phy_qsfp_active_unknown,
3066         ixgbe_phy_qsfp_intel,
3067         ixgbe_phy_qsfp_unknown,
3068         ixgbe_phy_sfp_unsupported,
3069         ixgbe_phy_sgmii,
3070         ixgbe_phy_generic
3071 };
3072
3073 /*
3074  * SFP+ module type IDs:
3075  *
3076  * ID   Module Type
3077  * =============
3078  * 0    SFP_DA_CU
3079  * 1    SFP_SR
3080  * 2    SFP_LR
3081  * 3    SFP_DA_CU_CORE0 - 82599-specific
3082  * 4    SFP_DA_CU_CORE1 - 82599-specific
3083  * 5    SFP_SR/LR_CORE0 - 82599-specific
3084  * 6    SFP_SR/LR_CORE1 - 82599-specific
3085  */
3086 enum ixgbe_sfp_type {
3087         ixgbe_sfp_type_da_cu = 0,
3088         ixgbe_sfp_type_sr = 1,
3089         ixgbe_sfp_type_lr = 2,
3090         ixgbe_sfp_type_da_cu_core0 = 3,
3091         ixgbe_sfp_type_da_cu_core1 = 4,
3092         ixgbe_sfp_type_srlr_core0 = 5,
3093         ixgbe_sfp_type_srlr_core1 = 6,
3094         ixgbe_sfp_type_da_act_lmt_core0 = 7,
3095         ixgbe_sfp_type_da_act_lmt_core1 = 8,
3096         ixgbe_sfp_type_1g_cu_core0 = 9,
3097         ixgbe_sfp_type_1g_cu_core1 = 10,
3098         ixgbe_sfp_type_1g_sx_core0 = 11,
3099         ixgbe_sfp_type_1g_sx_core1 = 12,
3100         ixgbe_sfp_type_1g_lx_core0 = 13,
3101         ixgbe_sfp_type_1g_lx_core1 = 14,
3102         ixgbe_sfp_type_not_present = 0xFFFE,
3103         ixgbe_sfp_type_unknown = 0xFFFF
3104 };
3105
3106 enum ixgbe_media_type {
3107         ixgbe_media_type_unknown = 0,
3108         ixgbe_media_type_fiber,
3109         ixgbe_media_type_fiber_qsfp,
3110         ixgbe_media_type_fiber_lco,
3111         ixgbe_media_type_copper,
3112         ixgbe_media_type_backplane,
3113         ixgbe_media_type_cx4,
3114         ixgbe_media_type_virtual
3115 };
3116
3117 /* Flow Control Settings */
3118 enum ixgbe_fc_mode {
3119         ixgbe_fc_none = 0,
3120         ixgbe_fc_rx_pause,
3121         ixgbe_fc_tx_pause,
3122         ixgbe_fc_full,
3123         ixgbe_fc_default
3124 };
3125
3126 /* Smart Speed Settings */
3127 #define IXGBE_SMARTSPEED_MAX_RETRIES    3
3128 enum ixgbe_smart_speed {
3129         ixgbe_smart_speed_auto = 0,
3130         ixgbe_smart_speed_on,
3131         ixgbe_smart_speed_off
3132 };
3133
3134 /* PCI bus types */
3135 enum ixgbe_bus_type {
3136         ixgbe_bus_type_unknown = 0,
3137         ixgbe_bus_type_pci_express,
3138         ixgbe_bus_type_internal,
3139         ixgbe_bus_type_reserved
3140 };
3141
3142 /* PCI bus speeds */
3143 enum ixgbe_bus_speed {
3144         ixgbe_bus_speed_unknown = 0,
3145         ixgbe_bus_speed_33      = 33,
3146         ixgbe_bus_speed_66      = 66,
3147         ixgbe_bus_speed_100     = 100,
3148         ixgbe_bus_speed_120     = 120,
3149         ixgbe_bus_speed_133     = 133,
3150         ixgbe_bus_speed_2500    = 2500,
3151         ixgbe_bus_speed_5000    = 5000,
3152         ixgbe_bus_speed_8000    = 8000,
3153         ixgbe_bus_speed_reserved
3154 };
3155
3156 /* PCI bus widths */
3157 enum ixgbe_bus_width {
3158         ixgbe_bus_width_unknown = 0,
3159         ixgbe_bus_width_pcie_x1 = 1,
3160         ixgbe_bus_width_pcie_x2 = 2,
3161         ixgbe_bus_width_pcie_x4 = 4,
3162         ixgbe_bus_width_pcie_x8 = 8,
3163         ixgbe_bus_width_32      = 32,
3164         ixgbe_bus_width_64      = 64,
3165         ixgbe_bus_width_reserved
3166 };
3167
3168 struct ixgbe_addr_filter_info {
3169         u32 num_mc_addrs;
3170         u32 rar_used_count;
3171         u32 mta_in_use;
3172         u32 overflow_promisc;
3173         bool uc_set_promisc;
3174         bool user_set_promisc;
3175 };
3176
3177 /* Bus parameters */
3178 struct ixgbe_bus_info {
3179         enum ixgbe_bus_speed speed;
3180         enum ixgbe_bus_width width;
3181         enum ixgbe_bus_type type;
3182
3183         u8 func;
3184         u8 lan_id;
3185         u8 instance_id;
3186 };
3187
3188 /* Flow control parameters */
3189 struct ixgbe_fc_info {
3190         u32 high_water[MAX_TRAFFIC_CLASS]; /* Flow Control High-water */
3191         u32 low_water[MAX_TRAFFIC_CLASS]; /* Flow Control Low-water */
3192         u16 pause_time; /* Flow Control Pause timer */
3193         bool send_xon; /* Flow control send XON */
3194         bool strict_ieee; /* Strict IEEE mode */
3195         bool disable_fc_autoneg; /* Do not autonegotiate FC */
3196         bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
3197         enum ixgbe_fc_mode current_mode; /* FC mode in effect */
3198         enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
3199 };
3200
3201 /* Statistics counters collected by the MAC */
3202 struct ixgbe_hw_stats {
3203         u64 crcerrs;
3204         u64 illerrc;
3205         u64 errbc;
3206         u64 mspdc;
3207         u64 mpctotal;
3208         u64 mpc[8];
3209         u64 mlfc;
3210         u64 mrfc;
3211         u64 rlec;
3212         u64 lxontxc;
3213         u64 lxonrxc;
3214         u64 lxofftxc;
3215         u64 lxoffrxc;
3216         u64 pxontxc[8];
3217         u64 pxonrxc[8];
3218         u64 pxofftxc[8];
3219         u64 pxoffrxc[8];
3220         u64 prc64;
3221         u64 prc127;
3222         u64 prc255;
3223         u64 prc511;
3224         u64 prc1023;
3225         u64 prc1522;
3226         u64 gprc;
3227         u64 bprc;
3228         u64 mprc;
3229         u64 gptc;
3230         u64 gorc;
3231         u64 gotc;
3232         u64 rnbc[8];
3233         u64 ruc;
3234         u64 rfc;
3235         u64 roc;
3236         u64 rjc;
3237         u64 mngprc;
3238         u64 mngpdc;
3239         u64 mngptc;
3240         u64 tor;
3241         u64 tpr;
3242         u64 tpt;
3243         u64 ptc64;
3244         u64 ptc127;
3245         u64 ptc255;
3246         u64 ptc511;
3247         u64 ptc1023;
3248         u64 ptc1522;
3249         u64 mptc;
3250         u64 bptc;
3251         u64 xec;
3252         u64 rqsmr[16];
3253         u64 tqsmr[8];
3254         u64 qprc[16];
3255         u64 qptc[16];
3256         u64 qbrc[16];
3257         u64 qbtc[16];
3258         u64 qprdc[16];
3259         u64 pxon2offc[8];
3260         u64 fdirustat_add;
3261         u64 fdirustat_remove;
3262         u64 fdirfstat_fadd;
3263         u64 fdirfstat_fremove;
3264         u64 fdirmatch;
3265         u64 fdirmiss;
3266         u64 fccrc;
3267         u64 fcoerpdc;
3268         u64 fcoeprc;
3269         u64 fcoeptc;
3270         u64 fcoedwrc;
3271         u64 fcoedwtc;
3272         u64 fcoe_noddp;
3273         u64 fcoe_noddp_ext_buff;
3274         u64 b2ospc;
3275         u64 b2ogprc;
3276         u64 o2bgptc;
3277         u64 o2bspc;
3278 };
3279
3280 /* forward declaration */
3281 struct ixgbe_hw;
3282
3283 /* iterator type for walking multicast address lists */
3284 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
3285                                   u32 *vmdq);
3286
3287 /* Function pointer table */
3288 struct ixgbe_eeprom_operations {
3289         s32 (*init_params)(struct ixgbe_hw *);
3290         s32 (*read)(struct ixgbe_hw *, u16, u16 *);
3291         s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
3292         s32 (*write)(struct ixgbe_hw *, u16, u16);
3293         s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
3294         s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
3295         s32 (*update_checksum)(struct ixgbe_hw *);
3296         s32 (*calc_checksum)(struct ixgbe_hw *);
3297 };
3298
3299 struct ixgbe_mac_operations {
3300         s32 (*init_hw)(struct ixgbe_hw *);
3301         s32 (*reset_hw)(struct ixgbe_hw *);
3302         s32 (*start_hw)(struct ixgbe_hw *);
3303         s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
3304         enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
3305         s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
3306         s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
3307         s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
3308         s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
3309         s32 (*stop_adapter)(struct ixgbe_hw *);
3310         s32 (*get_bus_info)(struct ixgbe_hw *);
3311         void (*set_lan_id)(struct ixgbe_hw *);
3312         s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
3313         s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
3314         s32 (*setup_sfp)(struct ixgbe_hw *);
3315         s32 (*disable_rx_buff)(struct ixgbe_hw *);
3316         s32 (*enable_rx_buff)(struct ixgbe_hw *);
3317         s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
3318         s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32);
3319         void (*release_swfw_sync)(struct ixgbe_hw *, u32);
3320         void (*init_swfw_sync)(struct ixgbe_hw *);
3321         s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);
3322         s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);
3323
3324         /* Link */
3325         void (*disable_tx_laser)(struct ixgbe_hw *);
3326         void (*enable_tx_laser)(struct ixgbe_hw *);
3327         void (*flap_tx_laser)(struct ixgbe_hw *);
3328         void (*stop_link_on_d3)(struct ixgbe_hw *);
3329         s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3330         s32 (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3331         s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
3332         s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
3333                                      bool *);
3334         void (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed);
3335
3336         /* Packet Buffer Manipulation */
3337         void (*set_rxpba)(struct ixgbe_hw *, int, u32, int);
3338
3339         /* LED */
3340         s32 (*led_on)(struct ixgbe_hw *, u32);
3341         s32 (*led_off)(struct ixgbe_hw *, u32);
3342         s32 (*blink_led_start)(struct ixgbe_hw *, u32);
3343         s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
3344
3345         /* RAR, Multicast, VLAN */
3346         s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
3347         s32 (*clear_rar)(struct ixgbe_hw *, u32);
3348         s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
3349         s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
3350         s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
3351         s32 (*init_rx_addrs)(struct ixgbe_hw *);
3352         s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *);
3353         s32 (*enable_mc)(struct ixgbe_hw *);
3354         s32 (*disable_mc)(struct ixgbe_hw *);
3355         s32 (*clear_vfta)(struct ixgbe_hw *);
3356         s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool, bool);
3357         s32 (*init_uta_tables)(struct ixgbe_hw *);
3358         void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
3359         void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
3360
3361         /* Flow Control */
3362         s32 (*fc_enable)(struct ixgbe_hw *);
3363         s32 (*setup_fc)(struct ixgbe_hw *);
3364
3365         /* Manageability interface */
3366         s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
3367         s32 (*get_thermal_sensor_data)(struct ixgbe_hw *);
3368         s32 (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw);
3369         void (*disable_rx)(struct ixgbe_hw *hw);
3370         void (*enable_rx)(struct ixgbe_hw *hw);
3371         void (*set_source_address_pruning)(struct ixgbe_hw *, bool,
3372                                            unsigned int);
3373         void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int);
3374
3375         /* DMA Coalescing */
3376         s32 (*dmac_config)(struct ixgbe_hw *hw);
3377         s32 (*dmac_update_tcs)(struct ixgbe_hw *hw);
3378         s32 (*dmac_config_tcs)(struct ixgbe_hw *hw);
3379         s32 (*read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *);
3380         s32 (*write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32);
3381 };
3382
3383 struct ixgbe_phy_operations {
3384         s32 (*identify)(struct ixgbe_hw *);
3385         s32 (*identify_sfp)(struct ixgbe_hw *);
3386         s32 (*init)(struct ixgbe_hw *);
3387         s32 (*reset)(struct ixgbe_hw *);
3388         s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
3389         s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
3390         s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *);
3391         s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16);
3392         s32 (*setup_link)(struct ixgbe_hw *);
3393         s32 (*setup_internal_link)(struct ixgbe_hw *);
3394         s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3395         s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
3396         s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
3397         s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
3398         s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
3399         s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);
3400         s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
3401         s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
3402         s32 (*read_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);
3403         s32 (*write_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);
3404         s32 (*check_overtemp)(struct ixgbe_hw *);
3405         s32 (*set_phy_power)(struct ixgbe_hw *, bool on);
3406         s32 (*enter_lplu)(struct ixgbe_hw *);
3407         s32 (*handle_lasi)(struct ixgbe_hw *hw);
3408         s32 (*read_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
3409                                           u16 *value);
3410         s32 (*write_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
3411                                            u16 value);
3412 };
3413
3414 struct ixgbe_eeprom_info {
3415         struct ixgbe_eeprom_operations  ops;
3416         enum ixgbe_eeprom_type          type;
3417         u32                             semaphore_delay;
3418         u16                             word_size;
3419         u16                             address_bits;
3420         u16                             word_page_size;
3421         u16                             ctrl_word_3;
3422 };
3423
3424 #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED       0x01
3425 struct ixgbe_mac_info {
3426         struct ixgbe_mac_operations     ops;
3427         enum ixgbe_mac_type             type;
3428         u8                              addr[ETH_ALEN];
3429         u8                              perm_addr[ETH_ALEN];
3430         u8                              san_addr[ETH_ALEN];
3431         /* prefix for World Wide Node Name (WWNN) */
3432         u16                             wwnn_prefix;
3433         /* prefix for World Wide Port Name (WWPN) */
3434         u16                             wwpn_prefix;
3435         u16                             max_msix_vectors;
3436 #define IXGBE_MAX_MTA                   128
3437         u32                             mta_shadow[IXGBE_MAX_MTA];
3438         s32                             mc_filter_type;
3439         u32                             mcft_size;
3440         u32                             vft_size;
3441         u32                             num_rar_entries;
3442         u32                             rar_highwater;
3443         u32                             rx_pb_size;
3444         u32                             max_tx_queues;
3445         u32                             max_rx_queues;
3446         u32                             orig_autoc;
3447         u32                             orig_autoc2;
3448         bool                            orig_link_settings_stored;
3449         bool                            autotry_restart;
3450         u8                              flags;
3451         u8                              san_mac_rar_index;
3452         struct ixgbe_thermal_sensor_data  thermal_sensor_data;
3453         bool                            set_lben;
3454 };
3455
3456 struct ixgbe_phy_info {
3457         struct ixgbe_phy_operations     ops;
3458         struct mdio_if_info             mdio;
3459         enum ixgbe_phy_type             type;
3460         u32                             id;
3461         enum ixgbe_sfp_type             sfp_type;
3462         bool                            sfp_setup_needed;
3463         u32                             revision;
3464         enum ixgbe_media_type           media_type;
3465         u32                             phy_semaphore_mask;
3466         bool                            reset_disable;
3467         ixgbe_autoneg_advertised        autoneg_advertised;
3468         ixgbe_link_speed                speeds_supported;
3469         enum ixgbe_smart_speed          smart_speed;
3470         bool                            smart_speed_active;
3471         bool                            multispeed_fiber;
3472         bool                            reset_if_overtemp;
3473         bool                            qsfp_shared_i2c_bus;
3474         u32                             nw_mng_if_sel;
3475 };
3476
3477 #include "ixgbe_mbx.h"
3478
3479 struct ixgbe_mbx_operations {
3480         s32 (*init_params)(struct ixgbe_hw *hw);
3481         s32 (*read)(struct ixgbe_hw *, u32 *, u16,  u16);
3482         s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);
3483         s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16,  u16);
3484         s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
3485         s32 (*check_for_msg)(struct ixgbe_hw *, u16);
3486         s32 (*check_for_ack)(struct ixgbe_hw *, u16);
3487         s32 (*check_for_rst)(struct ixgbe_hw *, u16);
3488 };
3489
3490 struct ixgbe_mbx_stats {
3491         u32 msgs_tx;
3492         u32 msgs_rx;
3493
3494         u32 acks;
3495         u32 reqs;
3496         u32 rsts;
3497 };
3498
3499 struct ixgbe_mbx_info {
3500         const struct ixgbe_mbx_operations *ops;
3501         struct ixgbe_mbx_stats stats;
3502         u32 timeout;
3503         u32 usec_delay;
3504         u32 v2p_mailbox;
3505         u16 size;
3506 };
3507
3508 struct ixgbe_hw {
3509         u8 __iomem                      *hw_addr;
3510         void                            *back;
3511         struct ixgbe_mac_info           mac;
3512         struct ixgbe_addr_filter_info   addr_ctrl;
3513         struct ixgbe_fc_info            fc;
3514         struct ixgbe_phy_info           phy;
3515         struct ixgbe_eeprom_info        eeprom;
3516         struct ixgbe_bus_info           bus;
3517         struct ixgbe_mbx_info           mbx;
3518         const u32                       *mvals;
3519         u16                             device_id;
3520         u16                             vendor_id;
3521         u16                             subsystem_device_id;
3522         u16                             subsystem_vendor_id;
3523         u8                              revision_id;
3524         bool                            adapter_stopped;
3525         bool                            force_full_reset;
3526         bool                            allow_unsupported_sfp;
3527         bool                            wol_enabled;
3528         bool                            need_crosstalk_fix;
3529 };
3530
3531 struct ixgbe_info {
3532         enum ixgbe_mac_type             mac;
3533         s32                             (*get_invariants)(struct ixgbe_hw *);
3534         const struct ixgbe_mac_operations       *mac_ops;
3535         const struct ixgbe_eeprom_operations    *eeprom_ops;
3536         const struct ixgbe_phy_operations       *phy_ops;
3537         const struct ixgbe_mbx_operations       *mbx_ops;
3538         const u32                       *mvals;
3539 };
3540
3541
3542 /* Error Codes */
3543 #define IXGBE_ERR_EEPROM                        -1
3544 #define IXGBE_ERR_EEPROM_CHECKSUM               -2
3545 #define IXGBE_ERR_PHY                           -3
3546 #define IXGBE_ERR_CONFIG                        -4
3547 #define IXGBE_ERR_PARAM                         -5
3548 #define IXGBE_ERR_MAC_TYPE                      -6
3549 #define IXGBE_ERR_UNKNOWN_PHY                   -7
3550 #define IXGBE_ERR_LINK_SETUP                    -8
3551 #define IXGBE_ERR_ADAPTER_STOPPED               -9
3552 #define IXGBE_ERR_INVALID_MAC_ADDR              -10
3553 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED          -11
3554 #define IXGBE_ERR_MASTER_REQUESTS_PENDING       -12
3555 #define IXGBE_ERR_INVALID_LINK_SETTINGS         -13
3556 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE          -14
3557 #define IXGBE_ERR_RESET_FAILED                  -15
3558 #define IXGBE_ERR_SWFW_SYNC                     -16
3559 #define IXGBE_ERR_PHY_ADDR_INVALID              -17
3560 #define IXGBE_ERR_I2C                           -18
3561 #define IXGBE_ERR_SFP_NOT_SUPPORTED             -19
3562 #define IXGBE_ERR_SFP_NOT_PRESENT               -20
3563 #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT       -21
3564 #define IXGBE_ERR_NO_SAN_ADDR_PTR               -22
3565 #define IXGBE_ERR_FDIR_REINIT_FAILED            -23
3566 #define IXGBE_ERR_EEPROM_VERSION                -24
3567 #define IXGBE_ERR_NO_SPACE                      -25
3568 #define IXGBE_ERR_OVERTEMP                      -26
3569 #define IXGBE_ERR_FC_NOT_NEGOTIATED             -27
3570 #define IXGBE_ERR_FC_NOT_SUPPORTED              -28
3571 #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE        -30
3572 #define IXGBE_ERR_PBA_SECTION                   -31
3573 #define IXGBE_ERR_INVALID_ARGUMENT              -32
3574 #define IXGBE_ERR_HOST_INTERFACE_COMMAND        -33
3575 #define IXGBE_ERR_FDIR_CMD_INCOMPLETE           -38
3576 #define IXGBE_ERR_FW_RESP_INVALID               -39
3577 #define IXGBE_ERR_TOKEN_RETRY                   -40
3578 #define IXGBE_NOT_IMPLEMENTED                   0x7FFFFFFF
3579
3580 #define IXGBE_FUSES0_GROUP(_i)          (0x11158 + ((_i) * 4))
3581 #define IXGBE_FUSES0_300MHZ             BIT(5)
3582 #define IXGBE_FUSES0_REV_MASK           (3u << 6)
3583
3584 #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P)  ((P) ? 0x8010 : 0x4010)
3585 #define IXGBE_KRM_LINK_CTRL_1(P)        ((P) ? 0x820C : 0x420C)
3586 #define IXGBE_KRM_AN_CNTL_1(P)          ((P) ? 0x822C : 0x422C)
3587 #define IXGBE_KRM_AN_CNTL_8(P)          ((P) ? 0x8248 : 0x4248)
3588 #define IXGBE_KRM_SGMII_CTRL(P)         ((P) ? 0x82A0 : 0x42A0)
3589 #define IXGBE_KRM_DSP_TXFFE_STATE_4(P)  ((P) ? 0x8634 : 0x4634)
3590 #define IXGBE_KRM_DSP_TXFFE_STATE_5(P)  ((P) ? 0x8638 : 0x4638)
3591 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00)
3592 #define IXGBE_KRM_PMD_DFX_BURNIN(P)     ((P) ? 0x8E00 : 0x4E00)
3593 #define IXGBE_KRM_TX_COEFF_CTRL_1(P)    ((P) ? 0x9520 : 0x5520)
3594 #define IXGBE_KRM_RX_ANA_CTL(P)         ((P) ? 0x9A00 : 0x5A00)
3595
3596 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B            BIT(9)
3597 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS          BIT(11)
3598
3599 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK     (7u << 8)
3600 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G       (2u << 8)
3601 #define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G      (4u << 8)
3602 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN          BIT(12)
3603 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN      BIT(13)
3604 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ           BIT(14)
3605 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC           BIT(15)
3606 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX            BIT(16)
3607 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR            BIT(18)
3608 #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX           BIT(24)
3609 #define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR           BIT(26)
3610 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE            BIT(29)
3611 #define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART           BIT(31)
3612
3613 #define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE                   BIT(28)
3614 #define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE                   BIT(29)
3615
3616 #define IXGBE_KRM_AN_CNTL_8_LINEAR                      BIT(0)
3617 #define IXGBE_KRM_AN_CNTL_8_LIMITING                    BIT(1)
3618
3619 #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D        BIT(12)
3620 #define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D         BIT(19)
3621
3622 #define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN                 BIT(6)
3623 #define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN            BIT(15)
3624 #define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN           BIT(16)
3625
3626 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL   BIT(4)
3627 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS    BIT(2)
3628
3629 #define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK       (3u << 16)
3630
3631 #define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN      BIT(1)
3632 #define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN       BIT(2)
3633 #define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN              BIT(3)
3634 #define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN              BIT(31)
3635
3636 #define IXGBE_KX4_LINK_CNTL_1                           0x4C
3637 #define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX            BIT(16)
3638 #define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4           BIT(17)
3639 #define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX           BIT(24)
3640 #define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX4          BIT(25)
3641 #define IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE            BIT(29)
3642 #define IXGBE_KX4_LINK_CNTL_1_TETH_FORCE_LINK_UP        BIT(30)
3643 #define IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART           BIT(31)
3644
3645 #define IXGBE_SB_IOSF_INDIRECT_CTRL             0x00011144
3646 #define IXGBE_SB_IOSF_INDIRECT_DATA             0x00011148
3647
3648 #define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT           0
3649 #define IXGBE_SB_IOSF_CTRL_ADDR_MASK            0xFF
3650 #define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT      18
3651 #define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \
3652                                 (0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT)
3653 #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT       20
3654 #define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK \
3655                                 (0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)
3656 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT  28
3657 #define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK   0x7
3658 #define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT           31
3659 #define IXGBE_SB_IOSF_CTRL_BUSY         BIT(IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
3660 #define IXGBE_SB_IOSF_TARGET_KR_PHY     0
3661 #define IXGBE_SB_IOSF_TARGET_KX4_UNIPHY 1
3662 #define IXGBE_SB_IOSF_TARGET_KX4_PCS0   2
3663 #define IXGBE_SB_IOSF_TARGET_KX4_PCS1   3
3664
3665 #define IXGBE_NW_MNG_IF_SEL             0x00011178
3666 #define IXGBE_NW_MNG_IF_SEL_MDIO_ACT            BIT(1)
3667 #define IXGBE_NW_MNG_IF_SEL_ENABLE_10_100M      BIT(23)
3668 #define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE        BIT(24)
3669 #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT  3
3670 #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD        \
3671                                 (0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)
3672 #endif /* _IXGBE_TYPE_H_ */