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Merge remote-tracking branch 'omap_dss2/for-next'
[deliverable/linux.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/of_device.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_net.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/clk.h>
21 #include <linux/if_vlan.h>
22 #include <linux/reset.h>
23 #include <linux/tcp.h>
24
25 #include "mtk_eth_soc.h"
26
27 static int mtk_msg_level = -1;
28 module_param_named(msg_level, mtk_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 #define MTK_ETHTOOL_STAT(x) { #x, \
32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
33
34 /* strings used by ethtool */
35 static const struct mtk_ethtool_stats {
36 char str[ETH_GSTRING_LEN];
37 u32 offset;
38 } mtk_ethtool_stats[] = {
39 MTK_ETHTOOL_STAT(tx_bytes),
40 MTK_ETHTOOL_STAT(tx_packets),
41 MTK_ETHTOOL_STAT(tx_skip),
42 MTK_ETHTOOL_STAT(tx_collisions),
43 MTK_ETHTOOL_STAT(rx_bytes),
44 MTK_ETHTOOL_STAT(rx_packets),
45 MTK_ETHTOOL_STAT(rx_overflow),
46 MTK_ETHTOOL_STAT(rx_fcs_errors),
47 MTK_ETHTOOL_STAT(rx_short_errors),
48 MTK_ETHTOOL_STAT(rx_long_errors),
49 MTK_ETHTOOL_STAT(rx_checksum_errors),
50 MTK_ETHTOOL_STAT(rx_flow_control_packets),
51 };
52
53 static const char * const mtk_clks_source_name[] = {
54 "ethif", "esw", "gp1", "gp2"
55 };
56
57 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
58 {
59 __raw_writel(val, eth->base + reg);
60 }
61
62 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
63 {
64 return __raw_readl(eth->base + reg);
65 }
66
67 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
68 {
69 unsigned long t_start = jiffies;
70
71 while (1) {
72 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
73 return 0;
74 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
75 break;
76 usleep_range(10, 20);
77 }
78
79 dev_err(eth->dev, "mdio: MDIO timeout\n");
80 return -1;
81 }
82
83 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
84 u32 phy_register, u32 write_data)
85 {
86 if (mtk_mdio_busy_wait(eth))
87 return -1;
88
89 write_data &= 0xffff;
90
91 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
92 (phy_register << PHY_IAC_REG_SHIFT) |
93 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
94 MTK_PHY_IAC);
95
96 if (mtk_mdio_busy_wait(eth))
97 return -1;
98
99 return 0;
100 }
101
102 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
103 {
104 u32 d;
105
106 if (mtk_mdio_busy_wait(eth))
107 return 0xffff;
108
109 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
110 (phy_reg << PHY_IAC_REG_SHIFT) |
111 (phy_addr << PHY_IAC_ADDR_SHIFT),
112 MTK_PHY_IAC);
113
114 if (mtk_mdio_busy_wait(eth))
115 return 0xffff;
116
117 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
118
119 return d;
120 }
121
122 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
123 int phy_reg, u16 val)
124 {
125 struct mtk_eth *eth = bus->priv;
126
127 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
128 }
129
130 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
131 {
132 struct mtk_eth *eth = bus->priv;
133
134 return _mtk_mdio_read(eth, phy_addr, phy_reg);
135 }
136
137 static void mtk_phy_link_adjust(struct net_device *dev)
138 {
139 struct mtk_mac *mac = netdev_priv(dev);
140 u16 lcl_adv = 0, rmt_adv = 0;
141 u8 flowctrl;
142 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
143 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
144 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
145 MAC_MCR_BACKPR_EN;
146
147 switch (mac->phy_dev->speed) {
148 case SPEED_1000:
149 mcr |= MAC_MCR_SPEED_1000;
150 break;
151 case SPEED_100:
152 mcr |= MAC_MCR_SPEED_100;
153 break;
154 };
155
156 if (mac->phy_dev->link)
157 mcr |= MAC_MCR_FORCE_LINK;
158
159 if (mac->phy_dev->duplex) {
160 mcr |= MAC_MCR_FORCE_DPX;
161
162 if (mac->phy_dev->pause)
163 rmt_adv = LPA_PAUSE_CAP;
164 if (mac->phy_dev->asym_pause)
165 rmt_adv |= LPA_PAUSE_ASYM;
166
167 if (mac->phy_dev->advertising & ADVERTISED_Pause)
168 lcl_adv |= ADVERTISE_PAUSE_CAP;
169 if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause)
170 lcl_adv |= ADVERTISE_PAUSE_ASYM;
171
172 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
173
174 if (flowctrl & FLOW_CTRL_TX)
175 mcr |= MAC_MCR_FORCE_TX_FC;
176 if (flowctrl & FLOW_CTRL_RX)
177 mcr |= MAC_MCR_FORCE_RX_FC;
178
179 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
180 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
181 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
182 }
183
184 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
185
186 if (mac->phy_dev->link)
187 netif_carrier_on(dev);
188 else
189 netif_carrier_off(dev);
190 }
191
192 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
193 struct device_node *phy_node)
194 {
195 const __be32 *_addr = NULL;
196 struct phy_device *phydev;
197 int phy_mode, addr;
198
199 _addr = of_get_property(phy_node, "reg", NULL);
200
201 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
202 pr_err("%s: invalid phy address\n", phy_node->name);
203 return -EINVAL;
204 }
205 addr = be32_to_cpu(*_addr);
206 phy_mode = of_get_phy_mode(phy_node);
207 if (phy_mode < 0) {
208 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
209 return -EINVAL;
210 }
211
212 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
213 mtk_phy_link_adjust, 0, phy_mode);
214 if (!phydev) {
215 dev_err(eth->dev, "could not connect to PHY\n");
216 return -ENODEV;
217 }
218
219 dev_info(eth->dev,
220 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
221 mac->id, phydev_name(phydev), phydev->phy_id,
222 phydev->drv->name);
223
224 mac->phy_dev = phydev;
225
226 return 0;
227 }
228
229 static int mtk_phy_connect(struct mtk_mac *mac)
230 {
231 struct mtk_eth *eth = mac->hw;
232 struct device_node *np;
233 u32 val, ge_mode;
234
235 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
236 if (!np && of_phy_is_fixed_link(mac->of_node))
237 if (!of_phy_register_fixed_link(mac->of_node))
238 np = of_node_get(mac->of_node);
239 if (!np)
240 return -ENODEV;
241
242 switch (of_get_phy_mode(np)) {
243 case PHY_INTERFACE_MODE_RGMII_TXID:
244 case PHY_INTERFACE_MODE_RGMII_RXID:
245 case PHY_INTERFACE_MODE_RGMII_ID:
246 case PHY_INTERFACE_MODE_RGMII:
247 ge_mode = 0;
248 break;
249 case PHY_INTERFACE_MODE_MII:
250 ge_mode = 1;
251 break;
252 case PHY_INTERFACE_MODE_REVMII:
253 ge_mode = 2;
254 break;
255 case PHY_INTERFACE_MODE_RMII:
256 if (!mac->id)
257 goto err_phy;
258 ge_mode = 3;
259 break;
260 default:
261 goto err_phy;
262 }
263
264 /* put the gmac into the right mode */
265 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
266 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
267 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
268 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
269
270 mtk_phy_connect_node(eth, mac, np);
271 mac->phy_dev->autoneg = AUTONEG_ENABLE;
272 mac->phy_dev->speed = 0;
273 mac->phy_dev->duplex = 0;
274
275 if (of_phy_is_fixed_link(mac->of_node))
276 mac->phy_dev->supported |=
277 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
278
279 mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
280 SUPPORTED_Asym_Pause;
281 mac->phy_dev->advertising = mac->phy_dev->supported |
282 ADVERTISED_Autoneg;
283 phy_start_aneg(mac->phy_dev);
284
285 of_node_put(np);
286
287 return 0;
288
289 err_phy:
290 of_node_put(np);
291 dev_err(eth->dev, "invalid phy_mode\n");
292 return -EINVAL;
293 }
294
295 static int mtk_mdio_init(struct mtk_eth *eth)
296 {
297 struct device_node *mii_np;
298 int ret;
299
300 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
301 if (!mii_np) {
302 dev_err(eth->dev, "no %s child node found", "mdio-bus");
303 return -ENODEV;
304 }
305
306 if (!of_device_is_available(mii_np)) {
307 ret = -ENODEV;
308 goto err_put_node;
309 }
310
311 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
312 if (!eth->mii_bus) {
313 ret = -ENOMEM;
314 goto err_put_node;
315 }
316
317 eth->mii_bus->name = "mdio";
318 eth->mii_bus->read = mtk_mdio_read;
319 eth->mii_bus->write = mtk_mdio_write;
320 eth->mii_bus->priv = eth;
321 eth->mii_bus->parent = eth->dev;
322
323 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
324 ret = of_mdiobus_register(eth->mii_bus, mii_np);
325
326 err_put_node:
327 of_node_put(mii_np);
328 return ret;
329 }
330
331 static void mtk_mdio_cleanup(struct mtk_eth *eth)
332 {
333 if (!eth->mii_bus)
334 return;
335
336 mdiobus_unregister(eth->mii_bus);
337 }
338
339 static inline void mtk_irq_disable(struct mtk_eth *eth,
340 unsigned reg, u32 mask)
341 {
342 unsigned long flags;
343 u32 val;
344
345 spin_lock_irqsave(&eth->irq_lock, flags);
346 val = mtk_r32(eth, reg);
347 mtk_w32(eth, val & ~mask, reg);
348 spin_unlock_irqrestore(&eth->irq_lock, flags);
349 }
350
351 static inline void mtk_irq_enable(struct mtk_eth *eth,
352 unsigned reg, u32 mask)
353 {
354 unsigned long flags;
355 u32 val;
356
357 spin_lock_irqsave(&eth->irq_lock, flags);
358 val = mtk_r32(eth, reg);
359 mtk_w32(eth, val | mask, reg);
360 spin_unlock_irqrestore(&eth->irq_lock, flags);
361 }
362
363 static int mtk_set_mac_address(struct net_device *dev, void *p)
364 {
365 int ret = eth_mac_addr(dev, p);
366 struct mtk_mac *mac = netdev_priv(dev);
367 const char *macaddr = dev->dev_addr;
368
369 if (ret)
370 return ret;
371
372 spin_lock_bh(&mac->hw->page_lock);
373 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
374 MTK_GDMA_MAC_ADRH(mac->id));
375 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
376 (macaddr[4] << 8) | macaddr[5],
377 MTK_GDMA_MAC_ADRL(mac->id));
378 spin_unlock_bh(&mac->hw->page_lock);
379
380 return 0;
381 }
382
383 void mtk_stats_update_mac(struct mtk_mac *mac)
384 {
385 struct mtk_hw_stats *hw_stats = mac->hw_stats;
386 unsigned int base = MTK_GDM1_TX_GBCNT;
387 u64 stats;
388
389 base += hw_stats->reg_offset;
390
391 u64_stats_update_begin(&hw_stats->syncp);
392
393 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
394 stats = mtk_r32(mac->hw, base + 0x04);
395 if (stats)
396 hw_stats->rx_bytes += (stats << 32);
397 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
398 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
399 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
400 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
401 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
402 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
403 hw_stats->rx_flow_control_packets +=
404 mtk_r32(mac->hw, base + 0x24);
405 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
406 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
407 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
408 stats = mtk_r32(mac->hw, base + 0x34);
409 if (stats)
410 hw_stats->tx_bytes += (stats << 32);
411 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
412 u64_stats_update_end(&hw_stats->syncp);
413 }
414
415 static void mtk_stats_update(struct mtk_eth *eth)
416 {
417 int i;
418
419 for (i = 0; i < MTK_MAC_COUNT; i++) {
420 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
421 continue;
422 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
423 mtk_stats_update_mac(eth->mac[i]);
424 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
425 }
426 }
427 }
428
429 static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
430 struct rtnl_link_stats64 *storage)
431 {
432 struct mtk_mac *mac = netdev_priv(dev);
433 struct mtk_hw_stats *hw_stats = mac->hw_stats;
434 unsigned int start;
435
436 if (netif_running(dev) && netif_device_present(dev)) {
437 if (spin_trylock(&hw_stats->stats_lock)) {
438 mtk_stats_update_mac(mac);
439 spin_unlock(&hw_stats->stats_lock);
440 }
441 }
442
443 do {
444 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
445 storage->rx_packets = hw_stats->rx_packets;
446 storage->tx_packets = hw_stats->tx_packets;
447 storage->rx_bytes = hw_stats->rx_bytes;
448 storage->tx_bytes = hw_stats->tx_bytes;
449 storage->collisions = hw_stats->tx_collisions;
450 storage->rx_length_errors = hw_stats->rx_short_errors +
451 hw_stats->rx_long_errors;
452 storage->rx_over_errors = hw_stats->rx_overflow;
453 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
454 storage->rx_errors = hw_stats->rx_checksum_errors;
455 storage->tx_aborted_errors = hw_stats->tx_skip;
456 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
457
458 storage->tx_errors = dev->stats.tx_errors;
459 storage->rx_dropped = dev->stats.rx_dropped;
460 storage->tx_dropped = dev->stats.tx_dropped;
461
462 return storage;
463 }
464
465 static inline int mtk_max_frag_size(int mtu)
466 {
467 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
468 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
469 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
470
471 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
472 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
473 }
474
475 static inline int mtk_max_buf_size(int frag_size)
476 {
477 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
478 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
479
480 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
481
482 return buf_size;
483 }
484
485 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
486 struct mtk_rx_dma *dma_rxd)
487 {
488 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
489 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
490 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
491 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
492 }
493
494 /* the qdma core needs scratch memory to be setup */
495 static int mtk_init_fq_dma(struct mtk_eth *eth)
496 {
497 dma_addr_t phy_ring_tail;
498 int cnt = MTK_DMA_SIZE;
499 dma_addr_t dma_addr;
500 int i;
501
502 eth->scratch_ring = dma_alloc_coherent(eth->dev,
503 cnt * sizeof(struct mtk_tx_dma),
504 &eth->phy_scratch_ring,
505 GFP_ATOMIC | __GFP_ZERO);
506 if (unlikely(!eth->scratch_ring))
507 return -ENOMEM;
508
509 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
510 GFP_KERNEL);
511 if (unlikely(!eth->scratch_head))
512 return -ENOMEM;
513
514 dma_addr = dma_map_single(eth->dev,
515 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
516 DMA_FROM_DEVICE);
517 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
518 return -ENOMEM;
519
520 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
521 phy_ring_tail = eth->phy_scratch_ring +
522 (sizeof(struct mtk_tx_dma) * (cnt - 1));
523
524 for (i = 0; i < cnt; i++) {
525 eth->scratch_ring[i].txd1 =
526 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
527 if (i < cnt - 1)
528 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
529 ((i + 1) * sizeof(struct mtk_tx_dma)));
530 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
531 }
532
533 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
534 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
535 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
536 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
537
538 return 0;
539 }
540
541 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
542 {
543 void *ret = ring->dma;
544
545 return ret + (desc - ring->phys);
546 }
547
548 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
549 struct mtk_tx_dma *txd)
550 {
551 int idx = txd - ring->dma;
552
553 return &ring->buf[idx];
554 }
555
556 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
557 {
558 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
559 dma_unmap_single(eth->dev,
560 dma_unmap_addr(tx_buf, dma_addr0),
561 dma_unmap_len(tx_buf, dma_len0),
562 DMA_TO_DEVICE);
563 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
564 dma_unmap_page(eth->dev,
565 dma_unmap_addr(tx_buf, dma_addr0),
566 dma_unmap_len(tx_buf, dma_len0),
567 DMA_TO_DEVICE);
568 }
569 tx_buf->flags = 0;
570 if (tx_buf->skb &&
571 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
572 dev_kfree_skb_any(tx_buf->skb);
573 tx_buf->skb = NULL;
574 }
575
576 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
577 int tx_num, struct mtk_tx_ring *ring, bool gso)
578 {
579 struct mtk_mac *mac = netdev_priv(dev);
580 struct mtk_eth *eth = mac->hw;
581 struct mtk_tx_dma *itxd, *txd;
582 struct mtk_tx_buf *tx_buf;
583 dma_addr_t mapped_addr;
584 unsigned int nr_frags;
585 int i, n_desc = 1;
586 u32 txd4 = 0, fport;
587
588 itxd = ring->next_free;
589 if (itxd == ring->last_free)
590 return -ENOMEM;
591
592 /* set the forward port */
593 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
594 txd4 |= fport;
595
596 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
597 memset(tx_buf, 0, sizeof(*tx_buf));
598
599 if (gso)
600 txd4 |= TX_DMA_TSO;
601
602 /* TX Checksum offload */
603 if (skb->ip_summed == CHECKSUM_PARTIAL)
604 txd4 |= TX_DMA_CHKSUM;
605
606 /* VLAN header offload */
607 if (skb_vlan_tag_present(skb))
608 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
609
610 mapped_addr = dma_map_single(eth->dev, skb->data,
611 skb_headlen(skb), DMA_TO_DEVICE);
612 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
613 return -ENOMEM;
614
615 WRITE_ONCE(itxd->txd1, mapped_addr);
616 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
617 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
618 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
619
620 /* TX SG offload */
621 txd = itxd;
622 nr_frags = skb_shinfo(skb)->nr_frags;
623 for (i = 0; i < nr_frags; i++) {
624 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
625 unsigned int offset = 0;
626 int frag_size = skb_frag_size(frag);
627
628 while (frag_size) {
629 bool last_frag = false;
630 unsigned int frag_map_size;
631
632 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
633 if (txd == ring->last_free)
634 goto err_dma;
635
636 n_desc++;
637 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
638 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
639 frag_map_size,
640 DMA_TO_DEVICE);
641 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
642 goto err_dma;
643
644 if (i == nr_frags - 1 &&
645 (frag_size - frag_map_size) == 0)
646 last_frag = true;
647
648 WRITE_ONCE(txd->txd1, mapped_addr);
649 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
650 TX_DMA_PLEN0(frag_map_size) |
651 last_frag * TX_DMA_LS0));
652 WRITE_ONCE(txd->txd4, fport);
653
654 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
655 tx_buf = mtk_desc_to_tx_buf(ring, txd);
656 memset(tx_buf, 0, sizeof(*tx_buf));
657
658 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
659 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
660 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
661 frag_size -= frag_map_size;
662 offset += frag_map_size;
663 }
664 }
665
666 /* store skb to cleanup */
667 tx_buf->skb = skb;
668
669 WRITE_ONCE(itxd->txd4, txd4);
670 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
671 (!nr_frags * TX_DMA_LS0)));
672
673 netdev_sent_queue(dev, skb->len);
674 skb_tx_timestamp(skb);
675
676 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
677 atomic_sub(n_desc, &ring->free_count);
678
679 /* make sure that all changes to the dma ring are flushed before we
680 * continue
681 */
682 wmb();
683
684 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
685 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
686
687 return 0;
688
689 err_dma:
690 do {
691 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
692
693 /* unmap dma */
694 mtk_tx_unmap(eth, tx_buf);
695
696 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
697 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
698 } while (itxd != txd);
699
700 return -ENOMEM;
701 }
702
703 static inline int mtk_cal_txd_req(struct sk_buff *skb)
704 {
705 int i, nfrags;
706 struct skb_frag_struct *frag;
707
708 nfrags = 1;
709 if (skb_is_gso(skb)) {
710 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
711 frag = &skb_shinfo(skb)->frags[i];
712 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
713 }
714 } else {
715 nfrags += skb_shinfo(skb)->nr_frags;
716 }
717
718 return nfrags;
719 }
720
721 static int mtk_queue_stopped(struct mtk_eth *eth)
722 {
723 int i;
724
725 for (i = 0; i < MTK_MAC_COUNT; i++) {
726 if (!eth->netdev[i])
727 continue;
728 if (netif_queue_stopped(eth->netdev[i]))
729 return 1;
730 }
731
732 return 0;
733 }
734
735 static void mtk_wake_queue(struct mtk_eth *eth)
736 {
737 int i;
738
739 for (i = 0; i < MTK_MAC_COUNT; i++) {
740 if (!eth->netdev[i])
741 continue;
742 netif_wake_queue(eth->netdev[i]);
743 }
744 }
745
746 static void mtk_stop_queue(struct mtk_eth *eth)
747 {
748 int i;
749
750 for (i = 0; i < MTK_MAC_COUNT; i++) {
751 if (!eth->netdev[i])
752 continue;
753 netif_stop_queue(eth->netdev[i]);
754 }
755 }
756
757 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
758 {
759 struct mtk_mac *mac = netdev_priv(dev);
760 struct mtk_eth *eth = mac->hw;
761 struct mtk_tx_ring *ring = &eth->tx_ring;
762 struct net_device_stats *stats = &dev->stats;
763 bool gso = false;
764 int tx_num;
765
766 /* normally we can rely on the stack not calling this more than once,
767 * however we have 2 queues running on the same ring so we need to lock
768 * the ring access
769 */
770 spin_lock(&eth->page_lock);
771
772 tx_num = mtk_cal_txd_req(skb);
773 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
774 mtk_stop_queue(eth);
775 netif_err(eth, tx_queued, dev,
776 "Tx Ring full when queue awake!\n");
777 spin_unlock(&eth->page_lock);
778 return NETDEV_TX_BUSY;
779 }
780
781 /* TSO: fill MSS info in tcp checksum field */
782 if (skb_is_gso(skb)) {
783 if (skb_cow_head(skb, 0)) {
784 netif_warn(eth, tx_err, dev,
785 "GSO expand head fail.\n");
786 goto drop;
787 }
788
789 if (skb_shinfo(skb)->gso_type &
790 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
791 gso = true;
792 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
793 }
794 }
795
796 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
797 goto drop;
798
799 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
800 mtk_stop_queue(eth);
801
802 spin_unlock(&eth->page_lock);
803
804 return NETDEV_TX_OK;
805
806 drop:
807 spin_unlock(&eth->page_lock);
808 stats->tx_dropped++;
809 dev_kfree_skb(skb);
810 return NETDEV_TX_OK;
811 }
812
813 static int mtk_poll_rx(struct napi_struct *napi, int budget,
814 struct mtk_eth *eth)
815 {
816 struct mtk_rx_ring *ring = &eth->rx_ring;
817 int idx = ring->calc_idx;
818 struct sk_buff *skb;
819 u8 *data, *new_data;
820 struct mtk_rx_dma *rxd, trxd;
821 int done = 0;
822
823 while (done < budget) {
824 struct net_device *netdev;
825 unsigned int pktlen;
826 dma_addr_t dma_addr;
827 int mac = 0;
828
829 idx = NEXT_RX_DESP_IDX(idx);
830 rxd = &ring->dma[idx];
831 data = ring->data[idx];
832
833 mtk_rx_get_desc(&trxd, rxd);
834 if (!(trxd.rxd2 & RX_DMA_DONE))
835 break;
836
837 /* find out which mac the packet come from. values start at 1 */
838 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
839 RX_DMA_FPORT_MASK;
840 mac--;
841
842 netdev = eth->netdev[mac];
843
844 /* alloc new buffer */
845 new_data = napi_alloc_frag(ring->frag_size);
846 if (unlikely(!new_data)) {
847 netdev->stats.rx_dropped++;
848 goto release_desc;
849 }
850 dma_addr = dma_map_single(eth->dev,
851 new_data + NET_SKB_PAD,
852 ring->buf_size,
853 DMA_FROM_DEVICE);
854 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
855 skb_free_frag(new_data);
856 netdev->stats.rx_dropped++;
857 goto release_desc;
858 }
859
860 /* receive data */
861 skb = build_skb(data, ring->frag_size);
862 if (unlikely(!skb)) {
863 skb_free_frag(new_data);
864 netdev->stats.rx_dropped++;
865 goto release_desc;
866 }
867 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
868
869 dma_unmap_single(eth->dev, trxd.rxd1,
870 ring->buf_size, DMA_FROM_DEVICE);
871 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
872 skb->dev = netdev;
873 skb_put(skb, pktlen);
874 if (trxd.rxd4 & RX_DMA_L4_VALID)
875 skb->ip_summed = CHECKSUM_UNNECESSARY;
876 else
877 skb_checksum_none_assert(skb);
878 skb->protocol = eth_type_trans(skb, netdev);
879
880 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
881 RX_DMA_VID(trxd.rxd3))
882 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
883 RX_DMA_VID(trxd.rxd3));
884 napi_gro_receive(napi, skb);
885
886 ring->data[idx] = new_data;
887 rxd->rxd1 = (unsigned int)dma_addr;
888
889 release_desc:
890 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
891
892 ring->calc_idx = idx;
893
894 done++;
895 }
896
897 if (done) {
898 /* make sure that all changes to the dma ring are flushed before
899 * we continue
900 */
901 wmb();
902 mtk_w32(eth, ring->calc_idx, MTK_PRX_CRX_IDX0);
903 }
904
905 return done;
906 }
907
908 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
909 {
910 struct mtk_tx_ring *ring = &eth->tx_ring;
911 struct mtk_tx_dma *desc;
912 struct sk_buff *skb;
913 struct mtk_tx_buf *tx_buf;
914 unsigned int done[MTK_MAX_DEVS];
915 unsigned int bytes[MTK_MAX_DEVS];
916 u32 cpu, dma;
917 static int condition;
918 int total = 0, i;
919
920 memset(done, 0, sizeof(done));
921 memset(bytes, 0, sizeof(bytes));
922
923 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
924 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
925
926 desc = mtk_qdma_phys_to_virt(ring, cpu);
927
928 while ((cpu != dma) && budget) {
929 u32 next_cpu = desc->txd2;
930 int mac;
931
932 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
933 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
934 break;
935
936 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
937 TX_DMA_FPORT_MASK;
938 mac--;
939
940 tx_buf = mtk_desc_to_tx_buf(ring, desc);
941 skb = tx_buf->skb;
942 if (!skb) {
943 condition = 1;
944 break;
945 }
946
947 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
948 bytes[mac] += skb->len;
949 done[mac]++;
950 budget--;
951 }
952 mtk_tx_unmap(eth, tx_buf);
953
954 ring->last_free = desc;
955 atomic_inc(&ring->free_count);
956
957 cpu = next_cpu;
958 }
959
960 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
961
962 for (i = 0; i < MTK_MAC_COUNT; i++) {
963 if (!eth->netdev[i] || !done[i])
964 continue;
965 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
966 total += done[i];
967 }
968
969 if (mtk_queue_stopped(eth) &&
970 (atomic_read(&ring->free_count) > ring->thresh))
971 mtk_wake_queue(eth);
972
973 return total;
974 }
975
976 static void mtk_handle_status_irq(struct mtk_eth *eth)
977 {
978 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
979
980 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
981 mtk_stats_update(eth);
982 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
983 MTK_INT_STATUS2);
984 }
985 }
986
987 static int mtk_napi_tx(struct napi_struct *napi, int budget)
988 {
989 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
990 u32 status, mask;
991 int tx_done = 0;
992
993 mtk_handle_status_irq(eth);
994 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
995 tx_done = mtk_poll_tx(eth, budget);
996
997 if (unlikely(netif_msg_intr(eth))) {
998 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
999 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1000 dev_info(eth->dev,
1001 "done tx %d, intr 0x%08x/0x%x\n",
1002 tx_done, status, mask);
1003 }
1004
1005 if (tx_done == budget)
1006 return budget;
1007
1008 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1009 if (status & MTK_TX_DONE_INT)
1010 return budget;
1011
1012 napi_complete(napi);
1013 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1014
1015 return tx_done;
1016 }
1017
1018 static int mtk_napi_rx(struct napi_struct *napi, int budget)
1019 {
1020 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1021 u32 status, mask;
1022 int rx_done = 0;
1023 int remain_budget = budget;
1024
1025 mtk_handle_status_irq(eth);
1026
1027 poll_again:
1028 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
1029 rx_done = mtk_poll_rx(napi, remain_budget, eth);
1030
1031 if (unlikely(netif_msg_intr(eth))) {
1032 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1033 mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
1034 dev_info(eth->dev,
1035 "done rx %d, intr 0x%08x/0x%x\n",
1036 rx_done, status, mask);
1037 }
1038 if (rx_done == remain_budget)
1039 return budget;
1040
1041 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1042 if (status & MTK_RX_DONE_INT) {
1043 remain_budget -= rx_done;
1044 goto poll_again;
1045 }
1046 napi_complete(napi);
1047 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1048
1049 return rx_done + budget - remain_budget;
1050 }
1051
1052 static int mtk_tx_alloc(struct mtk_eth *eth)
1053 {
1054 struct mtk_tx_ring *ring = &eth->tx_ring;
1055 int i, sz = sizeof(*ring->dma);
1056
1057 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1058 GFP_KERNEL);
1059 if (!ring->buf)
1060 goto no_tx_mem;
1061
1062 ring->dma = dma_alloc_coherent(eth->dev,
1063 MTK_DMA_SIZE * sz,
1064 &ring->phys,
1065 GFP_ATOMIC | __GFP_ZERO);
1066 if (!ring->dma)
1067 goto no_tx_mem;
1068
1069 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1070 for (i = 0; i < MTK_DMA_SIZE; i++) {
1071 int next = (i + 1) % MTK_DMA_SIZE;
1072 u32 next_ptr = ring->phys + next * sz;
1073
1074 ring->dma[i].txd2 = next_ptr;
1075 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1076 }
1077
1078 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1079 ring->next_free = &ring->dma[0];
1080 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
1081 ring->thresh = MAX_SKB_FRAGS;
1082
1083 /* make sure that all changes to the dma ring are flushed before we
1084 * continue
1085 */
1086 wmb();
1087
1088 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1089 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1090 mtk_w32(eth,
1091 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1092 MTK_QTX_CRX_PTR);
1093 mtk_w32(eth,
1094 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1095 MTK_QTX_DRX_PTR);
1096 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1097
1098 return 0;
1099
1100 no_tx_mem:
1101 return -ENOMEM;
1102 }
1103
1104 static void mtk_tx_clean(struct mtk_eth *eth)
1105 {
1106 struct mtk_tx_ring *ring = &eth->tx_ring;
1107 int i;
1108
1109 if (ring->buf) {
1110 for (i = 0; i < MTK_DMA_SIZE; i++)
1111 mtk_tx_unmap(eth, &ring->buf[i]);
1112 kfree(ring->buf);
1113 ring->buf = NULL;
1114 }
1115
1116 if (ring->dma) {
1117 dma_free_coherent(eth->dev,
1118 MTK_DMA_SIZE * sizeof(*ring->dma),
1119 ring->dma,
1120 ring->phys);
1121 ring->dma = NULL;
1122 }
1123 }
1124
1125 static int mtk_rx_alloc(struct mtk_eth *eth)
1126 {
1127 struct mtk_rx_ring *ring = &eth->rx_ring;
1128 int i;
1129
1130 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
1131 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1132 ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data),
1133 GFP_KERNEL);
1134 if (!ring->data)
1135 return -ENOMEM;
1136
1137 for (i = 0; i < MTK_DMA_SIZE; i++) {
1138 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1139 if (!ring->data[i])
1140 return -ENOMEM;
1141 }
1142
1143 ring->dma = dma_alloc_coherent(eth->dev,
1144 MTK_DMA_SIZE * sizeof(*ring->dma),
1145 &ring->phys,
1146 GFP_ATOMIC | __GFP_ZERO);
1147 if (!ring->dma)
1148 return -ENOMEM;
1149
1150 for (i = 0; i < MTK_DMA_SIZE; i++) {
1151 dma_addr_t dma_addr = dma_map_single(eth->dev,
1152 ring->data[i] + NET_SKB_PAD,
1153 ring->buf_size,
1154 DMA_FROM_DEVICE);
1155 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1156 return -ENOMEM;
1157 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1158
1159 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1160 }
1161 ring->calc_idx = MTK_DMA_SIZE - 1;
1162 /* make sure that all changes to the dma ring are flushed before we
1163 * continue
1164 */
1165 wmb();
1166
1167 mtk_w32(eth, eth->rx_ring.phys, MTK_PRX_BASE_PTR0);
1168 mtk_w32(eth, MTK_DMA_SIZE, MTK_PRX_MAX_CNT0);
1169 mtk_w32(eth, eth->rx_ring.calc_idx, MTK_PRX_CRX_IDX0);
1170 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_PDMA_RST_IDX);
1171
1172 return 0;
1173 }
1174
1175 static void mtk_rx_clean(struct mtk_eth *eth)
1176 {
1177 struct mtk_rx_ring *ring = &eth->rx_ring;
1178 int i;
1179
1180 if (ring->data && ring->dma) {
1181 for (i = 0; i < MTK_DMA_SIZE; i++) {
1182 if (!ring->data[i])
1183 continue;
1184 if (!ring->dma[i].rxd1)
1185 continue;
1186 dma_unmap_single(eth->dev,
1187 ring->dma[i].rxd1,
1188 ring->buf_size,
1189 DMA_FROM_DEVICE);
1190 skb_free_frag(ring->data[i]);
1191 }
1192 kfree(ring->data);
1193 ring->data = NULL;
1194 }
1195
1196 if (ring->dma) {
1197 dma_free_coherent(eth->dev,
1198 MTK_DMA_SIZE * sizeof(*ring->dma),
1199 ring->dma,
1200 ring->phys);
1201 ring->dma = NULL;
1202 }
1203 }
1204
1205 /* wait for DMA to finish whatever it is doing before we start using it again */
1206 static int mtk_dma_busy_wait(struct mtk_eth *eth)
1207 {
1208 unsigned long t_start = jiffies;
1209
1210 while (1) {
1211 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1212 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1213 return 0;
1214 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1215 break;
1216 }
1217
1218 dev_err(eth->dev, "DMA init timeout\n");
1219 return -1;
1220 }
1221
1222 static int mtk_dma_init(struct mtk_eth *eth)
1223 {
1224 int err;
1225
1226 if (mtk_dma_busy_wait(eth))
1227 return -EBUSY;
1228
1229 /* QDMA needs scratch memory for internal reordering of the
1230 * descriptors
1231 */
1232 err = mtk_init_fq_dma(eth);
1233 if (err)
1234 return err;
1235
1236 err = mtk_tx_alloc(eth);
1237 if (err)
1238 return err;
1239
1240 err = mtk_rx_alloc(eth);
1241 if (err)
1242 return err;
1243
1244 /* Enable random early drop and set drop threshold automatically */
1245 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1246 MTK_QDMA_FC_THRES);
1247 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1248
1249 return 0;
1250 }
1251
1252 static void mtk_dma_free(struct mtk_eth *eth)
1253 {
1254 int i;
1255
1256 for (i = 0; i < MTK_MAC_COUNT; i++)
1257 if (eth->netdev[i])
1258 netdev_reset_queue(eth->netdev[i]);
1259 if (eth->scratch_ring) {
1260 dma_free_coherent(eth->dev,
1261 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1262 eth->scratch_ring,
1263 eth->phy_scratch_ring);
1264 eth->scratch_ring = NULL;
1265 eth->phy_scratch_ring = 0;
1266 }
1267 mtk_tx_clean(eth);
1268 mtk_rx_clean(eth);
1269 kfree(eth->scratch_head);
1270 }
1271
1272 static void mtk_tx_timeout(struct net_device *dev)
1273 {
1274 struct mtk_mac *mac = netdev_priv(dev);
1275 struct mtk_eth *eth = mac->hw;
1276
1277 eth->netdev[mac->id]->stats.tx_errors++;
1278 netif_err(eth, tx_err, dev,
1279 "transmit timed out\n");
1280 schedule_work(&eth->pending_work);
1281 }
1282
1283 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
1284 {
1285 struct mtk_eth *eth = _eth;
1286
1287 if (likely(napi_schedule_prep(&eth->rx_napi))) {
1288 __napi_schedule(&eth->rx_napi);
1289 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1290 }
1291
1292 return IRQ_HANDLED;
1293 }
1294
1295 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1296 {
1297 struct mtk_eth *eth = _eth;
1298
1299 if (likely(napi_schedule_prep(&eth->tx_napi))) {
1300 __napi_schedule(&eth->tx_napi);
1301 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1302 }
1303
1304 return IRQ_HANDLED;
1305 }
1306
1307 #ifdef CONFIG_NET_POLL_CONTROLLER
1308 static void mtk_poll_controller(struct net_device *dev)
1309 {
1310 struct mtk_mac *mac = netdev_priv(dev);
1311 struct mtk_eth *eth = mac->hw;
1312
1313 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1314 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1315 mtk_handle_irq_rx(eth->irq[2], dev);
1316 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1317 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1318 }
1319 #endif
1320
1321 static int mtk_start_dma(struct mtk_eth *eth)
1322 {
1323 int err;
1324
1325 err = mtk_dma_init(eth);
1326 if (err) {
1327 mtk_dma_free(eth);
1328 return err;
1329 }
1330
1331 mtk_w32(eth,
1332 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
1333 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO,
1334 MTK_QDMA_GLO_CFG);
1335
1336 mtk_w32(eth,
1337 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1338 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
1339 MTK_PDMA_GLO_CFG);
1340
1341 return 0;
1342 }
1343
1344 static int mtk_open(struct net_device *dev)
1345 {
1346 struct mtk_mac *mac = netdev_priv(dev);
1347 struct mtk_eth *eth = mac->hw;
1348
1349 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1350 if (!atomic_read(&eth->dma_refcnt)) {
1351 int err = mtk_start_dma(eth);
1352
1353 if (err)
1354 return err;
1355
1356 napi_enable(&eth->tx_napi);
1357 napi_enable(&eth->rx_napi);
1358 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1359 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1360 }
1361 atomic_inc(&eth->dma_refcnt);
1362
1363 phy_start(mac->phy_dev);
1364 netif_start_queue(dev);
1365
1366 return 0;
1367 }
1368
1369 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1370 {
1371 u32 val;
1372 int i;
1373
1374 /* stop the dma engine */
1375 spin_lock_bh(&eth->page_lock);
1376 val = mtk_r32(eth, glo_cfg);
1377 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1378 glo_cfg);
1379 spin_unlock_bh(&eth->page_lock);
1380
1381 /* wait for dma stop */
1382 for (i = 0; i < 10; i++) {
1383 val = mtk_r32(eth, glo_cfg);
1384 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1385 msleep(20);
1386 continue;
1387 }
1388 break;
1389 }
1390 }
1391
1392 static int mtk_stop(struct net_device *dev)
1393 {
1394 struct mtk_mac *mac = netdev_priv(dev);
1395 struct mtk_eth *eth = mac->hw;
1396
1397 netif_tx_disable(dev);
1398 phy_stop(mac->phy_dev);
1399
1400 /* only shutdown DMA if this is the last user */
1401 if (!atomic_dec_and_test(&eth->dma_refcnt))
1402 return 0;
1403
1404 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT);
1405 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT);
1406 napi_disable(&eth->tx_napi);
1407 napi_disable(&eth->rx_napi);
1408
1409 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1410
1411 mtk_dma_free(eth);
1412
1413 return 0;
1414 }
1415
1416 static int __init mtk_hw_init(struct mtk_eth *eth)
1417 {
1418 int err, i;
1419
1420 /* reset the frame engine */
1421 reset_control_assert(eth->rstc);
1422 usleep_range(10, 20);
1423 reset_control_deassert(eth->rstc);
1424 usleep_range(10, 20);
1425
1426 /* Set GE2 driving and slew rate */
1427 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1428
1429 /* set GE2 TDSEL */
1430 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1431
1432 /* set GE2 TUNE */
1433 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1434
1435 /* GE1, Force 1000M/FD, FC ON */
1436 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1437
1438 /* GE2, Force 1000M/FD, FC ON */
1439 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1440
1441 /* Enable RX VLan Offloading */
1442 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1443
1444 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
1445 dev_name(eth->dev), eth);
1446 if (err)
1447 return err;
1448 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
1449 dev_name(eth->dev), eth);
1450 if (err)
1451 return err;
1452
1453 err = mtk_mdio_init(eth);
1454 if (err)
1455 return err;
1456
1457 /* disable delay and normal interrupt */
1458 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1459 mtk_w32(eth, 0, MTK_PDMA_DELAY_INT);
1460 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
1461 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
1462 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1463 mtk_w32(eth, 0, MTK_RST_GL);
1464
1465 /* FE int grouping */
1466 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1467 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1468 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1469 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1470 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
1471
1472 for (i = 0; i < 2; i++) {
1473 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1474
1475 /* setup the forward port to send frame to PDMA */
1476 val &= ~0xffff;
1477
1478 /* Enable RX checksum */
1479 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1480
1481 /* setup the mac dma */
1482 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1483 }
1484
1485 return 0;
1486 }
1487
1488 static int __init mtk_init(struct net_device *dev)
1489 {
1490 struct mtk_mac *mac = netdev_priv(dev);
1491 struct mtk_eth *eth = mac->hw;
1492 const char *mac_addr;
1493
1494 mac_addr = of_get_mac_address(mac->of_node);
1495 if (mac_addr)
1496 ether_addr_copy(dev->dev_addr, mac_addr);
1497
1498 /* If the mac address is invalid, use random mac address */
1499 if (!is_valid_ether_addr(dev->dev_addr)) {
1500 random_ether_addr(dev->dev_addr);
1501 dev_err(eth->dev, "generated random MAC address %pM\n",
1502 dev->dev_addr);
1503 dev->addr_assign_type = NET_ADDR_RANDOM;
1504 }
1505
1506 return mtk_phy_connect(mac);
1507 }
1508
1509 static void mtk_uninit(struct net_device *dev)
1510 {
1511 struct mtk_mac *mac = netdev_priv(dev);
1512 struct mtk_eth *eth = mac->hw;
1513
1514 phy_disconnect(mac->phy_dev);
1515 mtk_mdio_cleanup(eth);
1516 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0);
1517 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0);
1518 free_irq(eth->irq[1], dev);
1519 free_irq(eth->irq[2], dev);
1520 }
1521
1522 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1523 {
1524 struct mtk_mac *mac = netdev_priv(dev);
1525
1526 switch (cmd) {
1527 case SIOCGMIIPHY:
1528 case SIOCGMIIREG:
1529 case SIOCSMIIREG:
1530 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1531 default:
1532 break;
1533 }
1534
1535 return -EOPNOTSUPP;
1536 }
1537
1538 static void mtk_pending_work(struct work_struct *work)
1539 {
1540 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
1541 int err, i;
1542 unsigned long restart = 0;
1543
1544 rtnl_lock();
1545
1546 /* stop all devices to make sure that dma is properly shut down */
1547 for (i = 0; i < MTK_MAC_COUNT; i++) {
1548 if (!eth->netdev[i])
1549 continue;
1550 mtk_stop(eth->netdev[i]);
1551 __set_bit(i, &restart);
1552 }
1553
1554 /* restart DMA and enable IRQs */
1555 for (i = 0; i < MTK_MAC_COUNT; i++) {
1556 if (!test_bit(i, &restart))
1557 continue;
1558 err = mtk_open(eth->netdev[i]);
1559 if (err) {
1560 netif_alert(eth, ifup, eth->netdev[i],
1561 "Driver up/down cycle failed, closing device.\n");
1562 dev_close(eth->netdev[i]);
1563 }
1564 }
1565 rtnl_unlock();
1566 }
1567
1568 static int mtk_cleanup(struct mtk_eth *eth)
1569 {
1570 int i;
1571
1572 for (i = 0; i < MTK_MAC_COUNT; i++) {
1573 if (!eth->netdev[i])
1574 continue;
1575
1576 unregister_netdev(eth->netdev[i]);
1577 free_netdev(eth->netdev[i]);
1578 }
1579 cancel_work_sync(&eth->pending_work);
1580
1581 return 0;
1582 }
1583
1584 static int mtk_get_settings(struct net_device *dev,
1585 struct ethtool_cmd *cmd)
1586 {
1587 struct mtk_mac *mac = netdev_priv(dev);
1588 int err;
1589
1590 err = phy_read_status(mac->phy_dev);
1591 if (err)
1592 return -ENODEV;
1593
1594 return phy_ethtool_gset(mac->phy_dev, cmd);
1595 }
1596
1597 static int mtk_set_settings(struct net_device *dev,
1598 struct ethtool_cmd *cmd)
1599 {
1600 struct mtk_mac *mac = netdev_priv(dev);
1601
1602 if (cmd->phy_address != mac->phy_dev->mdio.addr) {
1603 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
1604 cmd->phy_address);
1605 if (!mac->phy_dev)
1606 return -ENODEV;
1607 }
1608
1609 return phy_ethtool_sset(mac->phy_dev, cmd);
1610 }
1611
1612 static void mtk_get_drvinfo(struct net_device *dev,
1613 struct ethtool_drvinfo *info)
1614 {
1615 struct mtk_mac *mac = netdev_priv(dev);
1616
1617 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
1618 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
1619 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
1620 }
1621
1622 static u32 mtk_get_msglevel(struct net_device *dev)
1623 {
1624 struct mtk_mac *mac = netdev_priv(dev);
1625
1626 return mac->hw->msg_enable;
1627 }
1628
1629 static void mtk_set_msglevel(struct net_device *dev, u32 value)
1630 {
1631 struct mtk_mac *mac = netdev_priv(dev);
1632
1633 mac->hw->msg_enable = value;
1634 }
1635
1636 static int mtk_nway_reset(struct net_device *dev)
1637 {
1638 struct mtk_mac *mac = netdev_priv(dev);
1639
1640 return genphy_restart_aneg(mac->phy_dev);
1641 }
1642
1643 static u32 mtk_get_link(struct net_device *dev)
1644 {
1645 struct mtk_mac *mac = netdev_priv(dev);
1646 int err;
1647
1648 err = genphy_update_link(mac->phy_dev);
1649 if (err)
1650 return ethtool_op_get_link(dev);
1651
1652 return mac->phy_dev->link;
1653 }
1654
1655 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1656 {
1657 int i;
1658
1659 switch (stringset) {
1660 case ETH_SS_STATS:
1661 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
1662 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
1663 data += ETH_GSTRING_LEN;
1664 }
1665 break;
1666 }
1667 }
1668
1669 static int mtk_get_sset_count(struct net_device *dev, int sset)
1670 {
1671 switch (sset) {
1672 case ETH_SS_STATS:
1673 return ARRAY_SIZE(mtk_ethtool_stats);
1674 default:
1675 return -EOPNOTSUPP;
1676 }
1677 }
1678
1679 static void mtk_get_ethtool_stats(struct net_device *dev,
1680 struct ethtool_stats *stats, u64 *data)
1681 {
1682 struct mtk_mac *mac = netdev_priv(dev);
1683 struct mtk_hw_stats *hwstats = mac->hw_stats;
1684 u64 *data_src, *data_dst;
1685 unsigned int start;
1686 int i;
1687
1688 if (netif_running(dev) && netif_device_present(dev)) {
1689 if (spin_trylock(&hwstats->stats_lock)) {
1690 mtk_stats_update_mac(mac);
1691 spin_unlock(&hwstats->stats_lock);
1692 }
1693 }
1694
1695 do {
1696 data_src = (u64 *)hwstats;
1697 data_dst = data;
1698 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
1699
1700 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
1701 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
1702 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
1703 }
1704
1705 static const struct ethtool_ops mtk_ethtool_ops = {
1706 .get_settings = mtk_get_settings,
1707 .set_settings = mtk_set_settings,
1708 .get_drvinfo = mtk_get_drvinfo,
1709 .get_msglevel = mtk_get_msglevel,
1710 .set_msglevel = mtk_set_msglevel,
1711 .nway_reset = mtk_nway_reset,
1712 .get_link = mtk_get_link,
1713 .get_strings = mtk_get_strings,
1714 .get_sset_count = mtk_get_sset_count,
1715 .get_ethtool_stats = mtk_get_ethtool_stats,
1716 };
1717
1718 static const struct net_device_ops mtk_netdev_ops = {
1719 .ndo_init = mtk_init,
1720 .ndo_uninit = mtk_uninit,
1721 .ndo_open = mtk_open,
1722 .ndo_stop = mtk_stop,
1723 .ndo_start_xmit = mtk_start_xmit,
1724 .ndo_set_mac_address = mtk_set_mac_address,
1725 .ndo_validate_addr = eth_validate_addr,
1726 .ndo_do_ioctl = mtk_do_ioctl,
1727 .ndo_change_mtu = eth_change_mtu,
1728 .ndo_tx_timeout = mtk_tx_timeout,
1729 .ndo_get_stats64 = mtk_get_stats64,
1730 #ifdef CONFIG_NET_POLL_CONTROLLER
1731 .ndo_poll_controller = mtk_poll_controller,
1732 #endif
1733 };
1734
1735 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
1736 {
1737 struct mtk_mac *mac;
1738 const __be32 *_id = of_get_property(np, "reg", NULL);
1739 int id, err;
1740
1741 if (!_id) {
1742 dev_err(eth->dev, "missing mac id\n");
1743 return -EINVAL;
1744 }
1745
1746 id = be32_to_cpup(_id);
1747 if (id >= MTK_MAC_COUNT) {
1748 dev_err(eth->dev, "%d is not a valid mac id\n", id);
1749 return -EINVAL;
1750 }
1751
1752 if (eth->netdev[id]) {
1753 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
1754 return -EINVAL;
1755 }
1756
1757 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
1758 if (!eth->netdev[id]) {
1759 dev_err(eth->dev, "alloc_etherdev failed\n");
1760 return -ENOMEM;
1761 }
1762 mac = netdev_priv(eth->netdev[id]);
1763 eth->mac[id] = mac;
1764 mac->id = id;
1765 mac->hw = eth;
1766 mac->of_node = np;
1767
1768 mac->hw_stats = devm_kzalloc(eth->dev,
1769 sizeof(*mac->hw_stats),
1770 GFP_KERNEL);
1771 if (!mac->hw_stats) {
1772 dev_err(eth->dev, "failed to allocate counter memory\n");
1773 err = -ENOMEM;
1774 goto free_netdev;
1775 }
1776 spin_lock_init(&mac->hw_stats->stats_lock);
1777 u64_stats_init(&mac->hw_stats->syncp);
1778 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
1779
1780 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
1781 eth->netdev[id]->watchdog_timeo = 5 * HZ;
1782 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
1783 eth->netdev[id]->base_addr = (unsigned long)eth->base;
1784 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
1785 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1786 eth->netdev[id]->features |= MTK_HW_FEATURES;
1787 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
1788
1789 err = register_netdev(eth->netdev[id]);
1790 if (err) {
1791 dev_err(eth->dev, "error bringing up device\n");
1792 goto free_netdev;
1793 }
1794 eth->netdev[id]->irq = eth->irq[0];
1795 netif_info(eth, probe, eth->netdev[id],
1796 "mediatek frame engine at 0x%08lx, irq %d\n",
1797 eth->netdev[id]->base_addr, eth->irq[0]);
1798
1799 return 0;
1800
1801 free_netdev:
1802 free_netdev(eth->netdev[id]);
1803 return err;
1804 }
1805
1806 static int mtk_probe(struct platform_device *pdev)
1807 {
1808 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1809 struct device_node *mac_np;
1810 const struct of_device_id *match;
1811 struct mtk_soc_data *soc;
1812 struct mtk_eth *eth;
1813 int err;
1814 int i;
1815
1816 match = of_match_device(of_mtk_match, &pdev->dev);
1817 soc = (struct mtk_soc_data *)match->data;
1818
1819 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
1820 if (!eth)
1821 return -ENOMEM;
1822
1823 eth->dev = &pdev->dev;
1824 eth->base = devm_ioremap_resource(&pdev->dev, res);
1825 if (IS_ERR(eth->base))
1826 return PTR_ERR(eth->base);
1827
1828 spin_lock_init(&eth->page_lock);
1829 spin_lock_init(&eth->irq_lock);
1830
1831 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1832 "mediatek,ethsys");
1833 if (IS_ERR(eth->ethsys)) {
1834 dev_err(&pdev->dev, "no ethsys regmap found\n");
1835 return PTR_ERR(eth->ethsys);
1836 }
1837
1838 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1839 "mediatek,pctl");
1840 if (IS_ERR(eth->pctl)) {
1841 dev_err(&pdev->dev, "no pctl regmap found\n");
1842 return PTR_ERR(eth->pctl);
1843 }
1844
1845 eth->rstc = devm_reset_control_get(&pdev->dev, "eth");
1846 if (IS_ERR(eth->rstc)) {
1847 dev_err(&pdev->dev, "no eth reset found\n");
1848 return PTR_ERR(eth->rstc);
1849 }
1850
1851 for (i = 0; i < 3; i++) {
1852 eth->irq[i] = platform_get_irq(pdev, i);
1853 if (eth->irq[i] < 0) {
1854 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
1855 return -ENXIO;
1856 }
1857 }
1858 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
1859 eth->clks[i] = devm_clk_get(eth->dev,
1860 mtk_clks_source_name[i]);
1861 if (IS_ERR(eth->clks[i])) {
1862 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
1863 return -EPROBE_DEFER;
1864 return -ENODEV;
1865 }
1866 }
1867
1868 clk_prepare_enable(eth->clks[MTK_CLK_ETHIF]);
1869 clk_prepare_enable(eth->clks[MTK_CLK_ESW]);
1870 clk_prepare_enable(eth->clks[MTK_CLK_GP1]);
1871 clk_prepare_enable(eth->clks[MTK_CLK_GP2]);
1872
1873 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
1874 INIT_WORK(&eth->pending_work, mtk_pending_work);
1875
1876 err = mtk_hw_init(eth);
1877 if (err)
1878 return err;
1879
1880 for_each_child_of_node(pdev->dev.of_node, mac_np) {
1881 if (!of_device_is_compatible(mac_np,
1882 "mediatek,eth-mac"))
1883 continue;
1884
1885 if (!of_device_is_available(mac_np))
1886 continue;
1887
1888 err = mtk_add_mac(eth, mac_np);
1889 if (err)
1890 goto err_free_dev;
1891 }
1892
1893 /* we run 2 devices on the same DMA ring so we need a dummy device
1894 * for NAPI to work
1895 */
1896 init_dummy_netdev(&eth->dummy_dev);
1897 netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
1898 MTK_NAPI_WEIGHT);
1899 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
1900 MTK_NAPI_WEIGHT);
1901
1902 platform_set_drvdata(pdev, eth);
1903
1904 return 0;
1905
1906 err_free_dev:
1907 mtk_cleanup(eth);
1908 return err;
1909 }
1910
1911 static int mtk_remove(struct platform_device *pdev)
1912 {
1913 struct mtk_eth *eth = platform_get_drvdata(pdev);
1914 int i;
1915
1916 /* stop all devices to make sure that dma is properly shut down */
1917 for (i = 0; i < MTK_MAC_COUNT; i++) {
1918 if (!eth->netdev[i])
1919 continue;
1920 mtk_stop(eth->netdev[i]);
1921 }
1922
1923 clk_disable_unprepare(eth->clks[MTK_CLK_ETHIF]);
1924 clk_disable_unprepare(eth->clks[MTK_CLK_ESW]);
1925 clk_disable_unprepare(eth->clks[MTK_CLK_GP1]);
1926 clk_disable_unprepare(eth->clks[MTK_CLK_GP2]);
1927
1928 netif_napi_del(&eth->tx_napi);
1929 netif_napi_del(&eth->rx_napi);
1930 mtk_cleanup(eth);
1931
1932 return 0;
1933 }
1934
1935 const struct of_device_id of_mtk_match[] = {
1936 { .compatible = "mediatek,mt7623-eth" },
1937 {},
1938 };
1939
1940 static struct platform_driver mtk_driver = {
1941 .probe = mtk_probe,
1942 .remove = mtk_remove,
1943 .driver = {
1944 .name = "mtk_soc_eth",
1945 .of_match_table = of_mtk_match,
1946 },
1947 };
1948
1949 module_platform_driver(mtk_driver);
1950
1951 MODULE_LICENSE("GPL");
1952 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1953 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
Linux kernel - Deliverables
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