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Merge remote-tracking branch 'ftrace/for-next'
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / en_rx.c
1 /*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #include <net/busy_poll.h>
35 #include <linux/bpf.h>
36 #include <linux/mlx4/cq.h>
37 #include <linux/slab.h>
38 #include <linux/mlx4/qp.h>
39 #include <linux/skbuff.h>
40 #include <linux/rculist.h>
41 #include <linux/if_ether.h>
42 #include <linux/if_vlan.h>
43 #include <linux/vmalloc.h>
44 #include <linux/irq.h>
45
46 #if IS_ENABLED(CONFIG_IPV6)
47 #include <net/ip6_checksum.h>
48 #endif
49
50 #include "mlx4_en.h"
51
52 static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
53 struct mlx4_en_rx_alloc *page_alloc,
54 const struct mlx4_en_frag_info *frag_info,
55 gfp_t _gfp)
56 {
57 int order;
58 struct page *page;
59 dma_addr_t dma;
60
61 for (order = frag_info->order; ;) {
62 gfp_t gfp = _gfp;
63
64 if (order)
65 gfp |= __GFP_COMP | __GFP_NOWARN | __GFP_NOMEMALLOC;
66 page = alloc_pages(gfp, order);
67 if (likely(page))
68 break;
69 if (--order < 0 ||
70 ((PAGE_SIZE << order) < frag_info->frag_size))
71 return -ENOMEM;
72 }
73 dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
74 frag_info->dma_dir);
75 if (dma_mapping_error(priv->ddev, dma)) {
76 put_page(page);
77 return -ENOMEM;
78 }
79 page_alloc->page_size = PAGE_SIZE << order;
80 page_alloc->page = page;
81 page_alloc->dma = dma;
82 page_alloc->page_offset = 0;
83 /* Not doing get_page() for each frag is a big win
84 * on asymetric workloads. Note we can not use atomic_set().
85 */
86 page_ref_add(page, page_alloc->page_size / frag_info->frag_stride - 1);
87 return 0;
88 }
89
90 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
91 struct mlx4_en_rx_desc *rx_desc,
92 struct mlx4_en_rx_alloc *frags,
93 struct mlx4_en_rx_alloc *ring_alloc,
94 gfp_t gfp)
95 {
96 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
97 const struct mlx4_en_frag_info *frag_info;
98 struct page *page;
99 dma_addr_t dma;
100 int i;
101
102 for (i = 0; i < priv->num_frags; i++) {
103 frag_info = &priv->frag_info[i];
104 page_alloc[i] = ring_alloc[i];
105 page_alloc[i].page_offset += frag_info->frag_stride;
106
107 if (page_alloc[i].page_offset + frag_info->frag_stride <=
108 ring_alloc[i].page_size)
109 continue;
110
111 if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp))
112 goto out;
113 }
114
115 for (i = 0; i < priv->num_frags; i++) {
116 frags[i] = ring_alloc[i];
117 dma = ring_alloc[i].dma + ring_alloc[i].page_offset;
118 ring_alloc[i] = page_alloc[i];
119 rx_desc->data[i].addr = cpu_to_be64(dma);
120 }
121
122 return 0;
123
124 out:
125 while (i--) {
126 if (page_alloc[i].page != ring_alloc[i].page) {
127 dma_unmap_page(priv->ddev, page_alloc[i].dma,
128 page_alloc[i].page_size,
129 priv->frag_info[i].dma_dir);
130 page = page_alloc[i].page;
131 /* Revert changes done by mlx4_alloc_pages */
132 page_ref_sub(page, page_alloc[i].page_size /
133 priv->frag_info[i].frag_stride - 1);
134 put_page(page);
135 }
136 }
137 return -ENOMEM;
138 }
139
140 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
141 struct mlx4_en_rx_alloc *frags,
142 int i)
143 {
144 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
145 u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride;
146
147
148 if (next_frag_end > frags[i].page_size)
149 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size,
150 frag_info->dma_dir);
151
152 if (frags[i].page)
153 put_page(frags[i].page);
154 }
155
156 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
157 struct mlx4_en_rx_ring *ring)
158 {
159 int i;
160 struct mlx4_en_rx_alloc *page_alloc;
161
162 for (i = 0; i < priv->num_frags; i++) {
163 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
164
165 if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
166 frag_info, GFP_KERNEL | __GFP_COLD))
167 goto out;
168
169 en_dbg(DRV, priv, " frag %d allocator: - size:%d frags:%d\n",
170 i, ring->page_alloc[i].page_size,
171 page_ref_count(ring->page_alloc[i].page));
172 }
173 return 0;
174
175 out:
176 while (i--) {
177 struct page *page;
178
179 page_alloc = &ring->page_alloc[i];
180 dma_unmap_page(priv->ddev, page_alloc->dma,
181 page_alloc->page_size,
182 priv->frag_info[i].dma_dir);
183 page = page_alloc->page;
184 /* Revert changes done by mlx4_alloc_pages */
185 page_ref_sub(page, page_alloc->page_size /
186 priv->frag_info[i].frag_stride - 1);
187 put_page(page);
188 page_alloc->page = NULL;
189 }
190 return -ENOMEM;
191 }
192
193 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
194 struct mlx4_en_rx_ring *ring)
195 {
196 struct mlx4_en_rx_alloc *page_alloc;
197 int i;
198
199 for (i = 0; i < priv->num_frags; i++) {
200 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
201
202 page_alloc = &ring->page_alloc[i];
203 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
204 i, page_count(page_alloc->page));
205
206 dma_unmap_page(priv->ddev, page_alloc->dma,
207 page_alloc->page_size, frag_info->dma_dir);
208 while (page_alloc->page_offset + frag_info->frag_stride <
209 page_alloc->page_size) {
210 put_page(page_alloc->page);
211 page_alloc->page_offset += frag_info->frag_stride;
212 }
213 page_alloc->page = NULL;
214 }
215 }
216
217 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
218 struct mlx4_en_rx_ring *ring, int index)
219 {
220 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
221 int possible_frags;
222 int i;
223
224 /* Set size and memtype fields */
225 for (i = 0; i < priv->num_frags; i++) {
226 rx_desc->data[i].byte_count =
227 cpu_to_be32(priv->frag_info[i].frag_size);
228 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
229 }
230
231 /* If the number of used fragments does not fill up the ring stride,
232 * remaining (unused) fragments must be padded with null address/size
233 * and a special memory key */
234 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
235 for (i = priv->num_frags; i < possible_frags; i++) {
236 rx_desc->data[i].byte_count = 0;
237 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
238 rx_desc->data[i].addr = 0;
239 }
240 }
241
242 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
243 struct mlx4_en_rx_ring *ring, int index,
244 gfp_t gfp)
245 {
246 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
247 struct mlx4_en_rx_alloc *frags = ring->rx_info +
248 (index << priv->log_rx_info);
249
250 if (ring->page_cache.index > 0) {
251 frags[0] = ring->page_cache.buf[--ring->page_cache.index];
252 rx_desc->data[0].addr = cpu_to_be64(frags[0].dma);
253 return 0;
254 }
255
256 return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
257 }
258
259 static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring)
260 {
261 return ring->prod == ring->cons;
262 }
263
264 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
265 {
266 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
267 }
268
269 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
270 struct mlx4_en_rx_ring *ring,
271 int index)
272 {
273 struct mlx4_en_rx_alloc *frags;
274 int nr;
275
276 frags = ring->rx_info + (index << priv->log_rx_info);
277 for (nr = 0; nr < priv->num_frags; nr++) {
278 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
279 mlx4_en_free_frag(priv, frags, nr);
280 }
281 }
282
283 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
284 {
285 struct mlx4_en_rx_ring *ring;
286 int ring_ind;
287 int buf_ind;
288 int new_size;
289
290 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
291 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
292 ring = priv->rx_ring[ring_ind];
293
294 if (mlx4_en_prepare_rx_desc(priv, ring,
295 ring->actual_size,
296 GFP_KERNEL | __GFP_COLD)) {
297 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
298 en_err(priv, "Failed to allocate enough rx buffers\n");
299 return -ENOMEM;
300 } else {
301 new_size = rounddown_pow_of_two(ring->actual_size);
302 en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
303 ring->actual_size, new_size);
304 goto reduce_rings;
305 }
306 }
307 ring->actual_size++;
308 ring->prod++;
309 }
310 }
311 return 0;
312
313 reduce_rings:
314 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
315 ring = priv->rx_ring[ring_ind];
316 while (ring->actual_size > new_size) {
317 ring->actual_size--;
318 ring->prod--;
319 mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
320 }
321 }
322
323 return 0;
324 }
325
326 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
327 struct mlx4_en_rx_ring *ring)
328 {
329 int index;
330
331 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
332 ring->cons, ring->prod);
333
334 /* Unmap and free Rx buffers */
335 while (!mlx4_en_is_ring_empty(ring)) {
336 index = ring->cons & ring->size_mask;
337 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
338 mlx4_en_free_rx_desc(priv, ring, index);
339 ++ring->cons;
340 }
341 }
342
343 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
344 {
345 int i;
346 int num_of_eqs;
347 int num_rx_rings;
348 struct mlx4_dev *dev = mdev->dev;
349
350 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
351 num_of_eqs = max_t(int, MIN_RX_RINGS,
352 min_t(int,
353 mlx4_get_eqs_per_port(mdev->dev, i),
354 DEF_RX_RINGS));
355
356 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
357 min_t(int, num_of_eqs,
358 netif_get_num_default_rss_queues());
359 mdev->profile.prof[i].rx_ring_num =
360 rounddown_pow_of_two(num_rx_rings);
361 }
362 }
363
364 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
365 struct mlx4_en_rx_ring **pring,
366 u32 size, u16 stride, int node)
367 {
368 struct mlx4_en_dev *mdev = priv->mdev;
369 struct mlx4_en_rx_ring *ring;
370 int err = -ENOMEM;
371 int tmp;
372
373 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
374 if (!ring) {
375 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
376 if (!ring) {
377 en_err(priv, "Failed to allocate RX ring structure\n");
378 return -ENOMEM;
379 }
380 }
381
382 ring->prod = 0;
383 ring->cons = 0;
384 ring->size = size;
385 ring->size_mask = size - 1;
386 ring->stride = stride;
387 ring->log_stride = ffs(ring->stride) - 1;
388 ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
389
390 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
391 sizeof(struct mlx4_en_rx_alloc));
392 ring->rx_info = vmalloc_node(tmp, node);
393 if (!ring->rx_info) {
394 ring->rx_info = vmalloc(tmp);
395 if (!ring->rx_info) {
396 err = -ENOMEM;
397 goto err_ring;
398 }
399 }
400
401 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
402 ring->rx_info, tmp);
403
404 /* Allocate HW buffers on provided NUMA node */
405 set_dev_node(&mdev->dev->persist->pdev->dev, node);
406 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
407 set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
408 if (err)
409 goto err_info;
410
411 ring->buf = ring->wqres.buf.direct.buf;
412
413 ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
414
415 *pring = ring;
416 return 0;
417
418 err_info:
419 vfree(ring->rx_info);
420 ring->rx_info = NULL;
421 err_ring:
422 kfree(ring);
423 *pring = NULL;
424
425 return err;
426 }
427
428 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
429 {
430 struct mlx4_en_rx_ring *ring;
431 int i;
432 int ring_ind;
433 int err;
434 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
435 DS_SIZE * priv->num_frags);
436
437 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
438 ring = priv->rx_ring[ring_ind];
439
440 ring->prod = 0;
441 ring->cons = 0;
442 ring->actual_size = 0;
443 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
444
445 ring->stride = stride;
446 if (ring->stride <= TXBB_SIZE)
447 ring->buf += TXBB_SIZE;
448
449 ring->log_stride = ffs(ring->stride) - 1;
450 ring->buf_size = ring->size * ring->stride;
451
452 memset(ring->buf, 0, ring->buf_size);
453 mlx4_en_update_rx_prod_db(ring);
454
455 /* Initialize all descriptors */
456 for (i = 0; i < ring->size; i++)
457 mlx4_en_init_rx_desc(priv, ring, i);
458
459 /* Initialize page allocators */
460 err = mlx4_en_init_allocator(priv, ring);
461 if (err) {
462 en_err(priv, "Failed initializing ring allocator\n");
463 if (ring->stride <= TXBB_SIZE)
464 ring->buf -= TXBB_SIZE;
465 ring_ind--;
466 goto err_allocator;
467 }
468 }
469 err = mlx4_en_fill_rx_buffers(priv);
470 if (err)
471 goto err_buffers;
472
473 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
474 ring = priv->rx_ring[ring_ind];
475
476 ring->size_mask = ring->actual_size - 1;
477 mlx4_en_update_rx_prod_db(ring);
478 }
479
480 return 0;
481
482 err_buffers:
483 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
484 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
485
486 ring_ind = priv->rx_ring_num - 1;
487 err_allocator:
488 while (ring_ind >= 0) {
489 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
490 priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
491 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]);
492 ring_ind--;
493 }
494 return err;
495 }
496
497 /* We recover from out of memory by scheduling our napi poll
498 * function (mlx4_en_process_cq), which tries to allocate
499 * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
500 */
501 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
502 {
503 int ring;
504
505 if (!priv->port_up)
506 return;
507
508 for (ring = 0; ring < priv->rx_ring_num; ring++) {
509 if (mlx4_en_is_ring_empty(priv->rx_ring[ring]))
510 napi_reschedule(&priv->rx_cq[ring]->napi);
511 }
512 }
513
514 /* When the rx ring is running in page-per-packet mode, a released frame can go
515 * directly into a small cache, to avoid unmapping or touching the page
516 * allocator. In bpf prog performance scenarios, buffers are either forwarded
517 * or dropped, never converted to skbs, so every page can come directly from
518 * this cache when it is sized to be a multiple of the napi budget.
519 */
520 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
521 struct mlx4_en_rx_alloc *frame)
522 {
523 struct mlx4_en_page_cache *cache = &ring->page_cache;
524
525 if (cache->index >= MLX4_EN_CACHE_SIZE)
526 return false;
527
528 cache->buf[cache->index++] = *frame;
529 return true;
530 }
531
532 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
533 struct mlx4_en_rx_ring **pring,
534 u32 size, u16 stride)
535 {
536 struct mlx4_en_dev *mdev = priv->mdev;
537 struct mlx4_en_rx_ring *ring = *pring;
538 struct bpf_prog *old_prog;
539
540 old_prog = rcu_dereference_protected(
541 ring->xdp_prog,
542 lockdep_is_held(&mdev->state_lock));
543 if (old_prog)
544 bpf_prog_put(old_prog);
545 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
546 vfree(ring->rx_info);
547 ring->rx_info = NULL;
548 kfree(ring);
549 *pring = NULL;
550 }
551
552 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
553 struct mlx4_en_rx_ring *ring)
554 {
555 int i;
556
557 for (i = 0; i < ring->page_cache.index; i++) {
558 struct mlx4_en_rx_alloc *frame = &ring->page_cache.buf[i];
559
560 dma_unmap_page(priv->ddev, frame->dma, frame->page_size,
561 priv->frag_info[0].dma_dir);
562 put_page(frame->page);
563 }
564 ring->page_cache.index = 0;
565 mlx4_en_free_rx_buf(priv, ring);
566 if (ring->stride <= TXBB_SIZE)
567 ring->buf -= TXBB_SIZE;
568 mlx4_en_destroy_allocator(priv, ring);
569 }
570
571
572 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
573 struct mlx4_en_rx_desc *rx_desc,
574 struct mlx4_en_rx_alloc *frags,
575 struct sk_buff *skb,
576 int length)
577 {
578 struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
579 struct mlx4_en_frag_info *frag_info;
580 int nr;
581 dma_addr_t dma;
582
583 /* Collect used fragments while replacing them in the HW descriptors */
584 for (nr = 0; nr < priv->num_frags; nr++) {
585 frag_info = &priv->frag_info[nr];
586 if (length <= frag_info->frag_prefix_size)
587 break;
588 if (!frags[nr].page)
589 goto fail;
590
591 dma = be64_to_cpu(rx_desc->data[nr].addr);
592 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
593 DMA_FROM_DEVICE);
594
595 /* Save page reference in skb */
596 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
597 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
598 skb_frags_rx[nr].page_offset = frags[nr].page_offset;
599 skb->truesize += frag_info->frag_stride;
600 frags[nr].page = NULL;
601 }
602 /* Adjust size of last fragment to match actual length */
603 if (nr > 0)
604 skb_frag_size_set(&skb_frags_rx[nr - 1],
605 length - priv->frag_info[nr - 1].frag_prefix_size);
606 return nr;
607
608 fail:
609 while (nr > 0) {
610 nr--;
611 __skb_frag_unref(&skb_frags_rx[nr]);
612 }
613 return 0;
614 }
615
616
617 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
618 struct mlx4_en_rx_desc *rx_desc,
619 struct mlx4_en_rx_alloc *frags,
620 unsigned int length)
621 {
622 struct sk_buff *skb;
623 void *va;
624 int used_frags;
625 dma_addr_t dma;
626
627 skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
628 if (!skb) {
629 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
630 return NULL;
631 }
632 skb_reserve(skb, NET_IP_ALIGN);
633 skb->len = length;
634
635 /* Get pointer to first fragment so we could copy the headers into the
636 * (linear part of the) skb */
637 va = page_address(frags[0].page) + frags[0].page_offset;
638
639 if (length <= SMALL_PACKET_SIZE) {
640 /* We are copying all relevant data to the skb - temporarily
641 * sync buffers for the copy */
642 dma = be64_to_cpu(rx_desc->data[0].addr);
643 dma_sync_single_for_cpu(priv->ddev, dma, length,
644 DMA_FROM_DEVICE);
645 skb_copy_to_linear_data(skb, va, length);
646 skb->tail += length;
647 } else {
648 unsigned int pull_len;
649
650 /* Move relevant fragments to skb */
651 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
652 skb, length);
653 if (unlikely(!used_frags)) {
654 kfree_skb(skb);
655 return NULL;
656 }
657 skb_shinfo(skb)->nr_frags = used_frags;
658
659 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE);
660 /* Copy headers into the skb linear buffer */
661 memcpy(skb->data, va, pull_len);
662 skb->tail += pull_len;
663
664 /* Skip headers in first fragment */
665 skb_shinfo(skb)->frags[0].page_offset += pull_len;
666
667 /* Adjust size of first fragment */
668 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len);
669 skb->data_len = length - pull_len;
670 }
671 return skb;
672 }
673
674 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
675 {
676 int i;
677 int offset = ETH_HLEN;
678
679 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
680 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
681 goto out_loopback;
682 }
683 /* Loopback found */
684 priv->loopback_ok = 1;
685
686 out_loopback:
687 dev_kfree_skb_any(skb);
688 }
689
690 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
691 struct mlx4_en_rx_ring *ring)
692 {
693 int index = ring->prod & ring->size_mask;
694
695 while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
696 if (mlx4_en_prepare_rx_desc(priv, ring, index,
697 GFP_ATOMIC | __GFP_COLD))
698 break;
699 ring->prod++;
700 index = ring->prod & ring->size_mask;
701 }
702 }
703
704 /* When hardware doesn't strip the vlan, we need to calculate the checksum
705 * over it and add it to the hardware's checksum calculation
706 */
707 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
708 struct vlan_hdr *vlanh)
709 {
710 return csum_add(hw_checksum, *(__wsum *)vlanh);
711 }
712
713 /* Although the stack expects checksum which doesn't include the pseudo
714 * header, the HW adds it. To address that, we are subtracting the pseudo
715 * header checksum from the checksum value provided by the HW.
716 */
717 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
718 struct iphdr *iph)
719 {
720 __u16 length_for_csum = 0;
721 __wsum csum_pseudo_header = 0;
722
723 length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
724 csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
725 length_for_csum, iph->protocol, 0);
726 skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
727 }
728
729 #if IS_ENABLED(CONFIG_IPV6)
730 /* In IPv6 packets, besides subtracting the pseudo header checksum,
731 * we also compute/add the IP header checksum which
732 * is not added by the HW.
733 */
734 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
735 struct ipv6hdr *ipv6h)
736 {
737 __wsum csum_pseudo_hdr = 0;
738
739 if (ipv6h->nexthdr == IPPROTO_FRAGMENT || ipv6h->nexthdr == IPPROTO_HOPOPTS)
740 return -1;
741 hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(ipv6h->nexthdr));
742
743 csum_pseudo_hdr = csum_partial(&ipv6h->saddr,
744 sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0);
745 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len);
746 csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr));
747
748 skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr);
749 skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0));
750 return 0;
751 }
752 #endif
753 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
754 netdev_features_t dev_features)
755 {
756 __wsum hw_checksum = 0;
757
758 void *hdr = (u8 *)va + sizeof(struct ethhdr);
759
760 hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
761
762 if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
763 !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
764 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
765 hdr += sizeof(struct vlan_hdr);
766 }
767
768 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4))
769 get_fixed_ipv4_csum(hw_checksum, skb, hdr);
770 #if IS_ENABLED(CONFIG_IPV6)
771 else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
772 if (get_fixed_ipv6_csum(hw_checksum, skb, hdr))
773 return -1;
774 #endif
775 return 0;
776 }
777
778 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
779 {
780 struct mlx4_en_priv *priv = netdev_priv(dev);
781 struct mlx4_en_dev *mdev = priv->mdev;
782 struct mlx4_cqe *cqe;
783 struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
784 struct mlx4_en_rx_alloc *frags;
785 struct mlx4_en_rx_desc *rx_desc;
786 struct bpf_prog *xdp_prog;
787 int doorbell_pending;
788 struct sk_buff *skb;
789 int tx_index;
790 int index;
791 int nr;
792 unsigned int length;
793 int polled = 0;
794 int ip_summed;
795 int factor = priv->cqe_factor;
796 u64 timestamp;
797 bool l2_tunnel;
798
799 if (!priv->port_up)
800 return 0;
801
802 if (budget <= 0)
803 return polled;
804
805 /* Protect accesses to: ring->xdp_prog, priv->mac_hash list */
806 rcu_read_lock();
807 xdp_prog = rcu_dereference(ring->xdp_prog);
808 doorbell_pending = 0;
809 tx_index = (priv->tx_ring_num - priv->xdp_ring_num) + cq->ring;
810
811 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
812 * descriptor offset can be deduced from the CQE index instead of
813 * reading 'cqe->index' */
814 index = cq->mcq.cons_index & ring->size_mask;
815 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
816
817 /* Process all completed CQEs */
818 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
819 cq->mcq.cons_index & cq->size)) {
820
821 frags = ring->rx_info + (index << priv->log_rx_info);
822 rx_desc = ring->buf + (index << ring->log_stride);
823
824 /*
825 * make sure we read the CQE after we read the ownership bit
826 */
827 dma_rmb();
828
829 /* Drop packet on bad receive or bad checksum */
830 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
831 MLX4_CQE_OPCODE_ERROR)) {
832 en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
833 ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
834 ((struct mlx4_err_cqe *)cqe)->syndrome);
835 goto next;
836 }
837 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
838 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
839 goto next;
840 }
841
842 /* Check if we need to drop the packet if SRIOV is not enabled
843 * and not performing the selftest or flb disabled
844 */
845 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
846 struct ethhdr *ethh;
847 dma_addr_t dma;
848 /* Get pointer to first fragment since we haven't
849 * skb yet and cast it to ethhdr struct
850 */
851 dma = be64_to_cpu(rx_desc->data[0].addr);
852 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
853 DMA_FROM_DEVICE);
854 ethh = (struct ethhdr *)(page_address(frags[0].page) +
855 frags[0].page_offset);
856
857 if (is_multicast_ether_addr(ethh->h_dest)) {
858 struct mlx4_mac_entry *entry;
859 struct hlist_head *bucket;
860 unsigned int mac_hash;
861
862 /* Drop the packet, since HW loopback-ed it */
863 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
864 bucket = &priv->mac_hash[mac_hash];
865 hlist_for_each_entry_rcu(entry, bucket, hlist) {
866 if (ether_addr_equal_64bits(entry->mac,
867 ethh->h_source))
868 goto next;
869 }
870 }
871 }
872
873 /*
874 * Packet is OK - process it.
875 */
876 length = be32_to_cpu(cqe->byte_cnt);
877 length -= ring->fcs_del;
878 ring->bytes += length;
879 ring->packets++;
880 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
881 (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
882
883 /* A bpf program gets first chance to drop the packet. It may
884 * read bytes but not past the end of the frag.
885 */
886 if (xdp_prog) {
887 struct xdp_buff xdp;
888 dma_addr_t dma;
889 u32 act;
890
891 dma = be64_to_cpu(rx_desc->data[0].addr);
892 dma_sync_single_for_cpu(priv->ddev, dma,
893 priv->frag_info[0].frag_size,
894 DMA_FROM_DEVICE);
895
896 xdp.data = page_address(frags[0].page) +
897 frags[0].page_offset;
898 xdp.data_end = xdp.data + length;
899
900 act = bpf_prog_run_xdp(xdp_prog, &xdp);
901 switch (act) {
902 case XDP_PASS:
903 break;
904 case XDP_TX:
905 if (!mlx4_en_xmit_frame(frags, dev,
906 length, tx_index,
907 &doorbell_pending))
908 goto consumed;
909 break;
910 default:
911 bpf_warn_invalid_xdp_action(act);
912 case XDP_ABORTED:
913 case XDP_DROP:
914 if (mlx4_en_rx_recycle(ring, frags))
915 goto consumed;
916 goto next;
917 }
918 }
919
920 if (likely(dev->features & NETIF_F_RXCSUM)) {
921 if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
922 MLX4_CQE_STATUS_UDP)) {
923 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
924 cqe->checksum == cpu_to_be16(0xffff)) {
925 ip_summed = CHECKSUM_UNNECESSARY;
926 ring->csum_ok++;
927 } else {
928 ip_summed = CHECKSUM_NONE;
929 ring->csum_none++;
930 }
931 } else {
932 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
933 (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
934 MLX4_CQE_STATUS_IPV6))) {
935 ip_summed = CHECKSUM_COMPLETE;
936 ring->csum_complete++;
937 } else {
938 ip_summed = CHECKSUM_NONE;
939 ring->csum_none++;
940 }
941 }
942 } else {
943 ip_summed = CHECKSUM_NONE;
944 ring->csum_none++;
945 }
946
947 /* This packet is eligible for GRO if it is:
948 * - DIX Ethernet (type interpretation)
949 * - TCP/IP (v4)
950 * - without IP options
951 * - not an IP fragment
952 */
953 if (dev->features & NETIF_F_GRO) {
954 struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
955 if (!gro_skb)
956 goto next;
957
958 nr = mlx4_en_complete_rx_desc(priv,
959 rx_desc, frags, gro_skb,
960 length);
961 if (!nr)
962 goto next;
963
964 if (ip_summed == CHECKSUM_COMPLETE) {
965 void *va = skb_frag_address(skb_shinfo(gro_skb)->frags);
966 if (check_csum(cqe, gro_skb, va,
967 dev->features)) {
968 ip_summed = CHECKSUM_NONE;
969 ring->csum_none++;
970 ring->csum_complete--;
971 }
972 }
973
974 skb_shinfo(gro_skb)->nr_frags = nr;
975 gro_skb->len = length;
976 gro_skb->data_len = length;
977 gro_skb->ip_summed = ip_summed;
978
979 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
980 gro_skb->csum_level = 1;
981
982 if ((cqe->vlan_my_qpn &
983 cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
984 (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
985 u16 vid = be16_to_cpu(cqe->sl_vid);
986
987 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
988 } else if ((be32_to_cpu(cqe->vlan_my_qpn) &
989 MLX4_CQE_SVLAN_PRESENT_MASK) &&
990 (dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
991 __vlan_hwaccel_put_tag(gro_skb,
992 htons(ETH_P_8021AD),
993 be16_to_cpu(cqe->sl_vid));
994 }
995
996 if (dev->features & NETIF_F_RXHASH)
997 skb_set_hash(gro_skb,
998 be32_to_cpu(cqe->immed_rss_invalid),
999 (ip_summed == CHECKSUM_UNNECESSARY) ?
1000 PKT_HASH_TYPE_L4 :
1001 PKT_HASH_TYPE_L3);
1002
1003 skb_record_rx_queue(gro_skb, cq->ring);
1004
1005 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
1006 timestamp = mlx4_en_get_cqe_ts(cqe);
1007 mlx4_en_fill_hwtstamps(mdev,
1008 skb_hwtstamps(gro_skb),
1009 timestamp);
1010 }
1011
1012 napi_gro_frags(&cq->napi);
1013 goto next;
1014 }
1015
1016 /* GRO not possible, complete processing here */
1017 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
1018 if (!skb) {
1019 ring->dropped++;
1020 goto next;
1021 }
1022
1023 if (unlikely(priv->validate_loopback)) {
1024 validate_loopback(priv, skb);
1025 goto next;
1026 }
1027
1028 if (ip_summed == CHECKSUM_COMPLETE) {
1029 if (check_csum(cqe, skb, skb->data, dev->features)) {
1030 ip_summed = CHECKSUM_NONE;
1031 ring->csum_complete--;
1032 ring->csum_none++;
1033 }
1034 }
1035
1036 skb->ip_summed = ip_summed;
1037 skb->protocol = eth_type_trans(skb, dev);
1038 skb_record_rx_queue(skb, cq->ring);
1039
1040 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
1041 skb->csum_level = 1;
1042
1043 if (dev->features & NETIF_F_RXHASH)
1044 skb_set_hash(skb,
1045 be32_to_cpu(cqe->immed_rss_invalid),
1046 (ip_summed == CHECKSUM_UNNECESSARY) ?
1047 PKT_HASH_TYPE_L4 :
1048 PKT_HASH_TYPE_L3);
1049
1050 if ((be32_to_cpu(cqe->vlan_my_qpn) &
1051 MLX4_CQE_CVLAN_PRESENT_MASK) &&
1052 (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
1053 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
1054 else if ((be32_to_cpu(cqe->vlan_my_qpn) &
1055 MLX4_CQE_SVLAN_PRESENT_MASK) &&
1056 (dev->features & NETIF_F_HW_VLAN_STAG_RX))
1057 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
1058 be16_to_cpu(cqe->sl_vid));
1059
1060 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
1061 timestamp = mlx4_en_get_cqe_ts(cqe);
1062 mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
1063 timestamp);
1064 }
1065
1066 napi_gro_receive(&cq->napi, skb);
1067 next:
1068 for (nr = 0; nr < priv->num_frags; nr++)
1069 mlx4_en_free_frag(priv, frags, nr);
1070
1071 consumed:
1072 ++cq->mcq.cons_index;
1073 index = (cq->mcq.cons_index) & ring->size_mask;
1074 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
1075 if (++polled == budget)
1076 goto out;
1077 }
1078
1079 out:
1080 rcu_read_unlock();
1081 if (doorbell_pending)
1082 mlx4_en_xmit_doorbell(priv->tx_ring[tx_index]);
1083
1084 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
1085 mlx4_cq_set_ci(&cq->mcq);
1086 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
1087 ring->cons = cq->mcq.cons_index;
1088 mlx4_en_refill_rx_buffers(priv, ring);
1089 mlx4_en_update_rx_prod_db(ring);
1090 return polled;
1091 }
1092
1093
1094 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
1095 {
1096 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
1097 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
1098
1099 if (likely(priv->port_up))
1100 napi_schedule_irqoff(&cq->napi);
1101 else
1102 mlx4_en_arm_cq(priv, cq);
1103 }
1104
1105 /* Rx CQ polling - called by NAPI */
1106 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
1107 {
1108 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
1109 struct net_device *dev = cq->dev;
1110 struct mlx4_en_priv *priv = netdev_priv(dev);
1111 int done;
1112
1113 done = mlx4_en_process_rx_cq(dev, cq, budget);
1114
1115 /* If we used up all the quota - we're probably not done yet... */
1116 if (done == budget) {
1117 const struct cpumask *aff;
1118 struct irq_data *idata;
1119 int cpu_curr;
1120
1121 INC_PERF_COUNTER(priv->pstats.napi_quota);
1122
1123 cpu_curr = smp_processor_id();
1124 idata = irq_desc_get_irq_data(cq->irq_desc);
1125 aff = irq_data_get_affinity_mask(idata);
1126
1127 if (likely(cpumask_test_cpu(cpu_curr, aff)))
1128 return budget;
1129
1130 /* Current cpu is not according to smp_irq_affinity -
1131 * probably affinity changed. need to stop this NAPI
1132 * poll, and restart it on the right CPU
1133 */
1134 done = 0;
1135 }
1136 /* Done for now */
1137 napi_complete_done(napi, done);
1138 mlx4_en_arm_cq(priv, cq);
1139 return done;
1140 }
1141
1142 static const int frag_sizes[] = {
1143 FRAG_SZ0,
1144 FRAG_SZ1,
1145 FRAG_SZ2,
1146 FRAG_SZ3
1147 };
1148
1149 void mlx4_en_calc_rx_buf(struct net_device *dev)
1150 {
1151 enum dma_data_direction dma_dir = PCI_DMA_FROMDEVICE;
1152 struct mlx4_en_priv *priv = netdev_priv(dev);
1153 int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu);
1154 int order = MLX4_EN_ALLOC_PREFER_ORDER;
1155 u32 align = SMP_CACHE_BYTES;
1156 int buf_size = 0;
1157 int i = 0;
1158
1159 /* bpf requires buffers to be set up as 1 packet per page.
1160 * This only works when num_frags == 1.
1161 */
1162 if (priv->xdp_ring_num) {
1163 dma_dir = PCI_DMA_BIDIRECTIONAL;
1164 /* This will gain efficient xdp frame recycling at the expense
1165 * of more costly truesize accounting
1166 */
1167 align = PAGE_SIZE;
1168 order = 0;
1169 }
1170
1171 while (buf_size < eff_mtu) {
1172 priv->frag_info[i].order = order;
1173 priv->frag_info[i].frag_size =
1174 (eff_mtu > buf_size + frag_sizes[i]) ?
1175 frag_sizes[i] : eff_mtu - buf_size;
1176 priv->frag_info[i].frag_prefix_size = buf_size;
1177 priv->frag_info[i].frag_stride =
1178 ALIGN(priv->frag_info[i].frag_size, align);
1179 priv->frag_info[i].dma_dir = dma_dir;
1180 buf_size += priv->frag_info[i].frag_size;
1181 i++;
1182 }
1183
1184 priv->num_frags = i;
1185 priv->rx_skb_size = eff_mtu;
1186 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1187
1188 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1189 eff_mtu, priv->num_frags);
1190 for (i = 0; i < priv->num_frags; i++) {
1191 en_err(priv,
1192 " frag:%d - size:%d prefix:%d stride:%d\n",
1193 i,
1194 priv->frag_info[i].frag_size,
1195 priv->frag_info[i].frag_prefix_size,
1196 priv->frag_info[i].frag_stride);
1197 }
1198 }
1199
1200 /* RSS related functions */
1201
1202 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1203 struct mlx4_en_rx_ring *ring,
1204 enum mlx4_qp_state *state,
1205 struct mlx4_qp *qp)
1206 {
1207 struct mlx4_en_dev *mdev = priv->mdev;
1208 struct mlx4_qp_context *context;
1209 int err = 0;
1210
1211 context = kmalloc(sizeof(*context), GFP_KERNEL);
1212 if (!context)
1213 return -ENOMEM;
1214
1215 err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL);
1216 if (err) {
1217 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1218 goto out;
1219 }
1220 qp->event = mlx4_en_sqp_event;
1221
1222 memset(context, 0, sizeof *context);
1223 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1224 qpn, ring->cqn, -1, context);
1225 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1226
1227 /* Cancel FCS removal if FW allows */
1228 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1229 context->param3 |= cpu_to_be32(1 << 29);
1230 if (priv->dev->features & NETIF_F_RXFCS)
1231 ring->fcs_del = 0;
1232 else
1233 ring->fcs_del = ETH_FCS_LEN;
1234 } else
1235 ring->fcs_del = 0;
1236
1237 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1238 if (err) {
1239 mlx4_qp_remove(mdev->dev, qp);
1240 mlx4_qp_free(mdev->dev, qp);
1241 }
1242 mlx4_en_update_rx_prod_db(ring);
1243 out:
1244 kfree(context);
1245 return err;
1246 }
1247
1248 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1249 {
1250 int err;
1251 u32 qpn;
1252
1253 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,
1254 MLX4_RESERVE_A0_QP);
1255 if (err) {
1256 en_err(priv, "Failed reserving drop qpn\n");
1257 return err;
1258 }
1259 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL);
1260 if (err) {
1261 en_err(priv, "Failed allocating drop qp\n");
1262 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1263 return err;
1264 }
1265
1266 return 0;
1267 }
1268
1269 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1270 {
1271 u32 qpn;
1272
1273 qpn = priv->drop_qp.qpn;
1274 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1275 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1276 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1277 }
1278
1279 /* Allocate rx qp's and configure them according to rss map */
1280 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1281 {
1282 struct mlx4_en_dev *mdev = priv->mdev;
1283 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1284 struct mlx4_qp_context context;
1285 struct mlx4_rss_context *rss_context;
1286 int rss_rings;
1287 void *ptr;
1288 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1289 MLX4_RSS_TCP_IPV6);
1290 int i, qpn;
1291 int err = 0;
1292 int good_qps = 0;
1293
1294 en_dbg(DRV, priv, "Configuring rss steering\n");
1295 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1296 priv->rx_ring_num,
1297 &rss_map->base_qpn, 0);
1298 if (err) {
1299 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1300 return err;
1301 }
1302
1303 for (i = 0; i < priv->rx_ring_num; i++) {
1304 qpn = rss_map->base_qpn + i;
1305 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1306 &rss_map->state[i],
1307 &rss_map->qps[i]);
1308 if (err)
1309 goto rss_err;
1310
1311 ++good_qps;
1312 }
1313
1314 /* Configure RSS indirection qp */
1315 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL);
1316 if (err) {
1317 en_err(priv, "Failed to allocate RSS indirection QP\n");
1318 goto rss_err;
1319 }
1320 rss_map->indir_qp.event = mlx4_en_sqp_event;
1321 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1322 priv->rx_ring[0]->cqn, -1, &context);
1323
1324 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1325 rss_rings = priv->rx_ring_num;
1326 else
1327 rss_rings = priv->prof->rss_rings;
1328
1329 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1330 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1331 rss_context = ptr;
1332 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1333 (rss_map->base_qpn));
1334 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1335 if (priv->mdev->profile.udp_rss) {
1336 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1337 rss_context->base_qpn_udp = rss_context->default_qpn;
1338 }
1339
1340 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1341 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1342 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1343 }
1344
1345 rss_context->flags = rss_mask;
1346 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1347 if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1348 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1349 } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1350 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1351 memcpy(rss_context->rss_key, priv->rss_key,
1352 MLX4_EN_RSS_KEY_SIZE);
1353 } else {
1354 en_err(priv, "Unknown RSS hash function requested\n");
1355 err = -EINVAL;
1356 goto indir_err;
1357 }
1358 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1359 &rss_map->indir_qp, &rss_map->indir_state);
1360 if (err)
1361 goto indir_err;
1362
1363 return 0;
1364
1365 indir_err:
1366 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1367 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1368 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1369 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1370 rss_err:
1371 for (i = 0; i < good_qps; i++) {
1372 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1373 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1374 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1375 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1376 }
1377 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1378 return err;
1379 }
1380
1381 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1382 {
1383 struct mlx4_en_dev *mdev = priv->mdev;
1384 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1385 int i;
1386
1387 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1388 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1389 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1390 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1391
1392 for (i = 0; i < priv->rx_ring_num; i++) {
1393 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1394 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1395 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1396 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1397 }
1398 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1399 }
Linux kernel - Deliverables
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