2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/if_vlan.h>
34 #include <linux/etherdevice.h>
35 #include <linux/timecounter.h>
36 #include <linux/net_tstamp.h>
37 #include <linux/ptp_clock_kernel.h>
38 #include <linux/mlx5/driver.h>
39 #include <linux/mlx5/qp.h>
40 #include <linux/mlx5/cq.h>
41 #include <linux/mlx5/vport.h>
42 #include <linux/mlx5/transobj.h>
44 #include "mlx5_core.h"
46 #define MLX5E_MAX_NUM_TC 8
48 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
49 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
50 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
52 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
53 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
54 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
56 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
57 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
58 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
59 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
60 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
61 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
63 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
64 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
65 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
66 #define MLX5E_TX_CQ_POLL_BUDGET 128
67 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
68 #define MLX5E_SQ_BF_BUDGET 16
70 #define MLX5E_NUM_MAIN_GROUPS 9
72 static const char vport_strings
[][ETH_GSTRING_LEN
] = {
73 /* vport statistics */
86 "rx_multicast_packets",
88 "tx_multicast_packets",
90 "rx_broadcast_packets",
92 "tx_broadcast_packets",
110 struct mlx5e_vport_stats
{
116 u64 rx_error_packets
;
118 u64 tx_error_packets
;
120 u64 rx_unicast_packets
;
121 u64 rx_unicast_bytes
;
122 u64 tx_unicast_packets
;
123 u64 tx_unicast_bytes
;
124 u64 rx_multicast_packets
;
125 u64 rx_multicast_bytes
;
126 u64 tx_multicast_packets
;
127 u64 tx_multicast_bytes
;
128 u64 rx_broadcast_packets
;
129 u64 rx_broadcast_bytes
;
130 u64 tx_broadcast_packets
;
131 u64 tx_broadcast_bytes
;
142 u64 tx_queue_stopped
;
144 u64 tx_queue_dropped
;
147 #define NUM_VPORT_COUNTERS 32
150 static const char pport_strings
[][ETH_GSTRING_LEN
] = {
151 /* IEEE802.3 counters */
162 "in_range_len_errors",
172 /* RFC2863 counters */
184 "out_multicast_pkts",
185 "out_broadcast_pkts",
187 /* RFC2819 counters */
208 "p8192to10239octets",
211 #define NUM_IEEE_802_3_COUNTERS 19
212 #define NUM_RFC_2863_COUNTERS 13
213 #define NUM_RFC_2819_COUNTERS 21
214 #define NUM_PPORT_COUNTERS (NUM_IEEE_802_3_COUNTERS + \
215 NUM_RFC_2863_COUNTERS + \
216 NUM_RFC_2819_COUNTERS)
218 struct mlx5e_pport_stats
{
219 __be64 IEEE_802_3_counters
[NUM_IEEE_802_3_COUNTERS
];
220 __be64 RFC_2863_counters
[NUM_RFC_2863_COUNTERS
];
221 __be64 RFC_2819_counters
[NUM_RFC_2819_COUNTERS
];
224 static const char rq_stats_strings
[][ETH_GSTRING_LEN
] = {
233 struct mlx5e_rq_stats
{
240 #define NUM_RQ_STATS 6
243 static const char sq_stats_strings
[][ETH_GSTRING_LEN
] = {
254 struct mlx5e_sq_stats
{
258 u64 csum_offload_none
;
263 #define NUM_SQ_STATS 8
267 struct mlx5e_vport_stats vport
;
268 struct mlx5e_pport_stats pport
;
271 struct mlx5e_params
{
275 u8 default_vlan_prio
;
277 u16 rx_cq_moderation_usec
;
278 u16 rx_cq_moderation_pkts
;
279 u16 tx_cq_moderation_usec
;
280 u16 tx_cq_moderation_pkts
;
286 u8 toeplitz_hash_key
[40];
287 u32 indirection_rqt
[MLX5E_INDIR_RQT_SIZE
];
290 struct mlx5e_tstamp
{
292 struct cyclecounter cycles
;
293 struct timecounter clock
;
294 struct hwtstamp_config hwtstamp_config
;
296 unsigned long overflow_period
;
297 struct delayed_work overflow_work
;
298 struct mlx5_core_dev
*mdev
;
299 struct ptp_clock
*ptp
;
300 struct ptp_clock_info ptp_info
;
304 MLX5E_RQ_STATE_POST_WQES_ENABLE
,
308 MLX5E_CQ_HAS_CQES
= 1,
312 /* data path - accessed per cqe */
316 /* data path - accessed per napi poll */
317 struct napi_struct
*napi
;
318 struct mlx5_core_cq mcq
;
319 struct mlx5e_channel
*channel
;
320 struct mlx5e_priv
*priv
;
323 struct mlx5_wq_ctrl wq_ctrl
;
324 } ____cacheline_aligned_in_smp
;
328 struct mlx5_wq_ll wq
;
330 struct sk_buff
**skb
;
333 struct net_device
*netdev
;
334 struct mlx5e_tstamp
*tstamp
;
335 struct mlx5e_rq_stats stats
;
342 struct mlx5_wq_ctrl wq_ctrl
;
344 struct mlx5e_channel
*channel
;
345 struct mlx5e_priv
*priv
;
346 } ____cacheline_aligned_in_smp
;
348 struct mlx5e_tx_wqe_info
{
354 enum mlx5e_dma_map_type
{
355 MLX5E_DMA_MAP_SINGLE
,
359 struct mlx5e_sq_dma
{
362 enum mlx5e_dma_map_type type
;
366 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE
,
372 /* dirtied @completion */
377 u16 pc ____cacheline_aligned_in_smp
;
382 struct mlx5e_sq_stats stats
;
386 /* pointers to per packet info: write@xmit, read@completion */
387 struct sk_buff
**skb
;
388 struct mlx5e_sq_dma
*dma_fifo
;
389 struct mlx5e_tx_wqe_info
*wqe_info
;
392 struct mlx5_wq_cyc wq
;
394 void __iomem
*uar_map
;
395 void __iomem
*uar_bf_map
;
396 struct netdev_queue
*txq
;
402 struct mlx5e_tstamp
*tstamp
;
407 struct mlx5_wq_ctrl wq_ctrl
;
409 struct mlx5e_channel
*channel
;
411 } ____cacheline_aligned_in_smp
;
413 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq
*sq
, u16 n
)
415 return (((sq
->wq
.sz_m1
& (sq
->cc
- sq
->pc
)) >= n
) ||
420 MLX5E_CHANNEL_NAPI_SCHED
= 1,
423 struct mlx5e_channel
{
426 struct mlx5e_sq sq
[MLX5E_MAX_NUM_TC
];
427 struct napi_struct napi
;
429 struct net_device
*netdev
;
435 struct mlx5e_priv
*priv
;
440 enum mlx5e_traffic_types
{
445 MLX5E_TT_IPV4_IPSEC_AH
,
446 MLX5E_TT_IPV6_IPSEC_AH
,
447 MLX5E_TT_IPV4_IPSEC_ESP
,
448 MLX5E_TT_IPV6_IPSEC_ESP
,
456 MLX5E_INDIRECTION_RQT
,
461 struct mlx5e_eth_addr_info
{
462 u8 addr
[ETH_ALEN
+ 2];
464 struct mlx5_flow_rule
*ft_rule
[MLX5E_NUM_TT
];
467 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
469 struct mlx5e_eth_addr_db
{
470 struct hlist_head netdev_uc
[MLX5E_ETH_ADDR_HASH_SIZE
];
471 struct hlist_head netdev_mc
[MLX5E_ETH_ADDR_HASH_SIZE
];
472 struct mlx5e_eth_addr_info broadcast
;
473 struct mlx5e_eth_addr_info allmulti
;
474 struct mlx5e_eth_addr_info promisc
;
475 bool broadcast_enabled
;
476 bool allmulti_enabled
;
477 bool promisc_enabled
;
481 MLX5E_STATE_ASYNC_EVENTS_ENABLE
,
483 MLX5E_STATE_DESTROYING
,
486 struct mlx5e_vlan_db
{
487 unsigned long active_vlans
[BITS_TO_LONGS(VLAN_N_VID
)];
488 struct mlx5_flow_rule
*active_vlans_rule
[VLAN_N_VID
];
489 struct mlx5_flow_rule
*untagged_rule
;
490 struct mlx5_flow_rule
*any_vlan_rule
;
491 bool filter_disabled
;
494 struct mlx5e_flow_table
{
496 struct mlx5_flow_table
*t
;
497 struct mlx5_flow_group
**g
;
500 struct mlx5e_flow_tables
{
501 struct mlx5_flow_namespace
*ns
;
502 struct mlx5e_flow_table vlan
;
503 struct mlx5e_flow_table main
;
507 /* priv data path fields - start */
508 int default_vlan_prio
;
509 struct mlx5e_sq
**txq_to_sq_map
;
510 int channeltc_to_txq_map
[MLX5E_MAX_NUM_CHANNELS
][MLX5E_MAX_NUM_TC
];
511 /* priv data path fields - end */
514 struct mutex state_lock
; /* Protects Interface state */
515 struct mlx5_uar cq_uar
;
518 struct mlx5_core_mr mr
;
519 struct mlx5e_rq drop_rq
;
521 struct mlx5e_channel
**channel
;
522 u32 tisn
[MLX5E_MAX_NUM_TC
];
523 u32 rqtn
[MLX5E_NUM_RQT
];
524 u32 tirn
[MLX5E_NUM_TT
];
526 struct mlx5e_flow_tables fts
;
527 struct mlx5e_eth_addr_db eth_addr
;
528 struct mlx5e_vlan_db vlan
;
530 struct mlx5e_params params
;
531 spinlock_t async_events_spinlock
; /* sync hw events */
532 struct work_struct update_carrier_work
;
533 struct work_struct set_rx_mode_work
;
534 struct delayed_work update_stats_work
;
536 struct mlx5_core_dev
*mdev
;
537 struct net_device
*netdev
;
538 struct mlx5e_stats stats
;
539 struct mlx5e_tstamp tstamp
;
542 #define MLX5E_NET_IP_ALIGN 2
544 struct mlx5e_tx_wqe
{
545 struct mlx5_wqe_ctrl_seg ctrl
;
546 struct mlx5_wqe_eth_seg eth
;
549 struct mlx5e_rx_wqe
{
550 struct mlx5_wqe_srq_next_seg next
;
551 struct mlx5_wqe_data_seg data
;
554 enum mlx5e_link_mode
{
555 MLX5E_1000BASE_CX_SGMII
= 0,
556 MLX5E_1000BASE_KX
= 1,
557 MLX5E_10GBASE_CX4
= 2,
558 MLX5E_10GBASE_KX4
= 3,
559 MLX5E_10GBASE_KR
= 4,
560 MLX5E_20GBASE_KR2
= 5,
561 MLX5E_40GBASE_CR4
= 6,
562 MLX5E_40GBASE_KR4
= 7,
563 MLX5E_56GBASE_R4
= 8,
564 MLX5E_10GBASE_CR
= 12,
565 MLX5E_10GBASE_SR
= 13,
566 MLX5E_10GBASE_ER
= 14,
567 MLX5E_40GBASE_SR4
= 15,
568 MLX5E_40GBASE_LR4
= 16,
569 MLX5E_100GBASE_CR4
= 20,
570 MLX5E_100GBASE_SR4
= 21,
571 MLX5E_100GBASE_KR4
= 22,
572 MLX5E_100GBASE_LR4
= 23,
573 MLX5E_100BASE_TX
= 24,
574 MLX5E_100BASE_T
= 25,
575 MLX5E_10GBASE_T
= 26,
576 MLX5E_25GBASE_CR
= 27,
577 MLX5E_25GBASE_KR
= 28,
578 MLX5E_25GBASE_SR
= 29,
579 MLX5E_50GBASE_CR2
= 30,
580 MLX5E_50GBASE_KR2
= 31,
581 MLX5E_LINK_MODES_NUMBER
,
584 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
586 void mlx5e_send_nop(struct mlx5e_sq
*sq
, bool notify_hw
);
587 u16
mlx5e_select_queue(struct net_device
*dev
, struct sk_buff
*skb
,
588 void *accel_priv
, select_queue_fallback_t fallback
);
589 netdev_tx_t
mlx5e_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
591 void mlx5e_completion_event(struct mlx5_core_cq
*mcq
);
592 void mlx5e_cq_error_event(struct mlx5_core_cq
*mcq
, enum mlx5_event event
);
593 int mlx5e_napi_poll(struct napi_struct
*napi
, int budget
);
594 bool mlx5e_poll_tx_cq(struct mlx5e_cq
*cq
);
595 int mlx5e_poll_rx_cq(struct mlx5e_cq
*cq
, int budget
);
596 bool mlx5e_post_rx_wqes(struct mlx5e_rq
*rq
);
597 struct mlx5_cqe64
*mlx5e_get_cqe(struct mlx5e_cq
*cq
);
599 void mlx5e_update_stats(struct mlx5e_priv
*priv
);
601 int mlx5e_create_flow_tables(struct mlx5e_priv
*priv
);
602 void mlx5e_destroy_flow_tables(struct mlx5e_priv
*priv
);
603 void mlx5e_init_eth_addr(struct mlx5e_priv
*priv
);
604 void mlx5e_set_rx_mode_work(struct work_struct
*work
);
606 void mlx5e_fill_hwstamp(struct mlx5e_tstamp
*clock
, u64 timestamp
,
607 struct skb_shared_hwtstamps
*hwts
);
608 void mlx5e_timestamp_init(struct mlx5e_priv
*priv
);
609 void mlx5e_timestamp_cleanup(struct mlx5e_priv
*priv
);
610 int mlx5e_hwstamp_set(struct net_device
*dev
, struct ifreq
*ifr
);
611 int mlx5e_hwstamp_get(struct net_device
*dev
, struct ifreq
*ifr
);
613 int mlx5e_vlan_rx_add_vid(struct net_device
*dev
, __always_unused __be16 proto
,
615 int mlx5e_vlan_rx_kill_vid(struct net_device
*dev
, __always_unused __be16 proto
,
617 void mlx5e_enable_vlan_filter(struct mlx5e_priv
*priv
);
618 void mlx5e_disable_vlan_filter(struct mlx5e_priv
*priv
);
620 int mlx5e_redirect_rqt(struct mlx5e_priv
*priv
, enum mlx5e_rqt_ix rqt_ix
);
622 int mlx5e_open_locked(struct net_device
*netdev
);
623 int mlx5e_close_locked(struct net_device
*netdev
);
625 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq
*sq
,
626 struct mlx5e_tx_wqe
*wqe
, int bf_sz
)
628 u16 ofst
= MLX5_BF_OFFSET
+ sq
->bf_offset
;
630 /* ensure wqe is visible to device before updating doorbell record */
633 *sq
->wq
.db
= cpu_to_be32(sq
->pc
);
635 /* ensure doorbell record is visible to device before ringing the
641 __iowrite64_copy(sq
->uar_bf_map
+ ofst
, &wqe
->ctrl
, bf_sz
);
643 /* flush the write-combining mapped buffer */
647 mlx5_write64((__be32
*)&wqe
->ctrl
, sq
->uar_map
+ ofst
, NULL
);
650 sq
->bf_offset
^= sq
->bf_buf_size
;
653 static inline void mlx5e_cq_arm(struct mlx5e_cq
*cq
)
655 struct mlx5_core_cq
*mcq
;
658 mlx5_cq_arm(mcq
, MLX5_CQ_DB_REQ_NOT
, mcq
->uar
->map
, NULL
, cq
->wq
.cc
);
661 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev
*mdev
)
663 return min_t(int, mdev
->priv
.eq_table
.num_comp_vectors
,
664 MLX5E_MAX_NUM_CHANNELS
);
667 extern const struct ethtool_ops mlx5e_ethtool_ops
;
668 u16
mlx5e_get_max_inline_cap(struct mlx5_core_dev
*mdev
);