drivers/net/ethernet/mellanox/mlx5/core/eq.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/interrupt.h>
  34 #include <linux/module.h>
  35 #include <linux/mlx5/driver.h>
  36 #include <linux/mlx5/cmd.h>
  37 #include "mlx5_core.h"
  38 #ifdef CONFIG_MLX5_CORE_EN
  39 #include "eswitch.h"
  40 #endif
  41
  42 enum {
  43         MLX5_EQE_SIZE           = sizeof(struct mlx5_eqe),
  44         MLX5_EQE_OWNER_INIT_VAL = 0x1,
  45 };
  46
  47 enum {
  48         MLX5_EQ_STATE_ARMED             = 0x9,
  49         MLX5_EQ_STATE_FIRED             = 0xa,
  50         MLX5_EQ_STATE_ALWAYS_ARMED      = 0xb,
  51 };
  52
  53 enum {
  54         MLX5_NUM_SPARE_EQE      = 0x80,
  55         MLX5_NUM_ASYNC_EQE      = 0x100,
  56         MLX5_NUM_CMD_EQE        = 32,
  57 };
  58
  59 enum {
  60         MLX5_EQ_DOORBEL_OFFSET  = 0x40,
  61 };
  62
  63 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG)           | \
  64                                (1ull << MLX5_EVENT_TYPE_COMM_EST)           | \
  65                                (1ull << MLX5_EVENT_TYPE_SQ_DRAINED)         | \
  66                                (1ull << MLX5_EVENT_TYPE_CQ_ERROR)           | \
  67                                (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR)     | \
  68                                (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED)    | \
  69                                (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
  70                                (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR)    | \
  71                                (1ull << MLX5_EVENT_TYPE_PORT_CHANGE)        | \
  72                                (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR)    | \
  73                                (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE)       | \
  74                                (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
  75
  76 struct map_eq_in {
  77         u64     mask;
  78         u32     reserved;
  79         u32     unmap_eqn;
  80 };
  81
  82 struct cre_des_eq {
  83         u8      reserved[15];
  84         u8      eqn;
  85 };
  86
  87 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
  88 {
  89         u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0};
  90         u32 in[MLX5_ST_SZ_DW(destroy_eq_in)]   = {0};
  91
  92         MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
  93         MLX5_SET(destroy_eq_in, in, eq_number, eqn);
  94         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
  95 }
  96
  97 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
  98 {
  99         return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
 100 }
 101
 102 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
 103 {
 104         struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
 105
 106         return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
 107 }
 108
 109 static const char *eqe_type_str(u8 type)
 110 {
 111         switch (type) {
 112         case MLX5_EVENT_TYPE_COMP:
 113                 return "MLX5_EVENT_TYPE_COMP";
 114         case MLX5_EVENT_TYPE_PATH_MIG:
 115                 return "MLX5_EVENT_TYPE_PATH_MIG";
 116         case MLX5_EVENT_TYPE_COMM_EST:
 117                 return "MLX5_EVENT_TYPE_COMM_EST";
 118         case MLX5_EVENT_TYPE_SQ_DRAINED:
 119                 return "MLX5_EVENT_TYPE_SQ_DRAINED";
 120         case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 121                 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
 122         case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
 123                 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
 124         case MLX5_EVENT_TYPE_CQ_ERROR:
 125                 return "MLX5_EVENT_TYPE_CQ_ERROR";
 126         case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 127                 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
 128         case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 129                 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
 130         case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 131                 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
 132         case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 133                 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
 134         case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
 135                 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
 136         case MLX5_EVENT_TYPE_INTERNAL_ERROR:
 137                 return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
 138         case MLX5_EVENT_TYPE_PORT_CHANGE:
 139                 return "MLX5_EVENT_TYPE_PORT_CHANGE";
 140         case MLX5_EVENT_TYPE_GPIO_EVENT:
 141                 return "MLX5_EVENT_TYPE_GPIO_EVENT";
 142         case MLX5_EVENT_TYPE_REMOTE_CONFIG:
 143                 return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
 144         case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
 145                 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
 146         case MLX5_EVENT_TYPE_STALL_EVENT:
 147                 return "MLX5_EVENT_TYPE_STALL_EVENT";
 148         case MLX5_EVENT_TYPE_CMD:
 149                 return "MLX5_EVENT_TYPE_CMD";
 150         case MLX5_EVENT_TYPE_PAGE_REQUEST:
 151                 return "MLX5_EVENT_TYPE_PAGE_REQUEST";
 152         case MLX5_EVENT_TYPE_PAGE_FAULT:
 153                 return "MLX5_EVENT_TYPE_PAGE_FAULT";
 154         default:
 155                 return "Unrecognized event";
 156         }
 157 }
 158
 159 static enum mlx5_dev_event port_subtype_event(u8 subtype)
 160 {
 161         switch (subtype) {
 162         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 163                 return MLX5_DEV_EVENT_PORT_DOWN;
 164         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 165                 return MLX5_DEV_EVENT_PORT_UP;
 166         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
 167                 return MLX5_DEV_EVENT_PORT_INITIALIZED;
 168         case MLX5_PORT_CHANGE_SUBTYPE_LID:
 169                 return MLX5_DEV_EVENT_LID_CHANGE;
 170         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
 171                 return MLX5_DEV_EVENT_PKEY_CHANGE;
 172         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
 173                 return MLX5_DEV_EVENT_GUID_CHANGE;
 174         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
 175                 return MLX5_DEV_EVENT_CLIENT_REREG;
 176         }
 177         return -1;
 178 }
 179
 180 static void eq_update_ci(struct mlx5_eq *eq, int arm)
 181 {
 182         __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
 183         u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
 184         __raw_writel((__force u32) cpu_to_be32(val), addr);
 185         /* We still want ordering, just not swabbing, so add a barrier */
 186         mb();
 187 }
 188
 189 static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
 190 {
 191         struct mlx5_eqe *eqe;
 192         int eqes_found = 0;
 193         int set_ci = 0;
 194         u32 cqn = -1;
 195         u32 rsn;
 196         u8 port;
 197
 198         while ((eqe = next_eqe_sw(eq))) {
 199                 /*
 200                  * Make sure we read EQ entry contents after we've
 201                  * checked the ownership bit.
 202                  */
 203                 dma_rmb();
 204
 205                 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
 206                               eq->eqn, eqe_type_str(eqe->type));
 207                 switch (eqe->type) {
 208                 case MLX5_EVENT_TYPE_COMP:
 209                         cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
 210                         mlx5_cq_completion(dev, cqn);
 211                         break;
 212
 213                 case MLX5_EVENT_TYPE_PATH_MIG:
 214                 case MLX5_EVENT_TYPE_COMM_EST:
 215                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 216                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 217                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 218                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 219                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 220                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 221                         rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
 222                         rsn |= (eqe->data.qp_srq.type << MLX5_USER_INDEX_LEN);
 223                         mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
 224                                       eqe_type_str(eqe->type), eqe->type, rsn);
 225                         mlx5_rsc_event(dev, rsn, eqe->type);
 226                         break;
 227
 228                 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
 229                 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
 230                         rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
 231                         mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
 232                                       eqe_type_str(eqe->type), eqe->type, rsn);
 233                         mlx5_srq_event(dev, rsn, eqe->type);
 234                         break;
 235
 236                 case MLX5_EVENT_TYPE_CMD:
 237                         mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector));
 238                         break;
 239
 240                 case MLX5_EVENT_TYPE_PORT_CHANGE:
 241                         port = (eqe->data.port.port >> 4) & 0xf;
 242                         switch (eqe->sub_type) {
 243                         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 244                         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 245                         case MLX5_PORT_CHANGE_SUBTYPE_LID:
 246                         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
 247                         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
 248                         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
 249                         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
 250                                 if (dev->event)
 251                                         dev->event(dev, port_subtype_event(eqe->sub_type),
 252                                                    (unsigned long)port);
 253                                 break;
 254                         default:
 255                                 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
 256                                                port, eqe->sub_type);
 257                         }
 258                         break;
 259                 case MLX5_EVENT_TYPE_CQ_ERROR:
 260                         cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
 261                         mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n",
 262                                        cqn, eqe->data.cq_err.syndrome);
 263                         mlx5_cq_event(dev, cqn, eqe->type);
 264                         break;
 265
 266                 case MLX5_EVENT_TYPE_PAGE_REQUEST:
 267                         {
 268                                 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
 269                                 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
 270
 271                                 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
 272                                               func_id, npages);
 273                                 mlx5_core_req_pages_handler(dev, func_id, npages);
 274                         }
 275                         break;
 276
 277 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 278                 case MLX5_EVENT_TYPE_PAGE_FAULT:
 279                         mlx5_eq_pagefault(dev, eqe);
 280                         break;
 281 #endif
 282
 283 #ifdef CONFIG_MLX5_CORE_EN
 284                 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
 285                         mlx5_eswitch_vport_event(dev->priv.eswitch, eqe);
 286                         break;
 287 #endif
 288                 default:
 289                         mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
 290                                        eqe->type, eq->eqn);
 291                         break;
 292                 }
 293
 294                 ++eq->cons_index;
 295                 eqes_found = 1;
 296                 ++set_ci;
 297
 298                 /* The HCA will think the queue has overflowed if we
 299                  * don't tell it we've been processing events.  We
 300                  * create our EQs with MLX5_NUM_SPARE_EQE extra
 301                  * entries, so we must update our consumer index at
 302                  * least that often.
 303                  */
 304                 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
 305                         eq_update_ci(eq, 0);
 306                         set_ci = 0;
 307                 }
 308         }
 309
 310         eq_update_ci(eq, 1);
 311
 312         if (cqn != -1)
 313                 tasklet_schedule(&eq->tasklet_ctx.task);
 314
 315         return eqes_found;
 316 }
 317
 318 static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr)
 319 {
 320         struct mlx5_eq *eq = eq_ptr;
 321         struct mlx5_core_dev *dev = eq->dev;
 322
 323         mlx5_eq_int(dev, eq);
 324
 325         /* MSI-X vectors always belong to us */
 326         return IRQ_HANDLED;
 327 }
 328
 329 static void init_eq_buf(struct mlx5_eq *eq)
 330 {
 331         struct mlx5_eqe *eqe;
 332         int i;
 333
 334         for (i = 0; i < eq->nent; i++) {
 335                 eqe = get_eqe(eq, i);
 336                 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
 337         }
 338 }
 339
 340 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
 341                        int nent, u64 mask, const char *name, struct mlx5_uar *uar)
 342 {
 343         u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0};
 344         struct mlx5_priv *priv = &dev->priv;
 345         __be64 *pas;
 346         void *eqc;
 347         int inlen;
 348         u32 *in;
 349         int err;
 350
 351         eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
 352         eq->cons_index = 0;
 353         err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, &eq->buf);
 354         if (err)
 355                 return err;
 356
 357         init_eq_buf(eq);
 358
 359         inlen = MLX5_ST_SZ_BYTES(create_eq_in) +
 360                 MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages;
 361
 362         in = mlx5_vzalloc(inlen);
 363         if (!in) {
 364                 err = -ENOMEM;
 365                 goto err_buf;
 366         }
 367
 368         pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas);
 369         mlx5_fill_page_array(&eq->buf, pas);
 370
 371         MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ);
 372         MLX5_SET64(create_eq_in, in, event_bitmask, mask);
 373
 374         eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry);
 375         MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent));
 376         MLX5_SET(eqc, eqc, uar_page, uar->index);
 377         MLX5_SET(eqc, eqc, intr, vecidx);
 378         MLX5_SET(eqc, eqc, log_page_size,
 379                  eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
 380
 381         err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
 382         if (err)
 383                 goto err_in;
 384
 385         snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
 386                  name, pci_name(dev->pdev));
 387
 388         eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
 389         eq->irqn = priv->msix_arr[vecidx].vector;
 390         eq->dev = dev;
 391         eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET;
 392         err = request_irq(eq->irqn, mlx5_msix_handler, 0,
 393                           priv->irq_info[vecidx].name, eq);
 394         if (err)
 395                 goto err_eq;
 396
 397         err = mlx5_debug_eq_add(dev, eq);
 398         if (err)
 399                 goto err_irq;
 400
 401         INIT_LIST_HEAD(&eq->tasklet_ctx.list);
 402         INIT_LIST_HEAD(&eq->tasklet_ctx.process_list);
 403         spin_lock_init(&eq->tasklet_ctx.lock);
 404         tasklet_init(&eq->tasklet_ctx.task, mlx5_cq_tasklet_cb,
 405                      (unsigned long)&eq->tasklet_ctx);
 406
 407         /* EQs are created in ARMED state
 408          */
 409         eq_update_ci(eq, 1);
 410
 411         kvfree(in);
 412         return 0;
 413
 414 err_irq:
 415         free_irq(priv->msix_arr[vecidx].vector, eq);
 416
 417 err_eq:
 418         mlx5_cmd_destroy_eq(dev, eq->eqn);
 419
 420 err_in:
 421         kvfree(in);
 422
 423 err_buf:
 424         mlx5_buf_free(dev, &eq->buf);
 425         return err;
 426 }
 427 EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
 428
 429 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
 430 {
 431         int err;
 432
 433         mlx5_debug_eq_remove(dev, eq);
 434         free_irq(eq->irqn, eq);
 435         err = mlx5_cmd_destroy_eq(dev, eq->eqn);
 436         if (err)
 437                 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
 438                                eq->eqn);
 439         synchronize_irq(eq->irqn);
 440         tasklet_disable(&eq->tasklet_ctx.task);
 441         mlx5_buf_free(dev, &eq->buf);
 442
 443         return err;
 444 }
 445 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
 446
 447 u32 mlx5_get_msix_vec(struct mlx5_core_dev *dev, int vecidx)
 448 {
 449         return dev->priv.msix_arr[MLX5_EQ_VEC_ASYNC].vector;
 450 }
 451
 452 int mlx5_eq_init(struct mlx5_core_dev *dev)
 453 {
 454         int err;
 455
 456         spin_lock_init(&dev->priv.eq_table.lock);
 457
 458         err = mlx5_eq_debugfs_init(dev);
 459
 460         return err;
 461 }
 462
 463
 464 void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
 465 {
 466         mlx5_eq_debugfs_cleanup(dev);
 467 }
 468
 469 int mlx5_start_eqs(struct mlx5_core_dev *dev)
 470 {
 471         struct mlx5_eq_table *table = &dev->priv.eq_table;
 472         u32 async_event_mask = MLX5_ASYNC_EVENT_MASK;
 473         int err;
 474
 475         if (MLX5_CAP_GEN(dev, pg))
 476                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PAGE_FAULT);
 477
 478         if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
 479             MLX5_CAP_GEN(dev, vport_group_manager) &&
 480             mlx5_core_is_pf(dev))
 481                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
 482
 483         err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
 484                                  MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
 485                                  "mlx5_cmd_eq", &dev->priv.uuari.uars[0]);
 486         if (err) {
 487                 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
 488                 return err;
 489         }
 490
 491         mlx5_cmd_use_events(dev);
 492
 493         err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
 494                                  MLX5_NUM_ASYNC_EQE, async_event_mask,
 495                                  "mlx5_async_eq", &dev->priv.uuari.uars[0]);
 496         if (err) {
 497                 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
 498                 goto err1;
 499         }
 500
 501         err = mlx5_create_map_eq(dev, &table->pages_eq,
 502                                  MLX5_EQ_VEC_PAGES,
 503                                  /* TODO: sriov max_vf + */ 1,
 504                                  1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq",
 505                                  &dev->priv.uuari.uars[0]);
 506         if (err) {
 507                 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
 508                 goto err2;
 509         }
 510
 511         return err;
 512
 513 err2:
 514         mlx5_destroy_unmap_eq(dev, &table->async_eq);
 515
 516 err1:
 517         mlx5_cmd_use_polling(dev);
 518         mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
 519         return err;
 520 }
 521
 522 int mlx5_stop_eqs(struct mlx5_core_dev *dev)
 523 {
 524         struct mlx5_eq_table *table = &dev->priv.eq_table;
 525         int err;
 526
 527         err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
 528         if (err)
 529                 return err;
 530
 531         mlx5_destroy_unmap_eq(dev, &table->async_eq);
 532         mlx5_cmd_use_polling(dev);
 533
 534         err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
 535         if (err)
 536                 mlx5_cmd_use_events(dev);
 537
 538         return err;
 539 }
 540
 541 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
 542                        u32 *out, int outlen)
 543 {
 544         u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0};
 545
 546         MLX5_SET(query_eq_in, in, opcode, MLX5_CMD_OP_QUERY_EQ);
 547         MLX5_SET(query_eq_in, in, eq_number, eq->eqn);
 548         return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
 549 }
 550 EXPORT_SYMBOL_GPL(mlx5_core_eq_query);