2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <linux/mlx5/driver.h>
35 #include <linux/mlx5/port.h>
36 #include <linux/mlx5/cmd.h>
37 #include "mlx5_core.h"
39 int mlx5_core_access_reg(struct mlx5_core_dev
*dev
, void *data_in
,
40 int size_in
, void *data_out
, int size_out
,
41 u16 reg_id
, int arg
, int write
)
43 int outlen
= MLX5_ST_SZ_BYTES(access_register_out
) + size_out
;
44 int inlen
= MLX5_ST_SZ_BYTES(access_register_in
) + size_in
;
50 in
= mlx5_vzalloc(inlen
);
51 out
= mlx5_vzalloc(outlen
);
55 data
= MLX5_ADDR_OF(access_register_in
, in
, register_data
);
56 memcpy(data
, data_in
, size_in
);
58 MLX5_SET(access_register_in
, in
, opcode
, MLX5_CMD_OP_ACCESS_REG
);
59 MLX5_SET(access_register_in
, in
, op_mod
, !write
);
60 MLX5_SET(access_register_in
, in
, argument
, arg
);
61 MLX5_SET(access_register_in
, in
, register_id
, reg_id
);
63 err
= mlx5_cmd_exec(dev
, in
, inlen
, out
, outlen
);
67 data
= MLX5_ADDR_OF(access_register_out
, out
, register_data
);
68 memcpy(data_out
, data
, size_out
);
75 EXPORT_SYMBOL_GPL(mlx5_core_access_reg
);
77 struct mlx5_reg_pcap
{
87 int mlx5_set_port_caps(struct mlx5_core_dev
*dev
, u8 port_num
, u32 caps
)
89 struct mlx5_reg_pcap in
;
90 struct mlx5_reg_pcap out
;
92 memset(&in
, 0, sizeof(in
));
93 in
.caps_127_96
= cpu_to_be32(caps
);
94 in
.port_num
= port_num
;
96 return mlx5_core_access_reg(dev
, &in
, sizeof(in
), &out
,
97 sizeof(out
), MLX5_REG_PCAP
, 0, 1);
99 EXPORT_SYMBOL_GPL(mlx5_set_port_caps
);
101 int mlx5_query_port_ptys(struct mlx5_core_dev
*dev
, u32
*ptys
,
102 int ptys_size
, int proto_mask
, u8 local_port
)
104 u32 in
[MLX5_ST_SZ_DW(ptys_reg
)] = {0};
106 MLX5_SET(ptys_reg
, in
, local_port
, local_port
);
107 MLX5_SET(ptys_reg
, in
, proto_mask
, proto_mask
);
108 return mlx5_core_access_reg(dev
, in
, sizeof(in
), ptys
,
109 ptys_size
, MLX5_REG_PTYS
, 0, 0);
111 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys
);
113 int mlx5_set_port_beacon(struct mlx5_core_dev
*dev
, u16 beacon_duration
)
115 u32 in
[MLX5_ST_SZ_DW(mlcr_reg
)] = {0};
116 u32 out
[MLX5_ST_SZ_DW(mlcr_reg
)];
118 MLX5_SET(mlcr_reg
, in
, local_port
, 1);
119 MLX5_SET(mlcr_reg
, in
, beacon_duration
, beacon_duration
);
120 return mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
121 sizeof(out
), MLX5_REG_MLCR
, 0, 1);
124 int mlx5_query_port_proto_cap(struct mlx5_core_dev
*dev
,
125 u32
*proto_cap
, int proto_mask
)
127 u32 out
[MLX5_ST_SZ_DW(ptys_reg
)];
130 err
= mlx5_query_port_ptys(dev
, out
, sizeof(out
), proto_mask
, 1);
134 if (proto_mask
== MLX5_PTYS_EN
)
135 *proto_cap
= MLX5_GET(ptys_reg
, out
, eth_proto_capability
);
137 *proto_cap
= MLX5_GET(ptys_reg
, out
, ib_proto_capability
);
141 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap
);
143 int mlx5_query_port_proto_admin(struct mlx5_core_dev
*dev
,
144 u32
*proto_admin
, int proto_mask
)
146 u32 out
[MLX5_ST_SZ_DW(ptys_reg
)];
149 err
= mlx5_query_port_ptys(dev
, out
, sizeof(out
), proto_mask
, 1);
153 if (proto_mask
== MLX5_PTYS_EN
)
154 *proto_admin
= MLX5_GET(ptys_reg
, out
, eth_proto_admin
);
156 *proto_admin
= MLX5_GET(ptys_reg
, out
, ib_proto_admin
);
160 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin
);
162 int mlx5_query_port_link_width_oper(struct mlx5_core_dev
*dev
,
163 u8
*link_width_oper
, u8 local_port
)
165 u32 out
[MLX5_ST_SZ_DW(ptys_reg
)];
168 err
= mlx5_query_port_ptys(dev
, out
, sizeof(out
), MLX5_PTYS_IB
, local_port
);
172 *link_width_oper
= MLX5_GET(ptys_reg
, out
, ib_link_width_oper
);
176 EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper
);
178 int mlx5_query_port_eth_proto_oper(struct mlx5_core_dev
*dev
,
179 u32
*proto_oper
, u8 local_port
)
181 u32 out
[MLX5_ST_SZ_DW(ptys_reg
)];
184 err
= mlx5_query_port_ptys(dev
, out
, sizeof(out
), MLX5_PTYS_EN
,
189 *proto_oper
= MLX5_GET(ptys_reg
, out
, eth_proto_oper
);
193 EXPORT_SYMBOL(mlx5_query_port_eth_proto_oper
);
195 int mlx5_query_port_ib_proto_oper(struct mlx5_core_dev
*dev
,
196 u8
*proto_oper
, u8 local_port
)
198 u32 out
[MLX5_ST_SZ_DW(ptys_reg
)];
201 err
= mlx5_query_port_ptys(dev
, out
, sizeof(out
), MLX5_PTYS_IB
,
206 *proto_oper
= MLX5_GET(ptys_reg
, out
, ib_proto_oper
);
210 EXPORT_SYMBOL(mlx5_query_port_ib_proto_oper
);
212 int mlx5_set_port_ptys(struct mlx5_core_dev
*dev
, bool an_disable
,
213 u32 proto_admin
, int proto_mask
)
215 u32 out
[MLX5_ST_SZ_DW(ptys_reg
)];
216 u32 in
[MLX5_ST_SZ_DW(ptys_reg
)];
221 mlx5_query_port_autoneg(dev
, proto_mask
, &an_status
,
222 &an_disable_cap
, &an_disable_admin
);
223 if (!an_disable_cap
&& an_disable
)
226 memset(in
, 0, sizeof(in
));
228 MLX5_SET(ptys_reg
, in
, local_port
, 1);
229 MLX5_SET(ptys_reg
, in
, an_disable_admin
, an_disable
);
230 MLX5_SET(ptys_reg
, in
, proto_mask
, proto_mask
);
231 if (proto_mask
== MLX5_PTYS_EN
)
232 MLX5_SET(ptys_reg
, in
, eth_proto_admin
, proto_admin
);
234 MLX5_SET(ptys_reg
, in
, ib_proto_admin
, proto_admin
);
236 return mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
237 sizeof(out
), MLX5_REG_PTYS
, 0, 1);
239 EXPORT_SYMBOL_GPL(mlx5_set_port_ptys
);
241 /* This function should be used after setting a port register only */
242 void mlx5_toggle_port_link(struct mlx5_core_dev
*dev
)
244 enum mlx5_port_status ps
;
246 mlx5_query_port_admin_status(dev
, &ps
);
247 mlx5_set_port_admin_status(dev
, MLX5_PORT_DOWN
);
248 if (ps
== MLX5_PORT_UP
)
249 mlx5_set_port_admin_status(dev
, MLX5_PORT_UP
);
251 EXPORT_SYMBOL_GPL(mlx5_toggle_port_link
);
253 int mlx5_set_port_admin_status(struct mlx5_core_dev
*dev
,
254 enum mlx5_port_status status
)
256 u32 in
[MLX5_ST_SZ_DW(paos_reg
)] = {0};
257 u32 out
[MLX5_ST_SZ_DW(paos_reg
)];
259 MLX5_SET(paos_reg
, in
, local_port
, 1);
260 MLX5_SET(paos_reg
, in
, admin_status
, status
);
261 MLX5_SET(paos_reg
, in
, ase
, 1);
262 return mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
263 sizeof(out
), MLX5_REG_PAOS
, 0, 1);
265 EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status
);
267 int mlx5_query_port_admin_status(struct mlx5_core_dev
*dev
,
268 enum mlx5_port_status
*status
)
270 u32 in
[MLX5_ST_SZ_DW(paos_reg
)] = {0};
271 u32 out
[MLX5_ST_SZ_DW(paos_reg
)];
274 MLX5_SET(paos_reg
, in
, local_port
, 1);
275 err
= mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
276 sizeof(out
), MLX5_REG_PAOS
, 0, 0);
279 *status
= MLX5_GET(paos_reg
, out
, admin_status
);
282 EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status
);
284 static void mlx5_query_port_mtu(struct mlx5_core_dev
*dev
, u16
*admin_mtu
,
285 u16
*max_mtu
, u16
*oper_mtu
, u8 port
)
287 u32 in
[MLX5_ST_SZ_DW(pmtu_reg
)] = {0};
288 u32 out
[MLX5_ST_SZ_DW(pmtu_reg
)];
290 MLX5_SET(pmtu_reg
, in
, local_port
, port
);
291 mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
292 sizeof(out
), MLX5_REG_PMTU
, 0, 0);
295 *max_mtu
= MLX5_GET(pmtu_reg
, out
, max_mtu
);
297 *oper_mtu
= MLX5_GET(pmtu_reg
, out
, oper_mtu
);
299 *admin_mtu
= MLX5_GET(pmtu_reg
, out
, admin_mtu
);
302 int mlx5_set_port_mtu(struct mlx5_core_dev
*dev
, u16 mtu
, u8 port
)
304 u32 in
[MLX5_ST_SZ_DW(pmtu_reg
)] = {0};
305 u32 out
[MLX5_ST_SZ_DW(pmtu_reg
)];
307 MLX5_SET(pmtu_reg
, in
, admin_mtu
, mtu
);
308 MLX5_SET(pmtu_reg
, in
, local_port
, port
);
309 return mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
310 sizeof(out
), MLX5_REG_PMTU
, 0, 1);
312 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu
);
314 void mlx5_query_port_max_mtu(struct mlx5_core_dev
*dev
, u16
*max_mtu
,
317 mlx5_query_port_mtu(dev
, NULL
, max_mtu
, NULL
, port
);
319 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu
);
321 void mlx5_query_port_oper_mtu(struct mlx5_core_dev
*dev
, u16
*oper_mtu
,
324 mlx5_query_port_mtu(dev
, NULL
, NULL
, oper_mtu
, port
);
326 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu
);
328 static int mlx5_query_module_num(struct mlx5_core_dev
*dev
, int *module_num
)
330 u32 in
[MLX5_ST_SZ_DW(pmlp_reg
)] = {0};
331 u32 out
[MLX5_ST_SZ_DW(pmlp_reg
)];
335 MLX5_SET(pmlp_reg
, in
, local_port
, 1);
336 err
= mlx5_core_access_reg(dev
, in
, sizeof(in
), out
, sizeof(out
),
337 MLX5_REG_PMLP
, 0, 0);
341 module_mapping
= MLX5_GET(pmlp_reg
, out
, lane0_module_mapping
);
342 *module_num
= module_mapping
& MLX5_EEPROM_IDENTIFIER_BYTE_MASK
;
347 int mlx5_query_module_eeprom(struct mlx5_core_dev
*dev
,
348 u16 offset
, u16 size
, u8
*data
)
350 u32 out
[MLX5_ST_SZ_DW(mcia_reg
)];
351 u32 in
[MLX5_ST_SZ_DW(mcia_reg
)];
356 void *ptr
= MLX5_ADDR_OF(mcia_reg
, out
, dword_0
);
358 err
= mlx5_query_module_num(dev
, &module_num
);
362 memset(in
, 0, sizeof(in
));
363 size
= min_t(int, size
, MLX5_EEPROM_MAX_BYTES
);
365 if (offset
< MLX5_EEPROM_PAGE_LENGTH
&&
366 offset
+ size
> MLX5_EEPROM_PAGE_LENGTH
)
367 /* Cross pages read, read until offset 256 in low page */
368 size
-= offset
+ size
- MLX5_EEPROM_PAGE_LENGTH
;
370 i2c_addr
= MLX5_I2C_ADDR_LOW
;
371 if (offset
>= MLX5_EEPROM_PAGE_LENGTH
) {
372 i2c_addr
= MLX5_I2C_ADDR_HIGH
;
373 offset
-= MLX5_EEPROM_PAGE_LENGTH
;
376 MLX5_SET(mcia_reg
, in
, l
, 0);
377 MLX5_SET(mcia_reg
, in
, module
, module_num
);
378 MLX5_SET(mcia_reg
, in
, i2c_device_address
, i2c_addr
);
379 MLX5_SET(mcia_reg
, in
, page_number
, 0);
380 MLX5_SET(mcia_reg
, in
, device_address
, offset
);
381 MLX5_SET(mcia_reg
, in
, size
, size
);
383 err
= mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
384 sizeof(out
), MLX5_REG_MCIA
, 0, 0);
388 status
= MLX5_GET(mcia_reg
, out
, status
);
390 mlx5_core_err(dev
, "query_mcia_reg failed: status: 0x%x\n",
395 memcpy(data
, ptr
, size
);
399 EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom
);
401 static int mlx5_query_port_pvlc(struct mlx5_core_dev
*dev
, u32
*pvlc
,
402 int pvlc_size
, u8 local_port
)
404 u32 in
[MLX5_ST_SZ_DW(pvlc_reg
)] = {0};
406 MLX5_SET(pvlc_reg
, in
, local_port
, local_port
);
407 return mlx5_core_access_reg(dev
, in
, sizeof(in
), pvlc
,
408 pvlc_size
, MLX5_REG_PVLC
, 0, 0);
411 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev
*dev
,
412 u8
*vl_hw_cap
, u8 local_port
)
414 u32 out
[MLX5_ST_SZ_DW(pvlc_reg
)];
417 err
= mlx5_query_port_pvlc(dev
, out
, sizeof(out
), local_port
);
421 *vl_hw_cap
= MLX5_GET(pvlc_reg
, out
, vl_hw_cap
);
425 EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap
);
427 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev
*dev
,
428 u8 port_num
, void *out
, size_t sz
)
433 in
= mlx5_vzalloc(sz
);
439 MLX5_SET(ppcnt_reg
, in
, local_port
, port_num
);
441 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_INFINIBAND_PORT_COUNTERS_GROUP
);
442 err
= mlx5_core_access_reg(dev
, in
, sz
, out
,
443 sz
, MLX5_REG_PPCNT
, 0, 0);
448 EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt
);
450 int mlx5_set_port_pause(struct mlx5_core_dev
*dev
, u32 rx_pause
, u32 tx_pause
)
452 u32 in
[MLX5_ST_SZ_DW(pfcc_reg
)] = {0};
453 u32 out
[MLX5_ST_SZ_DW(pfcc_reg
)];
455 MLX5_SET(pfcc_reg
, in
, local_port
, 1);
456 MLX5_SET(pfcc_reg
, in
, pptx
, tx_pause
);
457 MLX5_SET(pfcc_reg
, in
, pprx
, rx_pause
);
459 return mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
460 sizeof(out
), MLX5_REG_PFCC
, 0, 1);
462 EXPORT_SYMBOL_GPL(mlx5_set_port_pause
);
464 int mlx5_query_port_pause(struct mlx5_core_dev
*dev
,
465 u32
*rx_pause
, u32
*tx_pause
)
467 u32 in
[MLX5_ST_SZ_DW(pfcc_reg
)] = {0};
468 u32 out
[MLX5_ST_SZ_DW(pfcc_reg
)];
471 MLX5_SET(pfcc_reg
, in
, local_port
, 1);
472 err
= mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
473 sizeof(out
), MLX5_REG_PFCC
, 0, 0);
478 *rx_pause
= MLX5_GET(pfcc_reg
, out
, pprx
);
481 *tx_pause
= MLX5_GET(pfcc_reg
, out
, pptx
);
485 EXPORT_SYMBOL_GPL(mlx5_query_port_pause
);
487 int mlx5_set_port_pfc(struct mlx5_core_dev
*dev
, u8 pfc_en_tx
, u8 pfc_en_rx
)
489 u32 in
[MLX5_ST_SZ_DW(pfcc_reg
)] = {0};
490 u32 out
[MLX5_ST_SZ_DW(pfcc_reg
)];
492 MLX5_SET(pfcc_reg
, in
, local_port
, 1);
493 MLX5_SET(pfcc_reg
, in
, pfctx
, pfc_en_tx
);
494 MLX5_SET(pfcc_reg
, in
, pfcrx
, pfc_en_rx
);
495 MLX5_SET_TO_ONES(pfcc_reg
, in
, prio_mask_tx
);
496 MLX5_SET_TO_ONES(pfcc_reg
, in
, prio_mask_rx
);
498 return mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
499 sizeof(out
), MLX5_REG_PFCC
, 0, 1);
501 EXPORT_SYMBOL_GPL(mlx5_set_port_pfc
);
503 int mlx5_query_port_pfc(struct mlx5_core_dev
*dev
, u8
*pfc_en_tx
, u8
*pfc_en_rx
)
505 u32 in
[MLX5_ST_SZ_DW(pfcc_reg
)] = {0};
506 u32 out
[MLX5_ST_SZ_DW(pfcc_reg
)];
509 MLX5_SET(pfcc_reg
, in
, local_port
, 1);
510 err
= mlx5_core_access_reg(dev
, in
, sizeof(in
), out
,
511 sizeof(out
), MLX5_REG_PFCC
, 0, 0);
516 *pfc_en_tx
= MLX5_GET(pfcc_reg
, out
, pfctx
);
519 *pfc_en_rx
= MLX5_GET(pfcc_reg
, out
, pfcrx
);
523 EXPORT_SYMBOL_GPL(mlx5_query_port_pfc
);
525 void mlx5_query_port_autoneg(struct mlx5_core_dev
*dev
, int proto_mask
,
527 u8
*an_disable_cap
, u8
*an_disable_admin
)
529 u32 out
[MLX5_ST_SZ_DW(ptys_reg
)];
533 *an_disable_admin
= 0;
535 if (mlx5_query_port_ptys(dev
, out
, sizeof(out
), proto_mask
, 1))
538 *an_status
= MLX5_GET(ptys_reg
, out
, an_status
);
539 *an_disable_cap
= MLX5_GET(ptys_reg
, out
, an_disable_cap
);
540 *an_disable_admin
= MLX5_GET(ptys_reg
, out
, an_disable_admin
);
542 EXPORT_SYMBOL_GPL(mlx5_query_port_autoneg
);
544 int mlx5_max_tc(struct mlx5_core_dev
*mdev
)
546 u8 num_tc
= MLX5_CAP_GEN(mdev
, max_tc
) ? : 8;
551 int mlx5_set_port_prio_tc(struct mlx5_core_dev
*mdev
, u8
*prio_tc
)
553 u32 in
[MLX5_ST_SZ_DW(qtct_reg
)] = {0};
554 u32 out
[MLX5_ST_SZ_DW(qtct_reg
)];
558 for (i
= 0; i
< 8; i
++) {
559 if (prio_tc
[i
] > mlx5_max_tc(mdev
))
562 MLX5_SET(qtct_reg
, in
, prio
, i
);
563 MLX5_SET(qtct_reg
, in
, tclass
, prio_tc
[i
]);
565 err
= mlx5_core_access_reg(mdev
, in
, sizeof(in
), out
,
566 sizeof(out
), MLX5_REG_QTCT
, 0, 1);
573 EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc
);
575 static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev
*mdev
, u32
*in
,
578 u32 out
[MLX5_ST_SZ_DW(qtct_reg
)];
580 if (!MLX5_CAP_GEN(mdev
, ets
))
583 return mlx5_core_access_reg(mdev
, in
, inlen
, out
, sizeof(out
),
584 MLX5_REG_QETCR
, 0, 1);
587 static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev
*mdev
, u32
*out
,
590 u32 in
[MLX5_ST_SZ_DW(qtct_reg
)];
592 if (!MLX5_CAP_GEN(mdev
, ets
))
595 memset(in
, 0, sizeof(in
));
596 return mlx5_core_access_reg(mdev
, in
, sizeof(in
), out
, outlen
,
597 MLX5_REG_QETCR
, 0, 0);
600 int mlx5_set_port_tc_group(struct mlx5_core_dev
*mdev
, u8
*tc_group
)
602 u32 in
[MLX5_ST_SZ_DW(qetc_reg
)] = {0};
605 for (i
= 0; i
<= mlx5_max_tc(mdev
); i
++) {
606 MLX5_SET(qetc_reg
, in
, tc_configuration
[i
].g
, 1);
607 MLX5_SET(qetc_reg
, in
, tc_configuration
[i
].group
, tc_group
[i
]);
610 return mlx5_set_port_qetcr_reg(mdev
, in
, sizeof(in
));
612 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group
);
614 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev
*mdev
, u8
*tc_bw
)
616 u32 in
[MLX5_ST_SZ_DW(qetc_reg
)] = {0};
619 for (i
= 0; i
<= mlx5_max_tc(mdev
); i
++) {
620 MLX5_SET(qetc_reg
, in
, tc_configuration
[i
].b
, 1);
621 MLX5_SET(qetc_reg
, in
, tc_configuration
[i
].bw_allocation
, tc_bw
[i
]);
624 return mlx5_set_port_qetcr_reg(mdev
, in
, sizeof(in
));
626 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc
);
628 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev
*mdev
,
632 u32 in
[MLX5_ST_SZ_DW(qetc_reg
)] = {0};
636 MLX5_SET(qetc_reg
, in
, port_number
, 1);
638 for (i
= 0; i
<= mlx5_max_tc(mdev
); i
++) {
639 ets_tcn_conf
= MLX5_ADDR_OF(qetc_reg
, in
, tc_configuration
[i
]);
641 MLX5_SET(ets_tcn_config_reg
, ets_tcn_conf
, r
, 1);
642 MLX5_SET(ets_tcn_config_reg
, ets_tcn_conf
, max_bw_units
,
644 MLX5_SET(ets_tcn_config_reg
, ets_tcn_conf
, max_bw_value
,
648 return mlx5_set_port_qetcr_reg(mdev
, in
, sizeof(in
));
650 EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit
);
652 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev
*mdev
,
656 u32 out
[MLX5_ST_SZ_DW(qetc_reg
)];
661 err
= mlx5_query_port_qetcr_reg(mdev
, out
, sizeof(out
));
665 for (i
= 0; i
<= mlx5_max_tc(mdev
); i
++) {
666 ets_tcn_conf
= MLX5_ADDR_OF(qetc_reg
, out
, tc_configuration
[i
]);
668 max_bw_value
[i
] = MLX5_GET(ets_tcn_config_reg
, ets_tcn_conf
,
670 max_bw_units
[i
] = MLX5_GET(ets_tcn_config_reg
, ets_tcn_conf
,
676 EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit
);
678 int mlx5_set_port_wol(struct mlx5_core_dev
*mdev
, u8 wol_mode
)
680 u32 in
[MLX5_ST_SZ_DW(set_wol_rol_in
)] = {0};
681 u32 out
[MLX5_ST_SZ_DW(set_wol_rol_out
)] = {0};
683 MLX5_SET(set_wol_rol_in
, in
, opcode
, MLX5_CMD_OP_SET_WOL_ROL
);
684 MLX5_SET(set_wol_rol_in
, in
, wol_mode_valid
, 1);
685 MLX5_SET(set_wol_rol_in
, in
, wol_mode
, wol_mode
);
686 return mlx5_cmd_exec(mdev
, in
, sizeof(in
), out
, sizeof(out
));
688 EXPORT_SYMBOL_GPL(mlx5_set_port_wol
);
690 int mlx5_query_port_wol(struct mlx5_core_dev
*mdev
, u8
*wol_mode
)
692 u32 in
[MLX5_ST_SZ_DW(query_wol_rol_in
)] = {0};
693 u32 out
[MLX5_ST_SZ_DW(query_wol_rol_out
)] = {0};
696 MLX5_SET(query_wol_rol_in
, in
, opcode
, MLX5_CMD_OP_QUERY_WOL_ROL
);
697 err
= mlx5_cmd_exec(mdev
, in
, sizeof(in
), out
, sizeof(out
));
699 *wol_mode
= MLX5_GET(query_wol_rol_out
, out
, wol_mode
);
703 EXPORT_SYMBOL_GPL(mlx5_query_port_wol
);
705 static int mlx5_query_ports_check(struct mlx5_core_dev
*mdev
, u32
*out
,
708 u32 in
[MLX5_ST_SZ_DW(pcmr_reg
)] = {0};
710 MLX5_SET(pcmr_reg
, in
, local_port
, 1);
711 return mlx5_core_access_reg(mdev
, in
, sizeof(in
), out
,
712 outlen
, MLX5_REG_PCMR
, 0, 0);
715 static int mlx5_set_ports_check(struct mlx5_core_dev
*mdev
, u32
*in
, int inlen
)
717 u32 out
[MLX5_ST_SZ_DW(pcmr_reg
)];
719 return mlx5_core_access_reg(mdev
, in
, inlen
, out
,
720 sizeof(out
), MLX5_REG_PCMR
, 0, 1);
723 int mlx5_set_port_fcs(struct mlx5_core_dev
*mdev
, u8 enable
)
725 u32 in
[MLX5_ST_SZ_DW(pcmr_reg
)] = {0};
727 MLX5_SET(pcmr_reg
, in
, local_port
, 1);
728 MLX5_SET(pcmr_reg
, in
, fcs_chk
, enable
);
729 return mlx5_set_ports_check(mdev
, in
, sizeof(in
));
732 void mlx5_query_port_fcs(struct mlx5_core_dev
*mdev
, bool *supported
,
735 u32 out
[MLX5_ST_SZ_DW(pcmr_reg
)];
736 /* Default values for FW which do not support MLX5_REG_PCMR */
740 if (!MLX5_CAP_GEN(mdev
, ports_check
))
743 if (mlx5_query_ports_check(mdev
, out
, sizeof(out
)))
746 *supported
= !!(MLX5_GET(pcmr_reg
, out
, fcs_cap
));
747 *enabled
= !!(MLX5_GET(pcmr_reg
, out
, fcs_chk
));