drivers/net/ethernet/mellanox/mlxsw/reg.h

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/reg.h
   3  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2015-2016 Ido Schimmel <idosch@mellanox.com>
   5  * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
   6  * Copyright (c) 2015-2016 Jiri Pirko <jiri@mellanox.com>
   7  * Copyright (c) 2016 Yotam Gigi <yotamg@mellanox.com>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions are met:
  11  *
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. Neither the names of the copyright holders nor the names of its
  18  *    contributors may be used to endorse or promote products derived from
  19  *    this software without specific prior written permission.
  20  *
  21  * Alternatively, this software may be distributed under the terms of the
  22  * GNU General Public License ("GPL") version 2 as published by the Free
  23  * Software Foundation.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  26  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  27  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  28  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  29  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef _MLXSW_REG_H
  39 #define _MLXSW_REG_H
  40
  41 #include <linux/string.h>
  42 #include <linux/bitops.h>
  43 #include <linux/if_vlan.h>
  44
  45 #include "item.h"
  46 #include "port.h"
  47
  48 struct mlxsw_reg_info {
  49         u16 id;
  50         u16 len; /* In u8 */
  51 };
  52
  53 #define MLXSW_REG(type) (&mlxsw_reg_##type)
  54 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
  55 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
  56
  57 /* SGCR - Switch General Configuration Register
  58  * --------------------------------------------
  59  * This register is used for configuration of the switch capabilities.
  60  */
  61 #define MLXSW_REG_SGCR_ID 0x2000
  62 #define MLXSW_REG_SGCR_LEN 0x10
  63
  64 static const struct mlxsw_reg_info mlxsw_reg_sgcr = {
  65         .id = MLXSW_REG_SGCR_ID,
  66         .len = MLXSW_REG_SGCR_LEN,
  67 };
  68
  69 /* reg_sgcr_llb
  70  * Link Local Broadcast (Default=0)
  71  * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
  72  * packets and ignore the IGMP snooping entries.
  73  * Access: RW
  74  */
  75 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
  76
  77 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
  78 {
  79         MLXSW_REG_ZERO(sgcr, payload);
  80         mlxsw_reg_sgcr_llb_set(payload, !!llb);
  81 }
  82
  83 /* SPAD - Switch Physical Address Register
  84  * ---------------------------------------
  85  * The SPAD register configures the switch physical MAC address.
  86  */
  87 #define MLXSW_REG_SPAD_ID 0x2002
  88 #define MLXSW_REG_SPAD_LEN 0x10
  89
  90 static const struct mlxsw_reg_info mlxsw_reg_spad = {
  91         .id = MLXSW_REG_SPAD_ID,
  92         .len = MLXSW_REG_SPAD_LEN,
  93 };
  94
  95 /* reg_spad_base_mac
  96  * Base MAC address for the switch partitions.
  97  * Per switch partition MAC address is equal to:
  98  * base_mac + swid
  99  * Access: RW
 100  */
 101 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
 102
 103 /* SMID - Switch Multicast ID
 104  * --------------------------
 105  * The MID record maps from a MID (Multicast ID), which is a unique identifier
 106  * of the multicast group within the stacking domain, into a list of local
 107  * ports into which the packet is replicated.
 108  */
 109 #define MLXSW_REG_SMID_ID 0x2007
 110 #define MLXSW_REG_SMID_LEN 0x240
 111
 112 static const struct mlxsw_reg_info mlxsw_reg_smid = {
 113         .id = MLXSW_REG_SMID_ID,
 114         .len = MLXSW_REG_SMID_LEN,
 115 };
 116
 117 /* reg_smid_swid
 118  * Switch partition ID.
 119  * Access: Index
 120  */
 121 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
 122
 123 /* reg_smid_mid
 124  * Multicast identifier - global identifier that represents the multicast group
 125  * across all devices.
 126  * Access: Index
 127  */
 128 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
 129
 130 /* reg_smid_port
 131  * Local port memebership (1 bit per port).
 132  * Access: RW
 133  */
 134 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
 135
 136 /* reg_smid_port_mask
 137  * Local port mask (1 bit per port).
 138  * Access: W
 139  */
 140 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
 141
 142 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
 143                                        u8 port, bool set)
 144 {
 145         MLXSW_REG_ZERO(smid, payload);
 146         mlxsw_reg_smid_swid_set(payload, 0);
 147         mlxsw_reg_smid_mid_set(payload, mid);
 148         mlxsw_reg_smid_port_set(payload, port, set);
 149         mlxsw_reg_smid_port_mask_set(payload, port, 1);
 150 }
 151
 152 /* SSPR - Switch System Port Record Register
 153  * -----------------------------------------
 154  * Configures the system port to local port mapping.
 155  */
 156 #define MLXSW_REG_SSPR_ID 0x2008
 157 #define MLXSW_REG_SSPR_LEN 0x8
 158
 159 static const struct mlxsw_reg_info mlxsw_reg_sspr = {
 160         .id = MLXSW_REG_SSPR_ID,
 161         .len = MLXSW_REG_SSPR_LEN,
 162 };
 163
 164 /* reg_sspr_m
 165  * Master - if set, then the record describes the master system port.
 166  * This is needed in case a local port is mapped into several system ports
 167  * (for multipathing). That number will be reported as the source system
 168  * port when packets are forwarded to the CPU. Only one master port is allowed
 169  * per local port.
 170  *
 171  * Note: Must be set for Spectrum.
 172  * Access: RW
 173  */
 174 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
 175
 176 /* reg_sspr_local_port
 177  * Local port number.
 178  *
 179  * Access: RW
 180  */
 181 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
 182
 183 /* reg_sspr_sub_port
 184  * Virtual port within the physical port.
 185  * Should be set to 0 when virtual ports are not enabled on the port.
 186  *
 187  * Access: RW
 188  */
 189 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
 190
 191 /* reg_sspr_system_port
 192  * Unique identifier within the stacking domain that represents all the ports
 193  * that are available in the system (external ports).
 194  *
 195  * Currently, only single-ASIC configurations are supported, so we default to
 196  * 1:1 mapping between system ports and local ports.
 197  * Access: Index
 198  */
 199 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
 200
 201 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
 202 {
 203         MLXSW_REG_ZERO(sspr, payload);
 204         mlxsw_reg_sspr_m_set(payload, 1);
 205         mlxsw_reg_sspr_local_port_set(payload, local_port);
 206         mlxsw_reg_sspr_sub_port_set(payload, 0);
 207         mlxsw_reg_sspr_system_port_set(payload, local_port);
 208 }
 209
 210 /* SFDAT - Switch Filtering Database Aging Time
 211  * --------------------------------------------
 212  * Controls the Switch aging time. Aging time is able to be set per Switch
 213  * Partition.
 214  */
 215 #define MLXSW_REG_SFDAT_ID 0x2009
 216 #define MLXSW_REG_SFDAT_LEN 0x8
 217
 218 static const struct mlxsw_reg_info mlxsw_reg_sfdat = {
 219         .id = MLXSW_REG_SFDAT_ID,
 220         .len = MLXSW_REG_SFDAT_LEN,
 221 };
 222
 223 /* reg_sfdat_swid
 224  * Switch partition ID.
 225  * Access: Index
 226  */
 227 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
 228
 229 /* reg_sfdat_age_time
 230  * Aging time in seconds
 231  * Min - 10 seconds
 232  * Max - 1,000,000 seconds
 233  * Default is 300 seconds.
 234  * Access: RW
 235  */
 236 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
 237
 238 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
 239 {
 240         MLXSW_REG_ZERO(sfdat, payload);
 241         mlxsw_reg_sfdat_swid_set(payload, 0);
 242         mlxsw_reg_sfdat_age_time_set(payload, age_time);
 243 }
 244
 245 /* SFD - Switch Filtering Database
 246  * -------------------------------
 247  * The following register defines the access to the filtering database.
 248  * The register supports querying, adding, removing and modifying the database.
 249  * The access is optimized for bulk updates in which case more than one
 250  * FDB record is present in the same command.
 251  */
 252 #define MLXSW_REG_SFD_ID 0x200A
 253 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
 254 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
 255 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
 256 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN +     \
 257                            MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
 258
 259 static const struct mlxsw_reg_info mlxsw_reg_sfd = {
 260         .id = MLXSW_REG_SFD_ID,
 261         .len = MLXSW_REG_SFD_LEN,
 262 };
 263
 264 /* reg_sfd_swid
 265  * Switch partition ID for queries. Reserved on Write.
 266  * Access: Index
 267  */
 268 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
 269
 270 enum mlxsw_reg_sfd_op {
 271         /* Dump entire FDB a (process according to record_locator) */
 272         MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
 273         /* Query records by {MAC, VID/FID} value */
 274         MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
 275         /* Query and clear activity. Query records by {MAC, VID/FID} value */
 276         MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
 277         /* Test. Response indicates if each of the records could be
 278          * added to the FDB.
 279          */
 280         MLXSW_REG_SFD_OP_WRITE_TEST = 0,
 281         /* Add/modify. Aged-out records cannot be added. This command removes
 282          * the learning notification of the {MAC, VID/FID}. Response includes
 283          * the entries that were added to the FDB.
 284          */
 285         MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
 286         /* Remove record by {MAC, VID/FID}. This command also removes
 287          * the learning notification and aged-out notifications
 288          * of the {MAC, VID/FID}. The response provides current (pre-removal)
 289          * entries as non-aged-out.
 290          */
 291         MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
 292         /* Remove learned notification by {MAC, VID/FID}. The response provides
 293          * the removed learning notification.
 294          */
 295         MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
 296 };
 297
 298 /* reg_sfd_op
 299  * Operation.
 300  * Access: OP
 301  */
 302 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
 303
 304 /* reg_sfd_record_locator
 305  * Used for querying the FDB. Use record_locator=0 to initiate the
 306  * query. When a record is returned, a new record_locator is
 307  * returned to be used in the subsequent query.
 308  * Reserved for database update.
 309  * Access: Index
 310  */
 311 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
 312
 313 /* reg_sfd_num_rec
 314  * Request: Number of records to read/add/modify/remove
 315  * Response: Number of records read/added/replaced/removed
 316  * See above description for more details.
 317  * Ranges 0..64
 318  * Access: RW
 319  */
 320 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
 321
 322 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
 323                                       u32 record_locator)
 324 {
 325         MLXSW_REG_ZERO(sfd, payload);
 326         mlxsw_reg_sfd_op_set(payload, op);
 327         mlxsw_reg_sfd_record_locator_set(payload, record_locator);
 328 }
 329
 330 /* reg_sfd_rec_swid
 331  * Switch partition ID.
 332  * Access: Index
 333  */
 334 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
 335                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 336
 337 enum mlxsw_reg_sfd_rec_type {
 338         MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
 339         MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
 340         MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
 341 };
 342
 343 /* reg_sfd_rec_type
 344  * FDB record type.
 345  * Access: RW
 346  */
 347 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
 348                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 349
 350 enum mlxsw_reg_sfd_rec_policy {
 351         /* Replacement disabled, aging disabled. */
 352         MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
 353         /* (mlag remote): Replacement enabled, aging disabled,
 354          * learning notification enabled on this port.
 355          */
 356         MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
 357         /* (ingress device): Replacement enabled, aging enabled. */
 358         MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
 359 };
 360
 361 /* reg_sfd_rec_policy
 362  * Policy.
 363  * Access: RW
 364  */
 365 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
 366                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 367
 368 /* reg_sfd_rec_a
 369  * Activity. Set for new static entries. Set for static entries if a frame SMAC
 370  * lookup hits on the entry.
 371  * To clear the a bit, use "query and clear activity" op.
 372  * Access: RO
 373  */
 374 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
 375                      MLXSW_REG_SFD_REC_LEN, 0x00, false);
 376
 377 /* reg_sfd_rec_mac
 378  * MAC address.
 379  * Access: Index
 380  */
 381 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
 382                        MLXSW_REG_SFD_REC_LEN, 0x02);
 383
 384 enum mlxsw_reg_sfd_rec_action {
 385         /* forward */
 386         MLXSW_REG_SFD_REC_ACTION_NOP = 0,
 387         /* forward and trap, trap_id is FDB_TRAP */
 388         MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
 389         /* trap and do not forward, trap_id is FDB_TRAP */
 390         MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
 391         /* forward to IP router */
 392         MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
 393         MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
 394 };
 395
 396 /* reg_sfd_rec_action
 397  * Action to apply on the packet.
 398  * Note: Dynamic entries can only be configured with NOP action.
 399  * Access: RW
 400  */
 401 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
 402                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 403
 404 /* reg_sfd_uc_sub_port
 405  * VEPA channel on local port.
 406  * Valid only if local port is a non-stacking port. Must be 0 if multichannel
 407  * VEPA is not enabled.
 408  * Access: RW
 409  */
 410 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
 411                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 412
 413 /* reg_sfd_uc_fid_vid
 414  * Filtering ID or VLAN ID
 415  * For SwitchX and SwitchX-2:
 416  * - Dynamic entries (policy 2,3) use FID
 417  * - Static entries (policy 0) use VID
 418  * - When independent learning is configured, VID=FID
 419  * For Spectrum: use FID for both Dynamic and Static entries.
 420  * VID should not be used.
 421  * Access: Index
 422  */
 423 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 424                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 425
 426 /* reg_sfd_uc_system_port
 427  * Unique port identifier for the final destination of the packet.
 428  * Access: RW
 429  */
 430 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 431                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 432
 433 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
 434                                           enum mlxsw_reg_sfd_rec_type rec_type,
 435                                           const char *mac,
 436                                           enum mlxsw_reg_sfd_rec_action action)
 437 {
 438         u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
 439
 440         if (rec_index >= num_rec)
 441                 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
 442         mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
 443         mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
 444         mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
 445         mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
 446 }
 447
 448 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
 449                                          enum mlxsw_reg_sfd_rec_policy policy,
 450                                          const char *mac, u16 fid_vid,
 451                                          enum mlxsw_reg_sfd_rec_action action,
 452                                          u8 local_port)
 453 {
 454         mlxsw_reg_sfd_rec_pack(payload, rec_index,
 455                                MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
 456         mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
 457         mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
 458         mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
 459         mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
 460 }
 461
 462 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
 463                                            char *mac, u16 *p_fid_vid,
 464                                            u8 *p_local_port)
 465 {
 466         mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
 467         *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
 468         *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
 469 }
 470
 471 /* reg_sfd_uc_lag_sub_port
 472  * LAG sub port.
 473  * Must be 0 if multichannel VEPA is not enabled.
 474  * Access: RW
 475  */
 476 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
 477                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 478
 479 /* reg_sfd_uc_lag_fid_vid
 480  * Filtering ID or VLAN ID
 481  * For SwitchX and SwitchX-2:
 482  * - Dynamic entries (policy 2,3) use FID
 483  * - Static entries (policy 0) use VID
 484  * - When independent learning is configured, VID=FID
 485  * For Spectrum: use FID for both Dynamic and Static entries.
 486  * VID should not be used.
 487  * Access: Index
 488  */
 489 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 490                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 491
 492 /* reg_sfd_uc_lag_lag_vid
 493  * Indicates VID in case of vFIDs. Reserved for FIDs.
 494  * Access: RW
 495  */
 496 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
 497                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 498
 499 /* reg_sfd_uc_lag_lag_id
 500  * LAG Identifier - pointer into the LAG descriptor table.
 501  * Access: RW
 502  */
 503 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
 504                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 505
 506 static inline void
 507 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
 508                           enum mlxsw_reg_sfd_rec_policy policy,
 509                           const char *mac, u16 fid_vid,
 510                           enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
 511                           u16 lag_id)
 512 {
 513         mlxsw_reg_sfd_rec_pack(payload, rec_index,
 514                                MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
 515                                mac, action);
 516         mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
 517         mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
 518         mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
 519         mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
 520         mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
 521 }
 522
 523 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
 524                                                char *mac, u16 *p_vid,
 525                                                u16 *p_lag_id)
 526 {
 527         mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
 528         *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
 529         *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
 530 }
 531
 532 /* reg_sfd_mc_pgi
 533  *
 534  * Multicast port group index - index into the port group table.
 535  * Value 0x1FFF indicates the pgi should point to the MID entry.
 536  * For Spectrum this value must be set to 0x1FFF
 537  * Access: RW
 538  */
 539 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
 540                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 541
 542 /* reg_sfd_mc_fid_vid
 543  *
 544  * Filtering ID or VLAN ID
 545  * Access: Index
 546  */
 547 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 548                      MLXSW_REG_SFD_REC_LEN, 0x08, false);
 549
 550 /* reg_sfd_mc_mid
 551  *
 552  * Multicast identifier - global identifier that represents the multicast
 553  * group across all devices.
 554  * Access: RW
 555  */
 556 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
 557                      MLXSW_REG_SFD_REC_LEN, 0x0C, false);
 558
 559 static inline void
 560 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
 561                       const char *mac, u16 fid_vid,
 562                       enum mlxsw_reg_sfd_rec_action action, u16 mid)
 563 {
 564         mlxsw_reg_sfd_rec_pack(payload, rec_index,
 565                                MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
 566         mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
 567         mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
 568         mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
 569 }
 570
 571 /* SFN - Switch FDB Notification Register
 572  * -------------------------------------------
 573  * The switch provides notifications on newly learned FDB entries and
 574  * aged out entries. The notifications can be polled by software.
 575  */
 576 #define MLXSW_REG_SFN_ID 0x200B
 577 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
 578 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
 579 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
 580 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN +     \
 581                            MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
 582
 583 static const struct mlxsw_reg_info mlxsw_reg_sfn = {
 584         .id = MLXSW_REG_SFN_ID,
 585         .len = MLXSW_REG_SFN_LEN,
 586 };
 587
 588 /* reg_sfn_swid
 589  * Switch partition ID.
 590  * Access: Index
 591  */
 592 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
 593
 594 /* reg_sfn_num_rec
 595  * Request: Number of learned notifications and aged-out notification
 596  * records requested.
 597  * Response: Number of notification records returned (must be smaller
 598  * than or equal to the value requested)
 599  * Ranges 0..64
 600  * Access: OP
 601  */
 602 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
 603
 604 static inline void mlxsw_reg_sfn_pack(char *payload)
 605 {
 606         MLXSW_REG_ZERO(sfn, payload);
 607         mlxsw_reg_sfn_swid_set(payload, 0);
 608         mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
 609 }
 610
 611 /* reg_sfn_rec_swid
 612  * Switch partition ID.
 613  * Access: RO
 614  */
 615 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
 616                      MLXSW_REG_SFN_REC_LEN, 0x00, false);
 617
 618 enum mlxsw_reg_sfn_rec_type {
 619         /* MAC addresses learned on a regular port. */
 620         MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
 621         /* MAC addresses learned on a LAG port. */
 622         MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
 623         /* Aged-out MAC address on a regular port. */
 624         MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
 625         /* Aged-out MAC address on a LAG port. */
 626         MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
 627 };
 628
 629 /* reg_sfn_rec_type
 630  * Notification record type.
 631  * Access: RO
 632  */
 633 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
 634                      MLXSW_REG_SFN_REC_LEN, 0x00, false);
 635
 636 /* reg_sfn_rec_mac
 637  * MAC address.
 638  * Access: RO
 639  */
 640 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
 641                        MLXSW_REG_SFN_REC_LEN, 0x02);
 642
 643 /* reg_sfn_mac_sub_port
 644  * VEPA channel on the local port.
 645  * 0 if multichannel VEPA is not enabled.
 646  * Access: RO
 647  */
 648 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
 649                      MLXSW_REG_SFN_REC_LEN, 0x08, false);
 650
 651 /* reg_sfn_mac_fid
 652  * Filtering identifier.
 653  * Access: RO
 654  */
 655 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
 656                      MLXSW_REG_SFN_REC_LEN, 0x08, false);
 657
 658 /* reg_sfn_mac_system_port
 659  * Unique port identifier for the final destination of the packet.
 660  * Access: RO
 661  */
 662 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
 663                      MLXSW_REG_SFN_REC_LEN, 0x0C, false);
 664
 665 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
 666                                             char *mac, u16 *p_vid,
 667                                             u8 *p_local_port)
 668 {
 669         mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
 670         *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
 671         *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
 672 }
 673
 674 /* reg_sfn_mac_lag_lag_id
 675  * LAG ID (pointer into the LAG descriptor table).
 676  * Access: RO
 677  */
 678 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
 679                      MLXSW_REG_SFN_REC_LEN, 0x0C, false);
 680
 681 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
 682                                                 char *mac, u16 *p_vid,
 683                                                 u16 *p_lag_id)
 684 {
 685         mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
 686         *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
 687         *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
 688 }
 689
 690 /* SPMS - Switch Port MSTP/RSTP State Register
 691  * -------------------------------------------
 692  * Configures the spanning tree state of a physical port.
 693  */
 694 #define MLXSW_REG_SPMS_ID 0x200D
 695 #define MLXSW_REG_SPMS_LEN 0x404
 696
 697 static const struct mlxsw_reg_info mlxsw_reg_spms = {
 698         .id = MLXSW_REG_SPMS_ID,
 699         .len = MLXSW_REG_SPMS_LEN,
 700 };
 701
 702 /* reg_spms_local_port
 703  * Local port number.
 704  * Access: Index
 705  */
 706 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
 707
 708 enum mlxsw_reg_spms_state {
 709         MLXSW_REG_SPMS_STATE_NO_CHANGE,
 710         MLXSW_REG_SPMS_STATE_DISCARDING,
 711         MLXSW_REG_SPMS_STATE_LEARNING,
 712         MLXSW_REG_SPMS_STATE_FORWARDING,
 713 };
 714
 715 /* reg_spms_state
 716  * Spanning tree state of each VLAN ID (VID) of the local port.
 717  * 0 - Do not change spanning tree state (used only when writing).
 718  * 1 - Discarding. No learning or forwarding to/from this port (default).
 719  * 2 - Learning. Port is learning, but not forwarding.
 720  * 3 - Forwarding. Port is learning and forwarding.
 721  * Access: RW
 722  */
 723 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
 724
 725 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
 726 {
 727         MLXSW_REG_ZERO(spms, payload);
 728         mlxsw_reg_spms_local_port_set(payload, local_port);
 729 }
 730
 731 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
 732                                            enum mlxsw_reg_spms_state state)
 733 {
 734         mlxsw_reg_spms_state_set(payload, vid, state);
 735 }
 736
 737 /* SPVID - Switch Port VID
 738  * -----------------------
 739  * The switch port VID configures the default VID for a port.
 740  */
 741 #define MLXSW_REG_SPVID_ID 0x200E
 742 #define MLXSW_REG_SPVID_LEN 0x08
 743
 744 static const struct mlxsw_reg_info mlxsw_reg_spvid = {
 745         .id = MLXSW_REG_SPVID_ID,
 746         .len = MLXSW_REG_SPVID_LEN,
 747 };
 748
 749 /* reg_spvid_local_port
 750  * Local port number.
 751  * Access: Index
 752  */
 753 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
 754
 755 /* reg_spvid_sub_port
 756  * Virtual port within the physical port.
 757  * Should be set to 0 when virtual ports are not enabled on the port.
 758  * Access: Index
 759  */
 760 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
 761
 762 /* reg_spvid_pvid
 763  * Port default VID
 764  * Access: RW
 765  */
 766 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
 767
 768 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
 769 {
 770         MLXSW_REG_ZERO(spvid, payload);
 771         mlxsw_reg_spvid_local_port_set(payload, local_port);
 772         mlxsw_reg_spvid_pvid_set(payload, pvid);
 773 }
 774
 775 /* SPVM - Switch Port VLAN Membership
 776  * ----------------------------------
 777  * The Switch Port VLAN Membership register configures the VLAN membership
 778  * of a port in a VLAN denoted by VID. VLAN membership is managed per
 779  * virtual port. The register can be used to add and remove VID(s) from a port.
 780  */
 781 #define MLXSW_REG_SPVM_ID 0x200F
 782 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
 783 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
 784 #define MLXSW_REG_SPVM_REC_MAX_COUNT 256
 785 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN +   \
 786                     MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
 787
 788 static const struct mlxsw_reg_info mlxsw_reg_spvm = {
 789         .id = MLXSW_REG_SPVM_ID,
 790         .len = MLXSW_REG_SPVM_LEN,
 791 };
 792
 793 /* reg_spvm_pt
 794  * Priority tagged. If this bit is set, packets forwarded to the port with
 795  * untagged VLAN membership (u bit is set) will be tagged with priority tag
 796  * (VID=0)
 797  * Access: RW
 798  */
 799 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
 800
 801 /* reg_spvm_pte
 802  * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
 803  * the pt bit will NOT be updated. To update the pt bit, pte must be set.
 804  * Access: WO
 805  */
 806 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
 807
 808 /* reg_spvm_local_port
 809  * Local port number.
 810  * Access: Index
 811  */
 812 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
 813
 814 /* reg_spvm_sub_port
 815  * Virtual port within the physical port.
 816  * Should be set to 0 when virtual ports are not enabled on the port.
 817  * Access: Index
 818  */
 819 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
 820
 821 /* reg_spvm_num_rec
 822  * Number of records to update. Each record contains: i, e, u, vid.
 823  * Access: OP
 824  */
 825 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
 826
 827 /* reg_spvm_rec_i
 828  * Ingress membership in VLAN ID.
 829  * Access: Index
 830  */
 831 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
 832                      MLXSW_REG_SPVM_BASE_LEN, 14, 1,
 833                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 834
 835 /* reg_spvm_rec_e
 836  * Egress membership in VLAN ID.
 837  * Access: Index
 838  */
 839 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
 840                      MLXSW_REG_SPVM_BASE_LEN, 13, 1,
 841                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 842
 843 /* reg_spvm_rec_u
 844  * Untagged - port is an untagged member - egress transmission uses untagged
 845  * frames on VID<n>
 846  * Access: Index
 847  */
 848 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
 849                      MLXSW_REG_SPVM_BASE_LEN, 12, 1,
 850                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 851
 852 /* reg_spvm_rec_vid
 853  * Egress membership in VLAN ID.
 854  * Access: Index
 855  */
 856 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
 857                      MLXSW_REG_SPVM_BASE_LEN, 0, 12,
 858                      MLXSW_REG_SPVM_REC_LEN, 0, false);
 859
 860 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
 861                                        u16 vid_begin, u16 vid_end,
 862                                        bool is_member, bool untagged)
 863 {
 864         int size = vid_end - vid_begin + 1;
 865         int i;
 866
 867         MLXSW_REG_ZERO(spvm, payload);
 868         mlxsw_reg_spvm_local_port_set(payload, local_port);
 869         mlxsw_reg_spvm_num_rec_set(payload, size);
 870
 871         for (i = 0; i < size; i++) {
 872                 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
 873                 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
 874                 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
 875                 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
 876         }
 877 }
 878
 879 /* SPAFT - Switch Port Acceptable Frame Types
 880  * ------------------------------------------
 881  * The Switch Port Acceptable Frame Types register configures the frame
 882  * admittance of the port.
 883  */
 884 #define MLXSW_REG_SPAFT_ID 0x2010
 885 #define MLXSW_REG_SPAFT_LEN 0x08
 886
 887 static const struct mlxsw_reg_info mlxsw_reg_spaft = {
 888         .id = MLXSW_REG_SPAFT_ID,
 889         .len = MLXSW_REG_SPAFT_LEN,
 890 };
 891
 892 /* reg_spaft_local_port
 893  * Local port number.
 894  * Access: Index
 895  *
 896  * Note: CPU port is not supported (all tag types are allowed).
 897  */
 898 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
 899
 900 /* reg_spaft_sub_port
 901  * Virtual port within the physical port.
 902  * Should be set to 0 when virtual ports are not enabled on the port.
 903  * Access: RW
 904  */
 905 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
 906
 907 /* reg_spaft_allow_untagged
 908  * When set, untagged frames on the ingress are allowed (default).
 909  * Access: RW
 910  */
 911 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
 912
 913 /* reg_spaft_allow_prio_tagged
 914  * When set, priority tagged frames on the ingress are allowed (default).
 915  * Access: RW
 916  */
 917 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
 918
 919 /* reg_spaft_allow_tagged
 920  * When set, tagged frames on the ingress are allowed (default).
 921  * Access: RW
 922  */
 923 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
 924
 925 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
 926                                         bool allow_untagged)
 927 {
 928         MLXSW_REG_ZERO(spaft, payload);
 929         mlxsw_reg_spaft_local_port_set(payload, local_port);
 930         mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
 931         mlxsw_reg_spaft_allow_prio_tagged_set(payload, true);
 932         mlxsw_reg_spaft_allow_tagged_set(payload, true);
 933 }
 934
 935 /* SFGC - Switch Flooding Group Configuration
 936  * ------------------------------------------
 937  * The following register controls the association of flooding tables and MIDs
 938  * to packet types used for flooding.
 939  */
 940 #define MLXSW_REG_SFGC_ID 0x2011
 941 #define MLXSW_REG_SFGC_LEN 0x10
 942
 943 static const struct mlxsw_reg_info mlxsw_reg_sfgc = {
 944         .id = MLXSW_REG_SFGC_ID,
 945         .len = MLXSW_REG_SFGC_LEN,
 946 };
 947
 948 enum mlxsw_reg_sfgc_type {
 949         MLXSW_REG_SFGC_TYPE_BROADCAST,
 950         MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
 951         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
 952         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
 953         MLXSW_REG_SFGC_TYPE_RESERVED,
 954         MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
 955         MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
 956         MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
 957         MLXSW_REG_SFGC_TYPE_MAX,
 958 };
 959
 960 /* reg_sfgc_type
 961  * The traffic type to reach the flooding table.
 962  * Access: Index
 963  */
 964 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
 965
 966 enum mlxsw_reg_sfgc_bridge_type {
 967         MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
 968         MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
 969 };
 970
 971 /* reg_sfgc_bridge_type
 972  * Access: Index
 973  *
 974  * Note: SwitchX-2 only supports 802.1Q mode.
 975  */
 976 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
 977
 978 enum mlxsw_flood_table_type {
 979         MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
 980         MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
 981         MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
 982         MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3,
 983         MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
 984 };
 985
 986 /* reg_sfgc_table_type
 987  * See mlxsw_flood_table_type
 988  * Access: RW
 989  *
 990  * Note: FID offset and FID types are not supported in SwitchX-2.
 991  */
 992 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
 993
 994 /* reg_sfgc_flood_table
 995  * Flooding table index to associate with the specific type on the specific
 996  * switch partition.
 997  * Access: RW
 998  */
 999 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1000
1001 /* reg_sfgc_mid
1002  * The multicast ID for the swid. Not supported for Spectrum
1003  * Access: RW
1004  */
1005 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1006
1007 /* reg_sfgc_counter_set_type
1008  * Counter Set Type for flow counters.
1009  * Access: RW
1010  */
1011 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1012
1013 /* reg_sfgc_counter_index
1014  * Counter Index for flow counters.
1015  * Access: RW
1016  */
1017 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1018
1019 static inline void
1020 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1021                     enum mlxsw_reg_sfgc_bridge_type bridge_type,
1022                     enum mlxsw_flood_table_type table_type,
1023                     unsigned int flood_table)
1024 {
1025         MLXSW_REG_ZERO(sfgc, payload);
1026         mlxsw_reg_sfgc_type_set(payload, type);
1027         mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1028         mlxsw_reg_sfgc_table_type_set(payload, table_type);
1029         mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1030         mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1031 }
1032
1033 /* SFTR - Switch Flooding Table Register
1034  * -------------------------------------
1035  * The switch flooding table is used for flooding packet replication. The table
1036  * defines a bit mask of ports for packet replication.
1037  */
1038 #define MLXSW_REG_SFTR_ID 0x2012
1039 #define MLXSW_REG_SFTR_LEN 0x420
1040
1041 static const struct mlxsw_reg_info mlxsw_reg_sftr = {
1042         .id = MLXSW_REG_SFTR_ID,
1043         .len = MLXSW_REG_SFTR_LEN,
1044 };
1045
1046 /* reg_sftr_swid
1047  * Switch partition ID with which to associate the port.
1048  * Access: Index
1049  */
1050 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1051
1052 /* reg_sftr_flood_table
1053  * Flooding table index to associate with the specific type on the specific
1054  * switch partition.
1055  * Access: Index
1056  */
1057 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1058
1059 /* reg_sftr_index
1060  * Index. Used as an index into the Flooding Table in case the table is
1061  * configured to use VID / FID or FID Offset.
1062  * Access: Index
1063  */
1064 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1065
1066 /* reg_sftr_table_type
1067  * See mlxsw_flood_table_type
1068  * Access: RW
1069  */
1070 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1071
1072 /* reg_sftr_range
1073  * Range of entries to update
1074  * Access: Index
1075  */
1076 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1077
1078 /* reg_sftr_port
1079  * Local port membership (1 bit per port).
1080  * Access: RW
1081  */
1082 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1083
1084 /* reg_sftr_cpu_port_mask
1085  * CPU port mask (1 bit per port).
1086  * Access: W
1087  */
1088 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1089
1090 static inline void mlxsw_reg_sftr_pack(char *payload,
1091                                        unsigned int flood_table,
1092                                        unsigned int index,
1093                                        enum mlxsw_flood_table_type table_type,
1094                                        unsigned int range, u8 port, bool set)
1095 {
1096         MLXSW_REG_ZERO(sftr, payload);
1097         mlxsw_reg_sftr_swid_set(payload, 0);
1098         mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1099         mlxsw_reg_sftr_index_set(payload, index);
1100         mlxsw_reg_sftr_table_type_set(payload, table_type);
1101         mlxsw_reg_sftr_range_set(payload, range);
1102         mlxsw_reg_sftr_port_set(payload, port, set);
1103         mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1104 }
1105
1106 /* SFDF - Switch Filtering DB Flush
1107  * --------------------------------
1108  * The switch filtering DB flush register is used to flush the FDB.
1109  * Note that FDB notifications are flushed as well.
1110  */
1111 #define MLXSW_REG_SFDF_ID 0x2013
1112 #define MLXSW_REG_SFDF_LEN 0x14
1113
1114 static const struct mlxsw_reg_info mlxsw_reg_sfdf = {
1115         .id = MLXSW_REG_SFDF_ID,
1116         .len = MLXSW_REG_SFDF_LEN,
1117 };
1118
1119 /* reg_sfdf_swid
1120  * Switch partition ID.
1121  * Access: Index
1122  */
1123 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1124
1125 enum mlxsw_reg_sfdf_flush_type {
1126         MLXSW_REG_SFDF_FLUSH_PER_SWID,
1127         MLXSW_REG_SFDF_FLUSH_PER_FID,
1128         MLXSW_REG_SFDF_FLUSH_PER_PORT,
1129         MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1130         MLXSW_REG_SFDF_FLUSH_PER_LAG,
1131         MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1132 };
1133
1134 /* reg_sfdf_flush_type
1135  * Flush type.
1136  * 0 - All SWID dynamic entries are flushed.
1137  * 1 - All FID dynamic entries are flushed.
1138  * 2 - All dynamic entries pointing to port are flushed.
1139  * 3 - All FID dynamic entries pointing to port are flushed.
1140  * 4 - All dynamic entries pointing to LAG are flushed.
1141  * 5 - All FID dynamic entries pointing to LAG are flushed.
1142  * Access: RW
1143  */
1144 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1145
1146 /* reg_sfdf_flush_static
1147  * Static.
1148  * 0 - Flush only dynamic entries.
1149  * 1 - Flush both dynamic and static entries.
1150  * Access: RW
1151  */
1152 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1153
1154 static inline void mlxsw_reg_sfdf_pack(char *payload,
1155                                        enum mlxsw_reg_sfdf_flush_type type)
1156 {
1157         MLXSW_REG_ZERO(sfdf, payload);
1158         mlxsw_reg_sfdf_flush_type_set(payload, type);
1159         mlxsw_reg_sfdf_flush_static_set(payload, true);
1160 }
1161
1162 /* reg_sfdf_fid
1163  * FID to flush.
1164  * Access: RW
1165  */
1166 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1167
1168 /* reg_sfdf_system_port
1169  * Port to flush.
1170  * Access: RW
1171  */
1172 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1173
1174 /* reg_sfdf_port_fid_system_port
1175  * Port to flush, pointed to by FID.
1176  * Access: RW
1177  */
1178 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1179
1180 /* reg_sfdf_lag_id
1181  * LAG ID to flush.
1182  * Access: RW
1183  */
1184 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1185
1186 /* reg_sfdf_lag_fid_lag_id
1187  * LAG ID to flush, pointed to by FID.
1188  * Access: RW
1189  */
1190 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1191
1192 /* SLDR - Switch LAG Descriptor Register
1193  * -----------------------------------------
1194  * The switch LAG descriptor register is populated by LAG descriptors.
1195  * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1196  * max_lag-1.
1197  */
1198 #define MLXSW_REG_SLDR_ID 0x2014
1199 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1200
1201 static const struct mlxsw_reg_info mlxsw_reg_sldr = {
1202         .id = MLXSW_REG_SLDR_ID,
1203         .len = MLXSW_REG_SLDR_LEN,
1204 };
1205
1206 enum mlxsw_reg_sldr_op {
1207         /* Indicates a creation of a new LAG-ID, lag_id must be valid */
1208         MLXSW_REG_SLDR_OP_LAG_CREATE,
1209         MLXSW_REG_SLDR_OP_LAG_DESTROY,
1210         /* Ports that appear in the list have the Distributor enabled */
1211         MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1212         /* Removes ports from the disributor list */
1213         MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1214 };
1215
1216 /* reg_sldr_op
1217  * Operation.
1218  * Access: RW
1219  */
1220 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1221
1222 /* reg_sldr_lag_id
1223  * LAG identifier. The lag_id is the index into the LAG descriptor table.
1224  * Access: Index
1225  */
1226 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1227
1228 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1229 {
1230         MLXSW_REG_ZERO(sldr, payload);
1231         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1232         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1233 }
1234
1235 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1236 {
1237         MLXSW_REG_ZERO(sldr, payload);
1238         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1239         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1240 }
1241
1242 /* reg_sldr_num_ports
1243  * The number of member ports of the LAG.
1244  * Reserved for Create / Destroy operations
1245  * For Add / Remove operations - indicates the number of ports in the list.
1246  * Access: RW
1247  */
1248 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1249
1250 /* reg_sldr_system_port
1251  * System port.
1252  * Access: RW
1253  */
1254 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1255
1256 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1257                                                     u8 local_port)
1258 {
1259         MLXSW_REG_ZERO(sldr, payload);
1260         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1261         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1262         mlxsw_reg_sldr_num_ports_set(payload, 1);
1263         mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1264 }
1265
1266 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1267                                                        u8 local_port)
1268 {
1269         MLXSW_REG_ZERO(sldr, payload);
1270         mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1271         mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1272         mlxsw_reg_sldr_num_ports_set(payload, 1);
1273         mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1274 }
1275
1276 /* SLCR - Switch LAG Configuration 2 Register
1277  * -------------------------------------------
1278  * The Switch LAG Configuration register is used for configuring the
1279  * LAG properties of the switch.
1280  */
1281 #define MLXSW_REG_SLCR_ID 0x2015
1282 #define MLXSW_REG_SLCR_LEN 0x10
1283
1284 static const struct mlxsw_reg_info mlxsw_reg_slcr = {
1285         .id = MLXSW_REG_SLCR_ID,
1286         .len = MLXSW_REG_SLCR_LEN,
1287 };
1288
1289 enum mlxsw_reg_slcr_pp {
1290         /* Global Configuration (for all ports) */
1291         MLXSW_REG_SLCR_PP_GLOBAL,
1292         /* Per port configuration, based on local_port field */
1293         MLXSW_REG_SLCR_PP_PER_PORT,
1294 };
1295
1296 /* reg_slcr_pp
1297  * Per Port Configuration
1298  * Note: Reading at Global mode results in reading port 1 configuration.
1299  * Access: Index
1300  */
1301 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1302
1303 /* reg_slcr_local_port
1304  * Local port number
1305  * Supported from CPU port
1306  * Not supported from router port
1307  * Reserved when pp = Global Configuration
1308  * Access: Index
1309  */
1310 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1311
1312 enum mlxsw_reg_slcr_type {
1313         MLXSW_REG_SLCR_TYPE_CRC, /* default */
1314         MLXSW_REG_SLCR_TYPE_XOR,
1315         MLXSW_REG_SLCR_TYPE_RANDOM,
1316 };
1317
1318 /* reg_slcr_type
1319  * Hash type
1320  * Access: RW
1321  */
1322 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1323
1324 /* Ingress port */
1325 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT         BIT(0)
1326 /* SMAC - for IPv4 and IPv6 packets */
1327 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP         BIT(1)
1328 /* SMAC - for non-IP packets */
1329 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP      BIT(2)
1330 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1331         (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1332          MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1333 /* DMAC - for IPv4 and IPv6 packets */
1334 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP         BIT(3)
1335 /* DMAC - for non-IP packets */
1336 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP      BIT(4)
1337 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1338         (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1339          MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1340 /* Ethertype - for IPv4 and IPv6 packets */
1341 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP    BIT(5)
1342 /* Ethertype - for non-IP packets */
1343 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1344 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1345         (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1346          MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1347 /* VLAN ID - for IPv4 and IPv6 packets */
1348 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP       BIT(7)
1349 /* VLAN ID - for non-IP packets */
1350 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP    BIT(8)
1351 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1352         (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1353          MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1354 /* Source IP address (can be IPv4 or IPv6) */
1355 #define MLXSW_REG_SLCR_LAG_HASH_SIP             BIT(9)
1356 /* Destination IP address (can be IPv4 or IPv6) */
1357 #define MLXSW_REG_SLCR_LAG_HASH_DIP             BIT(10)
1358 /* TCP/UDP source port */
1359 #define MLXSW_REG_SLCR_LAG_HASH_SPORT           BIT(11)
1360 /* TCP/UDP destination port*/
1361 #define MLXSW_REG_SLCR_LAG_HASH_DPORT           BIT(12)
1362 /* IPv4 Protocol/IPv6 Next Header */
1363 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO         BIT(13)
1364 /* IPv6 Flow label */
1365 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL       BIT(14)
1366 /* SID - FCoE source ID */
1367 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID        BIT(15)
1368 /* DID - FCoE destination ID */
1369 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID        BIT(16)
1370 /* OXID - FCoE originator exchange ID */
1371 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID       BIT(17)
1372 /* Destination QP number - for RoCE packets */
1373 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP        BIT(19)
1374
1375 /* reg_slcr_lag_hash
1376  * LAG hashing configuration. This is a bitmask, in which each set
1377  * bit includes the corresponding item in the LAG hash calculation.
1378  * The default lag_hash contains SMAC, DMAC, VLANID and
1379  * Ethertype (for all packet types).
1380  * Access: RW
1381  */
1382 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1383
1384 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash)
1385 {
1386         MLXSW_REG_ZERO(slcr, payload);
1387         mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1388         mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_XOR);
1389         mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1390 }
1391
1392 /* SLCOR - Switch LAG Collector Register
1393  * -------------------------------------
1394  * The Switch LAG Collector register controls the Local Port membership
1395  * in a LAG and enablement of the collector.
1396  */
1397 #define MLXSW_REG_SLCOR_ID 0x2016
1398 #define MLXSW_REG_SLCOR_LEN 0x10
1399
1400 static const struct mlxsw_reg_info mlxsw_reg_slcor = {
1401         .id = MLXSW_REG_SLCOR_ID,
1402         .len = MLXSW_REG_SLCOR_LEN,
1403 };
1404
1405 enum mlxsw_reg_slcor_col {
1406         /* Port is added with collector disabled */
1407         MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1408         MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1409         MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1410         MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1411 };
1412
1413 /* reg_slcor_col
1414  * Collector configuration
1415  * Access: RW
1416  */
1417 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1418
1419 /* reg_slcor_local_port
1420  * Local port number
1421  * Not supported for CPU port
1422  * Access: Index
1423  */
1424 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1425
1426 /* reg_slcor_lag_id
1427  * LAG Identifier. Index into the LAG descriptor table.
1428  * Access: Index
1429  */
1430 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1431
1432 /* reg_slcor_port_index
1433  * Port index in the LAG list. Only valid on Add Port to LAG col.
1434  * Valid range is from 0 to cap_max_lag_members-1
1435  * Access: RW
1436  */
1437 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1438
1439 static inline void mlxsw_reg_slcor_pack(char *payload,
1440                                         u8 local_port, u16 lag_id,
1441                                         enum mlxsw_reg_slcor_col col)
1442 {
1443         MLXSW_REG_ZERO(slcor, payload);
1444         mlxsw_reg_slcor_col_set(payload, col);
1445         mlxsw_reg_slcor_local_port_set(payload, local_port);
1446         mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1447 }
1448
1449 static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1450                                                  u8 local_port, u16 lag_id,
1451                                                  u8 port_index)
1452 {
1453         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1454                              MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1455         mlxsw_reg_slcor_port_index_set(payload, port_index);
1456 }
1457
1458 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1459                                                     u8 local_port, u16 lag_id)
1460 {
1461         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1462                              MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1463 }
1464
1465 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1466                                                    u8 local_port, u16 lag_id)
1467 {
1468         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1469                              MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1470 }
1471
1472 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1473                                                     u8 local_port, u16 lag_id)
1474 {
1475         mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1476                              MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1477 }
1478
1479 /* SPMLR - Switch Port MAC Learning Register
1480  * -----------------------------------------
1481  * Controls the Switch MAC learning policy per port.
1482  */
1483 #define MLXSW_REG_SPMLR_ID 0x2018
1484 #define MLXSW_REG_SPMLR_LEN 0x8
1485
1486 static const struct mlxsw_reg_info mlxsw_reg_spmlr = {
1487         .id = MLXSW_REG_SPMLR_ID,
1488         .len = MLXSW_REG_SPMLR_LEN,
1489 };
1490
1491 /* reg_spmlr_local_port
1492  * Local port number.
1493  * Access: Index
1494  */
1495 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1496
1497 /* reg_spmlr_sub_port
1498  * Virtual port within the physical port.
1499  * Should be set to 0 when virtual ports are not enabled on the port.
1500  * Access: Index
1501  */
1502 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1503
1504 enum mlxsw_reg_spmlr_learn_mode {
1505         MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1506         MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1507         MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1508 };
1509
1510 /* reg_spmlr_learn_mode
1511  * Learning mode on the port.
1512  * 0 - Learning disabled.
1513  * 2 - Learning enabled.
1514  * 3 - Security mode.
1515  *
1516  * In security mode the switch does not learn MACs on the port, but uses the
1517  * SMAC to see if it exists on another ingress port. If so, the packet is
1518  * classified as a bad packet and is discarded unless the software registers
1519  * to receive port security error packets usign HPKT.
1520  */
1521 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1522
1523 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1524                                         enum mlxsw_reg_spmlr_learn_mode mode)
1525 {
1526         MLXSW_REG_ZERO(spmlr, payload);
1527         mlxsw_reg_spmlr_local_port_set(payload, local_port);
1528         mlxsw_reg_spmlr_sub_port_set(payload, 0);
1529         mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1530 }
1531
1532 /* SVFA - Switch VID to FID Allocation Register
1533  * --------------------------------------------
1534  * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1535  * virtualized ports.
1536  */
1537 #define MLXSW_REG_SVFA_ID 0x201C
1538 #define MLXSW_REG_SVFA_LEN 0x10
1539
1540 static const struct mlxsw_reg_info mlxsw_reg_svfa = {
1541         .id = MLXSW_REG_SVFA_ID,
1542         .len = MLXSW_REG_SVFA_LEN,
1543 };
1544
1545 /* reg_svfa_swid
1546  * Switch partition ID.
1547  * Access: Index
1548  */
1549 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1550
1551 /* reg_svfa_local_port
1552  * Local port number.
1553  * Access: Index
1554  *
1555  * Note: Reserved for 802.1Q FIDs.
1556  */
1557 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1558
1559 enum mlxsw_reg_svfa_mt {
1560         MLXSW_REG_SVFA_MT_VID_TO_FID,
1561         MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1562 };
1563
1564 /* reg_svfa_mapping_table
1565  * Mapping table:
1566  * 0 - VID to FID
1567  * 1 - {Port, VID} to FID
1568  * Access: Index
1569  *
1570  * Note: Reserved for SwitchX-2.
1571  */
1572 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1573
1574 /* reg_svfa_v
1575  * Valid.
1576  * Valid if set.
1577  * Access: RW
1578  *
1579  * Note: Reserved for SwitchX-2.
1580  */
1581 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1582
1583 /* reg_svfa_fid
1584  * Filtering ID.
1585  * Access: RW
1586  */
1587 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1588
1589 /* reg_svfa_vid
1590  * VLAN ID.
1591  * Access: Index
1592  */
1593 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1594
1595 /* reg_svfa_counter_set_type
1596  * Counter set type for flow counters.
1597  * Access: RW
1598  *
1599  * Note: Reserved for SwitchX-2.
1600  */
1601 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1602
1603 /* reg_svfa_counter_index
1604  * Counter index for flow counters.
1605  * Access: RW
1606  *
1607  * Note: Reserved for SwitchX-2.
1608  */
1609 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1610
1611 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1612                                        enum mlxsw_reg_svfa_mt mt, bool valid,
1613                                        u16 fid, u16 vid)
1614 {
1615         MLXSW_REG_ZERO(svfa, payload);
1616         local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1617         mlxsw_reg_svfa_swid_set(payload, 0);
1618         mlxsw_reg_svfa_local_port_set(payload, local_port);
1619         mlxsw_reg_svfa_mapping_table_set(payload, mt);
1620         mlxsw_reg_svfa_v_set(payload, valid);
1621         mlxsw_reg_svfa_fid_set(payload, fid);
1622         mlxsw_reg_svfa_vid_set(payload, vid);
1623 }
1624
1625 /* SVPE - Switch Virtual-Port Enabling Register
1626  * --------------------------------------------
1627  * Enables port virtualization.
1628  */
1629 #define MLXSW_REG_SVPE_ID 0x201E
1630 #define MLXSW_REG_SVPE_LEN 0x4
1631
1632 static const struct mlxsw_reg_info mlxsw_reg_svpe = {
1633         .id = MLXSW_REG_SVPE_ID,
1634         .len = MLXSW_REG_SVPE_LEN,
1635 };
1636
1637 /* reg_svpe_local_port
1638  * Local port number
1639  * Access: Index
1640  *
1641  * Note: CPU port is not supported (uses VLAN mode only).
1642  */
1643 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1644
1645 /* reg_svpe_vp_en
1646  * Virtual port enable.
1647  * 0 - Disable, VLAN mode (VID to FID).
1648  * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1649  * Access: RW
1650  */
1651 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1652
1653 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1654                                        bool enable)
1655 {
1656         MLXSW_REG_ZERO(svpe, payload);
1657         mlxsw_reg_svpe_local_port_set(payload, local_port);
1658         mlxsw_reg_svpe_vp_en_set(payload, enable);
1659 }
1660
1661 /* SFMR - Switch FID Management Register
1662  * -------------------------------------
1663  * Creates and configures FIDs.
1664  */
1665 #define MLXSW_REG_SFMR_ID 0x201F
1666 #define MLXSW_REG_SFMR_LEN 0x18
1667
1668 static const struct mlxsw_reg_info mlxsw_reg_sfmr = {
1669         .id = MLXSW_REG_SFMR_ID,
1670         .len = MLXSW_REG_SFMR_LEN,
1671 };
1672
1673 enum mlxsw_reg_sfmr_op {
1674         MLXSW_REG_SFMR_OP_CREATE_FID,
1675         MLXSW_REG_SFMR_OP_DESTROY_FID,
1676 };
1677
1678 /* reg_sfmr_op
1679  * Operation.
1680  * 0 - Create or edit FID.
1681  * 1 - Destroy FID.
1682  * Access: WO
1683  */
1684 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1685
1686 /* reg_sfmr_fid
1687  * Filtering ID.
1688  * Access: Index
1689  */
1690 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1691
1692 /* reg_sfmr_fid_offset
1693  * FID offset.
1694  * Used to point into the flooding table selected by SFGC register if
1695  * the table is of type FID-Offset. Otherwise, this field is reserved.
1696  * Access: RW
1697  */
1698 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1699
1700 /* reg_sfmr_vtfp
1701  * Valid Tunnel Flood Pointer.
1702  * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1703  * Access: RW
1704  *
1705  * Note: Reserved for 802.1Q FIDs.
1706  */
1707 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1708
1709 /* reg_sfmr_nve_tunnel_flood_ptr
1710  * Underlay Flooding and BC Pointer.
1711  * Used as a pointer to the first entry of the group based link lists of
1712  * flooding or BC entries (for NVE tunnels).
1713  * Access: RW
1714  */
1715 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1716
1717 /* reg_sfmr_vv
1718  * VNI Valid.
1719  * If not set, then vni is reserved.
1720  * Access: RW
1721  *
1722  * Note: Reserved for 802.1Q FIDs.
1723  */
1724 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1725
1726 /* reg_sfmr_vni
1727  * Virtual Network Identifier.
1728  * Access: RW
1729  *
1730  * Note: A given VNI can only be assigned to one FID.
1731  */
1732 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1733
1734 static inline void mlxsw_reg_sfmr_pack(char *payload,
1735                                        enum mlxsw_reg_sfmr_op op, u16 fid,
1736                                        u16 fid_offset)
1737 {
1738         MLXSW_REG_ZERO(sfmr, payload);
1739         mlxsw_reg_sfmr_op_set(payload, op);
1740         mlxsw_reg_sfmr_fid_set(payload, fid);
1741         mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1742         mlxsw_reg_sfmr_vtfp_set(payload, false);
1743         mlxsw_reg_sfmr_vv_set(payload, false);
1744 }
1745
1746 /* SPVMLR - Switch Port VLAN MAC Learning Register
1747  * -----------------------------------------------
1748  * Controls the switch MAC learning policy per {Port, VID}.
1749  */
1750 #define MLXSW_REG_SPVMLR_ID 0x2020
1751 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1752 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1753 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 256
1754 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1755                               MLXSW_REG_SPVMLR_REC_LEN * \
1756                               MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1757
1758 static const struct mlxsw_reg_info mlxsw_reg_spvmlr = {
1759         .id = MLXSW_REG_SPVMLR_ID,
1760         .len = MLXSW_REG_SPVMLR_LEN,
1761 };
1762
1763 /* reg_spvmlr_local_port
1764  * Local ingress port.
1765  * Access: Index
1766  *
1767  * Note: CPU port is not supported.
1768  */
1769 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1770
1771 /* reg_spvmlr_num_rec
1772  * Number of records to update.
1773  * Access: OP
1774  */
1775 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1776
1777 /* reg_spvmlr_rec_learn_enable
1778  * 0 - Disable learning for {Port, VID}.
1779  * 1 - Enable learning for {Port, VID}.
1780  * Access: RW
1781  */
1782 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1783                      31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1784
1785 /* reg_spvmlr_rec_vid
1786  * VLAN ID to be added/removed from port or for querying.
1787  * Access: Index
1788  */
1789 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1790                      MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1791
1792 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1793                                          u16 vid_begin, u16 vid_end,
1794                                          bool learn_enable)
1795 {
1796         int num_rec = vid_end - vid_begin + 1;
1797         int i;
1798
1799         WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1800
1801         MLXSW_REG_ZERO(spvmlr, payload);
1802         mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1803         mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1804
1805         for (i = 0; i < num_rec; i++) {
1806                 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1807                 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1808         }
1809 }
1810
1811 /* QTCT - QoS Switch Traffic Class Table
1812  * -------------------------------------
1813  * Configures the mapping between the packet switch priority and the
1814  * traffic class on the transmit port.
1815  */
1816 #define MLXSW_REG_QTCT_ID 0x400A
1817 #define MLXSW_REG_QTCT_LEN 0x08
1818
1819 static const struct mlxsw_reg_info mlxsw_reg_qtct = {
1820         .id = MLXSW_REG_QTCT_ID,
1821         .len = MLXSW_REG_QTCT_LEN,
1822 };
1823
1824 /* reg_qtct_local_port
1825  * Local port number.
1826  * Access: Index
1827  *
1828  * Note: CPU port is not supported.
1829  */
1830 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
1831
1832 /* reg_qtct_sub_port
1833  * Virtual port within the physical port.
1834  * Should be set to 0 when virtual ports are not enabled on the port.
1835  * Access: Index
1836  */
1837 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
1838
1839 /* reg_qtct_switch_prio
1840  * Switch priority.
1841  * Access: Index
1842  */
1843 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
1844
1845 /* reg_qtct_tclass
1846  * Traffic class.
1847  * Default values:
1848  * switch_prio 0 : tclass 1
1849  * switch_prio 1 : tclass 0
1850  * switch_prio i : tclass i, for i > 1
1851  * Access: RW
1852  */
1853 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
1854
1855 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
1856                                        u8 switch_prio, u8 tclass)
1857 {
1858         MLXSW_REG_ZERO(qtct, payload);
1859         mlxsw_reg_qtct_local_port_set(payload, local_port);
1860         mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
1861         mlxsw_reg_qtct_tclass_set(payload, tclass);
1862 }
1863
1864 /* QEEC - QoS ETS Element Configuration Register
1865  * ---------------------------------------------
1866  * Configures the ETS elements.
1867  */
1868 #define MLXSW_REG_QEEC_ID 0x400D
1869 #define MLXSW_REG_QEEC_LEN 0x1C
1870
1871 static const struct mlxsw_reg_info mlxsw_reg_qeec = {
1872         .id = MLXSW_REG_QEEC_ID,
1873         .len = MLXSW_REG_QEEC_LEN,
1874 };
1875
1876 /* reg_qeec_local_port
1877  * Local port number.
1878  * Access: Index
1879  *
1880  * Note: CPU port is supported.
1881  */
1882 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
1883
1884 enum mlxsw_reg_qeec_hr {
1885         MLXSW_REG_QEEC_HIERARCY_PORT,
1886         MLXSW_REG_QEEC_HIERARCY_GROUP,
1887         MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1888         MLXSW_REG_QEEC_HIERARCY_TC,
1889 };
1890
1891 /* reg_qeec_element_hierarchy
1892  * 0 - Port
1893  * 1 - Group
1894  * 2 - Subgroup
1895  * 3 - Traffic Class
1896  * Access: Index
1897  */
1898 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
1899
1900 /* reg_qeec_element_index
1901  * The index of the element in the hierarchy.
1902  * Access: Index
1903  */
1904 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
1905
1906 /* reg_qeec_next_element_index
1907  * The index of the next (lower) element in the hierarchy.
1908  * Access: RW
1909  *
1910  * Note: Reserved for element_hierarchy 0.
1911  */
1912 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
1913
1914 enum {
1915         MLXSW_REG_QEEC_BYTES_MODE,
1916         MLXSW_REG_QEEC_PACKETS_MODE,
1917 };
1918
1919 /* reg_qeec_pb
1920  * Packets or bytes mode.
1921  * 0 - Bytes mode
1922  * 1 - Packets mode
1923  * Access: RW
1924  *
1925  * Note: Used for max shaper configuration. For Spectrum, packets mode
1926  * is supported only for traffic classes of CPU port.
1927  */
1928 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
1929
1930 /* reg_qeec_mase
1931  * Max shaper configuration enable. Enables configuration of the max
1932  * shaper on this ETS element.
1933  * 0 - Disable
1934  * 1 - Enable
1935  * Access: RW
1936  */
1937 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
1938
1939 /* A large max rate will disable the max shaper. */
1940 #define MLXSW_REG_QEEC_MAS_DIS  200000000       /* Kbps */
1941
1942 /* reg_qeec_max_shaper_rate
1943  * Max shaper information rate.
1944  * For CPU port, can only be configured for port hierarchy.
1945  * When in bytes mode, value is specified in units of 1000bps.
1946  * Access: RW
1947  */
1948 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
1949
1950 /* reg_qeec_de
1951  * DWRR configuration enable. Enables configuration of the dwrr and
1952  * dwrr_weight.
1953  * 0 - Disable
1954  * 1 - Enable
1955  * Access: RW
1956  */
1957 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
1958
1959 /* reg_qeec_dwrr
1960  * Transmission selection algorithm to use on the link going down from
1961  * the ETS element.
1962  * 0 - Strict priority
1963  * 1 - DWRR
1964  * Access: RW
1965  */
1966 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
1967
1968 /* reg_qeec_dwrr_weight
1969  * DWRR weight on the link going down from the ETS element. The
1970  * percentage of bandwidth guaranteed to an ETS element within
1971  * its hierarchy. The sum of all weights across all ETS elements
1972  * within one hierarchy should be equal to 100. Reserved when
1973  * transmission selection algorithm is strict priority.
1974  * Access: RW
1975  */
1976 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
1977
1978 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
1979                                        enum mlxsw_reg_qeec_hr hr, u8 index,
1980                                        u8 next_index)
1981 {
1982         MLXSW_REG_ZERO(qeec, payload);
1983         mlxsw_reg_qeec_local_port_set(payload, local_port);
1984         mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
1985         mlxsw_reg_qeec_element_index_set(payload, index);
1986         mlxsw_reg_qeec_next_element_index_set(payload, next_index);
1987 }
1988
1989 /* PMLP - Ports Module to Local Port Register
1990  * ------------------------------------------
1991  * Configures the assignment of modules to local ports.
1992  */
1993 #define MLXSW_REG_PMLP_ID 0x5002
1994 #define MLXSW_REG_PMLP_LEN 0x40
1995
1996 static const struct mlxsw_reg_info mlxsw_reg_pmlp = {
1997         .id = MLXSW_REG_PMLP_ID,
1998         .len = MLXSW_REG_PMLP_LEN,
1999 };
2000
2001 /* reg_pmlp_rxtx
2002  * 0 - Tx value is used for both Tx and Rx.
2003  * 1 - Rx value is taken from a separte field.
2004  * Access: RW
2005  */
2006 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
2007
2008 /* reg_pmlp_local_port
2009  * Local port number.
2010  * Access: Index
2011  */
2012 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
2013
2014 /* reg_pmlp_width
2015  * 0 - Unmap local port.
2016  * 1 - Lane 0 is used.
2017  * 2 - Lanes 0 and 1 are used.
2018  * 4 - Lanes 0, 1, 2 and 3 are used.
2019  * Access: RW
2020  */
2021 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
2022
2023 /* reg_pmlp_module
2024  * Module number.
2025  * Access: RW
2026  */
2027 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
2028
2029 /* reg_pmlp_tx_lane
2030  * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
2031  * Access: RW
2032  */
2033 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
2034
2035 /* reg_pmlp_rx_lane
2036  * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
2037  * equal to Tx lane.
2038  * Access: RW
2039  */
2040 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
2041
2042 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
2043 {
2044         MLXSW_REG_ZERO(pmlp, payload);
2045         mlxsw_reg_pmlp_local_port_set(payload, local_port);
2046 }
2047
2048 /* PMTU - Port MTU Register
2049  * ------------------------
2050  * Configures and reports the port MTU.
2051  */
2052 #define MLXSW_REG_PMTU_ID 0x5003
2053 #define MLXSW_REG_PMTU_LEN 0x10
2054
2055 static const struct mlxsw_reg_info mlxsw_reg_pmtu = {
2056         .id = MLXSW_REG_PMTU_ID,
2057         .len = MLXSW_REG_PMTU_LEN,
2058 };
2059
2060 /* reg_pmtu_local_port
2061  * Local port number.
2062  * Access: Index
2063  */
2064 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
2065
2066 /* reg_pmtu_max_mtu
2067  * Maximum MTU.
2068  * When port type (e.g. Ethernet) is configured, the relevant MTU is
2069  * reported, otherwise the minimum between the max_mtu of the different
2070  * types is reported.
2071  * Access: RO
2072  */
2073 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
2074
2075 /* reg_pmtu_admin_mtu
2076  * MTU value to set port to. Must be smaller or equal to max_mtu.
2077  * Note: If port type is Infiniband, then port must be disabled, when its
2078  * MTU is set.
2079  * Access: RW
2080  */
2081 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
2082
2083 /* reg_pmtu_oper_mtu
2084  * The actual MTU configured on the port. Packets exceeding this size
2085  * will be dropped.
2086  * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
2087  * oper_mtu might be smaller than admin_mtu.
2088  * Access: RO
2089  */
2090 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
2091
2092 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
2093                                        u16 new_mtu)
2094 {
2095         MLXSW_REG_ZERO(pmtu, payload);
2096         mlxsw_reg_pmtu_local_port_set(payload, local_port);
2097         mlxsw_reg_pmtu_max_mtu_set(payload, 0);
2098         mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
2099         mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
2100 }
2101
2102 /* PTYS - Port Type and Speed Register
2103  * -----------------------------------
2104  * Configures and reports the port speed type.
2105  *
2106  * Note: When set while the link is up, the changes will not take effect
2107  * until the port transitions from down to up state.
2108  */
2109 #define MLXSW_REG_PTYS_ID 0x5004
2110 #define MLXSW_REG_PTYS_LEN 0x40
2111
2112 static const struct mlxsw_reg_info mlxsw_reg_ptys = {
2113         .id = MLXSW_REG_PTYS_ID,
2114         .len = MLXSW_REG_PTYS_LEN,
2115 };
2116
2117 /* reg_ptys_local_port
2118  * Local port number.
2119  * Access: Index
2120  */
2121 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
2122
2123 #define MLXSW_REG_PTYS_PROTO_MASK_ETH   BIT(2)
2124
2125 /* reg_ptys_proto_mask
2126  * Protocol mask. Indicates which protocol is used.
2127  * 0 - Infiniband.
2128  * 1 - Fibre Channel.
2129  * 2 - Ethernet.
2130  * Access: Index
2131  */
2132 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
2133
2134 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII                  BIT(0)
2135 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX            BIT(1)
2136 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4            BIT(2)
2137 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4            BIT(3)
2138 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR             BIT(4)
2139 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2            BIT(5)
2140 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4            BIT(6)
2141 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4            BIT(7)
2142 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4             BIT(8)
2143 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR             BIT(12)
2144 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR             BIT(13)
2145 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR          BIT(14)
2146 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4            BIT(15)
2147 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4        BIT(16)
2148 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4            BIT(19)
2149 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4           BIT(20)
2150 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4           BIT(21)
2151 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4           BIT(22)
2152 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4       BIT(23)
2153 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX             BIT(24)
2154 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T              BIT(25)
2155 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T              BIT(26)
2156 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR             BIT(27)
2157 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR             BIT(28)
2158 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR             BIT(29)
2159 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2            BIT(30)
2160 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2            BIT(31)
2161
2162 /* reg_ptys_eth_proto_cap
2163  * Ethernet port supported speeds and protocols.
2164  * Access: RO
2165  */
2166 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
2167
2168 /* reg_ptys_eth_proto_admin
2169  * Speed and protocol to set port to.
2170  * Access: RW
2171  */
2172 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
2173
2174 /* reg_ptys_eth_proto_oper
2175  * The current speed and protocol configured for the port.
2176  * Access: RO
2177  */
2178 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
2179
2180 static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port,
2181                                        u32 proto_admin)
2182 {
2183         MLXSW_REG_ZERO(ptys, payload);
2184         mlxsw_reg_ptys_local_port_set(payload, local_port);
2185         mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
2186         mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
2187 }
2188
2189 static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap,
2190                                          u32 *p_eth_proto_adm,
2191                                          u32 *p_eth_proto_oper)
2192 {
2193         if (p_eth_proto_cap)
2194                 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
2195         if (p_eth_proto_adm)
2196                 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
2197         if (p_eth_proto_oper)
2198                 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
2199 }
2200
2201 /* PPAD - Port Physical Address Register
2202  * -------------------------------------
2203  * The PPAD register configures the per port physical MAC address.
2204  */
2205 #define MLXSW_REG_PPAD_ID 0x5005
2206 #define MLXSW_REG_PPAD_LEN 0x10
2207
2208 static const struct mlxsw_reg_info mlxsw_reg_ppad = {
2209         .id = MLXSW_REG_PPAD_ID,
2210         .len = MLXSW_REG_PPAD_LEN,
2211 };
2212
2213 /* reg_ppad_single_base_mac
2214  * 0: base_mac, local port should be 0 and mac[7:0] is
2215  * reserved. HW will set incremental
2216  * 1: single_mac - mac of the local_port
2217  * Access: RW
2218  */
2219 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
2220
2221 /* reg_ppad_local_port
2222  * port number, if single_base_mac = 0 then local_port is reserved
2223  * Access: RW
2224  */
2225 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
2226
2227 /* reg_ppad_mac
2228  * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
2229  * If single_base_mac = 1 - the per port MAC address
2230  * Access: RW
2231  */
2232 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
2233
2234 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
2235                                        u8 local_port)
2236 {
2237         MLXSW_REG_ZERO(ppad, payload);
2238         mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
2239         mlxsw_reg_ppad_local_port_set(payload, local_port);
2240 }
2241
2242 /* PAOS - Ports Administrative and Operational Status Register
2243  * -----------------------------------------------------------
2244  * Configures and retrieves per port administrative and operational status.
2245  */
2246 #define MLXSW_REG_PAOS_ID 0x5006
2247 #define MLXSW_REG_PAOS_LEN 0x10
2248
2249 static const struct mlxsw_reg_info mlxsw_reg_paos = {
2250         .id = MLXSW_REG_PAOS_ID,
2251         .len = MLXSW_REG_PAOS_LEN,
2252 };
2253
2254 /* reg_paos_swid
2255  * Switch partition ID with which to associate the port.
2256  * Note: while external ports uses unique local port numbers (and thus swid is
2257  * redundant), router ports use the same local port number where swid is the
2258  * only indication for the relevant port.
2259  * Access: Index
2260  */
2261 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
2262
2263 /* reg_paos_local_port
2264  * Local port number.
2265  * Access: Index
2266  */
2267 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
2268
2269 /* reg_paos_admin_status
2270  * Port administrative state (the desired state of the port):
2271  * 1 - Up.
2272  * 2 - Down.
2273  * 3 - Up once. This means that in case of link failure, the port won't go
2274  *     into polling mode, but will wait to be re-enabled by software.
2275  * 4 - Disabled by system. Can only be set by hardware.
2276  * Access: RW
2277  */
2278 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
2279
2280 /* reg_paos_oper_status
2281  * Port operational state (the current state):
2282  * 1 - Up.
2283  * 2 - Down.
2284  * 3 - Down by port failure. This means that the device will not let the
2285  *     port up again until explicitly specified by software.
2286  * Access: RO
2287  */
2288 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
2289
2290 /* reg_paos_ase
2291  * Admin state update enabled.
2292  * Access: WO
2293  */
2294 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
2295
2296 /* reg_paos_ee
2297  * Event update enable. If this bit is set, event generation will be
2298  * updated based on the e field.
2299  * Access: WO
2300  */
2301 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
2302
2303 /* reg_paos_e
2304  * Event generation on operational state change:
2305  * 0 - Do not generate event.
2306  * 1 - Generate Event.
2307  * 2 - Generate Single Event.
2308  * Access: RW
2309  */
2310 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
2311
2312 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
2313                                        enum mlxsw_port_admin_status status)
2314 {
2315         MLXSW_REG_ZERO(paos, payload);
2316         mlxsw_reg_paos_swid_set(payload, 0);
2317         mlxsw_reg_paos_local_port_set(payload, local_port);
2318         mlxsw_reg_paos_admin_status_set(payload, status);
2319         mlxsw_reg_paos_oper_status_set(payload, 0);
2320         mlxsw_reg_paos_ase_set(payload, 1);
2321         mlxsw_reg_paos_ee_set(payload, 1);
2322         mlxsw_reg_paos_e_set(payload, 1);
2323 }
2324
2325 /* PFCC - Ports Flow Control Configuration Register
2326  * ------------------------------------------------
2327  * Configures and retrieves the per port flow control configuration.
2328  */
2329 #define MLXSW_REG_PFCC_ID 0x5007
2330 #define MLXSW_REG_PFCC_LEN 0x20
2331
2332 static const struct mlxsw_reg_info mlxsw_reg_pfcc = {
2333         .id = MLXSW_REG_PFCC_ID,
2334         .len = MLXSW_REG_PFCC_LEN,
2335 };
2336
2337 /* reg_pfcc_local_port
2338  * Local port number.
2339  * Access: Index
2340  */
2341 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
2342
2343 /* reg_pfcc_pnat
2344  * Port number access type. Determines the way local_port is interpreted:
2345  * 0 - Local port number.
2346  * 1 - IB / label port number.
2347  * Access: Index
2348  */
2349 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
2350
2351 /* reg_pfcc_shl_cap
2352  * Send to higher layers capabilities:
2353  * 0 - No capability of sending Pause and PFC frames to higher layers.
2354  * 1 - Device has capability of sending Pause and PFC frames to higher
2355  *     layers.
2356  * Access: RO
2357  */
2358 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
2359
2360 /* reg_pfcc_shl_opr
2361  * Send to higher layers operation:
2362  * 0 - Pause and PFC frames are handled by the port (default).
2363  * 1 - Pause and PFC frames are handled by the port and also sent to
2364  *     higher layers. Only valid if shl_cap = 1.
2365  * Access: RW
2366  */
2367 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
2368
2369 /* reg_pfcc_ppan
2370  * Pause policy auto negotiation.
2371  * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
2372  * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
2373  *     based on the auto-negotiation resolution.
2374  * Access: RW
2375  *
2376  * Note: The auto-negotiation advertisement is set according to pptx and
2377  * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
2378  */
2379 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
2380
2381 /* reg_pfcc_prio_mask_tx
2382  * Bit per priority indicating if Tx flow control policy should be
2383  * updated based on bit pfctx.
2384  * Access: WO
2385  */
2386 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
2387
2388 /* reg_pfcc_prio_mask_rx
2389  * Bit per priority indicating if Rx flow control policy should be
2390  * updated based on bit pfcrx.
2391  * Access: WO
2392  */
2393 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
2394
2395 /* reg_pfcc_pptx
2396  * Admin Pause policy on Tx.
2397  * 0 - Never generate Pause frames (default).
2398  * 1 - Generate Pause frames according to Rx buffer threshold.
2399  * Access: RW
2400  */
2401 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
2402
2403 /* reg_pfcc_aptx
2404  * Active (operational) Pause policy on Tx.
2405  * 0 - Never generate Pause frames.
2406  * 1 - Generate Pause frames according to Rx buffer threshold.
2407  * Access: RO
2408  */
2409 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
2410
2411 /* reg_pfcc_pfctx
2412  * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
2413  * 0 - Never generate priority Pause frames on the specified priority
2414  *     (default).
2415  * 1 - Generate priority Pause frames according to Rx buffer threshold on
2416  *     the specified priority.
2417  * Access: RW
2418  *
2419  * Note: pfctx and pptx must be mutually exclusive.
2420  */
2421 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
2422
2423 /* reg_pfcc_pprx
2424  * Admin Pause policy on Rx.
2425  * 0 - Ignore received Pause frames (default).
2426  * 1 - Respect received Pause frames.
2427  * Access: RW
2428  */
2429 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
2430
2431 /* reg_pfcc_aprx
2432  * Active (operational) Pause policy on Rx.
2433  * 0 - Ignore received Pause frames.
2434  * 1 - Respect received Pause frames.
2435  * Access: RO
2436  */
2437 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
2438
2439 /* reg_pfcc_pfcrx
2440  * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
2441  * 0 - Ignore incoming priority Pause frames on the specified priority
2442  *     (default).
2443  * 1 - Respect incoming priority Pause frames on the specified priority.
2444  * Access: RW
2445  */
2446 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
2447
2448 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF
2449
2450 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
2451 {
2452         mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
2453         mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
2454         mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
2455         mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
2456 }
2457
2458 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
2459 {
2460         MLXSW_REG_ZERO(pfcc, payload);
2461         mlxsw_reg_pfcc_local_port_set(payload, local_port);
2462 }
2463
2464 /* PPCNT - Ports Performance Counters Register
2465  * -------------------------------------------
2466  * The PPCNT register retrieves per port performance counters.
2467  */
2468 #define MLXSW_REG_PPCNT_ID 0x5008
2469 #define MLXSW_REG_PPCNT_LEN 0x100
2470
2471 static const struct mlxsw_reg_info mlxsw_reg_ppcnt = {
2472         .id = MLXSW_REG_PPCNT_ID,
2473         .len = MLXSW_REG_PPCNT_LEN,
2474 };
2475
2476 /* reg_ppcnt_swid
2477  * For HCA: must be always 0.
2478  * Switch partition ID to associate port with.
2479  * Switch partitions are numbered from 0 to 7 inclusively.
2480  * Switch partition 254 indicates stacking ports.
2481  * Switch partition 255 indicates all switch partitions.
2482  * Only valid on Set() operation with local_port=255.
2483  * Access: Index
2484  */
2485 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
2486
2487 /* reg_ppcnt_local_port
2488  * Local port number.
2489  * 255 indicates all ports on the device, and is only allowed
2490  * for Set() operation.
2491  * Access: Index
2492  */
2493 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
2494
2495 /* reg_ppcnt_pnat
2496  * Port number access type:
2497  * 0 - Local port number
2498  * 1 - IB port number
2499  * Access: Index
2500  */
2501 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
2502
2503 enum mlxsw_reg_ppcnt_grp {
2504         MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
2505         MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
2506         MLXSW_REG_PPCNT_TC_CNT = 0x11,
2507 };
2508
2509 /* reg_ppcnt_grp
2510  * Performance counter group.
2511  * Group 63 indicates all groups. Only valid on Set() operation with
2512  * clr bit set.
2513  * 0x0: IEEE 802.3 Counters
2514  * 0x1: RFC 2863 Counters
2515  * 0x2: RFC 2819 Counters
2516  * 0x3: RFC 3635 Counters
2517  * 0x5: Ethernet Extended Counters
2518  * 0x8: Link Level Retransmission Counters
2519  * 0x10: Per Priority Counters
2520  * 0x11: Per Traffic Class Counters
2521  * 0x12: Physical Layer Counters
2522  * Access: Index
2523  */
2524 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
2525
2526 /* reg_ppcnt_clr
2527  * Clear counters. Setting the clr bit will reset the counter value
2528  * for all counters in the counter group. This bit can be set
2529  * for both Set() and Get() operation.
2530  * Access: OP
2531  */
2532 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
2533
2534 /* reg_ppcnt_prio_tc
2535  * Priority for counter set that support per priority, valid values: 0-7.
2536  * Traffic class for counter set that support per traffic class,
2537  * valid values: 0- cap_max_tclass-1 .
2538  * For HCA: cap_max_tclass is always 8.
2539  * Otherwise must be 0.
2540  * Access: Index
2541  */
2542 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
2543
2544 /* Ethernet IEEE 802.3 Counter Group */
2545
2546 /* reg_ppcnt_a_frames_transmitted_ok
2547  * Access: RO
2548  */
2549 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
2550              0x08 + 0x00, 0, 64);
2551
2552 /* reg_ppcnt_a_frames_received_ok
2553  * Access: RO
2554  */
2555 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
2556              0x08 + 0x08, 0, 64);
2557
2558 /* reg_ppcnt_a_frame_check_sequence_errors
2559  * Access: RO
2560  */
2561 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
2562              0x08 + 0x10, 0, 64);
2563
2564 /* reg_ppcnt_a_alignment_errors
2565  * Access: RO
2566  */
2567 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
2568              0x08 + 0x18, 0, 64);
2569
2570 /* reg_ppcnt_a_octets_transmitted_ok
2571  * Access: RO
2572  */
2573 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
2574              0x08 + 0x20, 0, 64);
2575
2576 /* reg_ppcnt_a_octets_received_ok
2577  * Access: RO
2578  */
2579 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
2580              0x08 + 0x28, 0, 64);
2581
2582 /* reg_ppcnt_a_multicast_frames_xmitted_ok
2583  * Access: RO
2584  */
2585 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
2586              0x08 + 0x30, 0, 64);
2587
2588 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
2589  * Access: RO
2590  */
2591 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
2592              0x08 + 0x38, 0, 64);
2593
2594 /* reg_ppcnt_a_multicast_frames_received_ok
2595  * Access: RO
2596  */
2597 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
2598              0x08 + 0x40, 0, 64);
2599
2600 /* reg_ppcnt_a_broadcast_frames_received_ok
2601  * Access: RO
2602  */
2603 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
2604              0x08 + 0x48, 0, 64);
2605
2606 /* reg_ppcnt_a_in_range_length_errors
2607  * Access: RO
2608  */
2609 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
2610              0x08 + 0x50, 0, 64);
2611
2612 /* reg_ppcnt_a_out_of_range_length_field
2613  * Access: RO
2614  */
2615 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
2616              0x08 + 0x58, 0, 64);
2617
2618 /* reg_ppcnt_a_frame_too_long_errors
2619  * Access: RO
2620  */
2621 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
2622              0x08 + 0x60, 0, 64);
2623
2624 /* reg_ppcnt_a_symbol_error_during_carrier
2625  * Access: RO
2626  */
2627 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
2628              0x08 + 0x68, 0, 64);
2629
2630 /* reg_ppcnt_a_mac_control_frames_transmitted
2631  * Access: RO
2632  */
2633 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
2634              0x08 + 0x70, 0, 64);
2635
2636 /* reg_ppcnt_a_mac_control_frames_received
2637  * Access: RO
2638  */
2639 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
2640              0x08 + 0x78, 0, 64);
2641
2642 /* reg_ppcnt_a_unsupported_opcodes_received
2643  * Access: RO
2644  */
2645 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
2646              0x08 + 0x80, 0, 64);
2647
2648 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
2649  * Access: RO
2650  */
2651 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
2652              0x08 + 0x88, 0, 64);
2653
2654 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
2655  * Access: RO
2656  */
2657 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
2658              0x08 + 0x90, 0, 64);
2659
2660 /* Ethernet Per Priority Group Counters */
2661
2662 /* reg_ppcnt_rx_octets
2663  * Access: RO
2664  */
2665 MLXSW_ITEM64(reg, ppcnt, rx_octets, 0x08 + 0x00, 0, 64);
2666
2667 /* reg_ppcnt_rx_frames
2668  * Access: RO
2669  */
2670 MLXSW_ITEM64(reg, ppcnt, rx_frames, 0x08 + 0x20, 0, 64);
2671
2672 /* reg_ppcnt_tx_octets
2673  * Access: RO
2674  */
2675 MLXSW_ITEM64(reg, ppcnt, tx_octets, 0x08 + 0x28, 0, 64);
2676
2677 /* reg_ppcnt_tx_frames
2678  * Access: RO
2679  */
2680 MLXSW_ITEM64(reg, ppcnt, tx_frames, 0x08 + 0x48, 0, 64);
2681
2682 /* reg_ppcnt_rx_pause
2683  * Access: RO
2684  */
2685 MLXSW_ITEM64(reg, ppcnt, rx_pause, 0x08 + 0x50, 0, 64);
2686
2687 /* reg_ppcnt_rx_pause_duration
2688  * Access: RO
2689  */
2690 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 0x08 + 0x58, 0, 64);
2691
2692 /* reg_ppcnt_tx_pause
2693  * Access: RO
2694  */
2695 MLXSW_ITEM64(reg, ppcnt, tx_pause, 0x08 + 0x60, 0, 64);
2696
2697 /* reg_ppcnt_tx_pause_duration
2698  * Access: RO
2699  */
2700 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 0x08 + 0x68, 0, 64);
2701
2702 /* reg_ppcnt_rx_pause_transition
2703  * Access: RO
2704  */
2705 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 0x08 + 0x70, 0, 64);
2706
2707 /* Ethernet Per Traffic Group Counters */
2708
2709 /* reg_ppcnt_tc_transmit_queue
2710  * Contains the transmit queue depth in cells of traffic class
2711  * selected by prio_tc and the port selected by local_port.
2712  * The field cannot be cleared.
2713  * Access: RO
2714  */
2715 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 0x08 + 0x00, 0, 64);
2716
2717 /* reg_ppcnt_tc_no_buffer_discard_uc
2718  * The number of unicast packets dropped due to lack of shared
2719  * buffer resources.
2720  * Access: RO
2721  */
2722 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 0x08 + 0x08, 0, 64);
2723
2724 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
2725                                         enum mlxsw_reg_ppcnt_grp grp,
2726                                         u8 prio_tc)
2727 {
2728         MLXSW_REG_ZERO(ppcnt, payload);
2729         mlxsw_reg_ppcnt_swid_set(payload, 0);
2730         mlxsw_reg_ppcnt_local_port_set(payload, local_port);
2731         mlxsw_reg_ppcnt_pnat_set(payload, 0);
2732         mlxsw_reg_ppcnt_grp_set(payload, grp);
2733         mlxsw_reg_ppcnt_clr_set(payload, 0);
2734         mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
2735 }
2736
2737 /* PPTB - Port Prio To Buffer Register
2738  * -----------------------------------
2739  * Configures the switch priority to buffer table.
2740  */
2741 #define MLXSW_REG_PPTB_ID 0x500B
2742 #define MLXSW_REG_PPTB_LEN 0x10
2743
2744 static const struct mlxsw_reg_info mlxsw_reg_pptb = {
2745         .id = MLXSW_REG_PPTB_ID,
2746         .len = MLXSW_REG_PPTB_LEN,
2747 };
2748
2749 enum {
2750         MLXSW_REG_PPTB_MM_UM,
2751         MLXSW_REG_PPTB_MM_UNICAST,
2752         MLXSW_REG_PPTB_MM_MULTICAST,
2753 };
2754
2755 /* reg_pptb_mm
2756  * Mapping mode.
2757  * 0 - Map both unicast and multicast packets to the same buffer.
2758  * 1 - Map only unicast packets.
2759  * 2 - Map only multicast packets.
2760  * Access: Index
2761  *
2762  * Note: SwitchX-2 only supports the first option.
2763  */
2764 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
2765
2766 /* reg_pptb_local_port
2767  * Local port number.
2768  * Access: Index
2769  */
2770 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
2771
2772 /* reg_pptb_um
2773  * Enables the update of the untagged_buf field.
2774  * Access: RW
2775  */
2776 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
2777
2778 /* reg_pptb_pm
2779  * Enables the update of the prio_to_buff field.
2780  * Bit <i> is a flag for updating the mapping for switch priority <i>.
2781  * Access: RW
2782  */
2783 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
2784
2785 /* reg_pptb_prio_to_buff
2786  * Mapping of switch priority <i> to one of the allocated receive port
2787  * buffers.
2788  * Access: RW
2789  */
2790 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
2791
2792 /* reg_pptb_pm_msb
2793  * Enables the update of the prio_to_buff field.
2794  * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
2795  * Access: RW
2796  */
2797 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
2798
2799 /* reg_pptb_untagged_buff
2800  * Mapping of untagged frames to one of the allocated receive port buffers.
2801  * Access: RW
2802  *
2803  * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
2804  * Spectrum, as it maps untagged packets based on the default switch priority.
2805  */
2806 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
2807
2808 /* reg_pptb_prio_to_buff_msb
2809  * Mapping of switch priority <i+8> to one of the allocated receive port
2810  * buffers.
2811  * Access: RW
2812  */
2813 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
2814
2815 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF
2816
2817 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
2818 {
2819         MLXSW_REG_ZERO(pptb, payload);
2820         mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
2821         mlxsw_reg_pptb_local_port_set(payload, local_port);
2822         mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
2823         mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
2824 }
2825
2826 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
2827                                                     u8 buff)
2828 {
2829         mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
2830         mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
2831 }
2832
2833 /* PBMC - Port Buffer Management Control Register
2834  * ----------------------------------------------
2835  * The PBMC register configures and retrieves the port packet buffer
2836  * allocation for different Prios, and the Pause threshold management.
2837  */
2838 #define MLXSW_REG_PBMC_ID 0x500C
2839 #define MLXSW_REG_PBMC_LEN 0x6C
2840
2841 static const struct mlxsw_reg_info mlxsw_reg_pbmc = {
2842         .id = MLXSW_REG_PBMC_ID,
2843         .len = MLXSW_REG_PBMC_LEN,
2844 };
2845
2846 /* reg_pbmc_local_port
2847  * Local port number.
2848  * Access: Index
2849  */
2850 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
2851
2852 /* reg_pbmc_xoff_timer_value
2853  * When device generates a pause frame, it uses this value as the pause
2854  * timer (time for the peer port to pause in quota-512 bit time).
2855  * Access: RW
2856  */
2857 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
2858
2859 /* reg_pbmc_xoff_refresh
2860  * The time before a new pause frame should be sent to refresh the pause RW
2861  * state. Using the same units as xoff_timer_value above (in quota-512 bit
2862  * time).
2863  * Access: RW
2864  */
2865 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
2866
2867 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
2868
2869 /* reg_pbmc_buf_lossy
2870  * The field indicates if the buffer is lossy.
2871  * 0 - Lossless
2872  * 1 - Lossy
2873  * Access: RW
2874  */
2875 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
2876
2877 /* reg_pbmc_buf_epsb
2878  * Eligible for Port Shared buffer.
2879  * If epsb is set, packets assigned to buffer are allowed to insert the port
2880  * shared buffer.
2881  * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
2882  * Access: RW
2883  */
2884 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
2885
2886 /* reg_pbmc_buf_size
2887  * The part of the packet buffer array is allocated for the specific buffer.
2888  * Units are represented in cells.
2889  * Access: RW
2890  */
2891 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
2892
2893 /* reg_pbmc_buf_xoff_threshold
2894  * Once the amount of data in the buffer goes above this value, device
2895  * starts sending PFC frames for all priorities associated with the
2896  * buffer. Units are represented in cells. Reserved in case of lossy
2897  * buffer.
2898  * Access: RW
2899  *
2900  * Note: In Spectrum, reserved for buffer[9].
2901  */
2902 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
2903                      0x08, 0x04, false);
2904
2905 /* reg_pbmc_buf_xon_threshold
2906  * When the amount of data in the buffer goes below this value, device
2907  * stops sending PFC frames for the priorities associated with the
2908  * buffer. Units are represented in cells. Reserved in case of lossy
2909  * buffer.
2910  * Access: RW
2911  *
2912  * Note: In Spectrum, reserved for buffer[9].
2913  */
2914 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
2915                      0x08, 0x04, false);
2916
2917 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
2918                                        u16 xoff_timer_value, u16 xoff_refresh)
2919 {
2920         MLXSW_REG_ZERO(pbmc, payload);
2921         mlxsw_reg_pbmc_local_port_set(payload, local_port);
2922         mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
2923         mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
2924 }
2925
2926 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
2927                                                     int buf_index,
2928                                                     u16 size)
2929 {
2930         mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
2931         mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
2932         mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
2933 }
2934
2935 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
2936                                                        int buf_index, u16 size,
2937                                                        u16 threshold)
2938 {
2939         mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
2940         mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
2941         mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
2942         mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
2943         mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
2944 }
2945
2946 /* PSPA - Port Switch Partition Allocation
2947  * ---------------------------------------
2948  * Controls the association of a port with a switch partition and enables
2949  * configuring ports as stacking ports.
2950  */
2951 #define MLXSW_REG_PSPA_ID 0x500D
2952 #define MLXSW_REG_PSPA_LEN 0x8
2953
2954 static const struct mlxsw_reg_info mlxsw_reg_pspa = {
2955         .id = MLXSW_REG_PSPA_ID,
2956         .len = MLXSW_REG_PSPA_LEN,
2957 };
2958
2959 /* reg_pspa_swid
2960  * Switch partition ID.
2961  * Access: RW
2962  */
2963 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
2964
2965 /* reg_pspa_local_port
2966  * Local port number.
2967  * Access: Index
2968  */
2969 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
2970
2971 /* reg_pspa_sub_port
2972  * Virtual port within the local port. Set to 0 when virtual ports are
2973  * disabled on the local port.
2974  * Access: Index
2975  */
2976 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
2977
2978 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
2979 {
2980         MLXSW_REG_ZERO(pspa, payload);
2981         mlxsw_reg_pspa_swid_set(payload, swid);
2982         mlxsw_reg_pspa_local_port_set(payload, local_port);
2983         mlxsw_reg_pspa_sub_port_set(payload, 0);
2984 }
2985
2986 /* HTGT - Host Trap Group Table
2987  * ----------------------------
2988  * Configures the properties for forwarding to CPU.
2989  */
2990 #define MLXSW_REG_HTGT_ID 0x7002
2991 #define MLXSW_REG_HTGT_LEN 0x100
2992
2993 static const struct mlxsw_reg_info mlxsw_reg_htgt = {
2994         .id = MLXSW_REG_HTGT_ID,
2995         .len = MLXSW_REG_HTGT_LEN,
2996 };
2997
2998 /* reg_htgt_swid
2999  * Switch partition ID.
3000  * Access: Index
3001  */
3002 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
3003
3004 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0      /* For locally attached CPU */
3005
3006 /* reg_htgt_type
3007  * CPU path type.
3008  * Access: RW
3009  */
3010 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
3011
3012 enum mlxsw_reg_htgt_trap_group {
3013         MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3014         MLXSW_REG_HTGT_TRAP_GROUP_RX,
3015         MLXSW_REG_HTGT_TRAP_GROUP_CTRL,
3016 };
3017
3018 /* reg_htgt_trap_group
3019  * Trap group number. User defined number specifying which trap groups
3020  * should be forwarded to the CPU. The mapping between trap IDs and trap
3021  * groups is configured using HPKT register.
3022  * Access: Index
3023  */
3024 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
3025
3026 enum {
3027         MLXSW_REG_HTGT_POLICER_DISABLE,
3028         MLXSW_REG_HTGT_POLICER_ENABLE,
3029 };
3030
3031 /* reg_htgt_pide
3032  * Enable policer ID specified using 'pid' field.
3033  * Access: RW
3034  */
3035 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
3036
3037 /* reg_htgt_pid
3038  * Policer ID for the trap group.
3039  * Access: RW
3040  */
3041 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
3042
3043 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
3044
3045 /* reg_htgt_mirror_action
3046  * Mirror action to use.
3047  * 0 - Trap to CPU.
3048  * 1 - Trap to CPU and mirror to a mirroring agent.
3049  * 2 - Mirror to a mirroring agent and do not trap to CPU.
3050  * Access: RW
3051  *
3052  * Note: Mirroring to a mirroring agent is only supported in Spectrum.
3053  */
3054 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
3055
3056 /* reg_htgt_mirroring_agent
3057  * Mirroring agent.
3058  * Access: RW
3059  */
3060 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
3061
3062 /* reg_htgt_priority
3063  * Trap group priority.
3064  * In case a packet matches multiple classification rules, the packet will
3065  * only be trapped once, based on the trap ID associated with the group (via
3066  * register HPKT) with the highest priority.
3067  * Supported values are 0-7, with 7 represnting the highest priority.
3068  * Access: RW
3069  *
3070  * Note: In SwitchX-2 this field is ignored and the priority value is replaced
3071  * by the 'trap_group' field.
3072  */
3073 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
3074
3075 /* reg_htgt_local_path_cpu_tclass
3076  * CPU ingress traffic class for the trap group.
3077  * Access: RW
3078  */
3079 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
3080
3081 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD      0x15
3082 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX        0x14
3083 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL      0x13
3084
3085 /* reg_htgt_local_path_rdq
3086  * Receive descriptor queue (RDQ) to use for the trap group.
3087  * Access: RW
3088  */
3089 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
3090
3091 static inline void mlxsw_reg_htgt_pack(char *payload,
3092                                        enum mlxsw_reg_htgt_trap_group group)
3093 {
3094         u8 swid, rdq;
3095
3096         MLXSW_REG_ZERO(htgt, payload);
3097         switch (group) {
3098         case MLXSW_REG_HTGT_TRAP_GROUP_EMAD:
3099                 swid = MLXSW_PORT_SWID_ALL_SWIDS;
3100                 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD;
3101                 break;
3102         case MLXSW_REG_HTGT_TRAP_GROUP_RX:
3103                 swid = 0;
3104                 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX;
3105                 break;
3106         case MLXSW_REG_HTGT_TRAP_GROUP_CTRL:
3107                 swid = 0;
3108                 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL;
3109                 break;
3110         }
3111         mlxsw_reg_htgt_swid_set(payload, swid);
3112         mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
3113         mlxsw_reg_htgt_trap_group_set(payload, group);
3114         mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE);
3115         mlxsw_reg_htgt_pid_set(payload, 0);
3116         mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
3117         mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
3118         mlxsw_reg_htgt_priority_set(payload, 0);
3119         mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7);
3120         mlxsw_reg_htgt_local_path_rdq_set(payload, rdq);
3121 }
3122
3123 /* HPKT - Host Packet Trap
3124  * -----------------------
3125  * Configures trap IDs inside trap groups.
3126  */
3127 #define MLXSW_REG_HPKT_ID 0x7003
3128 #define MLXSW_REG_HPKT_LEN 0x10
3129
3130 static const struct mlxsw_reg_info mlxsw_reg_hpkt = {
3131         .id = MLXSW_REG_HPKT_ID,
3132         .len = MLXSW_REG_HPKT_LEN,
3133 };
3134
3135 enum {
3136         MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
3137         MLXSW_REG_HPKT_ACK_REQUIRED,
3138 };
3139
3140 /* reg_hpkt_ack
3141  * Require acknowledgements from the host for events.
3142  * If set, then the device will wait for the event it sent to be acknowledged
3143  * by the host. This option is only relevant for event trap IDs.
3144  * Access: RW
3145  *
3146  * Note: Currently not supported by firmware.
3147  */
3148 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
3149
3150 enum mlxsw_reg_hpkt_action {
3151         MLXSW_REG_HPKT_ACTION_FORWARD,
3152         MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
3153         MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
3154         MLXSW_REG_HPKT_ACTION_DISCARD,
3155         MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
3156         MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
3157 };
3158
3159 /* reg_hpkt_action
3160  * Action to perform on packet when trapped.
3161  * 0 - No action. Forward to CPU based on switching rules.
3162  * 1 - Trap to CPU (CPU receives sole copy).
3163  * 2 - Mirror to CPU (CPU receives a replica of the packet).
3164  * 3 - Discard.
3165  * 4 - Soft discard (allow other traps to act on the packet).
3166  * 5 - Trap and soft discard (allow other traps to overwrite this trap).
3167  * Access: RW
3168  *
3169  * Note: Must be set to 0 (forward) for event trap IDs, as they are already
3170  * addressed to the CPU.
3171  */
3172 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
3173
3174 /* reg_hpkt_trap_group
3175  * Trap group to associate the trap with.
3176  * Access: RW
3177  */
3178 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
3179
3180 /* reg_hpkt_trap_id
3181  * Trap ID.
3182  * Access: Index
3183  *
3184  * Note: A trap ID can only be associated with a single trap group. The device
3185  * will associate the trap ID with the last trap group configured.
3186  */
3187 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
3188
3189 enum {
3190         MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
3191         MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
3192         MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
3193 };
3194
3195 /* reg_hpkt_ctrl
3196  * Configure dedicated buffer resources for control packets.
3197  * 0 - Keep factory defaults.
3198  * 1 - Do not use control buffer for this trap ID.
3199  * 2 - Use control buffer for this trap ID.
3200  * Access: RW
3201  */
3202 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
3203
3204 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id)
3205 {
3206         enum mlxsw_reg_htgt_trap_group trap_group;
3207
3208         MLXSW_REG_ZERO(hpkt, payload);
3209         mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
3210         mlxsw_reg_hpkt_action_set(payload, action);
3211         switch (trap_id) {
3212         case MLXSW_TRAP_ID_ETHEMAD:
3213         case MLXSW_TRAP_ID_PUDE:
3214                 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_EMAD;
3215                 break;
3216         default:
3217                 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_RX;
3218                 break;
3219         }
3220         mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
3221         mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
3222         mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT);
3223 }
3224
3225 /* RGCR - Router General Configuration Register
3226  * --------------------------------------------
3227  * The register is used for setting up the router configuration.
3228  */
3229 #define MLXSW_REG_RGCR_ID 0x8001
3230 #define MLXSW_REG_RGCR_LEN 0x28
3231
3232 static const struct mlxsw_reg_info mlxsw_reg_rgcr = {
3233         .id = MLXSW_REG_RGCR_ID,
3234         .len = MLXSW_REG_RGCR_LEN,
3235 };
3236
3237 /* reg_rgcr_ipv4_en
3238  * IPv4 router enable.
3239  * Access: RW
3240  */
3241 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
3242
3243 /* reg_rgcr_ipv6_en
3244  * IPv6 router enable.
3245  * Access: RW
3246  */
3247 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
3248
3249 /* reg_rgcr_max_router_interfaces
3250  * Defines the maximum number of active router interfaces for all virtual
3251  * routers.
3252  * Access: RW
3253  */
3254 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
3255
3256 /* reg_rgcr_usp
3257  * Update switch priority and packet color.
3258  * 0 - Preserve the value of Switch Priority and packet color.
3259  * 1 - Recalculate the value of Switch Priority and packet color.
3260  * Access: RW
3261  *
3262  * Note: Not supported by SwitchX and SwitchX-2.
3263  */
3264 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
3265
3266 /* reg_rgcr_pcp_rw
3267  * Indicates how to handle the pcp_rewrite_en value:
3268  * 0 - Preserve the value of pcp_rewrite_en.
3269  * 2 - Disable PCP rewrite.
3270  * 3 - Enable PCP rewrite.
3271  * Access: RW
3272  *
3273  * Note: Not supported by SwitchX and SwitchX-2.
3274  */
3275 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
3276
3277 /* reg_rgcr_activity_dis
3278  * Activity disable:
3279  * 0 - Activity will be set when an entry is hit (default).
3280  * 1 - Activity will not be set when an entry is hit.
3281  *
3282  * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
3283  * (RALUE).
3284  * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
3285  * Entry (RAUHT).
3286  * Bits 2:7 are reserved.
3287  * Access: RW
3288  *
3289  * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
3290  */
3291 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
3292
3293 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en)
3294 {
3295         MLXSW_REG_ZERO(rgcr, payload);
3296         mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
3297 }
3298
3299 /* RITR - Router Interface Table Register
3300  * --------------------------------------
3301  * The register is used to configure the router interface table.
3302  */
3303 #define MLXSW_REG_RITR_ID 0x8002
3304 #define MLXSW_REG_RITR_LEN 0x40
3305
3306 static const struct mlxsw_reg_info mlxsw_reg_ritr = {
3307         .id = MLXSW_REG_RITR_ID,
3308         .len = MLXSW_REG_RITR_LEN,
3309 };
3310
3311 /* reg_ritr_enable
3312  * Enables routing on the router interface.
3313  * Access: RW
3314  */
3315 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
3316
3317 /* reg_ritr_ipv4
3318  * IPv4 routing enable. Enables routing of IPv4 traffic on the router
3319  * interface.
3320  * Access: RW
3321  */
3322 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
3323
3324 /* reg_ritr_ipv6
3325  * IPv6 routing enable. Enables routing of IPv6 traffic on the router
3326  * interface.
3327  * Access: RW
3328  */
3329 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
3330
3331 enum mlxsw_reg_ritr_if_type {
3332         MLXSW_REG_RITR_VLAN_IF,
3333         MLXSW_REG_RITR_FID_IF,
3334         MLXSW_REG_RITR_SP_IF,
3335 };
3336
3337 /* reg_ritr_type
3338  * Router interface type.
3339  * 0 - VLAN interface.
3340  * 1 - FID interface.
3341  * 2 - Sub-port interface.
3342  * Access: RW
3343  */
3344 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
3345
3346 enum {
3347         MLXSW_REG_RITR_RIF_CREATE,
3348         MLXSW_REG_RITR_RIF_DEL,
3349 };
3350
3351 /* reg_ritr_op
3352  * Opcode:
3353  * 0 - Create or edit RIF.
3354  * 1 - Delete RIF.
3355  * Reserved for SwitchX-2. For Spectrum, editing of interface properties
3356  * is not supported. An interface must be deleted and re-created in order
3357  * to update properties.
3358  * Access: WO
3359  */
3360 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
3361
3362 /* reg_ritr_rif
3363  * Router interface index. A pointer to the Router Interface Table.
3364  * Access: Index
3365  */
3366 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
3367
3368 /* reg_ritr_ipv4_fe
3369  * IPv4 Forwarding Enable.
3370  * Enables routing of IPv4 traffic on the router interface. When disabled,
3371  * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
3372  * Not supported in SwitchX-2.
3373  * Access: RW
3374  */
3375 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
3376
3377 /* reg_ritr_ipv6_fe
3378  * IPv6 Forwarding Enable.
3379  * Enables routing of IPv6 traffic on the router interface. When disabled,
3380  * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
3381  * Not supported in SwitchX-2.
3382  * Access: RW
3383  */
3384 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
3385
3386 /* reg_ritr_virtual_router
3387  * Virtual router ID associated with the router interface.
3388  * Access: RW
3389  */
3390 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
3391
3392 /* reg_ritr_mtu
3393  * Router interface MTU.
3394  * Access: RW
3395  */
3396 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
3397
3398 /* reg_ritr_if_swid
3399  * Switch partition ID.
3400  * Access: RW
3401  */
3402 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
3403
3404 /* reg_ritr_if_mac
3405  * Router interface MAC address.
3406  * In Spectrum, all MAC addresses must have the same 38 MSBits.
3407  * Access: RW
3408  */
3409 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
3410
3411 /* VLAN Interface */
3412
3413 /* reg_ritr_vlan_if_vid
3414  * VLAN ID.
3415  * Access: RW
3416  */
3417 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
3418
3419 /* FID Interface */
3420
3421 /* reg_ritr_fid_if_fid
3422  * Filtering ID. Used to connect a bridge to the router. Only FIDs from
3423  * the vFID range are supported.
3424  * Access: RW
3425  */
3426 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
3427
3428 static inline void mlxsw_reg_ritr_fid_set(char *payload,
3429                                           enum mlxsw_reg_ritr_if_type rif_type,
3430                                           u16 fid)
3431 {
3432         if (rif_type == MLXSW_REG_RITR_FID_IF)
3433                 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
3434         else
3435                 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
3436 }
3437
3438 /* Sub-port Interface */
3439
3440 /* reg_ritr_sp_if_lag
3441  * LAG indication. When this bit is set the system_port field holds the
3442  * LAG identifier.
3443  * Access: RW
3444  */
3445 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
3446
3447 /* reg_ritr_sp_system_port
3448  * Port unique indentifier. When lag bit is set, this field holds the
3449  * lag_id in bits 0:9.
3450  * Access: RW
3451  */
3452 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
3453
3454 /* reg_ritr_sp_if_vid
3455  * VLAN ID.
3456  * Access: RW
3457  */
3458 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
3459
3460 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
3461 {
3462         MLXSW_REG_ZERO(ritr, payload);
3463         mlxsw_reg_ritr_rif_set(payload, rif);
3464 }
3465
3466 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
3467                                              u16 system_port, u16 vid)
3468 {
3469         mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
3470         mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
3471         mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
3472 }
3473
3474 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
3475                                        enum mlxsw_reg_ritr_if_type type,
3476                                        u16 rif, u16 mtu, const char *mac)
3477 {
3478         bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
3479
3480         MLXSW_REG_ZERO(ritr, payload);
3481         mlxsw_reg_ritr_enable_set(payload, enable);
3482         mlxsw_reg_ritr_ipv4_set(payload, 1);
3483         mlxsw_reg_ritr_type_set(payload, type);
3484         mlxsw_reg_ritr_op_set(payload, op);
3485         mlxsw_reg_ritr_rif_set(payload, rif);
3486         mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
3487         mlxsw_reg_ritr_mtu_set(payload, mtu);
3488         mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
3489 }
3490
3491 /* RATR - Router Adjacency Table Register
3492  * --------------------------------------
3493  * The RATR register is used to configure the Router Adjacency (next-hop)
3494  * Table.
3495  */
3496 #define MLXSW_REG_RATR_ID 0x8008
3497 #define MLXSW_REG_RATR_LEN 0x2C
3498
3499 static const struct mlxsw_reg_info mlxsw_reg_ratr = {
3500         .id = MLXSW_REG_RATR_ID,
3501         .len = MLXSW_REG_RATR_LEN,
3502 };
3503
3504 enum mlxsw_reg_ratr_op {
3505         /* Read */
3506         MLXSW_REG_RATR_OP_QUERY_READ = 0,
3507         /* Read and clear activity */
3508         MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
3509         /* Write Adjacency entry */
3510         MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
3511         /* Write Adjacency entry only if the activity is cleared.
3512          * The write may not succeed if the activity is set. There is not
3513          * direct feedback if the write has succeeded or not, however
3514          * the get will reveal the actual entry (SW can compare the get
3515          * response to the set command).
3516          */
3517         MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
3518 };
3519
3520 /* reg_ratr_op
3521  * Note that Write operation may also be used for updating
3522  * counter_set_type and counter_index. In this case all other
3523  * fields must not be updated.
3524  * Access: OP
3525  */
3526 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
3527
3528 /* reg_ratr_v
3529  * Valid bit. Indicates if the adjacency entry is valid.
3530  * Note: the device may need some time before reusing an invalidated
3531  * entry. During this time the entry can not be reused. It is
3532  * recommended to use another entry before reusing an invalidated
3533  * entry (e.g. software can put it at the end of the list for
3534  * reusing). Trying to access an invalidated entry not yet cleared
3535  * by the device results with failure indicating "Try Again" status.
3536  * When valid is '0' then egress_router_interface,trap_action,
3537  * adjacency_parameters and counters are reserved
3538  * Access: RW
3539  */
3540 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
3541
3542 /* reg_ratr_a
3543  * Activity. Set for new entries. Set if a packet lookup has hit on
3544  * the specific entry. To clear the a bit, use "clear activity".
3545  * Access: RO
3546  */
3547 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
3548
3549 /* reg_ratr_adjacency_index_low
3550  * Bits 15:0 of index into the adjacency table.
3551  * For SwitchX and SwitchX-2, the adjacency table is linear and
3552  * used for adjacency entries only.
3553  * For Spectrum, the index is to the KVD linear.
3554  * Access: Index
3555  */
3556 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
3557
3558 /* reg_ratr_egress_router_interface
3559  * Range is 0 .. cap_max_router_interfaces - 1
3560  * Access: RW
3561  */
3562 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
3563
3564 enum mlxsw_reg_ratr_trap_action {
3565         MLXSW_REG_RATR_TRAP_ACTION_NOP,
3566         MLXSW_REG_RATR_TRAP_ACTION_TRAP,
3567         MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
3568         MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
3569         MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
3570 };
3571
3572 /* reg_ratr_trap_action
3573  * see mlxsw_reg_ratr_trap_action
3574  * Access: RW
3575  */
3576 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
3577
3578 enum mlxsw_reg_ratr_trap_id {
3579         MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0 = 0,
3580         MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1 = 1,
3581 };
3582
3583 /* reg_ratr_adjacency_index_high
3584  * Bits 23:16 of the adjacency_index.
3585  * Access: Index
3586  */
3587 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
3588
3589 /* reg_ratr_trap_id
3590  * Trap ID to be reported to CPU.
3591  * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
3592  * For trap_action of NOP, MIRROR and DISCARD_ERROR
3593  * Access: RW
3594  */
3595 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
3596
3597 /* reg_ratr_eth_destination_mac
3598  * MAC address of the destination next-hop.
3599  * Access: RW
3600  */
3601 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
3602
3603 static inline void
3604 mlxsw_reg_ratr_pack(char *payload,
3605                     enum mlxsw_reg_ratr_op op, bool valid,
3606                     u32 adjacency_index, u16 egress_rif)
3607 {
3608         MLXSW_REG_ZERO(ratr, payload);
3609         mlxsw_reg_ratr_op_set(payload, op);
3610         mlxsw_reg_ratr_v_set(payload, valid);
3611         mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
3612         mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
3613         mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
3614 }
3615
3616 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
3617                                                  const char *dest_mac)
3618 {
3619         mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
3620 }
3621
3622 /* RALTA - Router Algorithmic LPM Tree Allocation Register
3623  * -------------------------------------------------------
3624  * RALTA is used to allocate the LPM trees of the SHSPM method.
3625  */
3626 #define MLXSW_REG_RALTA_ID 0x8010
3627 #define MLXSW_REG_RALTA_LEN 0x04
3628
3629 static const struct mlxsw_reg_info mlxsw_reg_ralta = {
3630         .id = MLXSW_REG_RALTA_ID,
3631         .len = MLXSW_REG_RALTA_LEN,
3632 };
3633
3634 /* reg_ralta_op
3635  * opcode (valid for Write, must be 0 on Read)
3636  * 0 - allocate a tree
3637  * 1 - deallocate a tree
3638  * Access: OP
3639  */
3640 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
3641
3642 enum mlxsw_reg_ralxx_protocol {
3643         MLXSW_REG_RALXX_PROTOCOL_IPV4,
3644         MLXSW_REG_RALXX_PROTOCOL_IPV6,
3645 };
3646
3647 /* reg_ralta_protocol
3648  * Protocol.
3649  * Deallocation opcode: Reserved.
3650  * Access: RW
3651  */
3652 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
3653
3654 /* reg_ralta_tree_id
3655  * An identifier (numbered from 1..cap_shspm_max_trees-1) representing
3656  * the tree identifier (managed by software).
3657  * Note that tree_id 0 is allocated for a default-route tree.
3658  * Access: Index
3659  */
3660 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
3661
3662 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
3663                                         enum mlxsw_reg_ralxx_protocol protocol,
3664                                         u8 tree_id)
3665 {
3666         MLXSW_REG_ZERO(ralta, payload);
3667         mlxsw_reg_ralta_op_set(payload, !alloc);
3668         mlxsw_reg_ralta_protocol_set(payload, protocol);
3669         mlxsw_reg_ralta_tree_id_set(payload, tree_id);
3670 }
3671
3672 /* RALST - Router Algorithmic LPM Structure Tree Register
3673  * ------------------------------------------------------
3674  * RALST is used to set and query the structure of an LPM tree.
3675  * The structure of the tree must be sorted as a sorted binary tree, while
3676  * each node is a bin that is tagged as the length of the prefixes the lookup
3677  * will refer to. Therefore, bin X refers to a set of entries with prefixes
3678  * of X bits to match with the destination address. The bin 0 indicates
3679  * the default action, when there is no match of any prefix.
3680  */
3681 #define MLXSW_REG_RALST_ID 0x8011
3682 #define MLXSW_REG_RALST_LEN 0x104
3683
3684 static const struct mlxsw_reg_info mlxsw_reg_ralst = {
3685         .id = MLXSW_REG_RALST_ID,
3686         .len = MLXSW_REG_RALST_LEN,
3687 };
3688
3689 /* reg_ralst_root_bin
3690  * The bin number of the root bin.
3691  * 0<root_bin=<(length of IP address)
3692  * For a default-route tree configure 0xff
3693  * Access: RW
3694  */
3695 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
3696
3697 /* reg_ralst_tree_id
3698  * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
3699  * Access: Index
3700  */
3701 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
3702
3703 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
3704 #define MLXSW_REG_RALST_BIN_OFFSET 0x04
3705 #define MLXSW_REG_RALST_BIN_COUNT 128
3706
3707 /* reg_ralst_left_child_bin
3708  * Holding the children of the bin according to the stored tree's structure.
3709  * For trees composed of less than 4 blocks, the bins in excess are reserved.
3710  * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
3711  * Access: RW
3712  */
3713 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
3714
3715 /* reg_ralst_right_child_bin
3716  * Holding the children of the bin according to the stored tree's structure.
3717  * For trees composed of less than 4 blocks, the bins in excess are reserved.
3718  * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
3719  * Access: RW
3720  */
3721 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
3722                      false);
3723
3724 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
3725 {
3726         MLXSW_REG_ZERO(ralst, payload);
3727
3728         /* Initialize all bins to have no left or right child */
3729         memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
3730                MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
3731
3732         mlxsw_reg_ralst_root_bin_set(payload, root_bin);
3733         mlxsw_reg_ralst_tree_id_set(payload, tree_id);
3734 }
3735
3736 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
3737                                             u8 left_child_bin,
3738                                             u8 right_child_bin)
3739 {
3740         int bin_index = bin_number - 1;
3741
3742         mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
3743         mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
3744                                             right_child_bin);
3745 }
3746
3747 /* RALTB - Router Algorithmic LPM Tree Binding Register
3748  * ----------------------------------------------------
3749  * RALTB is used to bind virtual router and protocol to an allocated LPM tree.
3750  */
3751 #define MLXSW_REG_RALTB_ID 0x8012
3752 #define MLXSW_REG_RALTB_LEN 0x04
3753
3754 static const struct mlxsw_reg_info mlxsw_reg_raltb = {
3755         .id = MLXSW_REG_RALTB_ID,
3756         .len = MLXSW_REG_RALTB_LEN,
3757 };
3758
3759 /* reg_raltb_virtual_router
3760  * Virtual Router ID
3761  * Range is 0..cap_max_virtual_routers-1
3762  * Access: Index
3763  */
3764 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
3765
3766 /* reg_raltb_protocol
3767  * Protocol.
3768  * Access: Index
3769  */
3770 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
3771
3772 /* reg_raltb_tree_id
3773  * Tree to be used for the {virtual_router, protocol}
3774  * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
3775  * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0.
3776  * Access: RW
3777  */
3778 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
3779
3780 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
3781                                         enum mlxsw_reg_ralxx_protocol protocol,
3782                                         u8 tree_id)
3783 {
3784         MLXSW_REG_ZERO(raltb, payload);
3785         mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
3786         mlxsw_reg_raltb_protocol_set(payload, protocol);
3787         mlxsw_reg_raltb_tree_id_set(payload, tree_id);
3788 }
3789
3790 /* RALUE - Router Algorithmic LPM Unicast Entry Register
3791  * -----------------------------------------------------
3792  * RALUE is used to configure and query LPM entries that serve
3793  * the Unicast protocols.
3794  */
3795 #define MLXSW_REG_RALUE_ID 0x8013
3796 #define MLXSW_REG_RALUE_LEN 0x38
3797
3798 static const struct mlxsw_reg_info mlxsw_reg_ralue = {
3799         .id = MLXSW_REG_RALUE_ID,
3800         .len = MLXSW_REG_RALUE_LEN,
3801 };
3802
3803 /* reg_ralue_protocol
3804  * Protocol.
3805  * Access: Index
3806  */
3807 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
3808
3809 enum mlxsw_reg_ralue_op {
3810         /* Read operation. If entry doesn't exist, the operation fails. */
3811         MLXSW_REG_RALUE_OP_QUERY_READ = 0,
3812         /* Clear on read operation. Used to read entry and
3813          * clear Activity bit.
3814          */
3815         MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
3816         /* Write operation. Used to write a new entry to the table. All RW
3817          * fields are written for new entry. Activity bit is set
3818          * for new entries.
3819          */
3820         MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
3821         /* Update operation. Used to update an existing route entry and
3822          * only update the RW fields that are detailed in the field
3823          * op_u_mask. If entry doesn't exist, the operation fails.
3824          */
3825         MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
3826         /* Clear activity. The Activity bit (the field a) is cleared
3827          * for the entry.
3828          */
3829         MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
3830         /* Delete operation. Used to delete an existing entry. If entry
3831          * doesn't exist, the operation fails.
3832          */
3833         MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
3834 };
3835
3836 /* reg_ralue_op
3837  * Operation.
3838  * Access: OP
3839  */
3840 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
3841
3842 /* reg_ralue_a
3843  * Activity. Set for new entries. Set if a packet lookup has hit on the
3844  * specific entry, only if the entry is a route. To clear the a bit, use
3845  * "clear activity" op.
3846  * Enabled by activity_dis in RGCR
3847  * Access: RO
3848  */
3849 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
3850
3851 /* reg_ralue_virtual_router
3852  * Virtual Router ID
3853  * Range is 0..cap_max_virtual_routers-1
3854  * Access: Index
3855  */
3856 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
3857
3858 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE    BIT(0)
3859 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN       BIT(1)
3860 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION        BIT(2)
3861
3862 /* reg_ralue_op_u_mask
3863  * opcode update mask.
3864  * On read operation, this field is reserved.
3865  * This field is valid for update opcode, otherwise - reserved.
3866  * This field is a bitmask of the fields that should be updated.
3867  * Access: WO
3868  */
3869 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
3870
3871 /* reg_ralue_prefix_len
3872  * Number of bits in the prefix of the LPM route.
3873  * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes
3874  * two entries in the physical HW table.
3875  * Access: Index
3876  */
3877 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
3878
3879 /* reg_ralue_dip*
3880  * The prefix of the route or of the marker that the object of the LPM
3881  * is compared with. The most significant bits of the dip are the prefix.
3882  * The list significant bits must be '0' if the prefix_len is smaller
3883  * than 128 for IPv6 or smaller than 32 for IPv4.
3884  * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.
3885  * Access: Index
3886  */
3887 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
3888
3889 enum mlxsw_reg_ralue_entry_type {
3890         MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
3891         MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
3892         MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
3893 };
3894
3895 /* reg_ralue_entry_type
3896  * Entry type.
3897  * Note - for Marker entries, the action_type and action fields are reserved.
3898  * Access: RW
3899  */
3900 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
3901
3902 /* reg_ralue_bmp_len
3903  * The best match prefix length in the case that there is no match for
3904  * longer prefixes.
3905  * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
3906  * Note for any update operation with entry_type modification this
3907  * field must be set.
3908  * Access: RW
3909  */
3910 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
3911
3912 enum mlxsw_reg_ralue_action_type {
3913         MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
3914         MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
3915         MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
3916 };
3917
3918 /* reg_ralue_action_type
3919  * Action Type
3920  * Indicates how the IP address is connected.
3921  * It can be connected to a local subnet through local_erif or can be
3922  * on a remote subnet connected through a next-hop router,
3923  * or transmitted to the CPU.
3924  * Reserved when entry_type = MARKER_ENTRY
3925  * Access: RW
3926  */
3927 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
3928
3929 enum mlxsw_reg_ralue_trap_action {
3930         MLXSW_REG_RALUE_TRAP_ACTION_NOP,
3931         MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
3932         MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
3933         MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
3934         MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
3935 };
3936
3937 /* reg_ralue_trap_action
3938  * Trap action.
3939  * For IP2ME action, only NOP and MIRROR are possible.
3940  * Access: RW
3941  */
3942 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
3943
3944 /* reg_ralue_trap_id
3945  * Trap ID to be reported to CPU.
3946  * Trap ID is RTR_INGRESS0 or RTR_INGRESS1.
3947  * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.
3948  * Access: RW
3949  */
3950 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
3951
3952 /* reg_ralue_adjacency_index
3953  * Points to the first entry of the group-based ECMP.
3954  * Only relevant in case of REMOTE action.
3955  * Access: RW
3956  */
3957 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
3958
3959 /* reg_ralue_ecmp_size
3960  * Amount of sequential entries starting
3961  * from the adjacency_index (the number of ECMPs).
3962  * The valid range is 1-64, 512, 1024, 2048 and 4096.
3963  * Reserved when trap_action is TRAP or DISCARD_ERROR.
3964  * Only relevant in case of REMOTE action.
3965  * Access: RW
3966  */
3967 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
3968
3969 /* reg_ralue_local_erif
3970  * Egress Router Interface.
3971  * Only relevant in case of LOCAL action.
3972  * Access: RW
3973  */
3974 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
3975
3976 /* reg_ralue_v
3977  * Valid bit for the tunnel_ptr field.
3978  * If valid = 0 then trap to CPU as IP2ME trap ID.
3979  * If valid = 1 and the packet format allows NVE or IPinIP tunnel
3980  * decapsulation then tunnel decapsulation is done.
3981  * If valid = 1 and packet format does not allow NVE or IPinIP tunnel
3982  * decapsulation then trap as IP2ME trap ID.
3983  * Only relevant in case of IP2ME action.
3984  * Access: RW
3985  */
3986 MLXSW_ITEM32(reg, ralue, v, 0x24, 31, 1);
3987
3988 /* reg_ralue_tunnel_ptr
3989  * Tunnel Pointer for NVE or IPinIP tunnel decapsulation.
3990  * For Spectrum, pointer to KVD Linear.
3991  * Only relevant in case of IP2ME action.
3992  * Access: RW
3993  */
3994 MLXSW_ITEM32(reg, ralue, tunnel_ptr, 0x24, 0, 24);
3995
3996 static inline void mlxsw_reg_ralue_pack(char *payload,
3997                                         enum mlxsw_reg_ralxx_protocol protocol,
3998                                         enum mlxsw_reg_ralue_op op,
3999                                         u16 virtual_router, u8 prefix_len)
4000 {
4001         MLXSW_REG_ZERO(ralue, payload);
4002         mlxsw_reg_ralue_protocol_set(payload, protocol);
4003         mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
4004         mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
4005         mlxsw_reg_ralue_entry_type_set(payload,
4006                                        MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
4007         mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
4008 }
4009
4010 static inline void mlxsw_reg_ralue_pack4(char *payload,
4011                                          enum mlxsw_reg_ralxx_protocol protocol,
4012                                          enum mlxsw_reg_ralue_op op,
4013                                          u16 virtual_router, u8 prefix_len,
4014                                          u32 dip)
4015 {
4016         mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
4017         mlxsw_reg_ralue_dip4_set(payload, dip);
4018 }
4019
4020 static inline void
4021 mlxsw_reg_ralue_act_remote_pack(char *payload,
4022                                 enum mlxsw_reg_ralue_trap_action trap_action,
4023                                 u16 trap_id, u32 adjacency_index, u16 ecmp_size)
4024 {
4025         mlxsw_reg_ralue_action_type_set(payload,
4026                                         MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
4027         mlxsw_reg_ralue_trap_action_set(payload, trap_action);
4028         mlxsw_reg_ralue_trap_id_set(payload, trap_id);
4029         mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
4030         mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
4031 }
4032
4033 static inline void
4034 mlxsw_reg_ralue_act_local_pack(char *payload,
4035                                enum mlxsw_reg_ralue_trap_action trap_action,
4036                                u16 trap_id, u16 local_erif)
4037 {
4038         mlxsw_reg_ralue_action_type_set(payload,
4039                                         MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
4040         mlxsw_reg_ralue_trap_action_set(payload, trap_action);
4041         mlxsw_reg_ralue_trap_id_set(payload, trap_id);
4042         mlxsw_reg_ralue_local_erif_set(payload, local_erif);
4043 }
4044
4045 static inline void
4046 mlxsw_reg_ralue_act_ip2me_pack(char *payload)
4047 {
4048         mlxsw_reg_ralue_action_type_set(payload,
4049                                         MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
4050 }
4051
4052 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register
4053  * ----------------------------------------------------------
4054  * The RAUHT register is used to configure and query the Unicast Host table in
4055  * devices that implement the Algorithmic LPM.
4056  */
4057 #define MLXSW_REG_RAUHT_ID 0x8014
4058 #define MLXSW_REG_RAUHT_LEN 0x74
4059
4060 static const struct mlxsw_reg_info mlxsw_reg_rauht = {
4061         .id = MLXSW_REG_RAUHT_ID,
4062         .len = MLXSW_REG_RAUHT_LEN,
4063 };
4064
4065 enum mlxsw_reg_rauht_type {
4066         MLXSW_REG_RAUHT_TYPE_IPV4,
4067         MLXSW_REG_RAUHT_TYPE_IPV6,
4068 };
4069
4070 /* reg_rauht_type
4071  * Access: Index
4072  */
4073 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
4074
4075 enum mlxsw_reg_rauht_op {
4076         MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
4077         /* Read operation */
4078         MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
4079         /* Clear on read operation. Used to read entry and clear
4080          * activity bit.
4081          */
4082         MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
4083         /* Add. Used to write a new entry to the table. All R/W fields are
4084          * relevant for new entry. Activity bit is set for new entries.
4085          */
4086         MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
4087         /* Update action. Used to update an existing route entry and
4088          * only update the following fields:
4089          * trap_action, trap_id, mac, counter_set_type, counter_index
4090          */
4091         MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
4092         /* Clear activity. A bit is cleared for the entry. */
4093         MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
4094         /* Delete entry */
4095         MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
4096         /* Delete all host entries on a RIF. In this command, dip
4097          * field is reserved.
4098          */
4099 };
4100
4101 /* reg_rauht_op
4102  * Access: OP
4103  */
4104 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
4105
4106 /* reg_rauht_a
4107  * Activity. Set for new entries. Set if a packet lookup has hit on
4108  * the specific entry.
4109  * To clear the a bit, use "clear activity" op.
4110  * Enabled by activity_dis in RGCR
4111  * Access: RO
4112  */
4113 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
4114
4115 /* reg_rauht_rif
4116  * Router Interface
4117  * Access: Index
4118  */
4119 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
4120
4121 /* reg_rauht_dip*
4122  * Destination address.
4123  * Access: Index
4124  */
4125 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
4126
4127 enum mlxsw_reg_rauht_trap_action {
4128         MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
4129         MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
4130         MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
4131         MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
4132         MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
4133 };
4134
4135 /* reg_rauht_trap_action
4136  * Access: RW
4137  */
4138 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
4139
4140 enum mlxsw_reg_rauht_trap_id {
4141         MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
4142         MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
4143 };
4144
4145 /* reg_rauht_trap_id
4146  * Trap ID to be reported to CPU.
4147  * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
4148  * For trap_action of NOP, MIRROR and DISCARD_ERROR,
4149  * trap_id is reserved.
4150  * Access: RW
4151  */
4152 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
4153
4154 /* reg_rauht_counter_set_type
4155  * Counter set type for flow counters
4156  * Access: RW
4157  */
4158 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
4159
4160 /* reg_rauht_counter_index
4161  * Counter index for flow counters
4162  * Access: RW
4163  */
4164 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
4165
4166 /* reg_rauht_mac
4167  * MAC address.
4168  * Access: RW
4169  */
4170 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
4171
4172 static inline void mlxsw_reg_rauht_pack(char *payload,
4173                                         enum mlxsw_reg_rauht_op op, u16 rif,
4174                                         const char *mac)
4175 {
4176         MLXSW_REG_ZERO(rauht, payload);
4177         mlxsw_reg_rauht_op_set(payload, op);
4178         mlxsw_reg_rauht_rif_set(payload, rif);
4179         mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
4180 }
4181
4182 static inline void mlxsw_reg_rauht_pack4(char *payload,
4183                                          enum mlxsw_reg_rauht_op op, u16 rif,
4184                                          const char *mac, u32 dip)
4185 {
4186         mlxsw_reg_rauht_pack(payload, op, rif, mac);
4187         mlxsw_reg_rauht_dip4_set(payload, dip);
4188 }
4189
4190 /* RALEU - Router Algorithmic LPM ECMP Update Register
4191  * ---------------------------------------------------
4192  * The register enables updating the ECMP section in the action for multiple
4193  * LPM Unicast entries in a single operation. The update is executed to
4194  * all entries of a {virtual router, protocol} tuple using the same ECMP group.
4195  */
4196 #define MLXSW_REG_RALEU_ID 0x8015
4197 #define MLXSW_REG_RALEU_LEN 0x28
4198
4199 static const struct mlxsw_reg_info mlxsw_reg_raleu = {
4200         .id = MLXSW_REG_RALEU_ID,
4201         .len = MLXSW_REG_RALEU_LEN,
4202 };
4203
4204 /* reg_raleu_protocol
4205  * Protocol.
4206  * Access: Index
4207  */
4208 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
4209
4210 /* reg_raleu_virtual_router
4211  * Virtual Router ID
4212  * Range is 0..cap_max_virtual_routers-1
4213  * Access: Index
4214  */
4215 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
4216
4217 /* reg_raleu_adjacency_index
4218  * Adjacency Index used for matching on the existing entries.
4219  * Access: Index
4220  */
4221 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
4222
4223 /* reg_raleu_ecmp_size
4224  * ECMP Size used for matching on the existing entries.
4225  * Access: Index
4226  */
4227 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
4228
4229 /* reg_raleu_new_adjacency_index
4230  * New Adjacency Index.
4231  * Access: WO
4232  */
4233 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
4234
4235 /* reg_raleu_new_ecmp_size
4236  * New ECMP Size.
4237  * Access: WO
4238  */
4239 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
4240
4241 static inline void mlxsw_reg_raleu_pack(char *payload,
4242                                         enum mlxsw_reg_ralxx_protocol protocol,
4243                                         u16 virtual_router,
4244                                         u32 adjacency_index, u16 ecmp_size,
4245                                         u32 new_adjacency_index,
4246                                         u16 new_ecmp_size)
4247 {
4248         MLXSW_REG_ZERO(raleu, payload);
4249         mlxsw_reg_raleu_protocol_set(payload, protocol);
4250         mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
4251         mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
4252         mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
4253         mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
4254         mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
4255 }
4256
4257 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register
4258  * ----------------------------------------------------------------
4259  * The RAUHTD register allows dumping entries from the Router Unicast Host
4260  * Table. For a given session an entry is dumped no more than one time. The
4261  * first RAUHTD access after reset is a new session. A session ends when the
4262  * num_rec response is smaller than num_rec request or for IPv4 when the
4263  * num_entries is smaller than 4. The clear activity affect the current session
4264  * or the last session if a new session has not started.
4265  */
4266 #define MLXSW_REG_RAUHTD_ID 0x8018
4267 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20
4268 #define MLXSW_REG_RAUHTD_REC_LEN 0x20
4269 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
4270 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
4271                 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
4272 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
4273
4274 static const struct mlxsw_reg_info mlxsw_reg_rauhtd = {
4275         .id = MLXSW_REG_RAUHTD_ID,
4276         .len = MLXSW_REG_RAUHTD_LEN,
4277 };
4278
4279 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
4280 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
4281
4282 /* reg_rauhtd_filter_fields
4283  * if a bit is '0' then the relevant field is ignored and dump is done
4284  * regardless of the field value
4285  * Bit0 - filter by activity: entry_a
4286  * Bit3 - filter by entry rip: entry_rif
4287  * Access: Index
4288  */
4289 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
4290
4291 enum mlxsw_reg_rauhtd_op {
4292         MLXSW_REG_RAUHTD_OP_DUMP,
4293         MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
4294 };
4295
4296 /* reg_rauhtd_op
4297  * Access: OP
4298  */
4299 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
4300
4301 /* reg_rauhtd_num_rec
4302  * At request: number of records requested
4303  * At response: number of records dumped
4304  * For IPv4, each record has 4 entries at request and up to 4 entries
4305  * at response
4306  * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM
4307  * Access: Index
4308  */
4309 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
4310
4311 /* reg_rauhtd_entry_a
4312  * Dump only if activity has value of entry_a
4313  * Reserved if filter_fields bit0 is '0'
4314  * Access: Index
4315  */
4316 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
4317
4318 enum mlxsw_reg_rauhtd_type {
4319         MLXSW_REG_RAUHTD_TYPE_IPV4,
4320         MLXSW_REG_RAUHTD_TYPE_IPV6,
4321 };
4322
4323 /* reg_rauhtd_type
4324  * Dump only if record type is:
4325  * 0 - IPv4
4326  * 1 - IPv6
4327  * Access: Index
4328  */
4329 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
4330
4331 /* reg_rauhtd_entry_rif
4332  * Dump only if RIF has value of entry_rif
4333  * Reserved if filter_fields bit3 is '0'
4334  * Access: Index
4335  */
4336 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
4337
4338 static inline void mlxsw_reg_rauhtd_pack(char *payload,
4339                                          enum mlxsw_reg_rauhtd_type type)
4340 {
4341         MLXSW_REG_ZERO(rauhtd, payload);
4342         mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
4343         mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
4344         mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
4345         mlxsw_reg_rauhtd_entry_a_set(payload, 1);
4346         mlxsw_reg_rauhtd_type_set(payload, type);
4347 }
4348
4349 /* reg_rauhtd_ipv4_rec_num_entries
4350  * Number of valid entries in this record:
4351  * 0 - 1 valid entry
4352  * 1 - 2 valid entries
4353  * 2 - 3 valid entries
4354  * 3 - 4 valid entries
4355  * Access: RO
4356  */
4357 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
4358                      MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
4359                      MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
4360
4361 /* reg_rauhtd_rec_type
4362  * Record type.
4363  * 0 - IPv4
4364  * 1 - IPv6
4365  * Access: RO
4366  */
4367 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
4368                      MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
4369
4370 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
4371
4372 /* reg_rauhtd_ipv4_ent_a
4373  * Activity. Set for new entries. Set if a packet lookup has hit on the
4374  * specific entry.
4375  * Access: RO
4376  */
4377 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
4378                      MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
4379
4380 /* reg_rauhtd_ipv4_ent_rif
4381  * Router interface.
4382  * Access: RO
4383  */
4384 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
4385                      16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
4386
4387 /* reg_rauhtd_ipv4_ent_dip
4388  * Destination IPv4 address.
4389  * Access: RO
4390  */
4391 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
4392                      32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
4393
4394 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
4395                                                     int ent_index, u16 *p_rif,
4396                                                     u32 *p_dip)
4397 {
4398         *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
4399         *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
4400 }
4401
4402 /* MFCR - Management Fan Control Register
4403  * --------------------------------------
4404  * This register controls the settings of the Fan Speed PWM mechanism.
4405  */
4406 #define MLXSW_REG_MFCR_ID 0x9001
4407 #define MLXSW_REG_MFCR_LEN 0x08
4408
4409 static const struct mlxsw_reg_info mlxsw_reg_mfcr = {
4410         .id = MLXSW_REG_MFCR_ID,
4411         .len = MLXSW_REG_MFCR_LEN,
4412 };
4413
4414 enum mlxsw_reg_mfcr_pwm_frequency {
4415         MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
4416         MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
4417         MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
4418         MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
4419         MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
4420         MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
4421         MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
4422         MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
4423 };
4424
4425 /* reg_mfcr_pwm_frequency
4426  * Controls the frequency of the PWM signal.
4427  * Access: RW
4428  */
4429 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 6);
4430
4431 #define MLXSW_MFCR_TACHOS_MAX 10
4432
4433 /* reg_mfcr_tacho_active
4434  * Indicates which of the tachometer is active (bit per tachometer).
4435  * Access: RO
4436  */
4437 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
4438
4439 #define MLXSW_MFCR_PWMS_MAX 5
4440
4441 /* reg_mfcr_pwm_active
4442  * Indicates which of the PWM control is active (bit per PWM).
4443  * Access: RO
4444  */
4445 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
4446
4447 static inline void
4448 mlxsw_reg_mfcr_pack(char *payload,
4449                     enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
4450 {
4451         MLXSW_REG_ZERO(mfcr, payload);
4452         mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
4453 }
4454
4455 static inline void
4456 mlxsw_reg_mfcr_unpack(char *payload,
4457                       enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
4458                       u16 *p_tacho_active, u8 *p_pwm_active)
4459 {
4460         *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
4461         *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
4462         *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
4463 }
4464
4465 /* MFSC - Management Fan Speed Control Register
4466  * --------------------------------------------
4467  * This register controls the settings of the Fan Speed PWM mechanism.
4468  */
4469 #define MLXSW_REG_MFSC_ID 0x9002
4470 #define MLXSW_REG_MFSC_LEN 0x08
4471
4472 static const struct mlxsw_reg_info mlxsw_reg_mfsc = {
4473         .id = MLXSW_REG_MFSC_ID,
4474         .len = MLXSW_REG_MFSC_LEN,
4475 };
4476
4477 /* reg_mfsc_pwm
4478  * Fan pwm to control / monitor.
4479  * Access: Index
4480  */
4481 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
4482
4483 /* reg_mfsc_pwm_duty_cycle
4484  * Controls the duty cycle of the PWM. Value range from 0..255 to
4485  * represent duty cycle of 0%...100%.
4486  * Access: RW
4487  */
4488 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
4489
4490 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
4491                                        u8 pwm_duty_cycle)
4492 {
4493         MLXSW_REG_ZERO(mfsc, payload);
4494         mlxsw_reg_mfsc_pwm_set(payload, pwm);
4495         mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
4496 }
4497
4498 /* MFSM - Management Fan Speed Measurement
4499  * ---------------------------------------
4500  * This register controls the settings of the Tacho measurements and
4501  * enables reading the Tachometer measurements.
4502  */
4503 #define MLXSW_REG_MFSM_ID 0x9003
4504 #define MLXSW_REG_MFSM_LEN 0x08
4505
4506 static const struct mlxsw_reg_info mlxsw_reg_mfsm = {
4507         .id = MLXSW_REG_MFSM_ID,
4508         .len = MLXSW_REG_MFSM_LEN,
4509 };
4510
4511 /* reg_mfsm_tacho
4512  * Fan tachometer index.
4513  * Access: Index
4514  */
4515 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
4516
4517 /* reg_mfsm_rpm
4518  * Fan speed (round per minute).
4519  * Access: RO
4520  */
4521 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
4522
4523 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
4524 {
4525         MLXSW_REG_ZERO(mfsm, payload);
4526         mlxsw_reg_mfsm_tacho_set(payload, tacho);
4527 }
4528
4529 /* MTCAP - Management Temperature Capabilities
4530  * -------------------------------------------
4531  * This register exposes the capabilities of the device and
4532  * system temperature sensing.
4533  */
4534 #define MLXSW_REG_MTCAP_ID 0x9009
4535 #define MLXSW_REG_MTCAP_LEN 0x08
4536
4537 static const struct mlxsw_reg_info mlxsw_reg_mtcap = {
4538         .id = MLXSW_REG_MTCAP_ID,
4539         .len = MLXSW_REG_MTCAP_LEN,
4540 };
4541
4542 /* reg_mtcap_sensor_count
4543  * Number of sensors supported by the device.
4544  * This includes the QSFP module sensors (if exists in the QSFP module).
4545  * Access: RO
4546  */
4547 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
4548
4549 /* MTMP - Management Temperature
4550  * -----------------------------
4551  * This register controls the settings of the temperature measurements
4552  * and enables reading the temperature measurements. Note that temperature
4553  * is in 0.125 degrees Celsius.
4554  */
4555 #define MLXSW_REG_MTMP_ID 0x900A
4556 #define MLXSW_REG_MTMP_LEN 0x20
4557
4558 static const struct mlxsw_reg_info mlxsw_reg_mtmp = {
4559         .id = MLXSW_REG_MTMP_ID,
4560         .len = MLXSW_REG_MTMP_LEN,
4561 };
4562
4563 /* reg_mtmp_sensor_index
4564  * Sensors index to access.
4565  * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
4566  * (module 0 is mapped to sensor_index 64).
4567  * Access: Index
4568  */
4569 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7);
4570
4571 /* Convert to milli degrees Celsius */
4572 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125)
4573
4574 /* reg_mtmp_temperature
4575  * Temperature reading from the sensor. Reading is in 0.125 Celsius
4576  * degrees units.
4577  * Access: RO
4578  */
4579 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
4580
4581 /* reg_mtmp_mte
4582  * Max Temperature Enable - enables measuring the max temperature on a sensor.
4583  * Access: RW
4584  */
4585 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
4586
4587 /* reg_mtmp_mtr
4588  * Max Temperature Reset - clears the value of the max temperature register.
4589  * Access: WO
4590  */
4591 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
4592
4593 /* reg_mtmp_max_temperature
4594  * The highest measured temperature from the sensor.
4595  * When the bit mte is cleared, the field max_temperature is reserved.
4596  * Access: RO
4597  */
4598 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
4599
4600 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
4601
4602 /* reg_mtmp_sensor_name
4603  * Sensor Name
4604  * Access: RO
4605  */
4606 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
4607
4608 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index,
4609                                        bool max_temp_enable,
4610                                        bool max_temp_reset)
4611 {
4612         MLXSW_REG_ZERO(mtmp, payload);
4613         mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
4614         mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
4615         mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
4616 }
4617
4618 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp,
4619                                          unsigned int *p_max_temp,
4620                                          char *sensor_name)
4621 {
4622         u16 temp;
4623
4624         if (p_temp) {
4625                 temp = mlxsw_reg_mtmp_temperature_get(payload);
4626                 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
4627         }
4628         if (p_max_temp) {
4629                 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
4630                 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
4631         }
4632         if (sensor_name)
4633                 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
4634 }
4635
4636 /* MPAT - Monitoring Port Analyzer Table
4637  * -------------------------------------
4638  * MPAT Register is used to query and configure the Switch PortAnalyzer Table.
4639  * For an enabled analyzer, all fields except e (enable) cannot be modified.
4640  */
4641 #define MLXSW_REG_MPAT_ID 0x901A
4642 #define MLXSW_REG_MPAT_LEN 0x78
4643
4644 static const struct mlxsw_reg_info mlxsw_reg_mpat = {
4645         .id = MLXSW_REG_MPAT_ID,
4646         .len = MLXSW_REG_MPAT_LEN,
4647 };
4648
4649 /* reg_mpat_pa_id
4650  * Port Analyzer ID.
4651  * Access: Index
4652  */
4653 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
4654
4655 /* reg_mpat_system_port
4656  * A unique port identifier for the final destination of the packet.
4657  * Access: RW
4658  */
4659 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
4660
4661 /* reg_mpat_e
4662  * Enable. Indicating the Port Analyzer is enabled.
4663  * Access: RW
4664  */
4665 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
4666
4667 /* reg_mpat_qos
4668  * Quality Of Service Mode.
4669  * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation
4670  * PCP, DEI, DSCP or VL) are configured.
4671  * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the
4672  * same as in the original packet that has triggered the mirroring. For
4673  * SPAN also the pcp,dei are maintained.
4674  * Access: RW
4675  */
4676 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
4677
4678 /* reg_mpat_be
4679  * Best effort mode. Indicates mirroring traffic should not cause packet
4680  * drop or back pressure, but will discard the mirrored packets. Mirrored
4681  * packets will be forwarded on a best effort manner.
4682  * 0: Do not discard mirrored packets
4683  * 1: Discard mirrored packets if causing congestion
4684  * Access: RW
4685  */
4686 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
4687
4688 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
4689                                        u16 system_port, bool e)
4690 {
4691         MLXSW_REG_ZERO(mpat, payload);
4692         mlxsw_reg_mpat_pa_id_set(payload, pa_id);
4693         mlxsw_reg_mpat_system_port_set(payload, system_port);
4694         mlxsw_reg_mpat_e_set(payload, e);
4695         mlxsw_reg_mpat_qos_set(payload, 1);
4696         mlxsw_reg_mpat_be_set(payload, 1);
4697 }
4698
4699 /* MPAR - Monitoring Port Analyzer Register
4700  * ----------------------------------------
4701  * MPAR register is used to query and configure the port analyzer port mirroring
4702  * properties.
4703  */
4704 #define MLXSW_REG_MPAR_ID 0x901B
4705 #define MLXSW_REG_MPAR_LEN 0x08
4706
4707 static const struct mlxsw_reg_info mlxsw_reg_mpar = {
4708         .id = MLXSW_REG_MPAR_ID,
4709         .len = MLXSW_REG_MPAR_LEN,
4710 };
4711
4712 /* reg_mpar_local_port
4713  * The local port to mirror the packets from.
4714  * Access: Index
4715  */
4716 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8);
4717
4718 enum mlxsw_reg_mpar_i_e {
4719         MLXSW_REG_MPAR_TYPE_EGRESS,
4720         MLXSW_REG_MPAR_TYPE_INGRESS,
4721 };
4722
4723 /* reg_mpar_i_e
4724  * Ingress/Egress
4725  * Access: Index
4726  */
4727 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
4728
4729 /* reg_mpar_enable
4730  * Enable mirroring
4731  * By default, port mirroring is disabled for all ports.
4732  * Access: RW
4733  */
4734 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
4735
4736 /* reg_mpar_pa_id
4737  * Port Analyzer ID.
4738  * Access: RW
4739  */
4740 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
4741
4742 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
4743                                        enum mlxsw_reg_mpar_i_e i_e,
4744                                        bool enable, u8 pa_id)
4745 {
4746         MLXSW_REG_ZERO(mpar, payload);
4747         mlxsw_reg_mpar_local_port_set(payload, local_port);
4748         mlxsw_reg_mpar_enable_set(payload, enable);
4749         mlxsw_reg_mpar_i_e_set(payload, i_e);
4750         mlxsw_reg_mpar_pa_id_set(payload, pa_id);
4751 }
4752
4753 /* MLCR - Management LED Control Register
4754  * --------------------------------------
4755  * Controls the system LEDs.
4756  */
4757 #define MLXSW_REG_MLCR_ID 0x902B
4758 #define MLXSW_REG_MLCR_LEN 0x0C
4759
4760 static const struct mlxsw_reg_info mlxsw_reg_mlcr = {
4761         .id = MLXSW_REG_MLCR_ID,
4762         .len = MLXSW_REG_MLCR_LEN,
4763 };
4764
4765 /* reg_mlcr_local_port
4766  * Local port number.
4767  * Access: RW
4768  */
4769 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
4770
4771 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
4772
4773 /* reg_mlcr_beacon_duration
4774  * Duration of the beacon to be active, in seconds.
4775  * 0x0 - Will turn off the beacon.
4776  * 0xFFFF - Will turn on the beacon until explicitly turned off.
4777  * Access: RW
4778  */
4779 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
4780
4781 /* reg_mlcr_beacon_remain
4782  * Remaining duration of the beacon, in seconds.
4783  * 0xFFFF indicates an infinite amount of time.
4784  * Access: RO
4785  */
4786 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
4787
4788 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
4789                                        bool active)
4790 {
4791         MLXSW_REG_ZERO(mlcr, payload);
4792         mlxsw_reg_mlcr_local_port_set(payload, local_port);
4793         mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
4794                                            MLXSW_REG_MLCR_DURATION_MAX : 0);
4795 }
4796
4797 /* SBPR - Shared Buffer Pools Register
4798  * -----------------------------------
4799  * The SBPR configures and retrieves the shared buffer pools and configuration.
4800  */
4801 #define MLXSW_REG_SBPR_ID 0xB001
4802 #define MLXSW_REG_SBPR_LEN 0x14
4803
4804 static const struct mlxsw_reg_info mlxsw_reg_sbpr = {
4805         .id = MLXSW_REG_SBPR_ID,
4806         .len = MLXSW_REG_SBPR_LEN,
4807 };
4808
4809 /* shared direstion enum for SBPR, SBCM, SBPM */
4810 enum mlxsw_reg_sbxx_dir {
4811         MLXSW_REG_SBXX_DIR_INGRESS,
4812         MLXSW_REG_SBXX_DIR_EGRESS,
4813 };
4814
4815 /* reg_sbpr_dir
4816  * Direction.
4817  * Access: Index
4818  */
4819 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
4820
4821 /* reg_sbpr_pool
4822  * Pool index.
4823  * Access: Index
4824  */
4825 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
4826
4827 /* reg_sbpr_size
4828  * Pool size in buffer cells.
4829  * Access: RW
4830  */
4831 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
4832
4833 enum mlxsw_reg_sbpr_mode {
4834         MLXSW_REG_SBPR_MODE_STATIC,
4835         MLXSW_REG_SBPR_MODE_DYNAMIC,
4836 };
4837
4838 /* reg_sbpr_mode
4839  * Pool quota calculation mode.
4840  * Access: RW
4841  */
4842 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
4843
4844 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
4845                                        enum mlxsw_reg_sbxx_dir dir,
4846                                        enum mlxsw_reg_sbpr_mode mode, u32 size)
4847 {
4848         MLXSW_REG_ZERO(sbpr, payload);
4849         mlxsw_reg_sbpr_pool_set(payload, pool);
4850         mlxsw_reg_sbpr_dir_set(payload, dir);
4851         mlxsw_reg_sbpr_mode_set(payload, mode);
4852         mlxsw_reg_sbpr_size_set(payload, size);
4853 }
4854
4855 /* SBCM - Shared Buffer Class Management Register
4856  * ----------------------------------------------
4857  * The SBCM register configures and retrieves the shared buffer allocation
4858  * and configuration according to Port-PG, including the binding to pool
4859  * and definition of the associated quota.
4860  */
4861 #define MLXSW_REG_SBCM_ID 0xB002
4862 #define MLXSW_REG_SBCM_LEN 0x28
4863
4864 static const struct mlxsw_reg_info mlxsw_reg_sbcm = {
4865         .id = MLXSW_REG_SBCM_ID,
4866         .len = MLXSW_REG_SBCM_LEN,
4867 };
4868
4869 /* reg_sbcm_local_port
4870  * Local port number.
4871  * For Ingress: excludes CPU port and Router port
4872  * For Egress: excludes IP Router
4873  * Access: Index
4874  */
4875 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
4876
4877 /* reg_sbcm_pg_buff
4878  * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
4879  * For PG buffer: range is 0..cap_max_pg_buffers - 1
4880  * For traffic class: range is 0..cap_max_tclass - 1
4881  * Note that when traffic class is in MC aware mode then the traffic
4882  * classes which are MC aware cannot be configured.
4883  * Access: Index
4884  */
4885 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
4886
4887 /* reg_sbcm_dir
4888  * Direction.
4889  * Access: Index
4890  */
4891 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
4892
4893 /* reg_sbcm_min_buff
4894  * Minimum buffer size for the limiter, in cells.
4895  * Access: RW
4896  */
4897 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
4898
4899 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */
4900 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
4901 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
4902
4903 /* reg_sbcm_max_buff
4904  * When the pool associated to the port-pg/tclass is configured to
4905  * static, Maximum buffer size for the limiter configured in cells.
4906  * When the pool associated to the port-pg/tclass is configured to
4907  * dynamic, the max_buff holds the "alpha" parameter, supporting
4908  * the following values:
4909  * 0: 0
4910  * i: (1/128)*2^(i-1), for i=1..14
4911  * 0xFF: Infinity
4912  * Access: RW
4913  */
4914 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
4915
4916 /* reg_sbcm_pool
4917  * Association of the port-priority to a pool.
4918  * Access: RW
4919  */
4920 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
4921
4922 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
4923                                        enum mlxsw_reg_sbxx_dir dir,
4924                                        u32 min_buff, u32 max_buff, u8 pool)
4925 {
4926         MLXSW_REG_ZERO(sbcm, payload);
4927         mlxsw_reg_sbcm_local_port_set(payload, local_port);
4928         mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
4929         mlxsw_reg_sbcm_dir_set(payload, dir);
4930         mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
4931         mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
4932         mlxsw_reg_sbcm_pool_set(payload, pool);
4933 }
4934
4935 /* SBPM - Shared Buffer Port Management Register
4936  * ---------------------------------------------
4937  * The SBPM register configures and retrieves the shared buffer allocation
4938  * and configuration according to Port-Pool, including the definition
4939  * of the associated quota.
4940  */
4941 #define MLXSW_REG_SBPM_ID 0xB003
4942 #define MLXSW_REG_SBPM_LEN 0x28
4943
4944 static const struct mlxsw_reg_info mlxsw_reg_sbpm = {
4945         .id = MLXSW_REG_SBPM_ID,
4946         .len = MLXSW_REG_SBPM_LEN,
4947 };
4948
4949 /* reg_sbpm_local_port
4950  * Local port number.
4951  * For Ingress: excludes CPU port and Router port
4952  * For Egress: excludes IP Router
4953  * Access: Index
4954  */
4955 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
4956
4957 /* reg_sbpm_pool
4958  * The pool associated to quota counting on the local_port.
4959  * Access: Index
4960  */
4961 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
4962
4963 /* reg_sbpm_dir
4964  * Direction.
4965  * Access: Index
4966  */
4967 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
4968
4969 /* reg_sbpm_buff_occupancy
4970  * Current buffer occupancy in cells.
4971  * Access: RO
4972  */
4973 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
4974
4975 /* reg_sbpm_clr
4976  * Clear Max Buffer Occupancy
4977  * When this bit is set, max_buff_occupancy field is cleared (and a
4978  * new max value is tracked from the time the clear was performed).
4979  * Access: OP
4980  */
4981 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
4982
4983 /* reg_sbpm_max_buff_occupancy
4984  * Maximum value of buffer occupancy in cells monitored. Cleared by
4985  * writing to the clr field.
4986  * Access: RO
4987  */
4988 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
4989
4990 /* reg_sbpm_min_buff
4991  * Minimum buffer size for the limiter, in cells.
4992  * Access: RW
4993  */
4994 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
4995
4996 /* reg_sbpm_max_buff
4997  * When the pool associated to the port-pg/tclass is configured to
4998  * static, Maximum buffer size for the limiter configured in cells.
4999  * When the pool associated to the port-pg/tclass is configured to
5000  * dynamic, the max_buff holds the "alpha" parameter, supporting
5001  * the following values:
5002  * 0: 0
5003  * i: (1/128)*2^(i-1), for i=1..14
5004  * 0xFF: Infinity
5005  * Access: RW
5006  */
5007 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
5008
5009 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
5010                                        enum mlxsw_reg_sbxx_dir dir, bool clr,
5011                                        u32 min_buff, u32 max_buff)
5012 {
5013         MLXSW_REG_ZERO(sbpm, payload);
5014         mlxsw_reg_sbpm_local_port_set(payload, local_port);
5015         mlxsw_reg_sbpm_pool_set(payload, pool);
5016         mlxsw_reg_sbpm_dir_set(payload, dir);
5017         mlxsw_reg_sbpm_clr_set(payload, clr);
5018         mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
5019         mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
5020 }
5021
5022 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
5023                                          u32 *p_max_buff_occupancy)
5024 {
5025         *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
5026         *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
5027 }
5028
5029 /* SBMM - Shared Buffer Multicast Management Register
5030  * --------------------------------------------------
5031  * The SBMM register configures and retrieves the shared buffer allocation
5032  * and configuration for MC packets according to Switch-Priority, including
5033  * the binding to pool and definition of the associated quota.
5034  */
5035 #define MLXSW_REG_SBMM_ID 0xB004
5036 #define MLXSW_REG_SBMM_LEN 0x28
5037
5038 static const struct mlxsw_reg_info mlxsw_reg_sbmm = {
5039         .id = MLXSW_REG_SBMM_ID,
5040         .len = MLXSW_REG_SBMM_LEN,
5041 };
5042
5043 /* reg_sbmm_prio
5044  * Switch Priority.
5045  * Access: Index
5046  */
5047 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
5048
5049 /* reg_sbmm_min_buff
5050  * Minimum buffer size for the limiter, in cells.
5051  * Access: RW
5052  */
5053 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
5054
5055 /* reg_sbmm_max_buff
5056  * When the pool associated to the port-pg/tclass is configured to
5057  * static, Maximum buffer size for the limiter configured in cells.
5058  * When the pool associated to the port-pg/tclass is configured to
5059  * dynamic, the max_buff holds the "alpha" parameter, supporting
5060  * the following values:
5061  * 0: 0
5062  * i: (1/128)*2^(i-1), for i=1..14
5063  * 0xFF: Infinity
5064  * Access: RW
5065  */
5066 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
5067
5068 /* reg_sbmm_pool
5069  * Association of the port-priority to a pool.
5070  * Access: RW
5071  */
5072 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
5073
5074 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
5075                                        u32 max_buff, u8 pool)
5076 {
5077         MLXSW_REG_ZERO(sbmm, payload);
5078         mlxsw_reg_sbmm_prio_set(payload, prio);
5079         mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
5080         mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
5081         mlxsw_reg_sbmm_pool_set(payload, pool);
5082 }
5083
5084 /* SBSR - Shared Buffer Status Register
5085  * ------------------------------------
5086  * The SBSR register retrieves the shared buffer occupancy according to
5087  * Port-Pool. Note that this register enables reading a large amount of data.
5088  * It is the user's responsibility to limit the amount of data to ensure the
5089  * response can match the maximum transfer unit. In case the response exceeds
5090  * the maximum transport unit, it will be truncated with no special notice.
5091  */
5092 #define MLXSW_REG_SBSR_ID 0xB005
5093 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
5094 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
5095 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120
5096 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN +   \
5097                             MLXSW_REG_SBSR_REC_LEN *    \
5098                             MLXSW_REG_SBSR_REC_MAX_COUNT)
5099
5100 static const struct mlxsw_reg_info mlxsw_reg_sbsr = {
5101         .id = MLXSW_REG_SBSR_ID,
5102         .len = MLXSW_REG_SBSR_LEN,
5103 };
5104
5105 /* reg_sbsr_clr
5106  * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
5107  * field is cleared (and a new max value is tracked from the time the clear
5108  * was performed).
5109  * Access: OP
5110  */
5111 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
5112
5113 /* reg_sbsr_ingress_port_mask
5114  * Bit vector for all ingress network ports.
5115  * Indicates which of the ports (for which the relevant bit is set)
5116  * are affected by the set operation. Configuration of any other port
5117  * does not change.
5118  * Access: Index
5119  */
5120 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
5121
5122 /* reg_sbsr_pg_buff_mask
5123  * Bit vector for all switch priority groups.
5124  * Indicates which of the priorities (for which the relevant bit is set)
5125  * are affected by the set operation. Configuration of any other priority
5126  * does not change.
5127  * Range is 0..cap_max_pg_buffers - 1
5128  * Access: Index
5129  */
5130 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
5131
5132 /* reg_sbsr_egress_port_mask
5133  * Bit vector for all egress network ports.
5134  * Indicates which of the ports (for which the relevant bit is set)
5135  * are affected by the set operation. Configuration of any other port
5136  * does not change.
5137  * Access: Index
5138  */
5139 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
5140
5141 /* reg_sbsr_tclass_mask
5142  * Bit vector for all traffic classes.
5143  * Indicates which of the traffic classes (for which the relevant bit is
5144  * set) are affected by the set operation. Configuration of any other
5145  * traffic class does not change.
5146  * Range is 0..cap_max_tclass - 1
5147  * Access: Index
5148  */
5149 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
5150
5151 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
5152 {
5153         MLXSW_REG_ZERO(sbsr, payload);
5154         mlxsw_reg_sbsr_clr_set(payload, clr);
5155 }
5156
5157 /* reg_sbsr_rec_buff_occupancy
5158  * Current buffer occupancy in cells.
5159  * Access: RO
5160  */
5161 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
5162                      0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
5163
5164 /* reg_sbsr_rec_max_buff_occupancy
5165  * Maximum value of buffer occupancy in cells monitored. Cleared by
5166  * writing to the clr field.
5167  * Access: RO
5168  */
5169 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
5170                      0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
5171
5172 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
5173                                              u32 *p_buff_occupancy,
5174                                              u32 *p_max_buff_occupancy)
5175 {
5176         *p_buff_occupancy =
5177                 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
5178         *p_max_buff_occupancy =
5179                 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
5180 }
5181
5182 /* SBIB - Shared Buffer Internal Buffer Register
5183  * ---------------------------------------------
5184  * The SBIB register configures per port buffers for internal use. The internal
5185  * buffers consume memory on the port buffers (note that the port buffers are
5186  * used also by PBMC).
5187  *
5188  * For Spectrum this is used for egress mirroring.
5189  */
5190 #define MLXSW_REG_SBIB_ID 0xB006
5191 #define MLXSW_REG_SBIB_LEN 0x10
5192
5193 static const struct mlxsw_reg_info mlxsw_reg_sbib = {
5194         .id = MLXSW_REG_SBIB_ID,
5195         .len = MLXSW_REG_SBIB_LEN,
5196 };
5197
5198 /* reg_sbib_local_port
5199  * Local port number
5200  * Not supported for CPU port and router port
5201  * Access: Index
5202  */
5203 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8);
5204
5205 /* reg_sbib_buff_size
5206  * Units represented in cells
5207  * Allowed range is 0 to (cap_max_headroom_size - 1)
5208  * Default is 0
5209  * Access: RW
5210  */
5211 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
5212
5213 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
5214                                        u32 buff_size)
5215 {
5216         MLXSW_REG_ZERO(sbib, payload);
5217         mlxsw_reg_sbib_local_port_set(payload, local_port);
5218         mlxsw_reg_sbib_buff_size_set(payload, buff_size);
5219 }
5220
5221 static inline const char *mlxsw_reg_id_str(u16 reg_id)
5222 {
5223         switch (reg_id) {
5224         case MLXSW_REG_SGCR_ID:
5225                 return "SGCR";
5226         case MLXSW_REG_SPAD_ID:
5227                 return "SPAD";
5228         case MLXSW_REG_SMID_ID:
5229                 return "SMID";
5230         case MLXSW_REG_SSPR_ID:
5231                 return "SSPR";
5232         case MLXSW_REG_SFDAT_ID:
5233                 return "SFDAT";
5234         case MLXSW_REG_SFD_ID:
5235                 return "SFD";
5236         case MLXSW_REG_SFN_ID:
5237                 return "SFN";
5238         case MLXSW_REG_SPMS_ID:
5239                 return "SPMS";
5240         case MLXSW_REG_SPVID_ID:
5241                 return "SPVID";
5242         case MLXSW_REG_SPVM_ID:
5243                 return "SPVM";
5244         case MLXSW_REG_SPAFT_ID:
5245                 return "SPAFT";
5246         case MLXSW_REG_SFGC_ID:
5247                 return "SFGC";
5248         case MLXSW_REG_SFTR_ID:
5249                 return "SFTR";
5250         case MLXSW_REG_SFDF_ID:
5251                 return "SFDF";
5252         case MLXSW_REG_SLDR_ID:
5253                 return "SLDR";
5254         case MLXSW_REG_SLCR_ID:
5255                 return "SLCR";
5256         case MLXSW_REG_SLCOR_ID:
5257                 return "SLCOR";
5258         case MLXSW_REG_SPMLR_ID:
5259                 return "SPMLR";
5260         case MLXSW_REG_SVFA_ID:
5261                 return "SVFA";
5262         case MLXSW_REG_SVPE_ID:
5263                 return "SVPE";
5264         case MLXSW_REG_SFMR_ID:
5265                 return "SFMR";
5266         case MLXSW_REG_SPVMLR_ID:
5267                 return "SPVMLR";
5268         case MLXSW_REG_QTCT_ID:
5269                 return "QTCT";
5270         case MLXSW_REG_QEEC_ID:
5271                 return "QEEC";
5272         case MLXSW_REG_PMLP_ID:
5273                 return "PMLP";
5274         case MLXSW_REG_PMTU_ID:
5275                 return "PMTU";
5276         case MLXSW_REG_PTYS_ID:
5277                 return "PTYS";
5278         case MLXSW_REG_PPAD_ID:
5279                 return "PPAD";
5280         case MLXSW_REG_PAOS_ID:
5281                 return "PAOS";
5282         case MLXSW_REG_PFCC_ID:
5283                 return "PFCC";
5284         case MLXSW_REG_PPCNT_ID:
5285                 return "PPCNT";
5286         case MLXSW_REG_PPTB_ID:
5287                 return "PPTB";
5288         case MLXSW_REG_PBMC_ID:
5289                 return "PBMC";
5290         case MLXSW_REG_PSPA_ID:
5291                 return "PSPA";
5292         case MLXSW_REG_HTGT_ID:
5293                 return "HTGT";
5294         case MLXSW_REG_HPKT_ID:
5295                 return "HPKT";
5296         case MLXSW_REG_RGCR_ID:
5297                 return "RGCR";
5298         case MLXSW_REG_RITR_ID:
5299                 return "RITR";
5300         case MLXSW_REG_RATR_ID:
5301                 return "RATR";
5302         case MLXSW_REG_RALTA_ID:
5303                 return "RALTA";
5304         case MLXSW_REG_RALST_ID:
5305                 return "RALST";
5306         case MLXSW_REG_RALTB_ID:
5307                 return "RALTB";
5308         case MLXSW_REG_RALUE_ID:
5309                 return "RALUE";
5310         case MLXSW_REG_RAUHT_ID:
5311                 return "RAUHT";
5312         case MLXSW_REG_RALEU_ID:
5313                 return "RALEU";
5314         case MLXSW_REG_RAUHTD_ID:
5315                 return "RAUHTD";
5316         case MLXSW_REG_MFCR_ID:
5317                 return "MFCR";
5318         case MLXSW_REG_MFSC_ID:
5319                 return "MFSC";
5320         case MLXSW_REG_MFSM_ID:
5321                 return "MFSM";
5322         case MLXSW_REG_MTCAP_ID:
5323                 return "MTCAP";
5324         case MLXSW_REG_MPAT_ID:
5325                 return "MPAT";
5326         case MLXSW_REG_MPAR_ID:
5327                 return "MPAR";
5328         case MLXSW_REG_MTMP_ID:
5329                 return "MTMP";
5330         case MLXSW_REG_MLCR_ID:
5331                 return "MLCR";
5332         case MLXSW_REG_SBPR_ID:
5333                 return "SBPR";
5334         case MLXSW_REG_SBCM_ID:
5335                 return "SBCM";
5336         case MLXSW_REG_SBPM_ID:
5337                 return "SBPM";
5338         case MLXSW_REG_SBMM_ID:
5339                 return "SBMM";
5340         case MLXSW_REG_SBSR_ID:
5341                 return "SBSR";
5342         case MLXSW_REG_SBIB_ID:
5343                 return "SBIB";
5344         default:
5345                 return "*UNKNOWN*";
5346         }
5347 }
5348
5349 /* PUDE - Port Up / Down Event
5350  * ---------------------------
5351  * Reports the operational state change of a port.
5352  */
5353 #define MLXSW_REG_PUDE_LEN 0x10
5354
5355 /* reg_pude_swid
5356  * Switch partition ID with which to associate the port.
5357  * Access: Index
5358  */
5359 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
5360
5361 /* reg_pude_local_port
5362  * Local port number.
5363  * Access: Index
5364  */
5365 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
5366
5367 /* reg_pude_admin_status
5368  * Port administrative state (the desired state).
5369  * 1 - Up.
5370  * 2 - Down.
5371  * 3 - Up once. This means that in case of link failure, the port won't go
5372  *     into polling mode, but will wait to be re-enabled by software.
5373  * 4 - Disabled by system. Can only be set by hardware.
5374  * Access: RO
5375  */
5376 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
5377
5378 /* reg_pude_oper_status
5379  * Port operatioanl state.
5380  * 1 - Up.
5381  * 2 - Down.
5382  * 3 - Down by port failure. This means that the device will not let the
5383  *     port up again until explicitly specified by software.
5384  * Access: RO
5385  */
5386 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
5387
5388 #endif