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Merge remote-tracking branch 'md/for-next'
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlxsw / reg.h
1 /*
2 * drivers/net/ethernet/mellanox/mlxsw/reg.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2016 Ido Schimmel <idosch@mellanox.com>
5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
6 * Copyright (c) 2015-2016 Jiri Pirko <jiri@mellanox.com>
7 * Copyright (c) 2016 Yotam Gigi <yotamg@mellanox.com>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the names of the copyright holders nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
20 *
21 * Alternatively, this software may be distributed under the terms of the
22 * GNU General Public License ("GPL") version 2 as published by the Free
23 * Software Foundation.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #ifndef _MLXSW_REG_H
39 #define _MLXSW_REG_H
40
41 #include <linux/string.h>
42 #include <linux/bitops.h>
43 #include <linux/if_vlan.h>
44
45 #include "item.h"
46 #include "port.h"
47
48 struct mlxsw_reg_info {
49 u16 id;
50 u16 len; /* In u8 */
51 };
52
53 #define MLXSW_REG(type) (&mlxsw_reg_##type)
54 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
55 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
56
57 /* SGCR - Switch General Configuration Register
58 * --------------------------------------------
59 * This register is used for configuration of the switch capabilities.
60 */
61 #define MLXSW_REG_SGCR_ID 0x2000
62 #define MLXSW_REG_SGCR_LEN 0x10
63
64 static const struct mlxsw_reg_info mlxsw_reg_sgcr = {
65 .id = MLXSW_REG_SGCR_ID,
66 .len = MLXSW_REG_SGCR_LEN,
67 };
68
69 /* reg_sgcr_llb
70 * Link Local Broadcast (Default=0)
71 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
72 * packets and ignore the IGMP snooping entries.
73 * Access: RW
74 */
75 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
76
77 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
78 {
79 MLXSW_REG_ZERO(sgcr, payload);
80 mlxsw_reg_sgcr_llb_set(payload, !!llb);
81 }
82
83 /* SPAD - Switch Physical Address Register
84 * ---------------------------------------
85 * The SPAD register configures the switch physical MAC address.
86 */
87 #define MLXSW_REG_SPAD_ID 0x2002
88 #define MLXSW_REG_SPAD_LEN 0x10
89
90 static const struct mlxsw_reg_info mlxsw_reg_spad = {
91 .id = MLXSW_REG_SPAD_ID,
92 .len = MLXSW_REG_SPAD_LEN,
93 };
94
95 /* reg_spad_base_mac
96 * Base MAC address for the switch partitions.
97 * Per switch partition MAC address is equal to:
98 * base_mac + swid
99 * Access: RW
100 */
101 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
102
103 /* SMID - Switch Multicast ID
104 * --------------------------
105 * The MID record maps from a MID (Multicast ID), which is a unique identifier
106 * of the multicast group within the stacking domain, into a list of local
107 * ports into which the packet is replicated.
108 */
109 #define MLXSW_REG_SMID_ID 0x2007
110 #define MLXSW_REG_SMID_LEN 0x240
111
112 static const struct mlxsw_reg_info mlxsw_reg_smid = {
113 .id = MLXSW_REG_SMID_ID,
114 .len = MLXSW_REG_SMID_LEN,
115 };
116
117 /* reg_smid_swid
118 * Switch partition ID.
119 * Access: Index
120 */
121 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
122
123 /* reg_smid_mid
124 * Multicast identifier - global identifier that represents the multicast group
125 * across all devices.
126 * Access: Index
127 */
128 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
129
130 /* reg_smid_port
131 * Local port memebership (1 bit per port).
132 * Access: RW
133 */
134 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
135
136 /* reg_smid_port_mask
137 * Local port mask (1 bit per port).
138 * Access: W
139 */
140 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
141
142 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
143 u8 port, bool set)
144 {
145 MLXSW_REG_ZERO(smid, payload);
146 mlxsw_reg_smid_swid_set(payload, 0);
147 mlxsw_reg_smid_mid_set(payload, mid);
148 mlxsw_reg_smid_port_set(payload, port, set);
149 mlxsw_reg_smid_port_mask_set(payload, port, 1);
150 }
151
152 /* SSPR - Switch System Port Record Register
153 * -----------------------------------------
154 * Configures the system port to local port mapping.
155 */
156 #define MLXSW_REG_SSPR_ID 0x2008
157 #define MLXSW_REG_SSPR_LEN 0x8
158
159 static const struct mlxsw_reg_info mlxsw_reg_sspr = {
160 .id = MLXSW_REG_SSPR_ID,
161 .len = MLXSW_REG_SSPR_LEN,
162 };
163
164 /* reg_sspr_m
165 * Master - if set, then the record describes the master system port.
166 * This is needed in case a local port is mapped into several system ports
167 * (for multipathing). That number will be reported as the source system
168 * port when packets are forwarded to the CPU. Only one master port is allowed
169 * per local port.
170 *
171 * Note: Must be set for Spectrum.
172 * Access: RW
173 */
174 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
175
176 /* reg_sspr_local_port
177 * Local port number.
178 *
179 * Access: RW
180 */
181 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
182
183 /* reg_sspr_sub_port
184 * Virtual port within the physical port.
185 * Should be set to 0 when virtual ports are not enabled on the port.
186 *
187 * Access: RW
188 */
189 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
190
191 /* reg_sspr_system_port
192 * Unique identifier within the stacking domain that represents all the ports
193 * that are available in the system (external ports).
194 *
195 * Currently, only single-ASIC configurations are supported, so we default to
196 * 1:1 mapping between system ports and local ports.
197 * Access: Index
198 */
199 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
200
201 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
202 {
203 MLXSW_REG_ZERO(sspr, payload);
204 mlxsw_reg_sspr_m_set(payload, 1);
205 mlxsw_reg_sspr_local_port_set(payload, local_port);
206 mlxsw_reg_sspr_sub_port_set(payload, 0);
207 mlxsw_reg_sspr_system_port_set(payload, local_port);
208 }
209
210 /* SFDAT - Switch Filtering Database Aging Time
211 * --------------------------------------------
212 * Controls the Switch aging time. Aging time is able to be set per Switch
213 * Partition.
214 */
215 #define MLXSW_REG_SFDAT_ID 0x2009
216 #define MLXSW_REG_SFDAT_LEN 0x8
217
218 static const struct mlxsw_reg_info mlxsw_reg_sfdat = {
219 .id = MLXSW_REG_SFDAT_ID,
220 .len = MLXSW_REG_SFDAT_LEN,
221 };
222
223 /* reg_sfdat_swid
224 * Switch partition ID.
225 * Access: Index
226 */
227 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
228
229 /* reg_sfdat_age_time
230 * Aging time in seconds
231 * Min - 10 seconds
232 * Max - 1,000,000 seconds
233 * Default is 300 seconds.
234 * Access: RW
235 */
236 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
237
238 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
239 {
240 MLXSW_REG_ZERO(sfdat, payload);
241 mlxsw_reg_sfdat_swid_set(payload, 0);
242 mlxsw_reg_sfdat_age_time_set(payload, age_time);
243 }
244
245 /* SFD - Switch Filtering Database
246 * -------------------------------
247 * The following register defines the access to the filtering database.
248 * The register supports querying, adding, removing and modifying the database.
249 * The access is optimized for bulk updates in which case more than one
250 * FDB record is present in the same command.
251 */
252 #define MLXSW_REG_SFD_ID 0x200A
253 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
254 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
255 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
256 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
257 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
258
259 static const struct mlxsw_reg_info mlxsw_reg_sfd = {
260 .id = MLXSW_REG_SFD_ID,
261 .len = MLXSW_REG_SFD_LEN,
262 };
263
264 /* reg_sfd_swid
265 * Switch partition ID for queries. Reserved on Write.
266 * Access: Index
267 */
268 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
269
270 enum mlxsw_reg_sfd_op {
271 /* Dump entire FDB a (process according to record_locator) */
272 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
273 /* Query records by {MAC, VID/FID} value */
274 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
275 /* Query and clear activity. Query records by {MAC, VID/FID} value */
276 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
277 /* Test. Response indicates if each of the records could be
278 * added to the FDB.
279 */
280 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
281 /* Add/modify. Aged-out records cannot be added. This command removes
282 * the learning notification of the {MAC, VID/FID}. Response includes
283 * the entries that were added to the FDB.
284 */
285 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
286 /* Remove record by {MAC, VID/FID}. This command also removes
287 * the learning notification and aged-out notifications
288 * of the {MAC, VID/FID}. The response provides current (pre-removal)
289 * entries as non-aged-out.
290 */
291 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
292 /* Remove learned notification by {MAC, VID/FID}. The response provides
293 * the removed learning notification.
294 */
295 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
296 };
297
298 /* reg_sfd_op
299 * Operation.
300 * Access: OP
301 */
302 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
303
304 /* reg_sfd_record_locator
305 * Used for querying the FDB. Use record_locator=0 to initiate the
306 * query. When a record is returned, a new record_locator is
307 * returned to be used in the subsequent query.
308 * Reserved for database update.
309 * Access: Index
310 */
311 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
312
313 /* reg_sfd_num_rec
314 * Request: Number of records to read/add/modify/remove
315 * Response: Number of records read/added/replaced/removed
316 * See above description for more details.
317 * Ranges 0..64
318 * Access: RW
319 */
320 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
321
322 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
323 u32 record_locator)
324 {
325 MLXSW_REG_ZERO(sfd, payload);
326 mlxsw_reg_sfd_op_set(payload, op);
327 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
328 }
329
330 /* reg_sfd_rec_swid
331 * Switch partition ID.
332 * Access: Index
333 */
334 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
335 MLXSW_REG_SFD_REC_LEN, 0x00, false);
336
337 enum mlxsw_reg_sfd_rec_type {
338 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
339 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
340 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
341 };
342
343 /* reg_sfd_rec_type
344 * FDB record type.
345 * Access: RW
346 */
347 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
348 MLXSW_REG_SFD_REC_LEN, 0x00, false);
349
350 enum mlxsw_reg_sfd_rec_policy {
351 /* Replacement disabled, aging disabled. */
352 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
353 /* (mlag remote): Replacement enabled, aging disabled,
354 * learning notification enabled on this port.
355 */
356 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
357 /* (ingress device): Replacement enabled, aging enabled. */
358 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
359 };
360
361 /* reg_sfd_rec_policy
362 * Policy.
363 * Access: RW
364 */
365 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
366 MLXSW_REG_SFD_REC_LEN, 0x00, false);
367
368 /* reg_sfd_rec_a
369 * Activity. Set for new static entries. Set for static entries if a frame SMAC
370 * lookup hits on the entry.
371 * To clear the a bit, use "query and clear activity" op.
372 * Access: RO
373 */
374 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
375 MLXSW_REG_SFD_REC_LEN, 0x00, false);
376
377 /* reg_sfd_rec_mac
378 * MAC address.
379 * Access: Index
380 */
381 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
382 MLXSW_REG_SFD_REC_LEN, 0x02);
383
384 enum mlxsw_reg_sfd_rec_action {
385 /* forward */
386 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
387 /* forward and trap, trap_id is FDB_TRAP */
388 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
389 /* trap and do not forward, trap_id is FDB_TRAP */
390 MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
391 /* forward to IP router */
392 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
393 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
394 };
395
396 /* reg_sfd_rec_action
397 * Action to apply on the packet.
398 * Note: Dynamic entries can only be configured with NOP action.
399 * Access: RW
400 */
401 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
402 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
403
404 /* reg_sfd_uc_sub_port
405 * VEPA channel on local port.
406 * Valid only if local port is a non-stacking port. Must be 0 if multichannel
407 * VEPA is not enabled.
408 * Access: RW
409 */
410 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
411 MLXSW_REG_SFD_REC_LEN, 0x08, false);
412
413 /* reg_sfd_uc_fid_vid
414 * Filtering ID or VLAN ID
415 * For SwitchX and SwitchX-2:
416 * - Dynamic entries (policy 2,3) use FID
417 * - Static entries (policy 0) use VID
418 * - When independent learning is configured, VID=FID
419 * For Spectrum: use FID for both Dynamic and Static entries.
420 * VID should not be used.
421 * Access: Index
422 */
423 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
424 MLXSW_REG_SFD_REC_LEN, 0x08, false);
425
426 /* reg_sfd_uc_system_port
427 * Unique port identifier for the final destination of the packet.
428 * Access: RW
429 */
430 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
431 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
432
433 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
434 enum mlxsw_reg_sfd_rec_type rec_type,
435 const char *mac,
436 enum mlxsw_reg_sfd_rec_action action)
437 {
438 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
439
440 if (rec_index >= num_rec)
441 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
442 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
443 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
444 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
445 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
446 }
447
448 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
449 enum mlxsw_reg_sfd_rec_policy policy,
450 const char *mac, u16 fid_vid,
451 enum mlxsw_reg_sfd_rec_action action,
452 u8 local_port)
453 {
454 mlxsw_reg_sfd_rec_pack(payload, rec_index,
455 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
456 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
457 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
458 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
459 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
460 }
461
462 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
463 char *mac, u16 *p_fid_vid,
464 u8 *p_local_port)
465 {
466 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
467 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
468 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
469 }
470
471 /* reg_sfd_uc_lag_sub_port
472 * LAG sub port.
473 * Must be 0 if multichannel VEPA is not enabled.
474 * Access: RW
475 */
476 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
477 MLXSW_REG_SFD_REC_LEN, 0x08, false);
478
479 /* reg_sfd_uc_lag_fid_vid
480 * Filtering ID or VLAN ID
481 * For SwitchX and SwitchX-2:
482 * - Dynamic entries (policy 2,3) use FID
483 * - Static entries (policy 0) use VID
484 * - When independent learning is configured, VID=FID
485 * For Spectrum: use FID for both Dynamic and Static entries.
486 * VID should not be used.
487 * Access: Index
488 */
489 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
490 MLXSW_REG_SFD_REC_LEN, 0x08, false);
491
492 /* reg_sfd_uc_lag_lag_vid
493 * Indicates VID in case of vFIDs. Reserved for FIDs.
494 * Access: RW
495 */
496 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
497 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
498
499 /* reg_sfd_uc_lag_lag_id
500 * LAG Identifier - pointer into the LAG descriptor table.
501 * Access: RW
502 */
503 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
504 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
505
506 static inline void
507 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
508 enum mlxsw_reg_sfd_rec_policy policy,
509 const char *mac, u16 fid_vid,
510 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
511 u16 lag_id)
512 {
513 mlxsw_reg_sfd_rec_pack(payload, rec_index,
514 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
515 mac, action);
516 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
517 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
518 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
519 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
520 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
521 }
522
523 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
524 char *mac, u16 *p_vid,
525 u16 *p_lag_id)
526 {
527 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
528 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
529 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
530 }
531
532 /* reg_sfd_mc_pgi
533 *
534 * Multicast port group index - index into the port group table.
535 * Value 0x1FFF indicates the pgi should point to the MID entry.
536 * For Spectrum this value must be set to 0x1FFF
537 * Access: RW
538 */
539 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
540 MLXSW_REG_SFD_REC_LEN, 0x08, false);
541
542 /* reg_sfd_mc_fid_vid
543 *
544 * Filtering ID or VLAN ID
545 * Access: Index
546 */
547 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
548 MLXSW_REG_SFD_REC_LEN, 0x08, false);
549
550 /* reg_sfd_mc_mid
551 *
552 * Multicast identifier - global identifier that represents the multicast
553 * group across all devices.
554 * Access: RW
555 */
556 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
557 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
558
559 static inline void
560 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
561 const char *mac, u16 fid_vid,
562 enum mlxsw_reg_sfd_rec_action action, u16 mid)
563 {
564 mlxsw_reg_sfd_rec_pack(payload, rec_index,
565 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
566 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
567 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
568 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
569 }
570
571 /* SFN - Switch FDB Notification Register
572 * -------------------------------------------
573 * The switch provides notifications on newly learned FDB entries and
574 * aged out entries. The notifications can be polled by software.
575 */
576 #define MLXSW_REG_SFN_ID 0x200B
577 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
578 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
579 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
580 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
581 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
582
583 static const struct mlxsw_reg_info mlxsw_reg_sfn = {
584 .id = MLXSW_REG_SFN_ID,
585 .len = MLXSW_REG_SFN_LEN,
586 };
587
588 /* reg_sfn_swid
589 * Switch partition ID.
590 * Access: Index
591 */
592 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
593
594 /* reg_sfn_end
595 * Forces the current session to end.
596 * Access: OP
597 */
598 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
599
600 /* reg_sfn_num_rec
601 * Request: Number of learned notifications and aged-out notification
602 * records requested.
603 * Response: Number of notification records returned (must be smaller
604 * than or equal to the value requested)
605 * Ranges 0..64
606 * Access: OP
607 */
608 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
609
610 static inline void mlxsw_reg_sfn_pack(char *payload)
611 {
612 MLXSW_REG_ZERO(sfn, payload);
613 mlxsw_reg_sfn_swid_set(payload, 0);
614 mlxsw_reg_sfn_end_set(payload, 1);
615 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
616 }
617
618 /* reg_sfn_rec_swid
619 * Switch partition ID.
620 * Access: RO
621 */
622 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
623 MLXSW_REG_SFN_REC_LEN, 0x00, false);
624
625 enum mlxsw_reg_sfn_rec_type {
626 /* MAC addresses learned on a regular port. */
627 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
628 /* MAC addresses learned on a LAG port. */
629 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
630 /* Aged-out MAC address on a regular port. */
631 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
632 /* Aged-out MAC address on a LAG port. */
633 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
634 };
635
636 /* reg_sfn_rec_type
637 * Notification record type.
638 * Access: RO
639 */
640 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
641 MLXSW_REG_SFN_REC_LEN, 0x00, false);
642
643 /* reg_sfn_rec_mac
644 * MAC address.
645 * Access: RO
646 */
647 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
648 MLXSW_REG_SFN_REC_LEN, 0x02);
649
650 /* reg_sfn_mac_sub_port
651 * VEPA channel on the local port.
652 * 0 if multichannel VEPA is not enabled.
653 * Access: RO
654 */
655 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
656 MLXSW_REG_SFN_REC_LEN, 0x08, false);
657
658 /* reg_sfn_mac_fid
659 * Filtering identifier.
660 * Access: RO
661 */
662 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
663 MLXSW_REG_SFN_REC_LEN, 0x08, false);
664
665 /* reg_sfn_mac_system_port
666 * Unique port identifier for the final destination of the packet.
667 * Access: RO
668 */
669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
670 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
671
672 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
673 char *mac, u16 *p_vid,
674 u8 *p_local_port)
675 {
676 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
677 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
678 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
679 }
680
681 /* reg_sfn_mac_lag_lag_id
682 * LAG ID (pointer into the LAG descriptor table).
683 * Access: RO
684 */
685 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
686 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
687
688 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
689 char *mac, u16 *p_vid,
690 u16 *p_lag_id)
691 {
692 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
693 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
694 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
695 }
696
697 /* SPMS - Switch Port MSTP/RSTP State Register
698 * -------------------------------------------
699 * Configures the spanning tree state of a physical port.
700 */
701 #define MLXSW_REG_SPMS_ID 0x200D
702 #define MLXSW_REG_SPMS_LEN 0x404
703
704 static const struct mlxsw_reg_info mlxsw_reg_spms = {
705 .id = MLXSW_REG_SPMS_ID,
706 .len = MLXSW_REG_SPMS_LEN,
707 };
708
709 /* reg_spms_local_port
710 * Local port number.
711 * Access: Index
712 */
713 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
714
715 enum mlxsw_reg_spms_state {
716 MLXSW_REG_SPMS_STATE_NO_CHANGE,
717 MLXSW_REG_SPMS_STATE_DISCARDING,
718 MLXSW_REG_SPMS_STATE_LEARNING,
719 MLXSW_REG_SPMS_STATE_FORWARDING,
720 };
721
722 /* reg_spms_state
723 * Spanning tree state of each VLAN ID (VID) of the local port.
724 * 0 - Do not change spanning tree state (used only when writing).
725 * 1 - Discarding. No learning or forwarding to/from this port (default).
726 * 2 - Learning. Port is learning, but not forwarding.
727 * 3 - Forwarding. Port is learning and forwarding.
728 * Access: RW
729 */
730 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
731
732 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
733 {
734 MLXSW_REG_ZERO(spms, payload);
735 mlxsw_reg_spms_local_port_set(payload, local_port);
736 }
737
738 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
739 enum mlxsw_reg_spms_state state)
740 {
741 mlxsw_reg_spms_state_set(payload, vid, state);
742 }
743
744 /* SPVID - Switch Port VID
745 * -----------------------
746 * The switch port VID configures the default VID for a port.
747 */
748 #define MLXSW_REG_SPVID_ID 0x200E
749 #define MLXSW_REG_SPVID_LEN 0x08
750
751 static const struct mlxsw_reg_info mlxsw_reg_spvid = {
752 .id = MLXSW_REG_SPVID_ID,
753 .len = MLXSW_REG_SPVID_LEN,
754 };
755
756 /* reg_spvid_local_port
757 * Local port number.
758 * Access: Index
759 */
760 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
761
762 /* reg_spvid_sub_port
763 * Virtual port within the physical port.
764 * Should be set to 0 when virtual ports are not enabled on the port.
765 * Access: Index
766 */
767 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
768
769 /* reg_spvid_pvid
770 * Port default VID
771 * Access: RW
772 */
773 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
774
775 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
776 {
777 MLXSW_REG_ZERO(spvid, payload);
778 mlxsw_reg_spvid_local_port_set(payload, local_port);
779 mlxsw_reg_spvid_pvid_set(payload, pvid);
780 }
781
782 /* SPVM - Switch Port VLAN Membership
783 * ----------------------------------
784 * The Switch Port VLAN Membership register configures the VLAN membership
785 * of a port in a VLAN denoted by VID. VLAN membership is managed per
786 * virtual port. The register can be used to add and remove VID(s) from a port.
787 */
788 #define MLXSW_REG_SPVM_ID 0x200F
789 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
790 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
791 #define MLXSW_REG_SPVM_REC_MAX_COUNT 256
792 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
793 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
794
795 static const struct mlxsw_reg_info mlxsw_reg_spvm = {
796 .id = MLXSW_REG_SPVM_ID,
797 .len = MLXSW_REG_SPVM_LEN,
798 };
799
800 /* reg_spvm_pt
801 * Priority tagged. If this bit is set, packets forwarded to the port with
802 * untagged VLAN membership (u bit is set) will be tagged with priority tag
803 * (VID=0)
804 * Access: RW
805 */
806 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
807
808 /* reg_spvm_pte
809 * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
810 * the pt bit will NOT be updated. To update the pt bit, pte must be set.
811 * Access: WO
812 */
813 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
814
815 /* reg_spvm_local_port
816 * Local port number.
817 * Access: Index
818 */
819 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
820
821 /* reg_spvm_sub_port
822 * Virtual port within the physical port.
823 * Should be set to 0 when virtual ports are not enabled on the port.
824 * Access: Index
825 */
826 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
827
828 /* reg_spvm_num_rec
829 * Number of records to update. Each record contains: i, e, u, vid.
830 * Access: OP
831 */
832 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
833
834 /* reg_spvm_rec_i
835 * Ingress membership in VLAN ID.
836 * Access: Index
837 */
838 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
839 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
840 MLXSW_REG_SPVM_REC_LEN, 0, false);
841
842 /* reg_spvm_rec_e
843 * Egress membership in VLAN ID.
844 * Access: Index
845 */
846 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
847 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
848 MLXSW_REG_SPVM_REC_LEN, 0, false);
849
850 /* reg_spvm_rec_u
851 * Untagged - port is an untagged member - egress transmission uses untagged
852 * frames on VID<n>
853 * Access: Index
854 */
855 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
856 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
857 MLXSW_REG_SPVM_REC_LEN, 0, false);
858
859 /* reg_spvm_rec_vid
860 * Egress membership in VLAN ID.
861 * Access: Index
862 */
863 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
864 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
865 MLXSW_REG_SPVM_REC_LEN, 0, false);
866
867 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
868 u16 vid_begin, u16 vid_end,
869 bool is_member, bool untagged)
870 {
871 int size = vid_end - vid_begin + 1;
872 int i;
873
874 MLXSW_REG_ZERO(spvm, payload);
875 mlxsw_reg_spvm_local_port_set(payload, local_port);
876 mlxsw_reg_spvm_num_rec_set(payload, size);
877
878 for (i = 0; i < size; i++) {
879 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
880 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
881 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
882 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
883 }
884 }
885
886 /* SPAFT - Switch Port Acceptable Frame Types
887 * ------------------------------------------
888 * The Switch Port Acceptable Frame Types register configures the frame
889 * admittance of the port.
890 */
891 #define MLXSW_REG_SPAFT_ID 0x2010
892 #define MLXSW_REG_SPAFT_LEN 0x08
893
894 static const struct mlxsw_reg_info mlxsw_reg_spaft = {
895 .id = MLXSW_REG_SPAFT_ID,
896 .len = MLXSW_REG_SPAFT_LEN,
897 };
898
899 /* reg_spaft_local_port
900 * Local port number.
901 * Access: Index
902 *
903 * Note: CPU port is not supported (all tag types are allowed).
904 */
905 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
906
907 /* reg_spaft_sub_port
908 * Virtual port within the physical port.
909 * Should be set to 0 when virtual ports are not enabled on the port.
910 * Access: RW
911 */
912 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
913
914 /* reg_spaft_allow_untagged
915 * When set, untagged frames on the ingress are allowed (default).
916 * Access: RW
917 */
918 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
919
920 /* reg_spaft_allow_prio_tagged
921 * When set, priority tagged frames on the ingress are allowed (default).
922 * Access: RW
923 */
924 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
925
926 /* reg_spaft_allow_tagged
927 * When set, tagged frames on the ingress are allowed (default).
928 * Access: RW
929 */
930 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
931
932 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
933 bool allow_untagged)
934 {
935 MLXSW_REG_ZERO(spaft, payload);
936 mlxsw_reg_spaft_local_port_set(payload, local_port);
937 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
938 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true);
939 mlxsw_reg_spaft_allow_tagged_set(payload, true);
940 }
941
942 /* SFGC - Switch Flooding Group Configuration
943 * ------------------------------------------
944 * The following register controls the association of flooding tables and MIDs
945 * to packet types used for flooding.
946 */
947 #define MLXSW_REG_SFGC_ID 0x2011
948 #define MLXSW_REG_SFGC_LEN 0x10
949
950 static const struct mlxsw_reg_info mlxsw_reg_sfgc = {
951 .id = MLXSW_REG_SFGC_ID,
952 .len = MLXSW_REG_SFGC_LEN,
953 };
954
955 enum mlxsw_reg_sfgc_type {
956 MLXSW_REG_SFGC_TYPE_BROADCAST,
957 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
958 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
959 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
960 MLXSW_REG_SFGC_TYPE_RESERVED,
961 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
962 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
963 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
964 MLXSW_REG_SFGC_TYPE_MAX,
965 };
966
967 /* reg_sfgc_type
968 * The traffic type to reach the flooding table.
969 * Access: Index
970 */
971 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
972
973 enum mlxsw_reg_sfgc_bridge_type {
974 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
975 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
976 };
977
978 /* reg_sfgc_bridge_type
979 * Access: Index
980 *
981 * Note: SwitchX-2 only supports 802.1Q mode.
982 */
983 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
984
985 enum mlxsw_flood_table_type {
986 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
987 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
988 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
989 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3,
990 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
991 };
992
993 /* reg_sfgc_table_type
994 * See mlxsw_flood_table_type
995 * Access: RW
996 *
997 * Note: FID offset and FID types are not supported in SwitchX-2.
998 */
999 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
1000
1001 /* reg_sfgc_flood_table
1002 * Flooding table index to associate with the specific type on the specific
1003 * switch partition.
1004 * Access: RW
1005 */
1006 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1007
1008 /* reg_sfgc_mid
1009 * The multicast ID for the swid. Not supported for Spectrum
1010 * Access: RW
1011 */
1012 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1013
1014 /* reg_sfgc_counter_set_type
1015 * Counter Set Type for flow counters.
1016 * Access: RW
1017 */
1018 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1019
1020 /* reg_sfgc_counter_index
1021 * Counter Index for flow counters.
1022 * Access: RW
1023 */
1024 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1025
1026 static inline void
1027 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1028 enum mlxsw_reg_sfgc_bridge_type bridge_type,
1029 enum mlxsw_flood_table_type table_type,
1030 unsigned int flood_table)
1031 {
1032 MLXSW_REG_ZERO(sfgc, payload);
1033 mlxsw_reg_sfgc_type_set(payload, type);
1034 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1035 mlxsw_reg_sfgc_table_type_set(payload, table_type);
1036 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1037 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1038 }
1039
1040 /* SFTR - Switch Flooding Table Register
1041 * -------------------------------------
1042 * The switch flooding table is used for flooding packet replication. The table
1043 * defines a bit mask of ports for packet replication.
1044 */
1045 #define MLXSW_REG_SFTR_ID 0x2012
1046 #define MLXSW_REG_SFTR_LEN 0x420
1047
1048 static const struct mlxsw_reg_info mlxsw_reg_sftr = {
1049 .id = MLXSW_REG_SFTR_ID,
1050 .len = MLXSW_REG_SFTR_LEN,
1051 };
1052
1053 /* reg_sftr_swid
1054 * Switch partition ID with which to associate the port.
1055 * Access: Index
1056 */
1057 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1058
1059 /* reg_sftr_flood_table
1060 * Flooding table index to associate with the specific type on the specific
1061 * switch partition.
1062 * Access: Index
1063 */
1064 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1065
1066 /* reg_sftr_index
1067 * Index. Used as an index into the Flooding Table in case the table is
1068 * configured to use VID / FID or FID Offset.
1069 * Access: Index
1070 */
1071 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1072
1073 /* reg_sftr_table_type
1074 * See mlxsw_flood_table_type
1075 * Access: RW
1076 */
1077 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1078
1079 /* reg_sftr_range
1080 * Range of entries to update
1081 * Access: Index
1082 */
1083 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1084
1085 /* reg_sftr_port
1086 * Local port membership (1 bit per port).
1087 * Access: RW
1088 */
1089 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1090
1091 /* reg_sftr_cpu_port_mask
1092 * CPU port mask (1 bit per port).
1093 * Access: W
1094 */
1095 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1096
1097 static inline void mlxsw_reg_sftr_pack(char *payload,
1098 unsigned int flood_table,
1099 unsigned int index,
1100 enum mlxsw_flood_table_type table_type,
1101 unsigned int range, u8 port, bool set)
1102 {
1103 MLXSW_REG_ZERO(sftr, payload);
1104 mlxsw_reg_sftr_swid_set(payload, 0);
1105 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1106 mlxsw_reg_sftr_index_set(payload, index);
1107 mlxsw_reg_sftr_table_type_set(payload, table_type);
1108 mlxsw_reg_sftr_range_set(payload, range);
1109 mlxsw_reg_sftr_port_set(payload, port, set);
1110 mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1111 }
1112
1113 /* SFDF - Switch Filtering DB Flush
1114 * --------------------------------
1115 * The switch filtering DB flush register is used to flush the FDB.
1116 * Note that FDB notifications are flushed as well.
1117 */
1118 #define MLXSW_REG_SFDF_ID 0x2013
1119 #define MLXSW_REG_SFDF_LEN 0x14
1120
1121 static const struct mlxsw_reg_info mlxsw_reg_sfdf = {
1122 .id = MLXSW_REG_SFDF_ID,
1123 .len = MLXSW_REG_SFDF_LEN,
1124 };
1125
1126 /* reg_sfdf_swid
1127 * Switch partition ID.
1128 * Access: Index
1129 */
1130 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1131
1132 enum mlxsw_reg_sfdf_flush_type {
1133 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1134 MLXSW_REG_SFDF_FLUSH_PER_FID,
1135 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1136 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1137 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1138 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1139 };
1140
1141 /* reg_sfdf_flush_type
1142 * Flush type.
1143 * 0 - All SWID dynamic entries are flushed.
1144 * 1 - All FID dynamic entries are flushed.
1145 * 2 - All dynamic entries pointing to port are flushed.
1146 * 3 - All FID dynamic entries pointing to port are flushed.
1147 * 4 - All dynamic entries pointing to LAG are flushed.
1148 * 5 - All FID dynamic entries pointing to LAG are flushed.
1149 * Access: RW
1150 */
1151 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1152
1153 /* reg_sfdf_flush_static
1154 * Static.
1155 * 0 - Flush only dynamic entries.
1156 * 1 - Flush both dynamic and static entries.
1157 * Access: RW
1158 */
1159 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1160
1161 static inline void mlxsw_reg_sfdf_pack(char *payload,
1162 enum mlxsw_reg_sfdf_flush_type type)
1163 {
1164 MLXSW_REG_ZERO(sfdf, payload);
1165 mlxsw_reg_sfdf_flush_type_set(payload, type);
1166 mlxsw_reg_sfdf_flush_static_set(payload, true);
1167 }
1168
1169 /* reg_sfdf_fid
1170 * FID to flush.
1171 * Access: RW
1172 */
1173 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1174
1175 /* reg_sfdf_system_port
1176 * Port to flush.
1177 * Access: RW
1178 */
1179 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1180
1181 /* reg_sfdf_port_fid_system_port
1182 * Port to flush, pointed to by FID.
1183 * Access: RW
1184 */
1185 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1186
1187 /* reg_sfdf_lag_id
1188 * LAG ID to flush.
1189 * Access: RW
1190 */
1191 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1192
1193 /* reg_sfdf_lag_fid_lag_id
1194 * LAG ID to flush, pointed to by FID.
1195 * Access: RW
1196 */
1197 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1198
1199 /* SLDR - Switch LAG Descriptor Register
1200 * -----------------------------------------
1201 * The switch LAG descriptor register is populated by LAG descriptors.
1202 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1203 * max_lag-1.
1204 */
1205 #define MLXSW_REG_SLDR_ID 0x2014
1206 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1207
1208 static const struct mlxsw_reg_info mlxsw_reg_sldr = {
1209 .id = MLXSW_REG_SLDR_ID,
1210 .len = MLXSW_REG_SLDR_LEN,
1211 };
1212
1213 enum mlxsw_reg_sldr_op {
1214 /* Indicates a creation of a new LAG-ID, lag_id must be valid */
1215 MLXSW_REG_SLDR_OP_LAG_CREATE,
1216 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1217 /* Ports that appear in the list have the Distributor enabled */
1218 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1219 /* Removes ports from the disributor list */
1220 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1221 };
1222
1223 /* reg_sldr_op
1224 * Operation.
1225 * Access: RW
1226 */
1227 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1228
1229 /* reg_sldr_lag_id
1230 * LAG identifier. The lag_id is the index into the LAG descriptor table.
1231 * Access: Index
1232 */
1233 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1234
1235 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1236 {
1237 MLXSW_REG_ZERO(sldr, payload);
1238 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1239 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1240 }
1241
1242 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1243 {
1244 MLXSW_REG_ZERO(sldr, payload);
1245 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1246 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1247 }
1248
1249 /* reg_sldr_num_ports
1250 * The number of member ports of the LAG.
1251 * Reserved for Create / Destroy operations
1252 * For Add / Remove operations - indicates the number of ports in the list.
1253 * Access: RW
1254 */
1255 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1256
1257 /* reg_sldr_system_port
1258 * System port.
1259 * Access: RW
1260 */
1261 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1262
1263 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1264 u8 local_port)
1265 {
1266 MLXSW_REG_ZERO(sldr, payload);
1267 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1268 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1269 mlxsw_reg_sldr_num_ports_set(payload, 1);
1270 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1271 }
1272
1273 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1274 u8 local_port)
1275 {
1276 MLXSW_REG_ZERO(sldr, payload);
1277 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1278 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1279 mlxsw_reg_sldr_num_ports_set(payload, 1);
1280 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1281 }
1282
1283 /* SLCR - Switch LAG Configuration 2 Register
1284 * -------------------------------------------
1285 * The Switch LAG Configuration register is used for configuring the
1286 * LAG properties of the switch.
1287 */
1288 #define MLXSW_REG_SLCR_ID 0x2015
1289 #define MLXSW_REG_SLCR_LEN 0x10
1290
1291 static const struct mlxsw_reg_info mlxsw_reg_slcr = {
1292 .id = MLXSW_REG_SLCR_ID,
1293 .len = MLXSW_REG_SLCR_LEN,
1294 };
1295
1296 enum mlxsw_reg_slcr_pp {
1297 /* Global Configuration (for all ports) */
1298 MLXSW_REG_SLCR_PP_GLOBAL,
1299 /* Per port configuration, based on local_port field */
1300 MLXSW_REG_SLCR_PP_PER_PORT,
1301 };
1302
1303 /* reg_slcr_pp
1304 * Per Port Configuration
1305 * Note: Reading at Global mode results in reading port 1 configuration.
1306 * Access: Index
1307 */
1308 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1309
1310 /* reg_slcr_local_port
1311 * Local port number
1312 * Supported from CPU port
1313 * Not supported from router port
1314 * Reserved when pp = Global Configuration
1315 * Access: Index
1316 */
1317 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1318
1319 enum mlxsw_reg_slcr_type {
1320 MLXSW_REG_SLCR_TYPE_CRC, /* default */
1321 MLXSW_REG_SLCR_TYPE_XOR,
1322 MLXSW_REG_SLCR_TYPE_RANDOM,
1323 };
1324
1325 /* reg_slcr_type
1326 * Hash type
1327 * Access: RW
1328 */
1329 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1330
1331 /* Ingress port */
1332 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1333 /* SMAC - for IPv4 and IPv6 packets */
1334 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1335 /* SMAC - for non-IP packets */
1336 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1337 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1338 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1339 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1340 /* DMAC - for IPv4 and IPv6 packets */
1341 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1342 /* DMAC - for non-IP packets */
1343 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1344 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1345 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1346 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1347 /* Ethertype - for IPv4 and IPv6 packets */
1348 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1349 /* Ethertype - for non-IP packets */
1350 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1351 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1352 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1353 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1354 /* VLAN ID - for IPv4 and IPv6 packets */
1355 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1356 /* VLAN ID - for non-IP packets */
1357 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1358 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1359 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1360 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1361 /* Source IP address (can be IPv4 or IPv6) */
1362 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1363 /* Destination IP address (can be IPv4 or IPv6) */
1364 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1365 /* TCP/UDP source port */
1366 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1367 /* TCP/UDP destination port*/
1368 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1369 /* IPv4 Protocol/IPv6 Next Header */
1370 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1371 /* IPv6 Flow label */
1372 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1373 /* SID - FCoE source ID */
1374 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1375 /* DID - FCoE destination ID */
1376 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1377 /* OXID - FCoE originator exchange ID */
1378 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1379 /* Destination QP number - for RoCE packets */
1380 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1381
1382 /* reg_slcr_lag_hash
1383 * LAG hashing configuration. This is a bitmask, in which each set
1384 * bit includes the corresponding item in the LAG hash calculation.
1385 * The default lag_hash contains SMAC, DMAC, VLANID and
1386 * Ethertype (for all packet types).
1387 * Access: RW
1388 */
1389 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1390
1391 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash)
1392 {
1393 MLXSW_REG_ZERO(slcr, payload);
1394 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1395 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_XOR);
1396 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1397 }
1398
1399 /* SLCOR - Switch LAG Collector Register
1400 * -------------------------------------
1401 * The Switch LAG Collector register controls the Local Port membership
1402 * in a LAG and enablement of the collector.
1403 */
1404 #define MLXSW_REG_SLCOR_ID 0x2016
1405 #define MLXSW_REG_SLCOR_LEN 0x10
1406
1407 static const struct mlxsw_reg_info mlxsw_reg_slcor = {
1408 .id = MLXSW_REG_SLCOR_ID,
1409 .len = MLXSW_REG_SLCOR_LEN,
1410 };
1411
1412 enum mlxsw_reg_slcor_col {
1413 /* Port is added with collector disabled */
1414 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1415 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1416 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1417 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1418 };
1419
1420 /* reg_slcor_col
1421 * Collector configuration
1422 * Access: RW
1423 */
1424 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1425
1426 /* reg_slcor_local_port
1427 * Local port number
1428 * Not supported for CPU port
1429 * Access: Index
1430 */
1431 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1432
1433 /* reg_slcor_lag_id
1434 * LAG Identifier. Index into the LAG descriptor table.
1435 * Access: Index
1436 */
1437 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1438
1439 /* reg_slcor_port_index
1440 * Port index in the LAG list. Only valid on Add Port to LAG col.
1441 * Valid range is from 0 to cap_max_lag_members-1
1442 * Access: RW
1443 */
1444 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1445
1446 static inline void mlxsw_reg_slcor_pack(char *payload,
1447 u8 local_port, u16 lag_id,
1448 enum mlxsw_reg_slcor_col col)
1449 {
1450 MLXSW_REG_ZERO(slcor, payload);
1451 mlxsw_reg_slcor_col_set(payload, col);
1452 mlxsw_reg_slcor_local_port_set(payload, local_port);
1453 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1454 }
1455
1456 static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1457 u8 local_port, u16 lag_id,
1458 u8 port_index)
1459 {
1460 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1461 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1462 mlxsw_reg_slcor_port_index_set(payload, port_index);
1463 }
1464
1465 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1466 u8 local_port, u16 lag_id)
1467 {
1468 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1469 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1470 }
1471
1472 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1473 u8 local_port, u16 lag_id)
1474 {
1475 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1476 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1477 }
1478
1479 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1480 u8 local_port, u16 lag_id)
1481 {
1482 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1483 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1484 }
1485
1486 /* SPMLR - Switch Port MAC Learning Register
1487 * -----------------------------------------
1488 * Controls the Switch MAC learning policy per port.
1489 */
1490 #define MLXSW_REG_SPMLR_ID 0x2018
1491 #define MLXSW_REG_SPMLR_LEN 0x8
1492
1493 static const struct mlxsw_reg_info mlxsw_reg_spmlr = {
1494 .id = MLXSW_REG_SPMLR_ID,
1495 .len = MLXSW_REG_SPMLR_LEN,
1496 };
1497
1498 /* reg_spmlr_local_port
1499 * Local port number.
1500 * Access: Index
1501 */
1502 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1503
1504 /* reg_spmlr_sub_port
1505 * Virtual port within the physical port.
1506 * Should be set to 0 when virtual ports are not enabled on the port.
1507 * Access: Index
1508 */
1509 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1510
1511 enum mlxsw_reg_spmlr_learn_mode {
1512 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1513 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1514 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1515 };
1516
1517 /* reg_spmlr_learn_mode
1518 * Learning mode on the port.
1519 * 0 - Learning disabled.
1520 * 2 - Learning enabled.
1521 * 3 - Security mode.
1522 *
1523 * In security mode the switch does not learn MACs on the port, but uses the
1524 * SMAC to see if it exists on another ingress port. If so, the packet is
1525 * classified as a bad packet and is discarded unless the software registers
1526 * to receive port security error packets usign HPKT.
1527 */
1528 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1529
1530 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1531 enum mlxsw_reg_spmlr_learn_mode mode)
1532 {
1533 MLXSW_REG_ZERO(spmlr, payload);
1534 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1535 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1536 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1537 }
1538
1539 /* SVFA - Switch VID to FID Allocation Register
1540 * --------------------------------------------
1541 * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1542 * virtualized ports.
1543 */
1544 #define MLXSW_REG_SVFA_ID 0x201C
1545 #define MLXSW_REG_SVFA_LEN 0x10
1546
1547 static const struct mlxsw_reg_info mlxsw_reg_svfa = {
1548 .id = MLXSW_REG_SVFA_ID,
1549 .len = MLXSW_REG_SVFA_LEN,
1550 };
1551
1552 /* reg_svfa_swid
1553 * Switch partition ID.
1554 * Access: Index
1555 */
1556 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1557
1558 /* reg_svfa_local_port
1559 * Local port number.
1560 * Access: Index
1561 *
1562 * Note: Reserved for 802.1Q FIDs.
1563 */
1564 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1565
1566 enum mlxsw_reg_svfa_mt {
1567 MLXSW_REG_SVFA_MT_VID_TO_FID,
1568 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1569 };
1570
1571 /* reg_svfa_mapping_table
1572 * Mapping table:
1573 * 0 - VID to FID
1574 * 1 - {Port, VID} to FID
1575 * Access: Index
1576 *
1577 * Note: Reserved for SwitchX-2.
1578 */
1579 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1580
1581 /* reg_svfa_v
1582 * Valid.
1583 * Valid if set.
1584 * Access: RW
1585 *
1586 * Note: Reserved for SwitchX-2.
1587 */
1588 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1589
1590 /* reg_svfa_fid
1591 * Filtering ID.
1592 * Access: RW
1593 */
1594 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1595
1596 /* reg_svfa_vid
1597 * VLAN ID.
1598 * Access: Index
1599 */
1600 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1601
1602 /* reg_svfa_counter_set_type
1603 * Counter set type for flow counters.
1604 * Access: RW
1605 *
1606 * Note: Reserved for SwitchX-2.
1607 */
1608 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1609
1610 /* reg_svfa_counter_index
1611 * Counter index for flow counters.
1612 * Access: RW
1613 *
1614 * Note: Reserved for SwitchX-2.
1615 */
1616 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1617
1618 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1619 enum mlxsw_reg_svfa_mt mt, bool valid,
1620 u16 fid, u16 vid)
1621 {
1622 MLXSW_REG_ZERO(svfa, payload);
1623 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1624 mlxsw_reg_svfa_swid_set(payload, 0);
1625 mlxsw_reg_svfa_local_port_set(payload, local_port);
1626 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1627 mlxsw_reg_svfa_v_set(payload, valid);
1628 mlxsw_reg_svfa_fid_set(payload, fid);
1629 mlxsw_reg_svfa_vid_set(payload, vid);
1630 }
1631
1632 /* SVPE - Switch Virtual-Port Enabling Register
1633 * --------------------------------------------
1634 * Enables port virtualization.
1635 */
1636 #define MLXSW_REG_SVPE_ID 0x201E
1637 #define MLXSW_REG_SVPE_LEN 0x4
1638
1639 static const struct mlxsw_reg_info mlxsw_reg_svpe = {
1640 .id = MLXSW_REG_SVPE_ID,
1641 .len = MLXSW_REG_SVPE_LEN,
1642 };
1643
1644 /* reg_svpe_local_port
1645 * Local port number
1646 * Access: Index
1647 *
1648 * Note: CPU port is not supported (uses VLAN mode only).
1649 */
1650 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1651
1652 /* reg_svpe_vp_en
1653 * Virtual port enable.
1654 * 0 - Disable, VLAN mode (VID to FID).
1655 * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1656 * Access: RW
1657 */
1658 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1659
1660 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1661 bool enable)
1662 {
1663 MLXSW_REG_ZERO(svpe, payload);
1664 mlxsw_reg_svpe_local_port_set(payload, local_port);
1665 mlxsw_reg_svpe_vp_en_set(payload, enable);
1666 }
1667
1668 /* SFMR - Switch FID Management Register
1669 * -------------------------------------
1670 * Creates and configures FIDs.
1671 */
1672 #define MLXSW_REG_SFMR_ID 0x201F
1673 #define MLXSW_REG_SFMR_LEN 0x18
1674
1675 static const struct mlxsw_reg_info mlxsw_reg_sfmr = {
1676 .id = MLXSW_REG_SFMR_ID,
1677 .len = MLXSW_REG_SFMR_LEN,
1678 };
1679
1680 enum mlxsw_reg_sfmr_op {
1681 MLXSW_REG_SFMR_OP_CREATE_FID,
1682 MLXSW_REG_SFMR_OP_DESTROY_FID,
1683 };
1684
1685 /* reg_sfmr_op
1686 * Operation.
1687 * 0 - Create or edit FID.
1688 * 1 - Destroy FID.
1689 * Access: WO
1690 */
1691 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1692
1693 /* reg_sfmr_fid
1694 * Filtering ID.
1695 * Access: Index
1696 */
1697 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1698
1699 /* reg_sfmr_fid_offset
1700 * FID offset.
1701 * Used to point into the flooding table selected by SFGC register if
1702 * the table is of type FID-Offset. Otherwise, this field is reserved.
1703 * Access: RW
1704 */
1705 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1706
1707 /* reg_sfmr_vtfp
1708 * Valid Tunnel Flood Pointer.
1709 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1710 * Access: RW
1711 *
1712 * Note: Reserved for 802.1Q FIDs.
1713 */
1714 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1715
1716 /* reg_sfmr_nve_tunnel_flood_ptr
1717 * Underlay Flooding and BC Pointer.
1718 * Used as a pointer to the first entry of the group based link lists of
1719 * flooding or BC entries (for NVE tunnels).
1720 * Access: RW
1721 */
1722 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1723
1724 /* reg_sfmr_vv
1725 * VNI Valid.
1726 * If not set, then vni is reserved.
1727 * Access: RW
1728 *
1729 * Note: Reserved for 802.1Q FIDs.
1730 */
1731 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1732
1733 /* reg_sfmr_vni
1734 * Virtual Network Identifier.
1735 * Access: RW
1736 *
1737 * Note: A given VNI can only be assigned to one FID.
1738 */
1739 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1740
1741 static inline void mlxsw_reg_sfmr_pack(char *payload,
1742 enum mlxsw_reg_sfmr_op op, u16 fid,
1743 u16 fid_offset)
1744 {
1745 MLXSW_REG_ZERO(sfmr, payload);
1746 mlxsw_reg_sfmr_op_set(payload, op);
1747 mlxsw_reg_sfmr_fid_set(payload, fid);
1748 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1749 mlxsw_reg_sfmr_vtfp_set(payload, false);
1750 mlxsw_reg_sfmr_vv_set(payload, false);
1751 }
1752
1753 /* SPVMLR - Switch Port VLAN MAC Learning Register
1754 * -----------------------------------------------
1755 * Controls the switch MAC learning policy per {Port, VID}.
1756 */
1757 #define MLXSW_REG_SPVMLR_ID 0x2020
1758 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1759 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1760 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 256
1761 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1762 MLXSW_REG_SPVMLR_REC_LEN * \
1763 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1764
1765 static const struct mlxsw_reg_info mlxsw_reg_spvmlr = {
1766 .id = MLXSW_REG_SPVMLR_ID,
1767 .len = MLXSW_REG_SPVMLR_LEN,
1768 };
1769
1770 /* reg_spvmlr_local_port
1771 * Local ingress port.
1772 * Access: Index
1773 *
1774 * Note: CPU port is not supported.
1775 */
1776 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1777
1778 /* reg_spvmlr_num_rec
1779 * Number of records to update.
1780 * Access: OP
1781 */
1782 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1783
1784 /* reg_spvmlr_rec_learn_enable
1785 * 0 - Disable learning for {Port, VID}.
1786 * 1 - Enable learning for {Port, VID}.
1787 * Access: RW
1788 */
1789 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1790 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1791
1792 /* reg_spvmlr_rec_vid
1793 * VLAN ID to be added/removed from port or for querying.
1794 * Access: Index
1795 */
1796 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1797 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1798
1799 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1800 u16 vid_begin, u16 vid_end,
1801 bool learn_enable)
1802 {
1803 int num_rec = vid_end - vid_begin + 1;
1804 int i;
1805
1806 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1807
1808 MLXSW_REG_ZERO(spvmlr, payload);
1809 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1810 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1811
1812 for (i = 0; i < num_rec; i++) {
1813 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1814 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1815 }
1816 }
1817
1818 /* QTCT - QoS Switch Traffic Class Table
1819 * -------------------------------------
1820 * Configures the mapping between the packet switch priority and the
1821 * traffic class on the transmit port.
1822 */
1823 #define MLXSW_REG_QTCT_ID 0x400A
1824 #define MLXSW_REG_QTCT_LEN 0x08
1825
1826 static const struct mlxsw_reg_info mlxsw_reg_qtct = {
1827 .id = MLXSW_REG_QTCT_ID,
1828 .len = MLXSW_REG_QTCT_LEN,
1829 };
1830
1831 /* reg_qtct_local_port
1832 * Local port number.
1833 * Access: Index
1834 *
1835 * Note: CPU port is not supported.
1836 */
1837 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
1838
1839 /* reg_qtct_sub_port
1840 * Virtual port within the physical port.
1841 * Should be set to 0 when virtual ports are not enabled on the port.
1842 * Access: Index
1843 */
1844 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
1845
1846 /* reg_qtct_switch_prio
1847 * Switch priority.
1848 * Access: Index
1849 */
1850 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
1851
1852 /* reg_qtct_tclass
1853 * Traffic class.
1854 * Default values:
1855 * switch_prio 0 : tclass 1
1856 * switch_prio 1 : tclass 0
1857 * switch_prio i : tclass i, for i > 1
1858 * Access: RW
1859 */
1860 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
1861
1862 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
1863 u8 switch_prio, u8 tclass)
1864 {
1865 MLXSW_REG_ZERO(qtct, payload);
1866 mlxsw_reg_qtct_local_port_set(payload, local_port);
1867 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
1868 mlxsw_reg_qtct_tclass_set(payload, tclass);
1869 }
1870
1871 /* QEEC - QoS ETS Element Configuration Register
1872 * ---------------------------------------------
1873 * Configures the ETS elements.
1874 */
1875 #define MLXSW_REG_QEEC_ID 0x400D
1876 #define MLXSW_REG_QEEC_LEN 0x1C
1877
1878 static const struct mlxsw_reg_info mlxsw_reg_qeec = {
1879 .id = MLXSW_REG_QEEC_ID,
1880 .len = MLXSW_REG_QEEC_LEN,
1881 };
1882
1883 /* reg_qeec_local_port
1884 * Local port number.
1885 * Access: Index
1886 *
1887 * Note: CPU port is supported.
1888 */
1889 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
1890
1891 enum mlxsw_reg_qeec_hr {
1892 MLXSW_REG_QEEC_HIERARCY_PORT,
1893 MLXSW_REG_QEEC_HIERARCY_GROUP,
1894 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1895 MLXSW_REG_QEEC_HIERARCY_TC,
1896 };
1897
1898 /* reg_qeec_element_hierarchy
1899 * 0 - Port
1900 * 1 - Group
1901 * 2 - Subgroup
1902 * 3 - Traffic Class
1903 * Access: Index
1904 */
1905 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
1906
1907 /* reg_qeec_element_index
1908 * The index of the element in the hierarchy.
1909 * Access: Index
1910 */
1911 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
1912
1913 /* reg_qeec_next_element_index
1914 * The index of the next (lower) element in the hierarchy.
1915 * Access: RW
1916 *
1917 * Note: Reserved for element_hierarchy 0.
1918 */
1919 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
1920
1921 enum {
1922 MLXSW_REG_QEEC_BYTES_MODE,
1923 MLXSW_REG_QEEC_PACKETS_MODE,
1924 };
1925
1926 /* reg_qeec_pb
1927 * Packets or bytes mode.
1928 * 0 - Bytes mode
1929 * 1 - Packets mode
1930 * Access: RW
1931 *
1932 * Note: Used for max shaper configuration. For Spectrum, packets mode
1933 * is supported only for traffic classes of CPU port.
1934 */
1935 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
1936
1937 /* reg_qeec_mase
1938 * Max shaper configuration enable. Enables configuration of the max
1939 * shaper on this ETS element.
1940 * 0 - Disable
1941 * 1 - Enable
1942 * Access: RW
1943 */
1944 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
1945
1946 /* A large max rate will disable the max shaper. */
1947 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */
1948
1949 /* reg_qeec_max_shaper_rate
1950 * Max shaper information rate.
1951 * For CPU port, can only be configured for port hierarchy.
1952 * When in bytes mode, value is specified in units of 1000bps.
1953 * Access: RW
1954 */
1955 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
1956
1957 /* reg_qeec_de
1958 * DWRR configuration enable. Enables configuration of the dwrr and
1959 * dwrr_weight.
1960 * 0 - Disable
1961 * 1 - Enable
1962 * Access: RW
1963 */
1964 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
1965
1966 /* reg_qeec_dwrr
1967 * Transmission selection algorithm to use on the link going down from
1968 * the ETS element.
1969 * 0 - Strict priority
1970 * 1 - DWRR
1971 * Access: RW
1972 */
1973 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
1974
1975 /* reg_qeec_dwrr_weight
1976 * DWRR weight on the link going down from the ETS element. The
1977 * percentage of bandwidth guaranteed to an ETS element within
1978 * its hierarchy. The sum of all weights across all ETS elements
1979 * within one hierarchy should be equal to 100. Reserved when
1980 * transmission selection algorithm is strict priority.
1981 * Access: RW
1982 */
1983 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
1984
1985 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
1986 enum mlxsw_reg_qeec_hr hr, u8 index,
1987 u8 next_index)
1988 {
1989 MLXSW_REG_ZERO(qeec, payload);
1990 mlxsw_reg_qeec_local_port_set(payload, local_port);
1991 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
1992 mlxsw_reg_qeec_element_index_set(payload, index);
1993 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
1994 }
1995
1996 /* PMLP - Ports Module to Local Port Register
1997 * ------------------------------------------
1998 * Configures the assignment of modules to local ports.
1999 */
2000 #define MLXSW_REG_PMLP_ID 0x5002
2001 #define MLXSW_REG_PMLP_LEN 0x40
2002
2003 static const struct mlxsw_reg_info mlxsw_reg_pmlp = {
2004 .id = MLXSW_REG_PMLP_ID,
2005 .len = MLXSW_REG_PMLP_LEN,
2006 };
2007
2008 /* reg_pmlp_rxtx
2009 * 0 - Tx value is used for both Tx and Rx.
2010 * 1 - Rx value is taken from a separte field.
2011 * Access: RW
2012 */
2013 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
2014
2015 /* reg_pmlp_local_port
2016 * Local port number.
2017 * Access: Index
2018 */
2019 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
2020
2021 /* reg_pmlp_width
2022 * 0 - Unmap local port.
2023 * 1 - Lane 0 is used.
2024 * 2 - Lanes 0 and 1 are used.
2025 * 4 - Lanes 0, 1, 2 and 3 are used.
2026 * Access: RW
2027 */
2028 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
2029
2030 /* reg_pmlp_module
2031 * Module number.
2032 * Access: RW
2033 */
2034 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
2035
2036 /* reg_pmlp_tx_lane
2037 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
2038 * Access: RW
2039 */
2040 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
2041
2042 /* reg_pmlp_rx_lane
2043 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
2044 * equal to Tx lane.
2045 * Access: RW
2046 */
2047 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
2048
2049 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
2050 {
2051 MLXSW_REG_ZERO(pmlp, payload);
2052 mlxsw_reg_pmlp_local_port_set(payload, local_port);
2053 }
2054
2055 /* PMTU - Port MTU Register
2056 * ------------------------
2057 * Configures and reports the port MTU.
2058 */
2059 #define MLXSW_REG_PMTU_ID 0x5003
2060 #define MLXSW_REG_PMTU_LEN 0x10
2061
2062 static const struct mlxsw_reg_info mlxsw_reg_pmtu = {
2063 .id = MLXSW_REG_PMTU_ID,
2064 .len = MLXSW_REG_PMTU_LEN,
2065 };
2066
2067 /* reg_pmtu_local_port
2068 * Local port number.
2069 * Access: Index
2070 */
2071 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
2072
2073 /* reg_pmtu_max_mtu
2074 * Maximum MTU.
2075 * When port type (e.g. Ethernet) is configured, the relevant MTU is
2076 * reported, otherwise the minimum between the max_mtu of the different
2077 * types is reported.
2078 * Access: RO
2079 */
2080 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
2081
2082 /* reg_pmtu_admin_mtu
2083 * MTU value to set port to. Must be smaller or equal to max_mtu.
2084 * Note: If port type is Infiniband, then port must be disabled, when its
2085 * MTU is set.
2086 * Access: RW
2087 */
2088 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
2089
2090 /* reg_pmtu_oper_mtu
2091 * The actual MTU configured on the port. Packets exceeding this size
2092 * will be dropped.
2093 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
2094 * oper_mtu might be smaller than admin_mtu.
2095 * Access: RO
2096 */
2097 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
2098
2099 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
2100 u16 new_mtu)
2101 {
2102 MLXSW_REG_ZERO(pmtu, payload);
2103 mlxsw_reg_pmtu_local_port_set(payload, local_port);
2104 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
2105 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
2106 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
2107 }
2108
2109 /* PTYS - Port Type and Speed Register
2110 * -----------------------------------
2111 * Configures and reports the port speed type.
2112 *
2113 * Note: When set while the link is up, the changes will not take effect
2114 * until the port transitions from down to up state.
2115 */
2116 #define MLXSW_REG_PTYS_ID 0x5004
2117 #define MLXSW_REG_PTYS_LEN 0x40
2118
2119 static const struct mlxsw_reg_info mlxsw_reg_ptys = {
2120 .id = MLXSW_REG_PTYS_ID,
2121 .len = MLXSW_REG_PTYS_LEN,
2122 };
2123
2124 /* reg_ptys_local_port
2125 * Local port number.
2126 * Access: Index
2127 */
2128 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
2129
2130 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
2131
2132 /* reg_ptys_proto_mask
2133 * Protocol mask. Indicates which protocol is used.
2134 * 0 - Infiniband.
2135 * 1 - Fibre Channel.
2136 * 2 - Ethernet.
2137 * Access: Index
2138 */
2139 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
2140
2141 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
2142 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
2143 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
2144 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
2145 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
2146 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
2147 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
2148 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
2149 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
2150 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
2151 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
2152 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
2153 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
2154 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
2155 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
2156 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
2157 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
2158 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
2159 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
2160 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
2161 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
2162 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
2163 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
2164 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
2165 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
2166 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
2167 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
2168
2169 /* reg_ptys_eth_proto_cap
2170 * Ethernet port supported speeds and protocols.
2171 * Access: RO
2172 */
2173 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
2174
2175 /* reg_ptys_eth_proto_admin
2176 * Speed and protocol to set port to.
2177 * Access: RW
2178 */
2179 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
2180
2181 /* reg_ptys_eth_proto_oper
2182 * The current speed and protocol configured for the port.
2183 * Access: RO
2184 */
2185 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
2186
2187 static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port,
2188 u32 proto_admin)
2189 {
2190 MLXSW_REG_ZERO(ptys, payload);
2191 mlxsw_reg_ptys_local_port_set(payload, local_port);
2192 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
2193 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
2194 }
2195
2196 static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap,
2197 u32 *p_eth_proto_adm,
2198 u32 *p_eth_proto_oper)
2199 {
2200 if (p_eth_proto_cap)
2201 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
2202 if (p_eth_proto_adm)
2203 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
2204 if (p_eth_proto_oper)
2205 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
2206 }
2207
2208 /* PPAD - Port Physical Address Register
2209 * -------------------------------------
2210 * The PPAD register configures the per port physical MAC address.
2211 */
2212 #define MLXSW_REG_PPAD_ID 0x5005
2213 #define MLXSW_REG_PPAD_LEN 0x10
2214
2215 static const struct mlxsw_reg_info mlxsw_reg_ppad = {
2216 .id = MLXSW_REG_PPAD_ID,
2217 .len = MLXSW_REG_PPAD_LEN,
2218 };
2219
2220 /* reg_ppad_single_base_mac
2221 * 0: base_mac, local port should be 0 and mac[7:0] is
2222 * reserved. HW will set incremental
2223 * 1: single_mac - mac of the local_port
2224 * Access: RW
2225 */
2226 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
2227
2228 /* reg_ppad_local_port
2229 * port number, if single_base_mac = 0 then local_port is reserved
2230 * Access: RW
2231 */
2232 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
2233
2234 /* reg_ppad_mac
2235 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
2236 * If single_base_mac = 1 - the per port MAC address
2237 * Access: RW
2238 */
2239 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
2240
2241 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
2242 u8 local_port)
2243 {
2244 MLXSW_REG_ZERO(ppad, payload);
2245 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
2246 mlxsw_reg_ppad_local_port_set(payload, local_port);
2247 }
2248
2249 /* PAOS - Ports Administrative and Operational Status Register
2250 * -----------------------------------------------------------
2251 * Configures and retrieves per port administrative and operational status.
2252 */
2253 #define MLXSW_REG_PAOS_ID 0x5006
2254 #define MLXSW_REG_PAOS_LEN 0x10
2255
2256 static const struct mlxsw_reg_info mlxsw_reg_paos = {
2257 .id = MLXSW_REG_PAOS_ID,
2258 .len = MLXSW_REG_PAOS_LEN,
2259 };
2260
2261 /* reg_paos_swid
2262 * Switch partition ID with which to associate the port.
2263 * Note: while external ports uses unique local port numbers (and thus swid is
2264 * redundant), router ports use the same local port number where swid is the
2265 * only indication for the relevant port.
2266 * Access: Index
2267 */
2268 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
2269
2270 /* reg_paos_local_port
2271 * Local port number.
2272 * Access: Index
2273 */
2274 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
2275
2276 /* reg_paos_admin_status
2277 * Port administrative state (the desired state of the port):
2278 * 1 - Up.
2279 * 2 - Down.
2280 * 3 - Up once. This means that in case of link failure, the port won't go
2281 * into polling mode, but will wait to be re-enabled by software.
2282 * 4 - Disabled by system. Can only be set by hardware.
2283 * Access: RW
2284 */
2285 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
2286
2287 /* reg_paos_oper_status
2288 * Port operational state (the current state):
2289 * 1 - Up.
2290 * 2 - Down.
2291 * 3 - Down by port failure. This means that the device will not let the
2292 * port up again until explicitly specified by software.
2293 * Access: RO
2294 */
2295 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
2296
2297 /* reg_paos_ase
2298 * Admin state update enabled.
2299 * Access: WO
2300 */
2301 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
2302
2303 /* reg_paos_ee
2304 * Event update enable. If this bit is set, event generation will be
2305 * updated based on the e field.
2306 * Access: WO
2307 */
2308 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
2309
2310 /* reg_paos_e
2311 * Event generation on operational state change:
2312 * 0 - Do not generate event.
2313 * 1 - Generate Event.
2314 * 2 - Generate Single Event.
2315 * Access: RW
2316 */
2317 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
2318
2319 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
2320 enum mlxsw_port_admin_status status)
2321 {
2322 MLXSW_REG_ZERO(paos, payload);
2323 mlxsw_reg_paos_swid_set(payload, 0);
2324 mlxsw_reg_paos_local_port_set(payload, local_port);
2325 mlxsw_reg_paos_admin_status_set(payload, status);
2326 mlxsw_reg_paos_oper_status_set(payload, 0);
2327 mlxsw_reg_paos_ase_set(payload, 1);
2328 mlxsw_reg_paos_ee_set(payload, 1);
2329 mlxsw_reg_paos_e_set(payload, 1);
2330 }
2331
2332 /* PFCC - Ports Flow Control Configuration Register
2333 * ------------------------------------------------
2334 * Configures and retrieves the per port flow control configuration.
2335 */
2336 #define MLXSW_REG_PFCC_ID 0x5007
2337 #define MLXSW_REG_PFCC_LEN 0x20
2338
2339 static const struct mlxsw_reg_info mlxsw_reg_pfcc = {
2340 .id = MLXSW_REG_PFCC_ID,
2341 .len = MLXSW_REG_PFCC_LEN,
2342 };
2343
2344 /* reg_pfcc_local_port
2345 * Local port number.
2346 * Access: Index
2347 */
2348 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
2349
2350 /* reg_pfcc_pnat
2351 * Port number access type. Determines the way local_port is interpreted:
2352 * 0 - Local port number.
2353 * 1 - IB / label port number.
2354 * Access: Index
2355 */
2356 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
2357
2358 /* reg_pfcc_shl_cap
2359 * Send to higher layers capabilities:
2360 * 0 - No capability of sending Pause and PFC frames to higher layers.
2361 * 1 - Device has capability of sending Pause and PFC frames to higher
2362 * layers.
2363 * Access: RO
2364 */
2365 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
2366
2367 /* reg_pfcc_shl_opr
2368 * Send to higher layers operation:
2369 * 0 - Pause and PFC frames are handled by the port (default).
2370 * 1 - Pause and PFC frames are handled by the port and also sent to
2371 * higher layers. Only valid if shl_cap = 1.
2372 * Access: RW
2373 */
2374 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
2375
2376 /* reg_pfcc_ppan
2377 * Pause policy auto negotiation.
2378 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
2379 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
2380 * based on the auto-negotiation resolution.
2381 * Access: RW
2382 *
2383 * Note: The auto-negotiation advertisement is set according to pptx and
2384 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
2385 */
2386 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
2387
2388 /* reg_pfcc_prio_mask_tx
2389 * Bit per priority indicating if Tx flow control policy should be
2390 * updated based on bit pfctx.
2391 * Access: WO
2392 */
2393 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
2394
2395 /* reg_pfcc_prio_mask_rx
2396 * Bit per priority indicating if Rx flow control policy should be
2397 * updated based on bit pfcrx.
2398 * Access: WO
2399 */
2400 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
2401
2402 /* reg_pfcc_pptx
2403 * Admin Pause policy on Tx.
2404 * 0 - Never generate Pause frames (default).
2405 * 1 - Generate Pause frames according to Rx buffer threshold.
2406 * Access: RW
2407 */
2408 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
2409
2410 /* reg_pfcc_aptx
2411 * Active (operational) Pause policy on Tx.
2412 * 0 - Never generate Pause frames.
2413 * 1 - Generate Pause frames according to Rx buffer threshold.
2414 * Access: RO
2415 */
2416 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
2417
2418 /* reg_pfcc_pfctx
2419 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
2420 * 0 - Never generate priority Pause frames on the specified priority
2421 * (default).
2422 * 1 - Generate priority Pause frames according to Rx buffer threshold on
2423 * the specified priority.
2424 * Access: RW
2425 *
2426 * Note: pfctx and pptx must be mutually exclusive.
2427 */
2428 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
2429
2430 /* reg_pfcc_pprx
2431 * Admin Pause policy on Rx.
2432 * 0 - Ignore received Pause frames (default).
2433 * 1 - Respect received Pause frames.
2434 * Access: RW
2435 */
2436 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
2437
2438 /* reg_pfcc_aprx
2439 * Active (operational) Pause policy on Rx.
2440 * 0 - Ignore received Pause frames.
2441 * 1 - Respect received Pause frames.
2442 * Access: RO
2443 */
2444 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
2445
2446 /* reg_pfcc_pfcrx
2447 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
2448 * 0 - Ignore incoming priority Pause frames on the specified priority
2449 * (default).
2450 * 1 - Respect incoming priority Pause frames on the specified priority.
2451 * Access: RW
2452 */
2453 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
2454
2455 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF
2456
2457 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
2458 {
2459 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
2460 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
2461 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
2462 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
2463 }
2464
2465 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
2466 {
2467 MLXSW_REG_ZERO(pfcc, payload);
2468 mlxsw_reg_pfcc_local_port_set(payload, local_port);
2469 }
2470
2471 /* PPCNT - Ports Performance Counters Register
2472 * -------------------------------------------
2473 * The PPCNT register retrieves per port performance counters.
2474 */
2475 #define MLXSW_REG_PPCNT_ID 0x5008
2476 #define MLXSW_REG_PPCNT_LEN 0x100
2477
2478 static const struct mlxsw_reg_info mlxsw_reg_ppcnt = {
2479 .id = MLXSW_REG_PPCNT_ID,
2480 .len = MLXSW_REG_PPCNT_LEN,
2481 };
2482
2483 /* reg_ppcnt_swid
2484 * For HCA: must be always 0.
2485 * Switch partition ID to associate port with.
2486 * Switch partitions are numbered from 0 to 7 inclusively.
2487 * Switch partition 254 indicates stacking ports.
2488 * Switch partition 255 indicates all switch partitions.
2489 * Only valid on Set() operation with local_port=255.
2490 * Access: Index
2491 */
2492 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
2493
2494 /* reg_ppcnt_local_port
2495 * Local port number.
2496 * 255 indicates all ports on the device, and is only allowed
2497 * for Set() operation.
2498 * Access: Index
2499 */
2500 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
2501
2502 /* reg_ppcnt_pnat
2503 * Port number access type:
2504 * 0 - Local port number
2505 * 1 - IB port number
2506 * Access: Index
2507 */
2508 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
2509
2510 enum mlxsw_reg_ppcnt_grp {
2511 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
2512 MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
2513 MLXSW_REG_PPCNT_TC_CNT = 0x11,
2514 };
2515
2516 /* reg_ppcnt_grp
2517 * Performance counter group.
2518 * Group 63 indicates all groups. Only valid on Set() operation with
2519 * clr bit set.
2520 * 0x0: IEEE 802.3 Counters
2521 * 0x1: RFC 2863 Counters
2522 * 0x2: RFC 2819 Counters
2523 * 0x3: RFC 3635 Counters
2524 * 0x5: Ethernet Extended Counters
2525 * 0x8: Link Level Retransmission Counters
2526 * 0x10: Per Priority Counters
2527 * 0x11: Per Traffic Class Counters
2528 * 0x12: Physical Layer Counters
2529 * Access: Index
2530 */
2531 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
2532
2533 /* reg_ppcnt_clr
2534 * Clear counters. Setting the clr bit will reset the counter value
2535 * for all counters in the counter group. This bit can be set
2536 * for both Set() and Get() operation.
2537 * Access: OP
2538 */
2539 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
2540
2541 /* reg_ppcnt_prio_tc
2542 * Priority for counter set that support per priority, valid values: 0-7.
2543 * Traffic class for counter set that support per traffic class,
2544 * valid values: 0- cap_max_tclass-1 .
2545 * For HCA: cap_max_tclass is always 8.
2546 * Otherwise must be 0.
2547 * Access: Index
2548 */
2549 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
2550
2551 /* Ethernet IEEE 802.3 Counter Group */
2552
2553 /* reg_ppcnt_a_frames_transmitted_ok
2554 * Access: RO
2555 */
2556 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
2557 0x08 + 0x00, 0, 64);
2558
2559 /* reg_ppcnt_a_frames_received_ok
2560 * Access: RO
2561 */
2562 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
2563 0x08 + 0x08, 0, 64);
2564
2565 /* reg_ppcnt_a_frame_check_sequence_errors
2566 * Access: RO
2567 */
2568 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
2569 0x08 + 0x10, 0, 64);
2570
2571 /* reg_ppcnt_a_alignment_errors
2572 * Access: RO
2573 */
2574 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
2575 0x08 + 0x18, 0, 64);
2576
2577 /* reg_ppcnt_a_octets_transmitted_ok
2578 * Access: RO
2579 */
2580 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
2581 0x08 + 0x20, 0, 64);
2582
2583 /* reg_ppcnt_a_octets_received_ok
2584 * Access: RO
2585 */
2586 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
2587 0x08 + 0x28, 0, 64);
2588
2589 /* reg_ppcnt_a_multicast_frames_xmitted_ok
2590 * Access: RO
2591 */
2592 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
2593 0x08 + 0x30, 0, 64);
2594
2595 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
2596 * Access: RO
2597 */
2598 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
2599 0x08 + 0x38, 0, 64);
2600
2601 /* reg_ppcnt_a_multicast_frames_received_ok
2602 * Access: RO
2603 */
2604 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
2605 0x08 + 0x40, 0, 64);
2606
2607 /* reg_ppcnt_a_broadcast_frames_received_ok
2608 * Access: RO
2609 */
2610 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
2611 0x08 + 0x48, 0, 64);
2612
2613 /* reg_ppcnt_a_in_range_length_errors
2614 * Access: RO
2615 */
2616 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
2617 0x08 + 0x50, 0, 64);
2618
2619 /* reg_ppcnt_a_out_of_range_length_field
2620 * Access: RO
2621 */
2622 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
2623 0x08 + 0x58, 0, 64);
2624
2625 /* reg_ppcnt_a_frame_too_long_errors
2626 * Access: RO
2627 */
2628 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
2629 0x08 + 0x60, 0, 64);
2630
2631 /* reg_ppcnt_a_symbol_error_during_carrier
2632 * Access: RO
2633 */
2634 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
2635 0x08 + 0x68, 0, 64);
2636
2637 /* reg_ppcnt_a_mac_control_frames_transmitted
2638 * Access: RO
2639 */
2640 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
2641 0x08 + 0x70, 0, 64);
2642
2643 /* reg_ppcnt_a_mac_control_frames_received
2644 * Access: RO
2645 */
2646 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
2647 0x08 + 0x78, 0, 64);
2648
2649 /* reg_ppcnt_a_unsupported_opcodes_received
2650 * Access: RO
2651 */
2652 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
2653 0x08 + 0x80, 0, 64);
2654
2655 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
2656 * Access: RO
2657 */
2658 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
2659 0x08 + 0x88, 0, 64);
2660
2661 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
2662 * Access: RO
2663 */
2664 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
2665 0x08 + 0x90, 0, 64);
2666
2667 /* Ethernet Per Priority Group Counters */
2668
2669 /* reg_ppcnt_rx_octets
2670 * Access: RO
2671 */
2672 MLXSW_ITEM64(reg, ppcnt, rx_octets, 0x08 + 0x00, 0, 64);
2673
2674 /* reg_ppcnt_rx_frames
2675 * Access: RO
2676 */
2677 MLXSW_ITEM64(reg, ppcnt, rx_frames, 0x08 + 0x20, 0, 64);
2678
2679 /* reg_ppcnt_tx_octets
2680 * Access: RO
2681 */
2682 MLXSW_ITEM64(reg, ppcnt, tx_octets, 0x08 + 0x28, 0, 64);
2683
2684 /* reg_ppcnt_tx_frames
2685 * Access: RO
2686 */
2687 MLXSW_ITEM64(reg, ppcnt, tx_frames, 0x08 + 0x48, 0, 64);
2688
2689 /* reg_ppcnt_rx_pause
2690 * Access: RO
2691 */
2692 MLXSW_ITEM64(reg, ppcnt, rx_pause, 0x08 + 0x50, 0, 64);
2693
2694 /* reg_ppcnt_rx_pause_duration
2695 * Access: RO
2696 */
2697 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 0x08 + 0x58, 0, 64);
2698
2699 /* reg_ppcnt_tx_pause
2700 * Access: RO
2701 */
2702 MLXSW_ITEM64(reg, ppcnt, tx_pause, 0x08 + 0x60, 0, 64);
2703
2704 /* reg_ppcnt_tx_pause_duration
2705 * Access: RO
2706 */
2707 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 0x08 + 0x68, 0, 64);
2708
2709 /* reg_ppcnt_rx_pause_transition
2710 * Access: RO
2711 */
2712 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 0x08 + 0x70, 0, 64);
2713
2714 /* Ethernet Per Traffic Group Counters */
2715
2716 /* reg_ppcnt_tc_transmit_queue
2717 * Contains the transmit queue depth in cells of traffic class
2718 * selected by prio_tc and the port selected by local_port.
2719 * The field cannot be cleared.
2720 * Access: RO
2721 */
2722 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 0x08 + 0x00, 0, 64);
2723
2724 /* reg_ppcnt_tc_no_buffer_discard_uc
2725 * The number of unicast packets dropped due to lack of shared
2726 * buffer resources.
2727 * Access: RO
2728 */
2729 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 0x08 + 0x08, 0, 64);
2730
2731 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
2732 enum mlxsw_reg_ppcnt_grp grp,
2733 u8 prio_tc)
2734 {
2735 MLXSW_REG_ZERO(ppcnt, payload);
2736 mlxsw_reg_ppcnt_swid_set(payload, 0);
2737 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
2738 mlxsw_reg_ppcnt_pnat_set(payload, 0);
2739 mlxsw_reg_ppcnt_grp_set(payload, grp);
2740 mlxsw_reg_ppcnt_clr_set(payload, 0);
2741 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
2742 }
2743
2744 /* PPTB - Port Prio To Buffer Register
2745 * -----------------------------------
2746 * Configures the switch priority to buffer table.
2747 */
2748 #define MLXSW_REG_PPTB_ID 0x500B
2749 #define MLXSW_REG_PPTB_LEN 0x10
2750
2751 static const struct mlxsw_reg_info mlxsw_reg_pptb = {
2752 .id = MLXSW_REG_PPTB_ID,
2753 .len = MLXSW_REG_PPTB_LEN,
2754 };
2755
2756 enum {
2757 MLXSW_REG_PPTB_MM_UM,
2758 MLXSW_REG_PPTB_MM_UNICAST,
2759 MLXSW_REG_PPTB_MM_MULTICAST,
2760 };
2761
2762 /* reg_pptb_mm
2763 * Mapping mode.
2764 * 0 - Map both unicast and multicast packets to the same buffer.
2765 * 1 - Map only unicast packets.
2766 * 2 - Map only multicast packets.
2767 * Access: Index
2768 *
2769 * Note: SwitchX-2 only supports the first option.
2770 */
2771 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
2772
2773 /* reg_pptb_local_port
2774 * Local port number.
2775 * Access: Index
2776 */
2777 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
2778
2779 /* reg_pptb_um
2780 * Enables the update of the untagged_buf field.
2781 * Access: RW
2782 */
2783 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
2784
2785 /* reg_pptb_pm
2786 * Enables the update of the prio_to_buff field.
2787 * Bit <i> is a flag for updating the mapping for switch priority <i>.
2788 * Access: RW
2789 */
2790 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
2791
2792 /* reg_pptb_prio_to_buff
2793 * Mapping of switch priority <i> to one of the allocated receive port
2794 * buffers.
2795 * Access: RW
2796 */
2797 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
2798
2799 /* reg_pptb_pm_msb
2800 * Enables the update of the prio_to_buff field.
2801 * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
2802 * Access: RW
2803 */
2804 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
2805
2806 /* reg_pptb_untagged_buff
2807 * Mapping of untagged frames to one of the allocated receive port buffers.
2808 * Access: RW
2809 *
2810 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
2811 * Spectrum, as it maps untagged packets based on the default switch priority.
2812 */
2813 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
2814
2815 /* reg_pptb_prio_to_buff_msb
2816 * Mapping of switch priority <i+8> to one of the allocated receive port
2817 * buffers.
2818 * Access: RW
2819 */
2820 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
2821
2822 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF
2823
2824 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
2825 {
2826 MLXSW_REG_ZERO(pptb, payload);
2827 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
2828 mlxsw_reg_pptb_local_port_set(payload, local_port);
2829 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
2830 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
2831 }
2832
2833 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
2834 u8 buff)
2835 {
2836 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
2837 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
2838 }
2839
2840 /* PBMC - Port Buffer Management Control Register
2841 * ----------------------------------------------
2842 * The PBMC register configures and retrieves the port packet buffer
2843 * allocation for different Prios, and the Pause threshold management.
2844 */
2845 #define MLXSW_REG_PBMC_ID 0x500C
2846 #define MLXSW_REG_PBMC_LEN 0x6C
2847
2848 static const struct mlxsw_reg_info mlxsw_reg_pbmc = {
2849 .id = MLXSW_REG_PBMC_ID,
2850 .len = MLXSW_REG_PBMC_LEN,
2851 };
2852
2853 /* reg_pbmc_local_port
2854 * Local port number.
2855 * Access: Index
2856 */
2857 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
2858
2859 /* reg_pbmc_xoff_timer_value
2860 * When device generates a pause frame, it uses this value as the pause
2861 * timer (time for the peer port to pause in quota-512 bit time).
2862 * Access: RW
2863 */
2864 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
2865
2866 /* reg_pbmc_xoff_refresh
2867 * The time before a new pause frame should be sent to refresh the pause RW
2868 * state. Using the same units as xoff_timer_value above (in quota-512 bit
2869 * time).
2870 * Access: RW
2871 */
2872 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
2873
2874 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
2875
2876 /* reg_pbmc_buf_lossy
2877 * The field indicates if the buffer is lossy.
2878 * 0 - Lossless
2879 * 1 - Lossy
2880 * Access: RW
2881 */
2882 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
2883
2884 /* reg_pbmc_buf_epsb
2885 * Eligible for Port Shared buffer.
2886 * If epsb is set, packets assigned to buffer are allowed to insert the port
2887 * shared buffer.
2888 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
2889 * Access: RW
2890 */
2891 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
2892
2893 /* reg_pbmc_buf_size
2894 * The part of the packet buffer array is allocated for the specific buffer.
2895 * Units are represented in cells.
2896 * Access: RW
2897 */
2898 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
2899
2900 /* reg_pbmc_buf_xoff_threshold
2901 * Once the amount of data in the buffer goes above this value, device
2902 * starts sending PFC frames for all priorities associated with the
2903 * buffer. Units are represented in cells. Reserved in case of lossy
2904 * buffer.
2905 * Access: RW
2906 *
2907 * Note: In Spectrum, reserved for buffer[9].
2908 */
2909 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
2910 0x08, 0x04, false);
2911
2912 /* reg_pbmc_buf_xon_threshold
2913 * When the amount of data in the buffer goes below this value, device
2914 * stops sending PFC frames for the priorities associated with the
2915 * buffer. Units are represented in cells. Reserved in case of lossy
2916 * buffer.
2917 * Access: RW
2918 *
2919 * Note: In Spectrum, reserved for buffer[9].
2920 */
2921 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
2922 0x08, 0x04, false);
2923
2924 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
2925 u16 xoff_timer_value, u16 xoff_refresh)
2926 {
2927 MLXSW_REG_ZERO(pbmc, payload);
2928 mlxsw_reg_pbmc_local_port_set(payload, local_port);
2929 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
2930 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
2931 }
2932
2933 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
2934 int buf_index,
2935 u16 size)
2936 {
2937 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
2938 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
2939 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
2940 }
2941
2942 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
2943 int buf_index, u16 size,
2944 u16 threshold)
2945 {
2946 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
2947 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
2948 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
2949 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
2950 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
2951 }
2952
2953 /* PSPA - Port Switch Partition Allocation
2954 * ---------------------------------------
2955 * Controls the association of a port with a switch partition and enables
2956 * configuring ports as stacking ports.
2957 */
2958 #define MLXSW_REG_PSPA_ID 0x500D
2959 #define MLXSW_REG_PSPA_LEN 0x8
2960
2961 static const struct mlxsw_reg_info mlxsw_reg_pspa = {
2962 .id = MLXSW_REG_PSPA_ID,
2963 .len = MLXSW_REG_PSPA_LEN,
2964 };
2965
2966 /* reg_pspa_swid
2967 * Switch partition ID.
2968 * Access: RW
2969 */
2970 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
2971
2972 /* reg_pspa_local_port
2973 * Local port number.
2974 * Access: Index
2975 */
2976 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
2977
2978 /* reg_pspa_sub_port
2979 * Virtual port within the local port. Set to 0 when virtual ports are
2980 * disabled on the local port.
2981 * Access: Index
2982 */
2983 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
2984
2985 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
2986 {
2987 MLXSW_REG_ZERO(pspa, payload);
2988 mlxsw_reg_pspa_swid_set(payload, swid);
2989 mlxsw_reg_pspa_local_port_set(payload, local_port);
2990 mlxsw_reg_pspa_sub_port_set(payload, 0);
2991 }
2992
2993 /* HTGT - Host Trap Group Table
2994 * ----------------------------
2995 * Configures the properties for forwarding to CPU.
2996 */
2997 #define MLXSW_REG_HTGT_ID 0x7002
2998 #define MLXSW_REG_HTGT_LEN 0x100
2999
3000 static const struct mlxsw_reg_info mlxsw_reg_htgt = {
3001 .id = MLXSW_REG_HTGT_ID,
3002 .len = MLXSW_REG_HTGT_LEN,
3003 };
3004
3005 /* reg_htgt_swid
3006 * Switch partition ID.
3007 * Access: Index
3008 */
3009 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
3010
3011 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */
3012
3013 /* reg_htgt_type
3014 * CPU path type.
3015 * Access: RW
3016 */
3017 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
3018
3019 enum mlxsw_reg_htgt_trap_group {
3020 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3021 MLXSW_REG_HTGT_TRAP_GROUP_RX,
3022 MLXSW_REG_HTGT_TRAP_GROUP_CTRL,
3023 };
3024
3025 /* reg_htgt_trap_group
3026 * Trap group number. User defined number specifying which trap groups
3027 * should be forwarded to the CPU. The mapping between trap IDs and trap
3028 * groups is configured using HPKT register.
3029 * Access: Index
3030 */
3031 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
3032
3033 enum {
3034 MLXSW_REG_HTGT_POLICER_DISABLE,
3035 MLXSW_REG_HTGT_POLICER_ENABLE,
3036 };
3037
3038 /* reg_htgt_pide
3039 * Enable policer ID specified using 'pid' field.
3040 * Access: RW
3041 */
3042 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
3043
3044 /* reg_htgt_pid
3045 * Policer ID for the trap group.
3046 * Access: RW
3047 */
3048 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
3049
3050 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
3051
3052 /* reg_htgt_mirror_action
3053 * Mirror action to use.
3054 * 0 - Trap to CPU.
3055 * 1 - Trap to CPU and mirror to a mirroring agent.
3056 * 2 - Mirror to a mirroring agent and do not trap to CPU.
3057 * Access: RW
3058 *
3059 * Note: Mirroring to a mirroring agent is only supported in Spectrum.
3060 */
3061 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
3062
3063 /* reg_htgt_mirroring_agent
3064 * Mirroring agent.
3065 * Access: RW
3066 */
3067 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
3068
3069 /* reg_htgt_priority
3070 * Trap group priority.
3071 * In case a packet matches multiple classification rules, the packet will
3072 * only be trapped once, based on the trap ID associated with the group (via
3073 * register HPKT) with the highest priority.
3074 * Supported values are 0-7, with 7 represnting the highest priority.
3075 * Access: RW
3076 *
3077 * Note: In SwitchX-2 this field is ignored and the priority value is replaced
3078 * by the 'trap_group' field.
3079 */
3080 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
3081
3082 /* reg_htgt_local_path_cpu_tclass
3083 * CPU ingress traffic class for the trap group.
3084 * Access: RW
3085 */
3086 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
3087
3088 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD 0x15
3089 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX 0x14
3090 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL 0x13
3091
3092 /* reg_htgt_local_path_rdq
3093 * Receive descriptor queue (RDQ) to use for the trap group.
3094 * Access: RW
3095 */
3096 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
3097
3098 static inline void mlxsw_reg_htgt_pack(char *payload,
3099 enum mlxsw_reg_htgt_trap_group group)
3100 {
3101 u8 swid, rdq;
3102
3103 MLXSW_REG_ZERO(htgt, payload);
3104 switch (group) {
3105 case MLXSW_REG_HTGT_TRAP_GROUP_EMAD:
3106 swid = MLXSW_PORT_SWID_ALL_SWIDS;
3107 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD;
3108 break;
3109 case MLXSW_REG_HTGT_TRAP_GROUP_RX:
3110 swid = 0;
3111 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX;
3112 break;
3113 case MLXSW_REG_HTGT_TRAP_GROUP_CTRL:
3114 swid = 0;
3115 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL;
3116 break;
3117 }
3118 mlxsw_reg_htgt_swid_set(payload, swid);
3119 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
3120 mlxsw_reg_htgt_trap_group_set(payload, group);
3121 mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE);
3122 mlxsw_reg_htgt_pid_set(payload, 0);
3123 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
3124 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
3125 mlxsw_reg_htgt_priority_set(payload, 0);
3126 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7);
3127 mlxsw_reg_htgt_local_path_rdq_set(payload, rdq);
3128 }
3129
3130 /* HPKT - Host Packet Trap
3131 * -----------------------
3132 * Configures trap IDs inside trap groups.
3133 */
3134 #define MLXSW_REG_HPKT_ID 0x7003
3135 #define MLXSW_REG_HPKT_LEN 0x10
3136
3137 static const struct mlxsw_reg_info mlxsw_reg_hpkt = {
3138 .id = MLXSW_REG_HPKT_ID,
3139 .len = MLXSW_REG_HPKT_LEN,
3140 };
3141
3142 enum {
3143 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
3144 MLXSW_REG_HPKT_ACK_REQUIRED,
3145 };
3146
3147 /* reg_hpkt_ack
3148 * Require acknowledgements from the host for events.
3149 * If set, then the device will wait for the event it sent to be acknowledged
3150 * by the host. This option is only relevant for event trap IDs.
3151 * Access: RW
3152 *
3153 * Note: Currently not supported by firmware.
3154 */
3155 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
3156
3157 enum mlxsw_reg_hpkt_action {
3158 MLXSW_REG_HPKT_ACTION_FORWARD,
3159 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
3160 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
3161 MLXSW_REG_HPKT_ACTION_DISCARD,
3162 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
3163 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
3164 };
3165
3166 /* reg_hpkt_action
3167 * Action to perform on packet when trapped.
3168 * 0 - No action. Forward to CPU based on switching rules.
3169 * 1 - Trap to CPU (CPU receives sole copy).
3170 * 2 - Mirror to CPU (CPU receives a replica of the packet).
3171 * 3 - Discard.
3172 * 4 - Soft discard (allow other traps to act on the packet).
3173 * 5 - Trap and soft discard (allow other traps to overwrite this trap).
3174 * Access: RW
3175 *
3176 * Note: Must be set to 0 (forward) for event trap IDs, as they are already
3177 * addressed to the CPU.
3178 */
3179 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
3180
3181 /* reg_hpkt_trap_group
3182 * Trap group to associate the trap with.
3183 * Access: RW
3184 */
3185 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
3186
3187 /* reg_hpkt_trap_id
3188 * Trap ID.
3189 * Access: Index
3190 *
3191 * Note: A trap ID can only be associated with a single trap group. The device
3192 * will associate the trap ID with the last trap group configured.
3193 */
3194 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
3195
3196 enum {
3197 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
3198 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
3199 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
3200 };
3201
3202 /* reg_hpkt_ctrl
3203 * Configure dedicated buffer resources for control packets.
3204 * 0 - Keep factory defaults.
3205 * 1 - Do not use control buffer for this trap ID.
3206 * 2 - Use control buffer for this trap ID.
3207 * Access: RW
3208 */
3209 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
3210
3211 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id)
3212 {
3213 enum mlxsw_reg_htgt_trap_group trap_group;
3214
3215 MLXSW_REG_ZERO(hpkt, payload);
3216 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
3217 mlxsw_reg_hpkt_action_set(payload, action);
3218 switch (trap_id) {
3219 case MLXSW_TRAP_ID_ETHEMAD:
3220 case MLXSW_TRAP_ID_PUDE:
3221 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_EMAD;
3222 break;
3223 default:
3224 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_RX;
3225 break;
3226 }
3227 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
3228 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
3229 mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT);
3230 }
3231
3232 /* RGCR - Router General Configuration Register
3233 * --------------------------------------------
3234 * The register is used for setting up the router configuration.
3235 */
3236 #define MLXSW_REG_RGCR_ID 0x8001
3237 #define MLXSW_REG_RGCR_LEN 0x28
3238
3239 static const struct mlxsw_reg_info mlxsw_reg_rgcr = {
3240 .id = MLXSW_REG_RGCR_ID,
3241 .len = MLXSW_REG_RGCR_LEN,
3242 };
3243
3244 /* reg_rgcr_ipv4_en
3245 * IPv4 router enable.
3246 * Access: RW
3247 */
3248 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
3249
3250 /* reg_rgcr_ipv6_en
3251 * IPv6 router enable.
3252 * Access: RW
3253 */
3254 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
3255
3256 /* reg_rgcr_max_router_interfaces
3257 * Defines the maximum number of active router interfaces for all virtual
3258 * routers.
3259 * Access: RW
3260 */
3261 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
3262
3263 /* reg_rgcr_usp
3264 * Update switch priority and packet color.
3265 * 0 - Preserve the value of Switch Priority and packet color.
3266 * 1 - Recalculate the value of Switch Priority and packet color.
3267 * Access: RW
3268 *
3269 * Note: Not supported by SwitchX and SwitchX-2.
3270 */
3271 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
3272
3273 /* reg_rgcr_pcp_rw
3274 * Indicates how to handle the pcp_rewrite_en value:
3275 * 0 - Preserve the value of pcp_rewrite_en.
3276 * 2 - Disable PCP rewrite.
3277 * 3 - Enable PCP rewrite.
3278 * Access: RW
3279 *
3280 * Note: Not supported by SwitchX and SwitchX-2.
3281 */
3282 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
3283
3284 /* reg_rgcr_activity_dis
3285 * Activity disable:
3286 * 0 - Activity will be set when an entry is hit (default).
3287 * 1 - Activity will not be set when an entry is hit.
3288 *
3289 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
3290 * (RALUE).
3291 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
3292 * Entry (RAUHT).
3293 * Bits 2:7 are reserved.
3294 * Access: RW
3295 *
3296 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
3297 */
3298 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
3299
3300 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en)
3301 {
3302 MLXSW_REG_ZERO(rgcr, payload);
3303 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
3304 }
3305
3306 /* RITR - Router Interface Table Register
3307 * --------------------------------------
3308 * The register is used to configure the router interface table.
3309 */
3310 #define MLXSW_REG_RITR_ID 0x8002
3311 #define MLXSW_REG_RITR_LEN 0x40
3312
3313 static const struct mlxsw_reg_info mlxsw_reg_ritr = {
3314 .id = MLXSW_REG_RITR_ID,
3315 .len = MLXSW_REG_RITR_LEN,
3316 };
3317
3318 /* reg_ritr_enable
3319 * Enables routing on the router interface.
3320 * Access: RW
3321 */
3322 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
3323
3324 /* reg_ritr_ipv4
3325 * IPv4 routing enable. Enables routing of IPv4 traffic on the router
3326 * interface.
3327 * Access: RW
3328 */
3329 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
3330
3331 /* reg_ritr_ipv6
3332 * IPv6 routing enable. Enables routing of IPv6 traffic on the router
3333 * interface.
3334 * Access: RW
3335 */
3336 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
3337
3338 enum mlxsw_reg_ritr_if_type {
3339 MLXSW_REG_RITR_VLAN_IF,
3340 MLXSW_REG_RITR_FID_IF,
3341 MLXSW_REG_RITR_SP_IF,
3342 };
3343
3344 /* reg_ritr_type
3345 * Router interface type.
3346 * 0 - VLAN interface.
3347 * 1 - FID interface.
3348 * 2 - Sub-port interface.
3349 * Access: RW
3350 */
3351 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
3352
3353 enum {
3354 MLXSW_REG_RITR_RIF_CREATE,
3355 MLXSW_REG_RITR_RIF_DEL,
3356 };
3357
3358 /* reg_ritr_op
3359 * Opcode:
3360 * 0 - Create or edit RIF.
3361 * 1 - Delete RIF.
3362 * Reserved for SwitchX-2. For Spectrum, editing of interface properties
3363 * is not supported. An interface must be deleted and re-created in order
3364 * to update properties.
3365 * Access: WO
3366 */
3367 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
3368
3369 /* reg_ritr_rif
3370 * Router interface index. A pointer to the Router Interface Table.
3371 * Access: Index
3372 */
3373 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
3374
3375 /* reg_ritr_ipv4_fe
3376 * IPv4 Forwarding Enable.
3377 * Enables routing of IPv4 traffic on the router interface. When disabled,
3378 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
3379 * Not supported in SwitchX-2.
3380 * Access: RW
3381 */
3382 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
3383
3384 /* reg_ritr_ipv6_fe
3385 * IPv6 Forwarding Enable.
3386 * Enables routing of IPv6 traffic on the router interface. When disabled,
3387 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
3388 * Not supported in SwitchX-2.
3389 * Access: RW
3390 */
3391 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
3392
3393 /* reg_ritr_lb_en
3394 * Loop-back filter enable for unicast packets.
3395 * If the flag is set then loop-back filter for unicast packets is
3396 * implemented on the RIF. Multicast packets are always subject to
3397 * loop-back filtering.
3398 * Access: RW
3399 */
3400 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
3401
3402 /* reg_ritr_virtual_router
3403 * Virtual router ID associated with the router interface.
3404 * Access: RW
3405 */
3406 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
3407
3408 /* reg_ritr_mtu
3409 * Router interface MTU.
3410 * Access: RW
3411 */
3412 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
3413
3414 /* reg_ritr_if_swid
3415 * Switch partition ID.
3416 * Access: RW
3417 */
3418 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
3419
3420 /* reg_ritr_if_mac
3421 * Router interface MAC address.
3422 * In Spectrum, all MAC addresses must have the same 38 MSBits.
3423 * Access: RW
3424 */
3425 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
3426
3427 /* VLAN Interface */
3428
3429 /* reg_ritr_vlan_if_vid
3430 * VLAN ID.
3431 * Access: RW
3432 */
3433 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
3434
3435 /* FID Interface */
3436
3437 /* reg_ritr_fid_if_fid
3438 * Filtering ID. Used to connect a bridge to the router. Only FIDs from
3439 * the vFID range are supported.
3440 * Access: RW
3441 */
3442 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
3443
3444 static inline void mlxsw_reg_ritr_fid_set(char *payload,
3445 enum mlxsw_reg_ritr_if_type rif_type,
3446 u16 fid)
3447 {
3448 if (rif_type == MLXSW_REG_RITR_FID_IF)
3449 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
3450 else
3451 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
3452 }
3453
3454 /* Sub-port Interface */
3455
3456 /* reg_ritr_sp_if_lag
3457 * LAG indication. When this bit is set the system_port field holds the
3458 * LAG identifier.
3459 * Access: RW
3460 */
3461 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
3462
3463 /* reg_ritr_sp_system_port
3464 * Port unique indentifier. When lag bit is set, this field holds the
3465 * lag_id in bits 0:9.
3466 * Access: RW
3467 */
3468 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
3469
3470 /* reg_ritr_sp_if_vid
3471 * VLAN ID.
3472 * Access: RW
3473 */
3474 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
3475
3476 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
3477 {
3478 MLXSW_REG_ZERO(ritr, payload);
3479 mlxsw_reg_ritr_rif_set(payload, rif);
3480 }
3481
3482 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
3483 u16 system_port, u16 vid)
3484 {
3485 mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
3486 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
3487 mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
3488 }
3489
3490 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
3491 enum mlxsw_reg_ritr_if_type type,
3492 u16 rif, u16 mtu, const char *mac)
3493 {
3494 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
3495
3496 MLXSW_REG_ZERO(ritr, payload);
3497 mlxsw_reg_ritr_enable_set(payload, enable);
3498 mlxsw_reg_ritr_ipv4_set(payload, 1);
3499 mlxsw_reg_ritr_type_set(payload, type);
3500 mlxsw_reg_ritr_op_set(payload, op);
3501 mlxsw_reg_ritr_rif_set(payload, rif);
3502 mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
3503 mlxsw_reg_ritr_lb_en_set(payload, 1);
3504 mlxsw_reg_ritr_mtu_set(payload, mtu);
3505 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
3506 }
3507
3508 /* RATR - Router Adjacency Table Register
3509 * --------------------------------------
3510 * The RATR register is used to configure the Router Adjacency (next-hop)
3511 * Table.
3512 */
3513 #define MLXSW_REG_RATR_ID 0x8008
3514 #define MLXSW_REG_RATR_LEN 0x2C
3515
3516 static const struct mlxsw_reg_info mlxsw_reg_ratr = {
3517 .id = MLXSW_REG_RATR_ID,
3518 .len = MLXSW_REG_RATR_LEN,
3519 };
3520
3521 enum mlxsw_reg_ratr_op {
3522 /* Read */
3523 MLXSW_REG_RATR_OP_QUERY_READ = 0,
3524 /* Read and clear activity */
3525 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
3526 /* Write Adjacency entry */
3527 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
3528 /* Write Adjacency entry only if the activity is cleared.
3529 * The write may not succeed if the activity is set. There is not
3530 * direct feedback if the write has succeeded or not, however
3531 * the get will reveal the actual entry (SW can compare the get
3532 * response to the set command).
3533 */
3534 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
3535 };
3536
3537 /* reg_ratr_op
3538 * Note that Write operation may also be used for updating
3539 * counter_set_type and counter_index. In this case all other
3540 * fields must not be updated.
3541 * Access: OP
3542 */
3543 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
3544
3545 /* reg_ratr_v
3546 * Valid bit. Indicates if the adjacency entry is valid.
3547 * Note: the device may need some time before reusing an invalidated
3548 * entry. During this time the entry can not be reused. It is
3549 * recommended to use another entry before reusing an invalidated
3550 * entry (e.g. software can put it at the end of the list for
3551 * reusing). Trying to access an invalidated entry not yet cleared
3552 * by the device results with failure indicating "Try Again" status.
3553 * When valid is '0' then egress_router_interface,trap_action,
3554 * adjacency_parameters and counters are reserved
3555 * Access: RW
3556 */
3557 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
3558
3559 /* reg_ratr_a
3560 * Activity. Set for new entries. Set if a packet lookup has hit on
3561 * the specific entry. To clear the a bit, use "clear activity".
3562 * Access: RO
3563 */
3564 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
3565
3566 /* reg_ratr_adjacency_index_low
3567 * Bits 15:0 of index into the adjacency table.
3568 * For SwitchX and SwitchX-2, the adjacency table is linear and
3569 * used for adjacency entries only.
3570 * For Spectrum, the index is to the KVD linear.
3571 * Access: Index
3572 */
3573 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
3574
3575 /* reg_ratr_egress_router_interface
3576 * Range is 0 .. cap_max_router_interfaces - 1
3577 * Access: RW
3578 */
3579 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
3580
3581 enum mlxsw_reg_ratr_trap_action {
3582 MLXSW_REG_RATR_TRAP_ACTION_NOP,
3583 MLXSW_REG_RATR_TRAP_ACTION_TRAP,
3584 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
3585 MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
3586 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
3587 };
3588
3589 /* reg_ratr_trap_action
3590 * see mlxsw_reg_ratr_trap_action
3591 * Access: RW
3592 */
3593 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
3594
3595 enum mlxsw_reg_ratr_trap_id {
3596 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0 = 0,
3597 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1 = 1,
3598 };
3599
3600 /* reg_ratr_adjacency_index_high
3601 * Bits 23:16 of the adjacency_index.
3602 * Access: Index
3603 */
3604 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
3605
3606 /* reg_ratr_trap_id
3607 * Trap ID to be reported to CPU.
3608 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
3609 * For trap_action of NOP, MIRROR and DISCARD_ERROR
3610 * Access: RW
3611 */
3612 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
3613
3614 /* reg_ratr_eth_destination_mac
3615 * MAC address of the destination next-hop.
3616 * Access: RW
3617 */
3618 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
3619
3620 static inline void
3621 mlxsw_reg_ratr_pack(char *payload,
3622 enum mlxsw_reg_ratr_op op, bool valid,
3623 u32 adjacency_index, u16 egress_rif)
3624 {
3625 MLXSW_REG_ZERO(ratr, payload);
3626 mlxsw_reg_ratr_op_set(payload, op);
3627 mlxsw_reg_ratr_v_set(payload, valid);
3628 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
3629 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
3630 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
3631 }
3632
3633 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
3634 const char *dest_mac)
3635 {
3636 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
3637 }
3638
3639 /* RALTA - Router Algorithmic LPM Tree Allocation Register
3640 * -------------------------------------------------------
3641 * RALTA is used to allocate the LPM trees of the SHSPM method.
3642 */
3643 #define MLXSW_REG_RALTA_ID 0x8010
3644 #define MLXSW_REG_RALTA_LEN 0x04
3645
3646 static const struct mlxsw_reg_info mlxsw_reg_ralta = {
3647 .id = MLXSW_REG_RALTA_ID,
3648 .len = MLXSW_REG_RALTA_LEN,
3649 };
3650
3651 /* reg_ralta_op
3652 * opcode (valid for Write, must be 0 on Read)
3653 * 0 - allocate a tree
3654 * 1 - deallocate a tree
3655 * Access: OP
3656 */
3657 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
3658
3659 enum mlxsw_reg_ralxx_protocol {
3660 MLXSW_REG_RALXX_PROTOCOL_IPV4,
3661 MLXSW_REG_RALXX_PROTOCOL_IPV6,
3662 };
3663
3664 /* reg_ralta_protocol
3665 * Protocol.
3666 * Deallocation opcode: Reserved.
3667 * Access: RW
3668 */
3669 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
3670
3671 /* reg_ralta_tree_id
3672 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing
3673 * the tree identifier (managed by software).
3674 * Note that tree_id 0 is allocated for a default-route tree.
3675 * Access: Index
3676 */
3677 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
3678
3679 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
3680 enum mlxsw_reg_ralxx_protocol protocol,
3681 u8 tree_id)
3682 {
3683 MLXSW_REG_ZERO(ralta, payload);
3684 mlxsw_reg_ralta_op_set(payload, !alloc);
3685 mlxsw_reg_ralta_protocol_set(payload, protocol);
3686 mlxsw_reg_ralta_tree_id_set(payload, tree_id);
3687 }
3688
3689 /* RALST - Router Algorithmic LPM Structure Tree Register
3690 * ------------------------------------------------------
3691 * RALST is used to set and query the structure of an LPM tree.
3692 * The structure of the tree must be sorted as a sorted binary tree, while
3693 * each node is a bin that is tagged as the length of the prefixes the lookup
3694 * will refer to. Therefore, bin X refers to a set of entries with prefixes
3695 * of X bits to match with the destination address. The bin 0 indicates
3696 * the default action, when there is no match of any prefix.
3697 */
3698 #define MLXSW_REG_RALST_ID 0x8011
3699 #define MLXSW_REG_RALST_LEN 0x104
3700
3701 static const struct mlxsw_reg_info mlxsw_reg_ralst = {
3702 .id = MLXSW_REG_RALST_ID,
3703 .len = MLXSW_REG_RALST_LEN,
3704 };
3705
3706 /* reg_ralst_root_bin
3707 * The bin number of the root bin.
3708 * 0<root_bin=<(length of IP address)
3709 * For a default-route tree configure 0xff
3710 * Access: RW
3711 */
3712 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
3713
3714 /* reg_ralst_tree_id
3715 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
3716 * Access: Index
3717 */
3718 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
3719
3720 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
3721 #define MLXSW_REG_RALST_BIN_OFFSET 0x04
3722 #define MLXSW_REG_RALST_BIN_COUNT 128
3723
3724 /* reg_ralst_left_child_bin
3725 * Holding the children of the bin according to the stored tree's structure.
3726 * For trees composed of less than 4 blocks, the bins in excess are reserved.
3727 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
3728 * Access: RW
3729 */
3730 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
3731
3732 /* reg_ralst_right_child_bin
3733 * Holding the children of the bin according to the stored tree's structure.
3734 * For trees composed of less than 4 blocks, the bins in excess are reserved.
3735 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
3736 * Access: RW
3737 */
3738 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
3739 false);
3740
3741 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
3742 {
3743 MLXSW_REG_ZERO(ralst, payload);
3744
3745 /* Initialize all bins to have no left or right child */
3746 memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
3747 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
3748
3749 mlxsw_reg_ralst_root_bin_set(payload, root_bin);
3750 mlxsw_reg_ralst_tree_id_set(payload, tree_id);
3751 }
3752
3753 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
3754 u8 left_child_bin,
3755 u8 right_child_bin)
3756 {
3757 int bin_index = bin_number - 1;
3758
3759 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
3760 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
3761 right_child_bin);
3762 }
3763
3764 /* RALTB - Router Algorithmic LPM Tree Binding Register
3765 * ----------------------------------------------------
3766 * RALTB is used to bind virtual router and protocol to an allocated LPM tree.
3767 */
3768 #define MLXSW_REG_RALTB_ID 0x8012
3769 #define MLXSW_REG_RALTB_LEN 0x04
3770
3771 static const struct mlxsw_reg_info mlxsw_reg_raltb = {
3772 .id = MLXSW_REG_RALTB_ID,
3773 .len = MLXSW_REG_RALTB_LEN,
3774 };
3775
3776 /* reg_raltb_virtual_router
3777 * Virtual Router ID
3778 * Range is 0..cap_max_virtual_routers-1
3779 * Access: Index
3780 */
3781 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
3782
3783 /* reg_raltb_protocol
3784 * Protocol.
3785 * Access: Index
3786 */
3787 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
3788
3789 /* reg_raltb_tree_id
3790 * Tree to be used for the {virtual_router, protocol}
3791 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
3792 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0.
3793 * Access: RW
3794 */
3795 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
3796
3797 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
3798 enum mlxsw_reg_ralxx_protocol protocol,
3799 u8 tree_id)
3800 {
3801 MLXSW_REG_ZERO(raltb, payload);
3802 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
3803 mlxsw_reg_raltb_protocol_set(payload, protocol);
3804 mlxsw_reg_raltb_tree_id_set(payload, tree_id);
3805 }
3806
3807 /* RALUE - Router Algorithmic LPM Unicast Entry Register
3808 * -----------------------------------------------------
3809 * RALUE is used to configure and query LPM entries that serve
3810 * the Unicast protocols.
3811 */
3812 #define MLXSW_REG_RALUE_ID 0x8013
3813 #define MLXSW_REG_RALUE_LEN 0x38
3814
3815 static const struct mlxsw_reg_info mlxsw_reg_ralue = {
3816 .id = MLXSW_REG_RALUE_ID,
3817 .len = MLXSW_REG_RALUE_LEN,
3818 };
3819
3820 /* reg_ralue_protocol
3821 * Protocol.
3822 * Access: Index
3823 */
3824 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
3825
3826 enum mlxsw_reg_ralue_op {
3827 /* Read operation. If entry doesn't exist, the operation fails. */
3828 MLXSW_REG_RALUE_OP_QUERY_READ = 0,
3829 /* Clear on read operation. Used to read entry and
3830 * clear Activity bit.
3831 */
3832 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
3833 /* Write operation. Used to write a new entry to the table. All RW
3834 * fields are written for new entry. Activity bit is set
3835 * for new entries.
3836 */
3837 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
3838 /* Update operation. Used to update an existing route entry and
3839 * only update the RW fields that are detailed in the field
3840 * op_u_mask. If entry doesn't exist, the operation fails.
3841 */
3842 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
3843 /* Clear activity. The Activity bit (the field a) is cleared
3844 * for the entry.
3845 */
3846 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
3847 /* Delete operation. Used to delete an existing entry. If entry
3848 * doesn't exist, the operation fails.
3849 */
3850 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
3851 };
3852
3853 /* reg_ralue_op
3854 * Operation.
3855 * Access: OP
3856 */
3857 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
3858
3859 /* reg_ralue_a
3860 * Activity. Set for new entries. Set if a packet lookup has hit on the
3861 * specific entry, only if the entry is a route. To clear the a bit, use
3862 * "clear activity" op.
3863 * Enabled by activity_dis in RGCR
3864 * Access: RO
3865 */
3866 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
3867
3868 /* reg_ralue_virtual_router
3869 * Virtual Router ID
3870 * Range is 0..cap_max_virtual_routers-1
3871 * Access: Index
3872 */
3873 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
3874
3875 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0)
3876 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1)
3877 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2)
3878
3879 /* reg_ralue_op_u_mask
3880 * opcode update mask.
3881 * On read operation, this field is reserved.
3882 * This field is valid for update opcode, otherwise - reserved.
3883 * This field is a bitmask of the fields that should be updated.
3884 * Access: WO
3885 */
3886 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
3887
3888 /* reg_ralue_prefix_len
3889 * Number of bits in the prefix of the LPM route.
3890 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes
3891 * two entries in the physical HW table.
3892 * Access: Index
3893 */
3894 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
3895
3896 /* reg_ralue_dip*
3897 * The prefix of the route or of the marker that the object of the LPM
3898 * is compared with. The most significant bits of the dip are the prefix.
3899 * The list significant bits must be '0' if the prefix_len is smaller
3900 * than 128 for IPv6 or smaller than 32 for IPv4.
3901 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.
3902 * Access: Index
3903 */
3904 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
3905
3906 enum mlxsw_reg_ralue_entry_type {
3907 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
3908 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
3909 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
3910 };
3911
3912 /* reg_ralue_entry_type
3913 * Entry type.
3914 * Note - for Marker entries, the action_type and action fields are reserved.
3915 * Access: RW
3916 */
3917 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
3918
3919 /* reg_ralue_bmp_len
3920 * The best match prefix length in the case that there is no match for
3921 * longer prefixes.
3922 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
3923 * Note for any update operation with entry_type modification this
3924 * field must be set.
3925 * Access: RW
3926 */
3927 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
3928
3929 enum mlxsw_reg_ralue_action_type {
3930 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
3931 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
3932 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
3933 };
3934
3935 /* reg_ralue_action_type
3936 * Action Type
3937 * Indicates how the IP address is connected.
3938 * It can be connected to a local subnet through local_erif or can be
3939 * on a remote subnet connected through a next-hop router,
3940 * or transmitted to the CPU.
3941 * Reserved when entry_type = MARKER_ENTRY
3942 * Access: RW
3943 */
3944 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
3945
3946 enum mlxsw_reg_ralue_trap_action {
3947 MLXSW_REG_RALUE_TRAP_ACTION_NOP,
3948 MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
3949 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
3950 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
3951 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
3952 };
3953
3954 /* reg_ralue_trap_action
3955 * Trap action.
3956 * For IP2ME action, only NOP and MIRROR are possible.
3957 * Access: RW
3958 */
3959 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
3960
3961 /* reg_ralue_trap_id
3962 * Trap ID to be reported to CPU.
3963 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1.
3964 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.
3965 * Access: RW
3966 */
3967 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
3968
3969 /* reg_ralue_adjacency_index
3970 * Points to the first entry of the group-based ECMP.
3971 * Only relevant in case of REMOTE action.
3972 * Access: RW
3973 */
3974 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
3975
3976 /* reg_ralue_ecmp_size
3977 * Amount of sequential entries starting
3978 * from the adjacency_index (the number of ECMPs).
3979 * The valid range is 1-64, 512, 1024, 2048 and 4096.
3980 * Reserved when trap_action is TRAP or DISCARD_ERROR.
3981 * Only relevant in case of REMOTE action.
3982 * Access: RW
3983 */
3984 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
3985
3986 /* reg_ralue_local_erif
3987 * Egress Router Interface.
3988 * Only relevant in case of LOCAL action.
3989 * Access: RW
3990 */
3991 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
3992
3993 /* reg_ralue_v
3994 * Valid bit for the tunnel_ptr field.
3995 * If valid = 0 then trap to CPU as IP2ME trap ID.
3996 * If valid = 1 and the packet format allows NVE or IPinIP tunnel
3997 * decapsulation then tunnel decapsulation is done.
3998 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel
3999 * decapsulation then trap as IP2ME trap ID.
4000 * Only relevant in case of IP2ME action.
4001 * Access: RW
4002 */
4003 MLXSW_ITEM32(reg, ralue, v, 0x24, 31, 1);
4004
4005 /* reg_ralue_tunnel_ptr
4006 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation.
4007 * For Spectrum, pointer to KVD Linear.
4008 * Only relevant in case of IP2ME action.
4009 * Access: RW
4010 */
4011 MLXSW_ITEM32(reg, ralue, tunnel_ptr, 0x24, 0, 24);
4012
4013 static inline void mlxsw_reg_ralue_pack(char *payload,
4014 enum mlxsw_reg_ralxx_protocol protocol,
4015 enum mlxsw_reg_ralue_op op,
4016 u16 virtual_router, u8 prefix_len)
4017 {
4018 MLXSW_REG_ZERO(ralue, payload);
4019 mlxsw_reg_ralue_protocol_set(payload, protocol);
4020 mlxsw_reg_ralue_op_set(payload, op);
4021 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
4022 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
4023 mlxsw_reg_ralue_entry_type_set(payload,
4024 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
4025 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
4026 }
4027
4028 static inline void mlxsw_reg_ralue_pack4(char *payload,
4029 enum mlxsw_reg_ralxx_protocol protocol,
4030 enum mlxsw_reg_ralue_op op,
4031 u16 virtual_router, u8 prefix_len,
4032 u32 dip)
4033 {
4034 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
4035 mlxsw_reg_ralue_dip4_set(payload, dip);
4036 }
4037
4038 static inline void
4039 mlxsw_reg_ralue_act_remote_pack(char *payload,
4040 enum mlxsw_reg_ralue_trap_action trap_action,
4041 u16 trap_id, u32 adjacency_index, u16 ecmp_size)
4042 {
4043 mlxsw_reg_ralue_action_type_set(payload,
4044 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
4045 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
4046 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
4047 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
4048 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
4049 }
4050
4051 static inline void
4052 mlxsw_reg_ralue_act_local_pack(char *payload,
4053 enum mlxsw_reg_ralue_trap_action trap_action,
4054 u16 trap_id, u16 local_erif)
4055 {
4056 mlxsw_reg_ralue_action_type_set(payload,
4057 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
4058 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
4059 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
4060 mlxsw_reg_ralue_local_erif_set(payload, local_erif);
4061 }
4062
4063 static inline void
4064 mlxsw_reg_ralue_act_ip2me_pack(char *payload)
4065 {
4066 mlxsw_reg_ralue_action_type_set(payload,
4067 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
4068 }
4069
4070 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register
4071 * ----------------------------------------------------------
4072 * The RAUHT register is used to configure and query the Unicast Host table in
4073 * devices that implement the Algorithmic LPM.
4074 */
4075 #define MLXSW_REG_RAUHT_ID 0x8014
4076 #define MLXSW_REG_RAUHT_LEN 0x74
4077
4078 static const struct mlxsw_reg_info mlxsw_reg_rauht = {
4079 .id = MLXSW_REG_RAUHT_ID,
4080 .len = MLXSW_REG_RAUHT_LEN,
4081 };
4082
4083 enum mlxsw_reg_rauht_type {
4084 MLXSW_REG_RAUHT_TYPE_IPV4,
4085 MLXSW_REG_RAUHT_TYPE_IPV6,
4086 };
4087
4088 /* reg_rauht_type
4089 * Access: Index
4090 */
4091 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
4092
4093 enum mlxsw_reg_rauht_op {
4094 MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
4095 /* Read operation */
4096 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
4097 /* Clear on read operation. Used to read entry and clear
4098 * activity bit.
4099 */
4100 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
4101 /* Add. Used to write a new entry to the table. All R/W fields are
4102 * relevant for new entry. Activity bit is set for new entries.
4103 */
4104 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
4105 /* Update action. Used to update an existing route entry and
4106 * only update the following fields:
4107 * trap_action, trap_id, mac, counter_set_type, counter_index
4108 */
4109 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
4110 /* Clear activity. A bit is cleared for the entry. */
4111 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
4112 /* Delete entry */
4113 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
4114 /* Delete all host entries on a RIF. In this command, dip
4115 * field is reserved.
4116 */
4117 };
4118
4119 /* reg_rauht_op
4120 * Access: OP
4121 */
4122 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
4123
4124 /* reg_rauht_a
4125 * Activity. Set for new entries. Set if a packet lookup has hit on
4126 * the specific entry.
4127 * To clear the a bit, use "clear activity" op.
4128 * Enabled by activity_dis in RGCR
4129 * Access: RO
4130 */
4131 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
4132
4133 /* reg_rauht_rif
4134 * Router Interface
4135 * Access: Index
4136 */
4137 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
4138
4139 /* reg_rauht_dip*
4140 * Destination address.
4141 * Access: Index
4142 */
4143 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
4144
4145 enum mlxsw_reg_rauht_trap_action {
4146 MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
4147 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
4148 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
4149 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
4150 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
4151 };
4152
4153 /* reg_rauht_trap_action
4154 * Access: RW
4155 */
4156 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
4157
4158 enum mlxsw_reg_rauht_trap_id {
4159 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
4160 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
4161 };
4162
4163 /* reg_rauht_trap_id
4164 * Trap ID to be reported to CPU.
4165 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
4166 * For trap_action of NOP, MIRROR and DISCARD_ERROR,
4167 * trap_id is reserved.
4168 * Access: RW
4169 */
4170 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
4171
4172 /* reg_rauht_counter_set_type
4173 * Counter set type for flow counters
4174 * Access: RW
4175 */
4176 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
4177
4178 /* reg_rauht_counter_index
4179 * Counter index for flow counters
4180 * Access: RW
4181 */
4182 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
4183
4184 /* reg_rauht_mac
4185 * MAC address.
4186 * Access: RW
4187 */
4188 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
4189
4190 static inline void mlxsw_reg_rauht_pack(char *payload,
4191 enum mlxsw_reg_rauht_op op, u16 rif,
4192 const char *mac)
4193 {
4194 MLXSW_REG_ZERO(rauht, payload);
4195 mlxsw_reg_rauht_op_set(payload, op);
4196 mlxsw_reg_rauht_rif_set(payload, rif);
4197 mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
4198 }
4199
4200 static inline void mlxsw_reg_rauht_pack4(char *payload,
4201 enum mlxsw_reg_rauht_op op, u16 rif,
4202 const char *mac, u32 dip)
4203 {
4204 mlxsw_reg_rauht_pack(payload, op, rif, mac);
4205 mlxsw_reg_rauht_dip4_set(payload, dip);
4206 }
4207
4208 /* RALEU - Router Algorithmic LPM ECMP Update Register
4209 * ---------------------------------------------------
4210 * The register enables updating the ECMP section in the action for multiple
4211 * LPM Unicast entries in a single operation. The update is executed to
4212 * all entries of a {virtual router, protocol} tuple using the same ECMP group.
4213 */
4214 #define MLXSW_REG_RALEU_ID 0x8015
4215 #define MLXSW_REG_RALEU_LEN 0x28
4216
4217 static const struct mlxsw_reg_info mlxsw_reg_raleu = {
4218 .id = MLXSW_REG_RALEU_ID,
4219 .len = MLXSW_REG_RALEU_LEN,
4220 };
4221
4222 /* reg_raleu_protocol
4223 * Protocol.
4224 * Access: Index
4225 */
4226 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
4227
4228 /* reg_raleu_virtual_router
4229 * Virtual Router ID
4230 * Range is 0..cap_max_virtual_routers-1
4231 * Access: Index
4232 */
4233 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
4234
4235 /* reg_raleu_adjacency_index
4236 * Adjacency Index used for matching on the existing entries.
4237 * Access: Index
4238 */
4239 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
4240
4241 /* reg_raleu_ecmp_size
4242 * ECMP Size used for matching on the existing entries.
4243 * Access: Index
4244 */
4245 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
4246
4247 /* reg_raleu_new_adjacency_index
4248 * New Adjacency Index.
4249 * Access: WO
4250 */
4251 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
4252
4253 /* reg_raleu_new_ecmp_size
4254 * New ECMP Size.
4255 * Access: WO
4256 */
4257 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
4258
4259 static inline void mlxsw_reg_raleu_pack(char *payload,
4260 enum mlxsw_reg_ralxx_protocol protocol,
4261 u16 virtual_router,
4262 u32 adjacency_index, u16 ecmp_size,
4263 u32 new_adjacency_index,
4264 u16 new_ecmp_size)
4265 {
4266 MLXSW_REG_ZERO(raleu, payload);
4267 mlxsw_reg_raleu_protocol_set(payload, protocol);
4268 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
4269 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
4270 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
4271 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
4272 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
4273 }
4274
4275 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register
4276 * ----------------------------------------------------------------
4277 * The RAUHTD register allows dumping entries from the Router Unicast Host
4278 * Table. For a given session an entry is dumped no more than one time. The
4279 * first RAUHTD access after reset is a new session. A session ends when the
4280 * num_rec response is smaller than num_rec request or for IPv4 when the
4281 * num_entries is smaller than 4. The clear activity affect the current session
4282 * or the last session if a new session has not started.
4283 */
4284 #define MLXSW_REG_RAUHTD_ID 0x8018
4285 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20
4286 #define MLXSW_REG_RAUHTD_REC_LEN 0x20
4287 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
4288 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
4289 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
4290 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
4291
4292 static const struct mlxsw_reg_info mlxsw_reg_rauhtd = {
4293 .id = MLXSW_REG_RAUHTD_ID,
4294 .len = MLXSW_REG_RAUHTD_LEN,
4295 };
4296
4297 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
4298 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
4299
4300 /* reg_rauhtd_filter_fields
4301 * if a bit is '0' then the relevant field is ignored and dump is done
4302 * regardless of the field value
4303 * Bit0 - filter by activity: entry_a
4304 * Bit3 - filter by entry rip: entry_rif
4305 * Access: Index
4306 */
4307 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
4308
4309 enum mlxsw_reg_rauhtd_op {
4310 MLXSW_REG_RAUHTD_OP_DUMP,
4311 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
4312 };
4313
4314 /* reg_rauhtd_op
4315 * Access: OP
4316 */
4317 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
4318
4319 /* reg_rauhtd_num_rec
4320 * At request: number of records requested
4321 * At response: number of records dumped
4322 * For IPv4, each record has 4 entries at request and up to 4 entries
4323 * at response
4324 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM
4325 * Access: Index
4326 */
4327 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
4328
4329 /* reg_rauhtd_entry_a
4330 * Dump only if activity has value of entry_a
4331 * Reserved if filter_fields bit0 is '0'
4332 * Access: Index
4333 */
4334 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
4335
4336 enum mlxsw_reg_rauhtd_type {
4337 MLXSW_REG_RAUHTD_TYPE_IPV4,
4338 MLXSW_REG_RAUHTD_TYPE_IPV6,
4339 };
4340
4341 /* reg_rauhtd_type
4342 * Dump only if record type is:
4343 * 0 - IPv4
4344 * 1 - IPv6
4345 * Access: Index
4346 */
4347 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
4348
4349 /* reg_rauhtd_entry_rif
4350 * Dump only if RIF has value of entry_rif
4351 * Reserved if filter_fields bit3 is '0'
4352 * Access: Index
4353 */
4354 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
4355
4356 static inline void mlxsw_reg_rauhtd_pack(char *payload,
4357 enum mlxsw_reg_rauhtd_type type)
4358 {
4359 MLXSW_REG_ZERO(rauhtd, payload);
4360 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
4361 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
4362 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
4363 mlxsw_reg_rauhtd_entry_a_set(payload, 1);
4364 mlxsw_reg_rauhtd_type_set(payload, type);
4365 }
4366
4367 /* reg_rauhtd_ipv4_rec_num_entries
4368 * Number of valid entries in this record:
4369 * 0 - 1 valid entry
4370 * 1 - 2 valid entries
4371 * 2 - 3 valid entries
4372 * 3 - 4 valid entries
4373 * Access: RO
4374 */
4375 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
4376 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
4377 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
4378
4379 /* reg_rauhtd_rec_type
4380 * Record type.
4381 * 0 - IPv4
4382 * 1 - IPv6
4383 * Access: RO
4384 */
4385 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
4386 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
4387
4388 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
4389
4390 /* reg_rauhtd_ipv4_ent_a
4391 * Activity. Set for new entries. Set if a packet lookup has hit on the
4392 * specific entry.
4393 * Access: RO
4394 */
4395 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
4396 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
4397
4398 /* reg_rauhtd_ipv4_ent_rif
4399 * Router interface.
4400 * Access: RO
4401 */
4402 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
4403 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
4404
4405 /* reg_rauhtd_ipv4_ent_dip
4406 * Destination IPv4 address.
4407 * Access: RO
4408 */
4409 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
4410 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
4411
4412 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
4413 int ent_index, u16 *p_rif,
4414 u32 *p_dip)
4415 {
4416 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
4417 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
4418 }
4419
4420 /* MFCR - Management Fan Control Register
4421 * --------------------------------------
4422 * This register controls the settings of the Fan Speed PWM mechanism.
4423 */
4424 #define MLXSW_REG_MFCR_ID 0x9001
4425 #define MLXSW_REG_MFCR_LEN 0x08
4426
4427 static const struct mlxsw_reg_info mlxsw_reg_mfcr = {
4428 .id = MLXSW_REG_MFCR_ID,
4429 .len = MLXSW_REG_MFCR_LEN,
4430 };
4431
4432 enum mlxsw_reg_mfcr_pwm_frequency {
4433 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
4434 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
4435 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
4436 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
4437 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
4438 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
4439 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
4440 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
4441 };
4442
4443 /* reg_mfcr_pwm_frequency
4444 * Controls the frequency of the PWM signal.
4445 * Access: RW
4446 */
4447 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 6);
4448
4449 #define MLXSW_MFCR_TACHOS_MAX 10
4450
4451 /* reg_mfcr_tacho_active
4452 * Indicates which of the tachometer is active (bit per tachometer).
4453 * Access: RO
4454 */
4455 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
4456
4457 #define MLXSW_MFCR_PWMS_MAX 5
4458
4459 /* reg_mfcr_pwm_active
4460 * Indicates which of the PWM control is active (bit per PWM).
4461 * Access: RO
4462 */
4463 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
4464
4465 static inline void
4466 mlxsw_reg_mfcr_pack(char *payload,
4467 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
4468 {
4469 MLXSW_REG_ZERO(mfcr, payload);
4470 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
4471 }
4472
4473 static inline void
4474 mlxsw_reg_mfcr_unpack(char *payload,
4475 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
4476 u16 *p_tacho_active, u8 *p_pwm_active)
4477 {
4478 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
4479 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
4480 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
4481 }
4482
4483 /* MFSC - Management Fan Speed Control Register
4484 * --------------------------------------------
4485 * This register controls the settings of the Fan Speed PWM mechanism.
4486 */
4487 #define MLXSW_REG_MFSC_ID 0x9002
4488 #define MLXSW_REG_MFSC_LEN 0x08
4489
4490 static const struct mlxsw_reg_info mlxsw_reg_mfsc = {
4491 .id = MLXSW_REG_MFSC_ID,
4492 .len = MLXSW_REG_MFSC_LEN,
4493 };
4494
4495 /* reg_mfsc_pwm
4496 * Fan pwm to control / monitor.
4497 * Access: Index
4498 */
4499 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
4500
4501 /* reg_mfsc_pwm_duty_cycle
4502 * Controls the duty cycle of the PWM. Value range from 0..255 to
4503 * represent duty cycle of 0%...100%.
4504 * Access: RW
4505 */
4506 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
4507
4508 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
4509 u8 pwm_duty_cycle)
4510 {
4511 MLXSW_REG_ZERO(mfsc, payload);
4512 mlxsw_reg_mfsc_pwm_set(payload, pwm);
4513 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
4514 }
4515
4516 /* MFSM - Management Fan Speed Measurement
4517 * ---------------------------------------
4518 * This register controls the settings of the Tacho measurements and
4519 * enables reading the Tachometer measurements.
4520 */
4521 #define MLXSW_REG_MFSM_ID 0x9003
4522 #define MLXSW_REG_MFSM_LEN 0x08
4523
4524 static const struct mlxsw_reg_info mlxsw_reg_mfsm = {
4525 .id = MLXSW_REG_MFSM_ID,
4526 .len = MLXSW_REG_MFSM_LEN,
4527 };
4528
4529 /* reg_mfsm_tacho
4530 * Fan tachometer index.
4531 * Access: Index
4532 */
4533 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
4534
4535 /* reg_mfsm_rpm
4536 * Fan speed (round per minute).
4537 * Access: RO
4538 */
4539 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
4540
4541 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
4542 {
4543 MLXSW_REG_ZERO(mfsm, payload);
4544 mlxsw_reg_mfsm_tacho_set(payload, tacho);
4545 }
4546
4547 /* MTCAP - Management Temperature Capabilities
4548 * -------------------------------------------
4549 * This register exposes the capabilities of the device and
4550 * system temperature sensing.
4551 */
4552 #define MLXSW_REG_MTCAP_ID 0x9009
4553 #define MLXSW_REG_MTCAP_LEN 0x08
4554
4555 static const struct mlxsw_reg_info mlxsw_reg_mtcap = {
4556 .id = MLXSW_REG_MTCAP_ID,
4557 .len = MLXSW_REG_MTCAP_LEN,
4558 };
4559
4560 /* reg_mtcap_sensor_count
4561 * Number of sensors supported by the device.
4562 * This includes the QSFP module sensors (if exists in the QSFP module).
4563 * Access: RO
4564 */
4565 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
4566
4567 /* MTMP - Management Temperature
4568 * -----------------------------
4569 * This register controls the settings of the temperature measurements
4570 * and enables reading the temperature measurements. Note that temperature
4571 * is in 0.125 degrees Celsius.
4572 */
4573 #define MLXSW_REG_MTMP_ID 0x900A
4574 #define MLXSW_REG_MTMP_LEN 0x20
4575
4576 static const struct mlxsw_reg_info mlxsw_reg_mtmp = {
4577 .id = MLXSW_REG_MTMP_ID,
4578 .len = MLXSW_REG_MTMP_LEN,
4579 };
4580
4581 /* reg_mtmp_sensor_index
4582 * Sensors index to access.
4583 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
4584 * (module 0 is mapped to sensor_index 64).
4585 * Access: Index
4586 */
4587 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7);
4588
4589 /* Convert to milli degrees Celsius */
4590 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125)
4591
4592 /* reg_mtmp_temperature
4593 * Temperature reading from the sensor. Reading is in 0.125 Celsius
4594 * degrees units.
4595 * Access: RO
4596 */
4597 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
4598
4599 /* reg_mtmp_mte
4600 * Max Temperature Enable - enables measuring the max temperature on a sensor.
4601 * Access: RW
4602 */
4603 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
4604
4605 /* reg_mtmp_mtr
4606 * Max Temperature Reset - clears the value of the max temperature register.
4607 * Access: WO
4608 */
4609 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
4610
4611 /* reg_mtmp_max_temperature
4612 * The highest measured temperature from the sensor.
4613 * When the bit mte is cleared, the field max_temperature is reserved.
4614 * Access: RO
4615 */
4616 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
4617
4618 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
4619
4620 /* reg_mtmp_sensor_name
4621 * Sensor Name
4622 * Access: RO
4623 */
4624 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
4625
4626 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index,
4627 bool max_temp_enable,
4628 bool max_temp_reset)
4629 {
4630 MLXSW_REG_ZERO(mtmp, payload);
4631 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
4632 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
4633 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
4634 }
4635
4636 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp,
4637 unsigned int *p_max_temp,
4638 char *sensor_name)
4639 {
4640 u16 temp;
4641
4642 if (p_temp) {
4643 temp = mlxsw_reg_mtmp_temperature_get(payload);
4644 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
4645 }
4646 if (p_max_temp) {
4647 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
4648 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
4649 }
4650 if (sensor_name)
4651 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
4652 }
4653
4654 /* MPAT - Monitoring Port Analyzer Table
4655 * -------------------------------------
4656 * MPAT Register is used to query and configure the Switch PortAnalyzer Table.
4657 * For an enabled analyzer, all fields except e (enable) cannot be modified.
4658 */
4659 #define MLXSW_REG_MPAT_ID 0x901A
4660 #define MLXSW_REG_MPAT_LEN 0x78
4661
4662 static const struct mlxsw_reg_info mlxsw_reg_mpat = {
4663 .id = MLXSW_REG_MPAT_ID,
4664 .len = MLXSW_REG_MPAT_LEN,
4665 };
4666
4667 /* reg_mpat_pa_id
4668 * Port Analyzer ID.
4669 * Access: Index
4670 */
4671 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
4672
4673 /* reg_mpat_system_port
4674 * A unique port identifier for the final destination of the packet.
4675 * Access: RW
4676 */
4677 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
4678
4679 /* reg_mpat_e
4680 * Enable. Indicating the Port Analyzer is enabled.
4681 * Access: RW
4682 */
4683 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
4684
4685 /* reg_mpat_qos
4686 * Quality Of Service Mode.
4687 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation
4688 * PCP, DEI, DSCP or VL) are configured.
4689 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the
4690 * same as in the original packet that has triggered the mirroring. For
4691 * SPAN also the pcp,dei are maintained.
4692 * Access: RW
4693 */
4694 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
4695
4696 /* reg_mpat_be
4697 * Best effort mode. Indicates mirroring traffic should not cause packet
4698 * drop or back pressure, but will discard the mirrored packets. Mirrored
4699 * packets will be forwarded on a best effort manner.
4700 * 0: Do not discard mirrored packets
4701 * 1: Discard mirrored packets if causing congestion
4702 * Access: RW
4703 */
4704 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
4705
4706 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
4707 u16 system_port, bool e)
4708 {
4709 MLXSW_REG_ZERO(mpat, payload);
4710 mlxsw_reg_mpat_pa_id_set(payload, pa_id);
4711 mlxsw_reg_mpat_system_port_set(payload, system_port);
4712 mlxsw_reg_mpat_e_set(payload, e);
4713 mlxsw_reg_mpat_qos_set(payload, 1);
4714 mlxsw_reg_mpat_be_set(payload, 1);
4715 }
4716
4717 /* MPAR - Monitoring Port Analyzer Register
4718 * ----------------------------------------
4719 * MPAR register is used to query and configure the port analyzer port mirroring
4720 * properties.
4721 */
4722 #define MLXSW_REG_MPAR_ID 0x901B
4723 #define MLXSW_REG_MPAR_LEN 0x08
4724
4725 static const struct mlxsw_reg_info mlxsw_reg_mpar = {
4726 .id = MLXSW_REG_MPAR_ID,
4727 .len = MLXSW_REG_MPAR_LEN,
4728 };
4729
4730 /* reg_mpar_local_port
4731 * The local port to mirror the packets from.
4732 * Access: Index
4733 */
4734 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8);
4735
4736 enum mlxsw_reg_mpar_i_e {
4737 MLXSW_REG_MPAR_TYPE_EGRESS,
4738 MLXSW_REG_MPAR_TYPE_INGRESS,
4739 };
4740
4741 /* reg_mpar_i_e
4742 * Ingress/Egress
4743 * Access: Index
4744 */
4745 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
4746
4747 /* reg_mpar_enable
4748 * Enable mirroring
4749 * By default, port mirroring is disabled for all ports.
4750 * Access: RW
4751 */
4752 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
4753
4754 /* reg_mpar_pa_id
4755 * Port Analyzer ID.
4756 * Access: RW
4757 */
4758 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
4759
4760 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
4761 enum mlxsw_reg_mpar_i_e i_e,
4762 bool enable, u8 pa_id)
4763 {
4764 MLXSW_REG_ZERO(mpar, payload);
4765 mlxsw_reg_mpar_local_port_set(payload, local_port);
4766 mlxsw_reg_mpar_enable_set(payload, enable);
4767 mlxsw_reg_mpar_i_e_set(payload, i_e);
4768 mlxsw_reg_mpar_pa_id_set(payload, pa_id);
4769 }
4770
4771 /* MLCR - Management LED Control Register
4772 * --------------------------------------
4773 * Controls the system LEDs.
4774 */
4775 #define MLXSW_REG_MLCR_ID 0x902B
4776 #define MLXSW_REG_MLCR_LEN 0x0C
4777
4778 static const struct mlxsw_reg_info mlxsw_reg_mlcr = {
4779 .id = MLXSW_REG_MLCR_ID,
4780 .len = MLXSW_REG_MLCR_LEN,
4781 };
4782
4783 /* reg_mlcr_local_port
4784 * Local port number.
4785 * Access: RW
4786 */
4787 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
4788
4789 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
4790
4791 /* reg_mlcr_beacon_duration
4792 * Duration of the beacon to be active, in seconds.
4793 * 0x0 - Will turn off the beacon.
4794 * 0xFFFF - Will turn on the beacon until explicitly turned off.
4795 * Access: RW
4796 */
4797 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
4798
4799 /* reg_mlcr_beacon_remain
4800 * Remaining duration of the beacon, in seconds.
4801 * 0xFFFF indicates an infinite amount of time.
4802 * Access: RO
4803 */
4804 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
4805
4806 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
4807 bool active)
4808 {
4809 MLXSW_REG_ZERO(mlcr, payload);
4810 mlxsw_reg_mlcr_local_port_set(payload, local_port);
4811 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
4812 MLXSW_REG_MLCR_DURATION_MAX : 0);
4813 }
4814
4815 /* SBPR - Shared Buffer Pools Register
4816 * -----------------------------------
4817 * The SBPR configures and retrieves the shared buffer pools and configuration.
4818 */
4819 #define MLXSW_REG_SBPR_ID 0xB001
4820 #define MLXSW_REG_SBPR_LEN 0x14
4821
4822 static const struct mlxsw_reg_info mlxsw_reg_sbpr = {
4823 .id = MLXSW_REG_SBPR_ID,
4824 .len = MLXSW_REG_SBPR_LEN,
4825 };
4826
4827 /* shared direstion enum for SBPR, SBCM, SBPM */
4828 enum mlxsw_reg_sbxx_dir {
4829 MLXSW_REG_SBXX_DIR_INGRESS,
4830 MLXSW_REG_SBXX_DIR_EGRESS,
4831 };
4832
4833 /* reg_sbpr_dir
4834 * Direction.
4835 * Access: Index
4836 */
4837 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
4838
4839 /* reg_sbpr_pool
4840 * Pool index.
4841 * Access: Index
4842 */
4843 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
4844
4845 /* reg_sbpr_size
4846 * Pool size in buffer cells.
4847 * Access: RW
4848 */
4849 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
4850
4851 enum mlxsw_reg_sbpr_mode {
4852 MLXSW_REG_SBPR_MODE_STATIC,
4853 MLXSW_REG_SBPR_MODE_DYNAMIC,
4854 };
4855
4856 /* reg_sbpr_mode
4857 * Pool quota calculation mode.
4858 * Access: RW
4859 */
4860 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
4861
4862 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
4863 enum mlxsw_reg_sbxx_dir dir,
4864 enum mlxsw_reg_sbpr_mode mode, u32 size)
4865 {
4866 MLXSW_REG_ZERO(sbpr, payload);
4867 mlxsw_reg_sbpr_pool_set(payload, pool);
4868 mlxsw_reg_sbpr_dir_set(payload, dir);
4869 mlxsw_reg_sbpr_mode_set(payload, mode);
4870 mlxsw_reg_sbpr_size_set(payload, size);
4871 }
4872
4873 /* SBCM - Shared Buffer Class Management Register
4874 * ----------------------------------------------
4875 * The SBCM register configures and retrieves the shared buffer allocation
4876 * and configuration according to Port-PG, including the binding to pool
4877 * and definition of the associated quota.
4878 */
4879 #define MLXSW_REG_SBCM_ID 0xB002
4880 #define MLXSW_REG_SBCM_LEN 0x28
4881
4882 static const struct mlxsw_reg_info mlxsw_reg_sbcm = {
4883 .id = MLXSW_REG_SBCM_ID,
4884 .len = MLXSW_REG_SBCM_LEN,
4885 };
4886
4887 /* reg_sbcm_local_port
4888 * Local port number.
4889 * For Ingress: excludes CPU port and Router port
4890 * For Egress: excludes IP Router
4891 * Access: Index
4892 */
4893 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
4894
4895 /* reg_sbcm_pg_buff
4896 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
4897 * For PG buffer: range is 0..cap_max_pg_buffers - 1
4898 * For traffic class: range is 0..cap_max_tclass - 1
4899 * Note that when traffic class is in MC aware mode then the traffic
4900 * classes which are MC aware cannot be configured.
4901 * Access: Index
4902 */
4903 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
4904
4905 /* reg_sbcm_dir
4906 * Direction.
4907 * Access: Index
4908 */
4909 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
4910
4911 /* reg_sbcm_min_buff
4912 * Minimum buffer size for the limiter, in cells.
4913 * Access: RW
4914 */
4915 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
4916
4917 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */
4918 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
4919 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
4920
4921 /* reg_sbcm_max_buff
4922 * When the pool associated to the port-pg/tclass is configured to
4923 * static, Maximum buffer size for the limiter configured in cells.
4924 * When the pool associated to the port-pg/tclass is configured to
4925 * dynamic, the max_buff holds the "alpha" parameter, supporting
4926 * the following values:
4927 * 0: 0
4928 * i: (1/128)*2^(i-1), for i=1..14
4929 * 0xFF: Infinity
4930 * Access: RW
4931 */
4932 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
4933
4934 /* reg_sbcm_pool
4935 * Association of the port-priority to a pool.
4936 * Access: RW
4937 */
4938 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
4939
4940 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
4941 enum mlxsw_reg_sbxx_dir dir,
4942 u32 min_buff, u32 max_buff, u8 pool)
4943 {
4944 MLXSW_REG_ZERO(sbcm, payload);
4945 mlxsw_reg_sbcm_local_port_set(payload, local_port);
4946 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
4947 mlxsw_reg_sbcm_dir_set(payload, dir);
4948 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
4949 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
4950 mlxsw_reg_sbcm_pool_set(payload, pool);
4951 }
4952
4953 /* SBPM - Shared Buffer Port Management Register
4954 * ---------------------------------------------
4955 * The SBPM register configures and retrieves the shared buffer allocation
4956 * and configuration according to Port-Pool, including the definition
4957 * of the associated quota.
4958 */
4959 #define MLXSW_REG_SBPM_ID 0xB003
4960 #define MLXSW_REG_SBPM_LEN 0x28
4961
4962 static const struct mlxsw_reg_info mlxsw_reg_sbpm = {
4963 .id = MLXSW_REG_SBPM_ID,
4964 .len = MLXSW_REG_SBPM_LEN,
4965 };
4966
4967 /* reg_sbpm_local_port
4968 * Local port number.
4969 * For Ingress: excludes CPU port and Router port
4970 * For Egress: excludes IP Router
4971 * Access: Index
4972 */
4973 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
4974
4975 /* reg_sbpm_pool
4976 * The pool associated to quota counting on the local_port.
4977 * Access: Index
4978 */
4979 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
4980
4981 /* reg_sbpm_dir
4982 * Direction.
4983 * Access: Index
4984 */
4985 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
4986
4987 /* reg_sbpm_buff_occupancy
4988 * Current buffer occupancy in cells.
4989 * Access: RO
4990 */
4991 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
4992
4993 /* reg_sbpm_clr
4994 * Clear Max Buffer Occupancy
4995 * When this bit is set, max_buff_occupancy field is cleared (and a
4996 * new max value is tracked from the time the clear was performed).
4997 * Access: OP
4998 */
4999 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
5000
5001 /* reg_sbpm_max_buff_occupancy
5002 * Maximum value of buffer occupancy in cells monitored. Cleared by
5003 * writing to the clr field.
5004 * Access: RO
5005 */
5006 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
5007
5008 /* reg_sbpm_min_buff
5009 * Minimum buffer size for the limiter, in cells.
5010 * Access: RW
5011 */
5012 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
5013
5014 /* reg_sbpm_max_buff
5015 * When the pool associated to the port-pg/tclass is configured to
5016 * static, Maximum buffer size for the limiter configured in cells.
5017 * When the pool associated to the port-pg/tclass is configured to
5018 * dynamic, the max_buff holds the "alpha" parameter, supporting
5019 * the following values:
5020 * 0: 0
5021 * i: (1/128)*2^(i-1), for i=1..14
5022 * 0xFF: Infinity
5023 * Access: RW
5024 */
5025 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
5026
5027 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
5028 enum mlxsw_reg_sbxx_dir dir, bool clr,
5029 u32 min_buff, u32 max_buff)
5030 {
5031 MLXSW_REG_ZERO(sbpm, payload);
5032 mlxsw_reg_sbpm_local_port_set(payload, local_port);
5033 mlxsw_reg_sbpm_pool_set(payload, pool);
5034 mlxsw_reg_sbpm_dir_set(payload, dir);
5035 mlxsw_reg_sbpm_clr_set(payload, clr);
5036 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
5037 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
5038 }
5039
5040 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
5041 u32 *p_max_buff_occupancy)
5042 {
5043 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
5044 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
5045 }
5046
5047 /* SBMM - Shared Buffer Multicast Management Register
5048 * --------------------------------------------------
5049 * The SBMM register configures and retrieves the shared buffer allocation
5050 * and configuration for MC packets according to Switch-Priority, including
5051 * the binding to pool and definition of the associated quota.
5052 */
5053 #define MLXSW_REG_SBMM_ID 0xB004
5054 #define MLXSW_REG_SBMM_LEN 0x28
5055
5056 static const struct mlxsw_reg_info mlxsw_reg_sbmm = {
5057 .id = MLXSW_REG_SBMM_ID,
5058 .len = MLXSW_REG_SBMM_LEN,
5059 };
5060
5061 /* reg_sbmm_prio
5062 * Switch Priority.
5063 * Access: Index
5064 */
5065 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
5066
5067 /* reg_sbmm_min_buff
5068 * Minimum buffer size for the limiter, in cells.
5069 * Access: RW
5070 */
5071 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
5072
5073 /* reg_sbmm_max_buff
5074 * When the pool associated to the port-pg/tclass is configured to
5075 * static, Maximum buffer size for the limiter configured in cells.
5076 * When the pool associated to the port-pg/tclass is configured to
5077 * dynamic, the max_buff holds the "alpha" parameter, supporting
5078 * the following values:
5079 * 0: 0
5080 * i: (1/128)*2^(i-1), for i=1..14
5081 * 0xFF: Infinity
5082 * Access: RW
5083 */
5084 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
5085
5086 /* reg_sbmm_pool
5087 * Association of the port-priority to a pool.
5088 * Access: RW
5089 */
5090 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
5091
5092 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
5093 u32 max_buff, u8 pool)
5094 {
5095 MLXSW_REG_ZERO(sbmm, payload);
5096 mlxsw_reg_sbmm_prio_set(payload, prio);
5097 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
5098 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
5099 mlxsw_reg_sbmm_pool_set(payload, pool);
5100 }
5101
5102 /* SBSR - Shared Buffer Status Register
5103 * ------------------------------------
5104 * The SBSR register retrieves the shared buffer occupancy according to
5105 * Port-Pool. Note that this register enables reading a large amount of data.
5106 * It is the user's responsibility to limit the amount of data to ensure the
5107 * response can match the maximum transfer unit. In case the response exceeds
5108 * the maximum transport unit, it will be truncated with no special notice.
5109 */
5110 #define MLXSW_REG_SBSR_ID 0xB005
5111 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
5112 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
5113 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120
5114 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \
5115 MLXSW_REG_SBSR_REC_LEN * \
5116 MLXSW_REG_SBSR_REC_MAX_COUNT)
5117
5118 static const struct mlxsw_reg_info mlxsw_reg_sbsr = {
5119 .id = MLXSW_REG_SBSR_ID,
5120 .len = MLXSW_REG_SBSR_LEN,
5121 };
5122
5123 /* reg_sbsr_clr
5124 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
5125 * field is cleared (and a new max value is tracked from the time the clear
5126 * was performed).
5127 * Access: OP
5128 */
5129 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
5130
5131 /* reg_sbsr_ingress_port_mask
5132 * Bit vector for all ingress network ports.
5133 * Indicates which of the ports (for which the relevant bit is set)
5134 * are affected by the set operation. Configuration of any other port
5135 * does not change.
5136 * Access: Index
5137 */
5138 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
5139
5140 /* reg_sbsr_pg_buff_mask
5141 * Bit vector for all switch priority groups.
5142 * Indicates which of the priorities (for which the relevant bit is set)
5143 * are affected by the set operation. Configuration of any other priority
5144 * does not change.
5145 * Range is 0..cap_max_pg_buffers - 1
5146 * Access: Index
5147 */
5148 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
5149
5150 /* reg_sbsr_egress_port_mask
5151 * Bit vector for all egress network ports.
5152 * Indicates which of the ports (for which the relevant bit is set)
5153 * are affected by the set operation. Configuration of any other port
5154 * does not change.
5155 * Access: Index
5156 */
5157 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
5158
5159 /* reg_sbsr_tclass_mask
5160 * Bit vector for all traffic classes.
5161 * Indicates which of the traffic classes (for which the relevant bit is
5162 * set) are affected by the set operation. Configuration of any other
5163 * traffic class does not change.
5164 * Range is 0..cap_max_tclass - 1
5165 * Access: Index
5166 */
5167 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
5168
5169 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
5170 {
5171 MLXSW_REG_ZERO(sbsr, payload);
5172 mlxsw_reg_sbsr_clr_set(payload, clr);
5173 }
5174
5175 /* reg_sbsr_rec_buff_occupancy
5176 * Current buffer occupancy in cells.
5177 * Access: RO
5178 */
5179 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
5180 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
5181
5182 /* reg_sbsr_rec_max_buff_occupancy
5183 * Maximum value of buffer occupancy in cells monitored. Cleared by
5184 * writing to the clr field.
5185 * Access: RO
5186 */
5187 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
5188 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
5189
5190 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
5191 u32 *p_buff_occupancy,
5192 u32 *p_max_buff_occupancy)
5193 {
5194 *p_buff_occupancy =
5195 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
5196 *p_max_buff_occupancy =
5197 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
5198 }
5199
5200 /* SBIB - Shared Buffer Internal Buffer Register
5201 * ---------------------------------------------
5202 * The SBIB register configures per port buffers for internal use. The internal
5203 * buffers consume memory on the port buffers (note that the port buffers are
5204 * used also by PBMC).
5205 *
5206 * For Spectrum this is used for egress mirroring.
5207 */
5208 #define MLXSW_REG_SBIB_ID 0xB006
5209 #define MLXSW_REG_SBIB_LEN 0x10
5210
5211 static const struct mlxsw_reg_info mlxsw_reg_sbib = {
5212 .id = MLXSW_REG_SBIB_ID,
5213 .len = MLXSW_REG_SBIB_LEN,
5214 };
5215
5216 /* reg_sbib_local_port
5217 * Local port number
5218 * Not supported for CPU port and router port
5219 * Access: Index
5220 */
5221 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8);
5222
5223 /* reg_sbib_buff_size
5224 * Units represented in cells
5225 * Allowed range is 0 to (cap_max_headroom_size - 1)
5226 * Default is 0
5227 * Access: RW
5228 */
5229 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
5230
5231 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
5232 u32 buff_size)
5233 {
5234 MLXSW_REG_ZERO(sbib, payload);
5235 mlxsw_reg_sbib_local_port_set(payload, local_port);
5236 mlxsw_reg_sbib_buff_size_set(payload, buff_size);
5237 }
5238
5239 static inline const char *mlxsw_reg_id_str(u16 reg_id)
5240 {
5241 switch (reg_id) {
5242 case MLXSW_REG_SGCR_ID:
5243 return "SGCR";
5244 case MLXSW_REG_SPAD_ID:
5245 return "SPAD";
5246 case MLXSW_REG_SMID_ID:
5247 return "SMID";
5248 case MLXSW_REG_SSPR_ID:
5249 return "SSPR";
5250 case MLXSW_REG_SFDAT_ID:
5251 return "SFDAT";
5252 case MLXSW_REG_SFD_ID:
5253 return "SFD";
5254 case MLXSW_REG_SFN_ID:
5255 return "SFN";
5256 case MLXSW_REG_SPMS_ID:
5257 return "SPMS";
5258 case MLXSW_REG_SPVID_ID:
5259 return "SPVID";
5260 case MLXSW_REG_SPVM_ID:
5261 return "SPVM";
5262 case MLXSW_REG_SPAFT_ID:
5263 return "SPAFT";
5264 case MLXSW_REG_SFGC_ID:
5265 return "SFGC";
5266 case MLXSW_REG_SFTR_ID:
5267 return "SFTR";
5268 case MLXSW_REG_SFDF_ID:
5269 return "SFDF";
5270 case MLXSW_REG_SLDR_ID:
5271 return "SLDR";
5272 case MLXSW_REG_SLCR_ID:
5273 return "SLCR";
5274 case MLXSW_REG_SLCOR_ID:
5275 return "SLCOR";
5276 case MLXSW_REG_SPMLR_ID:
5277 return "SPMLR";
5278 case MLXSW_REG_SVFA_ID:
5279 return "SVFA";
5280 case MLXSW_REG_SVPE_ID:
5281 return "SVPE";
5282 case MLXSW_REG_SFMR_ID:
5283 return "SFMR";
5284 case MLXSW_REG_SPVMLR_ID:
5285 return "SPVMLR";
5286 case MLXSW_REG_QTCT_ID:
5287 return "QTCT";
5288 case MLXSW_REG_QEEC_ID:
5289 return "QEEC";
5290 case MLXSW_REG_PMLP_ID:
5291 return "PMLP";
5292 case MLXSW_REG_PMTU_ID:
5293 return "PMTU";
5294 case MLXSW_REG_PTYS_ID:
5295 return "PTYS";
5296 case MLXSW_REG_PPAD_ID:
5297 return "PPAD";
5298 case MLXSW_REG_PAOS_ID:
5299 return "PAOS";
5300 case MLXSW_REG_PFCC_ID:
5301 return "PFCC";
5302 case MLXSW_REG_PPCNT_ID:
5303 return "PPCNT";
5304 case MLXSW_REG_PPTB_ID:
5305 return "PPTB";
5306 case MLXSW_REG_PBMC_ID:
5307 return "PBMC";
5308 case MLXSW_REG_PSPA_ID:
5309 return "PSPA";
5310 case MLXSW_REG_HTGT_ID:
5311 return "HTGT";
5312 case MLXSW_REG_HPKT_ID:
5313 return "HPKT";
5314 case MLXSW_REG_RGCR_ID:
5315 return "RGCR";
5316 case MLXSW_REG_RITR_ID:
5317 return "RITR";
5318 case MLXSW_REG_RATR_ID:
5319 return "RATR";
5320 case MLXSW_REG_RALTA_ID:
5321 return "RALTA";
5322 case MLXSW_REG_RALST_ID:
5323 return "RALST";
5324 case MLXSW_REG_RALTB_ID:
5325 return "RALTB";
5326 case MLXSW_REG_RALUE_ID:
5327 return "RALUE";
5328 case MLXSW_REG_RAUHT_ID:
5329 return "RAUHT";
5330 case MLXSW_REG_RALEU_ID:
5331 return "RALEU";
5332 case MLXSW_REG_RAUHTD_ID:
5333 return "RAUHTD";
5334 case MLXSW_REG_MFCR_ID:
5335 return "MFCR";
5336 case MLXSW_REG_MFSC_ID:
5337 return "MFSC";
5338 case MLXSW_REG_MFSM_ID:
5339 return "MFSM";
5340 case MLXSW_REG_MTCAP_ID:
5341 return "MTCAP";
5342 case MLXSW_REG_MPAT_ID:
5343 return "MPAT";
5344 case MLXSW_REG_MPAR_ID:
5345 return "MPAR";
5346 case MLXSW_REG_MTMP_ID:
5347 return "MTMP";
5348 case MLXSW_REG_MLCR_ID:
5349 return "MLCR";
5350 case MLXSW_REG_SBPR_ID:
5351 return "SBPR";
5352 case MLXSW_REG_SBCM_ID:
5353 return "SBCM";
5354 case MLXSW_REG_SBPM_ID:
5355 return "SBPM";
5356 case MLXSW_REG_SBMM_ID:
5357 return "SBMM";
5358 case MLXSW_REG_SBSR_ID:
5359 return "SBSR";
5360 case MLXSW_REG_SBIB_ID:
5361 return "SBIB";
5362 default:
5363 return "*UNKNOWN*";
5364 }
5365 }
5366
5367 /* PUDE - Port Up / Down Event
5368 * ---------------------------
5369 * Reports the operational state change of a port.
5370 */
5371 #define MLXSW_REG_PUDE_LEN 0x10
5372
5373 /* reg_pude_swid
5374 * Switch partition ID with which to associate the port.
5375 * Access: Index
5376 */
5377 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
5378
5379 /* reg_pude_local_port
5380 * Local port number.
5381 * Access: Index
5382 */
5383 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
5384
5385 /* reg_pude_admin_status
5386 * Port administrative state (the desired state).
5387 * 1 - Up.
5388 * 2 - Down.
5389 * 3 - Up once. This means that in case of link failure, the port won't go
5390 * into polling mode, but will wait to be re-enabled by software.
5391 * 4 - Disabled by system. Can only be set by hardware.
5392 * Access: RO
5393 */
5394 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
5395
5396 /* reg_pude_oper_status
5397 * Port operatioanl state.
5398 * 1 - Up.
5399 * 2 - Down.
5400 * 3 - Down by port failure. This means that the device will not let the
5401 * port up again until explicitly specified by software.
5402 * Access: RO
5403 */
5404 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
5405
5406 #endif
Linux kernel - Deliverables
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