drivers/net/ethernet/netronome/nfp/nfp_net_ctrl.h

   1 /*
   2  * Copyright (C) 2015 Netronome Systems, Inc.
   3  *
   4  * This software is dual licensed under the GNU General License Version 2,
   5  * June 1991 as shown in the file COPYING in the top-level directory of this
   6  * source tree or the BSD 2-Clause License provided below.  You have the
   7  * option to license this software under the complete terms of either license.
   8  *
   9  * The BSD 2-Clause License:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      1. Redistributions of source code must retain the above
  16  *         copyright notice, this list of conditions and the following
  17  *         disclaimer.
  18  *
  19  *      2. Redistributions in binary form must reproduce the above
  20  *         copyright notice, this list of conditions and the following
  21  *         disclaimer in the documentation and/or other materials
  22  *         provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 /*
  35  * nfp_net_ctrl.h
  36  * Netronome network device driver: Control BAR layout
  37  * Authors: Jakub Kicinski <jakub.kicinski@netronome.com>
  38  *          Jason McMullan <jason.mcmullan@netronome.com>
  39  *          Rolf Neugebauer <rolf.neugebauer@netronome.com>
  40  *          Brad Petrus <brad.petrus@netronome.com>
  41  */
  42
  43 #ifndef _NFP_NET_CTRL_H_
  44 #define _NFP_NET_CTRL_H_
  45
  46 /* IMPORTANT: This header file is shared with the FW,
  47  *            no OS specific constructs, please!
  48  */
  49
  50 /**
  51  * Configuration BAR size.
  52  *
  53  * The configuration BAR is 8K in size, but on the NFP6000, due to
  54  * THB-350, 32k needs to be reserved.
  55  */
  56 #define NFP_NET_CFG_BAR_SZ              (32 * 1024)
  57
  58 /**
  59  * Offset in Freelist buffer where packet starts on RX
  60  */
  61 #define NFP_NET_RX_OFFSET               32
  62
  63 /**
  64  * Maximum header size supported for LSO frames
  65  */
  66 #define NFP_NET_LSO_MAX_HDR_SZ          255
  67
  68 /**
  69  * Hash type pre-pended when a RSS hash was computed
  70  */
  71 #define NFP_NET_RSS_NONE                0
  72 #define NFP_NET_RSS_IPV4                1
  73 #define NFP_NET_RSS_IPV6                2
  74 #define NFP_NET_RSS_IPV6_EX             3
  75 #define NFP_NET_RSS_IPV4_TCP            4
  76 #define NFP_NET_RSS_IPV6_TCP            5
  77 #define NFP_NET_RSS_IPV6_EX_TCP         6
  78 #define NFP_NET_RSS_IPV4_UDP            7
  79 #define NFP_NET_RSS_IPV6_UDP            8
  80 #define NFP_NET_RSS_IPV6_EX_UDP         9
  81
  82 /**
  83  * @NFP_NET_TXR_MAX:         Maximum number of TX rings
  84  * @NFP_NET_TXR_MASK:        Mask for TX rings
  85  * @NFP_NET_RXR_MAX:         Maximum number of RX rings
  86  * @NFP_NET_RXR_MASK:        Mask for RX rings
  87  */
  88 #define NFP_NET_TXR_MAX                 64
  89 #define NFP_NET_TXR_MASK                (NFP_NET_TXR_MAX - 1)
  90 #define NFP_NET_RXR_MAX                 64
  91 #define NFP_NET_RXR_MASK                (NFP_NET_RXR_MAX - 1)
  92
  93 /**
  94  * Read/Write config words (0x0000 - 0x002c)
  95  * @NFP_NET_CFG_CTRL:        Global control
  96  * @NFP_NET_CFG_UPDATE:      Indicate which fields are updated
  97  * @NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings
  98  * @NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings
  99  * @NFP_NET_CFG_MTU:         Set MTU size
 100  * @NFP_NET_CFG_FLBUFSZ:     Set freelist buffer size (must be larger than MTU)
 101  * @NFP_NET_CFG_EXN:         MSI-X table entry for exceptions
 102  * @NFP_NET_CFG_LSC:         MSI-X table entry for link state changes
 103  * @NFP_NET_CFG_MACADDR:     MAC address
 104  *
 105  * TODO:
 106  * - define Error details in UPDATE
 107  */
 108 #define NFP_NET_CFG_CTRL                0x0000
 109 #define   NFP_NET_CFG_CTRL_ENABLE         (0x1 <<  0) /* Global enable */
 110 #define   NFP_NET_CFG_CTRL_PROMISC        (0x1 <<  1) /* Enable Promisc mode */
 111 #define   NFP_NET_CFG_CTRL_L2BC           (0x1 <<  2) /* Allow L2 Broadcast */
 112 #define   NFP_NET_CFG_CTRL_L2MC           (0x1 <<  3) /* Allow L2 Multicast */
 113 #define   NFP_NET_CFG_CTRL_RXCSUM         (0x1 <<  4) /* Enable RX Checksum */
 114 #define   NFP_NET_CFG_CTRL_TXCSUM         (0x1 <<  5) /* Enable TX Checksum */
 115 #define   NFP_NET_CFG_CTRL_RXVLAN         (0x1 <<  6) /* Enable VLAN strip */
 116 #define   NFP_NET_CFG_CTRL_TXVLAN         (0x1 <<  7) /* Enable VLAN insert */
 117 #define   NFP_NET_CFG_CTRL_SCATTER        (0x1 <<  8) /* Scatter DMA */
 118 #define   NFP_NET_CFG_CTRL_GATHER         (0x1 <<  9) /* Gather DMA */
 119 #define   NFP_NET_CFG_CTRL_LSO            (0x1 << 10) /* LSO/TSO */
 120 #define   NFP_NET_CFG_CTRL_RINGCFG        (0x1 << 16) /* Ring runtime changes */
 121 #define   NFP_NET_CFG_CTRL_RSS            (0x1 << 17) /* RSS */
 122 #define   NFP_NET_CFG_CTRL_IRQMOD         (0x1 << 18) /* Interrupt moderation */
 123 #define   NFP_NET_CFG_CTRL_RINGPRIO       (0x1 << 19) /* Ring priorities */
 124 #define   NFP_NET_CFG_CTRL_MSIXAUTO       (0x1 << 20) /* MSI-X auto-masking */
 125 #define   NFP_NET_CFG_CTRL_TXRWB          (0x1 << 21) /* Write-back of TX ring*/
 126 #define   NFP_NET_CFG_CTRL_L2SWITCH       (0x1 << 22) /* L2 Switch */
 127 #define   NFP_NET_CFG_CTRL_L2SWITCH_LOCAL (0x1 << 23) /* Switch to local */
 128 #define   NFP_NET_CFG_CTRL_VXLAN          (0x1 << 24) /* VXLAN tunnel support */
 129 #define   NFP_NET_CFG_CTRL_NVGRE          (0x1 << 25) /* NVGRE tunnel support */
 130 #define NFP_NET_CFG_UPDATE              0x0004
 131 #define   NFP_NET_CFG_UPDATE_GEN          (0x1 <<  0) /* General update */
 132 #define   NFP_NET_CFG_UPDATE_RING         (0x1 <<  1) /* Ring config change */
 133 #define   NFP_NET_CFG_UPDATE_RSS          (0x1 <<  2) /* RSS config change */
 134 #define   NFP_NET_CFG_UPDATE_TXRPRIO      (0x1 <<  3) /* TX Ring prio change */
 135 #define   NFP_NET_CFG_UPDATE_RXRPRIO      (0x1 <<  4) /* RX Ring prio change */
 136 #define   NFP_NET_CFG_UPDATE_MSIX         (0x1 <<  5) /* MSI-X change */
 137 #define   NFP_NET_CFG_UPDATE_L2SWITCH     (0x1 <<  6) /* Switch changes */
 138 #define   NFP_NET_CFG_UPDATE_RESET        (0x1 <<  7) /* Update due to FLR */
 139 #define   NFP_NET_CFG_UPDATE_IRQMOD       (0x1 <<  8) /* IRQ mod change */
 140 #define   NFP_NET_CFG_UPDATE_VXLAN        (0x1 <<  9) /* VXLAN port change */
 141 #define   NFP_NET_CFG_UPDATE_ERR          (0x1 << 31) /* A error occurred */
 142 #define NFP_NET_CFG_TXRS_ENABLE         0x0008
 143 #define NFP_NET_CFG_RXRS_ENABLE         0x0010
 144 #define NFP_NET_CFG_MTU                 0x0018
 145 #define NFP_NET_CFG_FLBUFSZ             0x001c
 146 #define NFP_NET_CFG_EXN                 0x001f
 147 #define NFP_NET_CFG_LSC                 0x0020
 148 #define NFP_NET_CFG_MACADDR             0x0024
 149
 150 /**
 151  * Read-only words (0x0030 - 0x0050):
 152  * @NFP_NET_CFG_VERSION:     Firmware version number
 153  * @NFP_NET_CFG_STS:         Status
 154  * @NFP_NET_CFG_CAP:         Capabilities (same bits as @NFP_NET_CFG_CTRL)
 155  * @NFP_NET_MAX_TXRINGS:     Maximum number of TX rings
 156  * @NFP_NET_MAX_RXRINGS:     Maximum number of RX rings
 157  * @NFP_NET_MAX_MTU:         Maximum support MTU
 158  * @NFP_NET_CFG_START_TXQ:   Start Queue Control Queue to use for TX (PF only)
 159  * @NFP_NET_CFG_START_RXQ:   Start Queue Control Queue to use for RX (PF only)
 160  *
 161  * TODO:
 162  * - define more STS bits
 163  */
 164 #define NFP_NET_CFG_VERSION             0x0030
 165 #define   NFP_NET_CFG_VERSION_RESERVED_MASK     (0xff << 24)
 166 #define   NFP_NET_CFG_VERSION_CLASS_MASK  (0xff << 16)
 167 #define   NFP_NET_CFG_VERSION_CLASS(x)    (((x) & 0xff) << 16)
 168 #define   NFP_NET_CFG_VERSION_CLASS_GENERIC     0
 169 #define   NFP_NET_CFG_VERSION_MAJOR_MASK  (0xff <<  8)
 170 #define   NFP_NET_CFG_VERSION_MAJOR(x)    (((x) & 0xff) <<  8)
 171 #define   NFP_NET_CFG_VERSION_MINOR_MASK  (0xff <<  0)
 172 #define   NFP_NET_CFG_VERSION_MINOR(x)    (((x) & 0xff) <<  0)
 173 #define NFP_NET_CFG_STS                 0x0034
 174 #define   NFP_NET_CFG_STS_LINK            (0x1 << 0) /* Link up or down */
 175 #define NFP_NET_CFG_CAP                 0x0038
 176 #define NFP_NET_CFG_MAX_TXRINGS         0x003c
 177 #define NFP_NET_CFG_MAX_RXRINGS         0x0040
 178 #define NFP_NET_CFG_MAX_MTU             0x0044
 179 /* Next two words are being used by VFs for solving THB350 issue */
 180 #define NFP_NET_CFG_START_TXQ           0x0048
 181 #define NFP_NET_CFG_START_RXQ           0x004c
 182
 183 /**
 184  * NFP-3200 workaround (0x0050 - 0x0058)
 185  * @NFP_NET_CFG_SPARE_ADDR:  DMA address for ME code to use (e.g. YDS-155 fix)
 186  */
 187 #define NFP_NET_CFG_SPARE_ADDR          0x0050
 188 /**
 189  * NFP6000/NFP4000 - Prepend configuration
 190  */
 191 #define NFP_NET_CFG_RX_OFFSET           0x0050
 192 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC           0       /* Prepend mode */
 193
 194 /**
 195  * NFP6000/NFP4000 - VXLAN/UDP encap configuration
 196  * @NFP_NET_CFG_VXLAN_PORT:     Base address of table of tunnels' UDP dst ports
 197  * @NFP_NET_CFG_VXLAN_SZ:       Size of the UDP port table in bytes
 198  */
 199 #define NFP_NET_CFG_VXLAN_PORT          0x0060
 200 #define NFP_NET_CFG_VXLAN_SZ              0x0008
 201
 202 /**
 203  * 64B reserved for future use (0x0080 - 0x00c0)
 204  */
 205 #define NFP_NET_CFG_RESERVED            0x0080
 206 #define NFP_NET_CFG_RESERVED_SZ         0x0040
 207
 208 /**
 209  * RSS configuration (0x0100 - 0x01ac):
 210  * Used only when NFP_NET_CFG_CTRL_RSS is enabled
 211  * @NFP_NET_CFG_RSS_CFG:     RSS configuration word
 212  * @NFP_NET_CFG_RSS_KEY:     RSS "secret" key
 213  * @NFP_NET_CFG_RSS_ITBL:    RSS indirection table
 214  */
 215 #define NFP_NET_CFG_RSS_BASE            0x0100
 216 #define NFP_NET_CFG_RSS_CTRL            NFP_NET_CFG_RSS_BASE
 217 #define   NFP_NET_CFG_RSS_MASK            (0x7f)
 218 #define   NFP_NET_CFG_RSS_MASK_of(_x)     ((_x) & 0x7f)
 219 #define   NFP_NET_CFG_RSS_IPV4            (1 <<  8) /* RSS for IPv4 */
 220 #define   NFP_NET_CFG_RSS_IPV6            (1 <<  9) /* RSS for IPv6 */
 221 #define   NFP_NET_CFG_RSS_IPV4_TCP        (1 << 10) /* RSS for IPv4/TCP */
 222 #define   NFP_NET_CFG_RSS_IPV4_UDP        (1 << 11) /* RSS for IPv4/UDP */
 223 #define   NFP_NET_CFG_RSS_IPV6_TCP        (1 << 12) /* RSS for IPv6/TCP */
 224 #define   NFP_NET_CFG_RSS_IPV6_UDP        (1 << 13) /* RSS for IPv6/UDP */
 225 #define   NFP_NET_CFG_RSS_TOEPLITZ        (1 << 24) /* Use Toeplitz hash */
 226 #define NFP_NET_CFG_RSS_KEY             (NFP_NET_CFG_RSS_BASE + 0x4)
 227 #define NFP_NET_CFG_RSS_KEY_SZ          0x28
 228 #define NFP_NET_CFG_RSS_ITBL            (NFP_NET_CFG_RSS_BASE + 0x4 + \
 229                                          NFP_NET_CFG_RSS_KEY_SZ)
 230 #define NFP_NET_CFG_RSS_ITBL_SZ         0x80
 231
 232 /**
 233  * TX ring configuration (0x200 - 0x800)
 234  * @NFP_NET_CFG_TXR_BASE:    Base offset for TX ring configuration
 235  * @NFP_NET_CFG_TXR_ADDR:    Per TX ring DMA address (8B entries)
 236  * @NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries)
 237  * @NFP_NET_CFG_TXR_SZ:      Per TX ring ring size (1B entries)
 238  * @NFP_NET_CFG_TXR_VEC:     Per TX ring MSI-X table entry (1B entries)
 239  * @NFP_NET_CFG_TXR_PRIO:    Per TX ring priority (1B entries)
 240  * @NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation packet
 241  */
 242 #define NFP_NET_CFG_TXR_BASE            0x0200
 243 #define NFP_NET_CFG_TXR_ADDR(_x)        (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8))
 244 #define NFP_NET_CFG_TXR_WB_ADDR(_x)     (NFP_NET_CFG_TXR_BASE + 0x200 + \
 245                                          ((_x) * 0x8))
 246 #define NFP_NET_CFG_TXR_SZ(_x)          (NFP_NET_CFG_TXR_BASE + 0x400 + (_x))
 247 #define NFP_NET_CFG_TXR_VEC(_x)         (NFP_NET_CFG_TXR_BASE + 0x440 + (_x))
 248 #define NFP_NET_CFG_TXR_PRIO(_x)        (NFP_NET_CFG_TXR_BASE + 0x480 + (_x))
 249 #define NFP_NET_CFG_TXR_IRQ_MOD(_x)     (NFP_NET_CFG_TXR_BASE + 0x500 + \
 250                                          ((_x) * 0x4))
 251
 252 /**
 253  * RX ring configuration (0x0800 - 0x0c00)
 254  * @NFP_NET_CFG_RXR_BASE:    Base offset for RX ring configuration
 255  * @NFP_NET_CFG_RXR_ADDR:    Per RX ring DMA address (8B entries)
 256  * @NFP_NET_CFG_RXR_SZ:      Per RX ring ring size (1B entries)
 257  * @NFP_NET_CFG_RXR_VEC:     Per RX ring MSI-X table entry (1B entries)
 258  * @NFP_NET_CFG_RXR_PRIO:    Per RX ring priority (1B entries)
 259  * @NFP_NET_CFG_RXR_IRQ_MOD: Per RX ring interrupt moderation (4B entries)
 260  */
 261 #define NFP_NET_CFG_RXR_BASE            0x0800
 262 #define NFP_NET_CFG_RXR_ADDR(_x)        (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8))
 263 #define NFP_NET_CFG_RXR_SZ(_x)          (NFP_NET_CFG_RXR_BASE + 0x200 + (_x))
 264 #define NFP_NET_CFG_RXR_VEC(_x)         (NFP_NET_CFG_RXR_BASE + 0x240 + (_x))
 265 #define NFP_NET_CFG_RXR_PRIO(_x)        (NFP_NET_CFG_RXR_BASE + 0x280 + (_x))
 266 #define NFP_NET_CFG_RXR_IRQ_MOD(_x)     (NFP_NET_CFG_RXR_BASE + 0x300 + \
 267                                          ((_x) * 0x4))
 268
 269 /**
 270  * Interrupt Control/Cause registers (0x0c00 - 0x0d00)
 271  * These registers are only used when MSI-X auto-masking is not
 272  * enabled (@NFP_NET_CFG_CTRL_MSIXAUTO not set).  The array is index
 273  * by MSI-X entry and are 1B in size.  If an entry is zero, the
 274  * corresponding entry is enabled.  If the FW generates an interrupt,
 275  * it writes a cause into the corresponding field.  This also masks
 276  * the MSI-X entry and the host driver must clear the register to
 277  * re-enable the interrupt.
 278  */
 279 #define NFP_NET_CFG_ICR_BASE            0x0c00
 280 #define NFP_NET_CFG_ICR(_x)             (NFP_NET_CFG_ICR_BASE + (_x))
 281 #define   NFP_NET_CFG_ICR_UNMASKED      0x0
 282 #define   NFP_NET_CFG_ICR_RXTX          0x1
 283 #define   NFP_NET_CFG_ICR_LSC           0x2
 284
 285 /**
 286  * General device stats (0x0d00 - 0x0d90)
 287  * all counters are 64bit.
 288  */
 289 #define NFP_NET_CFG_STATS_BASE          0x0d00
 290 #define NFP_NET_CFG_STATS_RX_DISCARDS   (NFP_NET_CFG_STATS_BASE + 0x00)
 291 #define NFP_NET_CFG_STATS_RX_ERRORS     (NFP_NET_CFG_STATS_BASE + 0x08)
 292 #define NFP_NET_CFG_STATS_RX_OCTETS     (NFP_NET_CFG_STATS_BASE + 0x10)
 293 #define NFP_NET_CFG_STATS_RX_UC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x18)
 294 #define NFP_NET_CFG_STATS_RX_MC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x20)
 295 #define NFP_NET_CFG_STATS_RX_BC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x28)
 296 #define NFP_NET_CFG_STATS_RX_FRAMES     (NFP_NET_CFG_STATS_BASE + 0x30)
 297 #define NFP_NET_CFG_STATS_RX_MC_FRAMES  (NFP_NET_CFG_STATS_BASE + 0x38)
 298 #define NFP_NET_CFG_STATS_RX_BC_FRAMES  (NFP_NET_CFG_STATS_BASE + 0x40)
 299
 300 #define NFP_NET_CFG_STATS_TX_DISCARDS   (NFP_NET_CFG_STATS_BASE + 0x48)
 301 #define NFP_NET_CFG_STATS_TX_ERRORS     (NFP_NET_CFG_STATS_BASE + 0x50)
 302 #define NFP_NET_CFG_STATS_TX_OCTETS     (NFP_NET_CFG_STATS_BASE + 0x58)
 303 #define NFP_NET_CFG_STATS_TX_UC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x60)
 304 #define NFP_NET_CFG_STATS_TX_MC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x68)
 305 #define NFP_NET_CFG_STATS_TX_BC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x70)
 306 #define NFP_NET_CFG_STATS_TX_FRAMES     (NFP_NET_CFG_STATS_BASE + 0x78)
 307 #define NFP_NET_CFG_STATS_TX_MC_FRAMES  (NFP_NET_CFG_STATS_BASE + 0x80)
 308 #define NFP_NET_CFG_STATS_TX_BC_FRAMES  (NFP_NET_CFG_STATS_BASE + 0x88)
 309
 310 /**
 311  * Per ring stats (0x1000 - 0x1800)
 312  * options, 64bit per entry
 313  * @NFP_NET_CFG_TXR_STATS:   TX ring statistics (Packet and Byte count)
 314  * @NFP_NET_CFG_RXR_STATS:   RX ring statistics (Packet and Byte count)
 315  */
 316 #define NFP_NET_CFG_TXR_STATS_BASE      0x1000
 317 #define NFP_NET_CFG_TXR_STATS(_x)       (NFP_NET_CFG_TXR_STATS_BASE + \
 318                                          ((_x) * 0x10))
 319 #define NFP_NET_CFG_RXR_STATS_BASE      0x1400
 320 #define NFP_NET_CFG_RXR_STATS(_x)       (NFP_NET_CFG_RXR_STATS_BASE + \
 321                                          ((_x) * 0x10))
 322
 323 #endif /* _NFP_NET_CTRL_H_ */