1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
9 #include <linux/types.h>
10 #include <linux/bitops.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/errno.h>
13 #include <linux/kernel.h>
14 #include <linux/list.h>
15 #include <linux/log2.h>
16 #include <linux/pci.h>
17 #include <linux/slab.h>
18 #include <linux/string.h>
19 #include <linux/bitops.h>
22 #include "qed_dev_api.h"
25 #include "qed_init_ops.h"
26 #include "qed_reg_addr.h"
27 #include "qed_sriov.h"
29 /* Max number of connection types in HW (DQ/CDU etc.) */
30 #define MAX_CONN_TYPES PROTOCOLID_COMMON
31 #define NUM_TASK_TYPES 2
32 #define NUM_TASK_PF_SEGMENTS 4
33 #define NUM_TASK_VF_SEGMENTS 1
36 #define QM_PQ_ELEMENT_SIZE 4 /* in bytes */
38 /* Doorbell-Queue constants */
39 #define DQ_RANGE_SHIFT 4
40 #define DQ_RANGE_ALIGN BIT(DQ_RANGE_SHIFT)
42 /* Searcher constants */
43 #define SRC_MIN_NUM_ELEMS 256
45 /* Timers constants */
47 #define TM_ALIGN BIT(TM_SHIFT)
48 #define TM_ELEM_SIZE 4
51 #define ILT_DEFAULT_HW_P_SIZE 3
52 #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12))
53 #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET
55 /* ILT entry structure */
56 #define ILT_ENTRY_PHY_ADDR_MASK 0x000FFFFFFFFFFFULL
57 #define ILT_ENTRY_PHY_ADDR_SHIFT 0
58 #define ILT_ENTRY_VALID_MASK 0x1ULL
59 #define ILT_ENTRY_VALID_SHIFT 52
60 #define ILT_ENTRY_IN_REGS 2
61 #define ILT_REG_SIZE_IN_BYTES 4
63 /* connection context union */
65 struct core_conn_context core_ctx
;
66 struct eth_conn_context eth_ctx
;
67 struct iscsi_conn_context iscsi_ctx
;
68 struct roce_conn_context roce_ctx
;
71 /* TYPE-0 task context - iSCSI */
72 union type0_task_context
{
73 struct iscsi_task_context iscsi_ctx
;
76 /* TYPE-1 task context - ROCE */
77 union type1_task_context
{
78 struct rdma_task_context roce_ctx
;
86 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
87 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
89 #define CONN_CXT_SIZE(p_hwfn) \
90 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
92 #define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context))
94 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
95 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
97 /* Alignment is inherent to the type1_task_context structure */
98 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
100 /* PF per protocl configuration object */
101 #define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
102 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
110 struct qed_conn_type_cfg
{
114 struct qed_tid_seg tid_seg
[TASK_SEGMENTS
];
117 /* ILT Client configuration, Per connection type (protocol) resources. */
118 #define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2)
119 #define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2)
122 #define CDUT_SEG_BLK(n) (1 + (u8)(n))
123 #define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_ ## X ## _SEGMENTS)
135 struct ilt_cfg_pair
{
140 struct qed_ilt_cli_blk
{
141 u32 total_size
; /* 0 means not active */
142 u32 real_size_in_page
;
144 u32 dynamic_line_cnt
;
147 struct qed_ilt_client_cfg
{
151 struct ilt_cfg_pair first
;
152 struct ilt_cfg_pair last
;
153 struct ilt_cfg_pair p_size
;
155 /* ILT client blocks for PF */
156 struct qed_ilt_cli_blk pf_blks
[ILT_CLI_PF_BLOCKS
];
159 /* ILT client blocks for VFs */
160 struct qed_ilt_cli_blk vf_blks
[ILT_CLI_VF_BLOCKS
];
166 * Protocol acquired CID lists
167 * PF start line in ILT
175 struct qed_cid_acquired_map
{
178 unsigned long *cid_map
;
181 struct qed_cxt_mngr
{
182 /* Per protocl configuration */
183 struct qed_conn_type_cfg conn_cfg
[MAX_CONN_TYPES
];
185 /* computed ILT structure */
186 struct qed_ilt_client_cfg clients
[ILT_CLI_MAX
];
188 /* Task type sizes */
189 u32 task_type_size
[NUM_TASK_TYPES
];
191 /* total number of VFs for this hwfn -
192 * ALL VFs are symmetric in terms of HW resources
196 /* total number of SRQ's for this hwfn */
200 struct qed_cid_acquired_map acquired
[MAX_CONN_TYPES
];
202 /* ILT shadow table */
203 struct qed_dma_mem
*ilt_shadow
;
206 /* Mutex for a dynamic ILT allocation */
210 struct qed_dma_mem
*t2
;
215 static bool src_proto(enum protocol_type type
)
217 return type
== PROTOCOLID_ISCSI
||
218 type
== PROTOCOLID_ROCE
;
221 static bool tm_cid_proto(enum protocol_type type
)
223 return type
== PROTOCOLID_ISCSI
||
224 type
== PROTOCOLID_ROCE
;
227 /* counts the iids for the CDU/CDUC ILT client configuration */
228 struct qed_cdu_iids
{
233 static void qed_cxt_cdu_iids(struct qed_cxt_mngr
*p_mngr
,
234 struct qed_cdu_iids
*iids
)
238 for (type
= 0; type
< MAX_CONN_TYPES
; type
++) {
239 iids
->pf_cids
+= p_mngr
->conn_cfg
[type
].cid_count
;
240 iids
->per_vf_cids
+= p_mngr
->conn_cfg
[type
].cids_per_vf
;
244 /* counts the iids for the Searcher block configuration */
245 struct qed_src_iids
{
250 static void qed_cxt_src_iids(struct qed_cxt_mngr
*p_mngr
,
251 struct qed_src_iids
*iids
)
255 for (i
= 0; i
< MAX_CONN_TYPES
; i
++) {
259 iids
->pf_cids
+= p_mngr
->conn_cfg
[i
].cid_count
;
260 iids
->per_vf_cids
+= p_mngr
->conn_cfg
[i
].cids_per_vf
;
264 /* counts the iids for the Timers block configuration */
267 u32 pf_tids
[NUM_TASK_PF_SEGMENTS
]; /* per segment */
273 static void qed_cxt_tm_iids(struct qed_cxt_mngr
*p_mngr
,
274 struct qed_tm_iids
*iids
)
278 for (i
= 0; i
< MAX_CONN_TYPES
; i
++) {
279 struct qed_conn_type_cfg
*p_cfg
= &p_mngr
->conn_cfg
[i
];
281 if (tm_cid_proto(i
)) {
282 iids
->pf_cids
+= p_cfg
->cid_count
;
283 iids
->per_vf_cids
+= p_cfg
->cids_per_vf
;
287 iids
->pf_cids
= roundup(iids
->pf_cids
, TM_ALIGN
);
288 iids
->per_vf_cids
= roundup(iids
->per_vf_cids
, TM_ALIGN
);
289 iids
->per_vf_tids
= roundup(iids
->per_vf_tids
, TM_ALIGN
);
291 for (iids
->pf_tids_total
= 0, j
= 0; j
< NUM_TASK_PF_SEGMENTS
; j
++) {
292 iids
->pf_tids
[j
] = roundup(iids
->pf_tids
[j
], TM_ALIGN
);
293 iids
->pf_tids_total
+= iids
->pf_tids
[j
];
297 static void qed_cxt_qm_iids(struct qed_hwfn
*p_hwfn
,
298 struct qed_qm_iids
*iids
)
300 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
301 struct qed_tid_seg
*segs
;
302 u32 vf_cids
= 0, type
, j
;
305 for (type
= 0; type
< MAX_CONN_TYPES
; type
++) {
306 iids
->cids
+= p_mngr
->conn_cfg
[type
].cid_count
;
307 vf_cids
+= p_mngr
->conn_cfg
[type
].cids_per_vf
;
309 segs
= p_mngr
->conn_cfg
[type
].tid_seg
;
310 /* for each segment there is at most one
311 * protocol for which count is not 0.
313 for (j
= 0; j
< NUM_TASK_PF_SEGMENTS
; j
++)
314 iids
->tids
+= segs
[j
].count
;
316 /* The last array elelment is for the VFs. As for PF
317 * segments there can be only one protocol for
318 * which this value is not 0.
320 vf_tids
+= segs
[NUM_TASK_PF_SEGMENTS
].count
;
323 iids
->vf_cids
+= vf_cids
* p_mngr
->vf_count
;
324 iids
->tids
+= vf_tids
* p_mngr
->vf_count
;
326 DP_VERBOSE(p_hwfn
, QED_MSG_ILT
,
327 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
328 iids
->cids
, iids
->vf_cids
, iids
->tids
, vf_tids
);
331 static struct qed_tid_seg
*qed_cxt_tid_seg_info(struct qed_hwfn
*p_hwfn
,
334 struct qed_cxt_mngr
*p_cfg
= p_hwfn
->p_cxt_mngr
;
337 /* Find the protocol with tid count > 0 for this segment.
338 * Note: there can only be one and this is already validated.
340 for (i
= 0; i
< MAX_CONN_TYPES
; i
++)
341 if (p_cfg
->conn_cfg
[i
].tid_seg
[seg
].count
)
342 return &p_cfg
->conn_cfg
[i
].tid_seg
[seg
];
346 void qed_cxt_set_srq_count(struct qed_hwfn
*p_hwfn
, u32 num_srqs
)
348 struct qed_cxt_mngr
*p_mgr
= p_hwfn
->p_cxt_mngr
;
350 p_mgr
->srq_count
= num_srqs
;
353 u32
qed_cxt_get_srq_count(struct qed_hwfn
*p_hwfn
)
355 struct qed_cxt_mngr
*p_mgr
= p_hwfn
->p_cxt_mngr
;
357 return p_mgr
->srq_count
;
360 /* set the iids count per protocol */
361 static void qed_cxt_set_proto_cid_count(struct qed_hwfn
*p_hwfn
,
362 enum protocol_type type
,
363 u32 cid_count
, u32 vf_cid_cnt
)
365 struct qed_cxt_mngr
*p_mgr
= p_hwfn
->p_cxt_mngr
;
366 struct qed_conn_type_cfg
*p_conn
= &p_mgr
->conn_cfg
[type
];
368 p_conn
->cid_count
= roundup(cid_count
, DQ_RANGE_ALIGN
);
369 p_conn
->cids_per_vf
= roundup(vf_cid_cnt
, DQ_RANGE_ALIGN
);
371 if (type
== PROTOCOLID_ROCE
) {
372 u32 page_sz
= p_mgr
->clients
[ILT_CLI_CDUC
].p_size
.val
;
373 u32 cxt_size
= CONN_CXT_SIZE(p_hwfn
);
374 u32 elems_per_page
= ILT_PAGE_IN_BYTES(page_sz
) / cxt_size
;
376 p_conn
->cid_count
= roundup(p_conn
->cid_count
, elems_per_page
);
380 u32
qed_cxt_get_proto_cid_count(struct qed_hwfn
*p_hwfn
,
381 enum protocol_type type
, u32
*vf_cid
)
384 *vf_cid
= p_hwfn
->p_cxt_mngr
->conn_cfg
[type
].cids_per_vf
;
386 return p_hwfn
->p_cxt_mngr
->conn_cfg
[type
].cid_count
;
389 u32
qed_cxt_get_proto_cid_start(struct qed_hwfn
*p_hwfn
,
390 enum protocol_type type
)
392 return p_hwfn
->p_cxt_mngr
->acquired
[type
].start_cid
;
395 u32
qed_cxt_get_proto_tid_count(struct qed_hwfn
*p_hwfn
,
396 enum protocol_type type
)
401 for (i
= 0; i
< TASK_SEGMENTS
; i
++)
402 cnt
+= p_hwfn
->p_cxt_mngr
->conn_cfg
[type
].tid_seg
[i
].count
;
407 static void qed_cxt_set_proto_tid_count(struct qed_hwfn
*p_hwfn
,
408 enum protocol_type proto
,
410 u8 seg_type
, u32 count
, bool has_fl
)
412 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
413 struct qed_tid_seg
*p_seg
= &p_mngr
->conn_cfg
[proto
].tid_seg
[seg
];
415 p_seg
->count
= count
;
416 p_seg
->has_fl_mem
= has_fl
;
417 p_seg
->type
= seg_type
;
420 static void qed_ilt_cli_blk_fill(struct qed_ilt_client_cfg
*p_cli
,
421 struct qed_ilt_cli_blk
*p_blk
,
422 u32 start_line
, u32 total_size
, u32 elem_size
)
424 u32 ilt_size
= ILT_PAGE_IN_BYTES(p_cli
->p_size
.val
);
426 /* verify thatits called only once for each block */
427 if (p_blk
->total_size
)
430 p_blk
->total_size
= total_size
;
431 p_blk
->real_size_in_page
= 0;
433 p_blk
->real_size_in_page
= (ilt_size
/ elem_size
) * elem_size
;
434 p_blk
->start_line
= start_line
;
437 static void qed_ilt_cli_adv_line(struct qed_hwfn
*p_hwfn
,
438 struct qed_ilt_client_cfg
*p_cli
,
439 struct qed_ilt_cli_blk
*p_blk
,
440 u32
*p_line
, enum ilt_clients client_id
)
442 if (!p_blk
->total_size
)
446 p_cli
->first
.val
= *p_line
;
448 p_cli
->active
= true;
449 *p_line
+= DIV_ROUND_UP(p_blk
->total_size
, p_blk
->real_size_in_page
);
450 p_cli
->last
.val
= *p_line
- 1;
452 DP_VERBOSE(p_hwfn
, QED_MSG_ILT
,
453 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n",
454 client_id
, p_cli
->first
.val
,
455 p_cli
->last
.val
, p_blk
->total_size
,
456 p_blk
->real_size_in_page
, p_blk
->start_line
);
459 static u32
qed_ilt_get_dynamic_line_cnt(struct qed_hwfn
*p_hwfn
,
460 enum ilt_clients ilt_client
)
462 u32 cid_count
= p_hwfn
->p_cxt_mngr
->conn_cfg
[PROTOCOLID_ROCE
].cid_count
;
463 struct qed_ilt_client_cfg
*p_cli
;
464 u32 lines_to_skip
= 0;
467 if (ilt_client
== ILT_CLI_CDUC
) {
468 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUC
];
470 cxts_per_p
= ILT_PAGE_IN_BYTES(p_cli
->p_size
.val
) /
471 (u32
) CONN_CXT_SIZE(p_hwfn
);
473 lines_to_skip
= cid_count
/ cxts_per_p
;
476 return lines_to_skip
;
479 int qed_cxt_cfg_ilt_compute(struct qed_hwfn
*p_hwfn
)
481 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
482 u32 curr_line
, total
, i
, task_size
, line
;
483 struct qed_ilt_client_cfg
*p_cli
;
484 struct qed_ilt_cli_blk
*p_blk
;
485 struct qed_cdu_iids cdu_iids
;
486 struct qed_src_iids src_iids
;
487 struct qed_qm_iids qm_iids
;
488 struct qed_tm_iids tm_iids
;
489 struct qed_tid_seg
*p_seg
;
491 memset(&qm_iids
, 0, sizeof(qm_iids
));
492 memset(&cdu_iids
, 0, sizeof(cdu_iids
));
493 memset(&src_iids
, 0, sizeof(src_iids
));
494 memset(&tm_iids
, 0, sizeof(tm_iids
));
496 p_mngr
->pf_start_line
= RESC_START(p_hwfn
, QED_ILT
);
498 DP_VERBOSE(p_hwfn
, QED_MSG_ILT
,
499 "hwfn [%d] - Set context manager starting line to be 0x%08x\n",
500 p_hwfn
->my_id
, p_hwfn
->p_cxt_mngr
->pf_start_line
);
503 p_cli
= &p_mngr
->clients
[ILT_CLI_CDUC
];
504 curr_line
= p_mngr
->pf_start_line
;
507 p_cli
->pf_total_lines
= 0;
509 /* get the counters for the CDUC and QM clients */
510 qed_cxt_cdu_iids(p_mngr
, &cdu_iids
);
512 p_blk
= &p_cli
->pf_blks
[CDUC_BLK
];
514 total
= cdu_iids
.pf_cids
* CONN_CXT_SIZE(p_hwfn
);
516 qed_ilt_cli_blk_fill(p_cli
, p_blk
, curr_line
,
517 total
, CONN_CXT_SIZE(p_hwfn
));
519 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
, ILT_CLI_CDUC
);
520 p_cli
->pf_total_lines
= curr_line
- p_blk
->start_line
;
522 p_blk
->dynamic_line_cnt
= qed_ilt_get_dynamic_line_cnt(p_hwfn
,
526 p_blk
= &p_cli
->vf_blks
[CDUC_BLK
];
527 total
= cdu_iids
.per_vf_cids
* CONN_CXT_SIZE(p_hwfn
);
529 qed_ilt_cli_blk_fill(p_cli
, p_blk
, curr_line
,
530 total
, CONN_CXT_SIZE(p_hwfn
));
532 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
, ILT_CLI_CDUC
);
533 p_cli
->vf_total_lines
= curr_line
- p_blk
->start_line
;
535 for (i
= 1; i
< p_mngr
->vf_count
; i
++)
536 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
540 p_cli
= &p_mngr
->clients
[ILT_CLI_CDUT
];
541 p_cli
->first
.val
= curr_line
;
543 /* first the 'working' task memory */
544 for (i
= 0; i
< NUM_TASK_PF_SEGMENTS
; i
++) {
545 p_seg
= qed_cxt_tid_seg_info(p_hwfn
, i
);
546 if (!p_seg
|| p_seg
->count
== 0)
549 p_blk
= &p_cli
->pf_blks
[CDUT_SEG_BLK(i
)];
550 total
= p_seg
->count
* p_mngr
->task_type_size
[p_seg
->type
];
551 qed_ilt_cli_blk_fill(p_cli
, p_blk
, curr_line
, total
,
552 p_mngr
->task_type_size
[p_seg
->type
]);
554 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
558 /* next the 'init' task memory (forced load memory) */
559 for (i
= 0; i
< NUM_TASK_PF_SEGMENTS
; i
++) {
560 p_seg
= qed_cxt_tid_seg_info(p_hwfn
, i
);
561 if (!p_seg
|| p_seg
->count
== 0)
564 p_blk
= &p_cli
->pf_blks
[CDUT_FL_SEG_BLK(i
, PF
)];
566 if (!p_seg
->has_fl_mem
) {
567 /* The segment is active (total size pf 'working'
568 * memory is > 0) but has no FL (forced-load, Init)
571 * 1. The total-size in the corrsponding FL block of
572 * the ILT client is set to 0 - No ILT line are
573 * provisioned and no ILT memory allocated.
575 * 2. The start-line of said block is set to the
576 * start line of the matching working memory
577 * block in the ILT client. This is later used to
578 * configure the CDU segment offset registers and
579 * results in an FL command for TIDs of this
580 * segement behaves as regular load commands
581 * (loading TIDs from the working memory).
583 line
= p_cli
->pf_blks
[CDUT_SEG_BLK(i
)].start_line
;
585 qed_ilt_cli_blk_fill(p_cli
, p_blk
, line
, 0, 0);
588 total
= p_seg
->count
* p_mngr
->task_type_size
[p_seg
->type
];
590 qed_ilt_cli_blk_fill(p_cli
, p_blk
,
592 p_mngr
->task_type_size
[p_seg
->type
]);
594 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
597 p_cli
->pf_total_lines
= curr_line
- p_cli
->pf_blks
[0].start_line
;
600 p_seg
= qed_cxt_tid_seg_info(p_hwfn
, TASK_SEGMENT_VF
);
601 if (p_seg
&& p_seg
->count
) {
602 /* Stricly speaking we need to iterate over all VF
603 * task segment types, but a VF has only 1 segment
606 /* 'working' memory */
607 total
= p_seg
->count
* p_mngr
->task_type_size
[p_seg
->type
];
609 p_blk
= &p_cli
->vf_blks
[CDUT_SEG_BLK(0)];
610 qed_ilt_cli_blk_fill(p_cli
, p_blk
,
612 p_mngr
->task_type_size
[p_seg
->type
]);
614 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
618 p_blk
= &p_cli
->vf_blks
[CDUT_FL_SEG_BLK(0, VF
)];
619 if (!p_seg
->has_fl_mem
) {
620 /* see comment above */
621 line
= p_cli
->vf_blks
[CDUT_SEG_BLK(0)].start_line
;
622 qed_ilt_cli_blk_fill(p_cli
, p_blk
, line
, 0, 0);
624 task_size
= p_mngr
->task_type_size
[p_seg
->type
];
625 qed_ilt_cli_blk_fill(p_cli
, p_blk
,
626 curr_line
, total
, task_size
);
627 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
630 p_cli
->vf_total_lines
= curr_line
-
631 p_cli
->vf_blks
[0].start_line
;
633 /* Now for the rest of the VFs */
634 for (i
= 1; i
< p_mngr
->vf_count
; i
++) {
635 p_blk
= &p_cli
->vf_blks
[CDUT_SEG_BLK(0)];
636 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
639 p_blk
= &p_cli
->vf_blks
[CDUT_FL_SEG_BLK(0, VF
)];
640 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
646 p_cli
= &p_mngr
->clients
[ILT_CLI_QM
];
647 p_blk
= &p_cli
->pf_blks
[0];
649 qed_cxt_qm_iids(p_hwfn
, &qm_iids
);
650 total
= qed_qm_pf_mem_size(p_hwfn
->rel_pf_id
, qm_iids
.cids
,
651 qm_iids
.vf_cids
, qm_iids
.tids
,
652 p_hwfn
->qm_info
.num_pqs
,
653 p_hwfn
->qm_info
.num_vf_pqs
);
657 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n",
661 p_hwfn
->qm_info
.num_pqs
, p_hwfn
->qm_info
.num_vf_pqs
, total
);
663 qed_ilt_cli_blk_fill(p_cli
, p_blk
,
664 curr_line
, total
* 0x1000,
667 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
, ILT_CLI_QM
);
668 p_cli
->pf_total_lines
= curr_line
- p_blk
->start_line
;
671 p_cli
= &p_mngr
->clients
[ILT_CLI_SRC
];
672 qed_cxt_src_iids(p_mngr
, &src_iids
);
674 /* Both the PF and VFs searcher connections are stored in the per PF
675 * database. Thus sum the PF searcher cids and all the VFs searcher
678 total
= src_iids
.pf_cids
+ src_iids
.per_vf_cids
* p_mngr
->vf_count
;
680 u32 local_max
= max_t(u32
, total
,
683 total
= roundup_pow_of_two(local_max
);
685 p_blk
= &p_cli
->pf_blks
[0];
686 qed_ilt_cli_blk_fill(p_cli
, p_blk
, curr_line
,
687 total
* sizeof(struct src_ent
),
688 sizeof(struct src_ent
));
690 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
692 p_cli
->pf_total_lines
= curr_line
- p_blk
->start_line
;
696 p_cli
= &p_mngr
->clients
[ILT_CLI_TM
];
697 qed_cxt_tm_iids(p_mngr
, &tm_iids
);
698 total
= tm_iids
.pf_cids
+ tm_iids
.pf_tids_total
;
700 p_blk
= &p_cli
->pf_blks
[0];
701 qed_ilt_cli_blk_fill(p_cli
, p_blk
, curr_line
,
702 total
* TM_ELEM_SIZE
, TM_ELEM_SIZE
);
704 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
706 p_cli
->pf_total_lines
= curr_line
- p_blk
->start_line
;
710 total
= tm_iids
.per_vf_cids
+ tm_iids
.per_vf_tids
;
712 p_blk
= &p_cli
->vf_blks
[0];
713 qed_ilt_cli_blk_fill(p_cli
, p_blk
, curr_line
,
714 total
* TM_ELEM_SIZE
, TM_ELEM_SIZE
);
716 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
718 p_cli
->pf_total_lines
= curr_line
- p_blk
->start_line
;
720 for (i
= 1; i
< p_mngr
->vf_count
; i
++)
721 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
725 /* TSDM (SRQ CONTEXT) */
726 total
= qed_cxt_get_srq_count(p_hwfn
);
729 p_cli
= &p_mngr
->clients
[ILT_CLI_TSDM
];
730 p_blk
= &p_cli
->pf_blks
[SRQ_BLK
];
731 qed_ilt_cli_blk_fill(p_cli
, p_blk
, curr_line
,
732 total
* SRQ_CXT_SIZE
, SRQ_CXT_SIZE
);
734 qed_ilt_cli_adv_line(p_hwfn
, p_cli
, p_blk
, &curr_line
,
736 p_cli
->pf_total_lines
= curr_line
- p_blk
->start_line
;
739 if (curr_line
- p_hwfn
->p_cxt_mngr
->pf_start_line
>
740 RESC_NUM(p_hwfn
, QED_ILT
)) {
741 DP_ERR(p_hwfn
, "too many ilt lines...#lines=%d\n",
742 curr_line
- p_hwfn
->p_cxt_mngr
->pf_start_line
);
749 static void qed_cxt_src_t2_free(struct qed_hwfn
*p_hwfn
)
751 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
757 for (i
= 0; i
< p_mngr
->t2_num_pages
; i
++)
758 if (p_mngr
->t2
[i
].p_virt
)
759 dma_free_coherent(&p_hwfn
->cdev
->pdev
->dev
,
761 p_mngr
->t2
[i
].p_virt
,
762 p_mngr
->t2
[i
].p_phys
);
768 static int qed_cxt_src_t2_alloc(struct qed_hwfn
*p_hwfn
)
770 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
771 u32 conn_num
, total_size
, ent_per_page
, psz
, i
;
772 struct qed_ilt_client_cfg
*p_src
;
773 struct qed_src_iids src_iids
;
774 struct qed_dma_mem
*p_t2
;
777 memset(&src_iids
, 0, sizeof(src_iids
));
779 /* if the SRC ILT client is inactive - there are no connection
780 * requiring the searcer, leave.
782 p_src
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_SRC
];
786 qed_cxt_src_iids(p_mngr
, &src_iids
);
787 conn_num
= src_iids
.pf_cids
+ src_iids
.per_vf_cids
* p_mngr
->vf_count
;
788 total_size
= conn_num
* sizeof(struct src_ent
);
790 /* use the same page size as the SRC ILT client */
791 psz
= ILT_PAGE_IN_BYTES(p_src
->p_size
.val
);
792 p_mngr
->t2_num_pages
= DIV_ROUND_UP(total_size
, psz
);
795 p_mngr
->t2
= kcalloc(p_mngr
->t2_num_pages
, sizeof(struct qed_dma_mem
),
802 /* allocate t2 pages */
803 for (i
= 0; i
< p_mngr
->t2_num_pages
; i
++) {
804 u32 size
= min_t(u32
, total_size
, psz
);
805 void **p_virt
= &p_mngr
->t2
[i
].p_virt
;
807 *p_virt
= dma_alloc_coherent(&p_hwfn
->cdev
->pdev
->dev
,
809 &p_mngr
->t2
[i
].p_phys
, GFP_KERNEL
);
810 if (!p_mngr
->t2
[i
].p_virt
) {
814 memset(*p_virt
, 0, size
);
815 p_mngr
->t2
[i
].size
= size
;
819 /* Set the t2 pointers */
821 /* entries per page - must be a power of two */
822 ent_per_page
= psz
/ sizeof(struct src_ent
);
824 p_mngr
->first_free
= (u64
) p_mngr
->t2
[0].p_phys
;
826 p_t2
= &p_mngr
->t2
[(conn_num
- 1) / ent_per_page
];
827 p_mngr
->last_free
= (u64
) p_t2
->p_phys
+
828 ((conn_num
- 1) & (ent_per_page
- 1)) * sizeof(struct src_ent
);
830 for (i
= 0; i
< p_mngr
->t2_num_pages
; i
++) {
831 u32 ent_num
= min_t(u32
,
834 struct src_ent
*entries
= p_mngr
->t2
[i
].p_virt
;
835 u64 p_ent_phys
= (u64
) p_mngr
->t2
[i
].p_phys
, val
;
838 for (j
= 0; j
< ent_num
- 1; j
++) {
839 val
= p_ent_phys
+ (j
+ 1) * sizeof(struct src_ent
);
840 entries
[j
].next
= cpu_to_be64(val
);
843 if (i
< p_mngr
->t2_num_pages
- 1)
844 val
= (u64
) p_mngr
->t2
[i
+ 1].p_phys
;
847 entries
[j
].next
= cpu_to_be64(val
);
855 qed_cxt_src_t2_free(p_hwfn
);
859 #define for_each_ilt_valid_client(pos, clients) \
860 for (pos = 0; pos < ILT_CLI_MAX; pos++) \
861 if (!clients[pos].active) { \
865 /* Total number of ILT lines used by this PF */
866 static u32
qed_cxt_ilt_shadow_size(struct qed_ilt_client_cfg
*ilt_clients
)
871 for_each_ilt_valid_client(i
, ilt_clients
)
872 size
+= (ilt_clients
[i
].last
.val
- ilt_clients
[i
].first
.val
+ 1);
877 static void qed_ilt_shadow_free(struct qed_hwfn
*p_hwfn
)
879 struct qed_ilt_client_cfg
*p_cli
= p_hwfn
->p_cxt_mngr
->clients
;
880 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
883 ilt_size
= qed_cxt_ilt_shadow_size(p_cli
);
885 for (i
= 0; p_mngr
->ilt_shadow
&& i
< ilt_size
; i
++) {
886 struct qed_dma_mem
*p_dma
= &p_mngr
->ilt_shadow
[i
];
889 dma_free_coherent(&p_hwfn
->cdev
->pdev
->dev
,
890 p_dma
->size
, p_dma
->p_virt
,
892 p_dma
->p_virt
= NULL
;
894 kfree(p_mngr
->ilt_shadow
);
897 static int qed_ilt_blk_alloc(struct qed_hwfn
*p_hwfn
,
898 struct qed_ilt_cli_blk
*p_blk
,
899 enum ilt_clients ilt_client
,
900 u32 start_line_offset
)
902 struct qed_dma_mem
*ilt_shadow
= p_hwfn
->p_cxt_mngr
->ilt_shadow
;
903 u32 lines
, line
, sz_left
, lines_to_skip
= 0;
905 /* Special handling for RoCE that supports dynamic allocation */
906 if ((p_hwfn
->hw_info
.personality
== QED_PCI_ETH_ROCE
) &&
907 ((ilt_client
== ILT_CLI_CDUT
) || ilt_client
== ILT_CLI_TSDM
))
910 lines_to_skip
= p_blk
->dynamic_line_cnt
;
912 if (!p_blk
->total_size
)
915 sz_left
= p_blk
->total_size
;
916 lines
= DIV_ROUND_UP(sz_left
, p_blk
->real_size_in_page
) - lines_to_skip
;
917 line
= p_blk
->start_line
+ start_line_offset
-
918 p_hwfn
->p_cxt_mngr
->pf_start_line
+ lines_to_skip
;
920 for (; lines
; lines
--) {
925 size
= min_t(u32
, sz_left
, p_blk
->real_size_in_page
);
926 p_virt
= dma_alloc_coherent(&p_hwfn
->cdev
->pdev
->dev
,
927 size
, &p_phys
, GFP_KERNEL
);
930 memset(p_virt
, 0, size
);
932 ilt_shadow
[line
].p_phys
= p_phys
;
933 ilt_shadow
[line
].p_virt
= p_virt
;
934 ilt_shadow
[line
].size
= size
;
936 DP_VERBOSE(p_hwfn
, QED_MSG_ILT
,
937 "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n",
938 line
, (u64
)p_phys
, p_virt
, size
);
947 static int qed_ilt_shadow_alloc(struct qed_hwfn
*p_hwfn
)
949 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
950 struct qed_ilt_client_cfg
*clients
= p_mngr
->clients
;
951 struct qed_ilt_cli_blk
*p_blk
;
955 size
= qed_cxt_ilt_shadow_size(clients
);
956 p_mngr
->ilt_shadow
= kcalloc(size
, sizeof(struct qed_dma_mem
),
958 if (!p_mngr
->ilt_shadow
) {
960 goto ilt_shadow_fail
;
963 DP_VERBOSE(p_hwfn
, QED_MSG_ILT
,
964 "Allocated 0x%x bytes for ilt shadow\n",
965 (u32
)(size
* sizeof(struct qed_dma_mem
)));
967 for_each_ilt_valid_client(i
, clients
) {
968 for (j
= 0; j
< ILT_CLI_PF_BLOCKS
; j
++) {
969 p_blk
= &clients
[i
].pf_blks
[j
];
970 rc
= qed_ilt_blk_alloc(p_hwfn
, p_blk
, i
, 0);
972 goto ilt_shadow_fail
;
974 for (k
= 0; k
< p_mngr
->vf_count
; k
++) {
975 for (j
= 0; j
< ILT_CLI_VF_BLOCKS
; j
++) {
976 u32 lines
= clients
[i
].vf_total_lines
* k
;
978 p_blk
= &clients
[i
].vf_blks
[j
];
979 rc
= qed_ilt_blk_alloc(p_hwfn
, p_blk
, i
, lines
);
981 goto ilt_shadow_fail
;
989 qed_ilt_shadow_free(p_hwfn
);
993 static void qed_cid_map_free(struct qed_hwfn
*p_hwfn
)
995 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
998 for (type
= 0; type
< MAX_CONN_TYPES
; type
++) {
999 kfree(p_mngr
->acquired
[type
].cid_map
);
1000 p_mngr
->acquired
[type
].max_count
= 0;
1001 p_mngr
->acquired
[type
].start_cid
= 0;
1005 static int qed_cid_map_alloc(struct qed_hwfn
*p_hwfn
)
1007 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1011 for (type
= 0; type
< MAX_CONN_TYPES
; type
++) {
1012 u32 cid_cnt
= p_hwfn
->p_cxt_mngr
->conn_cfg
[type
].cid_count
;
1018 size
= DIV_ROUND_UP(cid_cnt
,
1019 sizeof(unsigned long) * BITS_PER_BYTE
) *
1020 sizeof(unsigned long);
1021 p_mngr
->acquired
[type
].cid_map
= kzalloc(size
, GFP_KERNEL
);
1022 if (!p_mngr
->acquired
[type
].cid_map
)
1025 p_mngr
->acquired
[type
].max_count
= cid_cnt
;
1026 p_mngr
->acquired
[type
].start_cid
= start_cid
;
1028 p_hwfn
->p_cxt_mngr
->conn_cfg
[type
].cid_start
= start_cid
;
1030 DP_VERBOSE(p_hwfn
, QED_MSG_CXT
,
1031 "Type %08x start: %08x count %08x\n",
1032 type
, p_mngr
->acquired
[type
].start_cid
,
1033 p_mngr
->acquired
[type
].max_count
);
1034 start_cid
+= cid_cnt
;
1040 qed_cid_map_free(p_hwfn
);
1044 int qed_cxt_mngr_alloc(struct qed_hwfn
*p_hwfn
)
1046 struct qed_ilt_client_cfg
*clients
;
1047 struct qed_cxt_mngr
*p_mngr
;
1050 p_mngr
= kzalloc(sizeof(*p_mngr
), GFP_KERNEL
);
1054 /* Initialize ILT client registers */
1055 clients
= p_mngr
->clients
;
1056 clients
[ILT_CLI_CDUC
].first
.reg
= ILT_CFG_REG(CDUC
, FIRST_ILT
);
1057 clients
[ILT_CLI_CDUC
].last
.reg
= ILT_CFG_REG(CDUC
, LAST_ILT
);
1058 clients
[ILT_CLI_CDUC
].p_size
.reg
= ILT_CFG_REG(CDUC
, P_SIZE
);
1060 clients
[ILT_CLI_QM
].first
.reg
= ILT_CFG_REG(QM
, FIRST_ILT
);
1061 clients
[ILT_CLI_QM
].last
.reg
= ILT_CFG_REG(QM
, LAST_ILT
);
1062 clients
[ILT_CLI_QM
].p_size
.reg
= ILT_CFG_REG(QM
, P_SIZE
);
1064 clients
[ILT_CLI_TM
].first
.reg
= ILT_CFG_REG(TM
, FIRST_ILT
);
1065 clients
[ILT_CLI_TM
].last
.reg
= ILT_CFG_REG(TM
, LAST_ILT
);
1066 clients
[ILT_CLI_TM
].p_size
.reg
= ILT_CFG_REG(TM
, P_SIZE
);
1068 clients
[ILT_CLI_SRC
].first
.reg
= ILT_CFG_REG(SRC
, FIRST_ILT
);
1069 clients
[ILT_CLI_SRC
].last
.reg
= ILT_CFG_REG(SRC
, LAST_ILT
);
1070 clients
[ILT_CLI_SRC
].p_size
.reg
= ILT_CFG_REG(SRC
, P_SIZE
);
1072 clients
[ILT_CLI_CDUT
].first
.reg
= ILT_CFG_REG(CDUT
, FIRST_ILT
);
1073 clients
[ILT_CLI_CDUT
].last
.reg
= ILT_CFG_REG(CDUT
, LAST_ILT
);
1074 clients
[ILT_CLI_CDUT
].p_size
.reg
= ILT_CFG_REG(CDUT
, P_SIZE
);
1076 clients
[ILT_CLI_TSDM
].first
.reg
= ILT_CFG_REG(TSDM
, FIRST_ILT
);
1077 clients
[ILT_CLI_TSDM
].last
.reg
= ILT_CFG_REG(TSDM
, LAST_ILT
);
1078 clients
[ILT_CLI_TSDM
].p_size
.reg
= ILT_CFG_REG(TSDM
, P_SIZE
);
1079 /* default ILT page size for all clients is 32K */
1080 for (i
= 0; i
< ILT_CLI_MAX
; i
++)
1081 p_mngr
->clients
[i
].p_size
.val
= ILT_DEFAULT_HW_P_SIZE
;
1083 /* Initialize task sizes */
1084 p_mngr
->task_type_size
[0] = TYPE0_TASK_CXT_SIZE(p_hwfn
);
1085 p_mngr
->task_type_size
[1] = TYPE1_TASK_CXT_SIZE(p_hwfn
);
1087 if (p_hwfn
->cdev
->p_iov_info
)
1088 p_mngr
->vf_count
= p_hwfn
->cdev
->p_iov_info
->total_vfs
;
1089 /* Initialize the dynamic ILT allocation mutex */
1090 mutex_init(&p_mngr
->mutex
);
1092 /* Set the cxt mangr pointer priori to further allocations */
1093 p_hwfn
->p_cxt_mngr
= p_mngr
;
1098 int qed_cxt_tables_alloc(struct qed_hwfn
*p_hwfn
)
1102 /* Allocate the ILT shadow table */
1103 rc
= qed_ilt_shadow_alloc(p_hwfn
);
1105 goto tables_alloc_fail
;
1107 /* Allocate the T2 table */
1108 rc
= qed_cxt_src_t2_alloc(p_hwfn
);
1110 goto tables_alloc_fail
;
1112 /* Allocate and initialize the acquired cids bitmaps */
1113 rc
= qed_cid_map_alloc(p_hwfn
);
1115 goto tables_alloc_fail
;
1120 qed_cxt_mngr_free(p_hwfn
);
1124 void qed_cxt_mngr_free(struct qed_hwfn
*p_hwfn
)
1126 if (!p_hwfn
->p_cxt_mngr
)
1129 qed_cid_map_free(p_hwfn
);
1130 qed_cxt_src_t2_free(p_hwfn
);
1131 qed_ilt_shadow_free(p_hwfn
);
1132 kfree(p_hwfn
->p_cxt_mngr
);
1134 p_hwfn
->p_cxt_mngr
= NULL
;
1137 void qed_cxt_mngr_setup(struct qed_hwfn
*p_hwfn
)
1139 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1142 /* Reset acquired cids */
1143 for (type
= 0; type
< MAX_CONN_TYPES
; type
++) {
1144 u32 cid_cnt
= p_hwfn
->p_cxt_mngr
->conn_cfg
[type
].cid_count
;
1149 memset(p_mngr
->acquired
[type
].cid_map
, 0,
1150 DIV_ROUND_UP(cid_cnt
,
1151 sizeof(unsigned long) * BITS_PER_BYTE
) *
1152 sizeof(unsigned long));
1157 #define CDUC_CXT_SIZE_SHIFT \
1158 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1160 #define CDUC_CXT_SIZE_MASK \
1161 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1163 #define CDUC_BLOCK_WASTE_SHIFT \
1164 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1166 #define CDUC_BLOCK_WASTE_MASK \
1167 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1169 #define CDUC_NCIB_SHIFT \
1170 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1172 #define CDUC_NCIB_MASK \
1173 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1175 #define CDUT_TYPE0_CXT_SIZE_SHIFT \
1176 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1178 #define CDUT_TYPE0_CXT_SIZE_MASK \
1179 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \
1180 CDUT_TYPE0_CXT_SIZE_SHIFT)
1182 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \
1183 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1185 #define CDUT_TYPE0_BLOCK_WASTE_MASK \
1186 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \
1187 CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1189 #define CDUT_TYPE0_NCIB_SHIFT \
1190 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1192 #define CDUT_TYPE0_NCIB_MASK \
1193 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \
1194 CDUT_TYPE0_NCIB_SHIFT)
1196 #define CDUT_TYPE1_CXT_SIZE_SHIFT \
1197 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1199 #define CDUT_TYPE1_CXT_SIZE_MASK \
1200 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \
1201 CDUT_TYPE1_CXT_SIZE_SHIFT)
1203 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \
1204 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1206 #define CDUT_TYPE1_BLOCK_WASTE_MASK \
1207 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \
1208 CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1210 #define CDUT_TYPE1_NCIB_SHIFT \
1211 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1213 #define CDUT_TYPE1_NCIB_MASK \
1214 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \
1215 CDUT_TYPE1_NCIB_SHIFT)
1217 static void qed_cdu_init_common(struct qed_hwfn
*p_hwfn
)
1219 u32 page_sz
, elems_per_page
, block_waste
, cxt_size
, cdu_params
= 0;
1221 /* CDUC - connection configuration */
1222 page_sz
= p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUC
].p_size
.val
;
1223 cxt_size
= CONN_CXT_SIZE(p_hwfn
);
1224 elems_per_page
= ILT_PAGE_IN_BYTES(page_sz
) / cxt_size
;
1225 block_waste
= ILT_PAGE_IN_BYTES(page_sz
) - elems_per_page
* cxt_size
;
1227 SET_FIELD(cdu_params
, CDUC_CXT_SIZE
, cxt_size
);
1228 SET_FIELD(cdu_params
, CDUC_BLOCK_WASTE
, block_waste
);
1229 SET_FIELD(cdu_params
, CDUC_NCIB
, elems_per_page
);
1230 STORE_RT_REG(p_hwfn
, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET
, cdu_params
);
1232 /* CDUT - type-0 tasks configuration */
1233 page_sz
= p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUT
].p_size
.val
;
1234 cxt_size
= p_hwfn
->p_cxt_mngr
->task_type_size
[0];
1235 elems_per_page
= ILT_PAGE_IN_BYTES(page_sz
) / cxt_size
;
1236 block_waste
= ILT_PAGE_IN_BYTES(page_sz
) - elems_per_page
* cxt_size
;
1238 /* cxt size and block-waste are multipes of 8 */
1240 SET_FIELD(cdu_params
, CDUT_TYPE0_CXT_SIZE
, (cxt_size
>> 3));
1241 SET_FIELD(cdu_params
, CDUT_TYPE0_BLOCK_WASTE
, (block_waste
>> 3));
1242 SET_FIELD(cdu_params
, CDUT_TYPE0_NCIB
, elems_per_page
);
1243 STORE_RT_REG(p_hwfn
, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET
, cdu_params
);
1245 /* CDUT - type-1 tasks configuration */
1246 cxt_size
= p_hwfn
->p_cxt_mngr
->task_type_size
[1];
1247 elems_per_page
= ILT_PAGE_IN_BYTES(page_sz
) / cxt_size
;
1248 block_waste
= ILT_PAGE_IN_BYTES(page_sz
) - elems_per_page
* cxt_size
;
1250 /* cxt size and block-waste are multipes of 8 */
1252 SET_FIELD(cdu_params
, CDUT_TYPE1_CXT_SIZE
, (cxt_size
>> 3));
1253 SET_FIELD(cdu_params
, CDUT_TYPE1_BLOCK_WASTE
, (block_waste
>> 3));
1254 SET_FIELD(cdu_params
, CDUT_TYPE1_NCIB
, elems_per_page
);
1255 STORE_RT_REG(p_hwfn
, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET
, cdu_params
);
1259 #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1260 #define CDU_SEG_REG_TYPE_MASK 0x1
1261 #define CDU_SEG_REG_OFFSET_SHIFT 0
1262 #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1264 static void qed_cdu_init_pf(struct qed_hwfn
*p_hwfn
)
1266 struct qed_ilt_client_cfg
*p_cli
;
1267 struct qed_tid_seg
*p_seg
;
1268 u32 cdu_seg_params
, offset
;
1271 static const u32 rt_type_offset_arr
[] = {
1272 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET
,
1273 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET
,
1274 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET
,
1275 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1278 static const u32 rt_type_offset_fl_arr
[] = {
1279 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET
,
1280 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET
,
1281 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET
,
1282 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1285 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUT
];
1287 /* There are initializations only for CDUT during pf Phase */
1288 for (i
= 0; i
< NUM_TASK_PF_SEGMENTS
; i
++) {
1290 p_seg
= qed_cxt_tid_seg_info(p_hwfn
, i
);
1294 /* Note: start_line is already adjusted for the CDU
1295 * segment register granularity, so we just need to
1296 * divide. Adjustment is implicit as we assume ILT
1297 * Page size is larger than 32K!
1299 offset
= (ILT_PAGE_IN_BYTES(p_cli
->p_size
.val
) *
1300 (p_cli
->pf_blks
[CDUT_SEG_BLK(i
)].start_line
-
1301 p_cli
->first
.val
)) / CDUT_SEG_ALIGNMET_IN_BYTES
;
1304 SET_FIELD(cdu_seg_params
, CDU_SEG_REG_TYPE
, p_seg
->type
);
1305 SET_FIELD(cdu_seg_params
, CDU_SEG_REG_OFFSET
, offset
);
1306 STORE_RT_REG(p_hwfn
, rt_type_offset_arr
[i
], cdu_seg_params
);
1308 offset
= (ILT_PAGE_IN_BYTES(p_cli
->p_size
.val
) *
1309 (p_cli
->pf_blks
[CDUT_FL_SEG_BLK(i
, PF
)].start_line
-
1310 p_cli
->first
.val
)) / CDUT_SEG_ALIGNMET_IN_BYTES
;
1313 SET_FIELD(cdu_seg_params
, CDU_SEG_REG_TYPE
, p_seg
->type
);
1314 SET_FIELD(cdu_seg_params
, CDU_SEG_REG_OFFSET
, offset
);
1315 STORE_RT_REG(p_hwfn
, rt_type_offset_fl_arr
[i
], cdu_seg_params
);
1319 void qed_qm_init_pf(struct qed_hwfn
*p_hwfn
)
1321 struct qed_qm_pf_rt_init_params params
;
1322 struct qed_qm_info
*qm_info
= &p_hwfn
->qm_info
;
1323 struct qed_qm_iids iids
;
1325 memset(&iids
, 0, sizeof(iids
));
1326 qed_cxt_qm_iids(p_hwfn
, &iids
);
1328 memset(¶ms
, 0, sizeof(params
));
1329 params
.port_id
= p_hwfn
->port_id
;
1330 params
.pf_id
= p_hwfn
->rel_pf_id
;
1331 params
.max_phys_tcs_per_port
= qm_info
->max_phys_tcs_per_port
;
1332 params
.is_first_pf
= p_hwfn
->first_on_engine
;
1333 params
.num_pf_cids
= iids
.cids
;
1334 params
.num_vf_cids
= iids
.vf_cids
;
1335 params
.start_pq
= qm_info
->start_pq
;
1336 params
.num_pf_pqs
= qm_info
->num_pqs
- qm_info
->num_vf_pqs
;
1337 params
.num_vf_pqs
= qm_info
->num_vf_pqs
;
1338 params
.start_vport
= qm_info
->start_vport
;
1339 params
.num_vports
= qm_info
->num_vports
;
1340 params
.pf_wfq
= qm_info
->pf_wfq
;
1341 params
.pf_rl
= qm_info
->pf_rl
;
1342 params
.pq_params
= qm_info
->qm_pq_params
;
1343 params
.vport_params
= qm_info
->qm_vport_params
;
1345 qed_qm_pf_rt_init(p_hwfn
, p_hwfn
->p_main_ptt
, ¶ms
);
1349 static int qed_cm_init_pf(struct qed_hwfn
*p_hwfn
)
1351 union qed_qm_pq_params pq_params
;
1354 /* XCM pure-LB queue */
1355 memset(&pq_params
, 0, sizeof(pq_params
));
1356 pq_params
.core
.tc
= LB_TC
;
1357 pq
= qed_get_qm_pq(p_hwfn
, PROTOCOLID_CORE
, &pq_params
);
1358 STORE_RT_REG(p_hwfn
, XCM_REG_CON_PHY_Q3_RT_OFFSET
, pq
);
1364 static void qed_dq_init_pf(struct qed_hwfn
*p_hwfn
)
1366 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1367 u32 dq_pf_max_cid
= 0, dq_vf_max_cid
= 0;
1369 dq_pf_max_cid
+= (p_mngr
->conn_cfg
[0].cid_count
>> DQ_RANGE_SHIFT
);
1370 STORE_RT_REG(p_hwfn
, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET
, dq_pf_max_cid
);
1372 dq_vf_max_cid
+= (p_mngr
->conn_cfg
[0].cids_per_vf
>> DQ_RANGE_SHIFT
);
1373 STORE_RT_REG(p_hwfn
, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET
, dq_vf_max_cid
);
1375 dq_pf_max_cid
+= (p_mngr
->conn_cfg
[1].cid_count
>> DQ_RANGE_SHIFT
);
1376 STORE_RT_REG(p_hwfn
, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET
, dq_pf_max_cid
);
1378 dq_vf_max_cid
+= (p_mngr
->conn_cfg
[1].cids_per_vf
>> DQ_RANGE_SHIFT
);
1379 STORE_RT_REG(p_hwfn
, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET
, dq_vf_max_cid
);
1381 dq_pf_max_cid
+= (p_mngr
->conn_cfg
[2].cid_count
>> DQ_RANGE_SHIFT
);
1382 STORE_RT_REG(p_hwfn
, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET
, dq_pf_max_cid
);
1384 dq_vf_max_cid
+= (p_mngr
->conn_cfg
[2].cids_per_vf
>> DQ_RANGE_SHIFT
);
1385 STORE_RT_REG(p_hwfn
, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET
, dq_vf_max_cid
);
1387 dq_pf_max_cid
+= (p_mngr
->conn_cfg
[3].cid_count
>> DQ_RANGE_SHIFT
);
1388 STORE_RT_REG(p_hwfn
, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET
, dq_pf_max_cid
);
1390 dq_vf_max_cid
+= (p_mngr
->conn_cfg
[3].cids_per_vf
>> DQ_RANGE_SHIFT
);
1391 STORE_RT_REG(p_hwfn
, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET
, dq_vf_max_cid
);
1393 dq_pf_max_cid
+= (p_mngr
->conn_cfg
[4].cid_count
>> DQ_RANGE_SHIFT
);
1394 STORE_RT_REG(p_hwfn
, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET
, dq_pf_max_cid
);
1396 dq_vf_max_cid
+= (p_mngr
->conn_cfg
[4].cids_per_vf
>> DQ_RANGE_SHIFT
);
1397 STORE_RT_REG(p_hwfn
, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET
, dq_vf_max_cid
);
1399 dq_pf_max_cid
+= (p_mngr
->conn_cfg
[5].cid_count
>> DQ_RANGE_SHIFT
);
1400 STORE_RT_REG(p_hwfn
, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET
, dq_pf_max_cid
);
1402 dq_vf_max_cid
+= (p_mngr
->conn_cfg
[5].cids_per_vf
>> DQ_RANGE_SHIFT
);
1403 STORE_RT_REG(p_hwfn
, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET
, dq_vf_max_cid
);
1405 /* Connection types 6 & 7 are not in use, yet they must be configured
1406 * as the highest possible connection. Not configuring them means the
1407 * defaults will be used, and with a large number of cids a bug may
1408 * occur, if the defaults will be smaller than dq_pf_max_cid /
1411 STORE_RT_REG(p_hwfn
, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET
, dq_pf_max_cid
);
1412 STORE_RT_REG(p_hwfn
, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET
, dq_vf_max_cid
);
1414 STORE_RT_REG(p_hwfn
, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET
, dq_pf_max_cid
);
1415 STORE_RT_REG(p_hwfn
, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET
, dq_vf_max_cid
);
1418 static void qed_ilt_bounds_init(struct qed_hwfn
*p_hwfn
)
1420 struct qed_ilt_client_cfg
*ilt_clients
;
1423 ilt_clients
= p_hwfn
->p_cxt_mngr
->clients
;
1424 for_each_ilt_valid_client(i
, ilt_clients
) {
1425 STORE_RT_REG(p_hwfn
,
1426 ilt_clients
[i
].first
.reg
,
1427 ilt_clients
[i
].first
.val
);
1428 STORE_RT_REG(p_hwfn
,
1429 ilt_clients
[i
].last
.reg
, ilt_clients
[i
].last
.val
);
1430 STORE_RT_REG(p_hwfn
,
1431 ilt_clients
[i
].p_size
.reg
,
1432 ilt_clients
[i
].p_size
.val
);
1436 static void qed_ilt_vf_bounds_init(struct qed_hwfn
*p_hwfn
)
1438 struct qed_ilt_client_cfg
*p_cli
;
1441 /* For simplicty we set the 'block' to be an ILT page */
1442 if (p_hwfn
->cdev
->p_iov_info
) {
1443 struct qed_hw_sriov_info
*p_iov
= p_hwfn
->cdev
->p_iov_info
;
1445 STORE_RT_REG(p_hwfn
,
1446 PSWRQ2_REG_VF_BASE_RT_OFFSET
,
1447 p_iov
->first_vf_in_pf
);
1448 STORE_RT_REG(p_hwfn
,
1449 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET
,
1450 p_iov
->first_vf_in_pf
+ p_iov
->total_vfs
);
1453 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUC
];
1454 blk_factor
= ilog2(ILT_PAGE_IN_BYTES(p_cli
->p_size
.val
) >> 10);
1455 if (p_cli
->active
) {
1456 STORE_RT_REG(p_hwfn
,
1457 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET
,
1459 STORE_RT_REG(p_hwfn
,
1460 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET
,
1461 p_cli
->pf_total_lines
);
1462 STORE_RT_REG(p_hwfn
,
1463 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET
,
1464 p_cli
->vf_total_lines
);
1467 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUT
];
1468 blk_factor
= ilog2(ILT_PAGE_IN_BYTES(p_cli
->p_size
.val
) >> 10);
1469 if (p_cli
->active
) {
1470 STORE_RT_REG(p_hwfn
,
1471 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET
,
1473 STORE_RT_REG(p_hwfn
,
1474 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET
,
1475 p_cli
->pf_total_lines
);
1476 STORE_RT_REG(p_hwfn
,
1477 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET
,
1478 p_cli
->vf_total_lines
);
1481 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_TM
];
1482 blk_factor
= ilog2(ILT_PAGE_IN_BYTES(p_cli
->p_size
.val
) >> 10);
1483 if (p_cli
->active
) {
1484 STORE_RT_REG(p_hwfn
,
1485 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET
, blk_factor
);
1486 STORE_RT_REG(p_hwfn
,
1487 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET
,
1488 p_cli
->pf_total_lines
);
1489 STORE_RT_REG(p_hwfn
,
1490 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET
,
1491 p_cli
->vf_total_lines
);
1495 /* ILT (PSWRQ2) PF */
1496 static void qed_ilt_init_pf(struct qed_hwfn
*p_hwfn
)
1498 struct qed_ilt_client_cfg
*clients
;
1499 struct qed_cxt_mngr
*p_mngr
;
1500 struct qed_dma_mem
*p_shdw
;
1501 u32 line
, rt_offst
, i
;
1503 qed_ilt_bounds_init(p_hwfn
);
1504 qed_ilt_vf_bounds_init(p_hwfn
);
1506 p_mngr
= p_hwfn
->p_cxt_mngr
;
1507 p_shdw
= p_mngr
->ilt_shadow
;
1508 clients
= p_hwfn
->p_cxt_mngr
->clients
;
1510 for_each_ilt_valid_client(i
, clients
) {
1511 /** Client's 1st val and RT array are absolute, ILT shadows'
1512 * lines are relative.
1514 line
= clients
[i
].first
.val
- p_mngr
->pf_start_line
;
1515 rt_offst
= PSWRQ2_REG_ILT_MEMORY_RT_OFFSET
+
1516 clients
[i
].first
.val
* ILT_ENTRY_IN_REGS
;
1518 for (; line
<= clients
[i
].last
.val
- p_mngr
->pf_start_line
;
1519 line
++, rt_offst
+= ILT_ENTRY_IN_REGS
) {
1520 u64 ilt_hw_entry
= 0;
1522 /** p_virt could be NULL incase of dynamic
1525 if (p_shdw
[line
].p_virt
) {
1526 SET_FIELD(ilt_hw_entry
, ILT_ENTRY_VALID
, 1ULL);
1527 SET_FIELD(ilt_hw_entry
, ILT_ENTRY_PHY_ADDR
,
1528 (p_shdw
[line
].p_phys
>> 12));
1530 DP_VERBOSE(p_hwfn
, QED_MSG_ILT
,
1531 "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n",
1533 (u64
)(p_shdw
[line
].p_phys
>> 12));
1536 STORE_RT_REG_AGG(p_hwfn
, rt_offst
, ilt_hw_entry
);
1541 /* SRC (Searcher) PF */
1542 static void qed_src_init_pf(struct qed_hwfn
*p_hwfn
)
1544 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1545 u32 rounded_conn_num
, conn_num
, conn_max
;
1546 struct qed_src_iids src_iids
;
1548 memset(&src_iids
, 0, sizeof(src_iids
));
1549 qed_cxt_src_iids(p_mngr
, &src_iids
);
1550 conn_num
= src_iids
.pf_cids
+ src_iids
.per_vf_cids
* p_mngr
->vf_count
;
1554 conn_max
= max_t(u32
, conn_num
, SRC_MIN_NUM_ELEMS
);
1555 rounded_conn_num
= roundup_pow_of_two(conn_max
);
1557 STORE_RT_REG(p_hwfn
, SRC_REG_COUNTFREE_RT_OFFSET
, conn_num
);
1558 STORE_RT_REG(p_hwfn
, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET
,
1559 ilog2(rounded_conn_num
));
1561 STORE_RT_REG_AGG(p_hwfn
, SRC_REG_FIRSTFREE_RT_OFFSET
,
1562 p_hwfn
->p_cxt_mngr
->first_free
);
1563 STORE_RT_REG_AGG(p_hwfn
, SRC_REG_LASTFREE_RT_OFFSET
,
1564 p_hwfn
->p_cxt_mngr
->last_free
);
1568 #define TM_CFG_NUM_IDS_SHIFT 0
1569 #define TM_CFG_NUM_IDS_MASK 0xFFFFULL
1570 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16
1571 #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL
1572 #define TM_CFG_PARENT_PF_SHIFT 25
1573 #define TM_CFG_PARENT_PF_MASK 0x7ULL
1575 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30
1576 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL
1578 #define TM_CFG_TID_OFFSET_SHIFT 30
1579 #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL
1580 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49
1581 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL
1583 static void qed_tm_init_pf(struct qed_hwfn
*p_hwfn
)
1585 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1586 u32 active_seg_mask
= 0, tm_offset
, rt_reg
;
1587 struct qed_tm_iids tm_iids
;
1591 memset(&tm_iids
, 0, sizeof(tm_iids
));
1592 qed_cxt_tm_iids(p_mngr
, &tm_iids
);
1594 /* @@@TBD No pre-scan for now */
1596 /* Note: We assume consecutive VFs for a PF */
1597 for (i
= 0; i
< p_mngr
->vf_count
; i
++) {
1599 SET_FIELD(cfg_word
, TM_CFG_NUM_IDS
, tm_iids
.per_vf_cids
);
1600 SET_FIELD(cfg_word
, TM_CFG_PRE_SCAN_OFFSET
, 0);
1601 SET_FIELD(cfg_word
, TM_CFG_PARENT_PF
, p_hwfn
->rel_pf_id
);
1602 SET_FIELD(cfg_word
, TM_CFG_CID_PRE_SCAN_ROWS
, 0);
1603 rt_reg
= TM_REG_CONFIG_CONN_MEM_RT_OFFSET
+
1604 (sizeof(cfg_word
) / sizeof(u32
)) *
1605 (p_hwfn
->cdev
->p_iov_info
->first_vf_in_pf
+ i
);
1606 STORE_RT_REG_AGG(p_hwfn
, rt_reg
, cfg_word
);
1610 SET_FIELD(cfg_word
, TM_CFG_NUM_IDS
, tm_iids
.pf_cids
);
1611 SET_FIELD(cfg_word
, TM_CFG_PRE_SCAN_OFFSET
, 0);
1612 SET_FIELD(cfg_word
, TM_CFG_PARENT_PF
, 0); /* n/a for PF */
1613 SET_FIELD(cfg_word
, TM_CFG_CID_PRE_SCAN_ROWS
, 0); /* scan all */
1615 rt_reg
= TM_REG_CONFIG_CONN_MEM_RT_OFFSET
+
1616 (sizeof(cfg_word
) / sizeof(u32
)) *
1617 (NUM_OF_VFS(p_hwfn
->cdev
) + p_hwfn
->rel_pf_id
);
1618 STORE_RT_REG_AGG(p_hwfn
, rt_reg
, cfg_word
);
1621 STORE_RT_REG(p_hwfn
, TM_REG_PF_ENABLE_CONN_RT_OFFSET
,
1622 tm_iids
.pf_cids
? 0x1 : 0x0);
1624 /* @@@TBD how to enable the scan for the VFs */
1626 tm_offset
= tm_iids
.per_vf_cids
;
1628 /* Note: We assume consecutive VFs for a PF */
1629 for (i
= 0; i
< p_mngr
->vf_count
; i
++) {
1631 SET_FIELD(cfg_word
, TM_CFG_NUM_IDS
, tm_iids
.per_vf_tids
);
1632 SET_FIELD(cfg_word
, TM_CFG_PRE_SCAN_OFFSET
, 0);
1633 SET_FIELD(cfg_word
, TM_CFG_PARENT_PF
, p_hwfn
->rel_pf_id
);
1634 SET_FIELD(cfg_word
, TM_CFG_TID_OFFSET
, tm_offset
);
1635 SET_FIELD(cfg_word
, TM_CFG_TID_PRE_SCAN_ROWS
, (u64
) 0);
1637 rt_reg
= TM_REG_CONFIG_TASK_MEM_RT_OFFSET
+
1638 (sizeof(cfg_word
) / sizeof(u32
)) *
1639 (p_hwfn
->cdev
->p_iov_info
->first_vf_in_pf
+ i
);
1641 STORE_RT_REG_AGG(p_hwfn
, rt_reg
, cfg_word
);
1644 tm_offset
= tm_iids
.pf_cids
;
1645 for (i
= 0; i
< NUM_TASK_PF_SEGMENTS
; i
++) {
1647 SET_FIELD(cfg_word
, TM_CFG_NUM_IDS
, tm_iids
.pf_tids
[i
]);
1648 SET_FIELD(cfg_word
, TM_CFG_PRE_SCAN_OFFSET
, 0);
1649 SET_FIELD(cfg_word
, TM_CFG_PARENT_PF
, 0);
1650 SET_FIELD(cfg_word
, TM_CFG_TID_OFFSET
, tm_offset
);
1651 SET_FIELD(cfg_word
, TM_CFG_TID_PRE_SCAN_ROWS
, (u64
) 0);
1653 rt_reg
= TM_REG_CONFIG_TASK_MEM_RT_OFFSET
+
1654 (sizeof(cfg_word
) / sizeof(u32
)) *
1655 (NUM_OF_VFS(p_hwfn
->cdev
) +
1656 p_hwfn
->rel_pf_id
* NUM_TASK_PF_SEGMENTS
+ i
);
1658 STORE_RT_REG_AGG(p_hwfn
, rt_reg
, cfg_word
);
1659 active_seg_mask
|= (tm_iids
.pf_tids
[i
] ? BIT(i
) : 0);
1661 tm_offset
+= tm_iids
.pf_tids
[i
];
1664 if (p_hwfn
->hw_info
.personality
== QED_PCI_ETH_ROCE
)
1665 active_seg_mask
= 0;
1667 STORE_RT_REG(p_hwfn
, TM_REG_PF_ENABLE_TASK_RT_OFFSET
, active_seg_mask
);
1669 /* @@@TBD how to enable the scan for the VFs */
1672 void qed_cxt_hw_init_common(struct qed_hwfn
*p_hwfn
)
1674 qed_cdu_init_common(p_hwfn
);
1677 void qed_cxt_hw_init_pf(struct qed_hwfn
*p_hwfn
)
1679 qed_qm_init_pf(p_hwfn
);
1680 qed_cm_init_pf(p_hwfn
);
1681 qed_dq_init_pf(p_hwfn
);
1682 qed_cdu_init_pf(p_hwfn
);
1683 qed_ilt_init_pf(p_hwfn
);
1684 qed_src_init_pf(p_hwfn
);
1685 qed_tm_init_pf(p_hwfn
);
1688 int qed_cxt_acquire_cid(struct qed_hwfn
*p_hwfn
,
1689 enum protocol_type type
, u32
*p_cid
)
1691 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1694 if (type
>= MAX_CONN_TYPES
|| !p_mngr
->acquired
[type
].cid_map
) {
1695 DP_NOTICE(p_hwfn
, "Invalid protocol type %d", type
);
1699 rel_cid
= find_first_zero_bit(p_mngr
->acquired
[type
].cid_map
,
1700 p_mngr
->acquired
[type
].max_count
);
1702 if (rel_cid
>= p_mngr
->acquired
[type
].max_count
) {
1703 DP_NOTICE(p_hwfn
, "no CID available for protocol %d\n", type
);
1707 __set_bit(rel_cid
, p_mngr
->acquired
[type
].cid_map
);
1709 *p_cid
= rel_cid
+ p_mngr
->acquired
[type
].start_cid
;
1714 static bool qed_cxt_test_cid_acquired(struct qed_hwfn
*p_hwfn
,
1715 u32 cid
, enum protocol_type
*p_type
)
1717 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1718 struct qed_cid_acquired_map
*p_map
;
1719 enum protocol_type p
;
1722 /* Iterate over protocols and find matching cid range */
1723 for (p
= 0; p
< MAX_CONN_TYPES
; p
++) {
1724 p_map
= &p_mngr
->acquired
[p
];
1726 if (!p_map
->cid_map
)
1728 if (cid
>= p_map
->start_cid
&&
1729 cid
< p_map
->start_cid
+ p_map
->max_count
)
1734 if (p
== MAX_CONN_TYPES
) {
1735 DP_NOTICE(p_hwfn
, "Invalid CID %d", cid
);
1739 rel_cid
= cid
- p_map
->start_cid
;
1740 if (!test_bit(rel_cid
, p_map
->cid_map
)) {
1741 DP_NOTICE(p_hwfn
, "CID %d not acquired", cid
);
1747 void qed_cxt_release_cid(struct qed_hwfn
*p_hwfn
, u32 cid
)
1749 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1750 enum protocol_type type
;
1754 /* Test acquired and find matching per-protocol map */
1755 b_acquired
= qed_cxt_test_cid_acquired(p_hwfn
, cid
, &type
);
1760 rel_cid
= cid
- p_mngr
->acquired
[type
].start_cid
;
1761 __clear_bit(rel_cid
, p_mngr
->acquired
[type
].cid_map
);
1764 int qed_cxt_get_cid_info(struct qed_hwfn
*p_hwfn
, struct qed_cxt_info
*p_info
)
1766 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1767 u32 conn_cxt_size
, hw_p_size
, cxts_per_p
, line
;
1768 enum protocol_type type
;
1771 /* Test acquired and find matching per-protocol map */
1772 b_acquired
= qed_cxt_test_cid_acquired(p_hwfn
, p_info
->iid
, &type
);
1777 /* set the protocl type */
1778 p_info
->type
= type
;
1780 /* compute context virtual pointer */
1781 hw_p_size
= p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUC
].p_size
.val
;
1783 conn_cxt_size
= CONN_CXT_SIZE(p_hwfn
);
1784 cxts_per_p
= ILT_PAGE_IN_BYTES(hw_p_size
) / conn_cxt_size
;
1785 line
= p_info
->iid
/ cxts_per_p
;
1787 /* Make sure context is allocated (dynamic allocation) */
1788 if (!p_mngr
->ilt_shadow
[line
].p_virt
)
1791 p_info
->p_cxt
= p_mngr
->ilt_shadow
[line
].p_virt
+
1792 p_info
->iid
% cxts_per_p
* conn_cxt_size
;
1794 DP_VERBOSE(p_hwfn
, (QED_MSG_ILT
| QED_MSG_CXT
),
1795 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
1796 p_info
->iid
/ cxts_per_p
, p_info
->p_cxt
, p_info
->iid
);
1801 void qed_rdma_set_pf_params(struct qed_hwfn
*p_hwfn
,
1802 struct qed_rdma_pf_params
*p_params
)
1804 u32 num_cons
, num_tasks
, num_qps
, num_mrs
, num_srqs
;
1805 enum protocol_type proto
;
1807 num_mrs
= min_t(u32
, RDMA_MAX_TIDS
, p_params
->num_mrs
);
1808 num_tasks
= num_mrs
; /* each mr uses a single task id */
1809 num_srqs
= min_t(u32
, 32 * 1024, p_params
->num_srqs
);
1811 switch (p_hwfn
->hw_info
.personality
) {
1812 case QED_PCI_ETH_ROCE
:
1813 num_qps
= min_t(u32
, ROCE_MAX_QPS
, p_params
->num_qps
);
1814 num_cons
= num_qps
* 2; /* each QP requires two connections */
1815 proto
= PROTOCOLID_ROCE
;
1821 if (num_cons
&& num_tasks
) {
1822 qed_cxt_set_proto_cid_count(p_hwfn
, proto
, num_cons
, 0);
1824 /* Deliberatly passing ROCE for tasks id. This is because
1825 * iWARP / RoCE share the task id.
1827 qed_cxt_set_proto_tid_count(p_hwfn
, PROTOCOLID_ROCE
,
1828 QED_CXT_ROCE_TID_SEG
, 1,
1830 qed_cxt_set_srq_count(p_hwfn
, num_srqs
);
1832 DP_INFO(p_hwfn
->cdev
,
1833 "RDMA personality used without setting params!\n");
1837 int qed_cxt_set_pf_params(struct qed_hwfn
*p_hwfn
)
1839 /* Set the number of required CORE connections */
1840 u32 core_cids
= 1; /* SPQ */
1842 qed_cxt_set_proto_cid_count(p_hwfn
, PROTOCOLID_CORE
, core_cids
, 0);
1844 switch (p_hwfn
->hw_info
.personality
) {
1845 case QED_PCI_ETH_ROCE
:
1847 qed_rdma_set_pf_params(p_hwfn
,
1849 pf_params
.rdma_pf_params
);
1850 /* no need for break since RoCE coexist with Ethernet */
1854 struct qed_eth_pf_params
*p_params
=
1855 &p_hwfn
->pf_params
.eth_pf_params
;
1857 qed_cxt_set_proto_cid_count(p_hwfn
, PROTOCOLID_ETH
,
1858 p_params
->num_cons
, 1);
1863 struct qed_iscsi_pf_params
*p_params
;
1865 p_params
= &p_hwfn
->pf_params
.iscsi_pf_params
;
1867 if (p_params
->num_cons
&& p_params
->num_tasks
) {
1868 qed_cxt_set_proto_cid_count(p_hwfn
,
1873 qed_cxt_set_proto_tid_count(p_hwfn
,
1875 QED_CXT_ISCSI_TID_SEG
,
1877 p_params
->num_tasks
,
1880 DP_INFO(p_hwfn
->cdev
,
1881 "Iscsi personality used without setting params!\n");
1892 int qed_cxt_get_tid_mem_info(struct qed_hwfn
*p_hwfn
,
1893 struct qed_tid_mem
*p_info
)
1895 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
1896 u32 proto
, seg
, total_lines
, i
, shadow_line
;
1897 struct qed_ilt_client_cfg
*p_cli
;
1898 struct qed_ilt_cli_blk
*p_fl_seg
;
1899 struct qed_tid_seg
*p_seg_info
;
1901 /* Verify the personality */
1902 switch (p_hwfn
->hw_info
.personality
) {
1904 proto
= PROTOCOLID_ISCSI
;
1905 seg
= QED_CXT_ISCSI_TID_SEG
;
1911 p_cli
= &p_mngr
->clients
[ILT_CLI_CDUT
];
1915 p_seg_info
= &p_mngr
->conn_cfg
[proto
].tid_seg
[seg
];
1916 if (!p_seg_info
->has_fl_mem
)
1919 p_fl_seg
= &p_cli
->pf_blks
[CDUT_FL_SEG_BLK(seg
, PF
)];
1920 total_lines
= DIV_ROUND_UP(p_fl_seg
->total_size
,
1921 p_fl_seg
->real_size_in_page
);
1923 for (i
= 0; i
< total_lines
; i
++) {
1924 shadow_line
= i
+ p_fl_seg
->start_line
-
1925 p_hwfn
->p_cxt_mngr
->pf_start_line
;
1926 p_info
->blocks
[i
] = p_mngr
->ilt_shadow
[shadow_line
].p_virt
;
1928 p_info
->waste
= ILT_PAGE_IN_BYTES(p_cli
->p_size
.val
) -
1929 p_fl_seg
->real_size_in_page
;
1930 p_info
->tid_size
= p_mngr
->task_type_size
[p_seg_info
->type
];
1931 p_info
->num_tids_per_block
= p_fl_seg
->real_size_in_page
/
1937 /* This function is very RoCE oriented, if another protocol in the future
1938 * will want this feature we'll need to modify the function to be more generic
1941 qed_cxt_dynamic_ilt_alloc(struct qed_hwfn
*p_hwfn
,
1942 enum qed_cxt_elem_type elem_type
, u32 iid
)
1944 u32 reg_offset
, shadow_line
, elem_size
, hw_p_size
, elems_per_p
, line
;
1945 struct qed_ilt_client_cfg
*p_cli
;
1946 struct qed_ilt_cli_blk
*p_blk
;
1947 struct qed_ptt
*p_ptt
;
1953 switch (elem_type
) {
1955 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUC
];
1956 elem_size
= CONN_CXT_SIZE(p_hwfn
);
1957 p_blk
= &p_cli
->pf_blks
[CDUC_BLK
];
1960 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_TSDM
];
1961 elem_size
= SRQ_CXT_SIZE
;
1962 p_blk
= &p_cli
->pf_blks
[SRQ_BLK
];
1965 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUT
];
1966 elem_size
= TYPE1_TASK_CXT_SIZE(p_hwfn
);
1967 p_blk
= &p_cli
->pf_blks
[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG
)];
1970 DP_NOTICE(p_hwfn
, "-EINVALID elem type = %d", elem_type
);
1974 /* Calculate line in ilt */
1975 hw_p_size
= p_cli
->p_size
.val
;
1976 elems_per_p
= ILT_PAGE_IN_BYTES(hw_p_size
) / elem_size
;
1977 line
= p_blk
->start_line
+ (iid
/ elems_per_p
);
1978 shadow_line
= line
- p_hwfn
->p_cxt_mngr
->pf_start_line
;
1980 /* If line is already allocated, do nothing, otherwise allocate it and
1981 * write it to the PSWRQ2 registers.
1982 * This section can be run in parallel from different contexts and thus
1983 * a mutex protection is needed.
1986 mutex_lock(&p_hwfn
->p_cxt_mngr
->mutex
);
1988 if (p_hwfn
->p_cxt_mngr
->ilt_shadow
[shadow_line
].p_virt
)
1991 p_ptt
= qed_ptt_acquire(p_hwfn
);
1994 "QED_TIME_OUT on ptt acquire - dynamic allocation");
1999 p_virt
= dma_alloc_coherent(&p_hwfn
->cdev
->pdev
->dev
,
2000 p_blk
->real_size_in_page
,
2001 &p_phys
, GFP_KERNEL
);
2006 memset(p_virt
, 0, p_blk
->real_size_in_page
);
2008 /* configuration of refTagMask to 0xF is required for RoCE DIF MR only,
2009 * to compensate for a HW bug, but it is configured even if DIF is not
2010 * enabled. This is harmless and allows us to avoid a dedicated API. We
2011 * configure the field for all of the contexts on the newly allocated
2014 if (elem_type
== QED_ELEM_TASK
) {
2016 u8
*elem_start
= (u8
*)p_virt
;
2017 union type1_task_context
*elem
;
2019 for (elem_i
= 0; elem_i
< elems_per_p
; elem_i
++) {
2020 elem
= (union type1_task_context
*)elem_start
;
2021 SET_FIELD(elem
->roce_ctx
.tdif_context
.flags1
,
2022 TDIF_TASK_CONTEXT_REFTAGMASK
, 0xf);
2023 elem_start
+= TYPE1_TASK_CXT_SIZE(p_hwfn
);
2027 p_hwfn
->p_cxt_mngr
->ilt_shadow
[shadow_line
].p_virt
= p_virt
;
2028 p_hwfn
->p_cxt_mngr
->ilt_shadow
[shadow_line
].p_phys
= p_phys
;
2029 p_hwfn
->p_cxt_mngr
->ilt_shadow
[shadow_line
].size
=
2030 p_blk
->real_size_in_page
;
2032 /* compute absolute offset */
2033 reg_offset
= PSWRQ2_REG_ILT_MEMORY
+
2034 (line
* ILT_REG_SIZE_IN_BYTES
* ILT_ENTRY_IN_REGS
);
2037 SET_FIELD(ilt_hw_entry
, ILT_ENTRY_VALID
, 1ULL);
2038 SET_FIELD(ilt_hw_entry
,
2040 (p_hwfn
->p_cxt_mngr
->ilt_shadow
[shadow_line
].p_phys
>> 12));
2042 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2043 qed_dmae_host2grc(p_hwfn
, p_ptt
, (u64
) (uintptr_t)&ilt_hw_entry
,
2044 reg_offset
, sizeof(ilt_hw_entry
) / sizeof(u32
), 0);
2046 if (elem_type
== QED_ELEM_CXT
) {
2047 u32 last_cid_allocated
= (1 + (iid
/ elems_per_p
)) *
2050 /* Update the relevant register in the parser */
2051 qed_wr(p_hwfn
, p_ptt
, PRS_REG_ROCE_DEST_QP_MAX_PF
,
2052 last_cid_allocated
- 1);
2054 if (!p_hwfn
->b_rdma_enabled_in_prs
) {
2055 /* Enable RoCE search */
2056 qed_wr(p_hwfn
, p_ptt
, p_hwfn
->rdma_prs_search_reg
, 1);
2057 p_hwfn
->b_rdma_enabled_in_prs
= true;
2062 qed_ptt_release(p_hwfn
, p_ptt
);
2064 mutex_unlock(&p_hwfn
->p_cxt_mngr
->mutex
);
2069 /* This function is very RoCE oriented, if another protocol in the future
2070 * will want this feature we'll need to modify the function to be more generic
2073 qed_cxt_free_ilt_range(struct qed_hwfn
*p_hwfn
,
2074 enum qed_cxt_elem_type elem_type
,
2075 u32 start_iid
, u32 count
)
2077 u32 start_line
, end_line
, shadow_start_line
, shadow_end_line
;
2078 u32 reg_offset
, elem_size
, hw_p_size
, elems_per_p
;
2079 struct qed_ilt_client_cfg
*p_cli
;
2080 struct qed_ilt_cli_blk
*p_blk
;
2081 u32 end_iid
= start_iid
+ count
;
2082 struct qed_ptt
*p_ptt
;
2083 u64 ilt_hw_entry
= 0;
2086 switch (elem_type
) {
2088 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUC
];
2089 elem_size
= CONN_CXT_SIZE(p_hwfn
);
2090 p_blk
= &p_cli
->pf_blks
[CDUC_BLK
];
2093 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_TSDM
];
2094 elem_size
= SRQ_CXT_SIZE
;
2095 p_blk
= &p_cli
->pf_blks
[SRQ_BLK
];
2098 p_cli
= &p_hwfn
->p_cxt_mngr
->clients
[ILT_CLI_CDUT
];
2099 elem_size
= TYPE1_TASK_CXT_SIZE(p_hwfn
);
2100 p_blk
= &p_cli
->pf_blks
[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG
)];
2103 DP_NOTICE(p_hwfn
, "-EINVALID elem type = %d", elem_type
);
2107 /* Calculate line in ilt */
2108 hw_p_size
= p_cli
->p_size
.val
;
2109 elems_per_p
= ILT_PAGE_IN_BYTES(hw_p_size
) / elem_size
;
2110 start_line
= p_blk
->start_line
+ (start_iid
/ elems_per_p
);
2111 end_line
= p_blk
->start_line
+ (end_iid
/ elems_per_p
);
2112 if (((end_iid
+ 1) / elems_per_p
) != (end_iid
/ elems_per_p
))
2115 shadow_start_line
= start_line
- p_hwfn
->p_cxt_mngr
->pf_start_line
;
2116 shadow_end_line
= end_line
- p_hwfn
->p_cxt_mngr
->pf_start_line
;
2118 p_ptt
= qed_ptt_acquire(p_hwfn
);
2121 "QED_TIME_OUT on ptt acquire - dynamic allocation");
2125 for (i
= shadow_start_line
; i
< shadow_end_line
; i
++) {
2126 if (!p_hwfn
->p_cxt_mngr
->ilt_shadow
[i
].p_virt
)
2129 dma_free_coherent(&p_hwfn
->cdev
->pdev
->dev
,
2130 p_hwfn
->p_cxt_mngr
->ilt_shadow
[i
].size
,
2131 p_hwfn
->p_cxt_mngr
->ilt_shadow
[i
].p_virt
,
2132 p_hwfn
->p_cxt_mngr
->ilt_shadow
[i
].p_phys
);
2134 p_hwfn
->p_cxt_mngr
->ilt_shadow
[i
].p_virt
= NULL
;
2135 p_hwfn
->p_cxt_mngr
->ilt_shadow
[i
].p_phys
= 0;
2136 p_hwfn
->p_cxt_mngr
->ilt_shadow
[i
].size
= 0;
2138 /* compute absolute offset */
2139 reg_offset
= PSWRQ2_REG_ILT_MEMORY
+
2140 ((start_line
++) * ILT_REG_SIZE_IN_BYTES
*
2143 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2146 qed_dmae_host2grc(p_hwfn
, p_ptt
,
2147 (u64
) (uintptr_t) &ilt_hw_entry
,
2149 sizeof(ilt_hw_entry
) / sizeof(u32
),
2153 qed_ptt_release(p_hwfn
, p_ptt
);
2158 int qed_cxt_free_proto_ilt(struct qed_hwfn
*p_hwfn
, enum protocol_type proto
)
2163 /* Free Connection CXT */
2164 rc
= qed_cxt_free_ilt_range(p_hwfn
, QED_ELEM_CXT
,
2165 qed_cxt_get_proto_cid_start(p_hwfn
,
2167 qed_cxt_get_proto_cid_count(p_hwfn
,
2174 rc
= qed_cxt_free_ilt_range(p_hwfn
, QED_ELEM_TASK
, 0,
2175 qed_cxt_get_proto_tid_count(p_hwfn
, proto
));
2180 rc
= qed_cxt_free_ilt_range(p_hwfn
, QED_ELEM_SRQ
, 0,
2181 qed_cxt_get_srq_count(p_hwfn
));
2186 int qed_cxt_get_task_ctx(struct qed_hwfn
*p_hwfn
,
2187 u32 tid
, u8 ctx_type
, void **pp_task_ctx
)
2189 struct qed_cxt_mngr
*p_mngr
= p_hwfn
->p_cxt_mngr
;
2190 struct qed_ilt_client_cfg
*p_cli
;
2191 struct qed_ilt_cli_blk
*p_seg
;
2192 struct qed_tid_seg
*p_seg_info
;
2195 u32 tid_size
, ilt_idx
;
2196 u32 num_tids_per_block
;
2198 /* Verify the personality */
2199 switch (p_hwfn
->hw_info
.personality
) {
2201 proto
= PROTOCOLID_ISCSI
;
2202 seg
= QED_CXT_ISCSI_TID_SEG
;
2208 p_cli
= &p_mngr
->clients
[ILT_CLI_CDUT
];
2212 p_seg_info
= &p_mngr
->conn_cfg
[proto
].tid_seg
[seg
];
2214 if (ctx_type
== QED_CTX_WORKING_MEM
) {
2215 p_seg
= &p_cli
->pf_blks
[CDUT_SEG_BLK(seg
)];
2216 } else if (ctx_type
== QED_CTX_FL_MEM
) {
2217 if (!p_seg_info
->has_fl_mem
)
2219 p_seg
= &p_cli
->pf_blks
[CDUT_FL_SEG_BLK(seg
, PF
)];
2223 total_lines
= DIV_ROUND_UP(p_seg
->total_size
, p_seg
->real_size_in_page
);
2224 tid_size
= p_mngr
->task_type_size
[p_seg_info
->type
];
2225 num_tids_per_block
= p_seg
->real_size_in_page
/ tid_size
;
2227 if (total_lines
< tid
/ num_tids_per_block
)
2230 ilt_idx
= tid
/ num_tids_per_block
+ p_seg
->start_line
-
2231 p_mngr
->pf_start_line
;
2232 *pp_task_ctx
= (u8
*)p_mngr
->ilt_shadow
[ilt_idx
].p_virt
+
2233 (tid
% num_tids_per_block
) * tid_size
;