drivers/net/ethernet/qlogic/qed/qed_hsi.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #ifndef _QED_HSI_H
  10 #define _QED_HSI_H
  11
  12 #include <linux/types.h>
  13 #include <linux/io.h>
  14 #include <linux/bitops.h>
  15 #include <linux/delay.h>
  16 #include <linux/kernel.h>
  17 #include <linux/list.h>
  18 #include <linux/slab.h>
  19 #include <linux/qed/common_hsi.h>
  20
  21 struct qed_hwfn;
  22 struct qed_ptt;
  23 /********************************/
  24 /* Add include to common target */
  25 /********************************/
  26
  27 /* opcodes for the event ring */
  28 enum common_event_opcode {
  29         COMMON_EVENT_PF_START,
  30         COMMON_EVENT_PF_STOP,
  31         COMMON_EVENT_RESERVED,
  32         COMMON_EVENT_RESERVED2,
  33         COMMON_EVENT_RESERVED3,
  34         COMMON_EVENT_RESERVED4,
  35         COMMON_EVENT_RESERVED5,
  36         MAX_COMMON_EVENT_OPCODE
  37 };
  38
  39 /* Common Ramrod Command IDs */
  40 enum common_ramrod_cmd_id {
  41         COMMON_RAMROD_UNUSED,
  42         COMMON_RAMROD_PF_START /* PF Function Start Ramrod */,
  43         COMMON_RAMROD_PF_STOP /* PF Function Stop Ramrod */,
  44         COMMON_RAMROD_RESERVED,
  45         COMMON_RAMROD_RESERVED2,
  46         COMMON_RAMROD_RESERVED3,
  47         MAX_COMMON_RAMROD_CMD_ID
  48 };
  49
  50 /* The core storm context for the Ystorm */
  51 struct ystorm_core_conn_st_ctx {
  52         __le32 reserved[4];
  53 };
  54
  55 /* The core storm context for the Pstorm */
  56 struct pstorm_core_conn_st_ctx {
  57         __le32 reserved[4];
  58 };
  59
  60 /* Core Slowpath Connection storm context of Xstorm */
  61 struct xstorm_core_conn_st_ctx {
  62         __le32          spq_base_lo /* SPQ Ring Base Address low dword */;
  63         __le32          spq_base_hi /* SPQ Ring Base Address high dword */;
  64         struct regpair  consolid_base_addr;
  65         __le16          spq_cons /* SPQ Ring Consumer */;
  66         __le16          consolid_cons /* Consolidation Ring Consumer */;
  67         __le32          reserved0[55] /* Pad to 15 cycles */;
  68 };
  69
  70 struct xstorm_core_conn_ag_ctx {
  71         u8      reserved0 /* cdu_validation */;
  72         u8      core_state /* state */;
  73         u8      flags0;
  74 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK         0x1
  75 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT        0
  76 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK            0x1
  77 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT           1
  78 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK            0x1
  79 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT           2
  80 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK         0x1
  81 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT        3
  82 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK            0x1
  83 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT           4
  84 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK            0x1
  85 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT           5
  86 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK            0x1   /* bit6 */
  87 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT           6
  88 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK            0x1   /* bit7 */
  89 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT           7
  90         u8 flags1;
  91 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK            0x1   /* bit8 */
  92 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT           0
  93 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK            0x1   /* bit9 */
  94 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT           1
  95 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK            0x1   /* bit10 */
  96 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT           2
  97 #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK                0x1   /* bit11 */
  98 #define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT               3
  99 #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK                0x1   /* bit12 */
 100 #define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT               4
 101 #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK                0x1   /* bit13 */
 102 #define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT               5
 103 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK       0x1   /* bit14 */
 104 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT      6
 105 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK         0x1   /* bit15 */
 106 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT        7
 107         u8 flags2;
 108 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK                  0x3   /* timer0cf */
 109 #define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT                 0
 110 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK                  0x3   /* timer1cf */
 111 #define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT                 2
 112 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK                  0x3   /* timer2cf */
 113 #define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT                 4
 114 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK                  0x3
 115 #define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT                 6
 116         u8 flags3;
 117 #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK                  0x3   /* cf4 */
 118 #define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT                 0
 119 #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK                  0x3   /* cf5 */
 120 #define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT                 2
 121 #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK                  0x3   /* cf6 */
 122 #define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT                 4
 123 #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK                  0x3   /* cf7 */
 124 #define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT                 6
 125         u8 flags4;
 126 #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK                  0x3   /* cf8 */
 127 #define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT                 0
 128 #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK                  0x3   /* cf9 */
 129 #define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT                 2
 130 #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK                 0x3   /* cf10 */
 131 #define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT                4
 132 #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK                 0x3   /* cf11 */
 133 #define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT                6
 134         u8 flags5;
 135 #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK                 0x3   /* cf12 */
 136 #define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT                0
 137 #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK                 0x3   /* cf13 */
 138 #define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT                2
 139 #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK                 0x3   /* cf14 */
 140 #define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT                4
 141 #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK                 0x3   /* cf15 */
 142 #define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT                6
 143         u8 flags6;
 144 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK     0x3   /* cf16 */
 145 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT    0
 146 #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK                 0x3
 147 #define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT                2
 148 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK                0x3   /* cf18 */
 149 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT               4
 150 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK         0x3   /* cf19 */
 151 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT        6
 152         u8 flags7;
 153 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK             0x3   /* cf20 */
 154 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT            0
 155 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK           0x3   /* cf21 */
 156 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT          2
 157 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK            0x3   /* cf22 */
 158 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT           4
 159 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK                0x1   /* cf0en */
 160 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT               6
 161 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK                0x1   /* cf1en */
 162 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT               7
 163         u8 flags8;
 164 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK                0x1   /* cf2en */
 165 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT               0
 166 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK                0x1   /* cf3en */
 167 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT               1
 168 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK                0x1   /* cf4en */
 169 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT               2
 170 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK                0x1   /* cf5en */
 171 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT               3
 172 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK                0x1   /* cf6en */
 173 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT               4
 174 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK                0x1   /* cf7en */
 175 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT               5
 176 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK                0x1   /* cf8en */
 177 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT               6
 178 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK                0x1   /* cf9en */
 179 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT               7
 180         u8 flags9;
 181 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK               0x1   /* cf10en */
 182 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT              0
 183 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK               0x1   /* cf11en */
 184 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT              1
 185 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK               0x1   /* cf12en */
 186 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT              2
 187 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK               0x1   /* cf13en */
 188 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT              3
 189 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK               0x1   /* cf14en */
 190 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT              4
 191 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK               0x1   /* cf15en */
 192 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT              5
 193 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK  0x1   /* cf16en */
 194 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
 195 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK               0x1
 196 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT              7
 197         u8 flags10;
 198 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK             0x1   /* cf18en */
 199 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT            0
 200 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK      0x1   /* cf19en */
 201 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT     1
 202 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK          0x1   /* cf20en */
 203 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT         2
 204 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK           0x1   /* cf21en */
 205 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT          3
 206 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK         0x1   /* cf22en */
 207 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT        4
 208 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK               0x1   /* cf23en */
 209 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT              5
 210 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK           0x1   /* rule0en */
 211 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT          6
 212 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK           0x1   /* rule1en */
 213 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT          7
 214         u8 flags11;
 215 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK           0x1   /* rule2en */
 216 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT          0
 217 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK           0x1   /* rule3en */
 218 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT          1
 219 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK       0x1   /* rule4en */
 220 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT      2
 221 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK              0x1   /* rule5en */
 222 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT             3
 223 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK              0x1   /* rule6en */
 224 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT             4
 225 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK              0x1   /* rule7en */
 226 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT             5
 227 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK         0x1   /* rule8en */
 228 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT        6
 229 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK              0x1   /* rule9en */
 230 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT             7
 231         u8 flags12;
 232 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK             0x1   /* rule10en */
 233 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT            0
 234 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK             0x1   /* rule11en */
 235 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT            1
 236 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK         0x1   /* rule12en */
 237 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT        2
 238 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK         0x1   /* rule13en */
 239 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT        3
 240 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK             0x1   /* rule14en */
 241 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT            4
 242 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK             0x1   /* rule15en */
 243 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT            5
 244 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK             0x1   /* rule16en */
 245 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT            6
 246 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK             0x1   /* rule17en */
 247 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT            7
 248         u8 flags13;
 249 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK             0x1   /* rule18en */
 250 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT            0
 251 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK             0x1   /* rule19en */
 252 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT            1
 253 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK         0x1   /* rule20en */
 254 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT        2
 255 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK         0x1   /* rule21en */
 256 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT        3
 257 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK         0x1   /* rule22en */
 258 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT        4
 259 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK         0x1   /* rule23en */
 260 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT        5
 261 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK         0x1   /* rule24en */
 262 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT        6
 263 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK         0x1   /* rule25en */
 264 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT        7
 265         u8 flags14;
 266 #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK                0x1   /* bit16 */
 267 #define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT               0
 268 #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK                0x1   /* bit17 */
 269 #define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT               1
 270 #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK                0x1   /* bit18 */
 271 #define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT               2
 272 #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK                0x1   /* bit19 */
 273 #define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT               3
 274 #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK                0x1   /* bit20 */
 275 #define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT               4
 276 #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK                0x1   /* bit21 */
 277 #define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT               5
 278 #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK                 0x3   /* cf23 */
 279 #define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT                6
 280         u8      byte2 /* byte2 */;
 281         __le16  physical_q0 /* physical_q0 */;
 282         __le16  consolid_prod /* physical_q1 */;
 283         __le16  reserved16 /* physical_q2 */;
 284         __le16  tx_bd_cons /* word3 */;
 285         __le16  tx_bd_or_spq_prod /* word4 */;
 286         __le16  word5 /* word5 */;
 287         __le16  conn_dpi /* conn_dpi */;
 288         u8      byte3 /* byte3 */;
 289         u8      byte4 /* byte4 */;
 290         u8      byte5 /* byte5 */;
 291         u8      byte6 /* byte6 */;
 292         __le32  reg0 /* reg0 */;
 293         __le32  reg1 /* reg1 */;
 294         __le32  reg2 /* reg2 */;
 295         __le32  reg3 /* reg3 */;
 296         __le32  reg4 /* reg4 */;
 297         __le32  reg5 /* cf_array0 */;
 298         __le32  reg6 /* cf_array1 */;
 299         __le16  word7 /* word7 */;
 300         __le16  word8 /* word8 */;
 301         __le16  word9 /* word9 */;
 302         __le16  word10 /* word10 */;
 303         __le32  reg7 /* reg7 */;
 304         __le32  reg8 /* reg8 */;
 305         __le32  reg9 /* reg9 */;
 306         u8      byte7 /* byte7 */;
 307         u8      byte8 /* byte8 */;
 308         u8      byte9 /* byte9 */;
 309         u8      byte10 /* byte10 */;
 310         u8      byte11 /* byte11 */;
 311         u8      byte12 /* byte12 */;
 312         u8      byte13 /* byte13 */;
 313         u8      byte14 /* byte14 */;
 314         u8      byte15 /* byte15 */;
 315         u8      byte16 /* byte16 */;
 316         __le16  word11 /* word11 */;
 317         __le32  reg10 /* reg10 */;
 318         __le32  reg11 /* reg11 */;
 319         __le32  reg12 /* reg12 */;
 320         __le32  reg13 /* reg13 */;
 321         __le32  reg14 /* reg14 */;
 322         __le32  reg15 /* reg15 */;
 323         __le32  reg16 /* reg16 */;
 324         __le32  reg17 /* reg17 */;
 325         __le32  reg18 /* reg18 */;
 326         __le32  reg19 /* reg19 */;
 327         __le16  word12 /* word12 */;
 328         __le16  word13 /* word13 */;
 329         __le16  word14 /* word14 */;
 330         __le16  word15 /* word15 */;
 331 };
 332
 333 /* The core storm context for the Mstorm */
 334 struct mstorm_core_conn_st_ctx {
 335         __le32 reserved[24];
 336 };
 337
 338 /* The core storm context for the Ustorm */
 339 struct ustorm_core_conn_st_ctx {
 340         __le32 reserved[4];
 341 };
 342
 343 /* core connection context */
 344 struct core_conn_context {
 345         struct ystorm_core_conn_st_ctx  ystorm_st_context;
 346         struct regpair                  ystorm_st_padding[2] /* padding */;
 347         struct pstorm_core_conn_st_ctx  pstorm_st_context;
 348         struct regpair                  pstorm_st_padding[2];
 349         struct xstorm_core_conn_st_ctx  xstorm_st_context;
 350         struct xstorm_core_conn_ag_ctx  xstorm_ag_context;
 351         struct mstorm_core_conn_st_ctx  mstorm_st_context;
 352         struct regpair                  mstorm_st_padding[2];
 353         struct ustorm_core_conn_st_ctx  ustorm_st_context;
 354         struct regpair                  ustorm_st_padding[2] /* padding */;
 355 };
 356
 357 /* Event Ring Next Page Address */
 358 struct event_ring_next_addr {
 359         struct regpair  addr /* Next Page Address */;
 360         __le32          reserved[2] /* Reserved */;
 361 };
 362
 363 union event_ring_element {
 364         struct event_ring_entry         entry /* Event Ring Entry */;
 365         struct event_ring_next_addr     next_addr;
 366 };
 367
 368 enum personality_type {
 369         PERSONALITY_RESERVED,
 370         PERSONALITY_RESERVED2,
 371         PERSONALITY_RDMA_AND_ETH /* Roce or Iwarp */,
 372         PERSONALITY_RESERVED3,
 373         PERSONALITY_ETH /* Ethernet */,
 374         PERSONALITY_RESERVED4,
 375         MAX_PERSONALITY_TYPE
 376 };
 377
 378 struct pf_start_tunnel_config {
 379         u8      set_vxlan_udp_port_flg;
 380         u8      set_geneve_udp_port_flg;
 381         u8      tx_enable_vxlan /* If set, enable VXLAN tunnel in TX path. */;
 382         u8      tx_enable_l2geneve;
 383         u8      tx_enable_ipgeneve;
 384         u8      tx_enable_l2gre /* If set, enable l2 GRE tunnel in TX path. */;
 385         u8      tx_enable_ipgre /* If set, enable IP GRE tunnel in TX path. */;
 386         u8      tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. */;
 387         u8      tunnel_clss_l2geneve;
 388         u8      tunnel_clss_ipgeneve;
 389         u8      tunnel_clss_l2gre;
 390         u8      tunnel_clss_ipgre;
 391         __le16  vxlan_udp_port /* VXLAN tunnel UDP destination port. */;
 392         __le16  geneve_udp_port /* GENEVE tunnel UDP destination port. */;
 393 };
 394
 395 /* Ramrod data for PF start ramrod */
 396 struct pf_start_ramrod_data {
 397         struct regpair                  event_ring_pbl_addr;
 398         struct regpair                  consolid_q_pbl_addr;
 399         struct pf_start_tunnel_config   tunnel_config;
 400         __le16                          event_ring_sb_id;
 401         u8                              base_vf_id;
 402         u8                              num_vfs;
 403         u8                              event_ring_num_pages;
 404         u8                              event_ring_sb_index;
 405         u8                              path_id;
 406         u8                              warning_as_error;
 407         u8                              dont_log_ramrods;
 408         u8                              personality;
 409         __le16                          log_type_mask;
 410         u8                              mf_mode /* Multi function mode */;
 411         u8                              integ_phase /* Integration phase */;
 412         u8                              allow_npar_tx_switching;
 413         u8                              inner_to_outer_pri_map[8];
 414         u8                              pri_map_valid;
 415         u32                             outer_tag;
 416         u8                              reserved0[4];
 417 };
 418
 419 enum ports_mode {
 420         ENGX2_PORTX1 /* 2 engines x 1 port */,
 421         ENGX2_PORTX2 /* 2 engines x 2 ports */,
 422         ENGX1_PORTX1 /* 1 engine  x 1 port */,
 423         ENGX1_PORTX2 /* 1 engine  x 2 ports */,
 424         ENGX1_PORTX4 /* 1 engine  x 4 ports */,
 425         MAX_PORTS_MODE
 426 };
 427
 428 /* Ramrod Header of SPQE */
 429 struct ramrod_header {
 430         __le32  cid /* Slowpath Connection CID */;
 431         u8      cmd_id /* Ramrod Cmd (Per Protocol Type) */;
 432         u8      protocol_id /* Ramrod Protocol ID */;
 433         __le16  echo /* Ramrod echo */;
 434 };
 435
 436 /* Slowpath Element (SPQE) */
 437 struct slow_path_element {
 438         struct ramrod_header    hdr /* Ramrod Header */;
 439         struct regpair          data_ptr;
 440 };
 441
 442 struct tstorm_per_port_stat {
 443         struct regpair  trunc_error_discard;
 444         struct regpair  mac_error_discard;
 445         struct regpair  mftag_filter_discard;
 446         struct regpair  eth_mac_filter_discard;
 447         struct regpair  ll2_mac_filter_discard;
 448         struct regpair  ll2_conn_disabled_discard;
 449         struct regpair  iscsi_irregular_pkt;
 450         struct regpair  fcoe_irregular_pkt;
 451         struct regpair  roce_irregular_pkt;
 452         struct regpair  eth_irregular_pkt;
 453         struct regpair  toe_irregular_pkt;
 454         struct regpair  preroce_irregular_pkt;
 455 };
 456
 457 struct atten_status_block {
 458         __le32  atten_bits;
 459         __le32  atten_ack;
 460         __le16  reserved0;
 461         __le16  sb_index /* status block running index */;
 462         __le32  reserved1;
 463 };
 464
 465 enum block_addr {
 466         GRCBASE_GRC             = 0x50000,
 467         GRCBASE_MISCS           = 0x9000,
 468         GRCBASE_MISC            = 0x8000,
 469         GRCBASE_DBU             = 0xa000,
 470         GRCBASE_PGLUE_B         = 0x2a8000,
 471         GRCBASE_CNIG            = 0x218000,
 472         GRCBASE_CPMU            = 0x30000,
 473         GRCBASE_NCSI            = 0x40000,
 474         GRCBASE_OPTE            = 0x53000,
 475         GRCBASE_BMB             = 0x540000,
 476         GRCBASE_PCIE            = 0x54000,
 477         GRCBASE_MCP             = 0xe00000,
 478         GRCBASE_MCP2            = 0x52000,
 479         GRCBASE_PSWHST          = 0x2a0000,
 480         GRCBASE_PSWHST2         = 0x29e000,
 481         GRCBASE_PSWRD           = 0x29c000,
 482         GRCBASE_PSWRD2          = 0x29d000,
 483         GRCBASE_PSWWR           = 0x29a000,
 484         GRCBASE_PSWWR2          = 0x29b000,
 485         GRCBASE_PSWRQ           = 0x280000,
 486         GRCBASE_PSWRQ2          = 0x240000,
 487         GRCBASE_PGLCS           = 0x0,
 488         GRCBASE_PTU             = 0x560000,
 489         GRCBASE_DMAE            = 0xc000,
 490         GRCBASE_TCM             = 0x1180000,
 491         GRCBASE_MCM             = 0x1200000,
 492         GRCBASE_UCM             = 0x1280000,
 493         GRCBASE_XCM             = 0x1000000,
 494         GRCBASE_YCM             = 0x1080000,
 495         GRCBASE_PCM             = 0x1100000,
 496         GRCBASE_QM              = 0x2f0000,
 497         GRCBASE_TM              = 0x2c0000,
 498         GRCBASE_DORQ            = 0x100000,
 499         GRCBASE_BRB             = 0x340000,
 500         GRCBASE_SRC             = 0x238000,
 501         GRCBASE_PRS             = 0x1f0000,
 502         GRCBASE_TSDM            = 0xfb0000,
 503         GRCBASE_MSDM            = 0xfc0000,
 504         GRCBASE_USDM            = 0xfd0000,
 505         GRCBASE_XSDM            = 0xf80000,
 506         GRCBASE_YSDM            = 0xf90000,
 507         GRCBASE_PSDM            = 0xfa0000,
 508         GRCBASE_TSEM            = 0x1700000,
 509         GRCBASE_MSEM            = 0x1800000,
 510         GRCBASE_USEM            = 0x1900000,
 511         GRCBASE_XSEM            = 0x1400000,
 512         GRCBASE_YSEM            = 0x1500000,
 513         GRCBASE_PSEM            = 0x1600000,
 514         GRCBASE_RSS             = 0x238800,
 515         GRCBASE_TMLD            = 0x4d0000,
 516         GRCBASE_MULD            = 0x4e0000,
 517         GRCBASE_YULD            = 0x4c8000,
 518         GRCBASE_XYLD            = 0x4c0000,
 519         GRCBASE_PRM             = 0x230000,
 520         GRCBASE_PBF_PB1         = 0xda0000,
 521         GRCBASE_PBF_PB2         = 0xda4000,
 522         GRCBASE_RPB             = 0x23c000,
 523         GRCBASE_BTB             = 0xdb0000,
 524         GRCBASE_PBF             = 0xd80000,
 525         GRCBASE_RDIF            = 0x300000,
 526         GRCBASE_TDIF            = 0x310000,
 527         GRCBASE_CDU             = 0x580000,
 528         GRCBASE_CCFC            = 0x2e0000,
 529         GRCBASE_TCFC            = 0x2d0000,
 530         GRCBASE_IGU             = 0x180000,
 531         GRCBASE_CAU             = 0x1c0000,
 532         GRCBASE_UMAC            = 0x51000,
 533         GRCBASE_XMAC            = 0x210000,
 534         GRCBASE_DBG             = 0x10000,
 535         GRCBASE_NIG             = 0x500000,
 536         GRCBASE_WOL             = 0x600000,
 537         GRCBASE_BMBN            = 0x610000,
 538         GRCBASE_IPC             = 0x20000,
 539         GRCBASE_NWM             = 0x800000,
 540         GRCBASE_NWS             = 0x700000,
 541         GRCBASE_MS              = 0x6a0000,
 542         GRCBASE_PHY_PCIE        = 0x618000,
 543         GRCBASE_MISC_AEU        = 0x8000,
 544         GRCBASE_BAR0_MAP        = 0x1c00000,
 545         MAX_BLOCK_ADDR
 546 };
 547
 548 enum block_id {
 549         BLOCK_GRC,
 550         BLOCK_MISCS,
 551         BLOCK_MISC,
 552         BLOCK_DBU,
 553         BLOCK_PGLUE_B,
 554         BLOCK_CNIG,
 555         BLOCK_CPMU,
 556         BLOCK_NCSI,
 557         BLOCK_OPTE,
 558         BLOCK_BMB,
 559         BLOCK_PCIE,
 560         BLOCK_MCP,
 561         BLOCK_MCP2,
 562         BLOCK_PSWHST,
 563         BLOCK_PSWHST2,
 564         BLOCK_PSWRD,
 565         BLOCK_PSWRD2,
 566         BLOCK_PSWWR,
 567         BLOCK_PSWWR2,
 568         BLOCK_PSWRQ,
 569         BLOCK_PSWRQ2,
 570         BLOCK_PGLCS,
 571         BLOCK_PTU,
 572         BLOCK_DMAE,
 573         BLOCK_TCM,
 574         BLOCK_MCM,
 575         BLOCK_UCM,
 576         BLOCK_XCM,
 577         BLOCK_YCM,
 578         BLOCK_PCM,
 579         BLOCK_QM,
 580         BLOCK_TM,
 581         BLOCK_DORQ,
 582         BLOCK_BRB,
 583         BLOCK_SRC,
 584         BLOCK_PRS,
 585         BLOCK_TSDM,
 586         BLOCK_MSDM,
 587         BLOCK_USDM,
 588         BLOCK_XSDM,
 589         BLOCK_YSDM,
 590         BLOCK_PSDM,
 591         BLOCK_TSEM,
 592         BLOCK_MSEM,
 593         BLOCK_USEM,
 594         BLOCK_XSEM,
 595         BLOCK_YSEM,
 596         BLOCK_PSEM,
 597         BLOCK_RSS,
 598         BLOCK_TMLD,
 599         BLOCK_MULD,
 600         BLOCK_YULD,
 601         BLOCK_XYLD,
 602         BLOCK_PRM,
 603         BLOCK_PBF_PB1,
 604         BLOCK_PBF_PB2,
 605         BLOCK_RPB,
 606         BLOCK_BTB,
 607         BLOCK_PBF,
 608         BLOCK_RDIF,
 609         BLOCK_TDIF,
 610         BLOCK_CDU,
 611         BLOCK_CCFC,
 612         BLOCK_TCFC,
 613         BLOCK_IGU,
 614         BLOCK_CAU,
 615         BLOCK_UMAC,
 616         BLOCK_XMAC,
 617         BLOCK_DBG,
 618         BLOCK_NIG,
 619         BLOCK_WOL,
 620         BLOCK_BMBN,
 621         BLOCK_IPC,
 622         BLOCK_NWM,
 623         BLOCK_NWS,
 624         BLOCK_MS,
 625         BLOCK_PHY_PCIE,
 626         BLOCK_MISC_AEU,
 627         BLOCK_BAR0_MAP,
 628         MAX_BLOCK_ID
 629 };
 630
 631 enum command_type_bit {
 632         IGU_COMMAND_TYPE_NOP    = 0,
 633         IGU_COMMAND_TYPE_SET    = 1,
 634         MAX_COMMAND_TYPE_BIT
 635 };
 636
 637 struct dmae_cmd {
 638         __le32 opcode;
 639 #define DMAE_CMD_SRC_MASK              0x1
 640 #define DMAE_CMD_SRC_SHIFT             0
 641 #define DMAE_CMD_DST_MASK              0x3
 642 #define DMAE_CMD_DST_SHIFT             1
 643 #define DMAE_CMD_C_DST_MASK            0x1
 644 #define DMAE_CMD_C_DST_SHIFT           3
 645 #define DMAE_CMD_CRC_RESET_MASK        0x1
 646 #define DMAE_CMD_CRC_RESET_SHIFT       4
 647 #define DMAE_CMD_SRC_ADDR_RESET_MASK   0x1
 648 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT  5
 649 #define DMAE_CMD_DST_ADDR_RESET_MASK   0x1
 650 #define DMAE_CMD_DST_ADDR_RESET_SHIFT  6
 651 #define DMAE_CMD_COMP_FUNC_MASK        0x1
 652 #define DMAE_CMD_COMP_FUNC_SHIFT       7
 653 #define DMAE_CMD_COMP_WORD_EN_MASK     0x1
 654 #define DMAE_CMD_COMP_WORD_EN_SHIFT    8
 655 #define DMAE_CMD_COMP_CRC_EN_MASK      0x1
 656 #define DMAE_CMD_COMP_CRC_EN_SHIFT     9
 657 #define DMAE_CMD_COMP_CRC_OFFSET_MASK  0x7
 658 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
 659 #define DMAE_CMD_RESERVED1_MASK        0x1
 660 #define DMAE_CMD_RESERVED1_SHIFT       13
 661 #define DMAE_CMD_ENDIANITY_MODE_MASK   0x3
 662 #define DMAE_CMD_ENDIANITY_MODE_SHIFT  14
 663 #define DMAE_CMD_ERR_HANDLING_MASK     0x3
 664 #define DMAE_CMD_ERR_HANDLING_SHIFT    16
 665 #define DMAE_CMD_PORT_ID_MASK          0x3
 666 #define DMAE_CMD_PORT_ID_SHIFT         18
 667 #define DMAE_CMD_SRC_PF_ID_MASK        0xF
 668 #define DMAE_CMD_SRC_PF_ID_SHIFT       20
 669 #define DMAE_CMD_DST_PF_ID_MASK        0xF
 670 #define DMAE_CMD_DST_PF_ID_SHIFT       24
 671 #define DMAE_CMD_SRC_VF_ID_VALID_MASK  0x1
 672 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
 673 #define DMAE_CMD_DST_VF_ID_VALID_MASK  0x1
 674 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
 675 #define DMAE_CMD_RESERVED2_MASK        0x3
 676 #define DMAE_CMD_RESERVED2_SHIFT       30
 677         __le32  src_addr_lo;
 678         __le32  src_addr_hi;
 679         __le32  dst_addr_lo;
 680         __le32  dst_addr_hi;
 681         __le16  length /* Length in DW */;
 682         __le16  opcode_b;
 683 #define DMAE_CMD_SRC_VF_ID_MASK        0xFF     /* Source VF id */
 684 #define DMAE_CMD_SRC_VF_ID_SHIFT       0
 685 #define DMAE_CMD_DST_VF_ID_MASK        0xFF     /* Destination VF id */
 686 #define DMAE_CMD_DST_VF_ID_SHIFT       8
 687         __le32  comp_addr_lo /* PCIe completion address low or grc address */;
 688         __le32  comp_addr_hi;
 689         __le32  comp_val /* Value to write to copmletion address */;
 690         __le32  crc32 /* crc16 result */;
 691         __le32  crc_32_c /* crc32_c result */;
 692         __le16  crc16 /* crc16 result */;
 693         __le16  crc16_c /* crc16_c result */;
 694         __le16  crc10 /* crc_t10 result */;
 695         __le16  reserved;
 696         __le16  xsum16 /* checksum16 result  */;
 697         __le16  xsum8 /* checksum8 result  */;
 698 };
 699
 700 struct igu_cleanup {
 701         __le32 sb_id_and_flags;
 702 #define IGU_CLEANUP_RESERVED0_MASK     0x7FFFFFF
 703 #define IGU_CLEANUP_RESERVED0_SHIFT    0
 704 #define IGU_CLEANUP_CLEANUP_SET_MASK   0x1 /* cleanup clear - 0, set - 1 */
 705 #define IGU_CLEANUP_CLEANUP_SET_SHIFT  27
 706 #define IGU_CLEANUP_CLEANUP_TYPE_MASK  0x7
 707 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
 708 #define IGU_CLEANUP_COMMAND_TYPE_MASK  0x1
 709 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
 710         __le32 reserved1;
 711 };
 712
 713 union igu_command {
 714         struct igu_prod_cons_update     prod_cons_update;
 715         struct igu_cleanup              cleanup;
 716 };
 717
 718 struct igu_command_reg_ctrl {
 719         __le16  opaque_fid;
 720         __le16  igu_command_reg_ctrl_fields;
 721 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK  0xFFF
 722 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
 723 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK      0x7
 724 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT     12
 725 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK  0x1
 726 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
 727 };
 728
 729 struct igu_mapping_line {
 730         __le32 igu_mapping_line_fields;
 731 #define IGU_MAPPING_LINE_VALID_MASK            0x1
 732 #define IGU_MAPPING_LINE_VALID_SHIFT           0
 733 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK    0xFF
 734 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT   1
 735 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK  0xFF
 736 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
 737 #define IGU_MAPPING_LINE_PF_VALID_MASK         0x1      /* PF-1, VF-0 */
 738 #define IGU_MAPPING_LINE_PF_VALID_SHIFT        17
 739 #define IGU_MAPPING_LINE_IPS_GROUP_MASK        0x3F
 740 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT       18
 741 #define IGU_MAPPING_LINE_RESERVED_MASK         0xFF
 742 #define IGU_MAPPING_LINE_RESERVED_SHIFT        24
 743 };
 744
 745 struct igu_msix_vector {
 746         struct regpair  address;
 747         __le32          data;
 748         __le32          msix_vector_fields;
 749 #define IGU_MSIX_VECTOR_MASK_BIT_MASK      0x1
 750 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT     0
 751 #define IGU_MSIX_VECTOR_RESERVED0_MASK     0x7FFF
 752 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT    1
 753 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK  0xFF
 754 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
 755 #define IGU_MSIX_VECTOR_RESERVED1_MASK     0xFF
 756 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT    24
 757 };
 758
 759 enum init_modes {
 760         MODE_BB_A0,
 761         MODE_RESERVED,
 762         MODE_RESERVED2,
 763         MODE_ASIC,
 764         MODE_RESERVED3,
 765         MODE_RESERVED4,
 766         MODE_RESERVED5,
 767         MODE_SF,
 768         MODE_MF_SD,
 769         MODE_MF_SI,
 770         MODE_PORTS_PER_ENG_1,
 771         MODE_PORTS_PER_ENG_2,
 772         MODE_PORTS_PER_ENG_4,
 773         MODE_40G,
 774         MODE_100G,
 775         MODE_EAGLE_ENG1_WORKAROUND,
 776         MAX_INIT_MODES
 777 };
 778
 779 enum init_phases {
 780         PHASE_ENGINE,
 781         PHASE_PORT,
 782         PHASE_PF,
 783         PHASE_RESERVED,
 784         PHASE_QM_PF,
 785         MAX_INIT_PHASES
 786 };
 787
 788 struct mstorm_core_conn_ag_ctx {
 789         u8      byte0 /* cdu_validation */;
 790         u8      byte1 /* state */;
 791         u8      flags0;
 792 #define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK     0x1       /* exist_in_qm0 */
 793 #define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT    0
 794 #define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK     0x1       /* exist_in_qm1 */
 795 #define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT    1
 796 #define MSTORM_CORE_CONN_AG_CTX_CF0_MASK      0x3       /* cf0 */
 797 #define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT     2
 798 #define MSTORM_CORE_CONN_AG_CTX_CF1_MASK      0x3       /* cf1 */
 799 #define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT     4
 800 #define MSTORM_CORE_CONN_AG_CTX_CF2_MASK      0x3       /* cf2 */
 801 #define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT     6
 802         u8 flags1;
 803 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK    0x1       /* cf0en */
 804 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT   0
 805 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK    0x1       /* cf1en */
 806 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT   1
 807 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK    0x1       /* cf2en */
 808 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT   2
 809 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK  0x1       /* rule0en */
 810 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
 811 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK  0x1       /* rule1en */
 812 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
 813 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK  0x1       /* rule2en */
 814 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
 815 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK  0x1       /* rule3en */
 816 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
 817 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK  0x1       /* rule4en */
 818 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
 819         __le16  word0 /* word0 */;
 820         __le16  word1 /* word1 */;
 821         __le32  reg0 /* reg0 */;
 822         __le32  reg1 /* reg1 */;
 823 };
 824
 825 /* per encapsulation type enabling flags */
 826 struct prs_reg_encapsulation_type_en {
 827         u8 flags;
 828 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK     0x1
 829 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT    0
 830 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK      0x1
 831 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT     1
 832 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK            0x1
 833 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT           2
 834 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK            0x1
 835 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT           3
 836 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK  0x1
 837 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
 838 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK   0x1
 839 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT  5
 840 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK                0x3
 841 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT               6
 842 };
 843
 844 enum pxp_tph_st_hint {
 845         TPH_ST_HINT_BIDIR /* Read/Write access by Host and Device */,
 846         TPH_ST_HINT_REQUESTER /* Read/Write access by Device */,
 847         TPH_ST_HINT_TARGET,
 848         TPH_ST_HINT_TARGET_PRIO,
 849         MAX_PXP_TPH_ST_HINT
 850 };
 851
 852 /* QM hardware structure of enable bypass credit mask */
 853 struct qm_rf_bypass_mask {
 854         u8 flags;
 855 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK    0x1
 856 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT   0
 857 #define QM_RF_BYPASS_MASK_RESERVED0_MASK  0x1
 858 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
 859 #define QM_RF_BYPASS_MASK_PFWFQ_MASK      0x1
 860 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT     2
 861 #define QM_RF_BYPASS_MASK_VPWFQ_MASK      0x1
 862 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT     3
 863 #define QM_RF_BYPASS_MASK_PFRL_MASK       0x1
 864 #define QM_RF_BYPASS_MASK_PFRL_SHIFT      4
 865 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK    0x1
 866 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT   5
 867 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK    0x1
 868 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT   6
 869 #define QM_RF_BYPASS_MASK_RESERVED1_MASK  0x1
 870 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
 871 };
 872
 873 /* QM hardware structure of opportunistic credit mask */
 874 struct qm_rf_opportunistic_mask {
 875         __le16 flags;
 876 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK     0x1
 877 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT    0
 878 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK     0x1
 879 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT    1
 880 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK       0x1
 881 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT      2
 882 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK       0x1
 883 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT      3
 884 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK        0x1
 885 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT       4
 886 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK     0x1
 887 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT    5
 888 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK     0x1
 889 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT    6
 890 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK   0x1
 891 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT  7
 892 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK  0x1
 893 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
 894 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK   0x7F
 895 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT  9
 896 };
 897
 898 /* QM hardware structure of QM map memory */
 899 struct qm_rf_pq_map {
 900         u32 reg;
 901 #define QM_RF_PQ_MAP_PQ_VALID_MASK          0x1         /* PQ active */
 902 #define QM_RF_PQ_MAP_PQ_VALID_SHIFT         0
 903 #define QM_RF_PQ_MAP_RL_ID_MASK             0xFF        /* RL ID */
 904 #define QM_RF_PQ_MAP_RL_ID_SHIFT            1
 905 #define QM_RF_PQ_MAP_VP_PQ_ID_MASK          0x1FF
 906 #define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT         9
 907 #define QM_RF_PQ_MAP_VOQ_MASK               0x1F        /* VOQ */
 908 #define QM_RF_PQ_MAP_VOQ_SHIFT              18
 909 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK  0x3         /* WRR weight */
 910 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
 911 #define QM_RF_PQ_MAP_RL_VALID_MASK          0x1         /* RL active */
 912 #define QM_RF_PQ_MAP_RL_VALID_SHIFT         25
 913 #define QM_RF_PQ_MAP_RESERVED_MASK          0x3F
 914 #define QM_RF_PQ_MAP_RESERVED_SHIFT         26
 915 };
 916
 917 /* SDM operation gen command (generate aggregative interrupt) */
 918 struct sdm_op_gen {
 919         __le32 command;
 920 #define SDM_OP_GEN_COMP_PARAM_MASK  0xFFFF      /* completion parameters 0-15 */
 921 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
 922 #define SDM_OP_GEN_COMP_TYPE_MASK   0xF         /* completion type 16-19 */
 923 #define SDM_OP_GEN_COMP_TYPE_SHIFT  16
 924 #define SDM_OP_GEN_RESERVED_MASK    0xFFF       /* reserved 20-31 */
 925 #define SDM_OP_GEN_RESERVED_SHIFT   20
 926 };
 927
 928 struct tstorm_core_conn_ag_ctx {
 929         u8      byte0 /* cdu_validation */;
 930         u8      byte1 /* state */;
 931         u8      flags0;
 932 #define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK     0x1       /* exist_in_qm0 */
 933 #define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT    0
 934 #define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK     0x1       /* exist_in_qm1 */
 935 #define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT    1
 936 #define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK     0x1       /* bit2 */
 937 #define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT    2
 938 #define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK     0x1       /* bit3 */
 939 #define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT    3
 940 #define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK     0x1       /* bit4 */
 941 #define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT    4
 942 #define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK     0x1       /* bit5 */
 943 #define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT    5
 944 #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK      0x3       /* timer0cf */
 945 #define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT     6
 946         u8 flags1;
 947 #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK      0x3       /* timer1cf */
 948 #define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT     0
 949 #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK      0x3       /* timer2cf */
 950 #define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT     2
 951 #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK      0x3       /* timer_stop_all */
 952 #define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT     4
 953 #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK      0x3       /* cf4 */
 954 #define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT     6
 955         u8 flags2;
 956 #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK      0x3       /* cf5 */
 957 #define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT     0
 958 #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK      0x3       /* cf6 */
 959 #define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT     2
 960 #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK      0x3       /* cf7 */
 961 #define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT     4
 962 #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK      0x3       /* cf8 */
 963 #define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT     6
 964         u8 flags3;
 965 #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK      0x3       /* cf9 */
 966 #define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT     0
 967 #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK     0x3       /* cf10 */
 968 #define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT    2
 969 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK    0x1       /* cf0en */
 970 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT   4
 971 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK    0x1       /* cf1en */
 972 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT   5
 973 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK    0x1       /* cf2en */
 974 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT   6
 975 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK    0x1       /* cf3en */
 976 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT   7
 977         u8 flags4;
 978 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK    0x1       /* cf4en */
 979 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT   0
 980 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK    0x1       /* cf5en */
 981 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT   1
 982 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK    0x1       /* cf6en */
 983 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT   2
 984 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK    0x1       /* cf7en */
 985 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT   3
 986 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK    0x1       /* cf8en */
 987 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT   4
 988 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK    0x1       /* cf9en */
 989 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT   5
 990 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK   0x1       /* cf10en */
 991 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT  6
 992 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK  0x1       /* rule0en */
 993 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
 994         u8 flags5;
 995 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK  0x1       /* rule1en */
 996 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
 997 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK  0x1       /* rule2en */
 998 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
 999 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK  0x1       /* rule3en */
1000 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
1001 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK  0x1       /* rule4en */
1002 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
1003 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK  0x1       /* rule5en */
1004 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
1005 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK  0x1       /* rule6en */
1006 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
1007 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK  0x1       /* rule7en */
1008 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
1009 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK  0x1       /* rule8en */
1010 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
1011         __le32  reg0 /* reg0 */;
1012         __le32  reg1 /* reg1 */;
1013         __le32  reg2 /* reg2 */;
1014         __le32  reg3 /* reg3 */;
1015         __le32  reg4 /* reg4 */;
1016         __le32  reg5 /* reg5 */;
1017         __le32  reg6 /* reg6 */;
1018         __le32  reg7 /* reg7 */;
1019         __le32  reg8 /* reg8 */;
1020         u8      byte2 /* byte2 */;
1021         u8      byte3 /* byte3 */;
1022         __le16  word0 /* word0 */;
1023         u8      byte4 /* byte4 */;
1024         u8      byte5 /* byte5 */;
1025         __le16  word1 /* word1 */;
1026         __le16  word2 /* conn_dpi */;
1027         __le16  word3 /* word3 */;
1028         __le32  reg9 /* reg9 */;
1029         __le32  reg10 /* reg10 */;
1030 };
1031
1032 struct ustorm_core_conn_ag_ctx {
1033         u8      reserved /* cdu_validation */;
1034         u8      byte1 /* state */;
1035         u8      flags0;
1036 #define USTORM_CORE_CONN_AG_CTX_BIT0_MASK     0x1       /* exist_in_qm0 */
1037 #define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT    0
1038 #define USTORM_CORE_CONN_AG_CTX_BIT1_MASK     0x1       /* exist_in_qm1 */
1039 #define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT    1
1040 #define USTORM_CORE_CONN_AG_CTX_CF0_MASK      0x3       /* timer0cf */
1041 #define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT     2
1042 #define USTORM_CORE_CONN_AG_CTX_CF1_MASK      0x3       /* timer1cf */
1043 #define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT     4
1044 #define USTORM_CORE_CONN_AG_CTX_CF2_MASK      0x3       /* timer2cf */
1045 #define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT     6
1046         u8 flags1;
1047 #define USTORM_CORE_CONN_AG_CTX_CF3_MASK      0x3       /* timer_stop_all */
1048 #define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT     0
1049 #define USTORM_CORE_CONN_AG_CTX_CF4_MASK      0x3       /* cf4 */
1050 #define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT     2
1051 #define USTORM_CORE_CONN_AG_CTX_CF5_MASK      0x3       /* cf5 */
1052 #define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT     4
1053 #define USTORM_CORE_CONN_AG_CTX_CF6_MASK      0x3       /* cf6 */
1054 #define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT     6
1055         u8 flags2;
1056 #define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK    0x1       /* cf0en */
1057 #define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT   0
1058 #define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK    0x1       /* cf1en */
1059 #define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT   1
1060 #define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK    0x1       /* cf2en */
1061 #define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT   2
1062 #define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK    0x1       /* cf3en */
1063 #define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT   3
1064 #define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK    0x1       /* cf4en */
1065 #define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT   4
1066 #define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK    0x1       /* cf5en */
1067 #define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT   5
1068 #define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK    0x1       /* cf6en */
1069 #define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT   6
1070 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK  0x1       /* rule0en */
1071 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
1072         u8 flags3;
1073 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK  0x1       /* rule1en */
1074 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
1075 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK  0x1       /* rule2en */
1076 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
1077 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK  0x1       /* rule3en */
1078 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
1079 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK  0x1       /* rule4en */
1080 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
1081 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK  0x1       /* rule5en */
1082 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
1083 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK  0x1       /* rule6en */
1084 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
1085 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK  0x1       /* rule7en */
1086 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
1087 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK  0x1       /* rule8en */
1088 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
1089         u8      byte2 /* byte2 */;
1090         u8      byte3 /* byte3 */;
1091         __le16  word0 /* conn_dpi */;
1092         __le16  word1 /* word1 */;
1093         __le32  rx_producers /* reg0 */;
1094         __le32  reg1 /* reg1 */;
1095         __le32  reg2 /* reg2 */;
1096         __le32  reg3 /* reg3 */;
1097         __le16  word2 /* word2 */;
1098         __le16  word3 /* word3 */;
1099 };
1100
1101 struct ystorm_core_conn_ag_ctx {
1102         u8      byte0 /* cdu_validation */;
1103         u8      byte1 /* state */;
1104         u8      flags0;
1105 #define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK     0x1       /* exist_in_qm0 */
1106 #define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT    0
1107 #define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK     0x1       /* exist_in_qm1 */
1108 #define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT    1
1109 #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK      0x3       /* cf0 */
1110 #define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT     2
1111 #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK      0x3       /* cf1 */
1112 #define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT     4
1113 #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK      0x3       /* cf2 */
1114 #define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT     6
1115         u8 flags1;
1116 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK    0x1       /* cf0en */
1117 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT   0
1118 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK    0x1       /* cf1en */
1119 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT   1
1120 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK    0x1       /* cf2en */
1121 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT   2
1122 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK  0x1       /* rule0en */
1123 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1124 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK  0x1       /* rule1en */
1125 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1126 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK  0x1       /* rule2en */
1127 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1128 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK  0x1       /* rule3en */
1129 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1130 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK  0x1       /* rule4en */
1131 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
1132         u8      byte2 /* byte2 */;
1133         u8      byte3 /* byte3 */;
1134         __le16  word0 /* word0 */;
1135         __le32  reg0 /* reg0 */;
1136         __le32  reg1 /* reg1 */;
1137         __le16  word1 /* word1 */;
1138         __le16  word2 /* word2 */;
1139         __le16  word3 /* word3 */;
1140         __le16  word4 /* word4 */;
1141         __le32  reg2 /* reg2 */;
1142         __le32  reg3 /* reg3 */;
1143 };
1144
1145 /*********************************** Init ************************************/
1146
1147 /* Width of GRC address in bits (addresses are specified in dwords) */
1148 #define GRC_ADDR_BITS                   23
1149 #define MAX_GRC_ADDR                    ((1 << GRC_ADDR_BITS) - 1)
1150
1151 /* indicates an init that should be applied to any phase ID */
1152 #define ANY_PHASE_ID                    0xffff
1153
1154 /* init pattern size in bytes */
1155 #define INIT_PATTERN_SIZE_BITS  4
1156 #define MAX_INIT_PATTERN_SIZE   BIT(INIT_PATTERN_SIZE_BITS)
1157
1158 /* Max size in dwords of a zipped array */
1159 #define MAX_ZIPPED_SIZE                 8192
1160
1161 /* Global PXP window */
1162 #define NUM_OF_PXP_WIN                  19
1163 #define PXP_WIN_DWORD_SIZE_BITS 10
1164 #define PXP_WIN_DWORD_SIZE              BIT(PXP_WIN_DWORD_SIZE_BITS)
1165 #define PXP_WIN_BYTE_SIZE_BITS  (PXP_WIN_DWORD_SIZE_BITS + 2)
1166 #define PXP_WIN_BYTE_SIZE               (PXP_WIN_DWORD_SIZE * 4)
1167
1168 /********************************* GRC Dump **********************************/
1169
1170 /* width of GRC dump register sequence length in bits */
1171 #define DUMP_SEQ_LEN_BITS                       8
1172 #define DUMP_SEQ_LEN_MAX_VAL            ((1 << DUMP_SEQ_LEN_BITS) - 1)
1173
1174 /* width of GRC dump memory length in bits */
1175 #define DUMP_MEM_LEN_BITS                       18
1176 #define DUMP_MEM_LEN_MAX_VAL            ((1 << DUMP_MEM_LEN_BITS) - 1)
1177
1178 /* width of register type ID in bits */
1179 #define REG_TYPE_ID_BITS                        6
1180 #define REG_TYPE_ID_MAX_VAL                     ((1 << REG_TYPE_ID_BITS) - 1)
1181
1182 /* width of block ID in bits */
1183 #define BLOCK_ID_BITS                           8
1184 #define BLOCK_ID_MAX_VAL                        ((1 << BLOCK_ID_BITS) - 1)
1185
1186 /******************************** Idle Check *********************************/
1187
1188 /* max number of idle check predicate immediates */
1189 #define MAX_IDLE_CHK_PRED_IMM           3
1190
1191 /* max number of idle check argument registers */
1192 #define MAX_IDLE_CHK_READ_REGS          3
1193
1194 /* max number of idle check loops */
1195 #define MAX_IDLE_CHK_LOOPS                      0x10000
1196
1197 /* max idle check address increment */
1198 #define MAX_IDLE_CHK_INCREMENT          0x10000
1199
1200 /* inicates an undefined idle check line index */
1201 #define IDLE_CHK_UNDEFINED_LINE_IDX     0xffffff
1202
1203 /* max number of register values following the idle check header */
1204 #define IDLE_CHK_MAX_DUMP_REGS          2
1205
1206 /* arguments for IDLE_CHK_MACRO_TYPE_QM_RD_WR */
1207 #define IDLE_CHK_QM_RD_WR_PTR           0
1208 #define IDLE_CHK_QM_RD_WR_BANK          1
1209
1210 /**************************************/
1211 /* HSI Functions constants and macros */
1212 /**************************************/
1213
1214 /* Number of VLAN priorities */
1215 #define NUM_OF_VLAN_PRIORITIES                  8
1216
1217 /* the MCP Trace meta data signautre is duplicated in the perl script that
1218  * generats the NVRAM images.
1219  */
1220 #define MCP_TRACE_META_IMAGE_SIGNATURE  0x669955aa
1221
1222 /* Binary buffer header */
1223 struct bin_buffer_hdr {
1224         u32     offset;
1225         u32     length /* buffer length in bytes */;
1226 };
1227
1228 /* binary buffer types */
1229 enum bin_buffer_type {
1230         BIN_BUF_FW_VER_INFO /* fw_ver_info struct */,
1231         BIN_BUF_INIT_CMD /* init commands */,
1232         BIN_BUF_INIT_VAL /* init data */,
1233         BIN_BUF_INIT_MODE_TREE /* init modes tree */,
1234         BIN_BUF_IRO /* internal RAM offsets array */,
1235         MAX_BIN_BUFFER_TYPE
1236 };
1237
1238 /* Chip IDs */
1239 enum chip_ids {
1240         CHIP_BB_A0 /* BB A0 chip ID */,
1241         CHIP_BB_B0 /* BB B0 chip ID */,
1242         CHIP_K2 /* AH chip ID */,
1243         MAX_CHIP_IDS
1244 };
1245
1246 enum idle_chk_severity_types {
1247         IDLE_CHK_SEVERITY_ERROR /* idle check failure should cause an error */,
1248         IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
1249         IDLE_CHK_SEVERITY_WARNING,
1250         MAX_IDLE_CHK_SEVERITY_TYPES
1251 };
1252
1253 struct init_array_raw_hdr {
1254         __le32 data;
1255 #define INIT_ARRAY_RAW_HDR_TYPE_MASK    0xF
1256 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT   0
1257 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK  0xFFFFFFF       /* init array params */
1258 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
1259 };
1260
1261 struct init_array_standard_hdr {
1262         __le32 data;
1263 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK  0xF
1264 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
1265 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK  0xFFFFFFF
1266 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
1267 };
1268
1269 struct init_array_zipped_hdr {
1270         __le32 data;
1271 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK         0xF
1272 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT        0
1273 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK  0xFFFFFFF
1274 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
1275 };
1276
1277 struct init_array_pattern_hdr {
1278         __le32 data;
1279 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK          0xF
1280 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT         0
1281 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK  0xF
1282 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
1283 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK   0xFFFFFF
1284 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT  8
1285 };
1286
1287 union init_array_hdr {
1288         struct init_array_raw_hdr       raw /* raw init array header */;
1289         struct init_array_standard_hdr  standard;
1290         struct init_array_zipped_hdr    zipped /* zipped init array header */;
1291         struct init_array_pattern_hdr   pattern /* pattern init array header */;
1292 };
1293
1294 enum init_array_types {
1295         INIT_ARR_STANDARD /* standard init array */,
1296         INIT_ARR_ZIPPED /* zipped init array */,
1297         INIT_ARR_PATTERN /* a repeated pattern */,
1298         MAX_INIT_ARRAY_TYPES
1299 };
1300
1301 /* init operation: callback */
1302 struct init_callback_op {
1303         __le32  op_data;
1304 #define INIT_CALLBACK_OP_OP_MASK        0xF
1305 #define INIT_CALLBACK_OP_OP_SHIFT       0
1306 #define INIT_CALLBACK_OP_RESERVED_MASK  0xFFFFFFF
1307 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
1308         __le16  callback_id /* Callback ID */;
1309         __le16  block_id /* Blocks ID */;
1310 };
1311
1312 /* init comparison types */
1313 enum init_comparison_types {
1314         INIT_COMPARISON_EQ /* init value is included in the init command */,
1315         INIT_COMPARISON_OR /* init value is all zeros */,
1316         INIT_COMPARISON_AND /* init value is an array of values */,
1317         MAX_INIT_COMPARISON_TYPES
1318 };
1319
1320 /* init operation: delay */
1321 struct init_delay_op {
1322         __le32  op_data;
1323 #define INIT_DELAY_OP_OP_MASK        0xF
1324 #define INIT_DELAY_OP_OP_SHIFT       0
1325 #define INIT_DELAY_OP_RESERVED_MASK  0xFFFFFFF
1326 #define INIT_DELAY_OP_RESERVED_SHIFT 4
1327         __le32  delay /* delay in us */;
1328 };
1329
1330 /* init operation: if_mode */
1331 struct init_if_mode_op {
1332         __le32 op_data;
1333 #define INIT_IF_MODE_OP_OP_MASK          0xF
1334 #define INIT_IF_MODE_OP_OP_SHIFT         0
1335 #define INIT_IF_MODE_OP_RESERVED1_MASK   0xFFF
1336 #define INIT_IF_MODE_OP_RESERVED1_SHIFT  4
1337 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK  0xFFFF
1338 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
1339         __le16  reserved2;
1340         __le16  modes_buf_offset;
1341 };
1342
1343 /*  init operation: if_phase */
1344 struct init_if_phase_op {
1345         __le32 op_data;
1346 #define INIT_IF_PHASE_OP_OP_MASK           0xF
1347 #define INIT_IF_PHASE_OP_OP_SHIFT          0
1348 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK  0x1
1349 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
1350 #define INIT_IF_PHASE_OP_RESERVED1_MASK    0x7FF
1351 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT   5
1352 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK   0xFFFF
1353 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT  16
1354         __le32 phase_data;
1355 #define INIT_IF_PHASE_OP_PHASE_MASK        0xFF /* Init phase */
1356 #define INIT_IF_PHASE_OP_PHASE_SHIFT       0
1357 #define INIT_IF_PHASE_OP_RESERVED2_MASK    0xFF
1358 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT   8
1359 #define INIT_IF_PHASE_OP_PHASE_ID_MASK     0xFFFF /* Init phase ID */
1360 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT    16
1361 };
1362
1363 /* init mode operators */
1364 enum init_mode_ops {
1365         INIT_MODE_OP_NOT /* init mode not operator */,
1366         INIT_MODE_OP_OR /* init mode or operator */,
1367         INIT_MODE_OP_AND /* init mode and operator */,
1368         MAX_INIT_MODE_OPS
1369 };
1370
1371 /* init operation: raw */
1372 struct init_raw_op {
1373         __le32  op_data;
1374 #define INIT_RAW_OP_OP_MASK      0xF
1375 #define INIT_RAW_OP_OP_SHIFT     0
1376 #define INIT_RAW_OP_PARAM1_MASK  0xFFFFFFF      /* init param 1 */
1377 #define INIT_RAW_OP_PARAM1_SHIFT 4
1378         __le32  param2 /* Init param 2 */;
1379 };
1380
1381 /* init array params */
1382 struct init_op_array_params {
1383         __le16  size /* array size in dwords */;
1384         __le16  offset /* array start offset in dwords */;
1385 };
1386
1387 /* Write init operation arguments */
1388 union init_write_args {
1389         __le32                          inline_val;
1390         __le32                          zeros_count;
1391         __le32                          array_offset;
1392         struct init_op_array_params     runtime;
1393 };
1394
1395 /* init operation: write */
1396 struct init_write_op {
1397         __le32 data;
1398 #define INIT_WRITE_OP_OP_MASK        0xF
1399 #define INIT_WRITE_OP_OP_SHIFT       0
1400 #define INIT_WRITE_OP_SOURCE_MASK    0x7
1401 #define INIT_WRITE_OP_SOURCE_SHIFT   4
1402 #define INIT_WRITE_OP_RESERVED_MASK  0x1
1403 #define INIT_WRITE_OP_RESERVED_SHIFT 7
1404 #define INIT_WRITE_OP_WIDE_BUS_MASK  0x1
1405 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
1406 #define INIT_WRITE_OP_ADDRESS_MASK   0x7FFFFF
1407 #define INIT_WRITE_OP_ADDRESS_SHIFT  9
1408         union init_write_args args /* Write init operation arguments */;
1409 };
1410
1411 /* init operation: read */
1412 struct init_read_op {
1413         __le32 op_data;
1414 #define INIT_READ_OP_OP_MASK         0xF
1415 #define INIT_READ_OP_OP_SHIFT        0
1416 #define INIT_READ_OP_POLL_COMP_MASK  0x7
1417 #define INIT_READ_OP_POLL_COMP_SHIFT 4
1418 #define INIT_READ_OP_RESERVED_MASK   0x1
1419 #define INIT_READ_OP_RESERVED_SHIFT  7
1420 #define INIT_READ_OP_POLL_MASK       0x1
1421 #define INIT_READ_OP_POLL_SHIFT      8
1422 #define INIT_READ_OP_ADDRESS_MASK    0x7FFFFF
1423 #define INIT_READ_OP_ADDRESS_SHIFT   9
1424         __le32 expected_val;
1425 };
1426
1427 /* Init operations union */
1428 union init_op {
1429         struct init_raw_op      raw /* raw init operation */;
1430         struct init_write_op    write /* write init operation */;
1431         struct init_read_op     read /* read init operation */;
1432         struct init_if_mode_op  if_mode /* if_mode init operation */;
1433         struct init_if_phase_op if_phase /* if_phase init operation */;
1434         struct init_callback_op callback /* callback init operation */;
1435         struct init_delay_op    delay /* delay init operation */;
1436 };
1437
1438 /* Init command operation types */
1439 enum init_op_types {
1440         INIT_OP_READ /* GRC read init command */,
1441         INIT_OP_WRITE /* GRC write init command */,
1442         INIT_OP_IF_MODE,
1443         INIT_OP_IF_PHASE,
1444         INIT_OP_DELAY /* delay init command */,
1445         INIT_OP_CALLBACK /* callback init command */,
1446         MAX_INIT_OP_TYPES
1447 };
1448
1449 /* init source types */
1450 enum init_source_types {
1451         INIT_SRC_INLINE /* init value is included in the init command */,
1452         INIT_SRC_ZEROS /* init value is all zeros */,
1453         INIT_SRC_ARRAY /* init value is an array of values */,
1454         INIT_SRC_RUNTIME /* init value is provided during runtime */,
1455         MAX_INIT_SOURCE_TYPES
1456 };
1457
1458 /* Internal RAM Offsets macro data */
1459 struct iro {
1460         u32     base /* RAM field offset */;
1461         u16     m1 /* multiplier 1 */;
1462         u16     m2 /* multiplier 2 */;
1463         u16     m3 /* multiplier 3 */;
1464         u16     size /* RAM field size */;
1465 };
1466
1467 /* QM per-port init parameters */
1468 struct init_qm_port_params {
1469         u8      active /* Indicates if this port is active */;
1470         u8      num_active_phys_tcs;
1471         u16     num_pbf_cmd_lines;
1472         u16     num_btb_blocks;
1473         __le16  reserved;
1474 };
1475
1476 /* QM per-PQ init parameters */
1477 struct init_qm_pq_params {
1478         u8      vport_id /* VPORT ID */;
1479         u8      tc_id /* TC ID */;
1480         u8      wrr_group /* WRR group */;
1481         u8      reserved;
1482 };
1483
1484 /* QM per-vport init parameters */
1485 struct init_qm_vport_params {
1486         u32     vport_rl;
1487         u16     vport_wfq;
1488         u16     first_tx_pq_id[NUM_OF_TCS];
1489 };
1490
1491 /* Win 2 */
1492 #define GTT_BAR0_MAP_REG_IGU_CMD \
1493         0x00f000UL
1494 /* Win 3 */
1495 #define GTT_BAR0_MAP_REG_TSDM_RAM \
1496         0x010000UL
1497 /* Win 4 */
1498 #define GTT_BAR0_MAP_REG_MSDM_RAM \
1499         0x011000UL
1500 /* Win 5 */
1501 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 \
1502         0x012000UL
1503 /* Win 6 */
1504 #define GTT_BAR0_MAP_REG_USDM_RAM \
1505         0x013000UL
1506 /* Win 7 */
1507 #define GTT_BAR0_MAP_REG_USDM_RAM_1024 \
1508         0x014000UL
1509 /* Win 8 */
1510 #define GTT_BAR0_MAP_REG_USDM_RAM_2048 \
1511         0x015000UL
1512 /* Win 9 */
1513 #define GTT_BAR0_MAP_REG_XSDM_RAM \
1514         0x016000UL
1515 /* Win 10 */
1516 #define GTT_BAR0_MAP_REG_YSDM_RAM \
1517         0x017000UL
1518 /* Win 11 */
1519 #define GTT_BAR0_MAP_REG_PSDM_RAM \
1520         0x018000UL
1521
1522 /**
1523  * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
1524  *
1525  * Returns the required host memory size in 4KB units.
1526  * Must be called before all QM init HSI functions.
1527  *
1528  * @param pf_id                 - physical function ID
1529  * @param num_pf_cids   - number of connections used by this PF
1530  * @param num_vf_cids   - number of connections used by VFs of this PF
1531  * @param num_tids              - number of tasks used by this PF
1532  * @param num_pf_pqs    - number of PQs used by this PF
1533  * @param num_vf_pqs    - number of PQs used by VFs of this PF
1534  *
1535  * @return The required host memory size in 4KB units.
1536  */
1537 u32 qed_qm_pf_mem_size(u8       pf_id,
1538                        u32      num_pf_cids,
1539                        u32      num_vf_cids,
1540                        u32      num_tids,
1541                        u16      num_pf_pqs,
1542                        u16      num_vf_pqs);
1543
1544 struct qed_qm_common_rt_init_params {
1545         u8                              max_ports_per_engine;
1546         u8                              max_phys_tcs_per_port;
1547         bool                            pf_rl_en;
1548         bool                            pf_wfq_en;
1549         bool                            vport_rl_en;
1550         bool                            vport_wfq_en;
1551         struct init_qm_port_params      *port_params;
1552 };
1553
1554 /**
1555  * @brief qed_qm_common_rt_init - Prepare QM runtime init values for the
1556  * engine phase.
1557  *
1558  * @param p_hwfn
1559  * @param max_ports_per_engine  - max number of ports per engine in HW
1560  * @param max_phys_tcs_per_port - max number of physical TCs per port in HW
1561  * @param pf_rl_en                              - enable per-PF rate limiters
1562  * @param pf_wfq_en                             - enable per-PF WFQ
1563  * @param vport_rl_en                   - enable per-VPORT rate limiters
1564  * @param vport_wfq_en                  - enable per-VPORT WFQ
1565  * @param port_params                   - array of size MAX_NUM_PORTS with
1566  *                                              arameters for each port
1567  *
1568  * @return 0 on success, -1 on error.
1569  */
1570 int qed_qm_common_rt_init(
1571         struct qed_hwfn                         *p_hwfn,
1572         struct qed_qm_common_rt_init_params     *p_params);
1573
1574 struct qed_qm_pf_rt_init_params {
1575         u8                              port_id;
1576         u8                              pf_id;
1577         u8                              max_phys_tcs_per_port;
1578         bool                            is_first_pf;
1579         u32                             num_pf_cids;
1580         u32                             num_vf_cids;
1581         u32                             num_tids;
1582         u16                             start_pq;
1583         u16                             num_pf_pqs;
1584         u16                             num_vf_pqs;
1585         u8                              start_vport;
1586         u8                              num_vports;
1587         u8                              pf_wfq;
1588         u32                             pf_rl;
1589         struct init_qm_pq_params        *pq_params;
1590         struct init_qm_vport_params     *vport_params;
1591 };
1592
1593 int qed_qm_pf_rt_init(struct qed_hwfn                   *p_hwfn,
1594                       struct qed_ptt                    *p_ptt,
1595                       struct qed_qm_pf_rt_init_params   *p_params);
1596
1597 /**
1598  * @brief qed_init_pf_rl  Initializes the rate limit of the specified PF
1599  *
1600  * @param p_hwfn
1601  * @param p_ptt - ptt window used for writing the registers
1602  * @param pf_id - PF ID
1603  * @param pf_rl - rate limit in Mb/sec units
1604  *
1605  * @return 0 on success, -1 on error.
1606  */
1607 int qed_init_pf_rl(struct qed_hwfn      *p_hwfn,
1608                    struct qed_ptt       *p_ptt,
1609                    u8                   pf_id,
1610                    u32                  pf_rl);
1611
1612 /**
1613  * @brief qed_init_vport_rl  Initializes the rate limit of the specified VPORT
1614  *
1615  * @param p_hwfn
1616  * @param p_ptt         - ptt window used for writing the registers
1617  * @param vport_id      - VPORT ID
1618  * @param vport_rl      - rate limit in Mb/sec units
1619  *
1620  * @return 0 on success, -1 on error.
1621  */
1622
1623 int qed_init_vport_rl(struct qed_hwfn   *p_hwfn,
1624                       struct qed_ptt    *p_ptt,
1625                       u8                vport_id,
1626                       u32               vport_rl);
1627 /**
1628  * @brief qed_send_qm_stop_cmd  Sends a stop command to the QM
1629  *
1630  * @param p_hwfn
1631  * @param p_ptt          - ptt window used for writing the registers
1632  * @param is_release_cmd - true for release, false for stop.
1633  * @param is_tx_pq       - true for Tx PQs, false for Other PQs.
1634  * @param start_pq       - first PQ ID to stop
1635  * @param num_pqs        - Number of PQs to stop, starting from start_pq.
1636  *
1637  * @return bool, true if successful, false if timeout occurred while waiting
1638  *                                      for QM command done.
1639  */
1640
1641 bool qed_send_qm_stop_cmd(struct qed_hwfn       *p_hwfn,
1642                           struct qed_ptt        *p_ptt,
1643                           bool                  is_release_cmd,
1644                           bool                  is_tx_pq,
1645                           u16                   start_pq,
1646                           u16                   num_pqs);
1647
1648 /* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
1649 #define YSTORM_FLOW_CONTROL_MODE_OFFSET                 (IRO[0].base)
1650 #define YSTORM_FLOW_CONTROL_MODE_SIZE                   (IRO[0].size)
1651 /* Tstorm port statistics */
1652 #define TSTORM_PORT_STAT_OFFSET(port_id)                (IRO[1].base + \
1653                                                          ((port_id) * \
1654                                                           IRO[1].m1))
1655 #define TSTORM_PORT_STAT_SIZE                           (IRO[1].size)
1656 /* Ustorm VF-PF Channel ready flag */
1657 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id)        (IRO[2].base +  \
1658                                                          ((vf_id) *     \
1659                                                           IRO[2].m1))
1660 #define USTORM_VF_PF_CHANNEL_READY_SIZE                 (IRO[2].size)
1661 /* Ustorm Final flr cleanup ack */
1662 #define USTORM_FLR_FINAL_ACK_OFFSET                     (IRO[3].base)
1663 #define USTORM_FLR_FINAL_ACK_SIZE                       (IRO[3].size)
1664 /* Ustorm Event ring consumer */
1665 #define USTORM_EQE_CONS_OFFSET(pf_id)                   (IRO[4].base +  \
1666                                                          ((pf_id) *     \
1667                                                           IRO[4].m1))
1668 #define USTORM_EQE_CONS_SIZE                            (IRO[4].size)
1669 /* Ustorm Completion ring consumer */
1670 #define USTORM_CQ_CONS_OFFSET(global_queue_id)          (IRO[5].base +  \
1671                                                          ((global_queue_id) * \
1672                                                           IRO[5].m1))
1673 #define USTORM_CQ_CONS_SIZE                             (IRO[5].size)
1674 /* Xstorm Integration Test Data */
1675 #define XSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[6].base)
1676 #define XSTORM_INTEG_TEST_DATA_SIZE                     (IRO[6].size)
1677 /* Ystorm Integration Test Data */
1678 #define YSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[7].base)
1679 #define YSTORM_INTEG_TEST_DATA_SIZE                     (IRO[7].size)
1680 /* Pstorm Integration Test Data */
1681 #define PSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[8].base)
1682 #define PSTORM_INTEG_TEST_DATA_SIZE                     (IRO[8].size)
1683 /* Tstorm Integration Test Data */
1684 #define TSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[9].base)
1685 #define TSTORM_INTEG_TEST_DATA_SIZE                     (IRO[9].size)
1686 /* Mstorm Integration Test Data */
1687 #define MSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[10].base)
1688 #define MSTORM_INTEG_TEST_DATA_SIZE                     (IRO[10].size)
1689 /* Ustorm Integration Test Data */
1690 #define USTORM_INTEG_TEST_DATA_OFFSET                   (IRO[11].base)
1691 #define USTORM_INTEG_TEST_DATA_SIZE                     (IRO[11].size)
1692 /* Tstorm producers */
1693 #define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id)    (IRO[12].base + \
1694                                                          ((core_rx_queue_id) * \
1695                                                           IRO[12].m1))
1696 #define TSTORM_LL2_RX_PRODS_SIZE                        (IRO[12].size)
1697 /* Tstorm LiteL2 queue statistics */
1698 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_q_id) (IRO[13].base + \
1699                                                              ((core_rx_q_id) * \
1700                                                               IRO[13].m1))
1701 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE             (IRO[13].size)
1702 /* Ustorm LiteL2 queue statistics */
1703 #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_q_id) (IRO[14].base + \
1704                                                              ((core_rx_q_id) * \
1705                                                               IRO[14].m1))
1706 #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE             (IRO[14].size)
1707 /* Pstorm LiteL2 queue statistics */
1708 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_txst_id) (IRO[15].base + \
1709                                                              ((core_txst_id) * \
1710                                                               IRO[15].m1))
1711 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE             (IRO[15].size)
1712 /* Mstorm queue statistics */
1713 #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) (IRO[16].base + \
1714                                                    ((stat_counter_id) * \
1715                                                     IRO[16].m1))
1716 #define MSTORM_QUEUE_STAT_SIZE                          (IRO[16].size)
1717 /* Mstorm producers */
1718 #define MSTORM_PRODS_OFFSET(queue_id)                   (IRO[17].base + \
1719                                                          ((queue_id) *  \
1720                                                           IRO[17].m1))
1721 #define MSTORM_PRODS_SIZE                               (IRO[17].size)
1722 /* TPA agregation timeout in us resolution (on ASIC) */
1723 #define MSTORM_TPA_TIMEOUT_US_OFFSET                    (IRO[18].base)
1724 #define MSTORM_TPA_TIMEOUT_US_SIZE                      (IRO[18].size)
1725 /* Ustorm queue statistics */
1726 #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id)       (IRO[19].base + \
1727                                                         ((stat_counter_id) * \
1728                                                          IRO[19].m1))
1729 #define USTORM_QUEUE_STAT_SIZE                          (IRO[19].size)
1730 /* Ustorm queue zone */
1731 #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_id)          (IRO[20].base + \
1732                                                          ((queue_id) *  \
1733                                                           IRO[20].m1))
1734 #define USTORM_ETH_QUEUE_ZONE_SIZE                      (IRO[20].size)
1735 /* Pstorm queue statistics */
1736 #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id)       (IRO[21].base + \
1737                                                          ((stat_counter_id) * \
1738                                                           IRO[21].m1))
1739 #define PSTORM_QUEUE_STAT_SIZE                          (IRO[21].size)
1740 /* Tstorm last parser message */
1741 #define TSTORM_ETH_PRS_INPUT_OFFSET(pf_id)              (IRO[22].base + \
1742                                                          ((pf_id) *     \
1743                                                           IRO[22].m1))
1744 #define TSTORM_ETH_PRS_INPUT_SIZE                       (IRO[22].size)
1745 /* Ystorm queue zone */
1746 #define YSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id)          (IRO[23].base + \
1747                                                          ((queue_id) *  \
1748                                                           IRO[23].m1))
1749 #define YSTORM_ETH_QUEUE_ZONE_SIZE                      (IRO[23].size)
1750 /* Ystorm cqe producer */
1751 #define YSTORM_TOE_CQ_PROD_OFFSET(rss_id)               (IRO[24].base + \
1752                                                          ((rss_id) *    \
1753                                                           IRO[24].m1))
1754 #define YSTORM_TOE_CQ_PROD_SIZE                         (IRO[24].size)
1755 /* Ustorm cqe producer */
1756 #define USTORM_TOE_CQ_PROD_OFFSET(rss_id)               (IRO[25].base + \
1757                                                          ((rss_id) *    \
1758                                                           IRO[25].m1))
1759 #define USTORM_TOE_CQ_PROD_SIZE                         (IRO[25].size)
1760 /* Ustorm grq producer */
1761 #define USTORM_TOE_GRQ_PROD_OFFSET(pf_id)               (IRO[26].base + \
1762                                                          ((pf_id) *     \
1763                                                           IRO[26].m1))
1764 #define USTORM_TOE_GRQ_PROD_SIZE                        (IRO[26].size)
1765 /* Tstorm cmdq-cons of given command queue-id */
1766 #define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id)     (IRO[27].base + \
1767                                                          ((cmdq_queue_id) * \
1768                                                           IRO[27].m1))
1769 #define TSTORM_SCSI_CMDQ_CONS_SIZE                      (IRO[27].size)
1770 /* Mstorm rq-cons of given queue-id */
1771 #define MSTORM_SCSI_RQ_CONS_OFFSET(rq_queue_id)         (IRO[28].base + \
1772                                                          ((rq_queue_id) * \
1773                                                           IRO[28].m1))
1774 #define MSTORM_SCSI_RQ_CONS_SIZE                        (IRO[28].size)
1775 /* Pstorm RoCE statistics */
1776 #define PSTORM_ROCE_STAT_OFFSET(stat_counter_id)        (IRO[29].base + \
1777                                                          ((stat_counter_id) * \
1778                                                           IRO[29].m1))
1779 #define PSTORM_ROCE_STAT_SIZE                           (IRO[29].size)
1780 /* Tstorm RoCE statistics */
1781 #define TSTORM_ROCE_STAT_OFFSET(stat_counter_id)        (IRO[30].base + \
1782                                                          ((stat_counter_id) * \
1783                                                           IRO[30].m1))
1784 #define TSTORM_ROCE_STAT_SIZE                           (IRO[30].size)
1785
1786 static const struct iro iro_arr[31] = {
1787         { 0x10,   0x0,   0x0,   0x0,   0x8     },
1788         { 0x4448, 0x60,  0x0,   0x0,   0x60    },
1789         { 0x498,  0x8,   0x0,   0x0,   0x4     },
1790         { 0x494,  0x0,   0x0,   0x0,   0x4     },
1791         { 0x10,   0x8,   0x0,   0x0,   0x2     },
1792         { 0x90,   0x8,   0x0,   0x0,   0x2     },
1793         { 0x4540, 0x0,   0x0,   0x0,   0xf8    },
1794         { 0x39e0, 0x0,   0x0,   0x0,   0xf8    },
1795         { 0x2598, 0x0,   0x0,   0x0,   0xf8    },
1796         { 0x4350, 0x0,   0x0,   0x0,   0xf8    },
1797         { 0x52d0, 0x0,   0x0,   0x0,   0xf8    },
1798         { 0x7a48, 0x0,   0x0,   0x0,   0xf8    },
1799         { 0x100,  0x8,   0x0,   0x0,   0x8     },
1800         { 0x5808, 0x10,  0x0,   0x0,   0x10    },
1801         { 0xb100, 0x30,  0x0,   0x0,   0x30    },
1802         { 0x95c0, 0x30,  0x0,   0x0,   0x30    },
1803         { 0x54f8, 0x40,  0x0,   0x0,   0x40    },
1804         { 0x200,  0x10,  0x0,   0x0,   0x8     },
1805         { 0x9e70, 0x0,   0x0,   0x0,   0x4     },
1806         { 0x7ca0, 0x40,  0x0,   0x0,   0x30    },
1807         { 0xd00,  0x8,   0x0,   0x0,   0x8     },
1808         { 0x2790, 0x80,  0x0,   0x0,   0x38    },
1809         { 0xa520, 0xf0,  0x0,   0x0,   0xf0    },
1810         { 0x80,   0x8,   0x0,   0x0,   0x8     },
1811         { 0xac0,  0x8,   0x0,   0x0,   0x8     },
1812         { 0x2580, 0x8,   0x0,   0x0,   0x8     },
1813         { 0x2500, 0x8,   0x0,   0x0,   0x8     },
1814         { 0x440,  0x8,   0x0,   0x0,   0x2     },
1815         { 0x1800, 0x8,   0x0,   0x0,   0x2     },
1816         { 0x27c8, 0x80,  0x0,   0x0,   0x10    },
1817         { 0x4710, 0x10,  0x0,   0x0,   0x10    },
1818 };
1819
1820 /* Runtime array offsets */
1821 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET                                0
1822 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET                                1
1823 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET                                2
1824 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET                                3
1825 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET                                4
1826 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET                                5
1827 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET                                6
1828 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET                                7
1829 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET                                8
1830 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET                                9
1831 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET                                10
1832 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET                                11
1833 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET                                12
1834 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET                                13
1835 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET                                14
1836 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET                                15
1837 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET                                  16
1838 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET                              17
1839 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET                              18
1840 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET                               19
1841 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET                               20
1842 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET                            21
1843 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET                           22
1844 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET                             23
1845 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET                                 760
1846 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE                                   736
1847 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET                                 760
1848 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE                                   736
1849 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET                                1496
1850 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE                                  736
1851 #define CAU_REG_PI_MEMORY_RT_OFFSET                                     2232
1852 #define CAU_REG_PI_MEMORY_RT_SIZE                                       4416
1853 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET                    6648
1854 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET                      6649
1855 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET                      6650
1856 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET                         6651
1857 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET                         6652
1858 #define PRS_REG_SEARCH_TCP_RT_OFFSET                                    6653
1859 #define PRS_REG_SEARCH_FCOE_RT_OFFSET                                   6654
1860 #define PRS_REG_SEARCH_ROCE_RT_OFFSET                                   6655
1861 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET                           6656
1862 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET                           6657
1863 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET                               6658
1864 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET                     6659
1865 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET           6660
1866 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET                      6661
1867 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET                         6662
1868 #define SRC_REG_FIRSTFREE_RT_OFFSET                                     6663
1869 #define SRC_REG_FIRSTFREE_RT_SIZE                                       2
1870 #define SRC_REG_LASTFREE_RT_OFFSET                                      6665
1871 #define SRC_REG_LASTFREE_RT_SIZE                                        2
1872 #define SRC_REG_COUNTFREE_RT_OFFSET                                     6667
1873 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET                              6668
1874 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET                                6669
1875 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET                                6670
1876 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET                                  6671
1877 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET                                  6672
1878 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET                                 6673
1879 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET                               6674
1880 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET                                6675
1881 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET                               6676
1882 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET                                6677
1883 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET                              6678
1884 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET                               6679
1885 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET                             6680
1886 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET                              6681
1887 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET                             6682
1888 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET                              6683
1889 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET                             6684
1890 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET                              6685
1891 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET                     6686
1892 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET                   6687
1893 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET                   6688
1894 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET                               6689
1895 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET                             6690
1896 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET                             6691
1897 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET                           6692
1898 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET                         6693
1899 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET                         6694
1900 #define PSWRQ2_REG_VF_BASE_RT_OFFSET                                    6695
1901 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET                                6696
1902 #define PSWRQ2_REG_WR_MBS0_RT_OFFSET                                    6697
1903 #define PSWRQ2_REG_RD_MBS0_RT_OFFSET                                    6698
1904 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET                              6699
1905 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET                              6700
1906 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET                                 6701
1907 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE                                   22000
1908 #define PGLUE_REG_B_VF_BASE_RT_OFFSET                                   28701
1909 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET                           28702
1910 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET                              28703
1911 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET                              28704
1912 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET                              28705
1913 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET                                 28706
1914 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET                                 28707
1915 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET                                 28708
1916 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET                     28709
1917 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET                     28710
1918 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET                                28711
1919 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE                                  416
1920 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET                                29127
1921 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE                                  512
1922 #define QM_REG_MAXPQSIZE_0_RT_OFFSET                                    29639
1923 #define QM_REG_MAXPQSIZE_1_RT_OFFSET                                    29640
1924 #define QM_REG_MAXPQSIZE_2_RT_OFFSET                                    29641
1925 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET                               29642
1926 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET                               29643
1927 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET                               29644
1928 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET                               29645
1929 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET                               29646
1930 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET                               29647
1931 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET                               29648
1932 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET                               29649
1933 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET                               29650
1934 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET                               29651
1935 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET                              29652
1936 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET                              29653
1937 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET                              29654
1938 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET                              29655
1939 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET                              29656
1940 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET                              29657
1941 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET                              29658
1942 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET                              29659
1943 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET                              29660
1944 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET                              29661
1945 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET                              29662
1946 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET                              29663
1947 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET                              29664
1948 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET                              29665
1949 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET                              29666
1950 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET                              29667
1951 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET                              29668
1952 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET                              29669
1953 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET                              29670
1954 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET                              29671
1955 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET                              29672
1956 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET                              29673
1957 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET                              29674
1958 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET                              29675
1959 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET                              29676
1960 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET                              29677
1961 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET                              29678
1962 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET                              29679
1963 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET                              29680
1964 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET                              29681
1965 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET                              29682
1966 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET                              29683
1967 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET                              29684
1968 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET                              29685
1969 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET                              29686
1970 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET                              29687
1971 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET                              29688
1972 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET                              29689
1973 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET                              29690
1974 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET                              29691
1975 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET                              29692
1976 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET                              29693
1977 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET                              29694
1978 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET                              29695
1979 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET                              29696
1980 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET                              29697
1981 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET                              29698
1982 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET                              29699
1983 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET                              29700
1984 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET                              29701
1985 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET                              29702
1986 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET                              29703
1987 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET                              29704
1988 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET                              29705
1989 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET                                29706
1990 #define QM_REG_BASEADDROTHERPQ_RT_SIZE                                  128
1991 #define QM_REG_VOQCRDLINE_RT_OFFSET                                     29834
1992 #define QM_REG_VOQCRDLINE_RT_SIZE                                       20
1993 #define QM_REG_VOQINITCRDLINE_RT_OFFSET                                 29854
1994 #define QM_REG_VOQINITCRDLINE_RT_SIZE                                   20
1995 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET                             29874
1996 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET                             29875
1997 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET                              29876
1998 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET                            29877
1999 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET                           29878
2000 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET                                29879
2001 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET                                29880
2002 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET                                29881
2003 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET                                29882
2004 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET                                29883
2005 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET                                29884
2006 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET                                29885
2007 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET                                29886
2008 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET                                29887
2009 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET                                29888
2010 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET                               29889
2011 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET                               29890
2012 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET                               29891
2013 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET                               29892
2014 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET                               29893
2015 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET                               29894
2016 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET                            29895
2017 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET                            29896
2018 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET                            29897
2019 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET                            29898
2020 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET                               29899
2021 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET                               29900
2022 #define QM_REG_PQTX2PF_0_RT_OFFSET                                      29901
2023 #define QM_REG_PQTX2PF_1_RT_OFFSET                                      29902
2024 #define QM_REG_PQTX2PF_2_RT_OFFSET                                      29903
2025 #define QM_REG_PQTX2PF_3_RT_OFFSET                                      29904
2026 #define QM_REG_PQTX2PF_4_RT_OFFSET                                      29905
2027 #define QM_REG_PQTX2PF_5_RT_OFFSET                                      29906
2028 #define QM_REG_PQTX2PF_6_RT_OFFSET                                      29907
2029 #define QM_REG_PQTX2PF_7_RT_OFFSET                                      29908
2030 #define QM_REG_PQTX2PF_8_RT_OFFSET                                      29909
2031 #define QM_REG_PQTX2PF_9_RT_OFFSET                                      29910
2032 #define QM_REG_PQTX2PF_10_RT_OFFSET                                     29911
2033 #define QM_REG_PQTX2PF_11_RT_OFFSET                                     29912
2034 #define QM_REG_PQTX2PF_12_RT_OFFSET                                     29913
2035 #define QM_REG_PQTX2PF_13_RT_OFFSET                                     29914
2036 #define QM_REG_PQTX2PF_14_RT_OFFSET                                     29915
2037 #define QM_REG_PQTX2PF_15_RT_OFFSET                                     29916
2038 #define QM_REG_PQTX2PF_16_RT_OFFSET                                     29917
2039 #define QM_REG_PQTX2PF_17_RT_OFFSET                                     29918
2040 #define QM_REG_PQTX2PF_18_RT_OFFSET                                     29919
2041 #define QM_REG_PQTX2PF_19_RT_OFFSET                                     29920
2042 #define QM_REG_PQTX2PF_20_RT_OFFSET                                     29921
2043 #define QM_REG_PQTX2PF_21_RT_OFFSET                                     29922
2044 #define QM_REG_PQTX2PF_22_RT_OFFSET                                     29923
2045 #define QM_REG_PQTX2PF_23_RT_OFFSET                                     29924
2046 #define QM_REG_PQTX2PF_24_RT_OFFSET                                     29925
2047 #define QM_REG_PQTX2PF_25_RT_OFFSET                                     29926
2048 #define QM_REG_PQTX2PF_26_RT_OFFSET                                     29927
2049 #define QM_REG_PQTX2PF_27_RT_OFFSET                                     29928
2050 #define QM_REG_PQTX2PF_28_RT_OFFSET                                     29929
2051 #define QM_REG_PQTX2PF_29_RT_OFFSET                                     29930
2052 #define QM_REG_PQTX2PF_30_RT_OFFSET                                     29931
2053 #define QM_REG_PQTX2PF_31_RT_OFFSET                                     29932
2054 #define QM_REG_PQTX2PF_32_RT_OFFSET                                     29933
2055 #define QM_REG_PQTX2PF_33_RT_OFFSET                                     29934
2056 #define QM_REG_PQTX2PF_34_RT_OFFSET                                     29935
2057 #define QM_REG_PQTX2PF_35_RT_OFFSET                                     29936
2058 #define QM_REG_PQTX2PF_36_RT_OFFSET                                     29937
2059 #define QM_REG_PQTX2PF_37_RT_OFFSET                                     29938
2060 #define QM_REG_PQTX2PF_38_RT_OFFSET                                     29939
2061 #define QM_REG_PQTX2PF_39_RT_OFFSET                                     29940
2062 #define QM_REG_PQTX2PF_40_RT_OFFSET                                     29941
2063 #define QM_REG_PQTX2PF_41_RT_OFFSET                                     29942
2064 #define QM_REG_PQTX2PF_42_RT_OFFSET                                     29943
2065 #define QM_REG_PQTX2PF_43_RT_OFFSET                                     29944
2066 #define QM_REG_PQTX2PF_44_RT_OFFSET                                     29945
2067 #define QM_REG_PQTX2PF_45_RT_OFFSET                                     29946
2068 #define QM_REG_PQTX2PF_46_RT_OFFSET                                     29947
2069 #define QM_REG_PQTX2PF_47_RT_OFFSET                                     29948
2070 #define QM_REG_PQTX2PF_48_RT_OFFSET                                     29949
2071 #define QM_REG_PQTX2PF_49_RT_OFFSET                                     29950
2072 #define QM_REG_PQTX2PF_50_RT_OFFSET                                     29951
2073 #define QM_REG_PQTX2PF_51_RT_OFFSET                                     29952
2074 #define QM_REG_PQTX2PF_52_RT_OFFSET                                     29953
2075 #define QM_REG_PQTX2PF_53_RT_OFFSET                                     29954
2076 #define QM_REG_PQTX2PF_54_RT_OFFSET                                     29955
2077 #define QM_REG_PQTX2PF_55_RT_OFFSET                                     29956
2078 #define QM_REG_PQTX2PF_56_RT_OFFSET                                     29957
2079 #define QM_REG_PQTX2PF_57_RT_OFFSET                                     29958
2080 #define QM_REG_PQTX2PF_58_RT_OFFSET                                     29959
2081 #define QM_REG_PQTX2PF_59_RT_OFFSET                                     29960
2082 #define QM_REG_PQTX2PF_60_RT_OFFSET                                     29961
2083 #define QM_REG_PQTX2PF_61_RT_OFFSET                                     29962
2084 #define QM_REG_PQTX2PF_62_RT_OFFSET                                     29963
2085 #define QM_REG_PQTX2PF_63_RT_OFFSET                                     29964
2086 #define QM_REG_PQOTHER2PF_0_RT_OFFSET                                   29965
2087 #define QM_REG_PQOTHER2PF_1_RT_OFFSET                                   29966
2088 #define QM_REG_PQOTHER2PF_2_RT_OFFSET                                   29967
2089 #define QM_REG_PQOTHER2PF_3_RT_OFFSET                                   29968
2090 #define QM_REG_PQOTHER2PF_4_RT_OFFSET                                   29969
2091 #define QM_REG_PQOTHER2PF_5_RT_OFFSET                                   29970
2092 #define QM_REG_PQOTHER2PF_6_RT_OFFSET                                   29971
2093 #define QM_REG_PQOTHER2PF_7_RT_OFFSET                                   29972
2094 #define QM_REG_PQOTHER2PF_8_RT_OFFSET                                   29973
2095 #define QM_REG_PQOTHER2PF_9_RT_OFFSET                                   29974
2096 #define QM_REG_PQOTHER2PF_10_RT_OFFSET                                  29975
2097 #define QM_REG_PQOTHER2PF_11_RT_OFFSET                                  29976
2098 #define QM_REG_PQOTHER2PF_12_RT_OFFSET                                  29977
2099 #define QM_REG_PQOTHER2PF_13_RT_OFFSET                                  29978
2100 #define QM_REG_PQOTHER2PF_14_RT_OFFSET                                  29979
2101 #define QM_REG_PQOTHER2PF_15_RT_OFFSET                                  29980
2102 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET                                 29981
2103 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET                                 29982
2104 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET                            29983
2105 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET                            29984
2106 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET                              29985
2107 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET                              29986
2108 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET                              29987
2109 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET                              29988
2110 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET                              29989
2111 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET                              29990
2112 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET                              29991
2113 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET                              29992
2114 #define QM_REG_RLGLBLINCVAL_RT_OFFSET                                   29993
2115 #define QM_REG_RLGLBLINCVAL_RT_SIZE                                     256
2116 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET                               30249
2117 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE                                 256
2118 #define QM_REG_RLGLBLCRD_RT_OFFSET                                      30505
2119 #define QM_REG_RLGLBLCRD_RT_SIZE                                        256
2120 #define QM_REG_RLGLBLENABLE_RT_OFFSET                                   30761
2121 #define QM_REG_RLPFPERIOD_RT_OFFSET                                     30762
2122 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET                                30763
2123 #define QM_REG_RLPFINCVAL_RT_OFFSET                                     30764
2124 #define QM_REG_RLPFINCVAL_RT_SIZE                                       16
2125 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET                                 30780
2126 #define QM_REG_RLPFUPPERBOUND_RT_SIZE                                   16
2127 #define QM_REG_RLPFCRD_RT_OFFSET                                        30796
2128 #define QM_REG_RLPFCRD_RT_SIZE                                          16
2129 #define QM_REG_RLPFENABLE_RT_OFFSET                                     30812
2130 #define QM_REG_RLPFVOQENABLE_RT_OFFSET                                  30813
2131 #define QM_REG_WFQPFWEIGHT_RT_OFFSET                                    30814
2132 #define QM_REG_WFQPFWEIGHT_RT_SIZE                                      16
2133 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET                                30830
2134 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE                                  16
2135 #define QM_REG_WFQPFCRD_RT_OFFSET                                       30846
2136 #define QM_REG_WFQPFCRD_RT_SIZE                                         160
2137 #define QM_REG_WFQPFENABLE_RT_OFFSET                                    31006
2138 #define QM_REG_WFQVPENABLE_RT_OFFSET                                    31007
2139 #define QM_REG_BASEADDRTXPQ_RT_OFFSET                                   31008
2140 #define QM_REG_BASEADDRTXPQ_RT_SIZE                                     512
2141 #define QM_REG_TXPQMAP_RT_OFFSET                                        31520
2142 #define QM_REG_TXPQMAP_RT_SIZE                                          512
2143 #define QM_REG_WFQVPWEIGHT_RT_OFFSET                                    32032
2144 #define QM_REG_WFQVPWEIGHT_RT_SIZE                                      512
2145 #define QM_REG_WFQVPUPPERBOUND_RT_OFFSET                                32544
2146 #define QM_REG_WFQVPUPPERBOUND_RT_SIZE                                  512
2147 #define QM_REG_WFQVPCRD_RT_OFFSET                                       33056
2148 #define QM_REG_WFQVPCRD_RT_SIZE                                         512
2149 #define QM_REG_WFQVPMAP_RT_OFFSET                                       33568
2150 #define QM_REG_WFQVPMAP_RT_SIZE                                         512
2151 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET                                   34080
2152 #define QM_REG_WFQPFCRD_MSB_RT_SIZE                                     160
2153 #define NIG_REG_LLH_CLS_TYPE_DUALMODE_RT_OFFSET                         34240
2154 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET                         34241
2155 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET                         34242
2156 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET                         34243
2157 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET                         34244
2158 #define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET                          34245
2159 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET                      34246
2160 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET                               34247
2161 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE                                 4
2162 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET                          34251
2163 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE                            4
2164 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET                            34255
2165 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE                              4
2166 #define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET                               34259
2167 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET                         34260
2168 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE                           32
2169 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET                            34292
2170 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE                              16
2171 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET                          34308
2172 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE                            16
2173 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET                 34324
2174 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE                   16
2175 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET                       34340
2176 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE                         16
2177 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET                                  34356
2178 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET                               34357
2179 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET                               34358
2180 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET                               34359
2181 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET                           34360
2182 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET                           34361
2183 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET                           34362
2184 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET                           34363
2185 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET                        34364
2186 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET                        34365
2187 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET                        34366
2188 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET                        34367
2189 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET                            34368
2190 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET                         34369
2191 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET                          34370
2192 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET                        34371
2193 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET                           34372
2194 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET                    34373
2195 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET                        34374
2196 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET                           34375
2197 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET                    34376
2198 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET                        34377
2199 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET                           34378
2200 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET                    34379
2201 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET                        34380
2202 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET                           34381
2203 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET                    34382
2204 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET                        34383
2205 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET                           34384
2206 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET                    34385
2207 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET                        34386
2208 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET                           34387
2209 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET                    34388
2210 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET                        34389
2211 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET                           34390
2212 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET                    34391
2213 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET                        34392
2214 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET                           34393
2215 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET                    34394
2216 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET                        34395
2217 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET                           34396
2218 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET                    34397
2219 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET                        34398
2220 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET                           34399
2221 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET                    34400
2222 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET                       34401
2223 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET                          34402
2224 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET                   34403
2225 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET                       34404
2226 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET                          34405
2227 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET                   34406
2228 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET                       34407
2229 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET                          34408
2230 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET                   34409
2231 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET                       34410
2232 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET                          34411
2233 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET                   34412
2234 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET                       34413
2235 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET                          34414
2236 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET                   34415
2237 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET                       34416
2238 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET                          34417
2239 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET                   34418
2240 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET                       34419
2241 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET                          34420
2242 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET                   34421
2243 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET                       34422
2244 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET                          34423
2245 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET                   34424
2246 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET                       34425
2247 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET                          34426
2248 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET                   34427
2249 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET                       34428
2250 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET                          34429
2251 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET                   34430
2252 #define XCM_REG_CON_PHY_Q3_RT_OFFSET                                    34431
2253
2254 #define RUNTIME_ARRAY_SIZE 34432
2255
2256 /* The eth storm context for the Ystorm */
2257 struct ystorm_eth_conn_st_ctx {
2258         __le32 reserved[4];
2259 };
2260
2261 /* The eth storm context for the Pstorm */
2262 struct pstorm_eth_conn_st_ctx {
2263         __le32 reserved[8];
2264 };
2265
2266 /* The eth storm context for the Xstorm */
2267 struct xstorm_eth_conn_st_ctx {
2268         __le32 reserved[60];
2269 };
2270
2271 struct xstorm_eth_conn_ag_ctx {
2272         u8      reserved0 /* cdu_validation */;
2273         u8      eth_state /* state */;
2274         u8      flags0;
2275 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK            0x1
2276 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT           0
2277 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK               0x1
2278 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT              1
2279 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK               0x1
2280 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT              2
2281 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK            0x1
2282 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT           3
2283 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK               0x1 /* bit4 */
2284 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT              4
2285 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK               0x1
2286 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT              5
2287 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK               0x1 /* bit6 */
2288 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT              6
2289 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK               0x1 /* bit7 */
2290 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT              7
2291         u8 flags1;
2292 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK               0x1 /* bit8 */
2293 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT              0
2294 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK               0x1 /* bit9 */
2295 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT              1
2296 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK               0x1 /* bit10 */
2297 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT              2
2298 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK                   0x1 /* bit11 */
2299 #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT                  3
2300 #define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK                   0x1 /* bit12 */
2301 #define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT                  4
2302 #define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK                   0x1 /* bit13 */
2303 #define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT                  5
2304 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK          0x1 /* bit14 */
2305 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT         6
2306 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK            0x1 /* bit15 */
2307 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT           7
2308         u8 flags2;
2309 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK                     0x3 /* timer0cf */
2310 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT                    0
2311 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK                     0x3 /* timer1cf */
2312 #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT                    2
2313 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK                     0x3 /* timer2cf */
2314 #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT                    4
2315 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK                     0x3
2316 #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT                    6
2317         u8 flags3;
2318 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK                     0x3 /* cf4 */
2319 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT                    0
2320 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK                     0x3 /* cf5 */
2321 #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT                    2
2322 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK                     0x3 /* cf6 */
2323 #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT                    4
2324 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK                     0x3 /* cf7 */
2325 #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT                    6
2326         u8 flags4;
2327 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK                     0x3 /* cf8 */
2328 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT                    0
2329 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK                     0x3 /* cf9 */
2330 #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT                    2
2331 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK                    0x3 /* cf10 */
2332 #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT                   4
2333 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK                    0x3 /* cf11 */
2334 #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT                   6
2335         u8 flags5;
2336 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK                    0x3 /* cf12 */
2337 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT                   0
2338 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK                    0x3 /* cf13 */
2339 #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT                   2
2340 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK                    0x3 /* cf14 */
2341 #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT                   4
2342 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK                    0x3 /* cf15 */
2343 #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT                   6
2344         u8 flags6;
2345 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK        0x3 /* cf16 */
2346 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT       0
2347 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK        0x3
2348 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT       2
2349 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK                   0x3 /* cf18 */
2350 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT                  4
2351 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK            0x3 /* cf19 */
2352 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT           6
2353         u8 flags7;
2354 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK                0x3 /* cf20 */
2355 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT               0
2356 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK              0x3 /* cf21 */
2357 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT             2
2358 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK               0x3 /* cf22 */
2359 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT              4
2360 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK                   0x1 /* cf0en */
2361 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT                  6
2362 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK                   0x1 /* cf1en */
2363 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT                  7
2364         u8 flags8;
2365 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK                   0x1 /* cf2en */
2366 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                  0
2367 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK                   0x1 /* cf3en */
2368 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT                  1
2369 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK                   0x1 /* cf4en */
2370 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT                  2
2371 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK                   0x1 /* cf5en */
2372 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT                  3
2373 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK                   0x1 /* cf6en */
2374 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT                  4
2375 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK                   0x1 /* cf7en */
2376 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT                  5
2377 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK                   0x1 /* cf8en */
2378 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT                  6
2379 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK                   0x1 /* cf9en */
2380 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT                  7
2381         u8 flags9;
2382 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK                  0x1 /* cf10en */
2383 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT                 0
2384 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK                  0x1 /* cf11en */
2385 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT                 1
2386 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK                  0x1 /* cf12en */
2387 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT                 2
2388 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK                  0x1 /* cf13en */
2389 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT                 3
2390 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK                  0x1 /* cf14en */
2391 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT                 4
2392 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK                  0x1 /* cf15en */
2393 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT                 5
2394 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK     0x1 /* cf16en */
2395 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT    6
2396 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK     0x1
2397 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT    7
2398         u8 flags10;
2399 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK                0x1 /* cf18en */
2400 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT               0
2401 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK         0x1 /* cf19en */
2402 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT        1
2403 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK             0x1 /* cf20en */
2404 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT            2
2405 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK              0x1 /* cf21en */
2406 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT             3
2407 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK            0x1 /* cf22en */
2408 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT           4
2409 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK  0x1 /* cf23en */
2410 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
2411 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK              0x1 /* rule0en */
2412 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT             6
2413 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK              0x1 /* rule1en */
2414 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT             7
2415         u8 flags11;
2416 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK              0x1 /* rule2en */
2417 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT             0
2418 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK              0x1 /* rule3en */
2419 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT             1
2420 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK          0x1 /* rule4en */
2421 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT         2
2422 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK                 0x1 /* rule5en */
2423 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT                3
2424 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK                 0x1 /* rule6en */
2425 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT                4
2426 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK                 0x1 /* rule7en */
2427 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT                5
2428 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK            0x1 /* rule8en */
2429 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT           6
2430 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK                 0x1 /* rule9en */
2431 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT                7
2432         u8 flags12;
2433 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK                0x1 /* rule10en */
2434 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT               0
2435 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK                0x1 /* rule11en */
2436 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT               1
2437 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK            0x1 /* rule12en */
2438 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT           2
2439 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK            0x1 /* rule13en */
2440 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT           3
2441 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK                0x1 /* rule14en */
2442 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT               4
2443 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK                0x1 /* rule15en */
2444 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT               5
2445 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK                0x1 /* rule16en */
2446 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT               6
2447 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK                0x1 /* rule17en */
2448 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT               7
2449         u8 flags13;
2450 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK                0x1 /* rule18en */
2451 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT               0
2452 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK                0x1 /* rule19en */
2453 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT               1
2454 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK            0x1 /* rule20en */
2455 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT           2
2456 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK            0x1 /* rule21en */
2457 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT           3
2458 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK            0x1 /* rule22en */
2459 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT           4
2460 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK            0x1 /* rule23en */
2461 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT           5
2462 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK            0x1 /* rule24en */
2463 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT           6
2464 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK            0x1 /* rule25en */
2465 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT           7
2466         u8 flags14;
2467 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK        0x1 /* bit16 */
2468 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT       0
2469 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK      0x1 /* bit17 */
2470 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT     1
2471 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK    0x1 /* bit18 */
2472 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT   2
2473 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK    0x1 /* bit19 */
2474 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT   3
2475 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK          0x1 /* bit20 */
2476 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT         4
2477 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK        0x1 /* bit21 */
2478 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT       5
2479 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK              0x3 /* cf23 */
2480 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT             6
2481         u8      edpm_event_id /* byte2 */;
2482         __le16  physical_q0 /* physical_q0 */;
2483         __le16  word1 /* physical_q1 */;
2484         __le16  edpm_num_bds /* physical_q2 */;
2485         __le16  tx_bd_cons /* word3 */;
2486         __le16  tx_bd_prod /* word4 */;
2487         __le16  go_to_bd_cons /* word5 */;
2488         __le16  conn_dpi /* conn_dpi */;
2489         u8      byte3 /* byte3 */;
2490         u8      byte4 /* byte4 */;
2491         u8      byte5 /* byte5 */;
2492         u8      byte6 /* byte6 */;
2493         __le32  reg0 /* reg0 */;
2494         __le32  reg1 /* reg1 */;
2495         __le32  reg2 /* reg2 */;
2496         __le32  reg3 /* reg3 */;
2497         __le32  reg4 /* reg4 */;
2498         __le32  reg5 /* cf_array0 */;
2499         __le32  reg6 /* cf_array1 */;
2500         __le16  word7 /* word7 */;
2501         __le16  word8 /* word8 */;
2502         __le16  word9 /* word9 */;
2503         __le16  word10 /* word10 */;
2504         __le32  reg7 /* reg7 */;
2505         __le32  reg8 /* reg8 */;
2506         __le32  reg9 /* reg9 */;
2507         u8      byte7 /* byte7 */;
2508         u8      byte8 /* byte8 */;
2509         u8      byte9 /* byte9 */;
2510         u8      byte10 /* byte10 */;
2511         u8      byte11 /* byte11 */;
2512         u8      byte12 /* byte12 */;
2513         u8      byte13 /* byte13 */;
2514         u8      byte14 /* byte14 */;
2515         u8      byte15 /* byte15 */;
2516         u8      byte16 /* byte16 */;
2517         __le16  word11 /* word11 */;
2518         __le32  reg10 /* reg10 */;
2519         __le32  reg11 /* reg11 */;
2520         __le32  reg12 /* reg12 */;
2521         __le32  reg13 /* reg13 */;
2522         __le32  reg14 /* reg14 */;
2523         __le32  reg15 /* reg15 */;
2524         __le32  reg16 /* reg16 */;
2525         __le32  reg17 /* reg17 */;
2526         __le32  reg18 /* reg18 */;
2527         __le32  reg19 /* reg19 */;
2528         __le16  word12 /* word12 */;
2529         __le16  word13 /* word13 */;
2530         __le16  word14 /* word14 */;
2531         __le16  word15 /* word15 */;
2532 };
2533
2534 /* The eth storm context for the Tstorm */
2535 struct tstorm_eth_conn_st_ctx {
2536         __le32 reserved[4];
2537 };
2538
2539 /* The eth storm context for the Mstorm */
2540 struct mstorm_eth_conn_st_ctx {
2541         __le32 reserved[8];
2542 };
2543
2544 /* The eth storm context for the Ustorm */
2545 struct ustorm_eth_conn_st_ctx {
2546         __le32 reserved[40];
2547 };
2548
2549 /* eth connection context */
2550 struct eth_conn_context {
2551         struct ystorm_eth_conn_st_ctx   ystorm_st_context;
2552         struct regpair                  ystorm_st_padding[2] /* padding */;
2553         struct pstorm_eth_conn_st_ctx   pstorm_st_context;
2554         struct regpair                  pstorm_st_padding[2] /* padding */;
2555         struct xstorm_eth_conn_st_ctx   xstorm_st_context;
2556         struct xstorm_eth_conn_ag_ctx   xstorm_ag_context;
2557         struct tstorm_eth_conn_st_ctx   tstorm_st_context;
2558         struct regpair                  tstorm_st_padding[2] /* padding */;
2559         struct mstorm_eth_conn_st_ctx   mstorm_st_context;
2560         struct ustorm_eth_conn_st_ctx   ustorm_st_context;
2561 };
2562
2563 struct mstorm_eth_conn_ag_ctx {
2564         u8      byte0 /* cdu_validation */;
2565         u8      byte1 /* state */;
2566         u8      flags0;
2567 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK  0x1   /* exist_in_qm0 */
2568 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
2569 #define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK          0x1   /* exist_in_qm1 */
2570 #define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT         1
2571 #define MSTORM_ETH_CONN_AG_CTX_CF0_MASK           0x3   /* cf0 */
2572 #define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT          2
2573 #define MSTORM_ETH_CONN_AG_CTX_CF1_MASK           0x3   /* cf1 */
2574 #define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT          4
2575 #define MSTORM_ETH_CONN_AG_CTX_CF2_MASK           0x3   /* cf2 */
2576 #define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT          6
2577         u8 flags1;
2578 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK         0x1   /* cf0en */
2579 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT        0
2580 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK         0x1   /* cf1en */
2581 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT        1
2582 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK         0x1   /* cf2en */
2583 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT        2
2584 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK       0x1   /* rule0en */
2585 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT      3
2586 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK       0x1   /* rule1en */
2587 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT      4
2588 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK       0x1   /* rule2en */
2589 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT      5
2590 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK       0x1   /* rule3en */
2591 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT      6
2592 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK       0x1   /* rule4en */
2593 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT      7
2594         __le16  word0 /* word0 */;
2595         __le16  word1 /* word1 */;
2596         __le32  reg0 /* reg0 */;
2597         __le32  reg1 /* reg1 */;
2598 };
2599
2600 struct tstorm_eth_conn_ag_ctx {
2601         u8      byte0 /* cdu_validation */;
2602         u8      byte1 /* state */;
2603         u8      flags0;
2604 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK      0x1       /* exist_in_qm0 */
2605 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT     0
2606 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK      0x1       /* exist_in_qm1 */
2607 #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT     1
2608 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK      0x1       /* bit2 */
2609 #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT     2
2610 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK      0x1       /* bit3 */
2611 #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT     3
2612 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK      0x1       /* bit4 */
2613 #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT     4
2614 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK      0x1       /* bit5 */
2615 #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT     5
2616 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK       0x3       /* timer0cf */
2617 #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT      6
2618         u8 flags1;
2619 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK       0x3       /* timer1cf */
2620 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT      0
2621 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK       0x3       /* timer2cf */
2622 #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT      2
2623 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK       0x3       /* timer_stop_all */
2624 #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT      4
2625 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK       0x3       /* cf4 */
2626 #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT      6
2627         u8 flags2;
2628 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK       0x3       /* cf5 */
2629 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT      0
2630 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK       0x3       /* cf6 */
2631 #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT      2
2632 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK       0x3       /* cf7 */
2633 #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT      4
2634 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK       0x3       /* cf8 */
2635 #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT      6
2636         u8 flags3;
2637 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK       0x3       /* cf9 */
2638 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT      0
2639 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK      0x3       /* cf10 */
2640 #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT     2
2641 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK     0x1       /* cf0en */
2642 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT    4
2643 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK     0x1       /* cf1en */
2644 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT    5
2645 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK     0x1       /* cf2en */
2646 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT    6
2647 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK     0x1       /* cf3en */
2648 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT    7
2649         u8 flags4;
2650 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK     0x1       /* cf4en */
2651 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT    0
2652 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK     0x1       /* cf5en */
2653 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT    1
2654 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK     0x1       /* cf6en */
2655 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT    2
2656 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK     0x1       /* cf7en */
2657 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT    3
2658 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK     0x1       /* cf8en */
2659 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT    4
2660 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK     0x1       /* cf9en */
2661 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT    5
2662 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK    0x1       /* cf10en */
2663 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT   6
2664 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK   0x1       /* rule0en */
2665 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT  7
2666         u8 flags5;
2667 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK   0x1       /* rule1en */
2668 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT  0
2669 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK   0x1       /* rule2en */
2670 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT  1
2671 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK   0x1       /* rule3en */
2672 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT  2
2673 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK   0x1       /* rule4en */
2674 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT  3
2675 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK   0x1       /* rule5en */
2676 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT  4
2677 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK  0x1       /* rule6en */
2678 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
2679 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK   0x1       /* rule7en */
2680 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT  6
2681 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK   0x1       /* rule8en */
2682 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT  7
2683         __le32  reg0 /* reg0 */;
2684         __le32  reg1 /* reg1 */;
2685         __le32  reg2 /* reg2 */;
2686         __le32  reg3 /* reg3 */;
2687         __le32  reg4 /* reg4 */;
2688         __le32  reg5 /* reg5 */;
2689         __le32  reg6 /* reg6 */;
2690         __le32  reg7 /* reg7 */;
2691         __le32  reg8 /* reg8 */;
2692         u8      byte2 /* byte2 */;
2693         u8      byte3 /* byte3 */;
2694         __le16  rx_bd_cons /* word0 */;
2695         u8      byte4 /* byte4 */;
2696         u8      byte5 /* byte5 */;
2697         __le16  rx_bd_prod /* word1 */;
2698         __le16  word2 /* conn_dpi */;
2699         __le16  word3 /* word3 */;
2700         __le32  reg9 /* reg9 */;
2701         __le32  reg10 /* reg10 */;
2702 };
2703
2704 struct ustorm_eth_conn_ag_ctx {
2705         u8      byte0 /* cdu_validation */;
2706         u8      byte1 /* state */;
2707         u8      flags0;
2708 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK                  0x1
2709 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT                 0
2710 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK                  0x1
2711 #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT                 1
2712 #define USTORM_ETH_CONN_AG_CTX_CF0_MASK                   0x3   /* timer0cf */
2713 #define USTORM_ETH_CONN_AG_CTX_CF0_SHIFT                  2
2714 #define USTORM_ETH_CONN_AG_CTX_CF1_MASK                   0x3   /* timer1cf */
2715 #define USTORM_ETH_CONN_AG_CTX_CF1_SHIFT                  4
2716 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK                   0x3   /* timer2cf */
2717 #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT                  6
2718         u8 flags1;
2719 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK                   0x3
2720 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT                  0
2721 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK             0x3   /* cf4 */
2722 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT            2
2723 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK             0x3   /* cf5 */
2724 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT            4
2725 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK     0x3   /* cf6 */
2726 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT    6
2727         u8 flags2;
2728 #define USTORM_ETH_CONN_AG_CTX_CF0EN_MASK                 0x1   /* cf0en */
2729 #define USTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT                0
2730 #define USTORM_ETH_CONN_AG_CTX_CF1EN_MASK                 0x1   /* cf1en */
2731 #define USTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT                1
2732 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK                 0x1   /* cf2en */
2733 #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                2
2734 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK                 0x1   /* cf3en */
2735 #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT                3
2736 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK          0x1   /* cf4en */
2737 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT         4
2738 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK          0x1   /* cf5en */
2739 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT         5
2740 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK  0x1   /* cf6en */
2741 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
2742 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK               0x1   /* rule0en */
2743 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT              7
2744         u8 flags3;
2745 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK               0x1   /* rule1en */
2746 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT              0
2747 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK               0x1   /* rule2en */
2748 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT              1
2749 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK               0x1   /* rule3en */
2750 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT              2
2751 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK               0x1   /* rule4en */
2752 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT              3
2753 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK               0x1   /* rule5en */
2754 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT              4
2755 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK               0x1   /* rule6en */
2756 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT              5
2757 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK               0x1   /* rule7en */
2758 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT              6
2759 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK               0x1   /* rule8en */
2760 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT              7
2761         u8      byte2 /* byte2 */;
2762         u8      byte3 /* byte3 */;
2763         __le16  word0 /* conn_dpi */;
2764         __le16  tx_bd_cons /* word1 */;
2765         __le32  reg0 /* reg0 */;
2766         __le32  reg1 /* reg1 */;
2767         __le32  reg2 /* reg2 */;
2768         __le32  reg3 /* reg3 */;
2769         __le16  tx_drv_bd_cons /* word2 */;
2770         __le16  rx_drv_cqe_cons /* word3 */;
2771 };
2772
2773 struct xstorm_eth_hw_conn_ag_ctx {
2774         u8      reserved0 /* cdu_validation */;
2775         u8      eth_state /* state */;
2776         u8      flags0;
2777 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK            0x1
2778 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT           0
2779 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK               0x1
2780 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT              1
2781 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK               0x1
2782 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT              2
2783 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK            0x1
2784 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT           3
2785 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK               0x1
2786 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT              4
2787 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK               0x1
2788 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT              5
2789 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK               0x1
2790 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT              6
2791 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK               0x1
2792 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT              7
2793         u8 flags1;
2794 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK               0x1
2795 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT              0
2796 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK               0x1
2797 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT              1
2798 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK               0x1
2799 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT              2
2800 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK                   0x1
2801 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT                  3
2802 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK                   0x1
2803 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT                  4
2804 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK                   0x1
2805 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT                  5
2806 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK          0x1
2807 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT         6
2808 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK            0x1
2809 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT           7
2810         u8 flags2;
2811 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK                     0x3
2812 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT                    0
2813 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK                     0x3
2814 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT                    2
2815 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK                     0x3
2816 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT                    4
2817 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK                     0x3
2818 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT                    6
2819         u8 flags3;
2820 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK                     0x3
2821 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT                    0
2822 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK                     0x3
2823 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT                    2
2824 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK                     0x3
2825 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT                    4
2826 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK                     0x3
2827 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT                    6
2828         u8 flags4;
2829 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK                     0x3
2830 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT                    0
2831 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK                     0x3
2832 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT                    2
2833 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK                    0x3
2834 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT                   4
2835 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK                    0x3
2836 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT                   6
2837         u8 flags5;
2838 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK                    0x3
2839 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT                   0
2840 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK                    0x3
2841 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT                   2
2842 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK                    0x3
2843 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT                   4
2844 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK                    0x3
2845 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT                   6
2846         u8 flags6;
2847 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK        0x3
2848 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT       0
2849 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK        0x3
2850 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT       2
2851 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK                   0x3
2852 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT                  4
2853 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK            0x3
2854 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT           6
2855         u8 flags7;
2856 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK                0x3
2857 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT               0
2858 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK              0x3
2859 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT             2
2860 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK               0x3
2861 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT              4
2862 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK                   0x1
2863 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT                  6
2864 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK                   0x1
2865 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT                  7
2866         u8 flags8;
2867 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK                   0x1
2868 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT                  0
2869 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK                   0x1
2870 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT                  1
2871 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK                   0x1
2872 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT                  2
2873 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK                   0x1
2874 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT                  3
2875 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK                   0x1
2876 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT                  4
2877 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK                   0x1
2878 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT                  5
2879 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK                   0x1
2880 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT                  6
2881 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK                   0x1
2882 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT                  7
2883         u8 flags9;
2884 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK                  0x1
2885 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT                 0
2886 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK                  0x1
2887 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT                 1
2888 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK                  0x1
2889 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT                 2
2890 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK                  0x1
2891 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT                 3
2892 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK                  0x1
2893 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT                 4
2894 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK                  0x1
2895 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT                 5
2896 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK     0x1
2897 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT    6
2898 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK     0x1
2899 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT    7
2900         u8 flags10;
2901 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK                0x1
2902 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT               0
2903 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK         0x1
2904 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT        1
2905 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK             0x1
2906 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT            2
2907 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK              0x1
2908 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT             3
2909 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK            0x1
2910 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT           4
2911 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK  0x1
2912 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
2913 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK              0x1
2914 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT             6
2915 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK              0x1
2916 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT             7
2917         u8 flags11;
2918 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK              0x1
2919 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT             0
2920 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK              0x1
2921 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT             1
2922 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK          0x1
2923 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT         2
2924 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK                 0x1
2925 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT                3
2926 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK                 0x1
2927 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT                4
2928 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK                 0x1
2929 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT                5
2930 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK            0x1
2931 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT           6
2932 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK                 0x1
2933 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT                7
2934         u8 flags12;
2935 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK                0x1
2936 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT               0
2937 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK                0x1
2938 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT               1
2939 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK            0x1
2940 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT           2
2941 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK            0x1
2942 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT           3
2943 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK                0x1
2944 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT               4
2945 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK                0x1
2946 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT               5
2947 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK                0x1
2948 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT               6
2949 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK                0x1
2950 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT               7
2951         u8 flags13;
2952 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK                0x1
2953 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT               0
2954 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK                0x1
2955 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT               1
2956 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK            0x1
2957 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT           2
2958 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK            0x1
2959 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT           3
2960 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK            0x1
2961 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT           4
2962 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK            0x1
2963 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT           5
2964 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK            0x1
2965 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT           6
2966 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK            0x1
2967 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT           7
2968         u8 flags14;
2969 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK        0x1
2970 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT       0
2971 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK      0x1
2972 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT     1
2973 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK    0x1
2974 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT   2
2975 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK    0x1
2976 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT   3
2977 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK          0x1
2978 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT         4
2979 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK        0x1
2980 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT       5
2981 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK              0x3
2982 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT             6
2983         u8      edpm_event_id /* byte2 */;
2984         __le16  physical_q0 /* physical_q0 */;
2985         __le16  word1 /* physical_q1 */;
2986         __le16  edpm_num_bds /* physical_q2 */;
2987         __le16  tx_bd_cons /* word3 */;
2988         __le16  tx_bd_prod /* word4 */;
2989         __le16  go_to_bd_cons /* word5 */;
2990         __le16  conn_dpi /* conn_dpi */;
2991 };
2992
2993 #define VF_MAX_STATIC 192       /* In case of K2 */
2994
2995 #define MCP_GLOB_PATH_MAX       2
2996 #define MCP_PORT_MAX            2       /* Global */
2997 #define MCP_GLOB_PORT_MAX       4       /* Global */
2998 #define MCP_GLOB_FUNC_MAX       16      /* Global */
2999
3000 typedef u32 offsize_t;                  /* In DWORDS !!! */
3001 /* Offset from the beginning of the MCP scratchpad */
3002 #define OFFSIZE_OFFSET_SHIFT    0
3003 #define OFFSIZE_OFFSET_MASK     0x0000ffff
3004 /* Size of specific element (not the whole array if any) */
3005 #define OFFSIZE_SIZE_SHIFT      16
3006 #define OFFSIZE_SIZE_MASK       0xffff0000
3007
3008 /* SECTION_OFFSET is calculating the offset in bytes out of offsize */
3009 #define SECTION_OFFSET(_offsize)        ((((_offsize &              \
3010                                             OFFSIZE_OFFSET_MASK) >> \
3011                                            OFFSIZE_OFFSET_SHIFT) << 2))
3012
3013 /* QED_SECTION_SIZE is calculating the size in bytes out of offsize */
3014 #define QED_SECTION_SIZE(_offsize)              (((_offsize &            \
3015                                                    OFFSIZE_SIZE_MASK) >> \
3016                                                   OFFSIZE_SIZE_SHIFT) << 2)
3017
3018 /* SECTION_ADDR returns the GRC addr of a section, given offsize and index
3019  * within section.
3020  */
3021 #define SECTION_ADDR(_offsize, idx)     (MCP_REG_SCRATCH +          \
3022                                          SECTION_OFFSET(_offsize) + \
3023                                          (QED_SECTION_SIZE(_offsize) * idx))
3024
3025 /* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address.
3026  * Use offsetof, since the OFFSETUP collide with the firmware definition
3027  */
3028 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) (_pub_base +               \
3029                                                    offsetof(struct           \
3030                                                             mcp_public_data, \
3031                                                             sections[_section]))
3032 /* PHY configuration */
3033 struct pmm_phy_cfg {
3034         u32     speed;
3035 #define PMM_SPEED_AUTONEG   0
3036
3037         u32     pause;  /* bitmask */
3038 #define PMM_PAUSE_NONE          0x0
3039 #define PMM_PAUSE_AUTONEG       0x1
3040 #define PMM_PAUSE_RX            0x2
3041 #define PMM_PAUSE_TX            0x4
3042
3043         u32     adv_speed;  /* Default should be the speed_cap_mask */
3044         u32     loopback_mode;
3045 #define PMM_LOOPBACK_NONE               0
3046 #define PMM_LOOPBACK_INT_PHY    1
3047 #define PMM_LOOPBACK_EXT_PHY    2
3048 #define PMM_LOOPBACK_EXT                3
3049 #define PMM_LOOPBACK_MAC                4
3050
3051         /* features */
3052         u32 feature_config_flags;
3053 };
3054
3055 struct port_mf_cfg {
3056         u32     dynamic_cfg; /* device control channel */
3057 #define PORT_MF_CFG_OV_TAG_MASK              0x0000ffff
3058 #define PORT_MF_CFG_OV_TAG_SHIFT             0
3059 #define PORT_MF_CFG_OV_TAG_DEFAULT         PORT_MF_CFG_OV_TAG_MASK
3060
3061         u32     reserved[1];
3062 };
3063
3064 /* DO NOT add new fields in the middle
3065  * MUST be synced with struct pmm_stats_map
3066  */
3067 struct pmm_stats {
3068         u64     r64;    /* 0x00 (Offset 0x00 ) RX 64-byte frame counter*/
3069         u64     r127;   /* 0x01 (Offset 0x08 ) RX 65 to 127 byte frame counter*/
3070         u64     r255;
3071         u64     r511;
3072         u64     r1023;
3073         u64     r1518;
3074         u64     r1522;
3075         u64     r2047;
3076         u64     r4095;
3077         u64     r9216;
3078         u64     r16383;
3079         u64     rfcs;   /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/
3080         u64     rxcf;   /* 0x10 (Offset 0x60 ) RX control frame counter*/
3081         u64     rxpf;   /* 0x11 (Offset 0x68 ) RX pause frame counter*/
3082         u64     rxpp;   /* 0x12 (Offset 0x70 ) RX PFC frame counter*/
3083         u64     raln;   /* 0x16 (Offset 0x78 ) RX alignment error counter*/
3084         u64     rfcr;   /* 0x19 (Offset 0x80 ) RX false carrier counter */
3085         u64     rovr;   /* 0x1A (Offset 0x88 ) RX oversized frame counter*/
3086         u64     rjbr;   /* 0x1B (Offset 0x90 ) RX jabber frame counter */
3087         u64     rund;   /* 0x34 (Offset 0x98 ) RX undersized frame counter */
3088         u64     rfrg;   /* 0x35 (Offset 0xa0 ) RX fragment counter */
3089         u64     t64;    /* 0x40 (Offset 0xa8 ) TX 64-byte frame counter */
3090         u64     t127;
3091         u64     t255;
3092         u64     t511;
3093         u64     t1023;
3094         u64     t1518;
3095         u64     t2047;
3096         u64     t4095;
3097         u64     t9216;
3098         u64     t16383;
3099         u64     txpf;   /* 0x50 (Offset 0xf8 ) TX pause frame counter */
3100         u64     txpp;   /* 0x51 (Offset 0x100) TX PFC frame counter */
3101         u64     tlpiec;
3102         u64     tncl;
3103         u64     rbyte;  /* 0x3d (Offset 0x118) RX byte counter */
3104         u64     rxuca;  /* 0x0c (Offset 0x120) RX UC frame counter */
3105         u64     rxmca;  /* 0x0d (Offset 0x128) RX MC frame counter */
3106         u64     rxbca;  /* 0x0e (Offset 0x130) RX BC frame counter */
3107         u64     rxpok;
3108         u64     tbyte;  /* 0x6f (Offset 0x140) TX byte counter */
3109         u64     txuca;  /* 0x4d (Offset 0x148) TX UC frame counter */
3110         u64     txmca;  /* 0x4e (Offset 0x150) TX MC frame counter */
3111         u64     txbca;  /* 0x4f (Offset 0x158) TX BC frame counter */
3112         u64     txcf;   /* 0x54 (Offset 0x160) TX control frame counter */
3113 };
3114
3115 struct brb_stats {
3116         u64     brb_truncate[8];
3117         u64     brb_discard[8];
3118 };
3119
3120 struct port_stats {
3121         struct brb_stats        brb;
3122         struct pmm_stats        pmm;
3123 };
3124
3125 #define CMT_TEAM0 0
3126 #define CMT_TEAM1 1
3127 #define CMT_TEAM_MAX 2
3128
3129 struct couple_mode_teaming {
3130         u8 port_cmt[MCP_GLOB_PORT_MAX];
3131 #define PORT_CMT_IN_TEAM                BIT(0)
3132
3133 #define PORT_CMT_PORT_ROLE              BIT(1)
3134 #define PORT_CMT_PORT_INACTIVE      (0 << 1)
3135 #define PORT_CMT_PORT_ACTIVE            BIT(1)
3136
3137 #define PORT_CMT_TEAM_MASK              BIT(2)
3138 #define PORT_CMT_TEAM0              (0 << 2)
3139 #define PORT_CMT_TEAM1                  BIT(2)
3140 };
3141
3142 /**************************************
3143 *     LLDP and DCBX HSI structures
3144 **************************************/
3145 #define LLDP_CHASSIS_ID_STAT_LEN 4
3146 #define LLDP_PORT_ID_STAT_LEN 4
3147 #define DCBX_MAX_APP_PROTOCOL           32
3148 #define MAX_SYSTEM_LLDP_TLV_DATA    32
3149
3150 enum lldp_agent_e {
3151         LLDP_NEAREST_BRIDGE = 0,
3152         LLDP_NEAREST_NON_TPMR_BRIDGE,
3153         LLDP_NEAREST_CUSTOMER_BRIDGE,
3154         LLDP_MAX_LLDP_AGENTS
3155 };
3156
3157 struct lldp_config_params_s {
3158         u32 config;
3159 #define LLDP_CONFIG_TX_INTERVAL_MASK        0x000000ff
3160 #define LLDP_CONFIG_TX_INTERVAL_SHIFT       0
3161 #define LLDP_CONFIG_HOLD_MASK               0x00000f00
3162 #define LLDP_CONFIG_HOLD_SHIFT              8
3163 #define LLDP_CONFIG_MAX_CREDIT_MASK         0x0000f000
3164 #define LLDP_CONFIG_MAX_CREDIT_SHIFT        12
3165 #define LLDP_CONFIG_ENABLE_RX_MASK          0x40000000
3166 #define LLDP_CONFIG_ENABLE_RX_SHIFT         30
3167 #define LLDP_CONFIG_ENABLE_TX_MASK          0x80000000
3168 #define LLDP_CONFIG_ENABLE_TX_SHIFT         31
3169         u32     local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
3170         u32     local_port_id[LLDP_PORT_ID_STAT_LEN];
3171 };
3172
3173 struct lldp_status_params_s {
3174         u32     prefix_seq_num;
3175         u32     status; /* TBD */
3176
3177         /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
3178         u32     peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
3179
3180         /* Holds remote Port ID TLV header, subtype and 9B of payload. */
3181         u32     peer_port_id[LLDP_PORT_ID_STAT_LEN];
3182         u32     suffix_seq_num;
3183 };
3184
3185 struct dcbx_ets_feature {
3186         u32 flags;
3187 #define DCBX_ETS_ENABLED_MASK                   0x00000001
3188 #define DCBX_ETS_ENABLED_SHIFT                  0
3189 #define DCBX_ETS_WILLING_MASK                   0x00000002
3190 #define DCBX_ETS_WILLING_SHIFT                  1
3191 #define DCBX_ETS_ERROR_MASK                     0x00000004
3192 #define DCBX_ETS_ERROR_SHIFT                    2
3193 #define DCBX_ETS_CBS_MASK                       0x00000008
3194 #define DCBX_ETS_CBS_SHIFT                      3
3195 #define DCBX_ETS_MAX_TCS_MASK                   0x000000f0
3196 #define DCBX_ETS_MAX_TCS_SHIFT                  4
3197         u32     pri_tc_tbl[1];
3198 #define DCBX_ISCSI_OOO_TC                       4
3199 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET         (DCBX_ISCSI_OOO_TC + 1)
3200         u32     tc_bw_tbl[2];
3201         u32     tc_tsa_tbl[2];
3202 #define DCBX_ETS_TSA_STRICT                     0
3203 #define DCBX_ETS_TSA_CBS                        1
3204 #define DCBX_ETS_TSA_ETS                        2
3205 };
3206
3207 struct dcbx_app_priority_entry {
3208         u32 entry;
3209 #define DCBX_APP_PRI_MAP_MASK       0x000000ff
3210 #define DCBX_APP_PRI_MAP_SHIFT      0
3211 #define DCBX_APP_PRI_0              0x01
3212 #define DCBX_APP_PRI_1              0x02
3213 #define DCBX_APP_PRI_2              0x04
3214 #define DCBX_APP_PRI_3              0x08
3215 #define DCBX_APP_PRI_4              0x10
3216 #define DCBX_APP_PRI_5              0x20
3217 #define DCBX_APP_PRI_6              0x40
3218 #define DCBX_APP_PRI_7              0x80
3219 #define DCBX_APP_SF_MASK            0x00000300
3220 #define DCBX_APP_SF_SHIFT           8
3221 #define DCBX_APP_SF_ETHTYPE         0
3222 #define DCBX_APP_SF_PORT            1
3223 #define DCBX_APP_PROTOCOL_ID_MASK   0xffff0000
3224 #define DCBX_APP_PROTOCOL_ID_SHIFT  16
3225 };
3226
3227 /* FW structure in BE */
3228 struct dcbx_app_priority_feature {
3229         u32 flags;
3230 #define DCBX_APP_ENABLED_MASK           0x00000001
3231 #define DCBX_APP_ENABLED_SHIFT          0
3232 #define DCBX_APP_WILLING_MASK           0x00000002
3233 #define DCBX_APP_WILLING_SHIFT          1
3234 #define DCBX_APP_ERROR_MASK             0x00000004
3235 #define DCBX_APP_ERROR_SHIFT            2
3236 /* Not in use
3237  * #define DCBX_APP_DEFAULT_PRI_MASK       0x00000f00
3238  * #define DCBX_APP_DEFAULT_PRI_SHIFT      8
3239  */
3240 #define DCBX_APP_MAX_TCS_MASK           0x0000f000
3241 #define DCBX_APP_MAX_TCS_SHIFT          12
3242 #define DCBX_APP_NUM_ENTRIES_MASK       0x00ff0000
3243 #define DCBX_APP_NUM_ENTRIES_SHIFT      16
3244         struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
3245 };
3246
3247 /* FW structure in BE */
3248 struct dcbx_features {
3249         /* PG feature */
3250         struct dcbx_ets_feature ets;
3251
3252         /* PFC feature */
3253         u32                     pfc;
3254 #define DCBX_PFC_PRI_EN_BITMAP_MASK             0x000000ff
3255 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT            0
3256 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0            0x01
3257 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1            0x02
3258 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2            0x04
3259 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3            0x08
3260 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4            0x10
3261 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5            0x20
3262 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6            0x40
3263 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7            0x80
3264
3265 #define DCBX_PFC_FLAGS_MASK                     0x0000ff00
3266 #define DCBX_PFC_FLAGS_SHIFT                    8
3267 #define DCBX_PFC_CAPS_MASK                      0x00000f00
3268 #define DCBX_PFC_CAPS_SHIFT                     8
3269 #define DCBX_PFC_MBC_MASK                       0x00004000
3270 #define DCBX_PFC_MBC_SHIFT                      14
3271 #define DCBX_PFC_WILLING_MASK                   0x00008000
3272 #define DCBX_PFC_WILLING_SHIFT                  15
3273 #define DCBX_PFC_ENABLED_MASK                   0x00010000
3274 #define DCBX_PFC_ENABLED_SHIFT                  16
3275 #define DCBX_PFC_ERROR_MASK                     0x00020000
3276 #define DCBX_PFC_ERROR_SHIFT                    17
3277
3278         /* APP feature */
3279         struct dcbx_app_priority_feature app;
3280 };
3281
3282 struct dcbx_local_params {
3283         u32 config;
3284 #define DCBX_CONFIG_VERSION_MASK            0x00000003
3285 #define DCBX_CONFIG_VERSION_SHIFT           0
3286 #define DCBX_CONFIG_VERSION_DISABLED        0
3287 #define DCBX_CONFIG_VERSION_IEEE            1
3288 #define DCBX_CONFIG_VERSION_CEE             2
3289
3290         u32                     flags;
3291         struct dcbx_features    features;
3292 };
3293
3294 struct dcbx_mib {
3295         u32     prefix_seq_num;
3296         u32     flags;
3297         struct dcbx_features    features;
3298         u32                     suffix_seq_num;
3299 };
3300
3301 struct lldp_system_tlvs_buffer_s {
3302         u16     valid;
3303         u16     length;
3304         u32     data[MAX_SYSTEM_LLDP_TLV_DATA];
3305 };
3306
3307 /**************************************/
3308 /*                                    */
3309 /*     P U B L I C      G L O B A L   */
3310 /*                                    */
3311 /**************************************/
3312 struct public_global {
3313         u32                             max_path;
3314 #define MAX_PATH_BIG_BEAR       2
3315 #define MAX_PATH_K2             1
3316         u32                             max_ports;
3317 #define MODE_1P 1
3318 #define MODE_2P 2
3319 #define MODE_3P 3
3320 #define MODE_4P 4
3321         u32                             debug_mb_offset;
3322         u32                             phymod_dbg_mb_offset;
3323         struct couple_mode_teaming      cmt;
3324         s32                             internal_temperature;
3325         u32                             mfw_ver;
3326         u32                             running_bundle_id;
3327 };
3328
3329 /**************************************/
3330 /*                                    */
3331 /*     P U B L I C      P A T H       */
3332 /*                                    */
3333 /**************************************/
3334
3335 /****************************************************************************
3336 * Shared Memory 2 Region                                                   *
3337 ****************************************************************************/
3338 /* The fw_flr_ack is actually built in the following way:                   */
3339 /* 8 bit:  PF ack                                                           */
3340 /* 128 bit: VF ack                                                           */
3341 /* 8 bit:  ios_dis_ack                                                      */
3342 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
3343 /* u32. The fw must have the VF right after the PF since this is how it     */
3344 /* access arrays(it expects always the VF to reside after the PF, and that  */
3345 /* makes the calculation much easier for it. )                              */
3346 /* In order to answer both limitations, and keep the struct small, the code */
3347 /* will abuse the structure defined here to achieve the actual partition    */
3348 /* above                                                                    */
3349 /****************************************************************************/
3350 struct fw_flr_mb {
3351         u32     aggint;
3352         u32     opgen_addr;
3353         u32     accum_ack;  /* 0..15:PF, 16..207:VF, 256..271:IOV_DIS */
3354 #define ACCUM_ACK_PF_BASE       0
3355 #define ACCUM_ACK_PF_SHIFT      0
3356
3357 #define ACCUM_ACK_VF_BASE       8
3358 #define ACCUM_ACK_VF_SHIFT      3
3359
3360 #define ACCUM_ACK_IOV_DIS_BASE  256
3361 #define ACCUM_ACK_IOV_DIS_SHIFT 8
3362 };
3363
3364 struct public_path {
3365         struct fw_flr_mb        flr_mb;
3366         u32                     mcp_vf_disabled[VF_MAX_STATIC / 32];
3367
3368         u32                     process_kill;
3369 #define PROCESS_KILL_COUNTER_MASK               0x0000ffff
3370 #define PROCESS_KILL_COUNTER_SHIFT              0
3371 #define PROCESS_KILL_GLOB_AEU_BIT_MASK          0xffff0000
3372 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT         16
3373 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
3374 };
3375
3376 /**************************************/
3377 /*                                    */
3378 /*     P U B L I C      P O R T       */
3379 /*                                    */
3380 /**************************************/
3381
3382 /****************************************************************************
3383 * Driver <-> FW Mailbox                                                    *
3384 ****************************************************************************/
3385
3386 struct public_port {
3387         u32 validity_map;   /* 0x0 (4*2 = 0x8) */
3388
3389         /* validity bits */
3390 #define MCP_VALIDITY_PCI_CFG                    0x00100000
3391 #define MCP_VALIDITY_MB                         0x00200000
3392 #define MCP_VALIDITY_DEV_INFO                   0x00400000
3393 #define MCP_VALIDITY_RESERVED                   0x00000007
3394
3395         /* One licensing bit should be set */
3396 #define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
3397 #define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
3398 #define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
3399 #define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
3400
3401         /* Active MFW */
3402 #define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
3403 #define MCP_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
3404 #define MCP_VALIDITY_ACTIVE_MFW_NCSI            0x00000040
3405 #define MCP_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
3406
3407         u32 link_status;
3408 #define LINK_STATUS_LINK_UP \
3409         0x00000001
3410 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK                       0x0000001e
3411 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            BIT(1)
3412 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (2 << 1)
3413 #define LINK_STATUS_SPEED_AND_DUPLEX_10G                        (3 << 1)
3414 #define LINK_STATUS_SPEED_AND_DUPLEX_20G                        (4 << 1)
3415 #define LINK_STATUS_SPEED_AND_DUPLEX_40G                        (5 << 1)
3416 #define LINK_STATUS_SPEED_AND_DUPLEX_50G                        (6 << 1)
3417 #define LINK_STATUS_SPEED_AND_DUPLEX_100G                       (7 << 1)
3418 #define LINK_STATUS_SPEED_AND_DUPLEX_25G                        (8 << 1)
3419
3420 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED                      0x00000020
3421
3422 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE                     0x00000040
3423 #define LINK_STATUS_PARALLEL_DETECTION_USED                     0x00000080
3424
3425 #define LINK_STATUS_PFC_ENABLED \
3426         0x00000100
3427 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
3428 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
3429 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE            0x00000800
3430 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE            0x00001000
3431 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE            0x00002000
3432 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE            0x00004000
3433 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE           0x00008000
3434 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE            0x00010000
3435
3436 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
3437 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0 << 18)
3438 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        BIT(18)
3439 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2 << 18)
3440 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE                     (3 << 18)
3441
3442 #define LINK_STATUS_SFP_TX_FAULT \
3443         0x00100000
3444 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED                     0x00200000
3445 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED                     0x00400000
3446
3447         u32                     link_status1;
3448         u32                     ext_phy_fw_version;
3449         u32                     drv_phy_cfg_addr;
3450
3451         u32                     port_stx;
3452
3453         u32                     stat_nig_timer;
3454
3455         struct port_mf_cfg      port_mf_config;
3456         struct port_stats       stats;
3457
3458         u32                     media_type;
3459 #define MEDIA_UNSPECIFIED       0x0
3460 #define MEDIA_SFPP_10G_FIBER    0x1
3461 #define MEDIA_XFP_FIBER         0x2
3462 #define MEDIA_DA_TWINAX         0x3
3463 #define MEDIA_BASE_T            0x4
3464 #define MEDIA_SFP_1G_FIBER      0x5
3465 #define MEDIA_KR                0xf0
3466 #define MEDIA_NOT_PRESENT       0xff
3467
3468         u32 lfa_status;
3469 #define LFA_LINK_FLAP_REASON_OFFSET             0
3470 #define LFA_LINK_FLAP_REASON_MASK               0x000000ff
3471 #define LFA_NO_REASON                                   (0 << 0)
3472 #define LFA_LINK_DOWN                                   BIT(0)
3473 #define LFA_FORCE_INIT                                  BIT(1)
3474 #define LFA_LOOPBACK_MISMATCH                           BIT(2)
3475 #define LFA_SPEED_MISMATCH                              BIT(3)
3476 #define LFA_FLOW_CTRL_MISMATCH                          BIT(4)
3477 #define LFA_ADV_SPEED_MISMATCH                          BIT(5)
3478 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET        8
3479 #define LINK_FLAP_AVOIDANCE_COUNT_MASK          0x0000ff00
3480 #define LINK_FLAP_COUNT_OFFSET                  16
3481 #define LINK_FLAP_COUNT_MASK                    0x00ff0000
3482
3483         u32                                     link_change_count;
3484
3485         /* LLDP params */
3486         struct lldp_config_params_s             lldp_config_params[
3487                 LLDP_MAX_LLDP_AGENTS];
3488         struct lldp_status_params_s             lldp_status_params[
3489                 LLDP_MAX_LLDP_AGENTS];
3490         struct lldp_system_tlvs_buffer_s        system_lldp_tlvs_buf;
3491
3492         /* DCBX related MIB */
3493         struct dcbx_local_params                local_admin_dcbx_mib;
3494         struct dcbx_mib                         remote_dcbx_mib;
3495         struct dcbx_mib                         operational_dcbx_mib;
3496 };
3497
3498 /**************************************/
3499 /*                                    */
3500 /*     P U B L I C      F U N C       */
3501 /*                                    */
3502 /**************************************/
3503
3504 struct public_func {
3505         u32     iscsi_boot_signature;
3506         u32     iscsi_boot_block_offset;
3507
3508         u32     reserved[8];
3509
3510         u32     config;
3511
3512         /* E/R/I/D */
3513         /* function 0 of each port cannot be hidden */
3514 #define FUNC_MF_CFG_FUNC_HIDE                   0x00000001
3515 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING          0x00000002
3516 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT    0x00000001
3517
3518 #define FUNC_MF_CFG_PROTOCOL_MASK               0x000000f0
3519 #define FUNC_MF_CFG_PROTOCOL_SHIFT              4
3520 #define FUNC_MF_CFG_PROTOCOL_ETHERNET           0x00000000
3521 #define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000010
3522 #define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000020
3523 #define FUNC_MF_CFG_PROTOCOL_ROCE               0x00000030
3524 #define FUNC_MF_CFG_PROTOCOL_MAX                0x00000030
3525
3526         /* MINBW, MAXBW */
3527         /* value range - 0..100, increments in 1 %  */
3528 #define FUNC_MF_CFG_MIN_BW_MASK                 0x0000ff00
3529 #define FUNC_MF_CFG_MIN_BW_SHIFT                8
3530 #define FUNC_MF_CFG_MIN_BW_DEFAULT              0x00000000
3531 #define FUNC_MF_CFG_MAX_BW_MASK                 0x00ff0000
3532 #define FUNC_MF_CFG_MAX_BW_SHIFT                16
3533 #define FUNC_MF_CFG_MAX_BW_DEFAULT              0x00640000
3534
3535         u32     status;
3536 #define FUNC_STATUS_VLINK_DOWN                  0x00000001
3537
3538         u32     mac_upper;  /* MAC */
3539 #define FUNC_MF_CFG_UPPERMAC_MASK               0x0000ffff
3540 #define FUNC_MF_CFG_UPPERMAC_SHIFT              0
3541 #define FUNC_MF_CFG_UPPERMAC_DEFAULT            FUNC_MF_CFG_UPPERMAC_MASK
3542         u32     mac_lower;
3543 #define FUNC_MF_CFG_LOWERMAC_DEFAULT            0xffffffff
3544
3545         u32     fcoe_wwn_port_name_upper;
3546         u32     fcoe_wwn_port_name_lower;
3547
3548         u32     fcoe_wwn_node_name_upper;
3549         u32     fcoe_wwn_node_name_lower;
3550
3551         u32     ovlan_stag; /* tags */
3552 #define FUNC_MF_CFG_OV_STAG_MASK              0x0000ffff
3553 #define FUNC_MF_CFG_OV_STAG_SHIFT             0
3554 #define FUNC_MF_CFG_OV_STAG_DEFAULT           FUNC_MF_CFG_OV_STAG_MASK
3555
3556         u32     pf_allocation;  /* vf per pf */
3557
3558         u32     preserve_data;  /* Will be used bt CCM */
3559
3560         u32     driver_last_activity_ts;
3561
3562         u32     drv_ack_vf_disabled[VF_MAX_STATIC / 32]; /* 0x0044 */
3563
3564         u32     drv_id;
3565 #define DRV_ID_PDA_COMP_VER_MASK        0x0000ffff
3566 #define DRV_ID_PDA_COMP_VER_SHIFT       0
3567
3568 #define DRV_ID_MCP_HSI_VER_MASK         0x00ff0000
3569 #define DRV_ID_MCP_HSI_VER_SHIFT        16
3570 #define DRV_ID_MCP_HSI_VER_CURRENT      BIT(DRV_ID_MCP_HSI_VER_SHIFT)
3571
3572 #define DRV_ID_DRV_TYPE_MASK            0xff000000
3573 #define DRV_ID_DRV_TYPE_SHIFT           24
3574 #define DRV_ID_DRV_TYPE_UNKNOWN         (0 << DRV_ID_DRV_TYPE_SHIFT)
3575 #define DRV_ID_DRV_TYPE_LINUX           BIT(DRV_ID_DRV_TYPE_SHIFT)
3576 #define DRV_ID_DRV_TYPE_WINDOWS         (2 << DRV_ID_DRV_TYPE_SHIFT)
3577 #define DRV_ID_DRV_TYPE_DIAG            (3 << DRV_ID_DRV_TYPE_SHIFT)
3578 #define DRV_ID_DRV_TYPE_PREBOOT         (4 << DRV_ID_DRV_TYPE_SHIFT)
3579 #define DRV_ID_DRV_TYPE_SOLARIS         (5 << DRV_ID_DRV_TYPE_SHIFT)
3580 #define DRV_ID_DRV_TYPE_VMWARE          (6 << DRV_ID_DRV_TYPE_SHIFT)
3581 #define DRV_ID_DRV_TYPE_FREEBSD         (7 << DRV_ID_DRV_TYPE_SHIFT)
3582 #define DRV_ID_DRV_TYPE_AIX             (8 << DRV_ID_DRV_TYPE_SHIFT)
3583 };
3584
3585 /**************************************/
3586 /*                                    */
3587 /*     P U B L I C       M B          */
3588 /*                                    */
3589 /**************************************/
3590 /* This is the only section that the driver can write to, and each */
3591 /* Basically each driver request to set feature parameters,
3592  * will be done using a different command, which will be linked
3593  * to a specific data structure from the union below.
3594  * For huge strucuture, the common blank structure should be used.
3595  */
3596
3597 struct mcp_mac {
3598         u32     mac_upper;  /* Upper 16 bits are always zeroes */
3599         u32     mac_lower;
3600 };
3601
3602 struct mcp_val64 {
3603         u32     lo;
3604         u32     hi;
3605 };
3606
3607 struct mcp_file_att {
3608         u32     nvm_start_addr;
3609         u32     len;
3610 };
3611
3612 #define MCP_DRV_VER_STR_SIZE 16
3613 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
3614 #define MCP_DRV_NVM_BUF_LEN 32
3615 struct drv_version_stc {
3616         u32     version;
3617         u8      name[MCP_DRV_VER_STR_SIZE - 4];
3618 };
3619
3620 union drv_union_data {
3621         u32                     ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
3622         struct mcp_mac          wol_mac;
3623
3624         struct pmm_phy_cfg      drv_phy_cfg;
3625
3626         struct mcp_val64        val64; /* For PHY / AVS commands */
3627
3628         u8                      raw_data[MCP_DRV_NVM_BUF_LEN];
3629
3630         struct mcp_file_att     file_att;
3631
3632         u32                     ack_vf_disabled[VF_MAX_STATIC / 32];
3633
3634         struct drv_version_stc  drv_version;
3635 };
3636
3637 struct public_drv_mb {
3638         u32 drv_mb_header;
3639 #define DRV_MSG_CODE_MASK                       0xffff0000
3640 #define DRV_MSG_CODE_LOAD_REQ                   0x10000000
3641 #define DRV_MSG_CODE_LOAD_DONE                  0x11000000
3642 #define DRV_MSG_CODE_UNLOAD_REQ                 0x20000000
3643 #define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
3644 #define DRV_MSG_CODE_INIT_PHY                   0x22000000
3645         /* Params - FORCE - Reinitialize the link regardless of LFA */
3646         /*        - DONT_CARE - Don't flap the link if up */
3647 #define DRV_MSG_CODE_LINK_RESET                 0x23000000
3648
3649 #define DRV_MSG_CODE_SET_LLDP                   0x24000000
3650 #define DRV_MSG_CODE_SET_DCBX                   0x25000000
3651
3652 #define DRV_MSG_CODE_NIG_DRAIN                  0x30000000
3653
3654 #define DRV_MSG_CODE_INITIATE_FLR               0x02000000
3655 #define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000
3656 #define DRV_MSG_CODE_CFG_VF_MSIX                0xc0010000
3657 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN         0x00010000
3658 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA          0x00020000
3659 #define DRV_MSG_CODE_NVM_GET_FILE_ATT           0x00030000
3660 #define DRV_MSG_CODE_NVM_READ_NVRAM             0x00050000
3661 #define DRV_MSG_CODE_NVM_WRITE_NVRAM            0x00060000
3662 #define DRV_MSG_CODE_NVM_DEL_FILE               0x00080000
3663 #define DRV_MSG_CODE_MCP_RESET                  0x00090000
3664 #define DRV_MSG_CODE_SET_SECURE_MODE            0x000a0000
3665 #define DRV_MSG_CODE_PHY_RAW_READ               0x000b0000
3666 #define DRV_MSG_CODE_PHY_RAW_WRITE              0x000c0000
3667 #define DRV_MSG_CODE_PHY_CORE_READ              0x000d0000
3668 #define DRV_MSG_CODE_PHY_CORE_WRITE             0x000e0000
3669 #define DRV_MSG_CODE_SET_VERSION                0x000f0000
3670
3671 #define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
3672
3673         u32 drv_mb_param;
3674
3675         /* UNLOAD_REQ params */
3676 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN         0x00000000
3677 #define DRV_MB_PARAM_UNLOAD_WOL_MCP             0x00000001
3678 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED        0x00000002
3679 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED         0x00000003
3680
3681         /* UNLOAD_DONE_params */
3682 #define DRV_MB_PARAM_UNLOAD_NON_D3_POWER        0x00000001
3683
3684         /* INIT_PHY params */
3685 #define DRV_MB_PARAM_INIT_PHY_FORCE             0x00000001
3686 #define DRV_MB_PARAM_INIT_PHY_DONT_CARE         0x00000002
3687
3688         /* LLDP / DCBX params*/
3689 #define DRV_MB_PARAM_LLDP_SEND_MASK             0x00000001
3690 #define DRV_MB_PARAM_LLDP_SEND_SHIFT            0
3691 #define DRV_MB_PARAM_LLDP_AGENT_MASK            0x00000006
3692 #define DRV_MB_PARAM_LLDP_AGENT_SHIFT           1
3693 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK           0x00000008
3694 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT          3
3695
3696 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK   0x000000FF
3697 #define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT  0
3698
3699 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW     0x1
3700 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE   0x2
3701
3702 #define DRV_MB_PARAM_NVM_OFFSET_SHIFT           0
3703 #define DRV_MB_PARAM_NVM_OFFSET_MASK            0x00FFFFFF
3704 #define DRV_MB_PARAM_NVM_LEN_SHIFT              24
3705 #define DRV_MB_PARAM_NVM_LEN_MASK               0xFF000000
3706
3707 #define DRV_MB_PARAM_PHY_ADDR_SHIFT             0
3708 #define DRV_MB_PARAM_PHY_ADDR_MASK              0x1FF0FFFF
3709 #define DRV_MB_PARAM_PHY_LANE_SHIFT             16
3710 #define DRV_MB_PARAM_PHY_LANE_MASK              0x000F0000
3711 #define DRV_MB_PARAM_PHY_SELECT_PORT_SHIFT      29
3712 #define DRV_MB_PARAM_PHY_SELECT_PORT_MASK       0x20000000
3713 #define DRV_MB_PARAM_PHY_PORT_SHIFT             30
3714 #define DRV_MB_PARAM_PHY_PORT_MASK              0xc0000000
3715
3716 /* configure vf MSIX params*/
3717 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT    0
3718 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK     0x000000FF
3719 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT   8
3720 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK    0x0000FF00
3721
3722         u32 fw_mb_header;
3723 #define FW_MSG_CODE_MASK                        0xffff0000
3724 #define FW_MSG_CODE_DRV_LOAD_ENGINE             0x10100000
3725 #define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
3726 #define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x10120000
3727 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA        0x10200000
3728 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI        0x10210000
3729 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG       0x10220000
3730 #define FW_MSG_CODE_DRV_LOAD_DONE               0x11100000
3731 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE           0x20110000
3732 #define FW_MSG_CODE_DRV_UNLOAD_PORT             0x20120000
3733 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x20130000
3734 #define FW_MSG_CODE_DRV_UNLOAD_DONE             0x21100000
3735 #define FW_MSG_CODE_INIT_PHY_DONE               0x21200000
3736 #define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS   0x21300000
3737 #define FW_MSG_CODE_LINK_RESET_DONE             0x23000000
3738 #define FW_MSG_CODE_SET_LLDP_DONE               0x24000000
3739 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT  0x24010000
3740 #define FW_MSG_CODE_SET_DCBX_DONE               0x25000000
3741 #define FW_MSG_CODE_NIG_DRAIN_DONE              0x30000000
3742 #define FW_MSG_CODE_VF_DISABLED_DONE            0xb0000000
3743 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE        0xb0010000
3744 #define FW_MSG_CODE_FLR_ACK                     0x02000000
3745 #define FW_MSG_CODE_FLR_NACK                    0x02100000
3746
3747 #define FW_MSG_CODE_NVM_OK                      0x00010000
3748 #define FW_MSG_CODE_NVM_INVALID_MODE            0x00020000
3749 #define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED       0x00030000
3750 #define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000
3751 #define FW_MSG_CODE_NVM_INVALID_DIR_FOUND       0x00050000
3752 #define FW_MSG_CODE_NVM_PAGE_NOT_FOUND          0x00060000
3753 #define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000
3754 #define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000
3755 #define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC     0x00090000
3756 #define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR     0x000a0000
3757 #define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE     0x000b0000
3758 #define FW_MSG_CODE_NVM_FILE_NOT_FOUND          0x000c0000
3759 #define FW_MSG_CODE_NVM_OPERATION_FAILED        0x000d0000
3760 #define FW_MSG_CODE_NVM_FAILED_UNALIGNED        0x000e0000
3761 #define FW_MSG_CODE_NVM_BAD_OFFSET              0x000f0000
3762 #define FW_MSG_CODE_NVM_BAD_SIGNATURE           0x00100000
3763 #define FW_MSG_CODE_NVM_FILE_READ_ONLY          0x00200000
3764 #define FW_MSG_CODE_NVM_UNKNOWN_FILE            0x00300000
3765 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK      0x00400000
3766 #define FW_MSG_CODE_MCP_RESET_REJECT            0x00600000
3767 #define FW_MSG_CODE_PHY_OK                      0x00110000
3768 #define FW_MSG_CODE_PHY_ERROR                   0x00120000
3769 #define FW_MSG_CODE_SET_SECURE_MODE_ERROR       0x00130000
3770 #define FW_MSG_CODE_SET_SECURE_MODE_OK          0x00140000
3771 #define FW_MSG_MODE_PHY_PRIVILEGE_ERROR         0x00150000
3772
3773 #define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
3774
3775         u32     fw_mb_param;
3776
3777         u32     drv_pulse_mb;
3778 #define DRV_PULSE_SEQ_MASK                      0x00007fff
3779 #define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
3780 #define DRV_PULSE_ALWAYS_ALIVE                  0x00008000
3781         u32 mcp_pulse_mb;
3782 #define MCP_PULSE_SEQ_MASK                      0x00007fff
3783 #define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
3784 #define MCP_EVENT_MASK                          0xffff0000
3785 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000
3786
3787         union drv_union_data union_data;
3788 };
3789
3790 /* MFW - DRV MB */
3791 /**********************************************************************
3792 * Description
3793 *   Incremental Aggregative
3794 *   8-bit MFW counter per message
3795 *   8-bit ack-counter per message
3796 * Capabilities
3797 *   Provides up to 256 aggregative message per type
3798 *   Provides 4 message types in dword
3799 *   Message type pointers to byte offset
3800 *   Backward Compatibility by using sizeof for the counters.
3801 *   No lock requires for 32bit messages
3802 * Limitations:
3803 * In case of messages greater than 32bit, a dedicated mechanism(e.g lock)
3804 * is required to prevent data corruption.
3805 **********************************************************************/
3806 enum MFW_DRV_MSG_TYPE {
3807         MFW_DRV_MSG_LINK_CHANGE,
3808         MFW_DRV_MSG_FLR_FW_ACK_FAILED,
3809         MFW_DRV_MSG_VF_DISABLED,
3810         MFW_DRV_MSG_LLDP_DATA_UPDATED,
3811         MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
3812         MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
3813         MFW_DRV_MSG_ERROR_RECOVERY,
3814         MFW_DRV_MSG_MAX
3815 };
3816
3817 #define MFW_DRV_MSG_MAX_DWORDS(msgs)    (((msgs - 1) >> 2) + 1)
3818 #define MFW_DRV_MSG_DWORD(msg_id)       (msg_id >> 2)
3819 #define MFW_DRV_MSG_OFFSET(msg_id)      ((msg_id & 0x3) << 3)
3820 #define MFW_DRV_MSG_MASK(msg_id)        (0xff << MFW_DRV_MSG_OFFSET(msg_id))
3821
3822 struct public_mfw_mb {
3823         u32     sup_msgs;
3824         u32     msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
3825         u32     ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
3826 };
3827
3828 /**************************************/
3829 /*                                    */
3830 /*     P U B L I C       D A T A      */
3831 /*                                    */
3832 /**************************************/
3833 enum public_sections {
3834         PUBLIC_DRV_MB,          /* Points to the first drv_mb of path0 */
3835         PUBLIC_MFW_MB,          /* Points to the first mfw_mb of path0 */
3836         PUBLIC_GLOBAL,
3837         PUBLIC_PATH,
3838         PUBLIC_PORT,
3839         PUBLIC_FUNC,
3840         PUBLIC_MAX_SECTIONS
3841 };
3842
3843 struct drv_ver_info_stc {
3844         u32     ver;
3845         u8      name[32];
3846 };
3847
3848 struct mcp_public_data {
3849         /* The sections fields is an array */
3850         u32                     num_sections;
3851         offsize_t               sections[PUBLIC_MAX_SECTIONS];
3852         struct public_drv_mb    drv_mb[MCP_GLOB_FUNC_MAX];
3853         struct public_mfw_mb    mfw_mb[MCP_GLOB_FUNC_MAX];
3854         struct public_global    global;
3855         struct public_path      path[MCP_GLOB_PATH_MAX];
3856         struct public_port      port[MCP_GLOB_PORT_MAX];
3857         struct public_func      func[MCP_GLOB_FUNC_MAX];
3858         struct drv_ver_info_stc drv_info;
3859 };
3860
3861 struct nvm_cfg_mac_address {
3862         u32     mac_addr_hi;
3863 #define NVM_CFG_MAC_ADDRESS_HI_MASK                             0x0000FFFF
3864 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET                           0
3865
3866         u32     mac_addr_lo;
3867 };
3868
3869 /******************************************
3870 * nvm_cfg1 structs
3871 ******************************************/
3872
3873 struct nvm_cfg1_glob {
3874         u32 generic_cont0;                                      /* 0x0 */
3875 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK                           0x0000000F
3876 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET                         0
3877 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE                           0x0
3878 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH                           0x1
3879 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT                           0x2
3880 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH                           0x3
3881 #define NVM_CFG1_GLOB_MF_MODE_MASK                              0x00000FF0
3882 #define NVM_CFG1_GLOB_MF_MODE_OFFSET                            4
3883 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED                        0x0
3884 #define NVM_CFG1_GLOB_MF_MODE_FORCED_SF                         0x1
3885 #define NVM_CFG1_GLOB_MF_MODE_SPIO4                             0x2
3886 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0                           0x3
3887 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5                           0x4
3888 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0                           0x5
3889 #define NVM_CFG1_GLOB_MF_MODE_BD                                0x6
3890 #define NVM_CFG1_GLOB_MF_MODE_UFP                               0x7
3891 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK              0x00001000
3892 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET            12
3893 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED          0x0
3894 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED           0x1
3895 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK                       0x001FE000
3896 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET                     13
3897 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK                      0x1FE00000
3898 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET                    21
3899 #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK                         0x20000000
3900 #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET                       29
3901 #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED                     0x0
3902 #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED                      0x1
3903 #define NVM_CFG1_GLOB_ENABLE_ATC_MASK                           0x40000000
3904 #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET                         30
3905 #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED                       0x0
3906 #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED                        0x1
3907 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_MASK                       0x80000000
3908 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_OFFSET                     31
3909 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_DISABLED                   0x0
3910 #define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_ENABLED                    0x1
3911
3912         u32     engineering_change[3];                          /* 0x4 */
3913
3914         u32     manufacturing_id;                               /* 0x10 */
3915
3916         u32     serial_number[4];                               /* 0x14 */
3917
3918         u32     pcie_cfg;                                       /* 0x24 */
3919 #define NVM_CFG1_GLOB_PCI_GEN_MASK                              0x00000003
3920 #define NVM_CFG1_GLOB_PCI_GEN_OFFSET                            0
3921 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1                          0x0
3922 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2                          0x1
3923 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3                          0x2
3924 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK                   0x00000004
3925 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET                 2
3926 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED               0x0
3927 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED                0x1
3928 #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK                         0x00000018
3929 #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET                       3
3930 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED               0x0
3931 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED                 0x1
3932 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED                  0x2
3933 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED              0x3
3934 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_MASK               0x00000020
3935 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_OFFSET             5
3936 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_DISABLED           0x0
3937 #define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_ENABLED            0x1
3938 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK                 0x000003C0
3939 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET               6
3940 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK                     0x00001C00
3941 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET                   10
3942 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW                       0x0
3943 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB                      0x1
3944 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB                    0x2
3945 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB                    0x3
3946 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK                     0x001FE000
3947 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET                   13
3948 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK                     0x1FE00000
3949 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET                   21
3950 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK                      0x60000000
3951 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET                    29
3952
3953         u32 mgmt_traffic;                                       /* 0x28 */
3954 #define NVM_CFG1_GLOB_RESERVED60_MASK                           0x00000001
3955 #define NVM_CFG1_GLOB_RESERVED60_OFFSET                         0
3956 #define NVM_CFG1_GLOB_RESERVED60_100KHZ                         0x0
3957 #define NVM_CFG1_GLOB_RESERVED60_400KHZ                         0x1
3958 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK                     0x000001FE
3959 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET                   1
3960 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK                     0x0001FE00
3961 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET                   9
3962 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK                        0x01FE0000
3963 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET                      17
3964 #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK                        0x06000000
3965 #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET                      25
3966 #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED                    0x0
3967 #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII                        0x1
3968 #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII                       0x2
3969
3970         u32 core_cfg;                                           /* 0x2C */
3971 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK                    0x000000FF
3972 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET                  0
3973 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G                0x0
3974 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G                0x1
3975 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G               0x2
3976 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F              0x3
3977 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E              0x4
3978 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G                0x5
3979 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G                0xB
3980 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G                0xC
3981 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G                0xD
3982 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_MASK             0x00000100
3983 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_OFFSET           8
3984 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_DISABLED         0x0
3985 #define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_ENABLED          0x1
3986 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_MASK            0x00000200
3987 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_OFFSET          9
3988 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_DISABLED        0x0
3989 #define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_ENABLED         0x1
3990 #define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_MASK                      0x0003FC00
3991 #define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_OFFSET                    10
3992 #define NVM_CFG1_GLOB_FALCON_CORE_ADDR_MASK                     0x03FC0000
3993 #define NVM_CFG1_GLOB_FALCON_CORE_ADDR_OFFSET                   18
3994 #define NVM_CFG1_GLOB_AVS_MODE_MASK                             0x1C000000
3995 #define NVM_CFG1_GLOB_AVS_MODE_OFFSET                           26
3996 #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP                       0x0
3997 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP                        0x1
3998 #define NVM_CFG1_GLOB_AVS_MODE_DISABLED                         0x3
3999 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK                 0x60000000
4000 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET               29
4001 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED             0x0
4002 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED              0x1
4003
4004         u32 e_lane_cfg1;                                        /* 0x30 */
4005 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK                        0x0000000F
4006 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET                      0
4007 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK                        0x000000F0
4008 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET                      4
4009 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK                        0x00000F00
4010 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET                      8
4011 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK                        0x0000F000
4012 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET                      12
4013 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK                        0x000F0000
4014 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET                      16
4015 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK                        0x00F00000
4016 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET                      20
4017 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK                        0x0F000000
4018 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET                      24
4019 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK                        0xF0000000
4020 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET                      28
4021
4022         u32 e_lane_cfg2;                                        /* 0x34 */
4023 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK                    0x00000001
4024 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET                  0
4025 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK                    0x00000002
4026 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET                  1
4027 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK                    0x00000004
4028 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET                  2
4029 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK                    0x00000008
4030 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET                  3
4031 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK                    0x00000010
4032 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET                  4
4033 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK                    0x00000020
4034 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET                  5
4035 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK                    0x00000040
4036 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET                  6
4037 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK                    0x00000080
4038 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET                  7
4039 #define NVM_CFG1_GLOB_SMBUS_MODE_MASK                           0x00000F00
4040 #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET                         8
4041 #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED                       0x0
4042 #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ                         0x1
4043 #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ                         0x2
4044 #define NVM_CFG1_GLOB_NCSI_MASK                                 0x0000F000
4045 #define NVM_CFG1_GLOB_NCSI_OFFSET                               12
4046 #define NVM_CFG1_GLOB_NCSI_DISABLED                             0x0
4047 #define NVM_CFG1_GLOB_NCSI_ENABLED                              0x1
4048
4049         u32 f_lane_cfg1;                                        /* 0x38 */
4050 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK                        0x0000000F
4051 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET                      0
4052 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK                        0x000000F0
4053 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET                      4
4054 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK                        0x00000F00
4055 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET                      8
4056 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK                        0x0000F000
4057 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET                      12
4058 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK                        0x000F0000
4059 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET                      16
4060 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK                        0x00F00000
4061 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET                      20
4062 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK                        0x0F000000
4063 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET                      24
4064 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK                        0xF0000000
4065 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET                      28
4066
4067         u32 f_lane_cfg2;                                        /* 0x3C */
4068 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK                    0x00000001
4069 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET                  0
4070 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK                    0x00000002
4071 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET                  1
4072 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK                    0x00000004
4073 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET                  2
4074 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK                    0x00000008
4075 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET                  3
4076 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK                    0x00000010
4077 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET                  4
4078 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK                    0x00000020
4079 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET                  5
4080 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK                    0x00000040
4081 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET                  6
4082 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK                    0x00000080
4083 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET                  7
4084
4085         u32 eagle_preemphasis;                                  /* 0x40 */
4086 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK                         0x000000FF
4087 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET                       0
4088 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK                         0x0000FF00
4089 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET                       8
4090 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK                         0x00FF0000
4091 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET                       16
4092 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK                         0xFF000000
4093 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET                       24
4094
4095         u32 eagle_driver_current;                               /* 0x44 */
4096 #define NVM_CFG1_GLOB_LANE0_AMP_MASK                            0x000000FF
4097 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET                          0
4098 #define NVM_CFG1_GLOB_LANE1_AMP_MASK                            0x0000FF00
4099 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET                          8
4100 #define NVM_CFG1_GLOB_LANE2_AMP_MASK                            0x00FF0000
4101 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET                          16
4102 #define NVM_CFG1_GLOB_LANE3_AMP_MASK                            0xFF000000
4103 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET                          24
4104
4105         u32 falcon_preemphasis;                                 /* 0x48 */
4106 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK                         0x000000FF
4107 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET                       0
4108 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK                         0x0000FF00
4109 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET                       8
4110 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK                         0x00FF0000
4111 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET                       16
4112 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK                         0xFF000000
4113 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET                       24
4114
4115         u32 falcon_driver_current;                              /* 0x4C */
4116 #define NVM_CFG1_GLOB_LANE0_AMP_MASK                            0x000000FF
4117 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET                          0
4118 #define NVM_CFG1_GLOB_LANE1_AMP_MASK                            0x0000FF00
4119 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET                          8
4120 #define NVM_CFG1_GLOB_LANE2_AMP_MASK                            0x00FF0000
4121 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET                          16
4122 #define NVM_CFG1_GLOB_LANE3_AMP_MASK                            0xFF000000
4123 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET                          24
4124
4125         u32     pci_id;                                         /* 0x50 */
4126 #define NVM_CFG1_GLOB_VENDOR_ID_MASK                            0x0000FFFF
4127 #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET                          0
4128
4129         u32     pci_subsys_id;                                  /* 0x54 */
4130 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK                  0x0000FFFF
4131 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET                0
4132 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK                  0xFFFF0000
4133 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET                16
4134
4135         u32     bar;                                            /* 0x58 */
4136 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK                   0x0000000F
4137 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET                 0
4138 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED               0x0
4139 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K                     0x1
4140 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K                     0x2
4141 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K                     0x3
4142 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K                    0x4
4143 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K                    0x5
4144 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K                    0x6
4145 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K                   0x7
4146 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K                   0x8
4147 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K                   0x9
4148 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M                     0xA
4149 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M                     0xB
4150 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M                     0xC
4151 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M                     0xD
4152 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M                    0xE
4153 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M                    0xF
4154 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK                     0x000000F0
4155 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET                   4
4156 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED                 0x0
4157 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K                       0x1
4158 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K                       0x2
4159 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K                      0x3
4160 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K                      0x4
4161 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K                      0x5
4162 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K                     0x6
4163 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K                     0x7
4164 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K                     0x8
4165 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M                       0x9
4166 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M                       0xA
4167 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M                       0xB
4168 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M                       0xC
4169 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M                      0xD
4170 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M                      0xE
4171 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M                      0xF
4172 #define NVM_CFG1_GLOB_BAR2_SIZE_MASK                            0x00000F00
4173 #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET                          8
4174 #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED                        0x0
4175 #define NVM_CFG1_GLOB_BAR2_SIZE_64K                             0x1
4176 #define NVM_CFG1_GLOB_BAR2_SIZE_128K                            0x2
4177 #define NVM_CFG1_GLOB_BAR2_SIZE_256K                            0x3
4178 #define NVM_CFG1_GLOB_BAR2_SIZE_512K                            0x4
4179 #define NVM_CFG1_GLOB_BAR2_SIZE_1M                              0x5
4180 #define NVM_CFG1_GLOB_BAR2_SIZE_2M                              0x6
4181 #define NVM_CFG1_GLOB_BAR2_SIZE_4M                              0x7
4182 #define NVM_CFG1_GLOB_BAR2_SIZE_8M                              0x8
4183 #define NVM_CFG1_GLOB_BAR2_SIZE_16M                             0x9
4184 #define NVM_CFG1_GLOB_BAR2_SIZE_32M                             0xA
4185 #define NVM_CFG1_GLOB_BAR2_SIZE_64M                             0xB
4186 #define NVM_CFG1_GLOB_BAR2_SIZE_128M                            0xC
4187 #define NVM_CFG1_GLOB_BAR2_SIZE_256M                            0xD
4188 #define NVM_CFG1_GLOB_BAR2_SIZE_512M                            0xE
4189 #define NVM_CFG1_GLOB_BAR2_SIZE_1G                              0xF
4190
4191         u32 eagle_txfir_main;                                   /* 0x5C */
4192 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK                     0x000000FF
4193 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET                   0
4194 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK                     0x0000FF00
4195 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET                   8
4196 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK                     0x00FF0000
4197 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET                   16
4198 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK                     0xFF000000
4199 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET                   24
4200
4201         u32 eagle_txfir_post;                                   /* 0x60 */
4202 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK                     0x000000FF
4203 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET                   0
4204 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK                     0x0000FF00
4205 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET                   8
4206 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK                     0x00FF0000
4207 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET                   16
4208 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK                     0xFF000000
4209 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET                   24
4210
4211         u32 falcon_txfir_main;                                  /* 0x64 */
4212 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK                     0x000000FF
4213 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET                   0
4214 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK                     0x0000FF00
4215 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET                   8
4216 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK                     0x00FF0000
4217 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET                   16
4218 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK                     0xFF000000
4219 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET                   24
4220
4221         u32 falcon_txfir_post;                                  /* 0x68 */
4222 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK                     0x000000FF
4223 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET                   0
4224 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK                     0x0000FF00
4225 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET                   8
4226 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK                     0x00FF0000
4227 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET                   16
4228 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK                     0xFF000000
4229 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET                   24
4230
4231         u32 manufacture_ver;                                    /* 0x6C */
4232 #define NVM_CFG1_GLOB_MANUF0_VER_MASK                           0x0000003F
4233 #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET                         0
4234 #define NVM_CFG1_GLOB_MANUF1_VER_MASK                           0x00000FC0
4235 #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET                         6
4236 #define NVM_CFG1_GLOB_MANUF2_VER_MASK                           0x0003F000
4237 #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET                         12
4238 #define NVM_CFG1_GLOB_MANUF3_VER_MASK                           0x00FC0000
4239 #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET                         18
4240 #define NVM_CFG1_GLOB_MANUF4_VER_MASK                           0x3F000000
4241 #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET                         24
4242
4243         u32 manufacture_time;                                   /* 0x70 */
4244 #define NVM_CFG1_GLOB_MANUF0_TIME_MASK                          0x0000003F
4245 #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET                        0
4246 #define NVM_CFG1_GLOB_MANUF1_TIME_MASK                          0x00000FC0
4247 #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET                        6
4248 #define NVM_CFG1_GLOB_MANUF2_TIME_MASK                          0x0003F000
4249 #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET                        12
4250
4251         u32 led_global_settings;                                /* 0x74 */
4252 #define NVM_CFG1_GLOB_LED_SWAP_0_MASK                           0x0000000F
4253 #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET                         0
4254 #define NVM_CFG1_GLOB_LED_SWAP_1_MASK                           0x000000F0
4255 #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET                         4
4256 #define NVM_CFG1_GLOB_LED_SWAP_2_MASK                           0x00000F00
4257 #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET                         8
4258 #define NVM_CFG1_GLOB_LED_SWAP_3_MASK                           0x0000F000
4259 #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET                         12
4260
4261         u32     generic_cont1;                                  /* 0x78 */
4262 #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK                         0x000003FF
4263 #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET                       0
4264
4265         u32     mbi_version;                                    /* 0x7C */
4266 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK                        0x000000FF
4267 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET                      0
4268 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK                        0x0000FF00
4269 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET                      8
4270 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK                        0x00FF0000
4271 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET                      16
4272
4273         u32     mbi_date;                                       /* 0x80 */
4274
4275         u32     misc_sig;                                       /* 0x84 */
4276
4277         /*  Define the GPIO mapping to switch i2c mux */
4278 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK                   0x000000FF
4279 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET                 0
4280 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK                   0x0000FF00
4281 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET                 8
4282 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA                      0x0
4283 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0                   0x1
4284 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1                   0x2
4285 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2                   0x3
4286 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3                   0x4
4287 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4                   0x5
4288 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5                   0x6
4289 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6                   0x7
4290 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7                   0x8
4291 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8                   0x9
4292 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9                   0xA
4293 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10                  0xB
4294 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11                  0xC
4295 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12                  0xD
4296 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13                  0xE
4297 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14                  0xF
4298 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15                  0x10
4299 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16                  0x11
4300 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17                  0x12
4301 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18                  0x13
4302 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19                  0x14
4303 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20                  0x15
4304 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21                  0x16
4305 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22                  0x17
4306 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23                  0x18
4307 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24                  0x19
4308 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25                  0x1A
4309 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26                  0x1B
4310 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27                  0x1C
4311 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28                  0x1D
4312 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29                  0x1E
4313 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30                  0x1F
4314 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31                  0x20
4315
4316         u32 reserved[46];                                       /* 0x88 */
4317 };
4318
4319 struct nvm_cfg1_path {
4320         u32 reserved[30];                                       /* 0x0 */
4321 };
4322
4323 struct nvm_cfg1_port {
4324         u32 power_dissipated;                                   /* 0x0 */
4325 #define NVM_CFG1_PORT_POWER_DIS_D0_MASK                         0x000000FF
4326 #define NVM_CFG1_PORT_POWER_DIS_D0_OFFSET                       0
4327 #define NVM_CFG1_PORT_POWER_DIS_D1_MASK                         0x0000FF00
4328 #define NVM_CFG1_PORT_POWER_DIS_D1_OFFSET                       8
4329 #define NVM_CFG1_PORT_POWER_DIS_D2_MASK                         0x00FF0000
4330 #define NVM_CFG1_PORT_POWER_DIS_D2_OFFSET                       16
4331 #define NVM_CFG1_PORT_POWER_DIS_D3_MASK                         0xFF000000
4332 #define NVM_CFG1_PORT_POWER_DIS_D3_OFFSET                       24
4333
4334         u32 power_consumed;                                     /* 0x4 */
4335 #define NVM_CFG1_PORT_POWER_CONS_D0_MASK                        0x000000FF
4336 #define NVM_CFG1_PORT_POWER_CONS_D0_OFFSET                      0
4337 #define NVM_CFG1_PORT_POWER_CONS_D1_MASK                        0x0000FF00
4338 #define NVM_CFG1_PORT_POWER_CONS_D1_OFFSET                      8
4339 #define NVM_CFG1_PORT_POWER_CONS_D2_MASK                        0x00FF0000
4340 #define NVM_CFG1_PORT_POWER_CONS_D2_OFFSET                      16
4341 #define NVM_CFG1_PORT_POWER_CONS_D3_MASK                        0xFF000000
4342 #define NVM_CFG1_PORT_POWER_CONS_D3_OFFSET                      24
4343
4344         u32 generic_cont0;                                      /* 0x8 */
4345 #define NVM_CFG1_PORT_LED_MODE_MASK                             0x000000FF
4346 #define NVM_CFG1_PORT_LED_MODE_OFFSET                           0
4347 #define NVM_CFG1_PORT_LED_MODE_MAC1                             0x0
4348 #define NVM_CFG1_PORT_LED_MODE_PHY1                             0x1
4349 #define NVM_CFG1_PORT_LED_MODE_PHY2                             0x2
4350 #define NVM_CFG1_PORT_LED_MODE_PHY3                             0x3
4351 #define NVM_CFG1_PORT_LED_MODE_MAC2                             0x4
4352 #define NVM_CFG1_PORT_LED_MODE_PHY4                             0x5
4353 #define NVM_CFG1_PORT_LED_MODE_PHY5                             0x6
4354 #define NVM_CFG1_PORT_LED_MODE_PHY6                             0x7
4355 #define NVM_CFG1_PORT_LED_MODE_MAC3                             0x8
4356 #define NVM_CFG1_PORT_LED_MODE_PHY7                             0x9
4357 #define NVM_CFG1_PORT_LED_MODE_PHY8                             0xA
4358 #define NVM_CFG1_PORT_LED_MODE_PHY9                             0xB
4359 #define NVM_CFG1_PORT_LED_MODE_MAC4                             0xC
4360 #define NVM_CFG1_PORT_LED_MODE_PHY10                            0xD
4361 #define NVM_CFG1_PORT_LED_MODE_PHY11                            0xE
4362 #define NVM_CFG1_PORT_LED_MODE_PHY12                            0xF
4363 #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK                        0x0000FF00
4364 #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET                      8
4365 #define NVM_CFG1_PORT_DCBX_MODE_MASK                            0x000F0000
4366 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET                          16
4367 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED                        0x0
4368 #define NVM_CFG1_PORT_DCBX_MODE_IEEE                            0x1
4369 #define NVM_CFG1_PORT_DCBX_MODE_CEE                             0x2
4370 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC                         0x3
4371
4372         u32     pcie_cfg;                                       /* 0xC */
4373 #define NVM_CFG1_PORT_RESERVED15_MASK                           0x00000007
4374 #define NVM_CFG1_PORT_RESERVED15_OFFSET                         0
4375
4376         u32     features;                                       /* 0x10 */
4377 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK           0x00000001
4378 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET         0
4379 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED       0x0
4380 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED        0x1
4381 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK                     0x00000002
4382 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET                   1
4383 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED                 0x0
4384 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED                  0x1
4385
4386         u32 speed_cap_mask;                                     /* 0x14 */
4387 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK            0x0000FFFF
4388 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET          0
4389 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G              0x1
4390 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G             0x2
4391 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G             0x8
4392 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G             0x10
4393 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G             0x20
4394 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G            0x40
4395 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK            0xFFFF0000
4396 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET          16
4397 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G              0x1
4398 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G             0x2
4399 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G             0x8
4400 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G             0x10
4401 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G             0x20
4402 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_100G            0x40
4403
4404         u32 link_settings;                                      /* 0x18 */
4405 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK                       0x0000000F
4406 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET                     0
4407 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG                    0x0
4408 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G                         0x1
4409 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G                        0x2
4410 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G                        0x4
4411 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G                        0x5
4412 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G                        0x6
4413 #define NVM_CFG1_PORT_DRV_LINK_SPEED_100G                       0x7
4414 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK                     0x00000070
4415 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET                   4
4416 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG                  0x1
4417 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX                       0x2
4418 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX                       0x4
4419 #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK                       0x00000780
4420 #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET                     7
4421 #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG                    0x0
4422 #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G                         0x1
4423 #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G                        0x2
4424 #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G                        0x4
4425 #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G                        0x5
4426 #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G                        0x6
4427 #define NVM_CFG1_PORT_MFW_LINK_SPEED_100G                       0x7
4428 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK                     0x00003800
4429 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET                   11
4430 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG                  0x1
4431 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX                       0x2
4432 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX                       0x4
4433 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK      0x00004000
4434 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET    14
4435 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED  0x0
4436 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED   0x1
4437
4438         u32 phy_cfg;                                            /* 0x1C */
4439 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK                  0x0000FFFF
4440 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET                0
4441 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG                 0x1
4442 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER             0x2
4443 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER                 0x4
4444 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN       0x8
4445 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN        0x10
4446 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK                 0x00FF0000
4447 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET               16
4448 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS               0x0
4449 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR                   0x2
4450 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2                  0x3
4451 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4                  0x4
4452 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI                  0x8
4453 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI                  0x9
4454 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X                0xB
4455 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII                0xC
4456 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI                0xD
4457 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI                 0xE
4458 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI                0xF
4459 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI                 0x10
4460 #define NVM_CFG1_PORT_AN_MODE_MASK                              0xFF000000
4461 #define NVM_CFG1_PORT_AN_MODE_OFFSET                            24
4462 #define NVM_CFG1_PORT_AN_MODE_NONE                              0x0
4463 #define NVM_CFG1_PORT_AN_MODE_CL73                              0x1
4464 #define NVM_CFG1_PORT_AN_MODE_CL37                              0x2
4465 #define NVM_CFG1_PORT_AN_MODE_CL73_BAM                          0x3
4466 #define NVM_CFG1_PORT_AN_MODE_CL37_BAM                          0x4
4467 #define NVM_CFG1_PORT_AN_MODE_HPAM                              0x5
4468 #define NVM_CFG1_PORT_AN_MODE_SGMII                             0x6
4469
4470         u32 mgmt_traffic;                                       /* 0x20 */
4471 #define NVM_CFG1_PORT_RESERVED61_MASK                           0x0000000F
4472 #define NVM_CFG1_PORT_RESERVED61_OFFSET                         0
4473 #define NVM_CFG1_PORT_RESERVED61_DISABLED                       0x0
4474 #define NVM_CFG1_PORT_RESERVED61_NCSI_OVER_RMII                 0x1
4475 #define NVM_CFG1_PORT_RESERVED61_NCSI_OVER_SMBUS                0x2
4476
4477         u32 ext_phy;                                            /* 0x24 */
4478 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK                    0x000000FF
4479 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET                  0
4480 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE                    0x0
4481 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM84844                0x1
4482 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK                 0x0000FF00
4483 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET               8
4484
4485         u32 mba_cfg1;                                           /* 0x28 */
4486 #define NVM_CFG1_PORT_MBA_MASK                                  0x00000001
4487 #define NVM_CFG1_PORT_MBA_OFFSET                                0
4488 #define NVM_CFG1_PORT_MBA_DISABLED                              0x0
4489 #define NVM_CFG1_PORT_MBA_ENABLED                               0x1
4490 #define NVM_CFG1_PORT_MBA_BOOT_TYPE_MASK                        0x00000006
4491 #define NVM_CFG1_PORT_MBA_BOOT_TYPE_OFFSET                      1
4492 #define NVM_CFG1_PORT_MBA_BOOT_TYPE_AUTO                        0x0
4493 #define NVM_CFG1_PORT_MBA_BOOT_TYPE_BBS                         0x1
4494 #define NVM_CFG1_PORT_MBA_BOOT_TYPE_INT18H                      0x2
4495 #define NVM_CFG1_PORT_MBA_BOOT_TYPE_INT19H                      0x3
4496 #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK                       0x00000078
4497 #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET                     3
4498 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK                    0x00000080
4499 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET                  7
4500 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S                  0x0
4501 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B                  0x1
4502 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK                0x00000100
4503 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET              8
4504 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED            0x0
4505 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED             0x1
4506 #define NVM_CFG1_PORT_RESERVED5_MASK                            0x0001FE00
4507 #define NVM_CFG1_PORT_RESERVED5_OFFSET                          9
4508 #define NVM_CFG1_PORT_RESERVED5_DISABLED                        0x0
4509 #define NVM_CFG1_PORT_RESERVED5_2K                              0x1
4510 #define NVM_CFG1_PORT_RESERVED5_4K                              0x2
4511 #define NVM_CFG1_PORT_RESERVED5_8K                              0x3
4512 #define NVM_CFG1_PORT_RESERVED5_16K                             0x4
4513 #define NVM_CFG1_PORT_RESERVED5_32K                             0x5
4514 #define NVM_CFG1_PORT_RESERVED5_64K                             0x6
4515 #define NVM_CFG1_PORT_RESERVED5_128K                            0x7
4516 #define NVM_CFG1_PORT_RESERVED5_256K                            0x8
4517 #define NVM_CFG1_PORT_RESERVED5_512K                            0x9
4518 #define NVM_CFG1_PORT_RESERVED5_1M                              0xA
4519 #define NVM_CFG1_PORT_RESERVED5_2M                              0xB
4520 #define NVM_CFG1_PORT_RESERVED5_4M                              0xC
4521 #define NVM_CFG1_PORT_RESERVED5_8M                              0xD
4522 #define NVM_CFG1_PORT_RESERVED5_16M                             0xE
4523 #define NVM_CFG1_PORT_RESERVED5_32M                             0xF
4524 #define NVM_CFG1_PORT_MBA_LINK_SPEED_MASK                       0x001E0000
4525 #define NVM_CFG1_PORT_MBA_LINK_SPEED_OFFSET                     17
4526 #define NVM_CFG1_PORT_MBA_LINK_SPEED_AUTONEG                    0x0
4527 #define NVM_CFG1_PORT_MBA_LINK_SPEED_1G                         0x1
4528 #define NVM_CFG1_PORT_MBA_LINK_SPEED_10G                        0x2
4529 #define NVM_CFG1_PORT_MBA_LINK_SPEED_25G                        0x4
4530 #define NVM_CFG1_PORT_MBA_LINK_SPEED_40G                        0x5
4531 #define NVM_CFG1_PORT_MBA_LINK_SPEED_50G                        0x6
4532 #define NVM_CFG1_PORT_MBA_LINK_SPEED_100G                       0x7
4533 #define NVM_CFG1_PORT_MBA_BOOT_RETRY_COUNT_MASK                 0x00E00000
4534 #define NVM_CFG1_PORT_MBA_BOOT_RETRY_COUNT_OFFSET               21
4535
4536         u32     mba_cfg2;                                       /* 0x2C */
4537 #define NVM_CFG1_PORT_MBA_VLAN_VALUE_MASK                       0x0000FFFF
4538 #define NVM_CFG1_PORT_MBA_VLAN_VALUE_OFFSET                     0
4539 #define NVM_CFG1_PORT_MBA_VLAN_MASK                             0x00010000
4540 #define NVM_CFG1_PORT_MBA_VLAN_OFFSET                           16
4541
4542         u32     vf_cfg;                                         /* 0x30 */
4543 #define NVM_CFG1_PORT_RESERVED8_MASK                            0x0000FFFF
4544 #define NVM_CFG1_PORT_RESERVED8_OFFSET                          0
4545 #define NVM_CFG1_PORT_RESERVED6_MASK                            0x000F0000
4546 #define NVM_CFG1_PORT_RESERVED6_OFFSET                          16
4547 #define NVM_CFG1_PORT_RESERVED6_DISABLED                        0x0
4548 #define NVM_CFG1_PORT_RESERVED6_4K                              0x1
4549 #define NVM_CFG1_PORT_RESERVED6_8K                              0x2
4550 #define NVM_CFG1_PORT_RESERVED6_16K                             0x3
4551 #define NVM_CFG1_PORT_RESERVED6_32K                             0x4
4552 #define NVM_CFG1_PORT_RESERVED6_64K                             0x5
4553 #define NVM_CFG1_PORT_RESERVED6_128K                            0x6
4554 #define NVM_CFG1_PORT_RESERVED6_256K                            0x7
4555 #define NVM_CFG1_PORT_RESERVED6_512K                            0x8
4556 #define NVM_CFG1_PORT_RESERVED6_1M                              0x9
4557 #define NVM_CFG1_PORT_RESERVED6_2M                              0xA
4558 #define NVM_CFG1_PORT_RESERVED6_4M                              0xB
4559 #define NVM_CFG1_PORT_RESERVED6_8M                              0xC
4560 #define NVM_CFG1_PORT_RESERVED6_16M                             0xD
4561 #define NVM_CFG1_PORT_RESERVED6_32M                             0xE
4562 #define NVM_CFG1_PORT_RESERVED6_64M                             0xF
4563
4564         struct nvm_cfg_mac_address      lldp_mac_address;       /* 0x34 */
4565
4566         u32                             led_port_settings;      /* 0x3C */
4567 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK                   0x000000FF
4568 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET                 0
4569 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK                   0x0000FF00
4570 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET                 8
4571 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK                   0x00FF0000
4572 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET                 16
4573 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G                      0x1
4574 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G                     0x2
4575 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G                     0x8
4576 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G                     0x10
4577 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G                     0x20
4578 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_100G                    0x40
4579
4580         u32 transceiver_00;                                     /* 0x40 */
4581
4582         /*  Define for mapping of transceiver signal module absent */
4583 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK                     0x000000FF
4584 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET                   0
4585 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA                       0x0
4586 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0                    0x1
4587 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1                    0x2
4588 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2                    0x3
4589 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3                    0x4
4590 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4                    0x5
4591 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5                    0x6
4592 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6                    0x7
4593 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7                    0x8
4594 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8                    0x9
4595 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9                    0xA
4596 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10                   0xB
4597 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11                   0xC
4598 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12                   0xD
4599 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13                   0xE
4600 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14                   0xF
4601 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15                   0x10
4602 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16                   0x11
4603 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17                   0x12
4604 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18                   0x13
4605 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19                   0x14
4606 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20                   0x15
4607 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21                   0x16
4608 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22                   0x17
4609 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23                   0x18
4610 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24                   0x19
4611 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25                   0x1A
4612 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26                   0x1B
4613 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27                   0x1C
4614 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28                   0x1D
4615 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29                   0x1E
4616 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30                   0x1F
4617 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31                   0x20
4618         /*  Define the GPIO mux settings  to switch i2c mux to this port */
4619 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK                  0x00000F00
4620 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET                8
4621 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK                  0x0000F000
4622 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET                12
4623
4624         u32 reserved[133];                                      /* 0x44 */
4625 };
4626
4627 struct nvm_cfg1_func {
4628         struct nvm_cfg_mac_address      mac_address;            /* 0x0 */
4629
4630         u32                             rsrv1;                  /* 0x8 */
4631 #define NVM_CFG1_FUNC_RESERVED1_MASK                            0x0000FFFF
4632 #define NVM_CFG1_FUNC_RESERVED1_OFFSET                          0
4633 #define NVM_CFG1_FUNC_RESERVED2_MASK                            0xFFFF0000
4634 #define NVM_CFG1_FUNC_RESERVED2_OFFSET                          16
4635
4636         u32                             rsrv2;                  /* 0xC */
4637 #define NVM_CFG1_FUNC_RESERVED3_MASK                            0x0000FFFF
4638 #define NVM_CFG1_FUNC_RESERVED3_OFFSET                          0
4639 #define NVM_CFG1_FUNC_RESERVED4_MASK                            0xFFFF0000
4640 #define NVM_CFG1_FUNC_RESERVED4_OFFSET                          16
4641
4642         u32                             device_id;              /* 0x10 */
4643 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK                  0x0000FFFF
4644 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET                0
4645 #define NVM_CFG1_FUNC_VENDOR_DEVICE_ID_MASK                     0xFFFF0000
4646 #define NVM_CFG1_FUNC_VENDOR_DEVICE_ID_OFFSET                   16
4647
4648         u32                             cmn_cfg;                /* 0x14 */
4649 #define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_MASK                    0x00000007
4650 #define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_OFFSET                  0
4651 #define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_PXE                     0x0
4652 #define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_RPL                     0x1
4653 #define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_BOOTP                   0x2
4654 #define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_ISCSI_BOOT              0x3
4655 #define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_FCOE_BOOT               0x4
4656 #define NVM_CFG1_FUNC_MBA_BOOT_PROTOCOL_NONE                    0x7
4657 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK                     0x0007FFF8
4658 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET                   3
4659 #define NVM_CFG1_FUNC_PERSONALITY_MASK                          0x00780000
4660 #define NVM_CFG1_FUNC_PERSONALITY_OFFSET                        19
4661 #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET                      0x0
4662 #define NVM_CFG1_FUNC_PERSONALITY_ISCSI                         0x1
4663 #define NVM_CFG1_FUNC_PERSONALITY_FCOE                          0x2
4664 #define NVM_CFG1_FUNC_PERSONALITY_ROCE                          0x3
4665 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK                     0x7F800000
4666 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET                   23
4667 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK                   0x80000000
4668 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET                 31
4669 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED               0x0
4670 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED                0x1
4671
4672         u32 pci_cfg;                                            /* 0x18 */
4673 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK                 0x0000007F
4674 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET               0
4675 #define NVM_CFG1_FUNC_RESERVESD12_MASK                          0x00003F80
4676 #define NVM_CFG1_FUNC_RESERVESD12_OFFSET                        7
4677 #define NVM_CFG1_FUNC_BAR1_SIZE_MASK                            0x0003C000
4678 #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET                          14
4679 #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED                        0x0
4680 #define NVM_CFG1_FUNC_BAR1_SIZE_64K                             0x1
4681 #define NVM_CFG1_FUNC_BAR1_SIZE_128K                            0x2
4682 #define NVM_CFG1_FUNC_BAR1_SIZE_256K                            0x3
4683 #define NVM_CFG1_FUNC_BAR1_SIZE_512K                            0x4
4684 #define NVM_CFG1_FUNC_BAR1_SIZE_1M                              0x5
4685 #define NVM_CFG1_FUNC_BAR1_SIZE_2M                              0x6
4686 #define NVM_CFG1_FUNC_BAR1_SIZE_4M                              0x7
4687 #define NVM_CFG1_FUNC_BAR1_SIZE_8M                              0x8
4688 #define NVM_CFG1_FUNC_BAR1_SIZE_16M                             0x9
4689 #define NVM_CFG1_FUNC_BAR1_SIZE_32M                             0xA
4690 #define NVM_CFG1_FUNC_BAR1_SIZE_64M                             0xB
4691 #define NVM_CFG1_FUNC_BAR1_SIZE_128M                            0xC
4692 #define NVM_CFG1_FUNC_BAR1_SIZE_256M                            0xD
4693 #define NVM_CFG1_FUNC_BAR1_SIZE_512M                            0xE
4694 #define NVM_CFG1_FUNC_BAR1_SIZE_1G                              0xF
4695 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK                        0x03FC0000
4696 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET                      18
4697
4698         struct nvm_cfg_mac_address      fcoe_node_wwn_mac_addr; /* 0x1C */
4699
4700         struct nvm_cfg_mac_address      fcoe_port_wwn_mac_addr; /* 0x24 */
4701
4702         u32                             reserved[9];            /* 0x2C */
4703 };
4704
4705 struct nvm_cfg1 {
4706         struct nvm_cfg1_glob    glob;                           /* 0x0 */
4707
4708         struct nvm_cfg1_path    path[MCP_GLOB_PATH_MAX];        /* 0x140 */
4709
4710         struct nvm_cfg1_port    port[MCP_GLOB_PORT_MAX];        /* 0x230 */
4711
4712         struct nvm_cfg1_func    func[MCP_GLOB_FUNC_MAX];        /* 0xB90 */
4713 };
4714
4715 /******************************************
4716 * nvm_cfg structs
4717 ******************************************/
4718
4719 enum nvm_cfg_sections {
4720         NVM_CFG_SECTION_NVM_CFG1,
4721         NVM_CFG_SECTION_MAX
4722 };
4723
4724 struct nvm_cfg {
4725         u32             num_sections;
4726         u32             sections_offset[NVM_CFG_SECTION_MAX];
4727         struct nvm_cfg1 cfg1;
4728 };
4729
4730 #define PORT_0          0
4731 #define PORT_1          1
4732 #define PORT_2          2
4733 #define PORT_3          3
4734
4735 extern struct spad_layout g_spad;
4736
4737 #define MCP_SPAD_SIZE                       0x00028000  /* 160 KB */
4738
4739 #define SPAD_OFFSET(addr) (((u32)addr - (u32)CPU_SPAD_BASE))
4740
4741 #define TO_OFFSIZE(_offset, _size)                              \
4742         (u32)((((u32)(_offset) >> 2) << OFFSIZE_OFFSET_SHIFT) | \
4743               (((u32)(_size) >> 2) << OFFSIZE_SIZE_SHIFT))
4744
4745 enum spad_sections {
4746         SPAD_SECTION_TRACE,
4747         SPAD_SECTION_NVM_CFG,
4748         SPAD_SECTION_PUBLIC,
4749         SPAD_SECTION_PRIVATE,
4750         SPAD_SECTION_MAX
4751 };
4752
4753 struct spad_layout {
4754         struct nvm_cfg          nvm_cfg;
4755         struct mcp_public_data  public_data;
4756 };
4757
4758 #define CRC_MAGIC_VALUE                     0xDEBB20E3
4759 #define CRC32_POLYNOMIAL                    0xEDB88320
4760 #define NVM_CRC_SIZE                            (sizeof(u32))
4761
4762 enum nvm_sw_arbitrator {
4763         NVM_SW_ARB_HOST,
4764         NVM_SW_ARB_MCP,
4765         NVM_SW_ARB_UART,
4766         NVM_SW_ARB_RESERVED
4767 };
4768
4769 /****************************************************************************
4770 * Boot Strap Region                                                        *
4771 ****************************************************************************/
4772 struct legacy_bootstrap_region {
4773         u32     magic_value;
4774 #define NVM_MAGIC_VALUE          0x669955aa
4775         u32     sram_start_addr;
4776         u32     code_len;               /* boot code length (in dwords) */
4777         u32     code_start_addr;
4778         u32     crc;                    /* 32-bit CRC */
4779 };
4780
4781 /****************************************************************************
4782 * Directories Region                                                       *
4783 ****************************************************************************/
4784 struct nvm_code_entry {
4785         u32     image_type;             /* Image type */
4786         u32     nvm_start_addr;         /* NVM address of the image */
4787         u32     len;                    /* Include CRC */
4788         u32     sram_start_addr;
4789         u32     sram_run_addr;          /* Relevant in case of MIM only */
4790 };
4791
4792 enum nvm_image_type {
4793         NVM_TYPE_TIM1           = 0x01,
4794         NVM_TYPE_TIM2           = 0x02,
4795         NVM_TYPE_MIM1           = 0x03,
4796         NVM_TYPE_MIM2           = 0x04,
4797         NVM_TYPE_MBA            = 0x05,
4798         NVM_TYPE_MODULES_PN     = 0x06,
4799         NVM_TYPE_VPD            = 0x07,
4800         NVM_TYPE_MFW_TRACE1     = 0x08,
4801         NVM_TYPE_MFW_TRACE2     = 0x09,
4802         NVM_TYPE_NVM_CFG1       = 0x0a,
4803         NVM_TYPE_L2B            = 0x0b,
4804         NVM_TYPE_DIR1           = 0x0c,
4805         NVM_TYPE_EAGLE_FW1      = 0x0d,
4806         NVM_TYPE_FALCON_FW1     = 0x0e,
4807         NVM_TYPE_PCIE_FW1       = 0x0f,
4808         NVM_TYPE_HW_SET         = 0x10,
4809         NVM_TYPE_LIM            = 0x11,
4810         NVM_TYPE_AVS_FW1        = 0x12,
4811         NVM_TYPE_DIR2           = 0x13,
4812         NVM_TYPE_CCM            = 0x14,
4813         NVM_TYPE_EAGLE_FW2      = 0x15,
4814         NVM_TYPE_FALCON_FW2     = 0x16,
4815         NVM_TYPE_PCIE_FW2       = 0x17,
4816         NVM_TYPE_AVS_FW2        = 0x18,
4817
4818         NVM_TYPE_MAX,
4819 };
4820
4821 #define MAX_NVM_DIR_ENTRIES 200
4822
4823 struct nvm_dir {
4824         s32 seq;
4825 #define NVM_DIR_NEXT_MFW_MASK   0x00000001
4826 #define NVM_DIR_SEQ_MASK        0xfffffffe
4827 #define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK)
4828
4829 #define IS_DIR_SEQ_VALID(seq) ((seq & NVM_DIR_SEQ_MASK) != NVM_DIR_SEQ_MASK)
4830
4831         u32                     num_images;
4832         u32                     rsrv;
4833         struct nvm_code_entry   code[1]; /* Up to MAX_NVM_DIR_ENTRIES */
4834 };
4835
4836 #define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) +              \
4837                                    (_num_images -                        \
4838                                     1) * sizeof(struct nvm_code_entry) + \
4839                                    NVM_CRC_SIZE)
4840
4841 struct nvm_vpd_image {
4842         u32     format_revision;
4843 #define VPD_IMAGE_VERSION        1
4844
4845         /* This array length depends on the number of VPD fields */
4846         u8      vpd_data[1];
4847 };
4848
4849 /****************************************************************************
4850 * NVRAM FULL MAP                                                           *
4851 ****************************************************************************/
4852 #define DIR_ID_1    (0)
4853 #define DIR_ID_2    (1)
4854 #define MAX_DIR_IDS (2)
4855
4856 #define MFW_BUNDLE_1    (0)
4857 #define MFW_BUNDLE_2    (1)
4858 #define MAX_MFW_BUNDLES (2)
4859
4860 #define FLASH_PAGE_SIZE 0x1000
4861 #define NVM_DIR_MAX_SIZE    (FLASH_PAGE_SIZE)           /* 4Kb */
4862 #define ASIC_MIM_MAX_SIZE   (300 * FLASH_PAGE_SIZE)     /* 1.2Mb */
4863 #define FPGA_MIM_MAX_SIZE   (25 * FLASH_PAGE_SIZE)      /* 60Kb */
4864
4865 #define LIM_MAX_SIZE        ((2 *                                     \
4866                               FLASH_PAGE_SIZE) -                      \
4867                              sizeof(struct legacy_bootstrap_region) - \
4868                              NVM_RSV_SIZE)
4869 #define LIM_OFFSET          (NVM_OFFSET(lim_image))
4870 #define NVM_RSV_SIZE            (44)
4871 #define MIM_MAX_SIZE(is_asic) ((is_asic) ? ASIC_MIM_MAX_SIZE : \
4872                                FPGA_MIM_MAX_SIZE)
4873 #define MIM_OFFSET(idx, is_asic) (NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + \
4874                                   ((idx ==                           \
4875                                     NVM_TYPE_MIM2) ? MIM_MAX_SIZE(is_asic) : 0))
4876 #define NVM_FIXED_AREA_SIZE(is_asic) (sizeof(struct nvm_image) + \
4877                                       MIM_MAX_SIZE(is_asic) * 2)
4878
4879 union nvm_dir_union {
4880         struct nvm_dir  dir;
4881         u8              page[FLASH_PAGE_SIZE];
4882 };
4883
4884 /*                        Address
4885  *  +-------------------+ 0x000000
4886  *  |    Bootstrap:     |
4887  *  | magic_number      |
4888  *  | sram_start_addr   |
4889  *  | code_len          |
4890  *  | code_start_addr   |
4891  *  | crc               |
4892  *  +-------------------+ 0x000014
4893  *  | rsrv              |
4894  *  +-------------------+ 0x000040
4895  *  | LIM               |
4896  *  +-------------------+ 0x002000
4897  *  | Dir1              |
4898  *  +-------------------+ 0x003000
4899  *  | Dir2              |
4900  *  +-------------------+ 0x004000
4901  *  | MIM1              |
4902  *  +-------------------+ 0x130000
4903  *  | MIM2              |
4904  *  +-------------------+ 0x25C000
4905  *  | Rest Images:      |
4906  *  | TIM1/2            |
4907  *  | MFW_TRACE1/2      |
4908  *  | Eagle/Falcon FW   |
4909  *  | PCIE/AVS FW       |
4910  *  | MBA/CCM/L2B       |
4911  *  | VPD               |
4912  *  | optic_modules     |
4913  *  |  ...              |
4914  *  +-------------------+ 0x400000
4915  */
4916 struct nvm_image {
4917 /*********** !!!  FIXED SECTIONS  !!! DO NOT MODIFY !!! **********************/
4918         /* NVM Offset  (size) */
4919         struct legacy_bootstrap_region  bootstrap;
4920         u8                              rsrv[NVM_RSV_SIZE];
4921         u8                              lim_image[LIM_MAX_SIZE];
4922         union nvm_dir_union             dir[MAX_MFW_BUNDLES];
4923
4924         /* MIM1_IMAGE                              0x004000 (0x12c000) */
4925         /* MIM2_IMAGE                              0x130000 (0x12c000) */
4926 /*********** !!!  FIXED SECTIONS  !!! DO NOT MODIFY !!! **********************/
4927 };                              /* 0x134 */
4928
4929 #define NVM_OFFSET(f)   ((u32_t)((int_ptr_t)(&(((struct nvm_image *)0)->f))))
4930
4931 struct hw_set_info {
4932         u32     reg_type;
4933 #define GRC_REG_TYPE 1
4934 #define PHY_REG_TYPE 2
4935 #define PCI_REG_TYPE 4
4936
4937         u32     bank_num;
4938         u32     pf_num;
4939         u32     operation;
4940 #define READ_OP     1
4941 #define WRITE_OP    2
4942 #define RMW_SET_OP  3
4943 #define RMW_CLR_OP  4
4944
4945         u32     reg_addr;
4946         u32     reg_data;
4947
4948         u32     reset_type;
4949 #define POR_RESET_TYPE  BIT(0)
4950 #define HARD_RESET_TYPE BIT(1)
4951 #define CORE_RESET_TYPE BIT(2)
4952 #define MCP_RESET_TYPE  BIT(3)
4953 #define PERSET_ASSERT   BIT(4)
4954 #define PERSET_DEASSERT BIT(5)
4955 };
4956
4957 struct hw_set_image {
4958         u32                     format_version;
4959 #define HW_SET_IMAGE_VERSION        1
4960         u32                     no_hw_sets;
4961
4962         /* This array length depends on the no_hw_sets */
4963         struct hw_set_info      hw_sets[1];
4964 };
4965
4966 #endif