drivers/net/ethernet/qlogic/qed/qed_reg_addr.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #ifndef REG_ADDR_H
  10 #define REG_ADDR_H
  11
  12 #define  CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
  13         0
  14
  15 #define  CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE           ( \
  16                 0xfff << 0)
  17
  18 #define  CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \
  19         12
  20
  21 #define  CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE            ( \
  22                 0xfff << 12)
  23
  24 #define  CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \
  25         24
  26
  27 #define  CDU_REG_CID_ADDR_PARAMS_NCIB                   ( \
  28                 0xff << 24)
  29
  30 #define CDU_REG_SEGMENT0_PARAMS \
  31         0x580904UL
  32 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \
  33         (0xfff << 0)
  34 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \
  35         0
  36 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \
  37         (0xff << 16)
  38 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \
  39         16
  40 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \
  41         (0xff << 24)
  42 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \
  43         24
  44 #define CDU_REG_SEGMENT1_PARAMS \
  45         0x580908UL
  46 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \
  47         (0xfff << 0)
  48 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \
  49         0
  50 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \
  51         (0xff << 16)
  52 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \
  53         16
  54 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \
  55         (0xff << 24)
  56 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \
  57         24
  58
  59 #define  XSDM_REG_OPERATION_GEN \
  60         0xf80408UL
  61 #define  NIG_REG_RX_BRB_OUT_EN \
  62         0x500e18UL
  63 #define  NIG_REG_STORM_OUT_EN \
  64         0x500e08UL
  65 #define  PSWRQ2_REG_L2P_VALIDATE_VFID \
  66         0x240c50UL
  67 #define  PGLUE_B_REG_USE_CLIENTID_IN_TAG        \
  68         0x2aae04UL
  69 #define  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER        \
  70         0x2aa16cUL
  71 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
  72         0x2aa118UL
  73 #define PSWHST_REG_ZONE_PERMISSION_TABLE \
  74         0x2a0800UL
  75 #define  BAR0_MAP_REG_MSDM_RAM \
  76         0x1d00000UL
  77 #define  BAR0_MAP_REG_USDM_RAM \
  78         0x1d80000UL
  79 #define  BAR0_MAP_REG_PSDM_RAM \
  80         0x1f00000UL
  81 #define  BAR0_MAP_REG_TSDM_RAM \
  82         0x1c80000UL
  83 #define BAR0_MAP_REG_XSDM_RAM \
  84         0x1e00000UL
  85 #define  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
  86         0x5011f4UL
  87 #define  PRS_REG_SEARCH_TCP \
  88         0x1f0400UL
  89 #define  PRS_REG_SEARCH_UDP \
  90         0x1f0404UL
  91 #define  PRS_REG_SEARCH_FCOE \
  92         0x1f0408UL
  93 #define  PRS_REG_SEARCH_ROCE \
  94         0x1f040cUL
  95 #define  PRS_REG_SEARCH_OPENFLOW        \
  96         0x1f0434UL
  97 #define  TM_REG_PF_ENABLE_CONN \
  98         0x2c043cUL
  99 #define  TM_REG_PF_ENABLE_TASK \
 100         0x2c0444UL
 101 #define  TM_REG_PF_SCAN_ACTIVE_CONN \
 102         0x2c04fcUL
 103 #define  TM_REG_PF_SCAN_ACTIVE_TASK \
 104         0x2c0500UL
 105 #define  IGU_REG_LEADING_EDGE_LATCH \
 106         0x18082cUL
 107 #define  IGU_REG_TRAILING_EDGE_LATCH \
 108         0x180830UL
 109 #define  QM_REG_USG_CNT_PF_TX \
 110         0x2f2eacUL
 111 #define  QM_REG_USG_CNT_PF_OTHER        \
 112         0x2f2eb0UL
 113 #define  DORQ_REG_PF_DB_ENABLE \
 114         0x100508UL
 115 #define DORQ_REG_VF_USAGE_CNT \
 116         0x1009c4UL
 117 #define  QM_REG_PF_EN \
 118         0x2f2ea4UL
 119 #define TCFC_REG_WEAK_ENABLE_VF \
 120         0x2d0704UL
 121 #define  TCFC_REG_STRONG_ENABLE_PF \
 122         0x2d0708UL
 123 #define  TCFC_REG_STRONG_ENABLE_VF \
 124         0x2d070cUL
 125 #define CCFC_REG_WEAK_ENABLE_VF \
 126         0x2e0704UL
 127 #define  CCFC_REG_STRONG_ENABLE_PF \
 128         0x2e0708UL
 129 #define  PGLUE_B_REG_PGL_ADDR_88_F0 \
 130         0x2aa404UL
 131 #define  PGLUE_B_REG_PGL_ADDR_8C_F0 \
 132         0x2aa408UL
 133 #define  PGLUE_B_REG_PGL_ADDR_90_F0 \
 134         0x2aa40cUL
 135 #define  PGLUE_B_REG_PGL_ADDR_94_F0 \
 136         0x2aa410UL
 137 #define  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \
 138         0x2aa138UL
 139 #define  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
 140         0x2aa174UL
 141 #define  MISC_REG_GEN_PURP_CR0 \
 142         0x008c80UL
 143 #define  MCP_REG_SCRATCH        \
 144         0xe20000UL
 145 #define  CNIG_REG_NW_PORT_MODE_BB_B0 \
 146         0x218200UL
 147 #define  MISCS_REG_CHIP_NUM \
 148         0x00976cUL
 149 #define  MISCS_REG_CHIP_REV \
 150         0x009770UL
 151 #define  MISCS_REG_CMT_ENABLED_FOR_PAIR \
 152         0x00971cUL
 153 #define  MISCS_REG_CHIP_TEST_REG        \
 154         0x009778UL
 155 #define  MISCS_REG_CHIP_METAL \
 156         0x009774UL
 157 #define MISCS_REG_FUNCTION_HIDE \
 158         0x0096f0UL
 159 #define  BRB_REG_HEADER_SIZE \
 160         0x340804UL
 161 #define  BTB_REG_HEADER_SIZE \
 162         0xdb0804UL
 163 #define  CAU_REG_LONG_TIMEOUT_THRESHOLD \
 164         0x1c0708UL
 165 #define  CCFC_REG_ACTIVITY_COUNTER \
 166         0x2e8800UL
 167 #define CCFC_REG_STRONG_ENABLE_VF \
 168         0x2e070cUL
 169 #define  CDU_REG_CID_ADDR_PARAMS        \
 170         0x580900UL
 171 #define  DBG_REG_CLIENT_ENABLE \
 172         0x010004UL
 173 #define  DMAE_REG_INIT \
 174         0x00c000UL
 175 #define  DORQ_REG_IFEN \
 176         0x100040UL
 177 #define DORQ_REG_DB_DROP_REASON \
 178         0x100a2cUL
 179 #define DORQ_REG_DB_DROP_DETAILS \
 180         0x100a24UL
 181 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS \
 182         0x100a1cUL
 183 #define  GRC_REG_TIMEOUT_EN \
 184         0x050404UL
 185 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \
 186         0x050054UL
 187 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \
 188         0x05004cUL
 189 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \
 190         0x050050UL
 191 #define  IGU_REG_BLOCK_CONFIGURATION \
 192         0x180040UL
 193 #define  MCM_REG_INIT \
 194         0x1200000UL
 195 #define  MCP2_REG_DBG_DWORD_ENABLE \
 196         0x052404UL
 197 #define  MISC_REG_PORT_MODE \
 198         0x008c00UL
 199 #define  MISCS_REG_CLK_100G_MODE        \
 200         0x009070UL
 201 #define  MSDM_REG_ENABLE_IN1 \
 202         0xfc0004UL
 203 #define  MSEM_REG_ENABLE_IN \
 204         0x1800004UL
 205 #define  NIG_REG_CM_HDR \
 206         0x500840UL
 207 #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \
 208         0x50196cUL
 209 #define NIG_REG_LLH_CLS_TYPE_DUALMODE \
 210         0x501964UL
 211 #define  NCSI_REG_CONFIG        \
 212         0x040200UL
 213 #define  PBF_REG_INIT \
 214         0xd80000UL
 215 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \
 216         0xd806c8UL
 217 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \
 218         0xd806ccUL
 219 #define  PTU_REG_ATC_INIT_ARRAY \
 220         0x560000UL
 221 #define  PCM_REG_INIT \
 222         0x1100000UL
 223 #define  PGLUE_B_REG_ADMIN_PER_PF_REGION        \
 224         0x2a9000UL
 225 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \
 226         0x2aa150UL
 227 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \
 228         0x2aa144UL
 229 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \
 230         0x2aa148UL
 231 #define PGLUE_B_REG_TX_ERR_WR_DETAILS \
 232         0x2aa14cUL
 233 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \
 234         0x2aa154UL
 235 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \
 236         0x2aa158UL
 237 #define PGLUE_B_REG_TX_ERR_RD_DETAILS \
 238         0x2aa15cUL
 239 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \
 240         0x2aa160UL
 241 #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \
 242         0x2aa164UL
 243 #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \
 244         0x2aa54cUL
 245 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \
 246         0x2aa544UL
 247 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \
 248         0x2aa548UL
 249 #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \
 250         0x2aae74UL
 251 #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \
 252         0x2aae78UL
 253 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS \
 254         0x2aae7cUL
 255 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \
 256         0x2aae80UL
 257 #define PGLUE_B_REG_LATCHED_ERRORS_CLR \
 258         0x2aa3bcUL
 259 #define  PRM_REG_DISABLE_PRM \
 260         0x230000UL
 261 #define  PRS_REG_SOFT_RST \
 262         0x1f0000UL
 263 #define PRS_REG_MSG_INFO \
 264         0x1f0a1cUL
 265 #define PRS_REG_ROCE_DEST_QP_MAX_PF \
 266         0x1f0430UL
 267 #define  PSDM_REG_ENABLE_IN1 \
 268         0xfa0004UL
 269 #define  PSEM_REG_ENABLE_IN \
 270         0x1600004UL
 271 #define  PSWRQ_REG_DBG_SELECT \
 272         0x280020UL
 273 #define  PSWRQ2_REG_CDUT_P_SIZE \
 274         0x24000cUL
 275 #define PSWRQ2_REG_ILT_MEMORY \
 276         0x260000UL
 277 #define  PSWHST_REG_DISCARD_INTERNAL_WRITES \
 278         0x2a0040UL
 279 #define  PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
 280         0x29e050UL
 281 #define PSWHST_REG_INCORRECT_ACCESS_VALID \
 282         0x2a0070UL
 283 #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \
 284         0x2a0074UL
 285 #define PSWHST_REG_INCORRECT_ACCESS_DATA \
 286         0x2a0068UL
 287 #define PSWHST_REG_INCORRECT_ACCESS_LENGTH \
 288         0x2a006cUL
 289 #define  PSWRD_REG_DBG_SELECT \
 290         0x29c040UL
 291 #define  PSWRD2_REG_CONF11 \
 292         0x29d064UL
 293 #define  PSWWR_REG_USDM_FULL_TH \
 294         0x29a040UL
 295 #define  PSWWR2_REG_CDU_FULL_TH2        \
 296         0x29b040UL
 297 #define  QM_REG_MAXPQSIZE_0 \
 298         0x2f0434UL
 299 #define  RSS_REG_RSS_INIT_EN \
 300         0x238804UL
 301 #define  RDIF_REG_STOP_ON_ERROR \
 302         0x300040UL
 303 #define  SRC_REG_SOFT_RST \
 304         0x23874cUL
 305 #define  TCFC_REG_ACTIVITY_COUNTER \
 306         0x2d8800UL
 307 #define  TCM_REG_INIT \
 308         0x1180000UL
 309 #define  TM_REG_PXP_READ_DATA_FIFO_INIT \
 310         0x2c0014UL
 311 #define  TSDM_REG_ENABLE_IN1 \
 312         0xfb0004UL
 313 #define  TSEM_REG_ENABLE_IN \
 314         0x1700004UL
 315 #define  TDIF_REG_STOP_ON_ERROR \
 316         0x310040UL
 317 #define  UCM_REG_INIT \
 318         0x1280000UL
 319 #define  UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \
 320         0x051004UL
 321 #define  USDM_REG_ENABLE_IN1 \
 322         0xfd0004UL
 323 #define  USEM_REG_ENABLE_IN \
 324         0x1900004UL
 325 #define  XCM_REG_INIT \
 326         0x1000000UL
 327 #define  XSDM_REG_ENABLE_IN1 \
 328         0xf80004UL
 329 #define  XSEM_REG_ENABLE_IN \
 330         0x1400004UL
 331 #define  YCM_REG_INIT \
 332         0x1080000UL
 333 #define  YSDM_REG_ENABLE_IN1 \
 334         0xf90004UL
 335 #define  YSEM_REG_ENABLE_IN \
 336         0x1500004UL
 337 #define  XYLD_REG_SCBD_STRICT_PRIO \
 338         0x4c0000UL
 339 #define  TMLD_REG_SCBD_STRICT_PRIO \
 340         0x4d0000UL
 341 #define  MULD_REG_SCBD_STRICT_PRIO \
 342         0x4e0000UL
 343 #define  YULD_REG_SCBD_STRICT_PRIO \
 344         0x4c8000UL
 345 #define  MISC_REG_SHARED_MEM_ADDR \
 346         0x008c20UL
 347 #define  DMAE_REG_GO_C0 \
 348         0x00c048UL
 349 #define  DMAE_REG_GO_C1 \
 350         0x00c04cUL
 351 #define  DMAE_REG_GO_C2 \
 352         0x00c050UL
 353 #define  DMAE_REG_GO_C3 \
 354         0x00c054UL
 355 #define  DMAE_REG_GO_C4 \
 356         0x00c058UL
 357 #define  DMAE_REG_GO_C5 \
 358         0x00c05cUL
 359 #define  DMAE_REG_GO_C6 \
 360         0x00c060UL
 361 #define  DMAE_REG_GO_C7 \
 362         0x00c064UL
 363 #define  DMAE_REG_GO_C8 \
 364         0x00c068UL
 365 #define  DMAE_REG_GO_C9 \
 366         0x00c06cUL
 367 #define  DMAE_REG_GO_C10        \
 368         0x00c070UL
 369 #define  DMAE_REG_GO_C11        \
 370         0x00c074UL
 371 #define  DMAE_REG_GO_C12        \
 372         0x00c078UL
 373 #define  DMAE_REG_GO_C13        \
 374         0x00c07cUL
 375 #define  DMAE_REG_GO_C14        \
 376         0x00c080UL
 377 #define  DMAE_REG_GO_C15        \
 378         0x00c084UL
 379 #define  DMAE_REG_GO_C16        \
 380         0x00c088UL
 381 #define  DMAE_REG_GO_C17        \
 382         0x00c08cUL
 383 #define  DMAE_REG_GO_C18        \
 384         0x00c090UL
 385 #define  DMAE_REG_GO_C19        \
 386         0x00c094UL
 387 #define  DMAE_REG_GO_C20        \
 388         0x00c098UL
 389 #define  DMAE_REG_GO_C21        \
 390         0x00c09cUL
 391 #define  DMAE_REG_GO_C22        \
 392         0x00c0a0UL
 393 #define  DMAE_REG_GO_C23        \
 394         0x00c0a4UL
 395 #define  DMAE_REG_GO_C24        \
 396         0x00c0a8UL
 397 #define  DMAE_REG_GO_C25        \
 398         0x00c0acUL
 399 #define  DMAE_REG_GO_C26        \
 400         0x00c0b0UL
 401 #define  DMAE_REG_GO_C27        \
 402         0x00c0b4UL
 403 #define  DMAE_REG_GO_C28        \
 404         0x00c0b8UL
 405 #define  DMAE_REG_GO_C29        \
 406         0x00c0bcUL
 407 #define  DMAE_REG_GO_C30        \
 408         0x00c0c0UL
 409 #define  DMAE_REG_GO_C31        \
 410         0x00c0c4UL
 411 #define  DMAE_REG_CMD_MEM \
 412         0x00c800UL
 413 #define  QM_REG_MAXPQSIZETXSEL_0        \
 414         0x2f0440UL
 415 #define  QM_REG_SDMCMDREADY \
 416         0x2f1e10UL
 417 #define  QM_REG_SDMCMDADDR \
 418         0x2f1e04UL
 419 #define  QM_REG_SDMCMDDATALSB \
 420         0x2f1e08UL
 421 #define  QM_REG_SDMCMDDATAMSB \
 422         0x2f1e0cUL
 423 #define  QM_REG_SDMCMDGO        \
 424         0x2f1e14UL
 425 #define  QM_REG_RLPFCRD \
 426         0x2f4d80UL
 427 #define  QM_REG_RLPFINCVAL \
 428         0x2f4c80UL
 429 #define  QM_REG_RLGLBLCRD \
 430         0x2f4400UL
 431 #define  QM_REG_RLGLBLINCVAL \
 432         0x2f3400UL
 433 #define  IGU_REG_ATTENTION_ENABLE \
 434         0x18083cUL
 435 #define  IGU_REG_ATTN_MSG_ADDR_L        \
 436         0x180820UL
 437 #define  IGU_REG_ATTN_MSG_ADDR_H        \
 438         0x180824UL
 439 #define  MISC_REG_AEU_GENERAL_ATTN_0 \
 440         0x008400UL
 441 #define  CAU_REG_SB_ADDR_MEMORY \
 442         0x1c8000UL
 443 #define  CAU_REG_SB_VAR_MEMORY \
 444         0x1c6000UL
 445 #define  CAU_REG_PI_MEMORY \
 446         0x1d0000UL
 447 #define  IGU_REG_PF_CONFIGURATION \
 448         0x180800UL
 449 #define IGU_REG_VF_CONFIGURATION \
 450         0x180804UL
 451 #define  MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
 452         0x00849cUL
 453 #define MISC_REG_AEU_AFTER_INVERT_1_IGU \
 454         0x0087b4UL
 455 #define  MISC_REG_AEU_MASK_ATTN_IGU \
 456         0x008494UL
 457 #define  IGU_REG_CLEANUP_STATUS_0 \
 458         0x180980UL
 459 #define  IGU_REG_CLEANUP_STATUS_1 \
 460         0x180a00UL
 461 #define  IGU_REG_CLEANUP_STATUS_2 \
 462         0x180a80UL
 463 #define  IGU_REG_CLEANUP_STATUS_3 \
 464         0x180b00UL
 465 #define  IGU_REG_CLEANUP_STATUS_4 \
 466         0x180b80UL
 467 #define  IGU_REG_COMMAND_REG_32LSB_DATA \
 468         0x180840UL
 469 #define  IGU_REG_COMMAND_REG_CTRL \
 470         0x180848UL
 471 #define  IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN      ( \
 472                 0x1 << 1)
 473 #define  IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN       ( \
 474                 0x1 << 0)
 475 #define  IGU_REG_MAPPING_MEMORY \
 476         0x184000UL
 477 #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \
 478         0x180408UL
 479 #define IGU_REG_WRITE_DONE_PENDING \
 480         0x180900UL
 481 #define  MISCS_REG_GENERIC_POR_0        \
 482         0x0096d4UL
 483 #define  MCP_REG_NVM_CFG4 \
 484         0xe0642cUL
 485 #define  MCP_REG_NVM_CFG4_FLASH_SIZE    ( \
 486                 0x7 << 0)
 487 #define  MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \
 488         0
 489 #define MCP_REG_CPU_STATE \
 490         0xe05004UL
 491 #define MCP_REG_CPU_EVENT_MASK \
 492         0xe05008UL
 493 #define PGLUE_B_REG_PF_BAR0_SIZE \
 494         0x2aae60UL
 495 #define PGLUE_B_REG_PF_BAR1_SIZE \
 496         0x2aae64UL
 497 #define PRS_REG_ENCAPSULATION_TYPE_EN   0x1f0730UL
 498 #define PRS_REG_GRE_PROTOCOL            0x1f0734UL
 499 #define PRS_REG_VXLAN_PORT              0x1f0738UL
 500 #define PRS_REG_OUTPUT_FORMAT_4_0       0x1f099cUL
 501 #define NIG_REG_ENC_TYPE_ENABLE         0x501058UL
 502
 503 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE             (0x1 << 0)
 504 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT       0
 505 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE              (0x1 << 1)
 506 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT        1
 507 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE                    (0x1 << 2)
 508 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT              2
 509
 510 #define NIG_REG_VXLAN_CTRL              0x50105cUL
 511 #define PBF_REG_VXLAN_PORT              0xd80518UL
 512 #define PBF_REG_NGE_PORT                0xd8051cUL
 513 #define PRS_REG_NGE_PORT                0x1f086cUL
 514 #define NIG_REG_NGE_PORT                0x508b38UL
 515
 516 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN      0x10090cUL
 517 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN       0x100910UL
 518 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN        0x100914UL
 519 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN       0x10092cUL
 520 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN      0x100930UL
 521
 522 #define NIG_REG_NGE_IP_ENABLE                   0x508b28UL
 523 #define NIG_REG_NGE_ETH_ENABLE                  0x508b2cUL
 524 #define NIG_REG_NGE_COMP_VER                    0x508b30UL
 525 #define PBF_REG_NGE_COMP_VER                    0xd80524UL
 526 #define PRS_REG_NGE_COMP_VER                    0x1f0878UL
 527
 528 #define QM_REG_WFQPFWEIGHT      0x2f4e80UL
 529 #define QM_REG_WFQVPWEIGHT      0x2fa000UL
 530
 531 #define PGLCS_REG_DBG_SELECT \
 532         0x001d14UL
 533 #define PGLCS_REG_DBG_DWORD_ENABLE \
 534         0x001d18UL
 535 #define PGLCS_REG_DBG_SHIFT \
 536         0x001d1cUL
 537 #define PGLCS_REG_DBG_FORCE_VALID \
 538         0x001d20UL
 539 #define PGLCS_REG_DBG_FORCE_FRAME \
 540         0x001d24UL
 541 #define MISC_REG_RESET_PL_PDA_VMAIN_1 \
 542         0x008070UL
 543 #define MISC_REG_RESET_PL_PDA_VMAIN_2 \
 544         0x008080UL
 545 #define MISC_REG_RESET_PL_PDA_VAUX \
 546         0x008090UL
 547 #define MISCS_REG_RESET_PL_UA \
 548         0x009050UL
 549 #define MISCS_REG_RESET_PL_HV \
 550         0x009060UL
 551 #define MISCS_REG_RESET_PL_HV_2 \
 552         0x009150UL
 553 #define DMAE_REG_DBG_SELECT \
 554         0x00c510UL
 555 #define DMAE_REG_DBG_DWORD_ENABLE \
 556         0x00c514UL
 557 #define DMAE_REG_DBG_SHIFT \
 558         0x00c518UL
 559 #define DMAE_REG_DBG_FORCE_VALID \
 560         0x00c51cUL
 561 #define DMAE_REG_DBG_FORCE_FRAME \
 562         0x00c520UL
 563 #define NCSI_REG_DBG_SELECT \
 564         0x040474UL
 565 #define NCSI_REG_DBG_DWORD_ENABLE \
 566         0x040478UL
 567 #define NCSI_REG_DBG_SHIFT \
 568         0x04047cUL
 569 #define NCSI_REG_DBG_FORCE_VALID \
 570         0x040480UL
 571 #define NCSI_REG_DBG_FORCE_FRAME \
 572         0x040484UL
 573 #define GRC_REG_DBG_SELECT \
 574         0x0500a4UL
 575 #define GRC_REG_DBG_DWORD_ENABLE \
 576         0x0500a8UL
 577 #define GRC_REG_DBG_SHIFT \
 578         0x0500acUL
 579 #define GRC_REG_DBG_FORCE_VALID \
 580         0x0500b0UL
 581 #define GRC_REG_DBG_FORCE_FRAME \
 582         0x0500b4UL
 583 #define UMAC_REG_DBG_SELECT \
 584         0x051094UL
 585 #define UMAC_REG_DBG_DWORD_ENABLE \
 586         0x051098UL
 587 #define UMAC_REG_DBG_SHIFT \
 588         0x05109cUL
 589 #define UMAC_REG_DBG_FORCE_VALID \
 590         0x0510a0UL
 591 #define UMAC_REG_DBG_FORCE_FRAME \
 592         0x0510a4UL
 593 #define MCP2_REG_DBG_SELECT \
 594         0x052400UL
 595 #define MCP2_REG_DBG_DWORD_ENABLE \
 596         0x052404UL
 597 #define MCP2_REG_DBG_SHIFT \
 598         0x052408UL
 599 #define MCP2_REG_DBG_FORCE_VALID \
 600         0x052440UL
 601 #define MCP2_REG_DBG_FORCE_FRAME \
 602         0x052444UL
 603 #define PCIE_REG_DBG_SELECT \
 604         0x0547e8UL
 605 #define PCIE_REG_DBG_DWORD_ENABLE \
 606         0x0547ecUL
 607 #define PCIE_REG_DBG_SHIFT \
 608         0x0547f0UL
 609 #define PCIE_REG_DBG_FORCE_VALID \
 610         0x0547f4UL
 611 #define PCIE_REG_DBG_FORCE_FRAME \
 612         0x0547f8UL
 613 #define DORQ_REG_DBG_SELECT \
 614         0x100ad0UL
 615 #define DORQ_REG_DBG_DWORD_ENABLE \
 616         0x100ad4UL
 617 #define DORQ_REG_DBG_SHIFT \
 618         0x100ad8UL
 619 #define DORQ_REG_DBG_FORCE_VALID \
 620         0x100adcUL
 621 #define DORQ_REG_DBG_FORCE_FRAME \
 622         0x100ae0UL
 623 #define IGU_REG_DBG_SELECT \
 624         0x181578UL
 625 #define IGU_REG_DBG_DWORD_ENABLE \
 626         0x18157cUL
 627 #define IGU_REG_DBG_SHIFT \
 628         0x181580UL
 629 #define IGU_REG_DBG_FORCE_VALID \
 630         0x181584UL
 631 #define IGU_REG_DBG_FORCE_FRAME \
 632         0x181588UL
 633 #define CAU_REG_DBG_SELECT \
 634         0x1c0ea8UL
 635 #define CAU_REG_DBG_DWORD_ENABLE \
 636         0x1c0eacUL
 637 #define CAU_REG_DBG_SHIFT \
 638         0x1c0eb0UL
 639 #define CAU_REG_DBG_FORCE_VALID \
 640         0x1c0eb4UL
 641 #define CAU_REG_DBG_FORCE_FRAME \
 642         0x1c0eb8UL
 643 #define PRS_REG_DBG_SELECT \
 644         0x1f0b6cUL
 645 #define PRS_REG_DBG_DWORD_ENABLE \
 646         0x1f0b70UL
 647 #define PRS_REG_DBG_SHIFT \
 648         0x1f0b74UL
 649 #define PRS_REG_DBG_FORCE_VALID \
 650         0x1f0ba0UL
 651 #define PRS_REG_DBG_FORCE_FRAME \
 652         0x1f0ba4UL
 653 #define CNIG_REG_DBG_SELECT_K2 \
 654         0x218254UL
 655 #define CNIG_REG_DBG_DWORD_ENABLE_K2 \
 656         0x218258UL
 657 #define CNIG_REG_DBG_SHIFT_K2 \
 658         0x21825cUL
 659 #define CNIG_REG_DBG_FORCE_VALID_K2 \
 660         0x218260UL
 661 #define CNIG_REG_DBG_FORCE_FRAME_K2 \
 662         0x218264UL
 663 #define PRM_REG_DBG_SELECT \
 664         0x2306a8UL
 665 #define PRM_REG_DBG_DWORD_ENABLE \
 666         0x2306acUL
 667 #define PRM_REG_DBG_SHIFT \
 668         0x2306b0UL
 669 #define PRM_REG_DBG_FORCE_VALID \
 670         0x2306b4UL
 671 #define PRM_REG_DBG_FORCE_FRAME \
 672         0x2306b8UL
 673 #define SRC_REG_DBG_SELECT \
 674         0x238700UL
 675 #define SRC_REG_DBG_DWORD_ENABLE \
 676         0x238704UL
 677 #define SRC_REG_DBG_SHIFT \
 678         0x238708UL
 679 #define SRC_REG_DBG_FORCE_VALID \
 680         0x23870cUL
 681 #define SRC_REG_DBG_FORCE_FRAME \
 682         0x238710UL
 683 #define RSS_REG_DBG_SELECT \
 684         0x238c4cUL
 685 #define RSS_REG_DBG_DWORD_ENABLE \
 686         0x238c50UL
 687 #define RSS_REG_DBG_SHIFT \
 688         0x238c54UL
 689 #define RSS_REG_DBG_FORCE_VALID \
 690         0x238c58UL
 691 #define RSS_REG_DBG_FORCE_FRAME \
 692         0x238c5cUL
 693 #define RPB_REG_DBG_SELECT \
 694         0x23c728UL
 695 #define RPB_REG_DBG_DWORD_ENABLE \
 696         0x23c72cUL
 697 #define RPB_REG_DBG_SHIFT \
 698         0x23c730UL
 699 #define RPB_REG_DBG_FORCE_VALID \
 700         0x23c734UL
 701 #define RPB_REG_DBG_FORCE_FRAME \
 702         0x23c738UL
 703 #define PSWRQ2_REG_DBG_SELECT \
 704         0x240100UL
 705 #define PSWRQ2_REG_DBG_DWORD_ENABLE \
 706         0x240104UL
 707 #define PSWRQ2_REG_DBG_SHIFT \
 708         0x240108UL
 709 #define PSWRQ2_REG_DBG_FORCE_VALID \
 710         0x24010cUL
 711 #define PSWRQ2_REG_DBG_FORCE_FRAME \
 712         0x240110UL
 713 #define PSWRQ_REG_DBG_SELECT \
 714         0x280020UL
 715 #define PSWRQ_REG_DBG_DWORD_ENABLE \
 716         0x280024UL
 717 #define PSWRQ_REG_DBG_SHIFT \
 718         0x280028UL
 719 #define PSWRQ_REG_DBG_FORCE_VALID \
 720         0x28002cUL
 721 #define PSWRQ_REG_DBG_FORCE_FRAME \
 722         0x280030UL
 723 #define PSWWR_REG_DBG_SELECT \
 724         0x29a084UL
 725 #define PSWWR_REG_DBG_DWORD_ENABLE \
 726         0x29a088UL
 727 #define PSWWR_REG_DBG_SHIFT \
 728         0x29a08cUL
 729 #define PSWWR_REG_DBG_FORCE_VALID \
 730         0x29a090UL
 731 #define PSWWR_REG_DBG_FORCE_FRAME \
 732         0x29a094UL
 733 #define PSWRD_REG_DBG_SELECT \
 734         0x29c040UL
 735 #define PSWRD_REG_DBG_DWORD_ENABLE \
 736         0x29c044UL
 737 #define PSWRD_REG_DBG_SHIFT \
 738         0x29c048UL
 739 #define PSWRD_REG_DBG_FORCE_VALID \
 740         0x29c04cUL
 741 #define PSWRD_REG_DBG_FORCE_FRAME \
 742         0x29c050UL
 743 #define PSWRD2_REG_DBG_SELECT \
 744         0x29d400UL
 745 #define PSWRD2_REG_DBG_DWORD_ENABLE \
 746         0x29d404UL
 747 #define PSWRD2_REG_DBG_SHIFT \
 748         0x29d408UL
 749 #define PSWRD2_REG_DBG_FORCE_VALID \
 750         0x29d40cUL
 751 #define PSWRD2_REG_DBG_FORCE_FRAME \
 752         0x29d410UL
 753 #define PSWHST2_REG_DBG_SELECT \
 754         0x29e058UL
 755 #define PSWHST2_REG_DBG_DWORD_ENABLE \
 756         0x29e05cUL
 757 #define PSWHST2_REG_DBG_SHIFT \
 758         0x29e060UL
 759 #define PSWHST2_REG_DBG_FORCE_VALID \
 760         0x29e064UL
 761 #define PSWHST2_REG_DBG_FORCE_FRAME \
 762         0x29e068UL
 763 #define PSWHST_REG_DBG_SELECT \
 764         0x2a0100UL
 765 #define PSWHST_REG_DBG_DWORD_ENABLE \
 766         0x2a0104UL
 767 #define PSWHST_REG_DBG_SHIFT \
 768         0x2a0108UL
 769 #define PSWHST_REG_DBG_FORCE_VALID \
 770         0x2a010cUL
 771 #define PSWHST_REG_DBG_FORCE_FRAME \
 772         0x2a0110UL
 773 #define PGLUE_B_REG_DBG_SELECT \
 774         0x2a8400UL
 775 #define PGLUE_B_REG_DBG_DWORD_ENABLE \
 776         0x2a8404UL
 777 #define PGLUE_B_REG_DBG_SHIFT \
 778         0x2a8408UL
 779 #define PGLUE_B_REG_DBG_FORCE_VALID \
 780         0x2a840cUL
 781 #define PGLUE_B_REG_DBG_FORCE_FRAME \
 782         0x2a8410UL
 783 #define TM_REG_DBG_SELECT \
 784         0x2c07a8UL
 785 #define TM_REG_DBG_DWORD_ENABLE \
 786         0x2c07acUL
 787 #define TM_REG_DBG_SHIFT \
 788         0x2c07b0UL
 789 #define TM_REG_DBG_FORCE_VALID \
 790         0x2c07b4UL
 791 #define TM_REG_DBG_FORCE_FRAME \
 792         0x2c07b8UL
 793 #define TCFC_REG_DBG_SELECT \
 794         0x2d0500UL
 795 #define TCFC_REG_DBG_DWORD_ENABLE \
 796         0x2d0504UL
 797 #define TCFC_REG_DBG_SHIFT \
 798         0x2d0508UL
 799 #define TCFC_REG_DBG_FORCE_VALID \
 800         0x2d050cUL
 801 #define TCFC_REG_DBG_FORCE_FRAME \
 802         0x2d0510UL
 803 #define CCFC_REG_DBG_SELECT \
 804         0x2e0500UL
 805 #define CCFC_REG_DBG_DWORD_ENABLE \
 806         0x2e0504UL
 807 #define CCFC_REG_DBG_SHIFT \
 808         0x2e0508UL
 809 #define CCFC_REG_DBG_FORCE_VALID \
 810         0x2e050cUL
 811 #define CCFC_REG_DBG_FORCE_FRAME \
 812         0x2e0510UL
 813 #define QM_REG_DBG_SELECT \
 814         0x2f2e74UL
 815 #define QM_REG_DBG_DWORD_ENABLE \
 816         0x2f2e78UL
 817 #define QM_REG_DBG_SHIFT \
 818         0x2f2e7cUL
 819 #define QM_REG_DBG_FORCE_VALID \
 820         0x2f2e80UL
 821 #define QM_REG_DBG_FORCE_FRAME \
 822         0x2f2e84UL
 823 #define RDIF_REG_DBG_SELECT \
 824         0x300500UL
 825 #define RDIF_REG_DBG_DWORD_ENABLE \
 826         0x300504UL
 827 #define RDIF_REG_DBG_SHIFT \
 828         0x300508UL
 829 #define RDIF_REG_DBG_FORCE_VALID \
 830         0x30050cUL
 831 #define RDIF_REG_DBG_FORCE_FRAME \
 832         0x300510UL
 833 #define TDIF_REG_DBG_SELECT \
 834         0x310500UL
 835 #define TDIF_REG_DBG_DWORD_ENABLE \
 836         0x310504UL
 837 #define TDIF_REG_DBG_SHIFT \
 838         0x310508UL
 839 #define TDIF_REG_DBG_FORCE_VALID \
 840         0x31050cUL
 841 #define TDIF_REG_DBG_FORCE_FRAME \
 842         0x310510UL
 843 #define BRB_REG_DBG_SELECT \
 844         0x340ed0UL
 845 #define BRB_REG_DBG_DWORD_ENABLE \
 846         0x340ed4UL
 847 #define BRB_REG_DBG_SHIFT \
 848         0x340ed8UL
 849 #define BRB_REG_DBG_FORCE_VALID \
 850         0x340edcUL
 851 #define BRB_REG_DBG_FORCE_FRAME \
 852         0x340ee0UL
 853 #define XYLD_REG_DBG_SELECT \
 854         0x4c1600UL
 855 #define XYLD_REG_DBG_DWORD_ENABLE \
 856         0x4c1604UL
 857 #define XYLD_REG_DBG_SHIFT \
 858         0x4c1608UL
 859 #define XYLD_REG_DBG_FORCE_VALID \
 860         0x4c160cUL
 861 #define XYLD_REG_DBG_FORCE_FRAME \
 862         0x4c1610UL
 863 #define YULD_REG_DBG_SELECT \
 864         0x4c9600UL
 865 #define YULD_REG_DBG_DWORD_ENABLE \
 866         0x4c9604UL
 867 #define YULD_REG_DBG_SHIFT \
 868         0x4c9608UL
 869 #define YULD_REG_DBG_FORCE_VALID \
 870         0x4c960cUL
 871 #define YULD_REG_DBG_FORCE_FRAME \
 872         0x4c9610UL
 873 #define TMLD_REG_DBG_SELECT \
 874         0x4d1600UL
 875 #define TMLD_REG_DBG_DWORD_ENABLE \
 876         0x4d1604UL
 877 #define TMLD_REG_DBG_SHIFT \
 878         0x4d1608UL
 879 #define TMLD_REG_DBG_FORCE_VALID \
 880         0x4d160cUL
 881 #define TMLD_REG_DBG_FORCE_FRAME \
 882         0x4d1610UL
 883 #define MULD_REG_DBG_SELECT \
 884         0x4e1600UL
 885 #define MULD_REG_DBG_DWORD_ENABLE \
 886         0x4e1604UL
 887 #define MULD_REG_DBG_SHIFT \
 888         0x4e1608UL
 889 #define MULD_REG_DBG_FORCE_VALID \
 890         0x4e160cUL
 891 #define MULD_REG_DBG_FORCE_FRAME \
 892         0x4e1610UL
 893 #define NIG_REG_DBG_SELECT \
 894         0x502140UL
 895 #define NIG_REG_DBG_DWORD_ENABLE \
 896         0x502144UL
 897 #define NIG_REG_DBG_SHIFT \
 898         0x502148UL
 899 #define NIG_REG_DBG_FORCE_VALID \
 900         0x50214cUL
 901 #define NIG_REG_DBG_FORCE_FRAME \
 902         0x502150UL
 903 #define BMB_REG_DBG_SELECT \
 904         0x540a7cUL
 905 #define BMB_REG_DBG_DWORD_ENABLE \
 906         0x540a80UL
 907 #define BMB_REG_DBG_SHIFT \
 908         0x540a84UL
 909 #define BMB_REG_DBG_FORCE_VALID \
 910         0x540a88UL
 911 #define BMB_REG_DBG_FORCE_FRAME \
 912         0x540a8cUL
 913 #define PTU_REG_DBG_SELECT \
 914         0x560100UL
 915 #define PTU_REG_DBG_DWORD_ENABLE \
 916         0x560104UL
 917 #define PTU_REG_DBG_SHIFT \
 918         0x560108UL
 919 #define PTU_REG_DBG_FORCE_VALID \
 920         0x56010cUL
 921 #define PTU_REG_DBG_FORCE_FRAME \
 922         0x560110UL
 923 #define CDU_REG_DBG_SELECT \
 924         0x580704UL
 925 #define CDU_REG_DBG_DWORD_ENABLE \
 926         0x580708UL
 927 #define CDU_REG_DBG_SHIFT \
 928         0x58070cUL
 929 #define CDU_REG_DBG_FORCE_VALID \
 930         0x580710UL
 931 #define CDU_REG_DBG_FORCE_FRAME \
 932         0x580714UL
 933 #define WOL_REG_DBG_SELECT \
 934         0x600140UL
 935 #define WOL_REG_DBG_DWORD_ENABLE \
 936         0x600144UL
 937 #define WOL_REG_DBG_SHIFT \
 938         0x600148UL
 939 #define WOL_REG_DBG_FORCE_VALID \
 940         0x60014cUL
 941 #define WOL_REG_DBG_FORCE_FRAME \
 942         0x600150UL
 943 #define BMBN_REG_DBG_SELECT \
 944         0x610140UL
 945 #define BMBN_REG_DBG_DWORD_ENABLE \
 946         0x610144UL
 947 #define BMBN_REG_DBG_SHIFT \
 948         0x610148UL
 949 #define BMBN_REG_DBG_FORCE_VALID \
 950         0x61014cUL
 951 #define BMBN_REG_DBG_FORCE_FRAME \
 952         0x610150UL
 953 #define NWM_REG_DBG_SELECT \
 954         0x8000ecUL
 955 #define NWM_REG_DBG_DWORD_ENABLE \
 956         0x8000f0UL
 957 #define NWM_REG_DBG_SHIFT \
 958         0x8000f4UL
 959 #define NWM_REG_DBG_FORCE_VALID \
 960         0x8000f8UL
 961 #define NWM_REG_DBG_FORCE_FRAME \
 962         0x8000fcUL
 963 #define PBF_REG_DBG_SELECT \
 964         0xd80060UL
 965 #define PBF_REG_DBG_DWORD_ENABLE \
 966         0xd80064UL
 967 #define PBF_REG_DBG_SHIFT \
 968         0xd80068UL
 969 #define PBF_REG_DBG_FORCE_VALID \
 970         0xd8006cUL
 971 #define PBF_REG_DBG_FORCE_FRAME \
 972         0xd80070UL
 973 #define PBF_PB1_REG_DBG_SELECT \
 974         0xda0728UL
 975 #define PBF_PB1_REG_DBG_DWORD_ENABLE \
 976         0xda072cUL
 977 #define PBF_PB1_REG_DBG_SHIFT \
 978         0xda0730UL
 979 #define PBF_PB1_REG_DBG_FORCE_VALID \
 980         0xda0734UL
 981 #define PBF_PB1_REG_DBG_FORCE_FRAME \
 982         0xda0738UL
 983 #define PBF_PB2_REG_DBG_SELECT \
 984         0xda4728UL
 985 #define PBF_PB2_REG_DBG_DWORD_ENABLE \
 986         0xda472cUL
 987 #define PBF_PB2_REG_DBG_SHIFT \
 988         0xda4730UL
 989 #define PBF_PB2_REG_DBG_FORCE_VALID \
 990         0xda4734UL
 991 #define PBF_PB2_REG_DBG_FORCE_FRAME \
 992         0xda4738UL
 993 #define BTB_REG_DBG_SELECT \
 994         0xdb08c8UL
 995 #define BTB_REG_DBG_DWORD_ENABLE \
 996         0xdb08ccUL
 997 #define BTB_REG_DBG_SHIFT \
 998         0xdb08d0UL
 999 #define BTB_REG_DBG_FORCE_VALID \
1000         0xdb08d4UL
1001 #define BTB_REG_DBG_FORCE_FRAME \
1002         0xdb08d8UL
1003 #define XSDM_REG_DBG_SELECT \
1004         0xf80e28UL
1005 #define XSDM_REG_DBG_DWORD_ENABLE \
1006         0xf80e2cUL
1007 #define XSDM_REG_DBG_SHIFT \
1008         0xf80e30UL
1009 #define XSDM_REG_DBG_FORCE_VALID \
1010         0xf80e34UL
1011 #define XSDM_REG_DBG_FORCE_FRAME \
1012         0xf80e38UL
1013 #define YSDM_REG_DBG_SELECT \
1014         0xf90e28UL
1015 #define YSDM_REG_DBG_DWORD_ENABLE \
1016         0xf90e2cUL
1017 #define YSDM_REG_DBG_SHIFT \
1018         0xf90e30UL
1019 #define YSDM_REG_DBG_FORCE_VALID \
1020         0xf90e34UL
1021 #define YSDM_REG_DBG_FORCE_FRAME \
1022         0xf90e38UL
1023 #define PSDM_REG_DBG_SELECT \
1024         0xfa0e28UL
1025 #define PSDM_REG_DBG_DWORD_ENABLE \
1026         0xfa0e2cUL
1027 #define PSDM_REG_DBG_SHIFT \
1028         0xfa0e30UL
1029 #define PSDM_REG_DBG_FORCE_VALID \
1030         0xfa0e34UL
1031 #define PSDM_REG_DBG_FORCE_FRAME \
1032         0xfa0e38UL
1033 #define TSDM_REG_DBG_SELECT \
1034         0xfb0e28UL
1035 #define TSDM_REG_DBG_DWORD_ENABLE \
1036         0xfb0e2cUL
1037 #define TSDM_REG_DBG_SHIFT \
1038         0xfb0e30UL
1039 #define TSDM_REG_DBG_FORCE_VALID \
1040         0xfb0e34UL
1041 #define TSDM_REG_DBG_FORCE_FRAME \
1042         0xfb0e38UL
1043 #define MSDM_REG_DBG_SELECT \
1044         0xfc0e28UL
1045 #define MSDM_REG_DBG_DWORD_ENABLE \
1046         0xfc0e2cUL
1047 #define MSDM_REG_DBG_SHIFT \
1048         0xfc0e30UL
1049 #define MSDM_REG_DBG_FORCE_VALID \
1050         0xfc0e34UL
1051 #define MSDM_REG_DBG_FORCE_FRAME \
1052         0xfc0e38UL
1053 #define USDM_REG_DBG_SELECT \
1054         0xfd0e28UL
1055 #define USDM_REG_DBG_DWORD_ENABLE \
1056         0xfd0e2cUL
1057 #define USDM_REG_DBG_SHIFT \
1058         0xfd0e30UL
1059 #define USDM_REG_DBG_FORCE_VALID \
1060         0xfd0e34UL
1061 #define USDM_REG_DBG_FORCE_FRAME \
1062         0xfd0e38UL
1063 #define XCM_REG_DBG_SELECT \
1064         0x1000040UL
1065 #define XCM_REG_DBG_DWORD_ENABLE \
1066         0x1000044UL
1067 #define XCM_REG_DBG_SHIFT \
1068         0x1000048UL
1069 #define XCM_REG_DBG_FORCE_VALID \
1070         0x100004cUL
1071 #define XCM_REG_DBG_FORCE_FRAME \
1072         0x1000050UL
1073 #define YCM_REG_DBG_SELECT \
1074         0x1080040UL
1075 #define YCM_REG_DBG_DWORD_ENABLE \
1076         0x1080044UL
1077 #define YCM_REG_DBG_SHIFT \
1078         0x1080048UL
1079 #define YCM_REG_DBG_FORCE_VALID \
1080         0x108004cUL
1081 #define YCM_REG_DBG_FORCE_FRAME \
1082         0x1080050UL
1083 #define PCM_REG_DBG_SELECT \
1084         0x1100040UL
1085 #define PCM_REG_DBG_DWORD_ENABLE \
1086         0x1100044UL
1087 #define PCM_REG_DBG_SHIFT \
1088         0x1100048UL
1089 #define PCM_REG_DBG_FORCE_VALID \
1090         0x110004cUL
1091 #define PCM_REG_DBG_FORCE_FRAME \
1092         0x1100050UL
1093 #define TCM_REG_DBG_SELECT \
1094         0x1180040UL
1095 #define TCM_REG_DBG_DWORD_ENABLE \
1096         0x1180044UL
1097 #define TCM_REG_DBG_SHIFT \
1098         0x1180048UL
1099 #define TCM_REG_DBG_FORCE_VALID \
1100         0x118004cUL
1101 #define TCM_REG_DBG_FORCE_FRAME \
1102         0x1180050UL
1103 #define MCM_REG_DBG_SELECT \
1104         0x1200040UL
1105 #define MCM_REG_DBG_DWORD_ENABLE \
1106         0x1200044UL
1107 #define MCM_REG_DBG_SHIFT \
1108         0x1200048UL
1109 #define MCM_REG_DBG_FORCE_VALID \
1110         0x120004cUL
1111 #define MCM_REG_DBG_FORCE_FRAME \
1112         0x1200050UL
1113 #define UCM_REG_DBG_SELECT \
1114         0x1280050UL
1115 #define UCM_REG_DBG_DWORD_ENABLE \
1116         0x1280054UL
1117 #define UCM_REG_DBG_SHIFT \
1118         0x1280058UL
1119 #define UCM_REG_DBG_FORCE_VALID \
1120         0x128005cUL
1121 #define UCM_REG_DBG_FORCE_FRAME \
1122         0x1280060UL
1123 #define XSEM_REG_DBG_SELECT \
1124         0x1401528UL
1125 #define XSEM_REG_DBG_DWORD_ENABLE \
1126         0x140152cUL
1127 #define XSEM_REG_DBG_SHIFT \
1128         0x1401530UL
1129 #define XSEM_REG_DBG_FORCE_VALID \
1130         0x1401534UL
1131 #define XSEM_REG_DBG_FORCE_FRAME \
1132         0x1401538UL
1133 #define YSEM_REG_DBG_SELECT \
1134         0x1501528UL
1135 #define YSEM_REG_DBG_DWORD_ENABLE \
1136         0x150152cUL
1137 #define YSEM_REG_DBG_SHIFT \
1138         0x1501530UL
1139 #define YSEM_REG_DBG_FORCE_VALID \
1140         0x1501534UL
1141 #define YSEM_REG_DBG_FORCE_FRAME \
1142         0x1501538UL
1143 #define PSEM_REG_DBG_SELECT \
1144         0x1601528UL
1145 #define PSEM_REG_DBG_DWORD_ENABLE \
1146         0x160152cUL
1147 #define PSEM_REG_DBG_SHIFT \
1148         0x1601530UL
1149 #define PSEM_REG_DBG_FORCE_VALID \
1150         0x1601534UL
1151 #define PSEM_REG_DBG_FORCE_FRAME \
1152         0x1601538UL
1153 #define TSEM_REG_DBG_SELECT \
1154         0x1701528UL
1155 #define TSEM_REG_DBG_DWORD_ENABLE \
1156         0x170152cUL
1157 #define TSEM_REG_DBG_SHIFT \
1158         0x1701530UL
1159 #define TSEM_REG_DBG_FORCE_VALID \
1160         0x1701534UL
1161 #define TSEM_REG_DBG_FORCE_FRAME \
1162         0x1701538UL
1163 #define MSEM_REG_DBG_SELECT \
1164         0x1801528UL
1165 #define MSEM_REG_DBG_DWORD_ENABLE \
1166         0x180152cUL
1167 #define MSEM_REG_DBG_SHIFT \
1168         0x1801530UL
1169 #define MSEM_REG_DBG_FORCE_VALID \
1170         0x1801534UL
1171 #define MSEM_REG_DBG_FORCE_FRAME \
1172         0x1801538UL
1173 #define USEM_REG_DBG_SELECT \
1174         0x1901528UL
1175 #define USEM_REG_DBG_DWORD_ENABLE \
1176         0x190152cUL
1177 #define USEM_REG_DBG_SHIFT \
1178         0x1901530UL
1179 #define USEM_REG_DBG_FORCE_VALID \
1180         0x1901534UL
1181 #define USEM_REG_DBG_FORCE_FRAME \
1182         0x1901538UL
1183 #define PCIE_REG_DBG_COMMON_SELECT \
1184         0x054398UL
1185 #define PCIE_REG_DBG_COMMON_DWORD_ENABLE \
1186         0x05439cUL
1187 #define PCIE_REG_DBG_COMMON_SHIFT \
1188         0x0543a0UL
1189 #define PCIE_REG_DBG_COMMON_FORCE_VALID \
1190         0x0543a4UL
1191 #define PCIE_REG_DBG_COMMON_FORCE_FRAME \
1192         0x0543a8UL
1193 #define MISC_REG_RESET_PL_UA \
1194         0x008050UL
1195 #define MISC_REG_RESET_PL_HV \
1196         0x008060UL
1197 #define XCM_REG_CTX_RBC_ACCS \
1198         0x1001800UL
1199 #define XCM_REG_AGG_CON_CTX \
1200         0x1001804UL
1201 #define XCM_REG_SM_CON_CTX \
1202         0x1001808UL
1203 #define YCM_REG_CTX_RBC_ACCS \
1204         0x1081800UL
1205 #define YCM_REG_AGG_CON_CTX \
1206         0x1081804UL
1207 #define YCM_REG_AGG_TASK_CTX \
1208         0x1081808UL
1209 #define YCM_REG_SM_CON_CTX \
1210         0x108180cUL
1211 #define YCM_REG_SM_TASK_CTX \
1212         0x1081810UL
1213 #define PCM_REG_CTX_RBC_ACCS \
1214         0x1101440UL
1215 #define PCM_REG_SM_CON_CTX \
1216         0x1101444UL
1217 #define TCM_REG_CTX_RBC_ACCS \
1218         0x11814c0UL
1219 #define TCM_REG_AGG_CON_CTX \
1220         0x11814c4UL
1221 #define TCM_REG_AGG_TASK_CTX \
1222         0x11814c8UL
1223 #define TCM_REG_SM_CON_CTX \
1224         0x11814ccUL
1225 #define TCM_REG_SM_TASK_CTX \
1226         0x11814d0UL
1227 #define MCM_REG_CTX_RBC_ACCS \
1228         0x1201800UL
1229 #define MCM_REG_AGG_CON_CTX \
1230         0x1201804UL
1231 #define MCM_REG_AGG_TASK_CTX \
1232         0x1201808UL
1233 #define MCM_REG_SM_CON_CTX \
1234         0x120180cUL
1235 #define MCM_REG_SM_TASK_CTX \
1236         0x1201810UL
1237 #define UCM_REG_CTX_RBC_ACCS \
1238         0x1281700UL
1239 #define UCM_REG_AGG_CON_CTX \
1240         0x1281704UL
1241 #define UCM_REG_AGG_TASK_CTX \
1242         0x1281708UL
1243 #define UCM_REG_SM_CON_CTX \
1244         0x128170cUL
1245 #define UCM_REG_SM_TASK_CTX \
1246         0x1281710UL
1247 #define XSEM_REG_SLOW_DBG_EMPTY \
1248         0x1401140UL
1249 #define XSEM_REG_SYNC_DBG_EMPTY \
1250         0x1401160UL
1251 #define XSEM_REG_SLOW_DBG_ACTIVE \
1252         0x1401400UL
1253 #define XSEM_REG_SLOW_DBG_MODE \
1254         0x1401404UL
1255 #define XSEM_REG_DBG_FRAME_MODE \
1256         0x1401408UL
1257 #define XSEM_REG_DBG_MODE1_CFG \
1258         0x1401420UL
1259 #define XSEM_REG_FAST_MEMORY \
1260         0x1440000UL
1261 #define YSEM_REG_SYNC_DBG_EMPTY \
1262         0x1501160UL
1263 #define YSEM_REG_SLOW_DBG_ACTIVE \
1264         0x1501400UL
1265 #define YSEM_REG_SLOW_DBG_MODE \
1266         0x1501404UL
1267 #define YSEM_REG_DBG_FRAME_MODE \
1268         0x1501408UL
1269 #define YSEM_REG_DBG_MODE1_CFG \
1270         0x1501420UL
1271 #define YSEM_REG_FAST_MEMORY \
1272         0x1540000UL
1273 #define PSEM_REG_SLOW_DBG_EMPTY \
1274         0x1601140UL
1275 #define PSEM_REG_SYNC_DBG_EMPTY \
1276         0x1601160UL
1277 #define PSEM_REG_SLOW_DBG_ACTIVE \
1278         0x1601400UL
1279 #define PSEM_REG_SLOW_DBG_MODE \
1280         0x1601404UL
1281 #define PSEM_REG_DBG_FRAME_MODE \
1282         0x1601408UL
1283 #define PSEM_REG_DBG_MODE1_CFG \
1284         0x1601420UL
1285 #define PSEM_REG_FAST_MEMORY \
1286         0x1640000UL
1287 #define TSEM_REG_SLOW_DBG_EMPTY \
1288         0x1701140UL
1289 #define TSEM_REG_SYNC_DBG_EMPTY \
1290         0x1701160UL
1291 #define TSEM_REG_SLOW_DBG_ACTIVE \
1292         0x1701400UL
1293 #define TSEM_REG_SLOW_DBG_MODE \
1294         0x1701404UL
1295 #define TSEM_REG_DBG_FRAME_MODE \
1296         0x1701408UL
1297 #define TSEM_REG_DBG_MODE1_CFG \
1298         0x1701420UL
1299 #define TSEM_REG_FAST_MEMORY \
1300         0x1740000UL
1301 #define MSEM_REG_SLOW_DBG_EMPTY \
1302         0x1801140UL
1303 #define MSEM_REG_SYNC_DBG_EMPTY \
1304         0x1801160UL
1305 #define MSEM_REG_SLOW_DBG_ACTIVE \
1306         0x1801400UL
1307 #define MSEM_REG_SLOW_DBG_MODE \
1308         0x1801404UL
1309 #define MSEM_REG_DBG_FRAME_MODE \
1310         0x1801408UL
1311 #define MSEM_REG_DBG_MODE1_CFG \
1312         0x1801420UL
1313 #define MSEM_REG_FAST_MEMORY \
1314         0x1840000UL
1315 #define USEM_REG_SLOW_DBG_EMPTY \
1316         0x1901140UL
1317 #define USEM_REG_SYNC_DBG_EMPTY \
1318         0x1901160UL
1319 #define USEM_REG_SLOW_DBG_ACTIVE \
1320         0x1901400UL
1321 #define USEM_REG_SLOW_DBG_MODE \
1322         0x1901404UL
1323 #define USEM_REG_DBG_FRAME_MODE \
1324         0x1901408UL
1325 #define USEM_REG_DBG_MODE1_CFG \
1326         0x1901420UL
1327 #define USEM_REG_FAST_MEMORY \
1328         0x1940000UL
1329 #define SEM_FAST_REG_INT_RAM \
1330         0x020000UL
1331 #define SEM_FAST_REG_INT_RAM_SIZE \
1332         20480
1333 #define GRC_REG_TRACE_FIFO_VALID_DATA \
1334         0x050064UL
1335 #define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \
1336         0x05040cUL
1337 #define GRC_REG_PROTECTION_OVERRIDE_WINDOW \
1338         0x050500UL
1339 #define IGU_REG_ERROR_HANDLING_MEMORY \
1340         0x181520UL
1341 #define MCP_REG_CPU_MODE \
1342         0xe05000UL
1343 #define MCP_REG_CPU_MODE_SOFT_HALT \
1344                 (0x1 << 10)
1345 #define BRB_REG_BIG_RAM_ADDRESS \
1346         0x340800UL
1347 #define BRB_REG_BIG_RAM_DATA \
1348         0x341500UL
1349 #define SEM_FAST_REG_STALL_0 \
1350         0x000488UL
1351 #define SEM_FAST_REG_STALLED \
1352         0x000494UL
1353 #define BTB_REG_BIG_RAM_ADDRESS \
1354         0xdb0800UL
1355 #define BTB_REG_BIG_RAM_DATA \
1356         0xdb0c00UL
1357 #define BMB_REG_BIG_RAM_ADDRESS \
1358         0x540800UL
1359 #define BMB_REG_BIG_RAM_DATA \
1360         0x540f00UL
1361 #define SEM_FAST_REG_STORM_REG_FILE \
1362         0x008000UL
1363 #define RSS_REG_RSS_RAM_ADDR \
1364         0x238c30UL
1365 #define MISCS_REG_BLOCK_256B_EN \
1366         0x009074UL
1367 #define MCP_REG_SCRATCH_SIZE \
1368         57344
1369 #define MCP_REG_CPU_REG_FILE \
1370         0xe05200UL
1371 #define MCP_REG_CPU_REG_FILE_SIZE \
1372         32
1373 #define DBG_REG_DEBUG_TARGET \
1374         0x01005cUL
1375 #define DBG_REG_FULL_MODE \
1376         0x010060UL
1377 #define DBG_REG_CALENDAR_OUT_DATA \
1378         0x010480UL
1379 #define GRC_REG_TRACE_FIFO \
1380         0x050068UL
1381 #define IGU_REG_ERROR_HANDLING_DATA_VALID \
1382         0x181530UL
1383 #define DBG_REG_DBG_BLOCK_ON \
1384         0x010454UL
1385 #define DBG_REG_FRAMING_MODE \
1386         0x010058UL
1387 #define SEM_FAST_REG_VFC_DATA_WR \
1388         0x000b40UL
1389 #define SEM_FAST_REG_VFC_ADDR \
1390         0x000b44UL
1391 #define SEM_FAST_REG_VFC_DATA_RD \
1392         0x000b48UL
1393 #define RSS_REG_RSS_RAM_DATA \
1394         0x238c20UL
1395 #define MISC_REG_BLOCK_256B_EN \
1396         0x008c14UL
1397 #define NWS_REG_NWS_CMU \
1398         0x720000UL
1399 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0 \
1400         0x000680UL
1401 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8 \
1402         0x000684UL
1403 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0 \
1404         0x0006c0UL
1405 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8 \
1406         0x0006c4UL
1407 #define MS_REG_MS_CMU \
1408         0x6a4000UL
1409 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130 \
1410         0x000208UL
1411 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132 \
1412         0x000210UL
1413 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131 \
1414         0x00020cUL
1415 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133 \
1416         0x000214UL
1417 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130 \
1418         0x000208UL
1419 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131 \
1420         0x00020cUL
1421 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132 \
1422         0x000210UL
1423 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133 \
1424         0x000214UL
1425 #define PHY_PCIE_REG_PHY0 \
1426         0x620000UL
1427 #define PHY_PCIE_REG_PHY1 \
1428         0x624000UL
1429
1430 #endif