drivers/net/ethernet/qlogic/qed/qed_reg_addr.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #ifndef REG_ADDR_H
  10 #define REG_ADDR_H
  11
  12 #define  CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
  13         0
  14
  15 #define  CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE           ( \
  16                 0xfff << 0)
  17
  18 #define  CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \
  19         12
  20
  21 #define  CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE            ( \
  22                 0xfff << 12)
  23
  24 #define  CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \
  25         24
  26
  27 #define  CDU_REG_CID_ADDR_PARAMS_NCIB                   ( \
  28                 0xff << 24)
  29
  30 #define CDU_REG_SEGMENT0_PARAMS \
  31         0x580904UL
  32 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \
  33         (0xfff << 0)
  34 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \
  35         0
  36 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \
  37         (0xff << 16)
  38 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \
  39         16
  40 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \
  41         (0xff << 24)
  42 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \
  43         24
  44 #define CDU_REG_SEGMENT1_PARAMS \
  45         0x580908UL
  46 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \
  47         (0xfff << 0)
  48 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \
  49         0
  50 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \
  51         (0xff << 16)
  52 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \
  53         16
  54 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \
  55         (0xff << 24)
  56 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \
  57         24
  58
  59 #define  XSDM_REG_OPERATION_GEN \
  60         0xf80408UL
  61 #define  NIG_REG_RX_BRB_OUT_EN \
  62         0x500e18UL
  63 #define  NIG_REG_STORM_OUT_EN \
  64         0x500e08UL
  65 #define  PSWRQ2_REG_L2P_VALIDATE_VFID \
  66         0x240c50UL
  67 #define  PGLUE_B_REG_USE_CLIENTID_IN_TAG        \
  68         0x2aae04UL
  69 #define  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER        \
  70         0x2aa16cUL
  71 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
  72         0x2aa118UL
  73 #define PSWHST_REG_ZONE_PERMISSION_TABLE \
  74         0x2a0800UL
  75 #define  BAR0_MAP_REG_MSDM_RAM \
  76         0x1d00000UL
  77 #define  BAR0_MAP_REG_USDM_RAM \
  78         0x1d80000UL
  79 #define  BAR0_MAP_REG_PSDM_RAM \
  80         0x1f00000UL
  81 #define  BAR0_MAP_REG_TSDM_RAM \
  82         0x1c80000UL
  83 #define BAR0_MAP_REG_XSDM_RAM \
  84         0x1e00000UL
  85 #define  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
  86         0x5011f4UL
  87 #define  PRS_REG_SEARCH_TCP \
  88         0x1f0400UL
  89 #define  PRS_REG_SEARCH_UDP \
  90         0x1f0404UL
  91 #define  PRS_REG_SEARCH_FCOE \
  92         0x1f0408UL
  93 #define  PRS_REG_SEARCH_ROCE \
  94         0x1f040cUL
  95 #define  PRS_REG_SEARCH_OPENFLOW        \
  96         0x1f0434UL
  97 #define  TM_REG_PF_ENABLE_CONN \
  98         0x2c043cUL
  99 #define  TM_REG_PF_ENABLE_TASK \
 100         0x2c0444UL
 101 #define  TM_REG_PF_SCAN_ACTIVE_CONN \
 102         0x2c04fcUL
 103 #define  TM_REG_PF_SCAN_ACTIVE_TASK \
 104         0x2c0500UL
 105 #define  IGU_REG_LEADING_EDGE_LATCH \
 106         0x18082cUL
 107 #define  IGU_REG_TRAILING_EDGE_LATCH \
 108         0x180830UL
 109 #define  QM_REG_USG_CNT_PF_TX \
 110         0x2f2eacUL
 111 #define  QM_REG_USG_CNT_PF_OTHER        \
 112         0x2f2eb0UL
 113 #define  DORQ_REG_PF_DB_ENABLE \
 114         0x100508UL
 115 #define DORQ_REG_VF_USAGE_CNT \
 116         0x1009c4UL
 117 #define  QM_REG_PF_EN \
 118         0x2f2ea4UL
 119 #define  TCFC_REG_STRONG_ENABLE_PF \
 120         0x2d0708UL
 121 #define  CCFC_REG_STRONG_ENABLE_PF \
 122         0x2e0708UL
 123 #define  PGLUE_B_REG_PGL_ADDR_88_F0 \
 124         0x2aa404UL
 125 #define  PGLUE_B_REG_PGL_ADDR_8C_F0 \
 126         0x2aa408UL
 127 #define  PGLUE_B_REG_PGL_ADDR_90_F0 \
 128         0x2aa40cUL
 129 #define  PGLUE_B_REG_PGL_ADDR_94_F0 \
 130         0x2aa410UL
 131 #define  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \
 132         0x2aa138UL
 133 #define  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
 134         0x2aa174UL
 135 #define  MISC_REG_GEN_PURP_CR0 \
 136         0x008c80UL
 137 #define  MCP_REG_SCRATCH        \
 138         0xe20000UL
 139 #define  CNIG_REG_NW_PORT_MODE_BB_B0 \
 140         0x218200UL
 141 #define  MISCS_REG_CHIP_NUM \
 142         0x00976cUL
 143 #define  MISCS_REG_CHIP_REV \
 144         0x009770UL
 145 #define  MISCS_REG_CMT_ENABLED_FOR_PAIR \
 146         0x00971cUL
 147 #define  MISCS_REG_CHIP_TEST_REG        \
 148         0x009778UL
 149 #define  MISCS_REG_CHIP_METAL \
 150         0x009774UL
 151 #define MISCS_REG_FUNCTION_HIDE \
 152         0x0096f0UL
 153 #define  BRB_REG_HEADER_SIZE \
 154         0x340804UL
 155 #define  BTB_REG_HEADER_SIZE \
 156         0xdb0804UL
 157 #define  CAU_REG_LONG_TIMEOUT_THRESHOLD \
 158         0x1c0708UL
 159 #define  CCFC_REG_ACTIVITY_COUNTER \
 160         0x2e8800UL
 161 #define CCFC_REG_STRONG_ENABLE_VF \
 162         0x2e070cUL
 163 #define  CDU_REG_CID_ADDR_PARAMS        \
 164         0x580900UL
 165 #define  DBG_REG_CLIENT_ENABLE \
 166         0x010004UL
 167 #define  DMAE_REG_INIT \
 168         0x00c000UL
 169 #define  DORQ_REG_IFEN \
 170         0x100040UL
 171 #define DORQ_REG_DB_DROP_REASON \
 172         0x100a2cUL
 173 #define DORQ_REG_DB_DROP_DETAILS \
 174         0x100a24UL
 175 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS \
 176         0x100a1cUL
 177 #define  GRC_REG_TIMEOUT_EN \
 178         0x050404UL
 179 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \
 180         0x050054UL
 181 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \
 182         0x05004cUL
 183 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \
 184         0x050050UL
 185 #define  IGU_REG_BLOCK_CONFIGURATION \
 186         0x180040UL
 187 #define  MCM_REG_INIT \
 188         0x1200000UL
 189 #define  MCP2_REG_DBG_DWORD_ENABLE \
 190         0x052404UL
 191 #define  MISC_REG_PORT_MODE \
 192         0x008c00UL
 193 #define  MISCS_REG_CLK_100G_MODE        \
 194         0x009070UL
 195 #define  MSDM_REG_ENABLE_IN1 \
 196         0xfc0004UL
 197 #define  MSEM_REG_ENABLE_IN \
 198         0x1800004UL
 199 #define  NIG_REG_CM_HDR \
 200         0x500840UL
 201 #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \
 202         0x50196cUL
 203 #define NIG_REG_LLH_CLS_TYPE_DUALMODE \
 204         0x501964UL
 205 #define  NCSI_REG_CONFIG        \
 206         0x040200UL
 207 #define  PBF_REG_INIT \
 208         0xd80000UL
 209 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \
 210         0xd806c8UL
 211 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \
 212         0xd806ccUL
 213 #define  PTU_REG_ATC_INIT_ARRAY \
 214         0x560000UL
 215 #define  PCM_REG_INIT \
 216         0x1100000UL
 217 #define  PGLUE_B_REG_ADMIN_PER_PF_REGION        \
 218         0x2a9000UL
 219 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \
 220         0x2aa150UL
 221 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \
 222         0x2aa144UL
 223 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \
 224         0x2aa148UL
 225 #define PGLUE_B_REG_TX_ERR_WR_DETAILS \
 226         0x2aa14cUL
 227 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \
 228         0x2aa154UL
 229 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \
 230         0x2aa158UL
 231 #define PGLUE_B_REG_TX_ERR_RD_DETAILS \
 232         0x2aa15cUL
 233 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \
 234         0x2aa160UL
 235 #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \
 236         0x2aa164UL
 237 #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \
 238         0x2aa54cUL
 239 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \
 240         0x2aa544UL
 241 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \
 242         0x2aa548UL
 243 #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \
 244         0x2aae74UL
 245 #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \
 246         0x2aae78UL
 247 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS \
 248         0x2aae7cUL
 249 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \
 250         0x2aae80UL
 251 #define PGLUE_B_REG_LATCHED_ERRORS_CLR \
 252         0x2aa3bcUL
 253 #define  PRM_REG_DISABLE_PRM \
 254         0x230000UL
 255 #define  PRS_REG_SOFT_RST \
 256         0x1f0000UL
 257 #define PRS_REG_MSG_INFO \
 258         0x1f0a1cUL
 259 #define PRS_REG_ROCE_DEST_QP_MAX_PF \
 260         0x1f0430UL
 261 #define  PSDM_REG_ENABLE_IN1 \
 262         0xfa0004UL
 263 #define  PSEM_REG_ENABLE_IN \
 264         0x1600004UL
 265 #define  PSWRQ_REG_DBG_SELECT \
 266         0x280020UL
 267 #define  PSWRQ2_REG_CDUT_P_SIZE \
 268         0x24000cUL
 269 #define PSWRQ2_REG_ILT_MEMORY \
 270         0x260000UL
 271 #define  PSWHST_REG_DISCARD_INTERNAL_WRITES \
 272         0x2a0040UL
 273 #define  PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
 274         0x29e050UL
 275 #define PSWHST_REG_INCORRECT_ACCESS_VALID \
 276         0x2a0070UL
 277 #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \
 278         0x2a0074UL
 279 #define PSWHST_REG_INCORRECT_ACCESS_DATA \
 280         0x2a0068UL
 281 #define PSWHST_REG_INCORRECT_ACCESS_LENGTH \
 282         0x2a006cUL
 283 #define  PSWRD_REG_DBG_SELECT \
 284         0x29c040UL
 285 #define  PSWRD2_REG_CONF11 \
 286         0x29d064UL
 287 #define  PSWWR_REG_USDM_FULL_TH \
 288         0x29a040UL
 289 #define  PSWWR2_REG_CDU_FULL_TH2        \
 290         0x29b040UL
 291 #define  QM_REG_MAXPQSIZE_0 \
 292         0x2f0434UL
 293 #define  RSS_REG_RSS_INIT_EN \
 294         0x238804UL
 295 #define  RDIF_REG_STOP_ON_ERROR \
 296         0x300040UL
 297 #define  SRC_REG_SOFT_RST \
 298         0x23874cUL
 299 #define  TCFC_REG_ACTIVITY_COUNTER \
 300         0x2d8800UL
 301 #define  TCM_REG_INIT \
 302         0x1180000UL
 303 #define  TM_REG_PXP_READ_DATA_FIFO_INIT \
 304         0x2c0014UL
 305 #define  TSDM_REG_ENABLE_IN1 \
 306         0xfb0004UL
 307 #define  TSEM_REG_ENABLE_IN \
 308         0x1700004UL
 309 #define  TDIF_REG_STOP_ON_ERROR \
 310         0x310040UL
 311 #define  UCM_REG_INIT \
 312         0x1280000UL
 313 #define  UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \
 314         0x051004UL
 315 #define  USDM_REG_ENABLE_IN1 \
 316         0xfd0004UL
 317 #define  USEM_REG_ENABLE_IN \
 318         0x1900004UL
 319 #define  XCM_REG_INIT \
 320         0x1000000UL
 321 #define  XSDM_REG_ENABLE_IN1 \
 322         0xf80004UL
 323 #define  XSEM_REG_ENABLE_IN \
 324         0x1400004UL
 325 #define  YCM_REG_INIT \
 326         0x1080000UL
 327 #define  YSDM_REG_ENABLE_IN1 \
 328         0xf90004UL
 329 #define  YSEM_REG_ENABLE_IN \
 330         0x1500004UL
 331 #define  XYLD_REG_SCBD_STRICT_PRIO \
 332         0x4c0000UL
 333 #define  TMLD_REG_SCBD_STRICT_PRIO \
 334         0x4d0000UL
 335 #define  MULD_REG_SCBD_STRICT_PRIO \
 336         0x4e0000UL
 337 #define  YULD_REG_SCBD_STRICT_PRIO \
 338         0x4c8000UL
 339 #define  MISC_REG_SHARED_MEM_ADDR \
 340         0x008c20UL
 341 #define  DMAE_REG_GO_C0 \
 342         0x00c048UL
 343 #define  DMAE_REG_GO_C1 \
 344         0x00c04cUL
 345 #define  DMAE_REG_GO_C2 \
 346         0x00c050UL
 347 #define  DMAE_REG_GO_C3 \
 348         0x00c054UL
 349 #define  DMAE_REG_GO_C4 \
 350         0x00c058UL
 351 #define  DMAE_REG_GO_C5 \
 352         0x00c05cUL
 353 #define  DMAE_REG_GO_C6 \
 354         0x00c060UL
 355 #define  DMAE_REG_GO_C7 \
 356         0x00c064UL
 357 #define  DMAE_REG_GO_C8 \
 358         0x00c068UL
 359 #define  DMAE_REG_GO_C9 \
 360         0x00c06cUL
 361 #define  DMAE_REG_GO_C10        \
 362         0x00c070UL
 363 #define  DMAE_REG_GO_C11        \
 364         0x00c074UL
 365 #define  DMAE_REG_GO_C12        \
 366         0x00c078UL
 367 #define  DMAE_REG_GO_C13        \
 368         0x00c07cUL
 369 #define  DMAE_REG_GO_C14        \
 370         0x00c080UL
 371 #define  DMAE_REG_GO_C15        \
 372         0x00c084UL
 373 #define  DMAE_REG_GO_C16        \
 374         0x00c088UL
 375 #define  DMAE_REG_GO_C17        \
 376         0x00c08cUL
 377 #define  DMAE_REG_GO_C18        \
 378         0x00c090UL
 379 #define  DMAE_REG_GO_C19        \
 380         0x00c094UL
 381 #define  DMAE_REG_GO_C20        \
 382         0x00c098UL
 383 #define  DMAE_REG_GO_C21        \
 384         0x00c09cUL
 385 #define  DMAE_REG_GO_C22        \
 386         0x00c0a0UL
 387 #define  DMAE_REG_GO_C23        \
 388         0x00c0a4UL
 389 #define  DMAE_REG_GO_C24        \
 390         0x00c0a8UL
 391 #define  DMAE_REG_GO_C25        \
 392         0x00c0acUL
 393 #define  DMAE_REG_GO_C26        \
 394         0x00c0b0UL
 395 #define  DMAE_REG_GO_C27        \
 396         0x00c0b4UL
 397 #define  DMAE_REG_GO_C28        \
 398         0x00c0b8UL
 399 #define  DMAE_REG_GO_C29        \
 400         0x00c0bcUL
 401 #define  DMAE_REG_GO_C30        \
 402         0x00c0c0UL
 403 #define  DMAE_REG_GO_C31        \
 404         0x00c0c4UL
 405 #define  DMAE_REG_CMD_MEM \
 406         0x00c800UL
 407 #define  QM_REG_MAXPQSIZETXSEL_0        \
 408         0x2f0440UL
 409 #define  QM_REG_SDMCMDREADY \
 410         0x2f1e10UL
 411 #define  QM_REG_SDMCMDADDR \
 412         0x2f1e04UL
 413 #define  QM_REG_SDMCMDDATALSB \
 414         0x2f1e08UL
 415 #define  QM_REG_SDMCMDDATAMSB \
 416         0x2f1e0cUL
 417 #define  QM_REG_SDMCMDGO        \
 418         0x2f1e14UL
 419 #define  QM_REG_RLPFCRD \
 420         0x2f4d80UL
 421 #define  QM_REG_RLPFINCVAL \
 422         0x2f4c80UL
 423 #define  QM_REG_RLGLBLCRD \
 424         0x2f4400UL
 425 #define  QM_REG_RLGLBLINCVAL \
 426         0x2f3400UL
 427 #define  IGU_REG_ATTENTION_ENABLE \
 428         0x18083cUL
 429 #define  IGU_REG_ATTN_MSG_ADDR_L        \
 430         0x180820UL
 431 #define  IGU_REG_ATTN_MSG_ADDR_H        \
 432         0x180824UL
 433 #define  MISC_REG_AEU_GENERAL_ATTN_0 \
 434         0x008400UL
 435 #define  CAU_REG_SB_ADDR_MEMORY \
 436         0x1c8000UL
 437 #define  CAU_REG_SB_VAR_MEMORY \
 438         0x1c6000UL
 439 #define  CAU_REG_PI_MEMORY \
 440         0x1d0000UL
 441 #define  IGU_REG_PF_CONFIGURATION \
 442         0x180800UL
 443 #define IGU_REG_VF_CONFIGURATION \
 444         0x180804UL
 445 #define  MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
 446         0x00849cUL
 447 #define MISC_REG_AEU_AFTER_INVERT_1_IGU \
 448         0x0087b4UL
 449 #define  MISC_REG_AEU_MASK_ATTN_IGU \
 450         0x008494UL
 451 #define  IGU_REG_CLEANUP_STATUS_0 \
 452         0x180980UL
 453 #define  IGU_REG_CLEANUP_STATUS_1 \
 454         0x180a00UL
 455 #define  IGU_REG_CLEANUP_STATUS_2 \
 456         0x180a80UL
 457 #define  IGU_REG_CLEANUP_STATUS_3 \
 458         0x180b00UL
 459 #define  IGU_REG_CLEANUP_STATUS_4 \
 460         0x180b80UL
 461 #define  IGU_REG_COMMAND_REG_32LSB_DATA \
 462         0x180840UL
 463 #define  IGU_REG_COMMAND_REG_CTRL \
 464         0x180848UL
 465 #define  IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN      ( \
 466                 0x1 << 1)
 467 #define  IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN       ( \
 468                 0x1 << 0)
 469 #define  IGU_REG_MAPPING_MEMORY \
 470         0x184000UL
 471 #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \
 472         0x180408UL
 473 #define IGU_REG_WRITE_DONE_PENDING \
 474         0x180900UL
 475 #define  MISCS_REG_GENERIC_POR_0        \
 476         0x0096d4UL
 477 #define  MCP_REG_NVM_CFG4 \
 478         0xe0642cUL
 479 #define  MCP_REG_NVM_CFG4_FLASH_SIZE    ( \
 480                 0x7 << 0)
 481 #define  MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \
 482         0
 483 #define MCP_REG_CPU_STATE \
 484         0xe05004UL
 485 #define MCP_REG_CPU_EVENT_MASK \
 486         0xe05008UL
 487 #define PGLUE_B_REG_PF_BAR0_SIZE \
 488         0x2aae60UL
 489 #define PGLUE_B_REG_PF_BAR1_SIZE \
 490         0x2aae64UL
 491 #define PRS_REG_ENCAPSULATION_TYPE_EN   0x1f0730UL
 492 #define PRS_REG_GRE_PROTOCOL            0x1f0734UL
 493 #define PRS_REG_VXLAN_PORT              0x1f0738UL
 494 #define PRS_REG_OUTPUT_FORMAT_4_0       0x1f099cUL
 495 #define NIG_REG_ENC_TYPE_ENABLE         0x501058UL
 496
 497 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE             (0x1 << 0)
 498 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT       0
 499 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE              (0x1 << 1)
 500 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT        1
 501 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE                    (0x1 << 2)
 502 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT              2
 503
 504 #define NIG_REG_VXLAN_CTRL              0x50105cUL
 505 #define PBF_REG_VXLAN_PORT              0xd80518UL
 506 #define PBF_REG_NGE_PORT                0xd8051cUL
 507 #define PRS_REG_NGE_PORT                0x1f086cUL
 508 #define NIG_REG_NGE_PORT                0x508b38UL
 509
 510 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN      0x10090cUL
 511 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN       0x100910UL
 512 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN        0x100914UL
 513 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN       0x10092cUL
 514 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN      0x100930UL
 515
 516 #define NIG_REG_NGE_IP_ENABLE                   0x508b28UL
 517 #define NIG_REG_NGE_ETH_ENABLE                  0x508b2cUL
 518 #define NIG_REG_NGE_COMP_VER                    0x508b30UL
 519 #define PBF_REG_NGE_COMP_VER                    0xd80524UL
 520 #define PRS_REG_NGE_COMP_VER                    0x1f0878UL
 521
 522 #define QM_REG_WFQPFWEIGHT      0x2f4e80UL
 523 #define QM_REG_WFQVPWEIGHT      0x2fa000UL
 524 #endif