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Merge remote-tracking branch 'mkp-scsi/4.8/scsi-fixes' into fixes
[deliverable/linux.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic.h
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #ifndef _QLCNIC_H_
9 #define _QLCNIC_H_
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ip.h>
19 #include <linux/in.h>
20 #include <linux/tcp.h>
21 #include <linux/skbuff.h>
22 #include <linux/firmware.h>
23 #include <linux/ethtool.h>
24 #include <linux/mii.h>
25 #include <linux/timer.h>
26 #include <linux/irq.h>
27 #include <linux/vmalloc.h>
28 #include <linux/io.h>
29 #include <asm/byteorder.h>
30 #include <linux/bitops.h>
31 #include <linux/if_vlan.h>
32
33 #include "qlcnic_hdr.h"
34 #include "qlcnic_hw.h"
35 #include "qlcnic_83xx_hw.h"
36 #include "qlcnic_dcb.h"
37
38 #define _QLCNIC_LINUX_MAJOR 5
39 #define _QLCNIC_LINUX_MINOR 3
40 #define _QLCNIC_LINUX_SUBVERSION 64
41 #define QLCNIC_LINUX_VERSIONID "5.3.64"
42 #define QLCNIC_DRV_IDC_VER 0x01
43 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
44 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
45
46 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
47 #define _major(v) (((v) >> 24) & 0xff)
48 #define _minor(v) (((v) >> 16) & 0xff)
49 #define _build(v) ((v) & 0xffff)
50
51 /* version in image has weird encoding:
52 * 7:0 - major
53 * 15:8 - minor
54 * 31:16 - build (little endian)
55 */
56 #define QLCNIC_DECODE_VERSION(v) \
57 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
58
59 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
60 #define QLCNIC_NUM_FLASH_SECTORS (64)
61 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
62 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
63 * QLCNIC_FLASH_SECTOR_SIZE)
64
65 #define RCV_DESC_RINGSIZE(rds_ring) \
66 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
67 #define RCV_BUFF_RINGSIZE(rds_ring) \
68 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
69 #define STATUS_DESC_RINGSIZE(sds_ring) \
70 (sizeof(struct status_desc) * (sds_ring)->num_desc)
71 #define TX_BUFF_RINGSIZE(tx_ring) \
72 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
73 #define TX_DESC_RINGSIZE(tx_ring) \
74 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
75
76 #define QLCNIC_P3P_A0 0x50
77 #define QLCNIC_P3P_C0 0x58
78
79 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
80
81 #define FIRST_PAGE_GROUP_START 0
82 #define FIRST_PAGE_GROUP_END 0x100000
83
84 #define P3P_MAX_MTU (9600)
85 #define P3P_MIN_MTU (68)
86 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
87
88 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
89 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
90 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
91 #define QLCNIC_LRO_BUFFER_EXTRA 2048
92
93 /* Tx defines */
94 #define QLCNIC_MAX_FRAGS_PER_TX 14
95 #define MAX_TSO_HEADER_DESC 2
96 #define MGMT_CMD_DESC_RESV 4
97 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
98 + MGMT_CMD_DESC_RESV)
99 #define QLCNIC_MAX_TX_TIMEOUTS 2
100
101 /* Driver will use 1 Tx ring in INT-x/MSI/SRIOV mode. */
102 #define QLCNIC_SINGLE_RING 1
103 #define QLCNIC_DEF_SDS_RINGS 4
104 #define QLCNIC_DEF_TX_RINGS 4
105 #define QLCNIC_MAX_VNIC_TX_RINGS 4
106 #define QLCNIC_MAX_VNIC_SDS_RINGS 4
107 #define QLCNIC_83XX_MINIMUM_VECTOR 3
108 #define QLCNIC_82XX_MINIMUM_VECTOR 2
109
110 enum qlcnic_queue_type {
111 QLCNIC_TX_QUEUE = 1,
112 QLCNIC_RX_QUEUE,
113 };
114
115 /* Operational mode for driver */
116 #define QLCNIC_VNIC_MODE 0xFF
117 #define QLCNIC_DEFAULT_MODE 0x0
118
119 /* Virtual NIC function count */
120 #define QLC_DEFAULT_VNIC_COUNT 8
121 #define QLC_84XX_VNIC_COUNT 16
122
123 /*
124 * Following are the states of the Phantom. Phantom will set them and
125 * Host will read to check if the fields are correct.
126 */
127 #define PHAN_INITIALIZE_FAILED 0xffff
128 #define PHAN_INITIALIZE_COMPLETE 0xff01
129
130 /* Host writes the following to notify that it has done the init-handshake */
131 #define PHAN_INITIALIZE_ACK 0xf00f
132 #define PHAN_PEG_RCV_INITIALIZED 0xff01
133
134 #define NUM_RCV_DESC_RINGS 3
135
136 #define RCV_RING_NORMAL 0
137 #define RCV_RING_JUMBO 1
138
139 #define MIN_CMD_DESCRIPTORS 64
140 #define MIN_RCV_DESCRIPTORS 64
141 #define MIN_JUMBO_DESCRIPTORS 32
142
143 #define MAX_CMD_DESCRIPTORS 1024
144 #define MAX_RCV_DESCRIPTORS_1G 4096
145 #define MAX_RCV_DESCRIPTORS_10G 8192
146 #define MAX_RCV_DESCRIPTORS_VF 2048
147 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
148 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
149
150 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
151 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
152 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
153 #define MAX_RDS_RINGS 2
154
155 #define get_next_index(index, length) \
156 (((index) + 1) & ((length) - 1))
157
158 /*
159 * Following data structures describe the descriptors that will be used.
160 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
161 * we are doing LSO (above the 1500 size packet) only.
162 */
163 struct cmd_desc_type0 {
164 u8 tcp_hdr_offset; /* For LSO only */
165 u8 ip_hdr_offset; /* For LSO only */
166 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
167 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
168
169 __le64 addr_buffer2;
170
171 __le16 encap_descr; /* 15:10 offset of outer L3 header,
172 * 9:6 number of 32bit words in outer L3 header,
173 * 5 offload outer L4 checksum,
174 * 4 offload outer L3 checksum,
175 * 3 Inner L4 type, TCP=0, UDP=1,
176 * 2 Inner L3 type, IPv4=0, IPv6=1,
177 * 1 Outer L3 type,IPv4=0, IPv6=1,
178 * 0 type of encapsulation, GRE=0, VXLAN=1
179 */
180 __le16 mss;
181 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
182 u8 hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
183 u8 outer_hdr_length; /* Encapsulation only */
184 u8 rsvd1;
185
186 __le64 addr_buffer3;
187 __le64 addr_buffer1;
188
189 __le16 buffer_length[4];
190
191 __le64 addr_buffer4;
192
193 u8 eth_addr[ETH_ALEN];
194 __le16 vlan_TCI; /* In case of encapsulation,
195 * this is for outer VLAN
196 */
197
198 } __attribute__ ((aligned(64)));
199
200 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
201 struct rcv_desc {
202 __le16 reference_handle;
203 __le16 reserved;
204 __le32 buffer_length; /* allocated buffer length (usually 2K) */
205 __le64 addr_buffer;
206 } __packed;
207
208 struct status_desc {
209 __le64 status_desc_data[2];
210 } __attribute__ ((aligned(16)));
211
212 /* UNIFIED ROMIMAGE */
213 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
214 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
215 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
216 #define QLCNIC_UNI_DIR_SECT_FW 0x7
217
218 /*Offsets */
219 #define QLCNIC_UNI_CHIP_REV_OFF 10
220 #define QLCNIC_UNI_FLAGS_OFF 11
221 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
222 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
223 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
224
225 struct uni_table_desc{
226 __le32 findex;
227 __le32 num_entries;
228 __le32 entry_size;
229 __le32 reserved[5];
230 };
231
232 struct uni_data_desc{
233 __le32 findex;
234 __le32 size;
235 __le32 reserved[5];
236 };
237
238 /* Flash Defines and Structures */
239 #define QLCNIC_FLT_LOCATION 0x3F1000
240 #define QLCNIC_FDT_LOCATION 0x3F0000
241 #define QLCNIC_B0_FW_IMAGE_REGION 0x74
242 #define QLCNIC_C0_FW_IMAGE_REGION 0x97
243 #define QLCNIC_BOOTLD_REGION 0X72
244 struct qlcnic_flt_header {
245 u16 version;
246 u16 len;
247 u16 checksum;
248 u16 reserved;
249 };
250
251 struct qlcnic_flt_entry {
252 u8 region;
253 u8 reserved0;
254 u8 attrib;
255 u8 reserved1;
256 u32 size;
257 u32 start_addr;
258 u32 end_addr;
259 };
260
261 /* Flash Descriptor Table */
262 struct qlcnic_fdt {
263 u32 valid;
264 u16 ver;
265 u16 len;
266 u16 cksum;
267 u16 unused;
268 u8 model[16];
269 u8 mfg_id;
270 u16 id;
271 u8 flag;
272 u8 erase_cmd;
273 u8 alt_erase_cmd;
274 u8 write_enable_cmd;
275 u8 write_enable_bits;
276 u8 write_statusreg_cmd;
277 u8 unprotected_sec_cmd;
278 u8 read_manuf_cmd;
279 u32 block_size;
280 u32 alt_block_size;
281 u32 flash_size;
282 u32 write_enable_data;
283 u8 readid_addr_len;
284 u8 write_disable_bits;
285 u8 read_dev_id_len;
286 u8 chip_erase_cmd;
287 u16 read_timeo;
288 u8 protected_sec_cmd;
289 u8 resvd[65];
290 };
291 /* Magic number to let user know flash is programmed */
292 #define QLCNIC_BDINFO_MAGIC 0x12345678
293
294 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
295 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
296 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
297 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
298 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
299 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
300 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
301 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
302 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
303 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
304 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
305 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
306 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
307 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
308
309 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
310
311 /* Flash memory map */
312 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
313 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
314 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
315 #define QLCNIC_USER_START 0x3E8000 /* Firmware info */
316
317 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
318 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
319 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
320 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
321
322 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
323 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
324
325 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
326 #define QLCNIC_UNIFIED_ROMIMAGE 0
327 #define QLCNIC_FLASH_ROMIMAGE 1
328 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
329
330 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
331 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
332
333 extern char qlcnic_driver_name[];
334
335 extern int qlcnic_use_msi;
336 extern int qlcnic_use_msi_x;
337 extern int qlcnic_auto_fw_reset;
338 extern int qlcnic_load_fw_file;
339
340 /* Number of status descriptors to handle per interrupt */
341 #define MAX_STATUS_HANDLE (64)
342
343 /*
344 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
345 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
346 */
347 struct qlcnic_skb_frag {
348 u64 dma;
349 u64 length;
350 };
351
352 /* Following defines are for the state of the buffers */
353 #define QLCNIC_BUFFER_FREE 0
354 #define QLCNIC_BUFFER_BUSY 1
355
356 /*
357 * There will be one qlcnic_buffer per skb packet. These will be
358 * used to save the dma info for pci_unmap_page()
359 */
360 struct qlcnic_cmd_buffer {
361 struct sk_buff *skb;
362 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
363 u32 frag_count;
364 };
365
366 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
367 struct qlcnic_rx_buffer {
368 u16 ref_handle;
369 struct sk_buff *skb;
370 struct list_head list;
371 u64 dma;
372 };
373
374 /* Board types */
375 #define QLCNIC_GBE 0x01
376 #define QLCNIC_XGBE 0x02
377
378 /*
379 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
380 * adjusted based on configured MTU.
381 */
382 #define QLCNIC_INTR_COAL_TYPE_RX 1
383 #define QLCNIC_INTR_COAL_TYPE_TX 2
384 #define QLCNIC_INTR_COAL_TYPE_RX_TX 3
385
386 #define QLCNIC_DEF_INTR_COALESCE_RX_TIME_US 3
387 #define QLCNIC_DEF_INTR_COALESCE_RX_PACKETS 256
388
389 #define QLCNIC_DEF_INTR_COALESCE_TX_TIME_US 64
390 #define QLCNIC_DEF_INTR_COALESCE_TX_PACKETS 64
391
392 #define QLCNIC_INTR_DEFAULT 0x04
393 #define QLCNIC_CONFIG_INTR_COALESCE 3
394 #define QLCNIC_DEV_INFO_SIZE 2
395
396 struct qlcnic_nic_intr_coalesce {
397 u8 type;
398 u8 sts_ring_mask;
399 u16 rx_packets;
400 u16 rx_time_us;
401 u16 tx_packets;
402 u16 tx_time_us;
403 u16 flag;
404 u32 timer_out;
405 };
406
407 struct qlcnic_83xx_dump_template_hdr {
408 u32 type;
409 u32 offset;
410 u32 size;
411 u32 cap_mask;
412 u32 num_entries;
413 u32 version;
414 u32 timestamp;
415 u32 checksum;
416 u32 drv_cap_mask;
417 u32 sys_info[3];
418 u32 saved_state[16];
419 u32 cap_sizes[8];
420 u32 ocm_wnd_reg[16];
421 u32 rsvd[0];
422 };
423
424 struct qlcnic_82xx_dump_template_hdr {
425 u32 type;
426 u32 offset;
427 u32 size;
428 u32 cap_mask;
429 u32 num_entries;
430 u32 version;
431 u32 timestamp;
432 u32 checksum;
433 u32 drv_cap_mask;
434 u32 sys_info[3];
435 u32 saved_state[16];
436 u32 cap_sizes[8];
437 u32 rsvd[7];
438 u32 capabilities;
439 u32 rsvd1[0];
440 };
441
442 #define QLC_PEX_DMA_READ_SIZE (PAGE_SIZE * 16)
443
444 struct qlcnic_fw_dump {
445 u8 clr; /* flag to indicate if dump is cleared */
446 bool enable; /* enable/disable dump */
447 u32 size; /* total size of the dump */
448 u32 cap_mask; /* Current capture mask */
449 void *data; /* dump data area */
450 void *tmpl_hdr;
451 dma_addr_t phys_addr;
452 void *dma_buffer;
453 bool use_pex_dma;
454 /* Read only elements which are common between 82xx and 83xx
455 * template header. Update these values immediately after we read
456 * template header from Firmware
457 */
458 u32 tmpl_hdr_size;
459 u32 version;
460 u32 num_entries;
461 u32 offset;
462 };
463
464 /*
465 * One hardware_context{} per adapter
466 * contains interrupt info as well shared hardware info.
467 */
468 struct qlcnic_hardware_context {
469 void __iomem *pci_base0;
470 void __iomem *ocm_win_crb;
471
472 unsigned long pci_len0;
473
474 rwlock_t crb_lock;
475 struct mutex mem_lock;
476
477 u8 revision_id;
478 u8 pci_func;
479 u8 linkup;
480 u8 loopback_state;
481 u8 beacon_state;
482 u8 has_link_events;
483 u8 fw_type;
484 u8 physical_port;
485 u8 reset_context;
486 u8 msix_supported;
487 u8 max_mac_filters;
488 u8 mc_enabled;
489 u8 max_mc_count;
490 u8 diag_test;
491 u8 num_msix;
492 u8 nic_mode;
493 int diag_cnt;
494
495 u16 max_uc_count;
496 u16 port_type;
497 u16 board_type;
498 u16 supported_type;
499
500 u16 link_speed;
501 u16 link_duplex;
502 u16 link_autoneg;
503 u16 module_type;
504
505 u16 op_mode;
506 u16 switch_mode;
507 u16 max_tx_ques;
508 u16 max_rx_ques;
509 u16 max_mtu;
510 u32 msg_enable;
511 u16 total_nic_func;
512 u16 max_pci_func;
513 u32 max_vnic_func;
514 u32 total_pci_func;
515
516 u32 capabilities;
517 u32 extra_capability[3];
518 u32 temp;
519 u32 int_vec_bit;
520 u32 fw_hal_version;
521 u32 port_config;
522 struct qlcnic_hardware_ops *hw_ops;
523 struct qlcnic_nic_intr_coalesce coal;
524 struct qlcnic_fw_dump fw_dump;
525 struct qlcnic_fdt fdt;
526 struct qlc_83xx_reset reset;
527 struct qlc_83xx_idc idc;
528 struct qlc_83xx_fw_info *fw_info;
529 struct qlcnic_intrpt_config *intr_tbl;
530 struct qlcnic_sriov *sriov;
531 u32 *reg_tbl;
532 u32 *ext_reg_tbl;
533 u32 mbox_aen[QLC_83XX_MBX_AEN_CNT];
534 u32 mbox_reg[4];
535 struct qlcnic_mailbox *mailbox;
536 u8 extend_lb_time;
537 u8 phys_port_id[ETH_ALEN];
538 u8 lb_mode;
539 u8 vxlan_port_count;
540 u16 vxlan_port;
541 struct device *hwmon_dev;
542 u32 post_mode;
543 bool run_post;
544 };
545
546 struct qlcnic_adapter_stats {
547 u64 xmitcalled;
548 u64 xmitfinished;
549 u64 rxdropped;
550 u64 txdropped;
551 u64 csummed;
552 u64 rx_pkts;
553 u64 lro_pkts;
554 u64 rxbytes;
555 u64 txbytes;
556 u64 lrobytes;
557 u64 lso_frames;
558 u64 encap_lso_frames;
559 u64 encap_tx_csummed;
560 u64 encap_rx_csummed;
561 u64 xmit_on;
562 u64 xmit_off;
563 u64 skb_alloc_failure;
564 u64 null_rxbuf;
565 u64 rx_dma_map_error;
566 u64 tx_dma_map_error;
567 u64 spurious_intr;
568 u64 mac_filter_limit_overrun;
569 u64 mbx_spurious_intr;
570 };
571
572 /*
573 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
574 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
575 */
576 struct qlcnic_host_rds_ring {
577 void __iomem *crb_rcv_producer;
578 struct rcv_desc *desc_head;
579 struct qlcnic_rx_buffer *rx_buf_arr;
580 u32 num_desc;
581 u32 producer;
582 u32 dma_size;
583 u32 skb_size;
584 u32 flags;
585 struct list_head free_list;
586 spinlock_t lock;
587 dma_addr_t phys_addr;
588 } ____cacheline_internodealigned_in_smp;
589
590 struct qlcnic_host_sds_ring {
591 u32 consumer;
592 u32 num_desc;
593 void __iomem *crb_sts_consumer;
594
595 struct qlcnic_host_tx_ring *tx_ring;
596 struct status_desc *desc_head;
597 struct qlcnic_adapter *adapter;
598 struct napi_struct napi;
599 struct list_head free_list[NUM_RCV_DESC_RINGS];
600
601 void __iomem *crb_intr_mask;
602 int irq;
603
604 dma_addr_t phys_addr;
605 char name[IFNAMSIZ + 12];
606 } ____cacheline_internodealigned_in_smp;
607
608 struct qlcnic_tx_queue_stats {
609 u64 xmit_on;
610 u64 xmit_off;
611 u64 xmit_called;
612 u64 xmit_finished;
613 u64 tx_bytes;
614 };
615
616 struct qlcnic_host_tx_ring {
617 int irq;
618 void __iomem *crb_intr_mask;
619 char name[IFNAMSIZ + 12];
620 u16 ctx_id;
621
622 u32 state;
623 u32 producer;
624 u32 sw_consumer;
625 u32 num_desc;
626
627 struct qlcnic_tx_queue_stats tx_stats;
628
629 void __iomem *crb_cmd_producer;
630 struct cmd_desc_type0 *desc_head;
631 struct qlcnic_adapter *adapter;
632 struct napi_struct napi;
633 struct qlcnic_cmd_buffer *cmd_buf_arr;
634 __le32 *hw_consumer;
635
636 dma_addr_t phys_addr;
637 dma_addr_t hw_cons_phys_addr;
638 struct netdev_queue *txq;
639 /* Lock to protect Tx descriptors cleanup */
640 spinlock_t tx_clean_lock;
641 } ____cacheline_internodealigned_in_smp;
642
643 /*
644 * Receive context. There is one such structure per instance of the
645 * receive processing. Any state information that is relevant to
646 * the receive, and is must be in this structure. The global data may be
647 * present elsewhere.
648 */
649 struct qlcnic_recv_context {
650 struct qlcnic_host_rds_ring *rds_rings;
651 struct qlcnic_host_sds_ring *sds_rings;
652 u32 state;
653 u16 context_id;
654 u16 virt_port;
655 };
656
657 /* HW context creation */
658
659 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
660
661 #define QLCNIC_CDRP_CMD_BIT 0x80000000
662
663 /*
664 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
665 * in the crb QLCNIC_CDRP_CRB_OFFSET.
666 */
667 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
668 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
669
670 #define QLCNIC_CDRP_RSP_OK 0x00000001
671 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
672 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
673
674 /*
675 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
676 * the crb QLCNIC_CDRP_CRB_OFFSET.
677 */
678 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
679
680 #define QLCNIC_RCODE_SUCCESS 0
681 #define QLCNIC_RCODE_INVALID_ARGS 6
682 #define QLCNIC_RCODE_NOT_SUPPORTED 9
683 #define QLCNIC_RCODE_NOT_PERMITTED 10
684 #define QLCNIC_RCODE_NOT_IMPL 15
685 #define QLCNIC_RCODE_INVALID 16
686 #define QLCNIC_RCODE_TIMEOUT 17
687 #define QLCNIC_DESTROY_CTX_RESET 0
688
689 /*
690 * Capabilities Announced
691 */
692 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
693 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
694 #define QLCNIC_CAP0_LSO (1 << 6)
695 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
696 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
697 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
698 #define QLCNIC_CAP0_LRO_MSS (1 << 21)
699 #define QLCNIC_CAP0_TX_MULTI (1 << 22)
700
701 /*
702 * Context state
703 */
704 #define QLCNIC_HOST_CTX_STATE_FREED 0
705 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
706
707 /*
708 * Rx context
709 */
710
711 struct qlcnic_hostrq_sds_ring {
712 __le64 host_phys_addr; /* Ring base addr */
713 __le32 ring_size; /* Ring entries */
714 __le16 msi_index;
715 __le16 rsvd; /* Padding */
716 } __packed;
717
718 struct qlcnic_hostrq_rds_ring {
719 __le64 host_phys_addr; /* Ring base addr */
720 __le64 buff_size; /* Packet buffer size */
721 __le32 ring_size; /* Ring entries */
722 __le32 ring_kind; /* Class of ring */
723 } __packed;
724
725 struct qlcnic_hostrq_rx_ctx {
726 __le64 host_rsp_dma_addr; /* Response dma'd here */
727 __le32 capabilities[4]; /* Flag bit vector */
728 __le32 host_int_crb_mode; /* Interrupt crb usage */
729 __le32 host_rds_crb_mode; /* RDS crb usage */
730 /* These ring offsets are relative to data[0] below */
731 __le32 rds_ring_offset; /* Offset to RDS config */
732 __le32 sds_ring_offset; /* Offset to SDS config */
733 __le16 num_rds_rings; /* Count of RDS rings */
734 __le16 num_sds_rings; /* Count of SDS rings */
735 __le16 valid_field_offset;
736 u8 txrx_sds_binding;
737 u8 msix_handler;
738 u8 reserved[128]; /* reserve space for future expansion*/
739 /* MUST BE 64-bit aligned.
740 The following is packed:
741 - N hostrq_rds_rings
742 - N hostrq_sds_rings */
743 char data[0];
744 } __packed;
745
746 struct qlcnic_cardrsp_rds_ring{
747 __le32 host_producer_crb; /* Crb to use */
748 __le32 rsvd1; /* Padding */
749 } __packed;
750
751 struct qlcnic_cardrsp_sds_ring {
752 __le32 host_consumer_crb; /* Crb to use */
753 __le32 interrupt_crb; /* Crb to use */
754 } __packed;
755
756 struct qlcnic_cardrsp_rx_ctx {
757 /* These ring offsets are relative to data[0] below */
758 __le32 rds_ring_offset; /* Offset to RDS config */
759 __le32 sds_ring_offset; /* Offset to SDS config */
760 __le32 host_ctx_state; /* Starting State */
761 __le32 num_fn_per_port; /* How many PCI fn share the port */
762 __le16 num_rds_rings; /* Count of RDS rings */
763 __le16 num_sds_rings; /* Count of SDS rings */
764 __le16 context_id; /* Handle for context */
765 u8 phys_port; /* Physical id of port */
766 u8 virt_port; /* Virtual/Logical id of port */
767 u8 reserved[128]; /* save space for future expansion */
768 /* MUST BE 64-bit aligned.
769 The following is packed:
770 - N cardrsp_rds_rings
771 - N cardrs_sds_rings */
772 char data[0];
773 } __packed;
774
775 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
776 (sizeof(HOSTRQ_RX) + \
777 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
778 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
779
780 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
781 (sizeof(CARDRSP_RX) + \
782 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
783 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
784
785 /*
786 * Tx context
787 */
788
789 struct qlcnic_hostrq_cds_ring {
790 __le64 host_phys_addr; /* Ring base addr */
791 __le32 ring_size; /* Ring entries */
792 __le32 rsvd; /* Padding */
793 } __packed;
794
795 struct qlcnic_hostrq_tx_ctx {
796 __le64 host_rsp_dma_addr; /* Response dma'd here */
797 __le64 cmd_cons_dma_addr; /* */
798 __le64 dummy_dma_addr; /* */
799 __le32 capabilities[4]; /* Flag bit vector */
800 __le32 host_int_crb_mode; /* Interrupt crb usage */
801 __le32 rsvd1; /* Padding */
802 __le16 rsvd2; /* Padding */
803 __le16 interrupt_ctl;
804 __le16 msi_index;
805 __le16 rsvd3; /* Padding */
806 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
807 u8 reserved[128]; /* future expansion */
808 } __packed;
809
810 struct qlcnic_cardrsp_cds_ring {
811 __le32 host_producer_crb; /* Crb to use */
812 __le32 interrupt_crb; /* Crb to use */
813 } __packed;
814
815 struct qlcnic_cardrsp_tx_ctx {
816 __le32 host_ctx_state; /* Starting state */
817 __le16 context_id; /* Handle for context */
818 u8 phys_port; /* Physical id of port */
819 u8 virt_port; /* Virtual/Logical id of port */
820 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
821 u8 reserved[128]; /* future expansion */
822 } __packed;
823
824 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
825 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
826
827 /* CRB */
828
829 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
830 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
831 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
832 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
833
834 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
835 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
836 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
837 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
838 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
839
840
841 /* MAC */
842
843 #define MC_COUNT_P3P 38
844
845 #define QLCNIC_MAC_NOOP 0
846 #define QLCNIC_MAC_ADD 1
847 #define QLCNIC_MAC_DEL 2
848 #define QLCNIC_MAC_VLAN_ADD 3
849 #define QLCNIC_MAC_VLAN_DEL 4
850
851 enum qlcnic_mac_type {
852 QLCNIC_UNICAST_MAC,
853 QLCNIC_MULTICAST_MAC,
854 QLCNIC_BROADCAST_MAC,
855 };
856
857 struct qlcnic_mac_vlan_list {
858 struct list_head list;
859 uint8_t mac_addr[ETH_ALEN+2];
860 u16 vlan_id;
861 enum qlcnic_mac_type mac_type;
862 };
863
864 /* MAC Learn */
865 #define NO_MAC_LEARN 0
866 #define DRV_MAC_LEARN 1
867 #define FDB_MAC_LEARN 2
868
869 #define QLCNIC_HOST_REQUEST 0x13
870 #define QLCNIC_REQUEST 0x14
871
872 #define QLCNIC_MAC_EVENT 0x1
873
874 #define QLCNIC_IP_UP 2
875 #define QLCNIC_IP_DOWN 3
876
877 #define QLCNIC_ILB_MODE 0x1
878 #define QLCNIC_ELB_MODE 0x2
879 #define QLCNIC_LB_MODE_MASK 0x3
880
881 #define QLCNIC_LINKEVENT 0x1
882 #define QLCNIC_LB_RESPONSE 0x2
883 #define QLCNIC_IS_LB_CONFIGURED(VAL) \
884 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
885
886 /*
887 * Driver --> Firmware
888 */
889 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1
890 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3
891 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4
892 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7
893 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc
894 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12
895
896 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15
897 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17
898 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18
899 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13
900
901 /*
902 * Firmware --> Driver
903 */
904
905 #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f
906 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D
907 #define QLCNIC_C2H_OPCODE_GET_DCB_AEN 0x90
908
909 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
910 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
911 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
912
913 #define QLCNIC_LRO_REQUEST_CLEANUP 4
914
915 /* Capabilites received */
916 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
917 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
918 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
919 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
920 #define QLCNIC_FW_CAPABILITY_2_MULTI_TX BIT_4
921 #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27
922 #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31
923
924 #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2
925 #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3
926 #define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5
927 #define QLCNIC_FW_CAPABILITY_2_BEACON BIT_7
928 #define QLCNIC_FW_CAPABILITY_2_PER_PORT_ESWITCH_CFG BIT_9
929 #define QLCNIC_FW_CAPABILITY_2_EXT_ISCSI_DUMP BIT_13
930
931 #define QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD BIT_0
932 #define QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD BIT_1
933 #define QLCNIC_83XX_FW_CAPAB_ENCAP_CKO_OFFLOAD BIT_4
934
935 /* module types */
936 #define LINKEVENT_MODULE_NOT_PRESENT 1
937 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
938 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
939 #define LINKEVENT_MODULE_OPTICAL_LRM 4
940 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
941 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
942 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
943 #define LINKEVENT_MODULE_TWINAX 8
944
945 #define LINKSPEED_10GBPS 10000
946 #define LINKSPEED_1GBPS 1000
947 #define LINKSPEED_100MBPS 100
948 #define LINKSPEED_10MBPS 10
949
950 #define LINKSPEED_ENCODED_10MBPS 0
951 #define LINKSPEED_ENCODED_100MBPS 1
952 #define LINKSPEED_ENCODED_1GBPS 2
953
954 #define LINKEVENT_AUTONEG_DISABLED 0
955 #define LINKEVENT_AUTONEG_ENABLED 1
956
957 #define LINKEVENT_HALF_DUPLEX 0
958 #define LINKEVENT_FULL_DUPLEX 1
959
960 #define LINKEVENT_LINKSPEED_MBPS 0
961 #define LINKEVENT_LINKSPEED_ENCODED 1
962
963 /* firmware response header:
964 * 63:58 - message type
965 * 57:56 - owner
966 * 55:53 - desc count
967 * 52:48 - reserved
968 * 47:40 - completion id
969 * 39:32 - opcode
970 * 31:16 - error code
971 * 15:00 - reserved
972 */
973 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
974 ((msg_hdr >> 32) & 0xFF)
975
976 struct qlcnic_fw_msg {
977 union {
978 struct {
979 u64 hdr;
980 u64 body[7];
981 };
982 u64 words[8];
983 };
984 };
985
986 struct qlcnic_nic_req {
987 __le64 qhdr;
988 __le64 req_hdr;
989 __le64 words[6];
990 } __packed;
991
992 struct qlcnic_mac_req {
993 u8 op;
994 u8 tag;
995 u8 mac_addr[6];
996 };
997
998 struct qlcnic_vlan_req {
999 __le16 vlan_id;
1000 __le16 rsvd[3];
1001 } __packed;
1002
1003 struct qlcnic_ipaddr {
1004 __be32 ipv4;
1005 __be32 ipv6[4];
1006 };
1007
1008 #define QLCNIC_MSI_ENABLED 0x02
1009 #define QLCNIC_MSIX_ENABLED 0x04
1010 #define QLCNIC_LRO_ENABLED 0x01
1011 #define QLCNIC_LRO_DISABLED 0x00
1012 #define QLCNIC_BRIDGE_ENABLED 0X10
1013 #define QLCNIC_DIAG_ENABLED 0x20
1014 #define QLCNIC_ESWITCH_ENABLED 0x40
1015 #define QLCNIC_ADAPTER_INITIALIZED 0x80
1016 #define QLCNIC_TAGGING_ENABLED 0x100
1017 #define QLCNIC_MACSPOOF 0x200
1018 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
1019 #define QLCNIC_PROMISC_DISABLED 0x800
1020 #define QLCNIC_NEED_FLR 0x1000
1021 #define QLCNIC_FW_RESET_OWNER 0x2000
1022 #define QLCNIC_FW_HANG 0x4000
1023 #define QLCNIC_FW_LRO_MSS_CAP 0x8000
1024 #define QLCNIC_TX_INTR_SHARED 0x10000
1025 #define QLCNIC_APP_CHANGED_FLAGS 0x20000
1026 #define QLCNIC_HAS_PHYS_PORT_ID 0x40000
1027 #define QLCNIC_TSS_RSS 0x80000
1028
1029 #define QLCNIC_ADD_VXLAN_PORT 0x100000
1030 #define QLCNIC_DEL_VXLAN_PORT 0x200000
1031
1032 #define QLCNIC_VLAN_FILTERING 0x800000
1033
1034 #define QLCNIC_IS_MSI_FAMILY(adapter) \
1035 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
1036 #define QLCNIC_IS_TSO_CAPABLE(adapter) \
1037 ((adapter)->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
1038
1039 #define QLCNIC_BEACON_EANBLE 0xC
1040 #define QLCNIC_BEACON_DISABLE 0xD
1041
1042 #define QLCNIC_BEACON_ON 2
1043 #define QLCNIC_BEACON_OFF 0
1044
1045 #define QLCNIC_MSIX_TBL_SPACE 8192
1046 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
1047 #define QLCNIC_MSIX_TBL_PGSIZE 4096
1048
1049 #define QLCNIC_ADAPTER_UP_MAGIC 777
1050
1051 #define __QLCNIC_FW_ATTACHED 0
1052 #define __QLCNIC_DEV_UP 1
1053 #define __QLCNIC_RESETTING 2
1054 #define __QLCNIC_START_FW 4
1055 #define __QLCNIC_AER 5
1056 #define __QLCNIC_DIAG_RES_ALLOC 6
1057 #define __QLCNIC_LED_ENABLE 7
1058 #define __QLCNIC_ELB_INPROGRESS 8
1059 #define __QLCNIC_MULTI_TX_UNIQUE 9
1060 #define __QLCNIC_SRIOV_ENABLE 10
1061 #define __QLCNIC_SRIOV_CAPABLE 11
1062 #define __QLCNIC_MBX_POLL_ENABLE 12
1063 #define __QLCNIC_DIAG_MODE 13
1064 #define __QLCNIC_MAINTENANCE_MODE 16
1065
1066 #define QLCNIC_INTERRUPT_TEST 1
1067 #define QLCNIC_LOOPBACK_TEST 2
1068 #define QLCNIC_LED_TEST 3
1069
1070 #define QLCNIC_FILTER_AGE 80
1071 #define QLCNIC_READD_AGE 20
1072 #define QLCNIC_LB_MAX_FILTERS 64
1073 #define QLCNIC_LB_BUCKET_SIZE 32
1074 #define QLCNIC_ILB_MAX_RCV_LOOP 10
1075
1076 struct qlcnic_filter {
1077 struct hlist_node fnode;
1078 u8 faddr[ETH_ALEN];
1079 u16 vlan_id;
1080 unsigned long ftime;
1081 };
1082
1083 struct qlcnic_filter_hash {
1084 struct hlist_head *fhead;
1085 u8 fnum;
1086 u16 fmax;
1087 u16 fbucket_size;
1088 };
1089
1090 /* Mailbox specific data structures */
1091 struct qlcnic_mailbox {
1092 struct workqueue_struct *work_q;
1093 struct qlcnic_adapter *adapter;
1094 const struct qlcnic_mbx_ops *ops;
1095 struct work_struct work;
1096 struct completion completion;
1097 struct list_head cmd_q;
1098 unsigned long status;
1099 spinlock_t queue_lock; /* Mailbox queue lock */
1100 spinlock_t aen_lock; /* Mailbox response/AEN lock */
1101 u32 rsp_status;
1102 u32 num_cmds;
1103 };
1104
1105 struct qlcnic_adapter {
1106 struct qlcnic_hardware_context *ahw;
1107 struct qlcnic_recv_context *recv_ctx;
1108 struct qlcnic_host_tx_ring *tx_ring;
1109 struct net_device *netdev;
1110 struct pci_dev *pdev;
1111
1112 unsigned long state;
1113 u32 flags;
1114
1115 u16 num_txd;
1116 u16 num_rxd;
1117 u16 num_jumbo_rxd;
1118 u16 max_rxd;
1119 u16 max_jumbo_rxd;
1120
1121 u8 max_rds_rings;
1122
1123 u8 max_sds_rings; /* max sds rings supported by adapter */
1124 u8 max_tx_rings; /* max tx rings supported by adapter */
1125
1126 u8 drv_tx_rings; /* max tx rings supported by driver */
1127 u8 drv_sds_rings; /* max sds rings supported by driver */
1128
1129 u8 drv_tss_rings; /* tss ring input */
1130 u8 drv_rss_rings; /* rss ring input */
1131
1132 u8 rx_csum;
1133 u8 portnum;
1134
1135 u8 fw_wait_cnt;
1136 u8 fw_fail_cnt;
1137 u8 tx_timeo_cnt;
1138 u8 need_fw_reset;
1139 u8 reset_ctx_cnt;
1140
1141 u16 is_up;
1142 u16 rx_pvid;
1143 u16 tx_pvid;
1144
1145 u32 irq;
1146 u32 heartbeat;
1147
1148 u8 dev_state;
1149 u8 reset_ack_timeo;
1150 u8 dev_init_timeo;
1151
1152 u8 mac_addr[ETH_ALEN];
1153
1154 u64 dev_rst_time;
1155 bool drv_mac_learn;
1156 bool fdb_mac_learn;
1157 bool rx_mac_learn;
1158 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)];
1159 u8 flash_mfg_id;
1160 struct qlcnic_npar_info *npars;
1161 struct qlcnic_eswitch *eswitch;
1162 struct qlcnic_nic_template *nic_ops;
1163
1164 struct qlcnic_adapter_stats stats;
1165 struct list_head mac_list;
1166
1167 void __iomem *tgt_mask_reg;
1168 void __iomem *tgt_status_reg;
1169 void __iomem *crb_int_state_reg;
1170 void __iomem *isr_int_vec;
1171
1172 struct msix_entry *msix_entries;
1173 struct workqueue_struct *qlcnic_wq;
1174 struct delayed_work fw_work;
1175 struct delayed_work idc_aen_work;
1176 struct delayed_work mbx_poll_work;
1177 struct qlcnic_dcb *dcb;
1178
1179 struct qlcnic_filter_hash fhash;
1180 struct qlcnic_filter_hash rx_fhash;
1181 struct list_head vf_mc_list;
1182
1183 spinlock_t mac_learn_lock;
1184 /* spinlock for catching rcv filters for eswitch traffic */
1185 spinlock_t rx_mac_learn_lock;
1186 u32 file_prd_off; /*File fw product offset*/
1187 u32 fw_version;
1188 u32 offload_flags;
1189 const struct firmware *fw;
1190 };
1191
1192 struct qlcnic_info_le {
1193 __le16 pci_func;
1194 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1195 __le16 phys_port;
1196 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1197
1198 __le32 capabilities;
1199 u8 max_mac_filters;
1200 u8 reserved1;
1201 __le16 max_mtu;
1202
1203 __le16 max_tx_ques;
1204 __le16 max_rx_ques;
1205 __le16 min_tx_bw;
1206 __le16 max_tx_bw;
1207 __le32 op_type;
1208 __le16 max_bw_reg_offset;
1209 __le16 max_linkspeed_reg_offset;
1210 __le32 capability1;
1211 __le32 capability2;
1212 __le32 capability3;
1213 __le16 max_tx_mac_filters;
1214 __le16 max_rx_mcast_mac_filters;
1215 __le16 max_rx_ucast_mac_filters;
1216 __le16 max_rx_ip_addr;
1217 __le16 max_rx_lro_flow;
1218 __le16 max_rx_status_rings;
1219 __le16 max_rx_buf_rings;
1220 __le16 max_tx_vlan_keys;
1221 u8 total_pf;
1222 u8 total_rss_engines;
1223 __le16 max_vports;
1224 __le16 linkstate_reg_offset;
1225 __le16 bit_offsets;
1226 __le16 max_local_ipv6_addrs;
1227 __le16 max_remote_ipv6_addrs;
1228 u8 reserved2[56];
1229 } __packed;
1230
1231 struct qlcnic_info {
1232 u16 pci_func;
1233 u16 op_mode;
1234 u16 phys_port;
1235 u16 switch_mode;
1236 u32 capabilities;
1237 u8 max_mac_filters;
1238 u16 max_mtu;
1239 u16 max_tx_ques;
1240 u16 max_rx_ques;
1241 u16 min_tx_bw;
1242 u16 max_tx_bw;
1243 u32 op_type;
1244 u16 max_bw_reg_offset;
1245 u16 max_linkspeed_reg_offset;
1246 u32 capability1;
1247 u32 capability2;
1248 u32 capability3;
1249 u16 max_tx_mac_filters;
1250 u16 max_rx_mcast_mac_filters;
1251 u16 max_rx_ucast_mac_filters;
1252 u16 max_rx_ip_addr;
1253 u16 max_rx_lro_flow;
1254 u16 max_rx_status_rings;
1255 u16 max_rx_buf_rings;
1256 u16 max_tx_vlan_keys;
1257 u8 total_pf;
1258 u8 total_rss_engines;
1259 u16 max_vports;
1260 u16 linkstate_reg_offset;
1261 u16 bit_offsets;
1262 u16 max_local_ipv6_addrs;
1263 u16 max_remote_ipv6_addrs;
1264 };
1265
1266 struct qlcnic_pci_info_le {
1267 __le16 id; /* pci function id */
1268 __le16 active; /* 1 = Enabled */
1269 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1270 __le16 default_port; /* default port number */
1271
1272 __le16 tx_min_bw; /* Multiple of 100mbpc */
1273 __le16 tx_max_bw;
1274 __le16 reserved1[2];
1275
1276 u8 mac[ETH_ALEN];
1277 __le16 func_count;
1278 u8 reserved2[104];
1279
1280 } __packed;
1281
1282 struct qlcnic_pci_info {
1283 u16 id;
1284 u16 active;
1285 u16 type;
1286 u16 default_port;
1287 u16 tx_min_bw;
1288 u16 tx_max_bw;
1289 u8 mac[ETH_ALEN];
1290 u16 func_count;
1291 };
1292
1293 struct qlcnic_npar_info {
1294 bool eswitch_status;
1295 u16 pvid;
1296 u16 min_bw;
1297 u16 max_bw;
1298 u8 phy_port;
1299 u8 type;
1300 u8 active;
1301 u8 enable_pm;
1302 u8 dest_npar;
1303 u8 discard_tagged;
1304 u8 mac_override;
1305 u8 mac_anti_spoof;
1306 u8 promisc_mode;
1307 u8 offload_flags;
1308 u8 pci_func;
1309 u8 mac[ETH_ALEN];
1310 };
1311
1312 struct qlcnic_eswitch {
1313 u8 port;
1314 u8 active_vports;
1315 u8 active_vlans;
1316 u8 active_ucast_filters;
1317 u8 max_ucast_filters;
1318 u8 max_active_vlans;
1319
1320 u32 flags;
1321 #define QLCNIC_SWITCH_ENABLE BIT_1
1322 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1323 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1324 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1325 };
1326
1327
1328 #define MAX_BW 100 /* % of link speed */
1329 #define MIN_BW 1 /* % of link speed */
1330 #define MAX_VLAN_ID 4095
1331 #define MIN_VLAN_ID 2
1332 #define DEFAULT_MAC_LEARN 1
1333
1334 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1335 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1336
1337 struct qlcnic_pci_func_cfg {
1338 u16 func_type;
1339 u16 min_bw;
1340 u16 max_bw;
1341 u16 port_num;
1342 u8 pci_func;
1343 u8 func_state;
1344 u8 def_mac_addr[ETH_ALEN];
1345 };
1346
1347 struct qlcnic_npar_func_cfg {
1348 u32 fw_capab;
1349 u16 port_num;
1350 u16 min_bw;
1351 u16 max_bw;
1352 u16 max_tx_queues;
1353 u16 max_rx_queues;
1354 u8 pci_func;
1355 u8 op_mode;
1356 };
1357
1358 struct qlcnic_pm_func_cfg {
1359 u8 pci_func;
1360 u8 action;
1361 u8 dest_npar;
1362 u8 reserved[5];
1363 };
1364
1365 struct qlcnic_esw_func_cfg {
1366 u16 vlan_id;
1367 u8 op_mode;
1368 u8 op_type;
1369 u8 pci_func;
1370 u8 host_vlan_tag;
1371 u8 promisc_mode;
1372 u8 discard_tagged;
1373 u8 mac_override;
1374 u8 mac_anti_spoof;
1375 u8 offload_flags;
1376 u8 reserved[5];
1377 };
1378
1379 #define QLCNIC_STATS_VERSION 1
1380 #define QLCNIC_STATS_PORT 1
1381 #define QLCNIC_STATS_ESWITCH 2
1382 #define QLCNIC_QUERY_RX_COUNTER 0
1383 #define QLCNIC_QUERY_TX_COUNTER 1
1384 #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL
1385 #define QLCNIC_FILL_STATS(VAL1) \
1386 (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1)
1387 #define QLCNIC_MAC_STATS 1
1388 #define QLCNIC_ESW_STATS 2
1389
1390 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1391 do { \
1392 if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \
1393 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1394 (VAL1) = (VAL2); \
1395 else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \
1396 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1397 (VAL1) += (VAL2); \
1398 } while (0)
1399
1400 struct qlcnic_mac_statistics_le {
1401 __le64 mac_tx_frames;
1402 __le64 mac_tx_bytes;
1403 __le64 mac_tx_mcast_pkts;
1404 __le64 mac_tx_bcast_pkts;
1405 __le64 mac_tx_pause_cnt;
1406 __le64 mac_tx_ctrl_pkt;
1407 __le64 mac_tx_lt_64b_pkts;
1408 __le64 mac_tx_lt_127b_pkts;
1409 __le64 mac_tx_lt_255b_pkts;
1410 __le64 mac_tx_lt_511b_pkts;
1411 __le64 mac_tx_lt_1023b_pkts;
1412 __le64 mac_tx_lt_1518b_pkts;
1413 __le64 mac_tx_gt_1518b_pkts;
1414 __le64 rsvd1[3];
1415
1416 __le64 mac_rx_frames;
1417 __le64 mac_rx_bytes;
1418 __le64 mac_rx_mcast_pkts;
1419 __le64 mac_rx_bcast_pkts;
1420 __le64 mac_rx_pause_cnt;
1421 __le64 mac_rx_ctrl_pkt;
1422 __le64 mac_rx_lt_64b_pkts;
1423 __le64 mac_rx_lt_127b_pkts;
1424 __le64 mac_rx_lt_255b_pkts;
1425 __le64 mac_rx_lt_511b_pkts;
1426 __le64 mac_rx_lt_1023b_pkts;
1427 __le64 mac_rx_lt_1518b_pkts;
1428 __le64 mac_rx_gt_1518b_pkts;
1429 __le64 rsvd2[3];
1430
1431 __le64 mac_rx_length_error;
1432 __le64 mac_rx_length_small;
1433 __le64 mac_rx_length_large;
1434 __le64 mac_rx_jabber;
1435 __le64 mac_rx_dropped;
1436 __le64 mac_rx_crc_error;
1437 __le64 mac_align_error;
1438 } __packed;
1439
1440 struct qlcnic_mac_statistics {
1441 u64 mac_tx_frames;
1442 u64 mac_tx_bytes;
1443 u64 mac_tx_mcast_pkts;
1444 u64 mac_tx_bcast_pkts;
1445 u64 mac_tx_pause_cnt;
1446 u64 mac_tx_ctrl_pkt;
1447 u64 mac_tx_lt_64b_pkts;
1448 u64 mac_tx_lt_127b_pkts;
1449 u64 mac_tx_lt_255b_pkts;
1450 u64 mac_tx_lt_511b_pkts;
1451 u64 mac_tx_lt_1023b_pkts;
1452 u64 mac_tx_lt_1518b_pkts;
1453 u64 mac_tx_gt_1518b_pkts;
1454 u64 rsvd1[3];
1455 u64 mac_rx_frames;
1456 u64 mac_rx_bytes;
1457 u64 mac_rx_mcast_pkts;
1458 u64 mac_rx_bcast_pkts;
1459 u64 mac_rx_pause_cnt;
1460 u64 mac_rx_ctrl_pkt;
1461 u64 mac_rx_lt_64b_pkts;
1462 u64 mac_rx_lt_127b_pkts;
1463 u64 mac_rx_lt_255b_pkts;
1464 u64 mac_rx_lt_511b_pkts;
1465 u64 mac_rx_lt_1023b_pkts;
1466 u64 mac_rx_lt_1518b_pkts;
1467 u64 mac_rx_gt_1518b_pkts;
1468 u64 rsvd2[3];
1469 u64 mac_rx_length_error;
1470 u64 mac_rx_length_small;
1471 u64 mac_rx_length_large;
1472 u64 mac_rx_jabber;
1473 u64 mac_rx_dropped;
1474 u64 mac_rx_crc_error;
1475 u64 mac_align_error;
1476 };
1477
1478 struct qlcnic_esw_stats_le {
1479 __le16 context_id;
1480 __le16 version;
1481 __le16 size;
1482 __le16 unused;
1483 __le64 unicast_frames;
1484 __le64 multicast_frames;
1485 __le64 broadcast_frames;
1486 __le64 dropped_frames;
1487 __le64 errors;
1488 __le64 local_frames;
1489 __le64 numbytes;
1490 __le64 rsvd[3];
1491 } __packed;
1492
1493 struct __qlcnic_esw_statistics {
1494 u16 context_id;
1495 u16 version;
1496 u16 size;
1497 u16 unused;
1498 u64 unicast_frames;
1499 u64 multicast_frames;
1500 u64 broadcast_frames;
1501 u64 dropped_frames;
1502 u64 errors;
1503 u64 local_frames;
1504 u64 numbytes;
1505 u64 rsvd[3];
1506 };
1507
1508 struct qlcnic_esw_statistics {
1509 struct __qlcnic_esw_statistics rx;
1510 struct __qlcnic_esw_statistics tx;
1511 };
1512
1513 #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed
1514 #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed
1515 #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed
1516 #define QLCNIC_FORCE_FW_RESET 0xdeaddead
1517 #define QLCNIC_SET_QUIESCENT 0xadd00010
1518 #define QLCNIC_RESET_QUIESCENT 0xadd00020
1519
1520 struct _cdrp_cmd {
1521 u32 num;
1522 u32 *arg;
1523 };
1524
1525 struct qlcnic_cmd_args {
1526 struct completion completion;
1527 struct list_head list;
1528 struct _cdrp_cmd req;
1529 struct _cdrp_cmd rsp;
1530 atomic_t rsp_status;
1531 int pay_size;
1532 u32 rsp_opcode;
1533 u32 total_cmds;
1534 u32 op_type;
1535 u32 type;
1536 u32 cmd_op;
1537 u32 *hdr; /* Back channel message header */
1538 u32 *pay; /* Back channel message payload */
1539 u8 func_num;
1540 };
1541
1542 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter);
1543 int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config);
1544 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1545 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1546
1547 #define ADDR_IN_RANGE(addr, low, high) \
1548 (((addr) < (high)) && ((addr) >= (low)))
1549
1550 #define QLCRD32(adapter, off, err) \
1551 (adapter->ahw->hw_ops->read_reg)(adapter, off, err)
1552
1553 #define QLCWR32(adapter, off, val) \
1554 adapter->ahw->hw_ops->write_reg(adapter, off, val)
1555
1556 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1557 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1558
1559 #define qlcnic_rom_lock(a) \
1560 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1561 #define qlcnic_rom_unlock(a) \
1562 qlcnic_pcie_sem_unlock((a), 2)
1563 #define qlcnic_phy_lock(a) \
1564 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1565 #define qlcnic_phy_unlock(a) \
1566 qlcnic_pcie_sem_unlock((a), 3)
1567 #define qlcnic_sw_lock(a) \
1568 qlcnic_pcie_sem_lock((a), 6, 0)
1569 #define qlcnic_sw_unlock(a) \
1570 qlcnic_pcie_sem_unlock((a), 6)
1571 #define crb_win_lock(a) \
1572 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1573 #define crb_win_unlock(a) \
1574 qlcnic_pcie_sem_unlock((a), 7)
1575
1576 #define __QLCNIC_MAX_LED_RATE 0xf
1577 #define __QLCNIC_MAX_LED_STATE 0x2
1578
1579 #define MAX_CTL_CHECK 1000
1580
1581 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1582 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1583 int qlcnic_dump_fw(struct qlcnic_adapter *);
1584 int qlcnic_enable_fw_dump_state(struct qlcnic_adapter *);
1585 bool qlcnic_check_fw_dump_state(struct qlcnic_adapter *);
1586
1587 /* Functions from qlcnic_init.c */
1588 void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int);
1589 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1590 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1591 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1592 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1593 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1594 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1595 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1596
1597 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp);
1598 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1599 u8 *bytes, size_t size);
1600 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1601 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1602
1603 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32);
1604
1605 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1606 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1607
1608 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1609 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1610
1611 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1612 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1613 void qlcnic_release_tx_buffers(struct qlcnic_adapter *,
1614 struct qlcnic_host_tx_ring *);
1615
1616 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1617 void qlcnic_watchdog_task(struct work_struct *work);
1618 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
1619 struct qlcnic_host_rds_ring *rds_ring, u8 ring_id);
1620 void qlcnic_set_multi(struct net_device *netdev);
1621 void qlcnic_flush_mcast_mac(struct qlcnic_adapter *);
1622 int qlcnic_nic_add_mac(struct qlcnic_adapter *, const u8 *, u16,
1623 enum qlcnic_mac_type);
1624 int qlcnic_nic_del_mac(struct qlcnic_adapter *, const u8 *);
1625 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter);
1626 int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *);
1627
1628 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1629 int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *, u32);
1630 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1631 netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1632 netdev_features_t features);
1633 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features);
1634 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1635 void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *);
1636
1637 /* Functions from qlcnic_ethtool.c */
1638 int qlcnic_check_loopback_buff(unsigned char *, u8 []);
1639 int qlcnic_do_lb_test(struct qlcnic_adapter *, u8);
1640
1641 /* Functions from qlcnic_main.c */
1642 int qlcnic_reset_context(struct qlcnic_adapter *);
1643 void qlcnic_diag_free_res(struct net_device *netdev, int);
1644 int qlcnic_diag_alloc_res(struct net_device *netdev, int);
1645 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *, struct net_device *);
1646 void qlcnic_set_tx_ring_count(struct qlcnic_adapter *, u8);
1647 void qlcnic_set_sds_ring_count(struct qlcnic_adapter *, u8);
1648 int qlcnic_setup_rings(struct qlcnic_adapter *);
1649 int qlcnic_validate_rings(struct qlcnic_adapter *, __u32, int);
1650 void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter);
1651 int qlcnic_enable_msix(struct qlcnic_adapter *, u32);
1652 void qlcnic_set_drv_version(struct qlcnic_adapter *);
1653
1654 /* eSwitch management functions */
1655 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1656 struct qlcnic_esw_func_cfg *);
1657
1658 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1659 struct qlcnic_esw_func_cfg *);
1660 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1661 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1662 struct __qlcnic_esw_statistics *);
1663 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1664 struct __qlcnic_esw_statistics *);
1665 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1666 int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *);
1667
1668 void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd);
1669
1670 int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int);
1671 void qlcnic_free_sds_rings(struct qlcnic_recv_context *);
1672 void qlcnic_advert_link_change(struct qlcnic_adapter *, int);
1673 void qlcnic_free_tx_rings(struct qlcnic_adapter *);
1674 int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *);
1675 void qlcnic_dump_mbx(struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1676
1677 void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter);
1678 void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter);
1679 void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter);
1680 void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter);
1681
1682 int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32);
1683 int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32);
1684 void qlcnic_set_vlan_config(struct qlcnic_adapter *,
1685 struct qlcnic_esw_func_cfg *);
1686 void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *,
1687 struct qlcnic_esw_func_cfg *);
1688 int qlcnic_setup_tss_rss_intr(struct qlcnic_adapter *);
1689 void qlcnic_down(struct qlcnic_adapter *, struct net_device *);
1690 int qlcnic_up(struct qlcnic_adapter *, struct net_device *);
1691 void __qlcnic_down(struct qlcnic_adapter *, struct net_device *);
1692 void qlcnic_detach(struct qlcnic_adapter *);
1693 void qlcnic_teardown_intr(struct qlcnic_adapter *);
1694 int qlcnic_attach(struct qlcnic_adapter *);
1695 int __qlcnic_up(struct qlcnic_adapter *, struct net_device *);
1696 void qlcnic_restore_indev_addr(struct net_device *, unsigned long);
1697
1698 int qlcnic_check_temp(struct qlcnic_adapter *);
1699 int qlcnic_init_pci_info(struct qlcnic_adapter *);
1700 int qlcnic_set_default_offload_settings(struct qlcnic_adapter *);
1701 int qlcnic_reset_npar_config(struct qlcnic_adapter *);
1702 int qlcnic_set_eswitch_port_config(struct qlcnic_adapter *);
1703 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter);
1704 int qlcnic_read_mac_addr(struct qlcnic_adapter *);
1705 int qlcnic_setup_netdev(struct qlcnic_adapter *, struct net_device *, int);
1706 void qlcnic_set_netdev_features(struct qlcnic_adapter *,
1707 struct qlcnic_esw_func_cfg *);
1708 void qlcnic_sriov_vf_set_multi(struct net_device *);
1709 int qlcnic_is_valid_nic_func(struct qlcnic_adapter *, u8);
1710 int qlcnic_get_pci_func_type(struct qlcnic_adapter *, u16, u16 *, u16 *,
1711 u16 *);
1712
1713 /*
1714 * QLOGIC Board information
1715 */
1716
1717 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1718 struct qlcnic_board_info {
1719 unsigned short vendor;
1720 unsigned short device;
1721 unsigned short sub_vendor;
1722 unsigned short sub_device;
1723 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1724 };
1725
1726 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1727 {
1728 if (likely(tx_ring->producer < tx_ring->sw_consumer))
1729 return tx_ring->sw_consumer - tx_ring->producer;
1730 else
1731 return tx_ring->sw_consumer + tx_ring->num_desc -
1732 tx_ring->producer;
1733 }
1734
1735 struct qlcnic_nic_template {
1736 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1737 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1738 int (*start_firmware) (struct qlcnic_adapter *);
1739 int (*init_driver) (struct qlcnic_adapter *);
1740 void (*request_reset) (struct qlcnic_adapter *, u32);
1741 void (*cancel_idc_work) (struct qlcnic_adapter *);
1742 int (*napi_add)(struct qlcnic_adapter *, struct net_device *);
1743 void (*napi_del)(struct qlcnic_adapter *);
1744 void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int);
1745 irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *);
1746 int (*shutdown)(struct pci_dev *);
1747 int (*resume)(struct qlcnic_adapter *);
1748 };
1749
1750 struct qlcnic_mbx_ops {
1751 int (*enqueue_cmd) (struct qlcnic_adapter *,
1752 struct qlcnic_cmd_args *, unsigned long *);
1753 void (*dequeue_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1754 void (*decode_resp) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1755 void (*encode_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1756 void (*nofity_fw) (struct qlcnic_adapter *, u8);
1757 };
1758
1759 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *);
1760 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *);
1761 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx);
1762 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx);
1763 void qlcnic_update_stats(struct qlcnic_adapter *);
1764
1765 /* Adapter hardware abstraction */
1766 struct qlcnic_hardware_ops {
1767 void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t);
1768 void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t);
1769 int (*read_reg) (struct qlcnic_adapter *, ulong, int *);
1770 int (*write_reg) (struct qlcnic_adapter *, ulong, u32);
1771 void (*get_ocm_win) (struct qlcnic_hardware_context *);
1772 int (*get_mac_address) (struct qlcnic_adapter *, u8 *, u8);
1773 int (*setup_intr) (struct qlcnic_adapter *);
1774 int (*alloc_mbx_args)(struct qlcnic_cmd_args *,
1775 struct qlcnic_adapter *, u32);
1776 int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1777 void (*get_func_no) (struct qlcnic_adapter *);
1778 int (*api_lock) (struct qlcnic_adapter *);
1779 void (*api_unlock) (struct qlcnic_adapter *);
1780 void (*add_sysfs) (struct qlcnic_adapter *);
1781 void (*remove_sysfs) (struct qlcnic_adapter *);
1782 void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *);
1783 int (*create_rx_ctx) (struct qlcnic_adapter *);
1784 int (*create_tx_ctx) (struct qlcnic_adapter *,
1785 struct qlcnic_host_tx_ring *, int);
1786 void (*del_rx_ctx) (struct qlcnic_adapter *);
1787 void (*del_tx_ctx) (struct qlcnic_adapter *,
1788 struct qlcnic_host_tx_ring *);
1789 int (*setup_link_event) (struct qlcnic_adapter *, int);
1790 int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8);
1791 int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *);
1792 int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *);
1793 int (*change_macvlan) (struct qlcnic_adapter *, u8*, u16, u8);
1794 void (*napi_enable) (struct qlcnic_adapter *);
1795 void (*napi_disable) (struct qlcnic_adapter *);
1796 int (*config_intr_coal) (struct qlcnic_adapter *,
1797 struct ethtool_coalesce *);
1798 int (*config_rss) (struct qlcnic_adapter *, int);
1799 int (*config_hw_lro) (struct qlcnic_adapter *, int);
1800 int (*config_loopback) (struct qlcnic_adapter *, u8);
1801 int (*clear_loopback) (struct qlcnic_adapter *, u8);
1802 int (*config_promisc_mode) (struct qlcnic_adapter *, u32);
1803 void (*change_l2_filter) (struct qlcnic_adapter *, u64 *, u16);
1804 int (*get_board_info) (struct qlcnic_adapter *);
1805 void (*set_mac_filter_count) (struct qlcnic_adapter *);
1806 void (*free_mac_list) (struct qlcnic_adapter *);
1807 int (*read_phys_port_id) (struct qlcnic_adapter *);
1808 pci_ers_result_t (*io_error_detected) (struct pci_dev *,
1809 pci_channel_state_t);
1810 pci_ers_result_t (*io_slot_reset) (struct pci_dev *);
1811 void (*io_resume) (struct pci_dev *);
1812 void (*get_beacon_state)(struct qlcnic_adapter *);
1813 void (*enable_sds_intr) (struct qlcnic_adapter *,
1814 struct qlcnic_host_sds_ring *);
1815 void (*disable_sds_intr) (struct qlcnic_adapter *,
1816 struct qlcnic_host_sds_ring *);
1817 void (*enable_tx_intr) (struct qlcnic_adapter *,
1818 struct qlcnic_host_tx_ring *);
1819 void (*disable_tx_intr) (struct qlcnic_adapter *,
1820 struct qlcnic_host_tx_ring *);
1821 u32 (*get_saved_state)(void *, u32);
1822 void (*set_saved_state)(void *, u32, u32);
1823 void (*cache_tmpl_hdr_values)(struct qlcnic_fw_dump *);
1824 u32 (*get_cap_size)(void *, int);
1825 void (*set_sys_info)(void *, int, u32);
1826 void (*store_cap_mask)(void *, u32);
1827 };
1828
1829 extern struct qlcnic_nic_template qlcnic_vf_ops;
1830
1831 static inline bool qlcnic_encap_tx_offload(struct qlcnic_adapter *adapter)
1832 {
1833 return adapter->ahw->extra_capability[0] &
1834 QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD;
1835 }
1836
1837 static inline bool qlcnic_encap_rx_offload(struct qlcnic_adapter *adapter)
1838 {
1839 return adapter->ahw->extra_capability[0] &
1840 QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD;
1841 }
1842
1843 static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter)
1844 {
1845 return adapter->nic_ops->start_firmware(adapter);
1846 }
1847
1848 static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf,
1849 loff_t offset, size_t size)
1850 {
1851 adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size);
1852 }
1853
1854 static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf,
1855 loff_t offset, size_t size)
1856 {
1857 adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size);
1858 }
1859
1860 static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter,
1861 ulong off, u32 data)
1862 {
1863 return adapter->ahw->hw_ops->write_reg(adapter, off, data);
1864 }
1865
1866 static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter,
1867 u8 *mac, u8 function)
1868 {
1869 return adapter->ahw->hw_ops->get_mac_address(adapter, mac, function);
1870 }
1871
1872 static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter)
1873 {
1874 return adapter->ahw->hw_ops->setup_intr(adapter);
1875 }
1876
1877 static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
1878 struct qlcnic_adapter *adapter, u32 arg)
1879 {
1880 return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg);
1881 }
1882
1883 static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1884 struct qlcnic_cmd_args *cmd)
1885 {
1886 if (adapter->ahw->hw_ops->mbx_cmd)
1887 return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd);
1888
1889 return -EIO;
1890 }
1891
1892 static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter)
1893 {
1894 adapter->ahw->hw_ops->get_func_no(adapter);
1895 }
1896
1897 static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter)
1898 {
1899 return adapter->ahw->hw_ops->api_lock(adapter);
1900 }
1901
1902 static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter)
1903 {
1904 adapter->ahw->hw_ops->api_unlock(adapter);
1905 }
1906
1907 static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter)
1908 {
1909 if (adapter->ahw->hw_ops->add_sysfs)
1910 adapter->ahw->hw_ops->add_sysfs(adapter);
1911 }
1912
1913 static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter)
1914 {
1915 if (adapter->ahw->hw_ops->remove_sysfs)
1916 adapter->ahw->hw_ops->remove_sysfs(adapter);
1917 }
1918
1919 static inline void
1920 qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring)
1921 {
1922 sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring);
1923 }
1924
1925 static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
1926 {
1927 return adapter->ahw->hw_ops->create_rx_ctx(adapter);
1928 }
1929
1930 static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
1931 struct qlcnic_host_tx_ring *ptr,
1932 int ring)
1933 {
1934 return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring);
1935 }
1936
1937 static inline void qlcnic_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter)
1938 {
1939 return adapter->ahw->hw_ops->del_rx_ctx(adapter);
1940 }
1941
1942 static inline void qlcnic_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter,
1943 struct qlcnic_host_tx_ring *ptr)
1944 {
1945 return adapter->ahw->hw_ops->del_tx_ctx(adapter, ptr);
1946 }
1947
1948 static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter,
1949 int enable)
1950 {
1951 return adapter->ahw->hw_ops->setup_link_event(adapter, enable);
1952 }
1953
1954 static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter,
1955 struct qlcnic_info *info, u8 id)
1956 {
1957 return adapter->ahw->hw_ops->get_nic_info(adapter, info, id);
1958 }
1959
1960 static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter,
1961 struct qlcnic_pci_info *info)
1962 {
1963 return adapter->ahw->hw_ops->get_pci_info(adapter, info);
1964 }
1965
1966 static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter,
1967 struct qlcnic_info *info)
1968 {
1969 return adapter->ahw->hw_ops->set_nic_info(adapter, info);
1970 }
1971
1972 static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter,
1973 u8 *addr, u16 id, u8 cmd)
1974 {
1975 return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd);
1976 }
1977
1978 static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter,
1979 struct net_device *netdev)
1980 {
1981 return adapter->nic_ops->napi_add(adapter, netdev);
1982 }
1983
1984 static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter)
1985 {
1986 adapter->nic_ops->napi_del(adapter);
1987 }
1988
1989 static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter)
1990 {
1991 adapter->ahw->hw_ops->napi_enable(adapter);
1992 }
1993
1994 static inline int __qlcnic_shutdown(struct pci_dev *pdev)
1995 {
1996 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
1997
1998 return adapter->nic_ops->shutdown(pdev);
1999 }
2000
2001 static inline int __qlcnic_resume(struct qlcnic_adapter *adapter)
2002 {
2003 return adapter->nic_ops->resume(adapter);
2004 }
2005
2006 static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter)
2007 {
2008 adapter->ahw->hw_ops->napi_disable(adapter);
2009 }
2010
2011 static inline int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter,
2012 struct ethtool_coalesce *ethcoal)
2013 {
2014 return adapter->ahw->hw_ops->config_intr_coal(adapter, ethcoal);
2015 }
2016
2017 static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
2018 {
2019 return adapter->ahw->hw_ops->config_rss(adapter, enable);
2020 }
2021
2022 static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter,
2023 int enable)
2024 {
2025 return adapter->ahw->hw_ops->config_hw_lro(adapter, enable);
2026 }
2027
2028 static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
2029 {
2030 return adapter->ahw->hw_ops->config_loopback(adapter, mode);
2031 }
2032
2033 static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
2034 {
2035 return adapter->ahw->hw_ops->clear_loopback(adapter, mode);
2036 }
2037
2038 static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter,
2039 u32 mode)
2040 {
2041 return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode);
2042 }
2043
2044 static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter,
2045 u64 *addr, u16 id)
2046 {
2047 adapter->ahw->hw_ops->change_l2_filter(adapter, addr, id);
2048 }
2049
2050 static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
2051 {
2052 return adapter->ahw->hw_ops->get_board_info(adapter);
2053 }
2054
2055 static inline void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
2056 {
2057 return adapter->ahw->hw_ops->free_mac_list(adapter);
2058 }
2059
2060 static inline void qlcnic_set_mac_filter_count(struct qlcnic_adapter *adapter)
2061 {
2062 if (adapter->ahw->hw_ops->set_mac_filter_count)
2063 adapter->ahw->hw_ops->set_mac_filter_count(adapter);
2064 }
2065
2066 static inline void qlcnic_get_beacon_state(struct qlcnic_adapter *adapter)
2067 {
2068 adapter->ahw->hw_ops->get_beacon_state(adapter);
2069 }
2070
2071 static inline void qlcnic_read_phys_port_id(struct qlcnic_adapter *adapter)
2072 {
2073 if (adapter->ahw->hw_ops->read_phys_port_id)
2074 adapter->ahw->hw_ops->read_phys_port_id(adapter);
2075 }
2076
2077 static inline u32 qlcnic_get_saved_state(struct qlcnic_adapter *adapter,
2078 void *t_hdr, u32 index)
2079 {
2080 return adapter->ahw->hw_ops->get_saved_state(t_hdr, index);
2081 }
2082
2083 static inline void qlcnic_set_saved_state(struct qlcnic_adapter *adapter,
2084 void *t_hdr, u32 index, u32 value)
2085 {
2086 adapter->ahw->hw_ops->set_saved_state(t_hdr, index, value);
2087 }
2088
2089 static inline void qlcnic_cache_tmpl_hdr_values(struct qlcnic_adapter *adapter,
2090 struct qlcnic_fw_dump *fw_dump)
2091 {
2092 adapter->ahw->hw_ops->cache_tmpl_hdr_values(fw_dump);
2093 }
2094
2095 static inline u32 qlcnic_get_cap_size(struct qlcnic_adapter *adapter,
2096 void *tmpl_hdr, int index)
2097 {
2098 return adapter->ahw->hw_ops->get_cap_size(tmpl_hdr, index);
2099 }
2100
2101 static inline void qlcnic_set_sys_info(struct qlcnic_adapter *adapter,
2102 void *tmpl_hdr, int idx, u32 value)
2103 {
2104 adapter->ahw->hw_ops->set_sys_info(tmpl_hdr, idx, value);
2105 }
2106
2107 static inline void qlcnic_store_cap_mask(struct qlcnic_adapter *adapter,
2108 void *tmpl_hdr, u32 mask)
2109 {
2110 adapter->ahw->hw_ops->store_cap_mask(tmpl_hdr, mask);
2111 }
2112
2113 static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter,
2114 u32 key)
2115 {
2116 if (adapter->nic_ops->request_reset)
2117 adapter->nic_ops->request_reset(adapter, key);
2118 }
2119
2120 static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter)
2121 {
2122 if (adapter->nic_ops->cancel_idc_work)
2123 adapter->nic_ops->cancel_idc_work(adapter);
2124 }
2125
2126 static inline irqreturn_t
2127 qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter)
2128 {
2129 return adapter->nic_ops->clear_legacy_intr(adapter);
2130 }
2131
2132 static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state,
2133 u32 rate)
2134 {
2135 return adapter->nic_ops->config_led(adapter, state, rate);
2136 }
2137
2138 static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter,
2139 __be32 ip, int cmd)
2140 {
2141 adapter->nic_ops->config_ipaddr(adapter, ip, cmd);
2142 }
2143
2144 static inline bool qlcnic_check_multi_tx(struct qlcnic_adapter *adapter)
2145 {
2146 return test_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state);
2147 }
2148
2149 static inline void
2150 qlcnic_82xx_enable_tx_intr(struct qlcnic_adapter *adapter,
2151 struct qlcnic_host_tx_ring *tx_ring)
2152 {
2153 if (qlcnic_check_multi_tx(adapter) &&
2154 !adapter->ahw->diag_test)
2155 writel(0x0, tx_ring->crb_intr_mask);
2156 }
2157
2158 static inline void
2159 qlcnic_82xx_disable_tx_intr(struct qlcnic_adapter *adapter,
2160 struct qlcnic_host_tx_ring *tx_ring)
2161 {
2162 if (qlcnic_check_multi_tx(adapter) &&
2163 !adapter->ahw->diag_test)
2164 writel(1, tx_ring->crb_intr_mask);
2165 }
2166
2167 static inline void
2168 qlcnic_83xx_enable_tx_intr(struct qlcnic_adapter *adapter,
2169 struct qlcnic_host_tx_ring *tx_ring)
2170 {
2171 writel(0, tx_ring->crb_intr_mask);
2172 }
2173
2174 static inline void
2175 qlcnic_83xx_disable_tx_intr(struct qlcnic_adapter *adapter,
2176 struct qlcnic_host_tx_ring *tx_ring)
2177 {
2178 writel(1, tx_ring->crb_intr_mask);
2179 }
2180
2181 /* Enable MSI-x and INT-x interrupts */
2182 static inline void
2183 qlcnic_83xx_enable_sds_intr(struct qlcnic_adapter *adapter,
2184 struct qlcnic_host_sds_ring *sds_ring)
2185 {
2186 writel(0, sds_ring->crb_intr_mask);
2187 }
2188
2189 /* Disable MSI-x and INT-x interrupts */
2190 static inline void
2191 qlcnic_83xx_disable_sds_intr(struct qlcnic_adapter *adapter,
2192 struct qlcnic_host_sds_ring *sds_ring)
2193 {
2194 writel(1, sds_ring->crb_intr_mask);
2195 }
2196
2197 static inline void qlcnic_disable_multi_tx(struct qlcnic_adapter *adapter)
2198 {
2199 test_and_clear_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state);
2200 adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
2201 }
2202
2203 /* When operating in a muti tx mode, driver needs to write 0x1
2204 * to src register, instead of 0x0 to disable receiving interrupt.
2205 */
2206 static inline void
2207 qlcnic_82xx_disable_sds_intr(struct qlcnic_adapter *adapter,
2208 struct qlcnic_host_sds_ring *sds_ring)
2209 {
2210 if (qlcnic_check_multi_tx(adapter) &&
2211 !adapter->ahw->diag_test &&
2212 (adapter->flags & QLCNIC_MSIX_ENABLED))
2213 writel(0x1, sds_ring->crb_intr_mask);
2214 else
2215 writel(0, sds_ring->crb_intr_mask);
2216 }
2217
2218 static inline void qlcnic_enable_sds_intr(struct qlcnic_adapter *adapter,
2219 struct qlcnic_host_sds_ring *sds_ring)
2220 {
2221 if (adapter->ahw->hw_ops->enable_sds_intr)
2222 adapter->ahw->hw_ops->enable_sds_intr(adapter, sds_ring);
2223 }
2224
2225 static inline void
2226 qlcnic_disable_sds_intr(struct qlcnic_adapter *adapter,
2227 struct qlcnic_host_sds_ring *sds_ring)
2228 {
2229 if (adapter->ahw->hw_ops->disable_sds_intr)
2230 adapter->ahw->hw_ops->disable_sds_intr(adapter, sds_ring);
2231 }
2232
2233 static inline void qlcnic_enable_tx_intr(struct qlcnic_adapter *adapter,
2234 struct qlcnic_host_tx_ring *tx_ring)
2235 {
2236 if (adapter->ahw->hw_ops->enable_tx_intr)
2237 adapter->ahw->hw_ops->enable_tx_intr(adapter, tx_ring);
2238 }
2239
2240 static inline void qlcnic_disable_tx_intr(struct qlcnic_adapter *adapter,
2241 struct qlcnic_host_tx_ring *tx_ring)
2242 {
2243 if (adapter->ahw->hw_ops->disable_tx_intr)
2244 adapter->ahw->hw_ops->disable_tx_intr(adapter, tx_ring);
2245 }
2246
2247 /* When operating in a muti tx mode, driver needs to write 0x0
2248 * to src register, instead of 0x1 to enable receiving interrupts.
2249 */
2250 static inline void
2251 qlcnic_82xx_enable_sds_intr(struct qlcnic_adapter *adapter,
2252 struct qlcnic_host_sds_ring *sds_ring)
2253 {
2254 if (qlcnic_check_multi_tx(adapter) &&
2255 !adapter->ahw->diag_test &&
2256 (adapter->flags & QLCNIC_MSIX_ENABLED))
2257 writel(0, sds_ring->crb_intr_mask);
2258 else
2259 writel(0x1, sds_ring->crb_intr_mask);
2260
2261 if (!QLCNIC_IS_MSI_FAMILY(adapter))
2262 writel(0xfbff, adapter->tgt_mask_reg);
2263 }
2264
2265 static inline int qlcnic_get_diag_lock(struct qlcnic_adapter *adapter)
2266 {
2267 return test_and_set_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2268 }
2269
2270 static inline void qlcnic_release_diag_lock(struct qlcnic_adapter *adapter)
2271 {
2272 clear_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2273 }
2274
2275 static inline int qlcnic_check_diag_status(struct qlcnic_adapter *adapter)
2276 {
2277 return test_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2278 }
2279
2280 extern const struct ethtool_ops qlcnic_sriov_vf_ethtool_ops;
2281 extern const struct ethtool_ops qlcnic_ethtool_ops;
2282 extern const struct ethtool_ops qlcnic_ethtool_failed_ops;
2283
2284 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
2285 if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \
2286 printk(KERN_INFO "%s: %s: " _fmt, \
2287 dev_name(&adapter->pdev->dev), \
2288 __func__, ##_args); \
2289 } while (0)
2290
2291 #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020
2292 #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030
2293 #define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430
2294 #define PCI_DEVICE_ID_QLOGIC_QLE8830 0x8830
2295 #define PCI_DEVICE_ID_QLOGIC_VF_QLE8C30 0x8C30
2296 #define PCI_DEVICE_ID_QLOGIC_QLE844X 0x8040
2297 #define PCI_DEVICE_ID_QLOGIC_VF_QLE844X 0x8440
2298
2299 static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter)
2300 {
2301 unsigned short device = adapter->pdev->device;
2302 return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false;
2303 }
2304
2305 static inline bool qlcnic_84xx_check(struct qlcnic_adapter *adapter)
2306 {
2307 unsigned short device = adapter->pdev->device;
2308
2309 return ((device == PCI_DEVICE_ID_QLOGIC_QLE844X) ||
2310 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false;
2311 }
2312
2313 static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter)
2314 {
2315 unsigned short device = adapter->pdev->device;
2316 bool status;
2317
2318 status = ((device == PCI_DEVICE_ID_QLOGIC_QLE834X) ||
2319 (device == PCI_DEVICE_ID_QLOGIC_QLE8830) ||
2320 (device == PCI_DEVICE_ID_QLOGIC_QLE844X) ||
2321 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) ||
2322 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ||
2323 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE8C30)) ? true : false;
2324
2325 return status;
2326 }
2327
2328 static inline bool qlcnic_sriov_pf_check(struct qlcnic_adapter *adapter)
2329 {
2330 return (adapter->ahw->op_mode == QLCNIC_SRIOV_PF_FUNC) ? true : false;
2331 }
2332
2333 static inline bool qlcnic_sriov_vf_check(struct qlcnic_adapter *adapter)
2334 {
2335 unsigned short device = adapter->pdev->device;
2336 bool status;
2337
2338 status = ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ||
2339 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) ||
2340 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE8C30)) ? true : false;
2341
2342 return status;
2343 }
2344
2345 static inline bool qlcnic_83xx_pf_check(struct qlcnic_adapter *adapter)
2346 {
2347 unsigned short device = adapter->pdev->device;
2348
2349 return (device == PCI_DEVICE_ID_QLOGIC_QLE834X) ? true : false;
2350 }
2351
2352 static inline bool qlcnic_83xx_vf_check(struct qlcnic_adapter *adapter)
2353 {
2354 unsigned short device = adapter->pdev->device;
2355
2356 return ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ||
2357 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE8C30)) ? true : false;
2358 }
2359
2360 static inline bool qlcnic_sriov_check(struct qlcnic_adapter *adapter)
2361 {
2362 bool status;
2363
2364 status = (qlcnic_sriov_pf_check(adapter) ||
2365 qlcnic_sriov_vf_check(adapter)) ? true : false;
2366
2367 return status;
2368 }
2369
2370 static inline u32 qlcnic_get_vnic_func_count(struct qlcnic_adapter *adapter)
2371 {
2372 if (qlcnic_84xx_check(adapter))
2373 return QLC_84XX_VNIC_COUNT;
2374 else
2375 return QLC_DEFAULT_VNIC_COUNT;
2376 }
2377
2378 static inline void qlcnic_swap32_buffer(u32 *buffer, int count)
2379 {
2380 #if defined(__BIG_ENDIAN)
2381 u32 *tmp = buffer;
2382 int i;
2383
2384 for (i = 0; i < count; i++) {
2385 *tmp = swab32(*tmp);
2386 tmp++;
2387 }
2388 #endif
2389 }
2390
2391 #ifdef CONFIG_QLCNIC_HWMON
2392 void qlcnic_register_hwmon_dev(struct qlcnic_adapter *);
2393 void qlcnic_unregister_hwmon_dev(struct qlcnic_adapter *);
2394 #else
2395 static inline void qlcnic_register_hwmon_dev(struct qlcnic_adapter *adapter)
2396 {
2397 return;
2398 }
2399 static inline void qlcnic_unregister_hwmon_dev(struct qlcnic_adapter *adapter)
2400 {
2401 return;
2402 }
2403 #endif
2404 #endif /* __QLCNIC_H_ */
Linux kernel - Deliverables
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