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[deliverable/linux.git] / drivers / net / ethernet / smsc / smc91x.h
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, see <http://www.gnu.org/licenses/>.
22 .
23 . Information contained in this file was obtained from the LAN91C111
24 . manual from SMC. To get a copy, if you really want one, you can find
25 . information under www.smsc.com.
26 .
27 . Authors
28 . Erik Stahlman <erik@vt.edu>
29 . Daris A Nevil <dnevil@snmc.com>
30 . Nicolas Pitre <nico@fluxnic.net>
31 .
32 ---------------------------------------------------------------------------*/
33 #ifndef _SMC91X_H_
34 #define _SMC91X_H_
35
36 #include <linux/dmaengine.h>
37 #include <linux/smc91x.h>
38
39 /*
40 * Any 16-bit access is performed with two 8-bit accesses if the hardware
41 * can't do it directly. Most registers are 16-bit so those are mandatory.
42 */
43 #define SMC_outw_b(x, a, r) \
44 do { \
45 unsigned int __val16 = (x); \
46 unsigned int __reg = (r); \
47 SMC_outb(__val16, a, __reg); \
48 SMC_outb(__val16 >> 8, a, __reg + (1 << SMC_IO_SHIFT)); \
49 } while (0)
50
51 #define SMC_inw_b(a, r) \
52 ({ \
53 unsigned int __val16; \
54 unsigned int __reg = r; \
55 __val16 = SMC_inb(a, __reg); \
56 __val16 |= SMC_inb(a, __reg + (1 << SMC_IO_SHIFT)) << 8; \
57 __val16; \
58 })
59
60 /*
61 * Define your architecture specific bus configuration parameters here.
62 */
63
64 #if defined(CONFIG_ARM)
65
66 #include <asm/mach-types.h>
67
68 /* Now the bus width is specified in the platform data
69 * pretend here to support all I/O access types
70 */
71 #define SMC_CAN_USE_8BIT 1
72 #define SMC_CAN_USE_16BIT 1
73 #define SMC_CAN_USE_32BIT 1
74 #define SMC_NOWAIT 1
75
76 #define SMC_IO_SHIFT (lp->io_shift)
77
78 #define SMC_inb(a, r) readb((a) + (r))
79 #define SMC_inw(a, r) \
80 ({ \
81 unsigned int __smc_r = r; \
82 SMC_16BIT(lp) ? readw((a) + __smc_r) : \
83 SMC_8BIT(lp) ? SMC_inw_b(a, __smc_r) : \
84 ({ BUG(); 0; }); \
85 })
86
87 #define SMC_inl(a, r) readl((a) + (r))
88 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
89 #define SMC_outw(v, a, r) \
90 do { \
91 unsigned int __v = v, __smc_r = r; \
92 if (SMC_16BIT(lp)) \
93 __SMC_outw(__v, a, __smc_r); \
94 else if (SMC_8BIT(lp)) \
95 SMC_outw_b(__v, a, __smc_r); \
96 else \
97 BUG(); \
98 } while (0)
99
100 #define SMC_outl(v, a, r) writel(v, (a) + (r))
101 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, l)
102 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, l)
103 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
104 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
105 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
106 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
107 #define SMC_IRQ_FLAGS (-1) /* from resource */
108
109 /* We actually can't write halfwords properly if not word aligned */
110 static inline void __SMC_outw(u16 val, void __iomem *ioaddr, int reg)
111 {
112 if ((machine_is_mainstone() || machine_is_stargate2() ||
113 machine_is_pxa_idp()) && reg & 2) {
114 unsigned int v = val << 16;
115 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
116 writel(v, ioaddr + (reg & ~2));
117 } else {
118 writew(val, ioaddr + reg);
119 }
120 }
121
122 #elif defined(CONFIG_SH_SH4202_MICRODEV)
123
124 #define SMC_CAN_USE_8BIT 0
125 #define SMC_CAN_USE_16BIT 1
126 #define SMC_CAN_USE_32BIT 0
127
128 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
129 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
130 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
131 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
132 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
133 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
134 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
135 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
136 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
137 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
138
139 #define SMC_IRQ_FLAGS (0)
140
141 #elif defined(CONFIG_M32R)
142
143 #define SMC_CAN_USE_8BIT 0
144 #define SMC_CAN_USE_16BIT 1
145 #define SMC_CAN_USE_32BIT 0
146
147 #define SMC_inb(a, r) inb(((u32)a) + (r))
148 #define SMC_inw(a, r) inw(((u32)a) + (r))
149 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
150 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
151 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
152 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
153
154 #define SMC_IRQ_FLAGS (0)
155
156 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
157 #define RPC_LSB_DEFAULT RPC_LED_100_10
158
159 #elif defined(CONFIG_MN10300)
160
161 /*
162 * MN10300/AM33 configuration
163 */
164
165 #include <unit/smc91111.h>
166
167 #elif defined(CONFIG_ATARI)
168
169 #define SMC_CAN_USE_8BIT 1
170 #define SMC_CAN_USE_16BIT 1
171 #define SMC_CAN_USE_32BIT 1
172 #define SMC_NOWAIT 1
173
174 #define SMC_inb(a, r) readb((a) + (r))
175 #define SMC_inw(a, r) readw((a) + (r))
176 #define SMC_inl(a, r) readl((a) + (r))
177 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
178 #define SMC_outw(v, a, r) writew(v, (a) + (r))
179 #define SMC_outl(v, a, r) writel(v, (a) + (r))
180 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
181 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
182 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
183 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
184
185 #define RPC_LSA_DEFAULT RPC_LED_100_10
186 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
187
188 #elif defined(CONFIG_COLDFIRE)
189
190 #define SMC_CAN_USE_8BIT 0
191 #define SMC_CAN_USE_16BIT 1
192 #define SMC_CAN_USE_32BIT 0
193 #define SMC_NOWAIT 1
194
195 static inline void mcf_insw(void *a, unsigned char *p, int l)
196 {
197 u16 *wp = (u16 *) p;
198 while (l-- > 0)
199 *wp++ = readw(a);
200 }
201
202 static inline void mcf_outsw(void *a, unsigned char *p, int l)
203 {
204 u16 *wp = (u16 *) p;
205 while (l-- > 0)
206 writew(*wp++, a);
207 }
208
209 #define SMC_inw(a, r) _swapw(readw((a) + (r)))
210 #define SMC_outw(v, a, r) writew(_swapw(v), (a) + (r))
211 #define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l)
212 #define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l)
213
214 #define SMC_IRQ_FLAGS 0
215
216 #elif defined(CONFIG_H8300)
217 #define SMC_CAN_USE_8BIT 1
218 #define SMC_CAN_USE_16BIT 0
219 #define SMC_CAN_USE_32BIT 0
220 #define SMC_NOWAIT 0
221
222 #define SMC_inb(a, r) ioread8((a) + (r))
223 #define SMC_outb(v, a, r) iowrite8(v, (a) + (r))
224 #define SMC_insb(a, r, p, l) ioread8_rep((a) + (r), p, l)
225 #define SMC_outsb(a, r, p, l) iowrite8_rep((a) + (r), p, l)
226
227 #else
228
229 /*
230 * Default configuration
231 */
232
233 #define SMC_CAN_USE_8BIT 1
234 #define SMC_CAN_USE_16BIT 1
235 #define SMC_CAN_USE_32BIT 1
236 #define SMC_NOWAIT 1
237
238 #define SMC_IO_SHIFT (lp->io_shift)
239
240 #define SMC_inb(a, r) ioread8((a) + (r))
241 #define SMC_inw(a, r) ioread16((a) + (r))
242 #define SMC_inl(a, r) ioread32((a) + (r))
243 #define SMC_outb(v, a, r) iowrite8(v, (a) + (r))
244 #define SMC_outw(v, a, r) iowrite16(v, (a) + (r))
245 #define SMC_outl(v, a, r) iowrite32(v, (a) + (r))
246 #define SMC_insw(a, r, p, l) ioread16_rep((a) + (r), p, l)
247 #define SMC_outsw(a, r, p, l) iowrite16_rep((a) + (r), p, l)
248 #define SMC_insl(a, r, p, l) ioread32_rep((a) + (r), p, l)
249 #define SMC_outsl(a, r, p, l) iowrite32_rep((a) + (r), p, l)
250
251 #define RPC_LSA_DEFAULT RPC_LED_100_10
252 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
253
254 #endif
255
256
257 /* store this information for the driver.. */
258 struct smc_local {
259 /*
260 * If I have to wait until memory is available to send a
261 * packet, I will store the skbuff here, until I get the
262 * desired memory. Then, I'll send it out and free it.
263 */
264 struct sk_buff *pending_tx_skb;
265 struct tasklet_struct tx_task;
266
267 struct gpio_desc *power_gpio;
268 struct gpio_desc *reset_gpio;
269
270 /* version/revision of the SMC91x chip */
271 int version;
272
273 /* Contains the current active transmission mode */
274 int tcr_cur_mode;
275
276 /* Contains the current active receive mode */
277 int rcr_cur_mode;
278
279 /* Contains the current active receive/phy mode */
280 int rpc_cur_mode;
281 int ctl_rfduplx;
282 int ctl_rspeed;
283
284 u32 msg_enable;
285 u32 phy_type;
286 struct mii_if_info mii;
287
288 /* work queue */
289 struct work_struct phy_configure;
290 struct net_device *dev;
291 int work_pending;
292
293 spinlock_t lock;
294
295 #ifdef CONFIG_ARCH_PXA
296 /* DMA needs the physical address of the chip */
297 u_long physaddr;
298 struct device *device;
299 #endif
300 struct dma_chan *dma_chan;
301 void __iomem *base;
302 void __iomem *datacs;
303
304 /* the low address lines on some platforms aren't connected... */
305 int io_shift;
306
307 struct smc91x_platdata cfg;
308 };
309
310 #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
311 #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
312 #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
313
314 #ifdef CONFIG_ARCH_PXA
315 /*
316 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
317 * always happening in irq context so no need to worry about races. TX is
318 * different and probably not worth it for that reason, and not as critical
319 * as RX which can overrun memory and lose packets.
320 */
321 #include <linux/dma-mapping.h>
322 #include <linux/dma/pxa-dma.h>
323
324 #ifdef SMC_insl
325 #undef SMC_insl
326 #define SMC_insl(a, r, p, l) \
327 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
328 static inline void
329 smc_pxa_dma_inpump(struct smc_local *lp, u_char *buf, int len)
330 {
331 dma_addr_t dmabuf;
332 struct dma_async_tx_descriptor *tx;
333 dma_cookie_t cookie;
334 enum dma_status status;
335 struct dma_tx_state state;
336
337 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
338 tx = dmaengine_prep_slave_single(lp->dma_chan, dmabuf, len,
339 DMA_DEV_TO_MEM, 0);
340 if (tx) {
341 cookie = dmaengine_submit(tx);
342 dma_async_issue_pending(lp->dma_chan);
343 do {
344 status = dmaengine_tx_status(lp->dma_chan, cookie,
345 &state);
346 cpu_relax();
347 } while (status != DMA_COMPLETE && status != DMA_ERROR &&
348 state.residue);
349 dmaengine_terminate_all(lp->dma_chan);
350 }
351 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
352 }
353
354 static inline void
355 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
356 u_char *buf, int len)
357 {
358 struct dma_slave_config config;
359 int ret;
360
361 /* fallback if no DMA available */
362 if (!lp->dma_chan) {
363 readsl(ioaddr + reg, buf, len);
364 return;
365 }
366
367 /* 64 bit alignment is required for memory to memory DMA */
368 if ((long)buf & 4) {
369 *((u32 *)buf) = SMC_inl(ioaddr, reg);
370 buf += 4;
371 len--;
372 }
373
374 memset(&config, 0, sizeof(config));
375 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
376 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
377 config.src_addr = lp->physaddr + reg;
378 config.dst_addr = lp->physaddr + reg;
379 config.src_maxburst = 32;
380 config.dst_maxburst = 32;
381 ret = dmaengine_slave_config(lp->dma_chan, &config);
382 if (ret) {
383 dev_err(lp->device, "dma channel configuration failed: %d\n",
384 ret);
385 return;
386 }
387
388 len *= 4;
389 smc_pxa_dma_inpump(lp, buf, len);
390 }
391 #endif
392
393 #ifdef SMC_insw
394 #undef SMC_insw
395 #define SMC_insw(a, r, p, l) \
396 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
397 static inline void
398 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
399 u_char *buf, int len)
400 {
401 struct dma_slave_config config;
402 int ret;
403
404 /* fallback if no DMA available */
405 if (!lp->dma_chan) {
406 readsw(ioaddr + reg, buf, len);
407 return;
408 }
409
410 /* 64 bit alignment is required for memory to memory DMA */
411 while ((long)buf & 6) {
412 *((u16 *)buf) = SMC_inw(ioaddr, reg);
413 buf += 2;
414 len--;
415 }
416
417 memset(&config, 0, sizeof(config));
418 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
419 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
420 config.src_addr = lp->physaddr + reg;
421 config.dst_addr = lp->physaddr + reg;
422 config.src_maxburst = 32;
423 config.dst_maxburst = 32;
424 ret = dmaengine_slave_config(lp->dma_chan, &config);
425 if (ret) {
426 dev_err(lp->device, "dma channel configuration failed: %d\n",
427 ret);
428 return;
429 }
430
431 len *= 2;
432 smc_pxa_dma_inpump(lp, buf, len);
433 }
434 #endif
435
436 #endif /* CONFIG_ARCH_PXA */
437
438
439 /*
440 * Everything a particular hardware setup needs should have been defined
441 * at this point. Add stubs for the undefined cases, mainly to avoid
442 * compilation warnings since they'll be optimized away, or to prevent buggy
443 * use of them.
444 */
445
446 #if ! SMC_CAN_USE_32BIT
447 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
448 #define SMC_outl(x, ioaddr, reg) BUG()
449 #define SMC_insl(a, r, p, l) BUG()
450 #define SMC_outsl(a, r, p, l) BUG()
451 #endif
452
453 #if !defined(SMC_insl) || !defined(SMC_outsl)
454 #define SMC_insl(a, r, p, l) BUG()
455 #define SMC_outsl(a, r, p, l) BUG()
456 #endif
457
458 #if ! SMC_CAN_USE_16BIT
459
460 #define SMC_outw(x, ioaddr, reg) SMC_outw_b(x, ioaddr, reg)
461 #define SMC_inw(ioaddr, reg) SMC_inw_b(ioaddr, reg)
462 #define SMC_insw(a, r, p, l) BUG()
463 #define SMC_outsw(a, r, p, l) BUG()
464
465 #endif
466
467 #if !defined(SMC_insw) || !defined(SMC_outsw)
468 #define SMC_insw(a, r, p, l) BUG()
469 #define SMC_outsw(a, r, p, l) BUG()
470 #endif
471
472 #if ! SMC_CAN_USE_8BIT
473 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
474 #define SMC_outb(x, ioaddr, reg) BUG()
475 #define SMC_insb(a, r, p, l) BUG()
476 #define SMC_outsb(a, r, p, l) BUG()
477 #endif
478
479 #if !defined(SMC_insb) || !defined(SMC_outsb)
480 #define SMC_insb(a, r, p, l) BUG()
481 #define SMC_outsb(a, r, p, l) BUG()
482 #endif
483
484 #ifndef SMC_CAN_USE_DATACS
485 #define SMC_CAN_USE_DATACS 0
486 #endif
487
488 #ifndef SMC_IO_SHIFT
489 #define SMC_IO_SHIFT 0
490 #endif
491
492 #ifndef SMC_IRQ_FLAGS
493 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
494 #endif
495
496 #ifndef SMC_INTERRUPT_PREAMBLE
497 #define SMC_INTERRUPT_PREAMBLE
498 #endif
499
500
501 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
502 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
503 #define SMC_DATA_EXTENT (4)
504
505 /*
506 . Bank Select Register:
507 .
508 . yyyy yyyy 0000 00xx
509 . xx = bank number
510 . yyyy yyyy = 0x33, for identification purposes.
511 */
512 #define BANK_SELECT (14 << SMC_IO_SHIFT)
513
514
515 // Transmit Control Register
516 /* BANK 0 */
517 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
518 #define TCR_ENABLE 0x0001 // When 1 we can transmit
519 #define TCR_LOOP 0x0002 // Controls output pin LBK
520 #define TCR_FORCOL 0x0004 // When 1 will force a collision
521 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
522 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
523 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
524 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
525 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
526 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
527 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
528
529 #define TCR_CLEAR 0 /* do NOTHING */
530 /* the default settings for the TCR register : */
531 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
532
533
534 // EPH Status Register
535 /* BANK 0 */
536 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
537 #define ES_TX_SUC 0x0001 // Last TX was successful
538 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
539 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
540 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
541 #define ES_16COL 0x0010 // 16 Collisions Reached
542 #define ES_SQET 0x0020 // Signal Quality Error Test
543 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
544 #define ES_TXDEFR 0x0080 // Transmit Deferred
545 #define ES_LATCOL 0x0200 // Late collision detected on last tx
546 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
547 #define ES_EXC_DEF 0x0800 // Excessive Deferral
548 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
549 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
550 #define ES_TXUNRN 0x8000 // Tx Underrun
551
552
553 // Receive Control Register
554 /* BANK 0 */
555 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
556 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
557 #define RCR_PRMS 0x0002 // Enable promiscuous mode
558 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
559 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
560 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
561 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
562 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
563 #define RCR_SOFTRST 0x8000 // resets the chip
564
565 /* the normal settings for the RCR register : */
566 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
567 #define RCR_CLEAR 0x0 // set it to a base state
568
569
570 // Counter Register
571 /* BANK 0 */
572 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
573
574
575 // Memory Information Register
576 /* BANK 0 */
577 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
578
579
580 // Receive/Phy Control Register
581 /* BANK 0 */
582 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
583 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
584 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
585 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
586 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
587 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
588
589 #ifndef RPC_LSA_DEFAULT
590 #define RPC_LSA_DEFAULT RPC_LED_100
591 #endif
592 #ifndef RPC_LSB_DEFAULT
593 #define RPC_LSB_DEFAULT RPC_LED_FD
594 #endif
595
596 #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
597
598
599 /* Bank 0 0x0C is reserved */
600
601 // Bank Select Register
602 /* All Banks */
603 #define BSR_REG 0x000E
604
605
606 // Configuration Reg
607 /* BANK 1 */
608 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
609 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
610 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
611 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
612 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
613
614 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
615 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
616
617
618 // Base Address Register
619 /* BANK 1 */
620 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
621
622
623 // Individual Address Registers
624 /* BANK 1 */
625 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
626 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
627 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
628
629
630 // General Purpose Register
631 /* BANK 1 */
632 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
633
634
635 // Control Register
636 /* BANK 1 */
637 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
638 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
639 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
640 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
641 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
642 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
643 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
644 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
645 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
646
647
648 // MMU Command Register
649 /* BANK 2 */
650 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
651 #define MC_BUSY 1 // When 1 the last release has not completed
652 #define MC_NOP (0<<5) // No Op
653 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
654 #define MC_RESET (2<<5) // Reset MMU to initial state
655 #define MC_REMOVE (3<<5) // Remove the current rx packet
656 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
657 #define MC_FREEPKT (5<<5) // Release packet in PNR register
658 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
659 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
660
661
662 // Packet Number Register
663 /* BANK 2 */
664 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
665
666
667 // Allocation Result Register
668 /* BANK 2 */
669 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
670 #define AR_FAILED 0x80 // Alocation Failed
671
672
673 // TX FIFO Ports Register
674 /* BANK 2 */
675 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
676 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
677
678 // RX FIFO Ports Register
679 /* BANK 2 */
680 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
681 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
682
683 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
684
685 // Pointer Register
686 /* BANK 2 */
687 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
688 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
689 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
690 #define PTR_READ 0x2000 // When 1 the operation is a read
691
692
693 // Data Register
694 /* BANK 2 */
695 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
696
697
698 // Interrupt Status/Acknowledge Register
699 /* BANK 2 */
700 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
701
702
703 // Interrupt Mask Register
704 /* BANK 2 */
705 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
706 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
707 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
708 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
709 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
710 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
711 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
712 #define IM_TX_INT 0x02 // Transmit Interrupt
713 #define IM_RCV_INT 0x01 // Receive Interrupt
714
715
716 // Multicast Table Registers
717 /* BANK 3 */
718 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
719 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
720 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
721 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
722
723
724 // Management Interface Register (MII)
725 /* BANK 3 */
726 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
727 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
728 #define MII_MDOE 0x0008 // MII Output Enable
729 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
730 #define MII_MDI 0x0002 // MII Input, pin MDI
731 #define MII_MDO 0x0001 // MII Output, pin MDO
732
733
734 // Revision Register
735 /* BANK 3 */
736 /* ( hi: chip id low: rev # ) */
737 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
738
739
740 // Early RCV Register
741 /* BANK 3 */
742 /* this is NOT on SMC9192 */
743 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
744 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
745 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
746
747
748 // External Register
749 /* BANK 7 */
750 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
751
752
753 #define CHIP_9192 3
754 #define CHIP_9194 4
755 #define CHIP_9195 5
756 #define CHIP_9196 6
757 #define CHIP_91100 7
758 #define CHIP_91100FD 8
759 #define CHIP_91111FD 9
760
761 static const char * chip_ids[ 16 ] = {
762 NULL, NULL, NULL,
763 /* 3 */ "SMC91C90/91C92",
764 /* 4 */ "SMC91C94",
765 /* 5 */ "SMC91C95",
766 /* 6 */ "SMC91C96",
767 /* 7 */ "SMC91C100",
768 /* 8 */ "SMC91C100FD",
769 /* 9 */ "SMC91C11xFD",
770 NULL, NULL, NULL,
771 NULL, NULL, NULL};
772
773
774 /*
775 . Receive status bits
776 */
777 #define RS_ALGNERR 0x8000
778 #define RS_BRODCAST 0x4000
779 #define RS_BADCRC 0x2000
780 #define RS_ODDFRAME 0x1000
781 #define RS_TOOLONG 0x0800
782 #define RS_TOOSHORT 0x0400
783 #define RS_MULTICAST 0x0001
784 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
785
786
787 /*
788 * PHY IDs
789 * LAN83C183 == LAN91C111 Internal PHY
790 */
791 #define PHY_LAN83C183 0x0016f840
792 #define PHY_LAN83C180 0x02821c50
793
794 /*
795 * PHY Register Addresses (LAN91C111 Internal PHY)
796 *
797 * Generic PHY registers can be found in <linux/mii.h>
798 *
799 * These phy registers are specific to our on-board phy.
800 */
801
802 // PHY Configuration Register 1
803 #define PHY_CFG1_REG 0x10
804 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
805 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
806 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
807 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
808 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
809 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
810 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
811 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
812 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
813 #define PHY_CFG1_TLVL_MASK 0x003C
814 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
815
816
817 // PHY Configuration Register 2
818 #define PHY_CFG2_REG 0x11
819 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
820 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
821 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
822 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
823
824 // PHY Status Output (and Interrupt status) Register
825 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
826 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
827 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
828 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
829 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
830 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
831 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
832 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
833 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
834 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
835 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
836
837 // PHY Interrupt/Status Mask Register
838 #define PHY_MASK_REG 0x13 // Interrupt Mask
839 // Uses the same bit definitions as PHY_INT_REG
840
841
842 /*
843 * SMC91C96 ethernet config and status registers.
844 * These are in the "attribute" space.
845 */
846 #define ECOR 0x8000
847 #define ECOR_RESET 0x80
848 #define ECOR_LEVEL_IRQ 0x40
849 #define ECOR_WR_ATTRIB 0x04
850 #define ECOR_ENABLE 0x01
851
852 #define ECSR 0x8002
853 #define ECSR_IOIS8 0x20
854 #define ECSR_PWRDWN 0x04
855 #define ECSR_INT 0x02
856
857 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
858
859
860 /*
861 * Macros to abstract register access according to the data bus
862 * capabilities. Please use those and not the in/out primitives.
863 * Note: the following macros do *not* select the bank -- this must
864 * be done separately as needed in the main code. The SMC_REG() macro
865 * only uses the bank argument for debugging purposes (when enabled).
866 *
867 * Note: despite inline functions being safer, everything leading to this
868 * should preferably be macros to let BUG() display the line number in
869 * the core source code since we're interested in the top call site
870 * not in any inline function location.
871 */
872
873 #if SMC_DEBUG > 0
874 #define SMC_REG(lp, reg, bank) \
875 ({ \
876 int __b = SMC_CURRENT_BANK(lp); \
877 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
878 pr_err("%s: bank reg screwed (0x%04x)\n", \
879 CARDNAME, __b); \
880 BUG(); \
881 } \
882 reg<<SMC_IO_SHIFT; \
883 })
884 #else
885 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
886 #endif
887
888 /*
889 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
890 * aligned to a 32 bit boundary. I tell you that does exist!
891 * Fortunately the affected register accesses can be easily worked around
892 * since we can write zeroes to the preceding 16 bits without adverse
893 * effects and use a 32-bit access.
894 *
895 * Enforce it on any 32-bit capable setup for now.
896 */
897 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
898
899 #define SMC_GET_PN(lp) \
900 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
901 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
902
903 #define SMC_SET_PN(lp, x) \
904 do { \
905 if (SMC_MUST_ALIGN_WRITE(lp)) \
906 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
907 else if (SMC_8BIT(lp)) \
908 SMC_outb(x, ioaddr, PN_REG(lp)); \
909 else \
910 SMC_outw(x, ioaddr, PN_REG(lp)); \
911 } while (0)
912
913 #define SMC_GET_AR(lp) \
914 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
915 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
916
917 #define SMC_GET_TXFIFO(lp) \
918 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
919 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
920
921 #define SMC_GET_RXFIFO(lp) \
922 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
923 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
924
925 #define SMC_GET_INT(lp) \
926 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
927 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
928
929 #define SMC_ACK_INT(lp, x) \
930 do { \
931 if (SMC_8BIT(lp)) \
932 SMC_outb(x, ioaddr, INT_REG(lp)); \
933 else { \
934 unsigned long __flags; \
935 int __mask; \
936 local_irq_save(__flags); \
937 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
938 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
939 local_irq_restore(__flags); \
940 } \
941 } while (0)
942
943 #define SMC_GET_INT_MASK(lp) \
944 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
945 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
946
947 #define SMC_SET_INT_MASK(lp, x) \
948 do { \
949 if (SMC_8BIT(lp)) \
950 SMC_outb(x, ioaddr, IM_REG(lp)); \
951 else \
952 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
953 } while (0)
954
955 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
956
957 #define SMC_SELECT_BANK(lp, x) \
958 do { \
959 if (SMC_MUST_ALIGN_WRITE(lp)) \
960 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
961 else \
962 SMC_outw(x, ioaddr, BANK_SELECT); \
963 } while (0)
964
965 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
966
967 #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
968
969 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
970
971 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
972
973 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
974
975 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
976
977 #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
978
979 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
980
981 #define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp))
982
983 #define SMC_SET_GP(lp, x) \
984 do { \
985 if (SMC_MUST_ALIGN_WRITE(lp)) \
986 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
987 else \
988 SMC_outw(x, ioaddr, GP_REG(lp)); \
989 } while (0)
990
991 #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
992
993 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
994
995 #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
996
997 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
998
999 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1000
1001 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
1002
1003 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
1004
1005 #define SMC_SET_PTR(lp, x) \
1006 do { \
1007 if (SMC_MUST_ALIGN_WRITE(lp)) \
1008 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
1009 else \
1010 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1011 } while (0)
1012
1013 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1014
1015 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
1016
1017 #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
1018
1019 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
1020
1021 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
1022
1023 #define SMC_SET_RPC(lp, x) \
1024 do { \
1025 if (SMC_MUST_ALIGN_WRITE(lp)) \
1026 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1027 else \
1028 SMC_outw(x, ioaddr, RPC_REG(lp)); \
1029 } while (0)
1030
1031 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1032
1033 #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1034
1035 #ifndef SMC_GET_MAC_ADDR
1036 #define SMC_GET_MAC_ADDR(lp, addr) \
1037 do { \
1038 unsigned int __v; \
1039 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1040 addr[0] = __v; addr[1] = __v >> 8; \
1041 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1042 addr[2] = __v; addr[3] = __v >> 8; \
1043 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1044 addr[4] = __v; addr[5] = __v >> 8; \
1045 } while (0)
1046 #endif
1047
1048 #define SMC_SET_MAC_ADDR(lp, addr) \
1049 do { \
1050 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1051 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1052 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1053 } while (0)
1054
1055 #define SMC_SET_MCAST(lp, x) \
1056 do { \
1057 const unsigned char *mt = (x); \
1058 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1059 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1060 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1061 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1062 } while (0)
1063
1064 #define SMC_PUT_PKT_HDR(lp, status, length) \
1065 do { \
1066 if (SMC_32BIT(lp)) \
1067 SMC_outl((status) | (length)<<16, ioaddr, \
1068 DATA_REG(lp)); \
1069 else { \
1070 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1071 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1072 } \
1073 } while (0)
1074
1075 #define SMC_GET_PKT_HDR(lp, status, length) \
1076 do { \
1077 if (SMC_32BIT(lp)) { \
1078 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1079 (status) = __val & 0xffff; \
1080 (length) = __val >> 16; \
1081 } else { \
1082 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1083 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1084 } \
1085 } while (0)
1086
1087 #define SMC_PUSH_DATA(lp, p, l) \
1088 do { \
1089 if (SMC_32BIT(lp)) { \
1090 void *__ptr = (p); \
1091 int __len = (l); \
1092 void __iomem *__ioaddr = ioaddr; \
1093 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1094 __len -= 2; \
1095 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1096 __ptr += 2; \
1097 } \
1098 if (SMC_CAN_USE_DATACS && lp->datacs) \
1099 __ioaddr = lp->datacs; \
1100 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1101 if (__len & 2) { \
1102 __ptr += (__len & ~3); \
1103 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1104 } \
1105 } else if (SMC_16BIT(lp)) \
1106 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1107 else if (SMC_8BIT(lp)) \
1108 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1109 } while (0)
1110
1111 #define SMC_PULL_DATA(lp, p, l) \
1112 do { \
1113 if (SMC_32BIT(lp)) { \
1114 void *__ptr = (p); \
1115 int __len = (l); \
1116 void __iomem *__ioaddr = ioaddr; \
1117 if ((unsigned long)__ptr & 2) { \
1118 /* \
1119 * We want 32bit alignment here. \
1120 * Since some buses perform a full \
1121 * 32bit fetch even for 16bit data \
1122 * we can't use SMC_inw() here. \
1123 * Back both source (on-chip) and \
1124 * destination pointers of 2 bytes. \
1125 * This is possible since the call to \
1126 * SMC_GET_PKT_HDR() already advanced \
1127 * the source pointer of 4 bytes, and \
1128 * the skb_reserve(skb, 2) advanced \
1129 * the destination pointer of 2 bytes. \
1130 */ \
1131 __ptr -= 2; \
1132 __len += 2; \
1133 SMC_SET_PTR(lp, \
1134 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1135 } \
1136 if (SMC_CAN_USE_DATACS && lp->datacs) \
1137 __ioaddr = lp->datacs; \
1138 __len += 2; \
1139 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1140 } else if (SMC_16BIT(lp)) \
1141 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1142 else if (SMC_8BIT(lp)) \
1143 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
1144 } while (0)
1145
1146 #endif /* _SMC91X_H_ */
Linux kernel - Deliverables
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