1 /* Copyright Altera Corporation (C) 2014. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License, version 2,
5 * as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 * Adopted from dwmac-sti.c
18 #include <linux/mfd/syscon.h>
20 #include <linux/of_address.h>
21 #include <linux/of_net.h>
22 #include <linux/phy.h>
23 #include <linux/regmap.h>
24 #include <linux/reset.h>
25 #include <linux/stmmac.h>
28 #include "stmmac_platform.h"
30 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
31 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
32 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
33 #define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
34 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
35 #define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010
37 #define SYSMGR_FPGAGRP_MODULE_REG 0x00000028
38 #define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004
40 #define EMAC_SPLITTER_CTRL_REG 0x0
41 #define EMAC_SPLITTER_CTRL_SPEED_MASK 0x3
42 #define EMAC_SPLITTER_CTRL_SPEED_10 0x2
43 #define EMAC_SPLITTER_CTRL_SPEED_100 0x3
44 #define EMAC_SPLITTER_CTRL_SPEED_1000 0x0
46 struct socfpga_dwmac
{
51 struct regmap
*sys_mgr_base_addr
;
52 struct reset_control
*stmmac_rst
;
53 void __iomem
*splitter_base
;
57 static void socfpga_dwmac_fix_mac_speed(void *priv
, unsigned int speed
)
59 struct socfpga_dwmac
*dwmac
= (struct socfpga_dwmac
*)priv
;
60 void __iomem
*splitter_base
= dwmac
->splitter_base
;
66 val
= readl(splitter_base
+ EMAC_SPLITTER_CTRL_REG
);
67 val
&= ~EMAC_SPLITTER_CTRL_SPEED_MASK
;
71 val
|= EMAC_SPLITTER_CTRL_SPEED_1000
;
74 val
|= EMAC_SPLITTER_CTRL_SPEED_100
;
77 val
|= EMAC_SPLITTER_CTRL_SPEED_10
;
83 writel(val
, splitter_base
+ EMAC_SPLITTER_CTRL_REG
);
86 static int socfpga_dwmac_parse_data(struct socfpga_dwmac
*dwmac
, struct device
*dev
)
88 struct device_node
*np
= dev
->of_node
;
89 struct regmap
*sys_mgr_base_addr
;
90 u32 reg_offset
, reg_shift
;
92 struct device_node
*np_splitter
;
93 struct resource res_splitter
;
95 dwmac
->stmmac_rst
= devm_reset_control_get(dev
,
96 STMMAC_RESOURCE_NAME
);
97 if (IS_ERR(dwmac
->stmmac_rst
)) {
98 dev_info(dev
, "Could not get reset control!\n");
99 if (PTR_ERR(dwmac
->stmmac_rst
) == -EPROBE_DEFER
)
100 return -EPROBE_DEFER
;
101 dwmac
->stmmac_rst
= NULL
;
104 dwmac
->interface
= of_get_phy_mode(np
);
106 sys_mgr_base_addr
= syscon_regmap_lookup_by_phandle(np
, "altr,sysmgr-syscon");
107 if (IS_ERR(sys_mgr_base_addr
)) {
108 dev_info(dev
, "No sysmgr-syscon node found\n");
109 return PTR_ERR(sys_mgr_base_addr
);
112 ret
= of_property_read_u32_index(np
, "altr,sysmgr-syscon", 1, ®_offset
);
114 dev_info(dev
, "Could not read reg_offset from sysmgr-syscon!\n");
118 ret
= of_property_read_u32_index(np
, "altr,sysmgr-syscon", 2, ®_shift
);
120 dev_info(dev
, "Could not read reg_shift from sysmgr-syscon!\n");
124 dwmac
->f2h_ptp_ref_clk
= of_property_read_bool(np
, "altr,f2h_ptp_ref_clk");
126 np_splitter
= of_parse_phandle(np
, "altr,emac-splitter", 0);
128 if (of_address_to_resource(np_splitter
, 0, &res_splitter
)) {
129 dev_info(dev
, "Missing emac splitter address\n");
133 dwmac
->splitter_base
= devm_ioremap_resource(dev
, &res_splitter
);
134 if (IS_ERR(dwmac
->splitter_base
)) {
135 dev_info(dev
, "Failed to mapping emac splitter\n");
136 return PTR_ERR(dwmac
->splitter_base
);
140 dwmac
->reg_offset
= reg_offset
;
141 dwmac
->reg_shift
= reg_shift
;
142 dwmac
->sys_mgr_base_addr
= sys_mgr_base_addr
;
148 static int socfpga_dwmac_setup(struct socfpga_dwmac
*dwmac
)
150 struct regmap
*sys_mgr_base_addr
= dwmac
->sys_mgr_base_addr
;
151 int phymode
= dwmac
->interface
;
152 u32 reg_offset
= dwmac
->reg_offset
;
153 u32 reg_shift
= dwmac
->reg_shift
;
154 u32 ctrl
, val
, module
;
157 case PHY_INTERFACE_MODE_RGMII
:
158 case PHY_INTERFACE_MODE_RGMII_ID
:
159 val
= SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII
;
161 case PHY_INTERFACE_MODE_MII
:
162 case PHY_INTERFACE_MODE_GMII
:
163 val
= SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII
;
166 dev_err(dwmac
->dev
, "bad phy mode %d\n", phymode
);
170 /* Overwrite val to GMII if splitter core is enabled. The phymode here
171 * is the actual phy mode on phy hardware, but phy interface from
174 if (dwmac
->splitter_base
)
175 val
= SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII
;
177 regmap_read(sys_mgr_base_addr
, reg_offset
, &ctrl
);
178 ctrl
&= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK
<< reg_shift
);
179 ctrl
|= val
<< reg_shift
;
181 if (dwmac
->f2h_ptp_ref_clk
) {
182 ctrl
|= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK
<< (reg_shift
/ 2);
183 regmap_read(sys_mgr_base_addr
, SYSMGR_FPGAGRP_MODULE_REG
,
185 module
|= (SYSMGR_FPGAGRP_MODULE_EMAC
<< (reg_shift
/ 2));
186 regmap_write(sys_mgr_base_addr
, SYSMGR_FPGAGRP_MODULE_REG
,
189 ctrl
&= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK
<< (reg_shift
/ 2));
192 regmap_write(sys_mgr_base_addr
, reg_offset
, ctrl
);
197 static void socfpga_dwmac_exit(struct platform_device
*pdev
, void *priv
)
199 struct socfpga_dwmac
*dwmac
= priv
;
201 /* On socfpga platform exit, assert and hold reset to the
202 * enet controller - the default state after a hard reset.
204 if (dwmac
->stmmac_rst
)
205 reset_control_assert(dwmac
->stmmac_rst
);
208 static int socfpga_dwmac_init(struct platform_device
*pdev
, void *priv
)
210 struct socfpga_dwmac
*dwmac
= priv
;
211 struct net_device
*ndev
= platform_get_drvdata(pdev
);
212 struct stmmac_priv
*stpriv
= NULL
;
216 stpriv
= netdev_priv(ndev
);
218 /* Assert reset to the enet controller before changing the phy mode */
219 if (dwmac
->stmmac_rst
)
220 reset_control_assert(dwmac
->stmmac_rst
);
222 /* Setup the phy mode in the system manager registers according to
223 * devicetree configuration
225 ret
= socfpga_dwmac_setup(dwmac
);
227 /* Deassert reset for the phy configuration to be sampled by
228 * the enet controller, and operation to start in requested mode
230 if (dwmac
->stmmac_rst
)
231 reset_control_deassert(dwmac
->stmmac_rst
);
233 /* Before the enet controller is suspended, the phy is suspended.
234 * This causes the phy clock to be gated. The enet controller is
235 * resumed before the phy, so the clock is still gated "off" when
236 * the enet controller is resumed. This code makes sure the phy
237 * is "resumed" before reinitializing the enet controller since
238 * the enet controller depends on an active phy clock to complete
239 * a DMA reset. A DMA reset will "time out" if executed
240 * with no phy clock input on the Synopsys enet controller.
241 * Verified through Synopsys Case #8000711656.
243 * Note that the phy clock is also gated when the phy is isolated.
244 * Phy "suspend" and "isolate" controls are located in phy basic
245 * control register 0, and can be modified by the phy driver
248 if (stpriv
&& stpriv
->phydev
)
249 phy_resume(stpriv
->phydev
);
254 static int socfpga_dwmac_probe(struct platform_device
*pdev
)
256 struct plat_stmmacenet_data
*plat_dat
;
257 struct stmmac_resources stmmac_res
;
258 struct device
*dev
= &pdev
->dev
;
260 struct socfpga_dwmac
*dwmac
;
262 ret
= stmmac_get_platform_resources(pdev
, &stmmac_res
);
266 plat_dat
= stmmac_probe_config_dt(pdev
, &stmmac_res
.mac
);
267 if (IS_ERR(plat_dat
))
268 return PTR_ERR(plat_dat
);
270 dwmac
= devm_kzalloc(dev
, sizeof(*dwmac
), GFP_KERNEL
);
274 ret
= socfpga_dwmac_parse_data(dwmac
, dev
);
276 dev_err(dev
, "Unable to parse OF data\n");
280 ret
= socfpga_dwmac_setup(dwmac
);
282 dev_err(dev
, "couldn't setup SoC glue (%d)\n", ret
);
286 plat_dat
->bsp_priv
= dwmac
;
287 plat_dat
->init
= socfpga_dwmac_init
;
288 plat_dat
->exit
= socfpga_dwmac_exit
;
289 plat_dat
->fix_mac_speed
= socfpga_dwmac_fix_mac_speed
;
291 ret
= socfpga_dwmac_init(pdev
, plat_dat
->bsp_priv
);
295 return stmmac_dvr_probe(&pdev
->dev
, plat_dat
, &stmmac_res
);
298 static const struct of_device_id socfpga_dwmac_match
[] = {
299 { .compatible
= "altr,socfpga-stmmac" },
302 MODULE_DEVICE_TABLE(of
, socfpga_dwmac_match
);
304 static struct platform_driver socfpga_dwmac_driver
= {
305 .probe
= socfpga_dwmac_probe
,
306 .remove
= stmmac_pltfr_remove
,
308 .name
= "socfpga-dwmac",
309 .pm
= &stmmac_pltfr_pm_ops
,
310 .of_match_table
= socfpga_dwmac_match
,
313 module_platform_driver(socfpga_dwmac_driver
);
315 MODULE_LICENSE("GPL v2");