drivers/net/ethernet/ti/davinci_cpdma.h

   1 /*
   2  * Texas Instruments CPDMA Driver
   3  *
   4  * Copyright (C) 2010 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #ifndef __DAVINCI_CPDMA_H__
  16 #define __DAVINCI_CPDMA_H__
  17
  18 #define CPDMA_MAX_CHANNELS      BITS_PER_LONG
  19
  20 #define tx_chan_num(chan)       (chan)
  21 #define rx_chan_num(chan)       ((chan) + CPDMA_MAX_CHANNELS)
  22 #define is_rx_chan(chan)        ((chan)->chan_num >= CPDMA_MAX_CHANNELS)
  23 #define is_tx_chan(chan)        (!is_rx_chan(chan))
  24 #define __chan_linear(chan_num) ((chan_num) & (CPDMA_MAX_CHANNELS - 1))
  25 #define chan_linear(chan)       __chan_linear((chan)->chan_num)
  26
  27 #define CPDMA_RX_SOURCE_PORT(__status__)        ((__status__ >> 16) & 0x7)
  28
  29 #define CPDMA_EOI_RX_THRESH     0x0
  30 #define CPDMA_EOI_RX            0x1
  31 #define CPDMA_EOI_TX            0x2
  32 #define CPDMA_EOI_MISC          0x3
  33
  34 struct cpdma_params {
  35         struct device           *dev;
  36         void __iomem            *dmaregs;
  37         void __iomem            *txhdp, *rxhdp, *txcp, *rxcp;
  38         void __iomem            *rxthresh, *rxfree;
  39         int                     num_chan;
  40         bool                    has_soft_reset;
  41         int                     min_packet_size;
  42         u32                     desc_mem_phys;
  43         u32                     desc_hw_addr;
  44         int                     desc_mem_size;
  45         int                     desc_align;
  46
  47         /*
  48          * Some instances of embedded cpdma controllers have extra control and
  49          * status registers.  The following flag enables access to these
  50          * "extended" registers.
  51          */
  52         bool                    has_ext_regs;
  53 };
  54
  55 struct cpdma_chan_stats {
  56         u32                     head_enqueue;
  57         u32                     tail_enqueue;
  58         u32                     pad_enqueue;
  59         u32                     misqueued;
  60         u32                     desc_alloc_fail;
  61         u32                     pad_alloc_fail;
  62         u32                     runt_receive_buff;
  63         u32                     runt_transmit_buff;
  64         u32                     empty_dequeue;
  65         u32                     busy_dequeue;
  66         u32                     good_dequeue;
  67         u32                     requeue;
  68         u32                     teardown_dequeue;
  69 };
  70
  71 struct cpdma_ctlr;
  72 struct cpdma_chan;
  73
  74 typedef void (*cpdma_handler_fn)(void *token, int len, int status);
  75
  76 struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params);
  77 int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr);
  78 int cpdma_ctlr_start(struct cpdma_ctlr *ctlr);
  79 int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr);
  80
  81 struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
  82                                      cpdma_handler_fn handler);
  83 int cpdma_chan_get_rx_buf_num(struct cpdma_ctlr *ctlr);
  84 int cpdma_chan_destroy(struct cpdma_chan *chan);
  85 int cpdma_chan_start(struct cpdma_chan *chan);
  86 int cpdma_chan_stop(struct cpdma_chan *chan);
  87
  88 int cpdma_chan_get_stats(struct cpdma_chan *chan,
  89                          struct cpdma_chan_stats *stats);
  90 int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
  91                       int len, int directed);
  92 int cpdma_chan_process(struct cpdma_chan *chan, int quota);
  93
  94 int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
  95 void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value);
  96 int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable);
  97 bool cpdma_check_free_tx_desc(struct cpdma_chan *chan);
  98
  99 enum cpdma_control {
 100         CPDMA_CMD_IDLE,                 /* write-only */
 101         CPDMA_COPY_ERROR_FRAMES,        /* read-write */
 102         CPDMA_RX_OFF_LEN_UPDATE,        /* read-write */
 103         CPDMA_RX_OWNERSHIP_FLIP,        /* read-write */
 104         CPDMA_TX_PRIO_FIXED,            /* read-write */
 105         CPDMA_STAT_IDLE,                /* read-only */
 106         CPDMA_STAT_TX_ERR_CHAN,         /* read-only */
 107         CPDMA_STAT_TX_ERR_CODE,         /* read-only */
 108         CPDMA_STAT_RX_ERR_CHAN,         /* read-only */
 109         CPDMA_STAT_RX_ERR_CODE,         /* read-only */
 110         CPDMA_RX_BUFFER_OFFSET,         /* read-write */
 111 };
 112
 113 int cpdma_control_get(struct cpdma_ctlr *ctlr, int control);
 114 int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value);
 115
 116 #endif