1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <net/checksum.h>
40 #include <net/ip6_checksum.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <scsi/fc/fc_fcoe.h>
46 #include "ixgbe_common.h"
47 #include "ixgbe_dcb_82599.h"
48 #include "ixgbe_sriov.h"
50 char ixgbe_driver_name
[] = "ixgbe";
51 static const char ixgbe_driver_string
[] =
52 "Intel(R) 10 Gigabit PCI Express Network Driver";
54 #define DRV_VERSION "2.0.62-k2"
55 const char ixgbe_driver_version
[] = DRV_VERSION
;
56 static char ixgbe_copyright
[] = "Copyright (c) 1999-2010 Intel Corporation.";
58 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
59 [board_82598
] = &ixgbe_82598_info
,
60 [board_82599
] = &ixgbe_82599_info
,
63 /* ixgbe_pci_tbl - PCI Device ID Table
65 * Wildcard entries (PCI_ANY_ID) should come last
66 * Last entry must be all 0s
68 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
69 * Class, Class Mask, private data (not used) }
71 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl
) = {
72 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
74 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
76 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
78 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
80 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT2
),
82 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
84 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
86 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
88 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
90 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
92 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
94 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
96 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
98 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
),
100 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KR
),
102 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
104 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_EM
),
106 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4_MEZZ
),
108 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_CX4
),
110 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_COMBO_BACKPLANE
),
113 /* required last entry */
116 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
118 #ifdef CONFIG_IXGBE_DCA
119 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
121 static struct notifier_block dca_notifier
= {
122 .notifier_call
= ixgbe_notify_dca
,
128 #ifdef CONFIG_PCI_IOV
129 static unsigned int max_vfs
;
130 module_param(max_vfs
, uint
, 0);
131 MODULE_PARM_DESC(max_vfs
, "Maximum number of virtual functions to allocate "
132 "per physical function");
133 #endif /* CONFIG_PCI_IOV */
135 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
136 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
137 MODULE_LICENSE("GPL");
138 MODULE_VERSION(DRV_VERSION
);
140 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
142 static inline void ixgbe_disable_sriov(struct ixgbe_adapter
*adapter
)
144 struct ixgbe_hw
*hw
= &adapter
->hw
;
149 #ifdef CONFIG_PCI_IOV
150 /* disable iov and allow time for transactions to clear */
151 pci_disable_sriov(adapter
->pdev
);
154 /* turn off device IOV mode */
155 gcr
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
156 gcr
&= ~(IXGBE_GCR_EXT_SRIOV
);
157 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr
);
158 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
159 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
160 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
162 /* set default pool back to 0 */
163 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
164 vmdctl
&= ~IXGBE_VT_CTL_POOL_MASK
;
165 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
);
167 /* take a breather then clean up driver data */
170 kfree(adapter
->vfinfo
);
171 adapter
->vfinfo
= NULL
;
173 adapter
->num_vfs
= 0;
174 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
177 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
181 /* Let firmware take over control of h/w */
182 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
183 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
184 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
187 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
191 /* Let firmware know the driver has taken over */
192 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
193 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
194 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
198 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
199 * @adapter: pointer to adapter struct
200 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
201 * @queue: queue to map the corresponding interrupt to
202 * @msix_vector: the vector to map to the corresponding queue
205 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
206 u8 queue
, u8 msix_vector
)
209 struct ixgbe_hw
*hw
= &adapter
->hw
;
210 switch (hw
->mac
.type
) {
211 case ixgbe_mac_82598EB
:
212 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
215 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
216 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
217 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
218 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
219 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
221 case ixgbe_mac_82599EB
:
222 if (direction
== -1) {
224 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
225 index
= ((queue
& 1) * 8);
226 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
227 ivar
&= ~(0xFF << index
);
228 ivar
|= (msix_vector
<< index
);
229 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
232 /* tx or rx causes */
233 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
234 index
= ((16 * (queue
& 1)) + (8 * direction
));
235 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
236 ivar
&= ~(0xFF << index
);
237 ivar
|= (msix_vector
<< index
);
238 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
246 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter
*adapter
,
251 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
252 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
253 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
, mask
);
255 mask
= (qmask
& 0xFFFFFFFF);
256 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0), mask
);
257 mask
= (qmask
>> 32);
258 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1), mask
);
262 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter
*adapter
,
263 struct ixgbe_tx_buffer
266 if (tx_buffer_info
->dma
) {
267 if (tx_buffer_info
->mapped_as_page
)
268 pci_unmap_page(adapter
->pdev
,
270 tx_buffer_info
->length
,
273 pci_unmap_single(adapter
->pdev
,
275 tx_buffer_info
->length
,
277 tx_buffer_info
->dma
= 0;
279 if (tx_buffer_info
->skb
) {
280 dev_kfree_skb_any(tx_buffer_info
->skb
);
281 tx_buffer_info
->skb
= NULL
;
283 tx_buffer_info
->time_stamp
= 0;
284 /* tx_buffer_info must be completely set up in the transmit path */
288 * ixgbe_tx_is_paused - check if the tx ring is paused
289 * @adapter: the ixgbe adapter
290 * @tx_ring: the corresponding tx_ring
292 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
293 * corresponding TC of this tx_ring when checking TFCS.
295 * Returns : true if paused
297 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter
*adapter
,
298 struct ixgbe_ring
*tx_ring
)
300 u32 txoff
= IXGBE_TFCS_TXOFF
;
302 #ifdef CONFIG_IXGBE_DCB
303 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
305 int reg_idx
= tx_ring
->reg_idx
;
306 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
308 switch (adapter
->hw
.mac
.type
) {
309 case ixgbe_mac_82598EB
:
311 txoff
= IXGBE_TFCS_TXOFF0
;
313 case ixgbe_mac_82599EB
:
315 txoff
= IXGBE_TFCS_TXOFF
;
319 if (tc
== 2) /* TC2, TC3 */
320 tc
+= (reg_idx
- 64) >> 4;
321 else if (tc
== 3) /* TC4, TC5, TC6, TC7 */
322 tc
+= 1 + ((reg_idx
- 96) >> 3);
323 } else if (dcb_i
== 4) {
327 tc
+= (reg_idx
- 64) >> 5;
328 if (tc
== 2) /* TC2, TC3 */
329 tc
+= (reg_idx
- 96) >> 4;
339 return IXGBE_READ_REG(&adapter
->hw
, IXGBE_TFCS
) & txoff
;
342 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter
*adapter
,
343 struct ixgbe_ring
*tx_ring
,
346 struct ixgbe_hw
*hw
= &adapter
->hw
;
348 /* Detect a transmit hang in hardware, this serializes the
349 * check with the clearing of time_stamp and movement of eop */
350 adapter
->detect_tx_hung
= false;
351 if (tx_ring
->tx_buffer_info
[eop
].time_stamp
&&
352 time_after(jiffies
, tx_ring
->tx_buffer_info
[eop
].time_stamp
+ HZ
) &&
353 !ixgbe_tx_is_paused(adapter
, tx_ring
)) {
354 /* detected Tx unit hang */
355 union ixgbe_adv_tx_desc
*tx_desc
;
356 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
357 DPRINTK(DRV
, ERR
, "Detected Tx Unit Hang\n"
359 " TDH, TDT <%x>, <%x>\n"
360 " next_to_use <%x>\n"
361 " next_to_clean <%x>\n"
362 "tx_buffer_info[next_to_clean]\n"
363 " time_stamp <%lx>\n"
365 tx_ring
->queue_index
,
366 IXGBE_READ_REG(hw
, tx_ring
->head
),
367 IXGBE_READ_REG(hw
, tx_ring
->tail
),
368 tx_ring
->next_to_use
, eop
,
369 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
376 #define IXGBE_MAX_TXD_PWR 14
377 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
379 /* Tx Descriptors needed, worst case */
380 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
381 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
382 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
383 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
385 static void ixgbe_tx_timeout(struct net_device
*netdev
);
388 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
389 * @q_vector: structure containing interrupt and ring information
390 * @tx_ring: tx ring to clean
392 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector
*q_vector
,
393 struct ixgbe_ring
*tx_ring
)
395 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
396 struct net_device
*netdev
= adapter
->netdev
;
397 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
398 struct ixgbe_tx_buffer
*tx_buffer_info
;
399 unsigned int i
, eop
, count
= 0;
400 unsigned int total_bytes
= 0, total_packets
= 0;
402 i
= tx_ring
->next_to_clean
;
403 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
404 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
406 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
407 (count
< tx_ring
->work_limit
)) {
408 bool cleaned
= false;
409 for ( ; !cleaned
; count
++) {
411 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
412 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
413 cleaned
= (i
== eop
);
414 skb
= tx_buffer_info
->skb
;
416 if (cleaned
&& skb
) {
417 unsigned int segs
, bytecount
;
418 unsigned int hlen
= skb_headlen(skb
);
420 /* gso_segs is currently only valid for tcp */
421 segs
= skb_shinfo(skb
)->gso_segs
?: 1;
423 /* adjust for FCoE Sequence Offload */
424 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
425 && (skb
->protocol
== htons(ETH_P_FCOE
)) &&
427 hlen
= skb_transport_offset(skb
) +
428 sizeof(struct fc_frame_header
) +
429 sizeof(struct fcoe_crc_eof
);
430 segs
= DIV_ROUND_UP(skb
->len
- hlen
,
431 skb_shinfo(skb
)->gso_size
);
433 #endif /* IXGBE_FCOE */
434 /* multiply data chunks by size of headers */
435 bytecount
= ((segs
- 1) * hlen
) + skb
->len
;
436 total_packets
+= segs
;
437 total_bytes
+= bytecount
;
440 ixgbe_unmap_and_free_tx_resource(adapter
,
443 tx_desc
->wb
.status
= 0;
446 if (i
== tx_ring
->count
)
450 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
451 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
454 tx_ring
->next_to_clean
= i
;
456 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
457 if (unlikely(count
&& netif_carrier_ok(netdev
) &&
458 (IXGBE_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
459 /* Make sure that anybody stopping the queue after this
460 * sees the new next_to_clean.
463 if (__netif_subqueue_stopped(netdev
, tx_ring
->queue_index
) &&
464 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
465 netif_wake_subqueue(netdev
, tx_ring
->queue_index
);
466 ++tx_ring
->restart_queue
;
470 if (adapter
->detect_tx_hung
) {
471 if (ixgbe_check_tx_hang(adapter
, tx_ring
, i
)) {
472 /* schedule immediate reset if we believe we hung */
474 "tx hang %d detected, resetting adapter\n",
475 adapter
->tx_timeout_count
+ 1);
476 ixgbe_tx_timeout(adapter
->netdev
);
480 /* re-arm the interrupt */
481 if (count
>= tx_ring
->work_limit
)
482 ixgbe_irq_rearm_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
484 tx_ring
->total_bytes
+= total_bytes
;
485 tx_ring
->total_packets
+= total_packets
;
486 tx_ring
->stats
.packets
+= total_packets
;
487 tx_ring
->stats
.bytes
+= total_bytes
;
488 return (count
< tx_ring
->work_limit
);
491 #ifdef CONFIG_IXGBE_DCA
492 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
493 struct ixgbe_ring
*rx_ring
)
497 int q
= rx_ring
->reg_idx
;
499 if (rx_ring
->cpu
!= cpu
) {
500 rxctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
));
501 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
502 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
503 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
504 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
505 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
506 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
507 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
509 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
510 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
511 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
512 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN
|
513 IXGBE_DCA_RXCTRL_DESC_HSRO_EN
);
514 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
), rxctrl
);
520 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
521 struct ixgbe_ring
*tx_ring
)
525 int q
= tx_ring
->reg_idx
;
526 struct ixgbe_hw
*hw
= &adapter
->hw
;
528 if (tx_ring
->cpu
!= cpu
) {
529 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
530 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(q
));
531 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
532 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
533 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
534 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(q
), txctrl
);
535 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
536 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
));
537 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
538 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
539 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
540 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
541 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
), txctrl
);
548 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
552 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
555 /* always use CB2 mode, difference is masked in the CB driver */
556 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
558 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
559 adapter
->tx_ring
[i
]->cpu
= -1;
560 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[i
]);
562 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
563 adapter
->rx_ring
[i
]->cpu
= -1;
564 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[i
]);
568 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
570 struct net_device
*netdev
= dev_get_drvdata(dev
);
571 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
572 unsigned long event
= *(unsigned long *)data
;
575 case DCA_PROVIDER_ADD
:
576 /* if we're already enabled, don't do it again */
577 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
579 if (dca_add_requester(dev
) == 0) {
580 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
581 ixgbe_setup_dca(adapter
);
584 /* Fall Through since DCA is disabled. */
585 case DCA_PROVIDER_REMOVE
:
586 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
587 dca_remove_requester(dev
);
588 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
589 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
597 #endif /* CONFIG_IXGBE_DCA */
599 * ixgbe_receive_skb - Send a completed packet up the stack
600 * @adapter: board private structure
601 * @skb: packet to send up
602 * @status: hardware indication of status of receive
603 * @rx_ring: rx descriptor ring (for a specific queue) to setup
604 * @rx_desc: rx descriptor
606 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
607 struct sk_buff
*skb
, u8 status
,
608 struct ixgbe_ring
*ring
,
609 union ixgbe_adv_rx_desc
*rx_desc
)
611 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
612 struct napi_struct
*napi
= &q_vector
->napi
;
613 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
614 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
616 skb_record_rx_queue(skb
, ring
->queue_index
);
617 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
)) {
618 if (adapter
->vlgrp
&& is_vlan
&& (tag
& VLAN_VID_MASK
))
619 vlan_gro_receive(napi
, adapter
->vlgrp
, tag
, skb
);
621 napi_gro_receive(napi
, skb
);
623 if (adapter
->vlgrp
&& is_vlan
&& (tag
& VLAN_VID_MASK
))
624 vlan_hwaccel_rx(skb
, adapter
->vlgrp
, tag
);
631 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
632 * @adapter: address of board private structure
633 * @status_err: hardware indication of status of receive
634 * @skb: skb currently being received and modified
636 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
637 union ixgbe_adv_rx_desc
*rx_desc
,
640 u32 status_err
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
642 skb
->ip_summed
= CHECKSUM_NONE
;
644 /* Rx csum disabled */
645 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
648 /* if IP and error */
649 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
650 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
651 adapter
->hw_csum_rx_error
++;
655 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
658 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
659 u16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
662 * 82599 errata, UDP frames with a 0 checksum can be marked as
665 if ((pkt_info
& IXGBE_RXDADV_PKTTYPE_UDP
) &&
666 (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
669 adapter
->hw_csum_rx_error
++;
673 /* It must be a TCP or UDP packet with a valid checksum */
674 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
677 static inline void ixgbe_release_rx_desc(struct ixgbe_hw
*hw
,
678 struct ixgbe_ring
*rx_ring
, u32 val
)
681 * Force memory writes to complete before letting h/w
682 * know there are new descriptors to fetch. (Only
683 * applicable for weak-ordered memory model archs,
687 IXGBE_WRITE_REG(hw
, IXGBE_RDT(rx_ring
->reg_idx
), val
);
691 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
692 * @adapter: address of board private structure
694 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter
*adapter
,
695 struct ixgbe_ring
*rx_ring
,
698 struct pci_dev
*pdev
= adapter
->pdev
;
699 union ixgbe_adv_rx_desc
*rx_desc
;
700 struct ixgbe_rx_buffer
*bi
;
703 i
= rx_ring
->next_to_use
;
704 bi
= &rx_ring
->rx_buffer_info
[i
];
706 while (cleaned_count
--) {
707 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
710 (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)) {
712 bi
->page
= alloc_page(GFP_ATOMIC
);
714 adapter
->alloc_rx_page_failed
++;
719 /* use a half page if we're re-using */
720 bi
->page_offset
^= (PAGE_SIZE
/ 2);
723 bi
->page_dma
= pci_map_page(pdev
, bi
->page
,
731 /* netdev_alloc_skb reserves 32 bytes up front!! */
732 uint bufsz
= rx_ring
->rx_buf_len
+ SMP_CACHE_BYTES
;
733 skb
= netdev_alloc_skb(adapter
->netdev
, bufsz
);
736 adapter
->alloc_rx_buff_failed
++;
740 /* advance the data pointer to the next cache line */
741 skb_reserve(skb
, (PTR_ALIGN(skb
->data
, SMP_CACHE_BYTES
)
745 bi
->dma
= pci_map_single(pdev
, skb
->data
,
749 /* Refresh the desc even if buffer_addrs didn't change because
750 * each write-back erases this info. */
751 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
752 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
753 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
755 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
759 if (i
== rx_ring
->count
)
761 bi
= &rx_ring
->rx_buffer_info
[i
];
765 if (rx_ring
->next_to_use
!= i
) {
766 rx_ring
->next_to_use
= i
;
768 i
= (rx_ring
->count
- 1);
770 ixgbe_release_rx_desc(&adapter
->hw
, rx_ring
, i
);
774 static inline u16
ixgbe_get_hdr_info(union ixgbe_adv_rx_desc
*rx_desc
)
776 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
;
779 static inline u16
ixgbe_get_pkt_info(union ixgbe_adv_rx_desc
*rx_desc
)
781 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
784 static inline u32
ixgbe_get_rsc_count(union ixgbe_adv_rx_desc
*rx_desc
)
786 return (le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
787 IXGBE_RXDADV_RSCCNT_MASK
) >>
788 IXGBE_RXDADV_RSCCNT_SHIFT
;
792 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
793 * @skb: pointer to the last skb in the rsc queue
794 * @count: pointer to number of packets coalesced in this context
796 * This function changes a queue full of hw rsc buffers into a completed
797 * packet. It uses the ->prev pointers to find the first packet and then
798 * turns it into the frag list owner.
800 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
,
803 unsigned int frag_list_size
= 0;
806 struct sk_buff
*prev
= skb
->prev
;
807 frag_list_size
+= skb
->len
;
813 skb_shinfo(skb
)->frag_list
= skb
->next
;
815 skb
->len
+= frag_list_size
;
816 skb
->data_len
+= frag_list_size
;
817 skb
->truesize
+= frag_list_size
;
821 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
822 struct ixgbe_ring
*rx_ring
,
823 int *work_done
, int work_to_do
)
825 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
826 struct net_device
*netdev
= adapter
->netdev
;
827 struct pci_dev
*pdev
= adapter
->pdev
;
828 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
829 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
831 unsigned int i
, rsc_count
= 0;
834 bool cleaned
= false;
835 int cleaned_count
= 0;
836 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
839 #endif /* IXGBE_FCOE */
841 i
= rx_ring
->next_to_clean
;
842 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
843 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
844 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
846 while (staterr
& IXGBE_RXD_STAT_DD
) {
848 if (*work_done
>= work_to_do
)
852 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
853 hdr_info
= le16_to_cpu(ixgbe_get_hdr_info(rx_desc
));
854 len
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
855 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
856 if (len
> IXGBE_RX_HDR_SIZE
)
857 len
= IXGBE_RX_HDR_SIZE
;
858 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
860 len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
864 skb
= rx_buffer_info
->skb
;
866 rx_buffer_info
->skb
= NULL
;
868 if (rx_buffer_info
->dma
) {
869 pci_unmap_single(pdev
, rx_buffer_info
->dma
,
872 rx_buffer_info
->dma
= 0;
877 pci_unmap_page(pdev
, rx_buffer_info
->page_dma
,
878 PAGE_SIZE
/ 2, PCI_DMA_FROMDEVICE
);
879 rx_buffer_info
->page_dma
= 0;
880 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
881 rx_buffer_info
->page
,
882 rx_buffer_info
->page_offset
,
885 if ((rx_ring
->rx_buf_len
> (PAGE_SIZE
/ 2)) ||
886 (page_count(rx_buffer_info
->page
) != 1))
887 rx_buffer_info
->page
= NULL
;
889 get_page(rx_buffer_info
->page
);
891 skb
->len
+= upper_len
;
892 skb
->data_len
+= upper_len
;
893 skb
->truesize
+= upper_len
;
897 if (i
== rx_ring
->count
)
900 next_rxd
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
904 if (adapter
->flags2
& IXGBE_FLAG2_RSC_CAPABLE
)
905 rsc_count
= ixgbe_get_rsc_count(rx_desc
);
908 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
909 IXGBE_RXDADV_NEXTP_SHIFT
;
910 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
912 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
915 if (staterr
& IXGBE_RXD_STAT_EOP
) {
917 skb
= ixgbe_transform_rsc_queue(skb
, &(rx_ring
->rsc_count
));
918 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
919 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)
920 rx_ring
->rsc_count
+= skb_shinfo(skb
)->nr_frags
;
922 rx_ring
->rsc_count
++;
923 rx_ring
->rsc_flush
++;
925 rx_ring
->stats
.packets
++;
926 rx_ring
->stats
.bytes
+= skb
->len
;
928 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
929 rx_buffer_info
->skb
= next_buffer
->skb
;
930 rx_buffer_info
->dma
= next_buffer
->dma
;
931 next_buffer
->skb
= skb
;
932 next_buffer
->dma
= 0;
934 skb
->next
= next_buffer
->skb
;
935 skb
->next
->prev
= skb
;
937 rx_ring
->non_eop_descs
++;
941 if (staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
) {
942 dev_kfree_skb_irq(skb
);
946 ixgbe_rx_checksum(adapter
, rx_desc
, skb
);
948 /* probably a little skewed due to removing CRC */
949 total_rx_bytes
+= skb
->len
;
952 skb
->protocol
= eth_type_trans(skb
, adapter
->netdev
);
954 /* if ddp, not passing to ULD unless for FCP_RSP or error */
955 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
956 ddp_bytes
= ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
);
960 #endif /* IXGBE_FCOE */
961 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
964 rx_desc
->wb
.upper
.status_error
= 0;
966 /* return some buffers to hardware, one at a time is too slow */
967 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
968 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
972 /* use prefetched values */
974 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
976 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
979 rx_ring
->next_to_clean
= i
;
980 cleaned_count
= IXGBE_DESC_UNUSED(rx_ring
);
983 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
986 /* include DDPed FCoE data */
990 mss
= adapter
->netdev
->mtu
- sizeof(struct fcoe_hdr
) -
991 sizeof(struct fc_frame_header
) -
992 sizeof(struct fcoe_crc_eof
);
995 total_rx_bytes
+= ddp_bytes
;
996 total_rx_packets
+= DIV_ROUND_UP(ddp_bytes
, mss
);
998 #endif /* IXGBE_FCOE */
1000 rx_ring
->total_packets
+= total_rx_packets
;
1001 rx_ring
->total_bytes
+= total_rx_bytes
;
1002 netdev
->stats
.rx_bytes
+= total_rx_bytes
;
1003 netdev
->stats
.rx_packets
+= total_rx_packets
;
1008 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
1010 * ixgbe_configure_msix - Configure MSI-X hardware
1011 * @adapter: board private structure
1013 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1016 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
1018 struct ixgbe_q_vector
*q_vector
;
1019 int i
, j
, q_vectors
, v_idx
, r_idx
;
1022 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1025 * Populate the IVAR table and set the ITR values to the
1026 * corresponding register.
1028 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
1029 q_vector
= adapter
->q_vector
[v_idx
];
1030 /* XXX for_each_bit(...) */
1031 r_idx
= find_first_bit(q_vector
->rxr_idx
,
1032 adapter
->num_rx_queues
);
1034 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1035 j
= adapter
->rx_ring
[r_idx
]->reg_idx
;
1036 ixgbe_set_ivar(adapter
, 0, j
, v_idx
);
1037 r_idx
= find_next_bit(q_vector
->rxr_idx
,
1038 adapter
->num_rx_queues
,
1041 r_idx
= find_first_bit(q_vector
->txr_idx
,
1042 adapter
->num_tx_queues
);
1044 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1045 j
= adapter
->tx_ring
[r_idx
]->reg_idx
;
1046 ixgbe_set_ivar(adapter
, 1, j
, v_idx
);
1047 r_idx
= find_next_bit(q_vector
->txr_idx
,
1048 adapter
->num_tx_queues
,
1052 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
1054 q_vector
->eitr
= adapter
->tx_eitr_param
;
1055 else if (q_vector
->rxr_count
)
1057 q_vector
->eitr
= adapter
->rx_eitr_param
;
1059 ixgbe_write_eitr(q_vector
);
1062 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
1063 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
1065 else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
1066 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
1067 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
1069 /* set up to autoclear timer, and the vectors */
1070 mask
= IXGBE_EIMS_ENABLE_MASK
;
1071 if (adapter
->num_vfs
)
1072 mask
&= ~(IXGBE_EIMS_OTHER
|
1073 IXGBE_EIMS_MAILBOX
|
1076 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
1077 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
1080 enum latency_range
{
1084 latency_invalid
= 255
1088 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1089 * @adapter: pointer to adapter
1090 * @eitr: eitr setting (ints per sec) to give last timeslice
1091 * @itr_setting: current throttle rate in ints/second
1092 * @packets: the number of packets during this measurement interval
1093 * @bytes: the number of bytes during this measurement interval
1095 * Stores a new ITR value based on packets and byte
1096 * counts during the last interrupt. The advantage of per interrupt
1097 * computation is faster updates and more accurate ITR for the current
1098 * traffic pattern. Constants in this function were computed
1099 * based on theoretical maximum wire speed and thresholds were set based
1100 * on testing data as well as attempting to minimize response time
1101 * while increasing bulk throughput.
1102 * this functionality is controlled by the InterruptThrottleRate module
1103 * parameter (see ixgbe_param.c)
1105 static u8
ixgbe_update_itr(struct ixgbe_adapter
*adapter
,
1106 u32 eitr
, u8 itr_setting
,
1107 int packets
, int bytes
)
1109 unsigned int retval
= itr_setting
;
1114 goto update_itr_done
;
1117 /* simple throttlerate management
1118 * 0-20MB/s lowest (100000 ints/s)
1119 * 20-100MB/s low (20000 ints/s)
1120 * 100-1249MB/s bulk (8000 ints/s)
1122 /* what was last interrupt timeslice? */
1123 timepassed_us
= 1000000/eitr
;
1124 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
1126 switch (itr_setting
) {
1127 case lowest_latency
:
1128 if (bytes_perint
> adapter
->eitr_low
)
1129 retval
= low_latency
;
1132 if (bytes_perint
> adapter
->eitr_high
)
1133 retval
= bulk_latency
;
1134 else if (bytes_perint
<= adapter
->eitr_low
)
1135 retval
= lowest_latency
;
1138 if (bytes_perint
<= adapter
->eitr_high
)
1139 retval
= low_latency
;
1148 * ixgbe_write_eitr - write EITR register in hardware specific way
1149 * @q_vector: structure containing interrupt and ring information
1151 * This function is made to be called by ethtool and by the driver
1152 * when it needs to update EITR registers at runtime. Hardware
1153 * specific quirks/differences are taken care of here.
1155 void ixgbe_write_eitr(struct ixgbe_q_vector
*q_vector
)
1157 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1158 struct ixgbe_hw
*hw
= &adapter
->hw
;
1159 int v_idx
= q_vector
->v_idx
;
1160 u32 itr_reg
= EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
);
1162 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1163 /* must write high and low 16 bits to reset counter */
1164 itr_reg
|= (itr_reg
<< 16);
1165 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1167 * set the WDIS bit to not clear the timer bits and cause an
1168 * immediate assertion of the interrupt
1170 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
1172 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
1175 static void ixgbe_set_itr_msix(struct ixgbe_q_vector
*q_vector
)
1177 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1179 u8 current_itr
, ret_itr
;
1181 struct ixgbe_ring
*rx_ring
, *tx_ring
;
1183 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1184 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1185 tx_ring
= adapter
->tx_ring
[r_idx
];
1186 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1188 tx_ring
->total_packets
,
1189 tx_ring
->total_bytes
);
1190 /* if the result for this queue would decrease interrupt
1191 * rate for this vector then use that result */
1192 q_vector
->tx_itr
= ((q_vector
->tx_itr
> ret_itr
) ?
1193 q_vector
->tx_itr
- 1 : ret_itr
);
1194 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1198 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1199 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1200 rx_ring
= adapter
->rx_ring
[r_idx
];
1201 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1203 rx_ring
->total_packets
,
1204 rx_ring
->total_bytes
);
1205 /* if the result for this queue would decrease interrupt
1206 * rate for this vector then use that result */
1207 q_vector
->rx_itr
= ((q_vector
->rx_itr
> ret_itr
) ?
1208 q_vector
->rx_itr
- 1 : ret_itr
);
1209 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1213 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1215 switch (current_itr
) {
1216 /* counts and packets in update_itr are dependent on these numbers */
1217 case lowest_latency
:
1221 new_itr
= 20000; /* aka hwitr = ~200 */
1229 if (new_itr
!= q_vector
->eitr
) {
1230 /* do an exponential smoothing */
1231 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1233 /* save the algorithm value here, not the smoothed one */
1234 q_vector
->eitr
= new_itr
;
1236 ixgbe_write_eitr(q_vector
);
1242 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1244 struct ixgbe_hw
*hw
= &adapter
->hw
;
1246 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1247 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1248 DPRINTK(PROBE
, CRIT
, "Fan has stopped, replace the adapter\n");
1249 /* write to clear the interrupt */
1250 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1254 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1256 struct ixgbe_hw
*hw
= &adapter
->hw
;
1258 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1259 /* Clear the interrupt */
1260 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1261 schedule_work(&adapter
->multispeed_fiber_task
);
1262 } else if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1263 /* Clear the interrupt */
1264 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1265 schedule_work(&adapter
->sfp_config_module_task
);
1267 /* Interrupt isn't for us... */
1272 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1274 struct ixgbe_hw
*hw
= &adapter
->hw
;
1277 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1278 adapter
->link_check_timeout
= jiffies
;
1279 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1280 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1281 IXGBE_WRITE_FLUSH(hw
);
1282 schedule_work(&adapter
->watchdog_task
);
1286 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1288 struct net_device
*netdev
= data
;
1289 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1290 struct ixgbe_hw
*hw
= &adapter
->hw
;
1294 * Workaround for Silicon errata. Use clear-by-write instead
1295 * of clear-by-read. Reading with EICS will return the
1296 * interrupt causes without clearing, which later be done
1297 * with the write to EICR.
1299 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1300 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1302 if (eicr
& IXGBE_EICR_LSC
)
1303 ixgbe_check_lsc(adapter
);
1305 if (eicr
& IXGBE_EICR_MAILBOX
)
1306 ixgbe_msg_task(adapter
);
1308 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
1309 ixgbe_check_fan_failure(adapter
, eicr
);
1311 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1312 ixgbe_check_sfp_event(adapter
, eicr
);
1314 /* Handle Flow Director Full threshold interrupt */
1315 if (eicr
& IXGBE_EICR_FLOW_DIR
) {
1317 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_FLOW_DIR
);
1318 /* Disable transmits before FDIR Re-initialization */
1319 netif_tx_stop_all_queues(netdev
);
1320 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1321 struct ixgbe_ring
*tx_ring
=
1322 adapter
->tx_ring
[i
];
1323 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE
,
1324 &tx_ring
->reinit_state
))
1325 schedule_work(&adapter
->fdir_reinit_task
);
1329 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1330 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_OTHER
);
1335 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1340 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1341 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1342 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1344 mask
= (qmask
& 0xFFFFFFFF);
1345 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(0), mask
);
1346 mask
= (qmask
>> 32);
1347 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(1), mask
);
1349 /* skip the flush */
1352 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter
*adapter
,
1357 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1358 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1359 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, mask
);
1361 mask
= (qmask
& 0xFFFFFFFF);
1362 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), mask
);
1363 mask
= (qmask
>> 32);
1364 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), mask
);
1366 /* skip the flush */
1369 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
1371 struct ixgbe_q_vector
*q_vector
= data
;
1372 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1373 struct ixgbe_ring
*tx_ring
;
1376 if (!q_vector
->txr_count
)
1379 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1380 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1381 tx_ring
= adapter
->tx_ring
[r_idx
];
1382 tx_ring
->total_bytes
= 0;
1383 tx_ring
->total_packets
= 0;
1384 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1388 /* EIAM disabled interrupts (on this vector) for us */
1389 napi_schedule(&q_vector
->napi
);
1395 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1397 * @data: pointer to our q_vector struct for this interrupt vector
1399 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
1401 struct ixgbe_q_vector
*q_vector
= data
;
1402 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1403 struct ixgbe_ring
*rx_ring
;
1407 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1408 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1409 rx_ring
= adapter
->rx_ring
[r_idx
];
1410 rx_ring
->total_bytes
= 0;
1411 rx_ring
->total_packets
= 0;
1412 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1416 if (!q_vector
->rxr_count
)
1419 /* disable interrupts on this vector only */
1420 /* EIAM disabled interrupts (on this vector) for us */
1421 napi_schedule(&q_vector
->napi
);
1426 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
1428 struct ixgbe_q_vector
*q_vector
= data
;
1429 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1430 struct ixgbe_ring
*ring
;
1434 if (!q_vector
->txr_count
&& !q_vector
->rxr_count
)
1437 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1438 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1439 ring
= adapter
->tx_ring
[r_idx
];
1440 ring
->total_bytes
= 0;
1441 ring
->total_packets
= 0;
1442 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1446 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1447 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1448 ring
= adapter
->rx_ring
[r_idx
];
1449 ring
->total_bytes
= 0;
1450 ring
->total_packets
= 0;
1451 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1455 /* EIAM disabled interrupts (on this vector) for us */
1456 napi_schedule(&q_vector
->napi
);
1462 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1463 * @napi: napi struct with our devices info in it
1464 * @budget: amount of work driver is allowed to do this pass, in packets
1466 * This function is optimized for cleaning one queue only on a single
1469 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
1471 struct ixgbe_q_vector
*q_vector
=
1472 container_of(napi
, struct ixgbe_q_vector
, napi
);
1473 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1474 struct ixgbe_ring
*rx_ring
= NULL
;
1478 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1479 rx_ring
= adapter
->rx_ring
[r_idx
];
1480 #ifdef CONFIG_IXGBE_DCA
1481 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1482 ixgbe_update_rx_dca(adapter
, rx_ring
);
1485 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
1487 /* If all Rx work done, exit the polling mode */
1488 if (work_done
< budget
) {
1489 napi_complete(napi
);
1490 if (adapter
->rx_itr_setting
& 1)
1491 ixgbe_set_itr_msix(q_vector
);
1492 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1493 ixgbe_irq_enable_queues(adapter
,
1494 ((u64
)1 << q_vector
->v_idx
));
1501 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1502 * @napi: napi struct with our devices info in it
1503 * @budget: amount of work driver is allowed to do this pass, in packets
1505 * This function will clean more than one rx queue associated with a
1508 static int ixgbe_clean_rxtx_many(struct napi_struct
*napi
, int budget
)
1510 struct ixgbe_q_vector
*q_vector
=
1511 container_of(napi
, struct ixgbe_q_vector
, napi
);
1512 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1513 struct ixgbe_ring
*ring
= NULL
;
1514 int work_done
= 0, i
;
1516 bool tx_clean_complete
= true;
1518 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1519 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1520 ring
= adapter
->tx_ring
[r_idx
];
1521 #ifdef CONFIG_IXGBE_DCA
1522 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1523 ixgbe_update_tx_dca(adapter
, ring
);
1525 tx_clean_complete
&= ixgbe_clean_tx_irq(q_vector
, ring
);
1526 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1530 /* attempt to distribute budget to each queue fairly, but don't allow
1531 * the budget to go below 1 because we'll exit polling */
1532 budget
/= (q_vector
->rxr_count
?: 1);
1533 budget
= max(budget
, 1);
1534 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1535 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1536 ring
= adapter
->rx_ring
[r_idx
];
1537 #ifdef CONFIG_IXGBE_DCA
1538 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1539 ixgbe_update_rx_dca(adapter
, ring
);
1541 ixgbe_clean_rx_irq(q_vector
, ring
, &work_done
, budget
);
1542 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1546 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1547 ring
= adapter
->rx_ring
[r_idx
];
1548 /* If all Rx work done, exit the polling mode */
1549 if (work_done
< budget
) {
1550 napi_complete(napi
);
1551 if (adapter
->rx_itr_setting
& 1)
1552 ixgbe_set_itr_msix(q_vector
);
1553 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1554 ixgbe_irq_enable_queues(adapter
,
1555 ((u64
)1 << q_vector
->v_idx
));
1563 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1564 * @napi: napi struct with our devices info in it
1565 * @budget: amount of work driver is allowed to do this pass, in packets
1567 * This function is optimized for cleaning one queue only on a single
1570 static int ixgbe_clean_txonly(struct napi_struct
*napi
, int budget
)
1572 struct ixgbe_q_vector
*q_vector
=
1573 container_of(napi
, struct ixgbe_q_vector
, napi
);
1574 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1575 struct ixgbe_ring
*tx_ring
= NULL
;
1579 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1580 tx_ring
= adapter
->tx_ring
[r_idx
];
1581 #ifdef CONFIG_IXGBE_DCA
1582 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1583 ixgbe_update_tx_dca(adapter
, tx_ring
);
1586 if (!ixgbe_clean_tx_irq(q_vector
, tx_ring
))
1589 /* If all Tx work done, exit the polling mode */
1590 if (work_done
< budget
) {
1591 napi_complete(napi
);
1592 if (adapter
->tx_itr_setting
& 1)
1593 ixgbe_set_itr_msix(q_vector
);
1594 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1595 ixgbe_irq_enable_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
1601 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
1604 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
1606 set_bit(r_idx
, q_vector
->rxr_idx
);
1607 q_vector
->rxr_count
++;
1610 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
1613 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
1615 set_bit(t_idx
, q_vector
->txr_idx
);
1616 q_vector
->txr_count
++;
1620 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1621 * @adapter: board private structure to initialize
1622 * @vectors: allotted vector count for descriptor rings
1624 * This function maps descriptor rings to the queue-specific vectors
1625 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1626 * one vector per ring/queue, but on a constrained vector budget, we
1627 * group the rings as "efficiently" as possible. You would add new
1628 * mapping configurations in here.
1630 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
,
1634 int rxr_idx
= 0, txr_idx
= 0;
1635 int rxr_remaining
= adapter
->num_rx_queues
;
1636 int txr_remaining
= adapter
->num_tx_queues
;
1641 /* No mapping required if MSI-X is disabled. */
1642 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
1646 * The ideal configuration...
1647 * We have enough vectors to map one per queue.
1649 if (vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
1650 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
1651 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
1653 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
1654 map_vector_to_txq(adapter
, v_start
, txr_idx
);
1660 * If we don't have enough vectors for a 1-to-1
1661 * mapping, we'll have to group them so there are
1662 * multiple queues per vector.
1664 /* Re-adjusting *qpv takes care of the remainder. */
1665 for (i
= v_start
; i
< vectors
; i
++) {
1666 rqpv
= DIV_ROUND_UP(rxr_remaining
, vectors
- i
);
1667 for (j
= 0; j
< rqpv
; j
++) {
1668 map_vector_to_rxq(adapter
, i
, rxr_idx
);
1673 for (i
= v_start
; i
< vectors
; i
++) {
1674 tqpv
= DIV_ROUND_UP(txr_remaining
, vectors
- i
);
1675 for (j
= 0; j
< tqpv
; j
++) {
1676 map_vector_to_txq(adapter
, i
, txr_idx
);
1687 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1688 * @adapter: board private structure
1690 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1691 * interrupts from the kernel.
1693 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
1695 struct net_device
*netdev
= adapter
->netdev
;
1696 irqreturn_t (*handler
)(int, void *);
1697 int i
, vector
, q_vectors
, err
;
1700 /* Decrement for Other and TCP Timer vectors */
1701 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1703 /* Map the Tx/Rx rings to the vectors we were allotted. */
1704 err
= ixgbe_map_rings_to_vectors(adapter
, q_vectors
);
1708 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1709 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1710 &ixgbe_msix_clean_many)
1711 for (vector
= 0; vector
< q_vectors
; vector
++) {
1712 handler
= SET_HANDLER(adapter
->q_vector
[vector
]);
1714 if(handler
== &ixgbe_msix_clean_rx
) {
1715 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1716 netdev
->name
, "rx", ri
++);
1718 else if(handler
== &ixgbe_msix_clean_tx
) {
1719 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1720 netdev
->name
, "tx", ti
++);
1723 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1724 netdev
->name
, "TxRx", vector
);
1726 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
1727 handler
, 0, adapter
->name
[vector
],
1728 adapter
->q_vector
[vector
]);
1731 "request_irq failed for MSIX interrupt "
1732 "Error: %d\n", err
);
1733 goto free_queue_irqs
;
1737 sprintf(adapter
->name
[vector
], "%s:lsc", netdev
->name
);
1738 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
1739 ixgbe_msix_lsc
, 0, adapter
->name
[vector
], netdev
);
1742 "request_irq for msix_lsc failed: %d\n", err
);
1743 goto free_queue_irqs
;
1749 for (i
= vector
- 1; i
>= 0; i
--)
1750 free_irq(adapter
->msix_entries
[--vector
].vector
,
1751 adapter
->q_vector
[i
]);
1752 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
1753 pci_disable_msix(adapter
->pdev
);
1754 kfree(adapter
->msix_entries
);
1755 adapter
->msix_entries
= NULL
;
1760 static void ixgbe_set_itr(struct ixgbe_adapter
*adapter
)
1762 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
1764 u32 new_itr
= q_vector
->eitr
;
1765 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[0];
1766 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[0];
1768 q_vector
->tx_itr
= ixgbe_update_itr(adapter
, new_itr
,
1770 tx_ring
->total_packets
,
1771 tx_ring
->total_bytes
);
1772 q_vector
->rx_itr
= ixgbe_update_itr(adapter
, new_itr
,
1774 rx_ring
->total_packets
,
1775 rx_ring
->total_bytes
);
1777 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1779 switch (current_itr
) {
1780 /* counts and packets in update_itr are dependent on these numbers */
1781 case lowest_latency
:
1785 new_itr
= 20000; /* aka hwitr = ~200 */
1794 if (new_itr
!= q_vector
->eitr
) {
1795 /* do an exponential smoothing */
1796 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1798 /* save the algorithm value here, not the smoothed one */
1799 q_vector
->eitr
= new_itr
;
1801 ixgbe_write_eitr(q_vector
);
1808 * ixgbe_irq_enable - Enable default interrupt generation settings
1809 * @adapter: board private structure
1811 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
)
1815 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
1816 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
1817 mask
|= IXGBE_EIMS_GPI_SDP1
;
1818 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1819 mask
|= IXGBE_EIMS_ECC
;
1820 mask
|= IXGBE_EIMS_GPI_SDP1
;
1821 mask
|= IXGBE_EIMS_GPI_SDP2
;
1822 if (adapter
->num_vfs
)
1823 mask
|= IXGBE_EIMS_MAILBOX
;
1825 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
1826 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
1827 mask
|= IXGBE_EIMS_FLOW_DIR
;
1829 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1830 ixgbe_irq_enable_queues(adapter
, ~0);
1831 IXGBE_WRITE_FLUSH(&adapter
->hw
);
1833 if (adapter
->num_vfs
> 32) {
1834 u32 eitrsel
= (1 << (adapter
->num_vfs
- 32)) - 1;
1835 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, eitrsel
);
1840 * ixgbe_intr - legacy mode Interrupt Handler
1841 * @irq: interrupt number
1842 * @data: pointer to a network interface device structure
1844 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
1846 struct net_device
*netdev
= data
;
1847 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1848 struct ixgbe_hw
*hw
= &adapter
->hw
;
1849 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
1853 * Workaround for silicon errata. Mask the interrupts
1854 * before the read of EICR.
1856 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
1858 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1859 * therefore no explict interrupt disable is necessary */
1860 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
1862 /* shared interrupt alert!
1863 * make sure interrupts are enabled because the read will
1864 * have disabled interrupts due to EIAM */
1865 ixgbe_irq_enable(adapter
);
1866 return IRQ_NONE
; /* Not our interrupt */
1869 if (eicr
& IXGBE_EICR_LSC
)
1870 ixgbe_check_lsc(adapter
);
1872 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
1873 ixgbe_check_sfp_event(adapter
, eicr
);
1875 ixgbe_check_fan_failure(adapter
, eicr
);
1877 if (napi_schedule_prep(&(q_vector
->napi
))) {
1878 adapter
->tx_ring
[0]->total_packets
= 0;
1879 adapter
->tx_ring
[0]->total_bytes
= 0;
1880 adapter
->rx_ring
[0]->total_packets
= 0;
1881 adapter
->rx_ring
[0]->total_bytes
= 0;
1882 /* would disable interrupts here but EIAM disabled it */
1883 __napi_schedule(&(q_vector
->napi
));
1889 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
1891 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1893 for (i
= 0; i
< q_vectors
; i
++) {
1894 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
1895 bitmap_zero(q_vector
->rxr_idx
, MAX_RX_QUEUES
);
1896 bitmap_zero(q_vector
->txr_idx
, MAX_TX_QUEUES
);
1897 q_vector
->rxr_count
= 0;
1898 q_vector
->txr_count
= 0;
1903 * ixgbe_request_irq - initialize interrupts
1904 * @adapter: board private structure
1906 * Attempts to configure interrupts using the best available
1907 * capabilities of the hardware and kernel.
1909 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
1911 struct net_device
*netdev
= adapter
->netdev
;
1914 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1915 err
= ixgbe_request_msix_irqs(adapter
);
1916 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
1917 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, 0,
1918 netdev
->name
, netdev
);
1920 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, IRQF_SHARED
,
1921 netdev
->name
, netdev
);
1925 DPRINTK(PROBE
, ERR
, "request_irq failed, Error %d\n", err
);
1930 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
1932 struct net_device
*netdev
= adapter
->netdev
;
1934 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1937 q_vectors
= adapter
->num_msix_vectors
;
1940 free_irq(adapter
->msix_entries
[i
].vector
, netdev
);
1943 for (; i
>= 0; i
--) {
1944 free_irq(adapter
->msix_entries
[i
].vector
,
1945 adapter
->q_vector
[i
]);
1948 ixgbe_reset_q_vectors(adapter
);
1950 free_irq(adapter
->pdev
->irq
, netdev
);
1955 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1956 * @adapter: board private structure
1958 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
1960 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1961 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
1963 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
1964 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
1965 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
1966 if (adapter
->num_vfs
> 32)
1967 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, 0);
1969 IXGBE_WRITE_FLUSH(&adapter
->hw
);
1970 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1972 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
1973 synchronize_irq(adapter
->msix_entries
[i
].vector
);
1975 synchronize_irq(adapter
->pdev
->irq
);
1980 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1983 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
1985 struct ixgbe_hw
*hw
= &adapter
->hw
;
1987 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
1988 EITR_INTS_PER_SEC_TO_REG(adapter
->rx_eitr_param
));
1990 ixgbe_set_ivar(adapter
, 0, 0, 0);
1991 ixgbe_set_ivar(adapter
, 1, 0, 0);
1993 map_vector_to_rxq(adapter
, 0, 0);
1994 map_vector_to_txq(adapter
, 0, 0);
1996 DPRINTK(HW
, INFO
, "Legacy interrupt IVAR setup done\n");
2000 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2001 * @adapter: board private structure
2003 * Configure the Tx unit of the MAC after a reset.
2005 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
2008 struct ixgbe_hw
*hw
= &adapter
->hw
;
2009 u32 i
, j
, tdlen
, txctrl
;
2011 /* Setup the HW Tx Head and Tail descriptor pointers */
2012 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2013 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
2016 tdlen
= ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
2017 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(j
),
2018 (tdba
& DMA_BIT_MASK(32)));
2019 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(j
), (tdba
>> 32));
2020 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(j
), tdlen
);
2021 IXGBE_WRITE_REG(hw
, IXGBE_TDH(j
), 0);
2022 IXGBE_WRITE_REG(hw
, IXGBE_TDT(j
), 0);
2023 adapter
->tx_ring
[i
]->head
= IXGBE_TDH(j
);
2024 adapter
->tx_ring
[i
]->tail
= IXGBE_TDT(j
);
2026 * Disable Tx Head Writeback RO bit, since this hoses
2027 * bookkeeping if things aren't delivered in order.
2029 switch (hw
->mac
.type
) {
2030 case ixgbe_mac_82598EB
:
2031 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(j
));
2033 case ixgbe_mac_82599EB
:
2035 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(j
));
2038 txctrl
&= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN
;
2039 switch (hw
->mac
.type
) {
2040 case ixgbe_mac_82598EB
:
2041 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(j
), txctrl
);
2043 case ixgbe_mac_82599EB
:
2045 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(j
), txctrl
);
2050 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2054 /* disable the arbiter while setting MTQC */
2055 rttdcs
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
2056 rttdcs
|= IXGBE_RTTDCS_ARBDIS
;
2057 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2059 /* set transmit pool layout */
2060 mask
= (IXGBE_FLAG_SRIOV_ENABLED
| IXGBE_FLAG_DCB_ENABLED
);
2061 switch (adapter
->flags
& mask
) {
2063 case (IXGBE_FLAG_SRIOV_ENABLED
):
2064 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2065 (IXGBE_MTQC_VT_ENA
| IXGBE_MTQC_64VF
));
2068 case (IXGBE_FLAG_DCB_ENABLED
):
2069 /* We enable 8 traffic classes, DCB only */
2070 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2071 (IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_8TC_8TQ
));
2075 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, IXGBE_MTQC_64Q_1PB
);
2079 /* re-eable the arbiter */
2080 rttdcs
&= ~IXGBE_RTTDCS_ARBDIS
;
2081 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2085 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2087 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
,
2088 struct ixgbe_ring
*rx_ring
)
2092 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
2094 index
= rx_ring
->reg_idx
;
2095 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2097 mask
= (unsigned long) feature
[RING_F_RSS
].mask
;
2098 index
= index
& mask
;
2100 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(index
));
2102 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
2103 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
2105 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
2106 IXGBE_SRRCTL_BSIZEHDR_MASK
;
2108 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2109 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2110 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2112 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2114 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2116 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
2117 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2118 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2121 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(index
), srrctl
);
2124 static u32
ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
2129 if (!(adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
2132 mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
2133 #ifdef CONFIG_IXGBE_DCB
2134 | IXGBE_FLAG_DCB_ENABLED
2136 | IXGBE_FLAG_SRIOV_ENABLED
2140 case (IXGBE_FLAG_RSS_ENABLED
):
2141 mrqc
= IXGBE_MRQC_RSSEN
;
2143 case (IXGBE_FLAG_SRIOV_ENABLED
):
2144 mrqc
= IXGBE_MRQC_VMDQEN
;
2146 #ifdef CONFIG_IXGBE_DCB
2147 case (IXGBE_FLAG_DCB_ENABLED
):
2148 mrqc
= IXGBE_MRQC_RT8TCEN
;
2150 #endif /* CONFIG_IXGBE_DCB */
2159 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2160 * @adapter: address of board private structure
2161 * @index: index of ring to set
2163 static void ixgbe_configure_rscctl(struct ixgbe_adapter
*adapter
, int index
)
2165 struct ixgbe_ring
*rx_ring
;
2166 struct ixgbe_hw
*hw
= &adapter
->hw
;
2171 rx_ring
= adapter
->rx_ring
[index
];
2172 j
= rx_ring
->reg_idx
;
2173 rx_buf_len
= rx_ring
->rx_buf_len
;
2174 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(j
));
2175 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
2177 * we must limit the number of descriptors so that the
2178 * total size of max desc * buf_len is not greater
2181 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2182 #if (MAX_SKB_FRAGS > 16)
2183 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2184 #elif (MAX_SKB_FRAGS > 8)
2185 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2186 #elif (MAX_SKB_FRAGS > 4)
2187 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2189 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2192 if (rx_buf_len
< IXGBE_RXBUFFER_4096
)
2193 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2194 else if (rx_buf_len
< IXGBE_RXBUFFER_8192
)
2195 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2197 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2199 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(j
), rscctrl
);
2203 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2204 * @adapter: board private structure
2206 * Configure the Rx unit of the MAC after a reset.
2208 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
2211 struct ixgbe_hw
*hw
= &adapter
->hw
;
2212 struct ixgbe_ring
*rx_ring
;
2213 struct net_device
*netdev
= adapter
->netdev
;
2214 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2216 u32 rdlen
, rxctrl
, rxcsum
;
2217 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2218 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2219 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2221 u32 reta
= 0, mrqc
= 0;
2225 /* Decide whether to use packet split mode or not */
2226 /* Do not use packet split if we're in SR-IOV Mode */
2227 if (!adapter
->num_vfs
)
2228 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
2230 /* Set the RX buffer length according to the mode */
2231 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
2232 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
2233 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2234 /* PSRTYPE must be initialized in 82599 */
2235 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
2236 IXGBE_PSRTYPE_UDPHDR
|
2237 IXGBE_PSRTYPE_IPV4HDR
|
2238 IXGBE_PSRTYPE_IPV6HDR
|
2239 IXGBE_PSRTYPE_L2HDR
;
2241 IXGBE_PSRTYPE(adapter
->num_vfs
),
2245 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
2246 (netdev
->mtu
<= ETH_DATA_LEN
))
2247 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
2249 rx_buf_len
= ALIGN(max_frame
, 1024);
2252 fctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_FCTRL
);
2253 fctrl
|= IXGBE_FCTRL_BAM
;
2254 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
2255 fctrl
|= IXGBE_FCTRL_PMCF
;
2256 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_FCTRL
, fctrl
);
2258 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
2259 if (adapter
->netdev
->mtu
<= ETH_DATA_LEN
)
2260 hlreg0
&= ~IXGBE_HLREG0_JUMBOEN
;
2262 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
2264 if (netdev
->features
& NETIF_F_FCOE_MTU
)
2265 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
2267 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
2269 rdlen
= adapter
->rx_ring
[0]->count
* sizeof(union ixgbe_adv_rx_desc
);
2270 /* disable receives while setting up the descriptors */
2271 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
2272 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
2275 * Setup the HW Rx Head and Tail Descriptor Pointers and
2276 * the Base and Length of the Rx Descriptor Ring
2278 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2279 rx_ring
= adapter
->rx_ring
[i
];
2280 rdba
= rx_ring
->dma
;
2281 j
= rx_ring
->reg_idx
;
2282 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(j
), (rdba
& DMA_BIT_MASK(32)));
2283 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(j
), (rdba
>> 32));
2284 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(j
), rdlen
);
2285 IXGBE_WRITE_REG(hw
, IXGBE_RDH(j
), 0);
2286 IXGBE_WRITE_REG(hw
, IXGBE_RDT(j
), 0);
2287 rx_ring
->head
= IXGBE_RDH(j
);
2288 rx_ring
->tail
= IXGBE_RDT(j
);
2289 rx_ring
->rx_buf_len
= rx_buf_len
;
2291 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
2292 rx_ring
->flags
|= IXGBE_RING_RX_PS_ENABLED
;
2294 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2297 if (netdev
->features
& NETIF_F_FCOE_MTU
) {
2298 struct ixgbe_ring_feature
*f
;
2299 f
= &adapter
->ring_feature
[RING_F_FCOE
];
2300 if ((i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
)) {
2301 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2302 if (rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
2303 rx_ring
->rx_buf_len
=
2304 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2308 #endif /* IXGBE_FCOE */
2309 ixgbe_configure_srrctl(adapter
, rx_ring
);
2312 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2314 * For VMDq support of different descriptor types or
2315 * buffer sizes through the use of multiple SRRCTL
2316 * registers, RDRXCTL.MVMEN must be set to 1
2318 * also, the manual doesn't mention it clearly but DCA hints
2319 * will only use queue 0's tags unless this bit is set. Side
2320 * effects of setting this bit are only that SRRCTL must be
2321 * fully programmed [0..15]
2323 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2324 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
2325 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
2328 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
2330 u32 reg_offset
, vf_shift
;
2331 u32 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
2332 vt_reg_bits
= IXGBE_VMD_CTL_VMDQ_EN
2333 | IXGBE_VT_CTL_REPLEN
;
2334 vt_reg_bits
|= (adapter
->num_vfs
<<
2335 IXGBE_VT_CTL_POOL_SHIFT
);
2336 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
| vt_reg_bits
);
2337 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, 0);
2339 vf_shift
= adapter
->num_vfs
% 32;
2340 reg_offset
= adapter
->num_vfs
/ 32;
2341 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(0), 0);
2342 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(1), 0);
2343 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(0), 0);
2344 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(1), 0);
2345 /* Enable only the PF's pool for Tx/Rx */
2346 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
), (1 << vf_shift
));
2347 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
), (1 << vf_shift
));
2348 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
2349 ixgbe_set_vmolr(hw
, adapter
->num_vfs
);
2352 /* Program MRQC for the distribution of queues */
2353 mrqc
= ixgbe_setup_mrqc(adapter
);
2355 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
2356 /* Fill out redirection table */
2357 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
2358 if (j
== adapter
->ring_feature
[RING_F_RSS
].indices
)
2360 /* reta = 4-byte sliding window of
2361 * 0x00..(indices-1)(indices-1)00..etc. */
2362 reta
= (reta
<< 8) | (j
* 0x11);
2364 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
2367 /* Fill out hash function seeds */
2368 for (i
= 0; i
< 10; i
++)
2369 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
2371 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2372 mrqc
|= IXGBE_MRQC_RSSEN
;
2373 /* Perform hash on these packet types */
2374 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
2375 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2376 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2377 | IXGBE_MRQC_RSS_FIELD_IPV6
2378 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2379 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
;
2381 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2383 if (adapter
->num_vfs
) {
2386 /* Map PF MAC address in RAR Entry 0 to first pool
2388 hw
->mac
.ops
.set_vmdq(hw
, 0, adapter
->num_vfs
);
2390 /* Set up VF register offsets for selected VT Mode, i.e.
2391 * 64 VFs for SR-IOV */
2392 reg
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
2393 reg
|= IXGBE_GCR_EXT_SRIOV
;
2394 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, reg
);
2397 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2399 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
||
2400 adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
) {
2401 /* Disable indicating checksum in descriptor, enables
2403 rxcsum
|= IXGBE_RXCSUM_PCSD
;
2405 if (!(rxcsum
& IXGBE_RXCSUM_PCSD
)) {
2406 /* Enable IPv4 payload checksum for UDP fragments
2407 * if PCSD is not set */
2408 rxcsum
|= IXGBE_RXCSUM_IPPCSE
;
2411 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2413 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2414 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2415 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
2416 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
2417 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
2420 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
2421 /* Enable 82599 HW-RSC */
2422 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2423 ixgbe_configure_rscctl(adapter
, i
);
2425 /* Disable RSC for ACK packets */
2426 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
2427 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
2431 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
2433 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2434 struct ixgbe_hw
*hw
= &adapter
->hw
;
2435 int pool_ndx
= adapter
->num_vfs
;
2437 /* add VID to filter table */
2438 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, true);
2441 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
2443 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2444 struct ixgbe_hw
*hw
= &adapter
->hw
;
2445 int pool_ndx
= adapter
->num_vfs
;
2447 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2448 ixgbe_irq_disable(adapter
);
2450 vlan_group_set_device(adapter
->vlgrp
, vid
, NULL
);
2452 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2453 ixgbe_irq_enable(adapter
);
2455 /* remove VID from filter table */
2456 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, false);
2459 static void ixgbe_vlan_rx_register(struct net_device
*netdev
,
2460 struct vlan_group
*grp
)
2462 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2466 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2467 ixgbe_irq_disable(adapter
);
2468 adapter
->vlgrp
= grp
;
2471 * For a DCB driver, always enable VLAN tag stripping so we can
2472 * still receive traffic from a DCB-enabled host even if we're
2475 ctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_VLNCTRL
);
2477 /* Disable CFI check */
2478 ctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2480 /* enable VLAN tag stripping */
2481 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2482 ctrl
|= IXGBE_VLNCTRL_VME
;
2483 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
2484 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2486 j
= adapter
->rx_ring
[i
]->reg_idx
;
2487 ctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_RXDCTL(j
));
2488 ctrl
|= IXGBE_RXDCTL_VME
;
2489 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_RXDCTL(j
), ctrl
);
2493 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_VLNCTRL
, ctrl
);
2495 ixgbe_vlan_rx_add_vid(netdev
, 0);
2497 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2498 ixgbe_irq_enable(adapter
);
2501 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
2503 ixgbe_vlan_rx_register(adapter
->netdev
, adapter
->vlgrp
);
2505 if (adapter
->vlgrp
) {
2507 for (vid
= 0; vid
< VLAN_GROUP_ARRAY_LEN
; vid
++) {
2508 if (!vlan_group_get_device(adapter
->vlgrp
, vid
))
2510 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
2515 static u8
*ixgbe_addr_list_itr(struct ixgbe_hw
*hw
, u8
**mc_addr_ptr
, u32
*vmdq
)
2517 struct dev_mc_list
*mc_ptr
;
2518 u8
*addr
= *mc_addr_ptr
;
2521 mc_ptr
= container_of(addr
, struct dev_mc_list
, dmi_addr
[0]);
2523 *mc_addr_ptr
= mc_ptr
->next
->dmi_addr
;
2525 *mc_addr_ptr
= NULL
;
2531 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2532 * @netdev: network interface device structure
2534 * The set_rx_method entry point is called whenever the unicast/multicast
2535 * address list or the network interface flags are updated. This routine is
2536 * responsible for configuring the hardware for proper unicast, multicast and
2539 void ixgbe_set_rx_mode(struct net_device
*netdev
)
2541 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2542 struct ixgbe_hw
*hw
= &adapter
->hw
;
2544 u8
*addr_list
= NULL
;
2547 /* Check for Promiscuous and All Multicast modes */
2549 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
2550 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2552 if (netdev
->flags
& IFF_PROMISC
) {
2553 hw
->addr_ctrl
.user_set_promisc
= 1;
2554 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
2555 vlnctrl
&= ~IXGBE_VLNCTRL_VFE
;
2557 if (netdev
->flags
& IFF_ALLMULTI
) {
2558 fctrl
|= IXGBE_FCTRL_MPE
;
2559 fctrl
&= ~IXGBE_FCTRL_UPE
;
2561 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
2563 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
2564 hw
->addr_ctrl
.user_set_promisc
= 0;
2567 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
2568 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2570 /* reprogram secondary unicast list */
2571 hw
->mac
.ops
.update_uc_addr_list(hw
, netdev
);
2573 /* reprogram multicast list */
2574 addr_count
= netdev_mc_count(netdev
);
2576 addr_list
= netdev
->mc_list
->dmi_addr
;
2577 hw
->mac
.ops
.update_mc_addr_list(hw
, addr_list
, addr_count
,
2578 ixgbe_addr_list_itr
);
2579 if (adapter
->num_vfs
)
2580 ixgbe_restore_vf_multicasts(adapter
);
2583 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
2586 struct ixgbe_q_vector
*q_vector
;
2587 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2589 /* legacy and MSI only use one vector */
2590 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2593 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
2594 struct napi_struct
*napi
;
2595 q_vector
= adapter
->q_vector
[q_idx
];
2596 napi
= &q_vector
->napi
;
2597 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2598 if (!q_vector
->rxr_count
|| !q_vector
->txr_count
) {
2599 if (q_vector
->txr_count
== 1)
2600 napi
->poll
= &ixgbe_clean_txonly
;
2601 else if (q_vector
->rxr_count
== 1)
2602 napi
->poll
= &ixgbe_clean_rxonly
;
2610 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
2613 struct ixgbe_q_vector
*q_vector
;
2614 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2616 /* legacy and MSI only use one vector */
2617 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2620 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
2621 q_vector
= adapter
->q_vector
[q_idx
];
2622 napi_disable(&q_vector
->napi
);
2626 #ifdef CONFIG_IXGBE_DCB
2628 * ixgbe_configure_dcb - Configure DCB hardware
2629 * @adapter: ixgbe adapter struct
2631 * This is called by the driver on open to configure the DCB hardware.
2632 * This is also called by the gennetlink interface when reconfiguring
2635 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
2637 struct ixgbe_hw
*hw
= &adapter
->hw
;
2638 u32 txdctl
, vlnctrl
;
2641 ixgbe_dcb_check_config(&adapter
->dcb_cfg
);
2642 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_TX_CONFIG
);
2643 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_RX_CONFIG
);
2645 /* reconfigure the hardware */
2646 ixgbe_dcb_hw_config(&adapter
->hw
, &adapter
->dcb_cfg
);
2648 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2649 j
= adapter
->tx_ring
[i
]->reg_idx
;
2650 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2651 /* PThresh workaround for Tx hang with DFP enabled. */
2653 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2655 /* Enable VLAN tag insert/strip */
2656 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2657 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2658 vlnctrl
|= IXGBE_VLNCTRL_VME
| IXGBE_VLNCTRL_VFE
;
2659 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2660 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2661 } else if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2662 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
2663 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2664 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2665 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2666 j
= adapter
->rx_ring
[i
]->reg_idx
;
2667 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2668 vlnctrl
|= IXGBE_RXDCTL_VME
;
2669 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
2672 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
2676 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
2678 struct net_device
*netdev
= adapter
->netdev
;
2679 struct ixgbe_hw
*hw
= &adapter
->hw
;
2682 ixgbe_set_rx_mode(netdev
);
2684 ixgbe_restore_vlan(adapter
);
2685 #ifdef CONFIG_IXGBE_DCB
2686 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2687 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2688 netif_set_gso_max_size(netdev
, 32768);
2690 netif_set_gso_max_size(netdev
, 65536);
2691 ixgbe_configure_dcb(adapter
);
2693 netif_set_gso_max_size(netdev
, 65536);
2696 netif_set_gso_max_size(netdev
, 65536);
2700 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
2701 ixgbe_configure_fcoe(adapter
);
2703 #endif /* IXGBE_FCOE */
2704 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
2705 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2706 adapter
->tx_ring
[i
]->atr_sample_rate
=
2707 adapter
->atr_sample_rate
;
2708 ixgbe_init_fdir_signature_82599(hw
, adapter
->fdir_pballoc
);
2709 } else if (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
) {
2710 ixgbe_init_fdir_perfect_82599(hw
, adapter
->fdir_pballoc
);
2713 ixgbe_configure_tx(adapter
);
2714 ixgbe_configure_rx(adapter
);
2715 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2716 ixgbe_alloc_rx_buffers(adapter
, adapter
->rx_ring
[i
],
2717 (adapter
->rx_ring
[i
]->count
- 1));
2720 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
2722 switch (hw
->phy
.type
) {
2723 case ixgbe_phy_sfp_avago
:
2724 case ixgbe_phy_sfp_ftl
:
2725 case ixgbe_phy_sfp_intel
:
2726 case ixgbe_phy_sfp_unknown
:
2727 case ixgbe_phy_tw_tyco
:
2728 case ixgbe_phy_tw_unknown
:
2736 * ixgbe_sfp_link_config - set up SFP+ link
2737 * @adapter: pointer to private adapter struct
2739 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
2741 struct ixgbe_hw
*hw
= &adapter
->hw
;
2743 if (hw
->phy
.multispeed_fiber
) {
2745 * In multispeed fiber setups, the device may not have
2746 * had a physical connection when the driver loaded.
2747 * If that's the case, the initial link configuration
2748 * couldn't get the MAC into 10G or 1G mode, so we'll
2749 * never have a link status change interrupt fire.
2750 * We need to try and force an autonegotiation
2751 * session, then bring up link.
2753 hw
->mac
.ops
.setup_sfp(hw
);
2754 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
2755 schedule_work(&adapter
->multispeed_fiber_task
);
2758 * Direct Attach Cu and non-multispeed fiber modules
2759 * still need to be configured properly prior to
2762 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_MOD_TASK
))
2763 schedule_work(&adapter
->sfp_config_module_task
);
2768 * ixgbe_non_sfp_link_config - set up non-SFP+ link
2769 * @hw: pointer to private hardware struct
2771 * Returns 0 on success, negative on failure
2773 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
2776 bool negotiation
, link_up
= false;
2777 u32 ret
= IXGBE_ERR_LINK_SETUP
;
2779 if (hw
->mac
.ops
.check_link
)
2780 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
2785 if (hw
->mac
.ops
.get_link_capabilities
)
2786 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
2790 if (hw
->mac
.ops
.setup_link
)
2791 ret
= hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, link_up
);
2796 #define IXGBE_MAX_RX_DESC_POLL 10
2797 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
2800 int j
= adapter
->rx_ring
[rxr
]->reg_idx
;
2803 for (k
= 0; k
< IXGBE_MAX_RX_DESC_POLL
; k
++) {
2804 if (IXGBE_READ_REG(&adapter
->hw
,
2805 IXGBE_RXDCTL(j
)) & IXGBE_RXDCTL_ENABLE
)
2810 if (k
>= IXGBE_MAX_RX_DESC_POLL
) {
2811 DPRINTK(DRV
, ERR
, "RXDCTL.ENABLE on Rx queue %d "
2812 "not set within the polling period\n", rxr
);
2814 ixgbe_release_rx_desc(&adapter
->hw
, adapter
->rx_ring
[rxr
],
2815 (adapter
->rx_ring
[rxr
]->count
- 1));
2818 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
2820 struct net_device
*netdev
= adapter
->netdev
;
2821 struct ixgbe_hw
*hw
= &adapter
->hw
;
2823 int num_rx_rings
= adapter
->num_rx_queues
;
2825 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2826 u32 txdctl
, rxdctl
, mhadd
;
2831 ixgbe_get_hw_control(adapter
);
2833 if ((adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) ||
2834 (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
)) {
2835 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2836 gpie
= (IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_EIAME
|
2837 IXGBE_GPIE_PBA_SUPPORT
| IXGBE_GPIE_OCD
);
2842 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
2843 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
2844 gpie
|= IXGBE_GPIE_VTMODE_64
;
2846 /* XXX: to interrupt immediately for EICS writes, enable this */
2847 /* gpie |= IXGBE_GPIE_EIMEN; */
2848 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2851 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2853 * use EIAM to auto-mask when MSI-X interrupt is asserted
2854 * this saves a register write for every interrupt
2856 switch (hw
->mac
.type
) {
2857 case ixgbe_mac_82598EB
:
2858 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
2861 case ixgbe_mac_82599EB
:
2862 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2863 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2867 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2868 * specifically only auto mask tx and rx interrupts */
2869 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
2872 /* Enable fan failure interrupt if media type is copper */
2873 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
2874 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
2875 gpie
|= IXGBE_SDP1_GPIEN
;
2876 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2879 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2880 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
2881 gpie
|= IXGBE_SDP1_GPIEN
;
2882 gpie
|= IXGBE_SDP2_GPIEN
;
2883 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2887 /* adjust max frame to be able to do baby jumbo for FCoE */
2888 if ((netdev
->features
& NETIF_F_FCOE_MTU
) &&
2889 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
2890 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2892 #endif /* IXGBE_FCOE */
2893 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
2894 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
2895 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
2896 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
2898 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
2901 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2902 j
= adapter
->tx_ring
[i
]->reg_idx
;
2903 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2904 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2905 txdctl
|= (8 << 16);
2906 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2909 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2910 /* DMATXCTL.EN must be set after all Tx queue config is done */
2911 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
2912 dmatxctl
|= IXGBE_DMATXCTL_TE
;
2913 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
2915 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2916 j
= adapter
->tx_ring
[i
]->reg_idx
;
2917 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2918 txdctl
|= IXGBE_TXDCTL_ENABLE
;
2919 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2920 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2922 /* poll for Tx Enable ready */
2925 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2926 } while (--wait_loop
&&
2927 !(txdctl
& IXGBE_TXDCTL_ENABLE
));
2929 DPRINTK(DRV
, ERR
, "Could not enable "
2930 "Tx Queue %d\n", j
);
2934 for (i
= 0; i
< num_rx_rings
; i
++) {
2935 j
= adapter
->rx_ring
[i
]->reg_idx
;
2936 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2937 /* enable PTHRESH=32 descriptors (half the internal cache)
2938 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2939 * this also removes a pesky rx_no_buffer_count increment */
2941 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
2942 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), rxdctl
);
2943 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
2944 ixgbe_rx_desc_queue_enable(adapter
, i
);
2946 /* enable all receives */
2947 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
2948 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2949 rxdctl
|= (IXGBE_RXCTRL_DMBYPS
| IXGBE_RXCTRL_RXEN
);
2951 rxdctl
|= IXGBE_RXCTRL_RXEN
;
2952 hw
->mac
.ops
.enable_rx_dma(hw
, rxdctl
);
2954 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
2955 ixgbe_configure_msix(adapter
);
2957 ixgbe_configure_msi_and_legacy(adapter
);
2959 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
2960 ixgbe_napi_enable_all(adapter
);
2962 /* clear any pending interrupts, may auto mask */
2963 IXGBE_READ_REG(hw
, IXGBE_EICR
);
2965 ixgbe_irq_enable(adapter
);
2968 * If this adapter has a fan, check to see if we had a failure
2969 * before we enabled the interrupt.
2971 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
2972 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
2973 if (esdp
& IXGBE_ESDP_SDP1
)
2975 "Fan has stopped, replace the adapter\n");
2979 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2980 * arrived before interrupts were enabled but after probe. Such
2981 * devices wouldn't have their type identified yet. We need to
2982 * kick off the SFP+ module setup first, then try to bring up link.
2983 * If we're not hot-pluggable SFP+, we just need to configure link
2986 if (hw
->phy
.type
== ixgbe_phy_unknown
) {
2987 err
= hw
->phy
.ops
.identify(hw
);
2988 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
2990 * Take the device down and schedule the sfp tasklet
2991 * which will unregister_netdev and log it.
2993 ixgbe_down(adapter
);
2994 schedule_work(&adapter
->sfp_config_module_task
);
2999 if (ixgbe_is_sfp(hw
)) {
3000 ixgbe_sfp_link_config(adapter
);
3002 err
= ixgbe_non_sfp_link_config(hw
);
3004 DPRINTK(PROBE
, ERR
, "link_config FAILED %d\n", err
);
3007 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3008 set_bit(__IXGBE_FDIR_INIT_DONE
,
3009 &(adapter
->tx_ring
[i
]->reinit_state
));
3011 /* enable transmits */
3012 netif_tx_start_all_queues(netdev
);
3014 /* bring the link up in the watchdog, this could race with our first
3015 * link up interrupt but shouldn't be a problem */
3016 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
3017 adapter
->link_check_timeout
= jiffies
;
3018 mod_timer(&adapter
->watchdog_timer
, jiffies
);
3020 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3021 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
3022 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
3023 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
3028 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
3030 WARN_ON(in_interrupt());
3031 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
3033 ixgbe_down(adapter
);
3035 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
3038 int ixgbe_up(struct ixgbe_adapter
*adapter
)
3040 /* hardware has been reset, we need to reload some things */
3041 ixgbe_configure(adapter
);
3043 return ixgbe_up_complete(adapter
);
3046 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
3048 struct ixgbe_hw
*hw
= &adapter
->hw
;
3051 err
= hw
->mac
.ops
.init_hw(hw
);
3054 case IXGBE_ERR_SFP_NOT_PRESENT
:
3056 case IXGBE_ERR_MASTER_REQUESTS_PENDING
:
3057 dev_err(&adapter
->pdev
->dev
, "master disable timed out\n");
3059 case IXGBE_ERR_EEPROM_VERSION
:
3060 /* We are running on a pre-production device, log a warning */
3061 dev_warn(&adapter
->pdev
->dev
, "This device is a pre-production "
3062 "adapter/LOM. Please be aware there may be issues "
3063 "associated with your hardware. If you are "
3064 "experiencing problems please contact your Intel or "
3065 "hardware representative who provided you with this "
3069 dev_err(&adapter
->pdev
->dev
, "Hardware Error: %d\n", err
);
3072 /* reprogram the RAR[0] in case user changed it. */
3073 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
3078 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3079 * @adapter: board private structure
3080 * @rx_ring: ring to free buffers from
3082 static void ixgbe_clean_rx_ring(struct ixgbe_adapter
*adapter
,
3083 struct ixgbe_ring
*rx_ring
)
3085 struct pci_dev
*pdev
= adapter
->pdev
;
3089 /* Free all the Rx ring sk_buffs */
3091 for (i
= 0; i
< rx_ring
->count
; i
++) {
3092 struct ixgbe_rx_buffer
*rx_buffer_info
;
3094 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
3095 if (rx_buffer_info
->dma
) {
3096 pci_unmap_single(pdev
, rx_buffer_info
->dma
,
3097 rx_ring
->rx_buf_len
,
3098 PCI_DMA_FROMDEVICE
);
3099 rx_buffer_info
->dma
= 0;
3101 if (rx_buffer_info
->skb
) {
3102 struct sk_buff
*skb
= rx_buffer_info
->skb
;
3103 rx_buffer_info
->skb
= NULL
;
3105 struct sk_buff
*this = skb
;
3107 dev_kfree_skb(this);
3110 if (!rx_buffer_info
->page
)
3112 if (rx_buffer_info
->page_dma
) {
3113 pci_unmap_page(pdev
, rx_buffer_info
->page_dma
,
3114 PAGE_SIZE
/ 2, PCI_DMA_FROMDEVICE
);
3115 rx_buffer_info
->page_dma
= 0;
3117 put_page(rx_buffer_info
->page
);
3118 rx_buffer_info
->page
= NULL
;
3119 rx_buffer_info
->page_offset
= 0;
3122 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
3123 memset(rx_ring
->rx_buffer_info
, 0, size
);
3125 /* Zero out the descriptor ring */
3126 memset(rx_ring
->desc
, 0, rx_ring
->size
);
3128 rx_ring
->next_to_clean
= 0;
3129 rx_ring
->next_to_use
= 0;
3132 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->head
);
3134 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->tail
);
3138 * ixgbe_clean_tx_ring - Free Tx Buffers
3139 * @adapter: board private structure
3140 * @tx_ring: ring to be cleaned
3142 static void ixgbe_clean_tx_ring(struct ixgbe_adapter
*adapter
,
3143 struct ixgbe_ring
*tx_ring
)
3145 struct ixgbe_tx_buffer
*tx_buffer_info
;
3149 /* Free all the Tx ring sk_buffs */
3151 for (i
= 0; i
< tx_ring
->count
; i
++) {
3152 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
3153 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
3156 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
3157 memset(tx_ring
->tx_buffer_info
, 0, size
);
3159 /* Zero out the descriptor ring */
3160 memset(tx_ring
->desc
, 0, tx_ring
->size
);
3162 tx_ring
->next_to_use
= 0;
3163 tx_ring
->next_to_clean
= 0;
3166 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->head
);
3168 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
3172 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3173 * @adapter: board private structure
3175 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
3179 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3180 ixgbe_clean_rx_ring(adapter
, adapter
->rx_ring
[i
]);
3184 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3185 * @adapter: board private structure
3187 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
3191 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3192 ixgbe_clean_tx_ring(adapter
, adapter
->tx_ring
[i
]);
3195 void ixgbe_down(struct ixgbe_adapter
*adapter
)
3197 struct net_device
*netdev
= adapter
->netdev
;
3198 struct ixgbe_hw
*hw
= &adapter
->hw
;
3203 /* signal that we are down to the interrupt handler */
3204 set_bit(__IXGBE_DOWN
, &adapter
->state
);
3206 /* disable receive for all VFs and wait one second */
3207 if (adapter
->num_vfs
) {
3208 for (i
= 0 ; i
< adapter
->num_vfs
; i
++)
3209 adapter
->vfinfo
[i
].clear_to_send
= 0;
3211 /* ping all the active vfs to let them know we are going down */
3212 ixgbe_ping_all_vfs(adapter
);
3213 /* Disable all VFTE/VFRE TX/RX */
3214 ixgbe_disable_tx_rx(adapter
);
3217 /* disable receives */
3218 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3219 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3221 netif_tx_disable(netdev
);
3223 IXGBE_WRITE_FLUSH(hw
);
3226 netif_tx_stop_all_queues(netdev
);
3228 ixgbe_irq_disable(adapter
);
3230 ixgbe_napi_disable_all(adapter
);
3232 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
3233 del_timer_sync(&adapter
->sfp_timer
);
3234 del_timer_sync(&adapter
->watchdog_timer
);
3235 cancel_work_sync(&adapter
->watchdog_task
);
3237 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3238 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
3239 cancel_work_sync(&adapter
->fdir_reinit_task
);
3241 /* disable transmits in the hardware now that interrupts are off */
3242 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3243 j
= adapter
->tx_ring
[i
]->reg_idx
;
3244 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3245 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
),
3246 (txdctl
& ~IXGBE_TXDCTL_ENABLE
));
3248 /* Disable the Tx DMA engine on 82599 */
3249 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3250 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
3251 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
3252 ~IXGBE_DMATXCTL_TE
));
3254 netif_carrier_off(netdev
);
3256 /* clear n-tuple filters that are cached */
3257 ethtool_ntuple_flush(netdev
);
3259 if (!pci_channel_offline(adapter
->pdev
))
3260 ixgbe_reset(adapter
);
3261 ixgbe_clean_all_tx_rings(adapter
);
3262 ixgbe_clean_all_rx_rings(adapter
);
3264 #ifdef CONFIG_IXGBE_DCA
3265 /* since we reset the hardware DCA settings were cleared */
3266 ixgbe_setup_dca(adapter
);
3271 * ixgbe_poll - NAPI Rx polling callback
3272 * @napi: structure for representing this polling device
3273 * @budget: how many packets driver is allowed to clean
3275 * This function is used for legacy and MSI, NAPI mode
3277 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
3279 struct ixgbe_q_vector
*q_vector
=
3280 container_of(napi
, struct ixgbe_q_vector
, napi
);
3281 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
3282 int tx_clean_complete
, work_done
= 0;
3284 #ifdef CONFIG_IXGBE_DCA
3285 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
3286 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[0]);
3287 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[0]);
3291 tx_clean_complete
= ixgbe_clean_tx_irq(q_vector
, adapter
->tx_ring
[0]);
3292 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
[0], &work_done
, budget
);
3294 if (!tx_clean_complete
)
3297 /* If budget not fully consumed, exit the polling mode */
3298 if (work_done
< budget
) {
3299 napi_complete(napi
);
3300 if (adapter
->rx_itr_setting
& 1)
3301 ixgbe_set_itr(adapter
);
3302 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
3303 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
3309 * ixgbe_tx_timeout - Respond to a Tx Hang
3310 * @netdev: network interface device structure
3312 static void ixgbe_tx_timeout(struct net_device
*netdev
)
3314 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3316 /* Do the reset outside of interrupt context */
3317 schedule_work(&adapter
->reset_task
);
3320 static void ixgbe_reset_task(struct work_struct
*work
)
3322 struct ixgbe_adapter
*adapter
;
3323 adapter
= container_of(work
, struct ixgbe_adapter
, reset_task
);
3325 /* If we're already down or resetting, just bail */
3326 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
3327 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
3330 adapter
->tx_timeout_count
++;
3332 ixgbe_reinit_locked(adapter
);
3335 #ifdef CONFIG_IXGBE_DCB
3336 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
3339 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_DCB
];
3341 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
3345 adapter
->num_rx_queues
= f
->indices
;
3346 adapter
->num_tx_queues
= f
->indices
;
3354 * ixgbe_set_rss_queues: Allocate queues for RSS
3355 * @adapter: board private structure to initialize
3357 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3358 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3361 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
3364 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
3366 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3368 adapter
->num_rx_queues
= f
->indices
;
3369 adapter
->num_tx_queues
= f
->indices
;
3379 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3380 * @adapter: board private structure to initialize
3382 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3383 * to the original CPU that initiated the Tx session. This runs in addition
3384 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3385 * Rx load across CPUs using RSS.
3388 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter
*adapter
)
3391 struct ixgbe_ring_feature
*f_fdir
= &adapter
->ring_feature
[RING_F_FDIR
];
3393 f_fdir
->indices
= min((int)num_online_cpus(), f_fdir
->indices
);
3396 /* Flow Director must have RSS enabled */
3397 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
3398 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3399 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)))) {
3400 adapter
->num_tx_queues
= f_fdir
->indices
;
3401 adapter
->num_rx_queues
= f_fdir
->indices
;
3404 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
3405 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
3412 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3413 * @adapter: board private structure to initialize
3415 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3416 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3417 * rx queues out of the max number of rx queues, instead, it is used as the
3418 * index of the first rx queue used by FCoE.
3421 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
3424 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
3426 f
->indices
= min((int)num_online_cpus(), f
->indices
);
3427 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
3428 adapter
->num_rx_queues
= 1;
3429 adapter
->num_tx_queues
= 1;
3430 #ifdef CONFIG_IXGBE_DCB
3431 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3432 DPRINTK(PROBE
, INFO
, "FCoE enabled with DCB \n");
3433 ixgbe_set_dcb_queues(adapter
);
3436 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3437 DPRINTK(PROBE
, INFO
, "FCoE enabled with RSS \n");
3438 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
3439 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
3440 ixgbe_set_fdir_queues(adapter
);
3442 ixgbe_set_rss_queues(adapter
);
3444 /* adding FCoE rx rings to the end */
3445 f
->mask
= adapter
->num_rx_queues
;
3446 adapter
->num_rx_queues
+= f
->indices
;
3447 adapter
->num_tx_queues
+= f
->indices
;
3455 #endif /* IXGBE_FCOE */
3457 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3458 * @adapter: board private structure to initialize
3460 * IOV doesn't actually use anything, so just NAK the
3461 * request for now and let the other queue routines
3462 * figure out what to do.
3464 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter
*adapter
)
3470 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3471 * @adapter: board private structure to initialize
3473 * This is the top level queue allocation routine. The order here is very
3474 * important, starting with the "most" number of features turned on at once,
3475 * and ending with the smallest set of features. This way large combinations
3476 * can be allocated if they're turned on, and smaller combinations are the
3477 * fallthrough conditions.
3480 static void ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
3482 /* Start with base case */
3483 adapter
->num_rx_queues
= 1;
3484 adapter
->num_tx_queues
= 1;
3485 adapter
->num_rx_pools
= adapter
->num_rx_queues
;
3486 adapter
->num_rx_queues_per_pool
= 1;
3488 if (ixgbe_set_sriov_queues(adapter
))
3492 if (ixgbe_set_fcoe_queues(adapter
))
3495 #endif /* IXGBE_FCOE */
3496 #ifdef CONFIG_IXGBE_DCB
3497 if (ixgbe_set_dcb_queues(adapter
))
3501 if (ixgbe_set_fdir_queues(adapter
))
3504 if (ixgbe_set_rss_queues(adapter
))
3507 /* fallback to base case */
3508 adapter
->num_rx_queues
= 1;
3509 adapter
->num_tx_queues
= 1;
3512 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3513 adapter
->netdev
->real_num_tx_queues
= adapter
->num_tx_queues
;
3516 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
3519 int err
, vector_threshold
;
3521 /* We'll want at least 3 (vector_threshold):
3524 * 3) Other (Link Status Change, etc.)
3525 * 4) TCP Timer (optional)
3527 vector_threshold
= MIN_MSIX_COUNT
;
3529 /* The more we get, the more we will assign to Tx/Rx Cleanup
3530 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3531 * Right now, we simply care about how many we'll get; we'll
3532 * set them up later while requesting irq's.
3534 while (vectors
>= vector_threshold
) {
3535 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
3537 if (!err
) /* Success in acquiring all requested vectors. */
3540 vectors
= 0; /* Nasty failure, quit now */
3541 else /* err == number of vectors we should try again with */
3545 if (vectors
< vector_threshold
) {
3546 /* Can't allocate enough MSI-X interrupts? Oh well.
3547 * This just means we'll go with either a single MSI
3548 * vector or fall back to legacy interrupts.
3550 DPRINTK(HW
, DEBUG
, "Unable to allocate MSI-X interrupts\n");
3551 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
3552 kfree(adapter
->msix_entries
);
3553 adapter
->msix_entries
= NULL
;
3555 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
3557 * Adjust for only the vectors we'll use, which is minimum
3558 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3559 * vectors we were allocated.
3561 adapter
->num_msix_vectors
= min(vectors
,
3562 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
3567 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3568 * @adapter: board private structure to initialize
3570 * Cache the descriptor ring offsets for RSS to the assigned rings.
3573 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
3578 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3579 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3580 adapter
->rx_ring
[i
]->reg_idx
= i
;
3581 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3582 adapter
->tx_ring
[i
]->reg_idx
= i
;
3591 #ifdef CONFIG_IXGBE_DCB
3593 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3594 * @adapter: board private structure to initialize
3596 * Cache the descriptor ring offsets for DCB to the assigned rings.
3599 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
3603 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
3605 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3606 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
3607 /* the number of queues is assumed to be symmetric */
3608 for (i
= 0; i
< dcb_i
; i
++) {
3609 adapter
->rx_ring
[i
]->reg_idx
= i
<< 3;
3610 adapter
->tx_ring
[i
]->reg_idx
= i
<< 2;
3613 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
3616 * Tx TC0 starts at: descriptor queue 0
3617 * Tx TC1 starts at: descriptor queue 32
3618 * Tx TC2 starts at: descriptor queue 64
3619 * Tx TC3 starts at: descriptor queue 80
3620 * Tx TC4 starts at: descriptor queue 96
3621 * Tx TC5 starts at: descriptor queue 104
3622 * Tx TC6 starts at: descriptor queue 112
3623 * Tx TC7 starts at: descriptor queue 120
3625 * Rx TC0-TC7 are offset by 16 queues each
3627 for (i
= 0; i
< 3; i
++) {
3628 adapter
->tx_ring
[i
]->reg_idx
= i
<< 5;
3629 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
3631 for ( ; i
< 5; i
++) {
3632 adapter
->tx_ring
[i
]->reg_idx
=
3634 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
3636 for ( ; i
< dcb_i
; i
++) {
3637 adapter
->tx_ring
[i
]->reg_idx
=
3639 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
3643 } else if (dcb_i
== 4) {
3645 * Tx TC0 starts at: descriptor queue 0
3646 * Tx TC1 starts at: descriptor queue 64
3647 * Tx TC2 starts at: descriptor queue 96
3648 * Tx TC3 starts at: descriptor queue 112
3650 * Rx TC0-TC3 are offset by 32 queues each
3652 adapter
->tx_ring
[0]->reg_idx
= 0;
3653 adapter
->tx_ring
[1]->reg_idx
= 64;
3654 adapter
->tx_ring
[2]->reg_idx
= 96;
3655 adapter
->tx_ring
[3]->reg_idx
= 112;
3656 for (i
= 0 ; i
< dcb_i
; i
++)
3657 adapter
->rx_ring
[i
]->reg_idx
= i
<< 5;
3675 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3676 * @adapter: board private structure to initialize
3678 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3681 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter
*adapter
)
3686 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
3687 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
3688 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))) {
3689 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3690 adapter
->rx_ring
[i
]->reg_idx
= i
;
3691 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3692 adapter
->tx_ring
[i
]->reg_idx
= i
;
3701 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3702 * @adapter: board private structure to initialize
3704 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3707 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
3709 int i
, fcoe_rx_i
= 0, fcoe_tx_i
= 0;
3711 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
3713 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
3714 #ifdef CONFIG_IXGBE_DCB
3715 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3716 struct ixgbe_fcoe
*fcoe
= &adapter
->fcoe
;
3718 ixgbe_cache_ring_dcb(adapter
);
3719 /* find out queues in TC for FCoE */
3720 fcoe_rx_i
= adapter
->rx_ring
[fcoe
->tc
]->reg_idx
+ 1;
3721 fcoe_tx_i
= adapter
->tx_ring
[fcoe
->tc
]->reg_idx
+ 1;
3723 * In 82599, the number of Tx queues for each traffic
3724 * class for both 8-TC and 4-TC modes are:
3725 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3726 * 8 TCs: 32 32 16 16 8 8 8 8
3727 * 4 TCs: 64 64 32 32
3728 * We have max 8 queues for FCoE, where 8 the is
3729 * FCoE redirection table size. If TC for FCoE is
3730 * less than or equal to TC3, we have enough queues
3731 * to add max of 8 queues for FCoE, so we start FCoE
3732 * tx descriptor from the next one, i.e., reg_idx + 1.
3733 * If TC for FCoE is above TC3, implying 8 TC mode,
3734 * and we need 8 for FCoE, we have to take all queues
3735 * in that traffic class for FCoE.
3737 if ((f
->indices
== IXGBE_FCRETA_SIZE
) && (fcoe
->tc
> 3))
3740 #endif /* CONFIG_IXGBE_DCB */
3741 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3742 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
3743 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
3744 ixgbe_cache_ring_fdir(adapter
);
3746 ixgbe_cache_ring_rss(adapter
);
3748 fcoe_rx_i
= f
->mask
;
3749 fcoe_tx_i
= f
->mask
;
3751 for (i
= 0; i
< f
->indices
; i
++, fcoe_rx_i
++, fcoe_tx_i
++) {
3752 adapter
->rx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_rx_i
;
3753 adapter
->tx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_tx_i
;
3760 #endif /* IXGBE_FCOE */
3762 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
3763 * @adapter: board private structure to initialize
3765 * SR-IOV doesn't use any descriptor rings but changes the default if
3766 * no other mapping is used.
3769 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter
*adapter
)
3771 adapter
->rx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
3772 adapter
->tx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
3773 if (adapter
->num_vfs
)
3780 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3781 * @adapter: board private structure to initialize
3783 * Once we know the feature-set enabled for the device, we'll cache
3784 * the register offset the descriptor ring is assigned to.
3786 * Note, the order the various feature calls is important. It must start with
3787 * the "most" features enabled at the same time, then trickle down to the
3788 * least amount of features turned on at once.
3790 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
3792 /* start with default case */
3793 adapter
->rx_ring
[0]->reg_idx
= 0;
3794 adapter
->tx_ring
[0]->reg_idx
= 0;
3796 if (ixgbe_cache_ring_sriov(adapter
))
3800 if (ixgbe_cache_ring_fcoe(adapter
))
3803 #endif /* IXGBE_FCOE */
3804 #ifdef CONFIG_IXGBE_DCB
3805 if (ixgbe_cache_ring_dcb(adapter
))
3809 if (ixgbe_cache_ring_fdir(adapter
))
3812 if (ixgbe_cache_ring_rss(adapter
))
3817 * ixgbe_alloc_queues - Allocate memory for all rings
3818 * @adapter: board private structure to initialize
3820 * We allocate one ring per queue at run-time since we don't know the
3821 * number of queues at compile-time. The polling_netdev array is
3822 * intended for Multiqueue, but should work fine with a single queue.
3824 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
3827 int orig_node
= adapter
->node
;
3829 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3830 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
3831 if (orig_node
== -1) {
3832 int cur_node
= next_online_node(adapter
->node
);
3833 if (cur_node
== MAX_NUMNODES
)
3834 cur_node
= first_online_node
;
3835 adapter
->node
= cur_node
;
3837 ring
= kzalloc_node(sizeof(struct ixgbe_ring
), GFP_KERNEL
,
3840 ring
= kzalloc(sizeof(struct ixgbe_ring
), GFP_KERNEL
);
3842 goto err_tx_ring_allocation
;
3843 ring
->count
= adapter
->tx_ring_count
;
3844 ring
->queue_index
= i
;
3845 ring
->numa_node
= adapter
->node
;
3847 adapter
->tx_ring
[i
] = ring
;
3850 /* Restore the adapter's original node */
3851 adapter
->node
= orig_node
;
3853 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3854 struct ixgbe_ring
*ring
= adapter
->rx_ring
[i
];
3855 if (orig_node
== -1) {
3856 int cur_node
= next_online_node(adapter
->node
);
3857 if (cur_node
== MAX_NUMNODES
)
3858 cur_node
= first_online_node
;
3859 adapter
->node
= cur_node
;
3861 ring
= kzalloc_node(sizeof(struct ixgbe_ring
), GFP_KERNEL
,
3864 ring
= kzalloc(sizeof(struct ixgbe_ring
), GFP_KERNEL
);
3866 goto err_rx_ring_allocation
;
3867 ring
->count
= adapter
->rx_ring_count
;
3868 ring
->queue_index
= i
;
3869 ring
->numa_node
= adapter
->node
;
3871 adapter
->rx_ring
[i
] = ring
;
3874 /* Restore the adapter's original node */
3875 adapter
->node
= orig_node
;
3877 ixgbe_cache_ring_register(adapter
);
3881 err_rx_ring_allocation
:
3882 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3883 kfree(adapter
->tx_ring
[i
]);
3884 err_tx_ring_allocation
:
3889 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3890 * @adapter: board private structure to initialize
3892 * Attempt to configure the interrupts using the best available
3893 * capabilities of the hardware and the kernel.
3895 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
3897 struct ixgbe_hw
*hw
= &adapter
->hw
;
3899 int vector
, v_budget
;
3902 * It's easy to be greedy for MSI-X vectors, but it really
3903 * doesn't do us much good if we have a lot more vectors
3904 * than CPU's. So let's be conservative and only ask for
3905 * (roughly) the same number of vectors as there are CPU's.
3907 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
3908 (int)num_online_cpus()) + NON_Q_VECTORS
;
3911 * At the same time, hardware can only support a maximum of
3912 * hw.mac->max_msix_vectors vectors. With features
3913 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3914 * descriptor queues supported by our device. Thus, we cap it off in
3915 * those rare cases where the cpu count also exceeds our vector limit.
3917 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
3919 /* A failure in MSI-X entry allocation isn't fatal, but it does
3920 * mean we disable MSI-X capabilities of the adapter. */
3921 adapter
->msix_entries
= kcalloc(v_budget
,
3922 sizeof(struct msix_entry
), GFP_KERNEL
);
3923 if (adapter
->msix_entries
) {
3924 for (vector
= 0; vector
< v_budget
; vector
++)
3925 adapter
->msix_entries
[vector
].entry
= vector
;
3927 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
3929 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3933 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
3934 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
3935 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
3936 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
3937 adapter
->atr_sample_rate
= 0;
3938 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
3939 ixgbe_disable_sriov(adapter
);
3941 ixgbe_set_num_queues(adapter
);
3943 err
= pci_enable_msi(adapter
->pdev
);
3945 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
3947 DPRINTK(HW
, DEBUG
, "Unable to allocate MSI interrupt, "
3948 "falling back to legacy. Error: %d\n", err
);
3958 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3959 * @adapter: board private structure to initialize
3961 * We allocate one q_vector per queue interrupt. If allocation fails we
3964 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
3966 int q_idx
, num_q_vectors
;
3967 struct ixgbe_q_vector
*q_vector
;
3969 int (*poll
)(struct napi_struct
*, int);
3971 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3972 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3973 napi_vectors
= adapter
->num_rx_queues
;
3974 poll
= &ixgbe_clean_rxtx_many
;
3981 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
3982 q_vector
= kzalloc_node(sizeof(struct ixgbe_q_vector
),
3983 GFP_KERNEL
, adapter
->node
);
3985 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
),
3989 q_vector
->adapter
= adapter
;
3990 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
3991 q_vector
->eitr
= adapter
->tx_eitr_param
;
3993 q_vector
->eitr
= adapter
->rx_eitr_param
;
3994 q_vector
->v_idx
= q_idx
;
3995 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, (*poll
), 64);
3996 adapter
->q_vector
[q_idx
] = q_vector
;
4004 q_vector
= adapter
->q_vector
[q_idx
];
4005 netif_napi_del(&q_vector
->napi
);
4007 adapter
->q_vector
[q_idx
] = NULL
;
4013 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4014 * @adapter: board private structure to initialize
4016 * This function frees the memory allocated to the q_vectors. In addition if
4017 * NAPI is enabled it will delete any references to the NAPI struct prior
4018 * to freeing the q_vector.
4020 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
4022 int q_idx
, num_q_vectors
;
4024 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4025 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4029 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4030 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
4031 adapter
->q_vector
[q_idx
] = NULL
;
4032 netif_napi_del(&q_vector
->napi
);
4037 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
4039 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4040 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4041 pci_disable_msix(adapter
->pdev
);
4042 kfree(adapter
->msix_entries
);
4043 adapter
->msix_entries
= NULL
;
4044 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
4045 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
4046 pci_disable_msi(adapter
->pdev
);
4052 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4053 * @adapter: board private structure to initialize
4055 * We determine which interrupt scheme to use based on...
4056 * - Kernel support (MSI, MSI-X)
4057 * - which can be user-defined (via MODULE_PARAM)
4058 * - Hardware queue count (num_*_queues)
4059 * - defined by miscellaneous hardware support/features (RSS, etc.)
4061 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4065 /* Number of supported queues */
4066 ixgbe_set_num_queues(adapter
);
4068 err
= ixgbe_set_interrupt_capability(adapter
);
4070 DPRINTK(PROBE
, ERR
, "Unable to setup interrupt capabilities\n");
4071 goto err_set_interrupt
;
4074 err
= ixgbe_alloc_q_vectors(adapter
);
4076 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for queue "
4078 goto err_alloc_q_vectors
;
4081 err
= ixgbe_alloc_queues(adapter
);
4083 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for queues\n");
4084 goto err_alloc_queues
;
4087 DPRINTK(DRV
, INFO
, "Multiqueue %s: Rx Queue count = %u, "
4088 "Tx Queue count = %u\n",
4089 (adapter
->num_rx_queues
> 1) ? "Enabled" :
4090 "Disabled", adapter
->num_rx_queues
, adapter
->num_tx_queues
);
4092 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4097 ixgbe_free_q_vectors(adapter
);
4098 err_alloc_q_vectors
:
4099 ixgbe_reset_interrupt_capability(adapter
);
4105 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4106 * @adapter: board private structure to clear interrupt scheme on
4108 * We go through and clear interrupt specific resources and reset the structure
4109 * to pre-load conditions
4111 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4115 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4116 kfree(adapter
->tx_ring
[i
]);
4117 adapter
->tx_ring
[i
] = NULL
;
4119 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4120 kfree(adapter
->rx_ring
[i
]);
4121 adapter
->rx_ring
[i
] = NULL
;
4124 ixgbe_free_q_vectors(adapter
);
4125 ixgbe_reset_interrupt_capability(adapter
);
4129 * ixgbe_sfp_timer - worker thread to find a missing module
4130 * @data: pointer to our adapter struct
4132 static void ixgbe_sfp_timer(unsigned long data
)
4134 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
4137 * Do the sfp_timer outside of interrupt context due to the
4138 * delays that sfp+ detection requires
4140 schedule_work(&adapter
->sfp_task
);
4144 * ixgbe_sfp_task - worker thread to find a missing module
4145 * @work: pointer to work_struct containing our data
4147 static void ixgbe_sfp_task(struct work_struct
*work
)
4149 struct ixgbe_adapter
*adapter
= container_of(work
,
4150 struct ixgbe_adapter
,
4152 struct ixgbe_hw
*hw
= &adapter
->hw
;
4154 if ((hw
->phy
.type
== ixgbe_phy_nl
) &&
4155 (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)) {
4156 s32 ret
= hw
->phy
.ops
.identify_sfp(hw
);
4157 if (ret
== IXGBE_ERR_SFP_NOT_PRESENT
)
4159 ret
= hw
->phy
.ops
.reset(hw
);
4160 if (ret
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
4161 dev_err(&adapter
->pdev
->dev
, "failed to initialize "
4162 "because an unsupported SFP+ module type "
4164 "Reload the driver after installing a "
4165 "supported module.\n");
4166 unregister_netdev(adapter
->netdev
);
4168 DPRINTK(PROBE
, INFO
, "detected SFP+: %d\n",
4171 /* don't need this routine any more */
4172 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
4176 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
))
4177 mod_timer(&adapter
->sfp_timer
,
4178 round_jiffies(jiffies
+ (2 * HZ
)));
4182 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4183 * @adapter: board private structure to initialize
4185 * ixgbe_sw_init initializes the Adapter private data structure.
4186 * Fields are initialized based on PCI device information and
4187 * OS network device settings (MTU size).
4189 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
4191 struct ixgbe_hw
*hw
= &adapter
->hw
;
4192 struct pci_dev
*pdev
= adapter
->pdev
;
4193 struct net_device
*dev
= adapter
->netdev
;
4195 #ifdef CONFIG_IXGBE_DCB
4197 struct tc_configuration
*tc
;
4200 /* PCI config space info */
4202 hw
->vendor_id
= pdev
->vendor
;
4203 hw
->device_id
= pdev
->device
;
4204 hw
->revision_id
= pdev
->revision
;
4205 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
4206 hw
->subsystem_device_id
= pdev
->subsystem_device
;
4208 /* Set capability flags */
4209 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
4210 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
4211 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
4212 adapter
->ring_feature
[RING_F_DCB
].indices
= IXGBE_MAX_DCB_INDICES
;
4213 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
4214 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
4215 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
4216 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
4217 } else if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4218 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
4219 adapter
->flags2
|= IXGBE_FLAG2_RSC_CAPABLE
;
4220 adapter
->flags2
|= IXGBE_FLAG2_RSC_ENABLED
;
4221 if (dev
->features
& NETIF_F_NTUPLE
) {
4222 /* Flow Director perfect filter enabled */
4223 adapter
->flags
|= IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4224 adapter
->atr_sample_rate
= 0;
4225 spin_lock_init(&adapter
->fdir_perfect_lock
);
4227 /* Flow Director hash filters enabled */
4228 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4229 adapter
->atr_sample_rate
= 20;
4231 adapter
->ring_feature
[RING_F_FDIR
].indices
=
4232 IXGBE_MAX_FDIR_INDICES
;
4233 adapter
->fdir_pballoc
= 0;
4235 adapter
->flags
|= IXGBE_FLAG_FCOE_CAPABLE
;
4236 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
4237 adapter
->ring_feature
[RING_F_FCOE
].indices
= 0;
4238 #ifdef CONFIG_IXGBE_DCB
4239 /* Default traffic class to use for FCoE */
4240 adapter
->fcoe
.tc
= IXGBE_FCOE_DEFTC
;
4242 #endif /* IXGBE_FCOE */
4245 #ifdef CONFIG_IXGBE_DCB
4246 /* Configure DCB traffic classes */
4247 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
4248 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
4249 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
4250 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4251 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
4252 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4253 tc
->dcb_pfc
= pfc_disabled
;
4255 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
4256 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
4257 adapter
->dcb_cfg
.rx_pba_cfg
= pba_equal
;
4258 adapter
->dcb_cfg
.pfc_mode_enable
= false;
4259 adapter
->dcb_cfg
.round_robin_enable
= false;
4260 adapter
->dcb_set_bitmap
= 0x00;
4261 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
4262 adapter
->ring_feature
[RING_F_DCB
].indices
);
4266 /* default flow control settings */
4267 hw
->fc
.requested_mode
= ixgbe_fc_full
;
4268 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
4270 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
4272 hw
->fc
.high_water
= IXGBE_DEFAULT_FCRTH
;
4273 hw
->fc
.low_water
= IXGBE_DEFAULT_FCRTL
;
4274 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
4275 hw
->fc
.send_xon
= true;
4276 hw
->fc
.disable_fc_autoneg
= false;
4278 /* enable itr by default in dynamic mode */
4279 adapter
->rx_itr_setting
= 1;
4280 adapter
->rx_eitr_param
= 20000;
4281 adapter
->tx_itr_setting
= 1;
4282 adapter
->tx_eitr_param
= 10000;
4284 /* set defaults for eitr in MegaBytes */
4285 adapter
->eitr_low
= 10;
4286 adapter
->eitr_high
= 20;
4288 /* set default ring sizes */
4289 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
4290 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
4292 /* initialize eeprom parameters */
4293 if (ixgbe_init_eeprom_params_generic(hw
)) {
4294 dev_err(&pdev
->dev
, "EEPROM initialization failed\n");
4298 /* enable rx csum by default */
4299 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
4301 /* get assigned NUMA node */
4302 adapter
->node
= dev_to_node(&pdev
->dev
);
4304 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4310 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4311 * @adapter: board private structure
4312 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4314 * Return 0 on success, negative on failure
4316 int ixgbe_setup_tx_resources(struct ixgbe_adapter
*adapter
,
4317 struct ixgbe_ring
*tx_ring
)
4319 struct pci_dev
*pdev
= adapter
->pdev
;
4322 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
4323 tx_ring
->tx_buffer_info
= vmalloc_node(size
, tx_ring
->numa_node
);
4324 if (!tx_ring
->tx_buffer_info
)
4325 tx_ring
->tx_buffer_info
= vmalloc(size
);
4326 if (!tx_ring
->tx_buffer_info
)
4328 memset(tx_ring
->tx_buffer_info
, 0, size
);
4330 /* round up to nearest 4K */
4331 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
4332 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
4334 tx_ring
->desc
= pci_alloc_consistent(pdev
, tx_ring
->size
,
4339 tx_ring
->next_to_use
= 0;
4340 tx_ring
->next_to_clean
= 0;
4341 tx_ring
->work_limit
= tx_ring
->count
;
4345 vfree(tx_ring
->tx_buffer_info
);
4346 tx_ring
->tx_buffer_info
= NULL
;
4347 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for the transmit "
4348 "descriptor ring\n");
4353 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4354 * @adapter: board private structure
4356 * If this function returns with an error, then it's possible one or
4357 * more of the rings is populated (while the rest are not). It is the
4358 * callers duty to clean those orphaned rings.
4360 * Return 0 on success, negative on failure
4362 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
4366 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4367 err
= ixgbe_setup_tx_resources(adapter
, adapter
->tx_ring
[i
]);
4370 DPRINTK(PROBE
, ERR
, "Allocation for Tx Queue %u failed\n", i
);
4378 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4379 * @adapter: board private structure
4380 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4382 * Returns 0 on success, negative on failure
4384 int ixgbe_setup_rx_resources(struct ixgbe_adapter
*adapter
,
4385 struct ixgbe_ring
*rx_ring
)
4387 struct pci_dev
*pdev
= adapter
->pdev
;
4390 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
4391 rx_ring
->rx_buffer_info
= vmalloc_node(size
, adapter
->node
);
4392 if (!rx_ring
->rx_buffer_info
)
4393 rx_ring
->rx_buffer_info
= vmalloc(size
);
4394 if (!rx_ring
->rx_buffer_info
) {
4396 "vmalloc allocation failed for the rx desc ring\n");
4399 memset(rx_ring
->rx_buffer_info
, 0, size
);
4401 /* Round up to nearest 4K */
4402 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
4403 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
4405 rx_ring
->desc
= pci_alloc_consistent(pdev
, rx_ring
->size
, &rx_ring
->dma
);
4407 if (!rx_ring
->desc
) {
4409 "Memory allocation failed for the rx desc ring\n");
4410 vfree(rx_ring
->rx_buffer_info
);
4414 rx_ring
->next_to_clean
= 0;
4415 rx_ring
->next_to_use
= 0;
4424 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4425 * @adapter: board private structure
4427 * If this function returns with an error, then it's possible one or
4428 * more of the rings is populated (while the rest are not). It is the
4429 * callers duty to clean those orphaned rings.
4431 * Return 0 on success, negative on failure
4434 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
4438 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4439 err
= ixgbe_setup_rx_resources(adapter
, adapter
->rx_ring
[i
]);
4442 DPRINTK(PROBE
, ERR
, "Allocation for Rx Queue %u failed\n", i
);
4450 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4451 * @adapter: board private structure
4452 * @tx_ring: Tx descriptor ring for a specific queue
4454 * Free all transmit software resources
4456 void ixgbe_free_tx_resources(struct ixgbe_adapter
*adapter
,
4457 struct ixgbe_ring
*tx_ring
)
4459 struct pci_dev
*pdev
= adapter
->pdev
;
4461 ixgbe_clean_tx_ring(adapter
, tx_ring
);
4463 vfree(tx_ring
->tx_buffer_info
);
4464 tx_ring
->tx_buffer_info
= NULL
;
4466 pci_free_consistent(pdev
, tx_ring
->size
, tx_ring
->desc
, tx_ring
->dma
);
4468 tx_ring
->desc
= NULL
;
4472 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4473 * @adapter: board private structure
4475 * Free all transmit software resources
4477 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
4481 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4482 if (adapter
->tx_ring
[i
]->desc
)
4483 ixgbe_free_tx_resources(adapter
, adapter
->tx_ring
[i
]);
4487 * ixgbe_free_rx_resources - Free Rx Resources
4488 * @adapter: board private structure
4489 * @rx_ring: ring to clean the resources from
4491 * Free all receive software resources
4493 void ixgbe_free_rx_resources(struct ixgbe_adapter
*adapter
,
4494 struct ixgbe_ring
*rx_ring
)
4496 struct pci_dev
*pdev
= adapter
->pdev
;
4498 ixgbe_clean_rx_ring(adapter
, rx_ring
);
4500 vfree(rx_ring
->rx_buffer_info
);
4501 rx_ring
->rx_buffer_info
= NULL
;
4503 pci_free_consistent(pdev
, rx_ring
->size
, rx_ring
->desc
, rx_ring
->dma
);
4505 rx_ring
->desc
= NULL
;
4509 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4510 * @adapter: board private structure
4512 * Free all receive software resources
4514 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
4518 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4519 if (adapter
->rx_ring
[i
]->desc
)
4520 ixgbe_free_rx_resources(adapter
, adapter
->rx_ring
[i
]);
4524 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4525 * @netdev: network interface device structure
4526 * @new_mtu: new value for maximum frame size
4528 * Returns 0 on success, negative on failure
4530 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
4532 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4533 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
4535 /* MTU < 68 is an error and causes problems on some kernels */
4536 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
4539 DPRINTK(PROBE
, INFO
, "changing MTU from %d to %d\n",
4540 netdev
->mtu
, new_mtu
);
4541 /* must set new MTU before calling down or up */
4542 netdev
->mtu
= new_mtu
;
4544 if (netif_running(netdev
))
4545 ixgbe_reinit_locked(adapter
);
4551 * ixgbe_open - Called when a network interface is made active
4552 * @netdev: network interface device structure
4554 * Returns 0 on success, negative value on failure
4556 * The open entry point is called when a network interface is made
4557 * active by the system (IFF_UP). At this point all resources needed
4558 * for transmit and receive operations are allocated, the interrupt
4559 * handler is registered with the OS, the watchdog timer is started,
4560 * and the stack is notified that the interface is ready.
4562 static int ixgbe_open(struct net_device
*netdev
)
4564 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4567 /* disallow open during test */
4568 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
4571 netif_carrier_off(netdev
);
4573 /* allocate transmit descriptors */
4574 err
= ixgbe_setup_all_tx_resources(adapter
);
4578 /* allocate receive descriptors */
4579 err
= ixgbe_setup_all_rx_resources(adapter
);
4583 ixgbe_configure(adapter
);
4585 err
= ixgbe_request_irq(adapter
);
4589 err
= ixgbe_up_complete(adapter
);
4593 netif_tx_start_all_queues(netdev
);
4598 ixgbe_release_hw_control(adapter
);
4599 ixgbe_free_irq(adapter
);
4602 ixgbe_free_all_rx_resources(adapter
);
4604 ixgbe_free_all_tx_resources(adapter
);
4605 ixgbe_reset(adapter
);
4611 * ixgbe_close - Disables a network interface
4612 * @netdev: network interface device structure
4614 * Returns 0, this is not allowed to fail
4616 * The close entry point is called when an interface is de-activated
4617 * by the OS. The hardware is still under the drivers control, but
4618 * needs to be disabled. A global MAC reset is issued to stop the
4619 * hardware, and all transmit and receive resources are freed.
4621 static int ixgbe_close(struct net_device
*netdev
)
4623 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4625 ixgbe_down(adapter
);
4626 ixgbe_free_irq(adapter
);
4628 ixgbe_free_all_tx_resources(adapter
);
4629 ixgbe_free_all_rx_resources(adapter
);
4631 ixgbe_release_hw_control(adapter
);
4637 static int ixgbe_resume(struct pci_dev
*pdev
)
4639 struct net_device
*netdev
= pci_get_drvdata(pdev
);
4640 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4643 pci_set_power_state(pdev
, PCI_D0
);
4644 pci_restore_state(pdev
);
4646 * pci_restore_state clears dev->state_saved so call
4647 * pci_save_state to restore it.
4649 pci_save_state(pdev
);
4651 err
= pci_enable_device_mem(pdev
);
4653 printk(KERN_ERR
"ixgbe: Cannot enable PCI device from "
4657 pci_set_master(pdev
);
4659 pci_wake_from_d3(pdev
, false);
4661 err
= ixgbe_init_interrupt_scheme(adapter
);
4663 printk(KERN_ERR
"ixgbe: Cannot initialize interrupts for "
4668 ixgbe_reset(adapter
);
4670 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
4672 if (netif_running(netdev
)) {
4673 err
= ixgbe_open(adapter
->netdev
);
4678 netif_device_attach(netdev
);
4682 #endif /* CONFIG_PM */
4684 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
4686 struct net_device
*netdev
= pci_get_drvdata(pdev
);
4687 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4688 struct ixgbe_hw
*hw
= &adapter
->hw
;
4690 u32 wufc
= adapter
->wol
;
4695 netif_device_detach(netdev
);
4697 if (netif_running(netdev
)) {
4698 ixgbe_down(adapter
);
4699 ixgbe_free_irq(adapter
);
4700 ixgbe_free_all_tx_resources(adapter
);
4701 ixgbe_free_all_rx_resources(adapter
);
4703 ixgbe_clear_interrupt_scheme(adapter
);
4706 retval
= pci_save_state(pdev
);
4712 ixgbe_set_rx_mode(netdev
);
4714 /* turn on all-multi mode if wake on multicast is enabled */
4715 if (wufc
& IXGBE_WUFC_MC
) {
4716 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
4717 fctrl
|= IXGBE_FCTRL_MPE
;
4718 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
4721 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
4722 ctrl
|= IXGBE_CTRL_GIO_DIS
;
4723 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
4725 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
4727 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
4728 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
4731 if (wufc
&& hw
->mac
.type
== ixgbe_mac_82599EB
)
4732 pci_wake_from_d3(pdev
, true);
4734 pci_wake_from_d3(pdev
, false);
4736 *enable_wake
= !!wufc
;
4738 ixgbe_release_hw_control(adapter
);
4740 pci_disable_device(pdev
);
4746 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4751 retval
= __ixgbe_shutdown(pdev
, &wake
);
4756 pci_prepare_to_sleep(pdev
);
4758 pci_wake_from_d3(pdev
, false);
4759 pci_set_power_state(pdev
, PCI_D3hot
);
4764 #endif /* CONFIG_PM */
4766 static void ixgbe_shutdown(struct pci_dev
*pdev
)
4770 __ixgbe_shutdown(pdev
, &wake
);
4772 if (system_state
== SYSTEM_POWER_OFF
) {
4773 pci_wake_from_d3(pdev
, wake
);
4774 pci_set_power_state(pdev
, PCI_D3hot
);
4779 * ixgbe_update_stats - Update the board statistics counters.
4780 * @adapter: board private structure
4782 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
4784 struct net_device
*netdev
= adapter
->netdev
;
4785 struct ixgbe_hw
*hw
= &adapter
->hw
;
4787 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
4788 u64 non_eop_descs
= 0, restart_queue
= 0;
4790 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
4793 for (i
= 0; i
< 16; i
++)
4794 adapter
->hw_rx_no_dma_resources
+=
4795 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
4796 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4797 rsc_count
+= adapter
->rx_ring
[i
]->rsc_count
;
4798 rsc_flush
+= adapter
->rx_ring
[i
]->rsc_flush
;
4800 adapter
->rsc_total_count
= rsc_count
;
4801 adapter
->rsc_total_flush
= rsc_flush
;
4804 /* gather some stats to the adapter struct that are per queue */
4805 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4806 restart_queue
+= adapter
->tx_ring
[i
]->restart_queue
;
4807 adapter
->restart_queue
= restart_queue
;
4809 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4810 non_eop_descs
+= adapter
->rx_ring
[i
]->non_eop_descs
;
4811 adapter
->non_eop_descs
= non_eop_descs
;
4813 adapter
->stats
.crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
4814 for (i
= 0; i
< 8; i
++) {
4815 /* for packet buffers not used, the register should read 0 */
4816 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
4818 adapter
->stats
.mpc
[i
] += mpc
;
4819 total_mpc
+= adapter
->stats
.mpc
[i
];
4820 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
4821 adapter
->stats
.rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
4822 adapter
->stats
.qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
4823 adapter
->stats
.qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
4824 adapter
->stats
.qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
4825 adapter
->stats
.qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
4826 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4827 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
4828 IXGBE_PXONRXCNT(i
));
4829 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
4830 IXGBE_PXOFFRXCNT(i
));
4831 adapter
->stats
.qprdc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
4833 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
4835 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
4838 adapter
->stats
.pxontxc
[i
] += IXGBE_READ_REG(hw
,
4840 adapter
->stats
.pxofftxc
[i
] += IXGBE_READ_REG(hw
,
4843 adapter
->stats
.gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
4844 /* work around hardware counting issue */
4845 adapter
->stats
.gprc
-= missed_rx
;
4847 /* 82598 hardware only has a 32 bit counter in the high register */
4848 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4850 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
4851 tmp
= IXGBE_READ_REG(hw
, IXGBE_GORCH
) & 0xF; /* 4 high bits of GORC */
4852 adapter
->stats
.gorc
+= (tmp
<< 32);
4853 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
4854 tmp
= IXGBE_READ_REG(hw
, IXGBE_GOTCH
) & 0xF; /* 4 high bits of GOTC */
4855 adapter
->stats
.gotc
+= (tmp
<< 32);
4856 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
4857 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
4858 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
4859 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
4860 adapter
->stats
.fdirmatch
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
4861 adapter
->stats
.fdirmiss
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
4863 adapter
->stats
.fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
4864 adapter
->stats
.fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
4865 adapter
->stats
.fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
4866 adapter
->stats
.fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
4867 adapter
->stats
.fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
4868 adapter
->stats
.fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
4869 #endif /* IXGBE_FCOE */
4871 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
4872 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
4873 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
4874 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
4875 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
4877 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
4878 adapter
->stats
.bprc
+= bprc
;
4879 adapter
->stats
.mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
4880 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
4881 adapter
->stats
.mprc
-= bprc
;
4882 adapter
->stats
.roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
4883 adapter
->stats
.prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
4884 adapter
->stats
.prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
4885 adapter
->stats
.prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
4886 adapter
->stats
.prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
4887 adapter
->stats
.prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
4888 adapter
->stats
.prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
4889 adapter
->stats
.rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
4890 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
4891 adapter
->stats
.lxontxc
+= lxon
;
4892 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
4893 adapter
->stats
.lxofftxc
+= lxoff
;
4894 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
4895 adapter
->stats
.gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
4896 adapter
->stats
.mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
4898 * 82598 errata - tx of flow control packets is included in tx counters
4900 xon_off_tot
= lxon
+ lxoff
;
4901 adapter
->stats
.gptc
-= xon_off_tot
;
4902 adapter
->stats
.mptc
-= xon_off_tot
;
4903 adapter
->stats
.gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
4904 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
4905 adapter
->stats
.rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
4906 adapter
->stats
.rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
4907 adapter
->stats
.tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
4908 adapter
->stats
.ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
4909 adapter
->stats
.ptc64
-= xon_off_tot
;
4910 adapter
->stats
.ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
4911 adapter
->stats
.ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
4912 adapter
->stats
.ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
4913 adapter
->stats
.ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
4914 adapter
->stats
.ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
4915 adapter
->stats
.bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
4917 /* Fill out the OS statistics structure */
4918 netdev
->stats
.multicast
= adapter
->stats
.mprc
;
4921 netdev
->stats
.rx_errors
= adapter
->stats
.crcerrs
+
4922 adapter
->stats
.rlec
;
4923 netdev
->stats
.rx_dropped
= 0;
4924 netdev
->stats
.rx_length_errors
= adapter
->stats
.rlec
;
4925 netdev
->stats
.rx_crc_errors
= adapter
->stats
.crcerrs
;
4926 netdev
->stats
.rx_missed_errors
= total_mpc
;
4930 * ixgbe_watchdog - Timer Call-back
4931 * @data: pointer to adapter cast into an unsigned long
4933 static void ixgbe_watchdog(unsigned long data
)
4935 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
4936 struct ixgbe_hw
*hw
= &adapter
->hw
;
4941 * Do the watchdog outside of interrupt context due to the lovely
4942 * delays that some of the newer hardware requires
4945 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
4946 goto watchdog_short_circuit
;
4948 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
4950 * for legacy and MSI interrupts don't set any bits
4951 * that are enabled for EIAM, because this operation
4952 * would set *both* EIMS and EICS for any bit in EIAM
4954 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
4955 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
4956 goto watchdog_reschedule
;
4959 /* get one bit for every active tx/rx interrupt vector */
4960 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++) {
4961 struct ixgbe_q_vector
*qv
= adapter
->q_vector
[i
];
4962 if (qv
->rxr_count
|| qv
->txr_count
)
4963 eics
|= ((u64
)1 << i
);
4966 /* Cause software interrupt to ensure rx rings are cleaned */
4967 ixgbe_irq_rearm_queues(adapter
, eics
);
4969 watchdog_reschedule
:
4970 /* Reset the timer */
4971 mod_timer(&adapter
->watchdog_timer
, round_jiffies(jiffies
+ 2 * HZ
));
4973 watchdog_short_circuit
:
4974 schedule_work(&adapter
->watchdog_task
);
4978 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4979 * @work: pointer to work_struct containing our data
4981 static void ixgbe_multispeed_fiber_task(struct work_struct
*work
)
4983 struct ixgbe_adapter
*adapter
= container_of(work
,
4984 struct ixgbe_adapter
,
4985 multispeed_fiber_task
);
4986 struct ixgbe_hw
*hw
= &adapter
->hw
;
4990 adapter
->flags
|= IXGBE_FLAG_IN_SFP_LINK_TASK
;
4991 autoneg
= hw
->phy
.autoneg_advertised
;
4992 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
4993 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
4994 if (hw
->mac
.ops
.setup_link
)
4995 hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, true);
4996 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
4997 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_LINK_TASK
;
5001 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5002 * @work: pointer to work_struct containing our data
5004 static void ixgbe_sfp_config_module_task(struct work_struct
*work
)
5006 struct ixgbe_adapter
*adapter
= container_of(work
,
5007 struct ixgbe_adapter
,
5008 sfp_config_module_task
);
5009 struct ixgbe_hw
*hw
= &adapter
->hw
;
5012 adapter
->flags
|= IXGBE_FLAG_IN_SFP_MOD_TASK
;
5014 /* Time for electrical oscillations to settle down */
5016 err
= hw
->phy
.ops
.identify_sfp(hw
);
5018 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
5019 dev_err(&adapter
->pdev
->dev
, "failed to initialize because "
5020 "an unsupported SFP+ module type was detected.\n"
5021 "Reload the driver after installing a supported "
5023 unregister_netdev(adapter
->netdev
);
5026 hw
->mac
.ops
.setup_sfp(hw
);
5028 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
5029 /* This will also work for DA Twinax connections */
5030 schedule_work(&adapter
->multispeed_fiber_task
);
5031 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_MOD_TASK
;
5035 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5036 * @work: pointer to work_struct containing our data
5038 static void ixgbe_fdir_reinit_task(struct work_struct
*work
)
5040 struct ixgbe_adapter
*adapter
= container_of(work
,
5041 struct ixgbe_adapter
,
5043 struct ixgbe_hw
*hw
= &adapter
->hw
;
5046 if (ixgbe_reinit_fdir_tables_82599(hw
) == 0) {
5047 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5048 set_bit(__IXGBE_FDIR_INIT_DONE
,
5049 &(adapter
->tx_ring
[i
]->reinit_state
));
5051 DPRINTK(PROBE
, ERR
, "failed to finish FDIR re-initialization, "
5052 "ignored adding FDIR ATR filters \n");
5054 /* Done FDIR Re-initialization, enable transmits */
5055 netif_tx_start_all_queues(adapter
->netdev
);
5058 static DEFINE_MUTEX(ixgbe_watchdog_lock
);
5061 * ixgbe_watchdog_task - worker thread to bring link up
5062 * @work: pointer to work_struct containing our data
5064 static void ixgbe_watchdog_task(struct work_struct
*work
)
5066 struct ixgbe_adapter
*adapter
= container_of(work
,
5067 struct ixgbe_adapter
,
5069 struct net_device
*netdev
= adapter
->netdev
;
5070 struct ixgbe_hw
*hw
= &adapter
->hw
;
5074 struct ixgbe_ring
*tx_ring
;
5075 int some_tx_pending
= 0;
5077 mutex_lock(&ixgbe_watchdog_lock
);
5079 link_up
= adapter
->link_up
;
5080 link_speed
= adapter
->link_speed
;
5082 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
) {
5083 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
5086 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5087 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
5088 hw
->mac
.ops
.fc_enable(hw
, i
);
5090 hw
->mac
.ops
.fc_enable(hw
, 0);
5093 hw
->mac
.ops
.fc_enable(hw
, 0);
5098 time_after(jiffies
, (adapter
->link_check_timeout
+
5099 IXGBE_TRY_LINK_TIMEOUT
))) {
5100 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
5101 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
5103 adapter
->link_up
= link_up
;
5104 adapter
->link_speed
= link_speed
;
5108 if (!netif_carrier_ok(netdev
)) {
5109 bool flow_rx
, flow_tx
;
5111 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5112 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
5113 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
5114 flow_rx
= !!(mflcn
& IXGBE_MFLCN_RFCE
);
5115 flow_tx
= !!(fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
5117 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5118 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
5119 flow_rx
= !!(frctl
& IXGBE_FCTRL_RFCE
);
5120 flow_tx
= !!(rmcs
& IXGBE_RMCS_TFCE_802_3X
);
5123 printk(KERN_INFO
"ixgbe: %s NIC Link is Up %s, "
5124 "Flow Control: %s\n",
5126 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
5128 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
5129 "1 Gbps" : "unknown speed")),
5130 ((flow_rx
&& flow_tx
) ? "RX/TX" :
5132 (flow_tx
? "TX" : "None"))));
5134 netif_carrier_on(netdev
);
5136 /* Force detection of hung controller */
5137 adapter
->detect_tx_hung
= true;
5140 adapter
->link_up
= false;
5141 adapter
->link_speed
= 0;
5142 if (netif_carrier_ok(netdev
)) {
5143 printk(KERN_INFO
"ixgbe: %s NIC Link is Down\n",
5145 netif_carrier_off(netdev
);
5149 if (!netif_carrier_ok(netdev
)) {
5150 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5151 tx_ring
= adapter
->tx_ring
[i
];
5152 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
5153 some_tx_pending
= 1;
5158 if (some_tx_pending
) {
5159 /* We've lost link, so the controller stops DMA,
5160 * but we've got queued Tx work that's never going
5161 * to get done, so reset controller to flush Tx.
5162 * (Do the reset outside of interrupt context).
5164 schedule_work(&adapter
->reset_task
);
5168 ixgbe_update_stats(adapter
);
5169 mutex_unlock(&ixgbe_watchdog_lock
);
5172 static int ixgbe_tso(struct ixgbe_adapter
*adapter
,
5173 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
5174 u32 tx_flags
, u8
*hdr_len
)
5176 struct ixgbe_adv_tx_context_desc
*context_desc
;
5179 struct ixgbe_tx_buffer
*tx_buffer_info
;
5180 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
;
5181 u32 mss_l4len_idx
, l4len
;
5183 if (skb_is_gso(skb
)) {
5184 if (skb_header_cloned(skb
)) {
5185 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
5189 l4len
= tcp_hdrlen(skb
);
5192 if (skb
->protocol
== htons(ETH_P_IP
)) {
5193 struct iphdr
*iph
= ip_hdr(skb
);
5196 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5200 } else if (skb_is_gso_v6(skb
)) {
5201 ipv6_hdr(skb
)->payload_len
= 0;
5202 tcp_hdr(skb
)->check
=
5203 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
5204 &ipv6_hdr(skb
)->daddr
,
5208 i
= tx_ring
->next_to_use
;
5210 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5211 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
5213 /* VLAN MACLEN IPLEN */
5214 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5216 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5217 vlan_macip_lens
|= ((skb_network_offset(skb
)) <<
5218 IXGBE_ADVTXD_MACLEN_SHIFT
);
5219 *hdr_len
+= skb_network_offset(skb
);
5221 (skb_transport_header(skb
) - skb_network_header(skb
));
5223 (skb_transport_header(skb
) - skb_network_header(skb
));
5224 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5225 context_desc
->seqnum_seed
= 0;
5227 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5228 type_tucmd_mlhl
= (IXGBE_TXD_CMD_DEXT
|
5229 IXGBE_ADVTXD_DTYP_CTXT
);
5231 if (skb
->protocol
== htons(ETH_P_IP
))
5232 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5233 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5234 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5238 (skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
);
5239 mss_l4len_idx
|= (l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
);
5240 /* use index 1 for TSO */
5241 mss_l4len_idx
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5242 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
5244 tx_buffer_info
->time_stamp
= jiffies
;
5245 tx_buffer_info
->next_to_watch
= i
;
5248 if (i
== tx_ring
->count
)
5250 tx_ring
->next_to_use
= i
;
5257 static bool ixgbe_tx_csum(struct ixgbe_adapter
*adapter
,
5258 struct ixgbe_ring
*tx_ring
,
5259 struct sk_buff
*skb
, u32 tx_flags
)
5261 struct ixgbe_adv_tx_context_desc
*context_desc
;
5263 struct ixgbe_tx_buffer
*tx_buffer_info
;
5264 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
= 0;
5266 if (skb
->ip_summed
== CHECKSUM_PARTIAL
||
5267 (tx_flags
& IXGBE_TX_FLAGS_VLAN
)) {
5268 i
= tx_ring
->next_to_use
;
5269 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5270 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
5272 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5274 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5275 vlan_macip_lens
|= (skb_network_offset(skb
) <<
5276 IXGBE_ADVTXD_MACLEN_SHIFT
);
5277 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5278 vlan_macip_lens
|= (skb_transport_header(skb
) -
5279 skb_network_header(skb
));
5281 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5282 context_desc
->seqnum_seed
= 0;
5284 type_tucmd_mlhl
|= (IXGBE_TXD_CMD_DEXT
|
5285 IXGBE_ADVTXD_DTYP_CTXT
);
5287 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5290 if (skb
->protocol
== cpu_to_be16(ETH_P_8021Q
)) {
5291 const struct vlan_ethhdr
*vhdr
=
5292 (const struct vlan_ethhdr
*)skb
->data
;
5294 protocol
= vhdr
->h_vlan_encapsulated_proto
;
5296 protocol
= skb
->protocol
;
5300 case cpu_to_be16(ETH_P_IP
):
5301 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5302 if (ip_hdr(skb
)->protocol
== IPPROTO_TCP
)
5304 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5305 else if (ip_hdr(skb
)->protocol
== IPPROTO_SCTP
)
5307 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5309 case cpu_to_be16(ETH_P_IPV6
):
5310 /* XXX what about other V6 headers?? */
5311 if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_TCP
)
5313 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5314 else if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_SCTP
)
5316 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5319 if (unlikely(net_ratelimit())) {
5320 DPRINTK(PROBE
, WARNING
,
5321 "partial checksum but proto=%x!\n",
5328 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5329 /* use index zero for tx checksum offload */
5330 context_desc
->mss_l4len_idx
= 0;
5332 tx_buffer_info
->time_stamp
= jiffies
;
5333 tx_buffer_info
->next_to_watch
= i
;
5336 if (i
== tx_ring
->count
)
5338 tx_ring
->next_to_use
= i
;
5346 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
5347 struct ixgbe_ring
*tx_ring
,
5348 struct sk_buff
*skb
, u32 tx_flags
,
5351 struct pci_dev
*pdev
= adapter
->pdev
;
5352 struct ixgbe_tx_buffer
*tx_buffer_info
;
5354 unsigned int total
= skb
->len
;
5355 unsigned int offset
= 0, size
, count
= 0, i
;
5356 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
5359 i
= tx_ring
->next_to_use
;
5361 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
5362 /* excluding fcoe_crc_eof for FCoE */
5363 total
-= sizeof(struct fcoe_crc_eof
);
5365 len
= min(skb_headlen(skb
), total
);
5367 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5368 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
5370 tx_buffer_info
->length
= size
;
5371 tx_buffer_info
->mapped_as_page
= false;
5372 tx_buffer_info
->dma
= pci_map_single(pdev
,
5374 size
, PCI_DMA_TODEVICE
);
5375 if (pci_dma_mapping_error(pdev
, tx_buffer_info
->dma
))
5377 tx_buffer_info
->time_stamp
= jiffies
;
5378 tx_buffer_info
->next_to_watch
= i
;
5387 if (i
== tx_ring
->count
)
5392 for (f
= 0; f
< nr_frags
; f
++) {
5393 struct skb_frag_struct
*frag
;
5395 frag
= &skb_shinfo(skb
)->frags
[f
];
5396 len
= min((unsigned int)frag
->size
, total
);
5397 offset
= frag
->page_offset
;
5401 if (i
== tx_ring
->count
)
5404 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5405 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
5407 tx_buffer_info
->length
= size
;
5408 tx_buffer_info
->dma
= pci_map_page(adapter
->pdev
,
5412 tx_buffer_info
->mapped_as_page
= true;
5413 if (pci_dma_mapping_error(pdev
, tx_buffer_info
->dma
))
5415 tx_buffer_info
->time_stamp
= jiffies
;
5416 tx_buffer_info
->next_to_watch
= i
;
5427 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
5428 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
5433 dev_err(&pdev
->dev
, "TX DMA map failed\n");
5435 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5436 tx_buffer_info
->dma
= 0;
5437 tx_buffer_info
->time_stamp
= 0;
5438 tx_buffer_info
->next_to_watch
= 0;
5442 /* clear timestamp and dma mappings for remaining portion of packet */
5445 i
+= tx_ring
->count
;
5447 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5448 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
5454 static void ixgbe_tx_queue(struct ixgbe_adapter
*adapter
,
5455 struct ixgbe_ring
*tx_ring
,
5456 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
5458 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
5459 struct ixgbe_tx_buffer
*tx_buffer_info
;
5460 u32 olinfo_status
= 0, cmd_type_len
= 0;
5462 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
5464 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
5466 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
5468 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5469 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
5471 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
5472 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
5474 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
5475 IXGBE_ADVTXD_POPTS_SHIFT
;
5477 /* use index 1 context for tso */
5478 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5479 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
5480 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
5481 IXGBE_ADVTXD_POPTS_SHIFT
;
5483 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
5484 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
5485 IXGBE_ADVTXD_POPTS_SHIFT
;
5487 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
5488 olinfo_status
|= IXGBE_ADVTXD_CC
;
5489 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5490 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
5491 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
5494 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
5496 i
= tx_ring
->next_to_use
;
5498 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5499 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
5500 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
5501 tx_desc
->read
.cmd_type_len
=
5502 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
5503 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
5505 if (i
== tx_ring
->count
)
5509 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
5512 * Force memory writes to complete before letting h/w
5513 * know there are new descriptors to fetch. (Only
5514 * applicable for weak-ordered memory model archs,
5519 tx_ring
->next_to_use
= i
;
5520 writel(i
, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
5523 static void ixgbe_atr(struct ixgbe_adapter
*adapter
, struct sk_buff
*skb
,
5524 int queue
, u32 tx_flags
)
5526 /* Right now, we support IPv4 only */
5527 struct ixgbe_atr_input atr_input
;
5529 struct iphdr
*iph
= ip_hdr(skb
);
5530 struct ethhdr
*eth
= (struct ethhdr
*)skb
->data
;
5531 u16 vlan_id
, src_port
, dst_port
, flex_bytes
;
5532 u32 src_ipv4_addr
, dst_ipv4_addr
;
5535 /* check if we're UDP or TCP */
5536 if (iph
->protocol
== IPPROTO_TCP
) {
5538 src_port
= th
->source
;
5539 dst_port
= th
->dest
;
5540 l4type
|= IXGBE_ATR_L4TYPE_TCP
;
5541 /* l4type IPv4 type is 0, no need to assign */
5543 /* Unsupported L4 header, just bail here */
5547 memset(&atr_input
, 0, sizeof(struct ixgbe_atr_input
));
5549 vlan_id
= (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
) >>
5550 IXGBE_TX_FLAGS_VLAN_SHIFT
;
5551 src_ipv4_addr
= iph
->saddr
;
5552 dst_ipv4_addr
= iph
->daddr
;
5553 flex_bytes
= eth
->h_proto
;
5555 ixgbe_atr_set_vlan_id_82599(&atr_input
, vlan_id
);
5556 ixgbe_atr_set_src_port_82599(&atr_input
, dst_port
);
5557 ixgbe_atr_set_dst_port_82599(&atr_input
, src_port
);
5558 ixgbe_atr_set_flex_byte_82599(&atr_input
, flex_bytes
);
5559 ixgbe_atr_set_l4type_82599(&atr_input
, l4type
);
5560 /* src and dst are inverted, think how the receiver sees them */
5561 ixgbe_atr_set_src_ipv4_82599(&atr_input
, dst_ipv4_addr
);
5562 ixgbe_atr_set_dst_ipv4_82599(&atr_input
, src_ipv4_addr
);
5564 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5565 ixgbe_fdir_add_signature_filter_82599(&adapter
->hw
, &atr_input
, queue
);
5568 static int __ixgbe_maybe_stop_tx(struct net_device
*netdev
,
5569 struct ixgbe_ring
*tx_ring
, int size
)
5571 netif_stop_subqueue(netdev
, tx_ring
->queue_index
);
5572 /* Herbert's original patch had:
5573 * smp_mb__after_netif_stop_queue();
5574 * but since that doesn't exist yet, just open code it. */
5577 /* We need to check again in a case another CPU has just
5578 * made room available. */
5579 if (likely(IXGBE_DESC_UNUSED(tx_ring
) < size
))
5582 /* A reprieve! - use start_queue because it doesn't call schedule */
5583 netif_start_subqueue(netdev
, tx_ring
->queue_index
);
5584 ++tx_ring
->restart_queue
;
5588 static int ixgbe_maybe_stop_tx(struct net_device
*netdev
,
5589 struct ixgbe_ring
*tx_ring
, int size
)
5591 if (likely(IXGBE_DESC_UNUSED(tx_ring
) >= size
))
5593 return __ixgbe_maybe_stop_tx(netdev
, tx_ring
, size
);
5596 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
5598 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
5599 int txq
= smp_processor_id();
5601 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
5602 while (unlikely(txq
>= dev
->real_num_tx_queues
))
5603 txq
-= dev
->real_num_tx_queues
;
5608 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
5609 (skb
->protocol
== htons(ETH_P_FCOE
))) {
5610 txq
&= (adapter
->ring_feature
[RING_F_FCOE
].indices
- 1);
5611 txq
+= adapter
->ring_feature
[RING_F_FCOE
].mask
;
5615 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
5616 return (skb
->vlan_tci
& IXGBE_TX_FLAGS_VLAN_PRIO_MASK
) >> 13;
5618 return skb_tx_hash(dev
, skb
);
5621 static netdev_tx_t
ixgbe_xmit_frame(struct sk_buff
*skb
,
5622 struct net_device
*netdev
)
5624 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5625 struct ixgbe_ring
*tx_ring
;
5626 struct netdev_queue
*txq
;
5628 unsigned int tx_flags
= 0;
5634 if (adapter
->vlgrp
&& vlan_tx_tag_present(skb
)) {
5635 tx_flags
|= vlan_tx_tag_get(skb
);
5636 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5637 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
5638 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
5640 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
5641 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
5642 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5643 if (skb
->priority
!= TC_PRIO_CONTROL
) {
5644 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
5645 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
5646 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
5648 skb
->queue_mapping
=
5649 adapter
->ring_feature
[RING_F_DCB
].indices
-1;
5653 tx_ring
= adapter
->tx_ring
[skb
->queue_mapping
];
5655 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
5656 (skb
->protocol
== htons(ETH_P_FCOE
))) {
5657 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
5659 #ifdef CONFIG_IXGBE_DCB
5660 tx_flags
&= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5661 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
5662 tx_flags
|= ((adapter
->fcoe
.up
<< 13)
5663 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
5667 /* four things can cause us to need a context descriptor */
5668 if (skb_is_gso(skb
) ||
5669 (skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
5670 (tx_flags
& IXGBE_TX_FLAGS_VLAN
) ||
5671 (tx_flags
& IXGBE_TX_FLAGS_FCOE
))
5674 count
+= TXD_USE_COUNT(skb_headlen(skb
));
5675 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
5676 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
5678 if (ixgbe_maybe_stop_tx(netdev
, tx_ring
, count
)) {
5680 return NETDEV_TX_BUSY
;
5683 first
= tx_ring
->next_to_use
;
5684 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
5686 /* setup tx offload for FCoE */
5687 tso
= ixgbe_fso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
5689 dev_kfree_skb_any(skb
);
5690 return NETDEV_TX_OK
;
5693 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
5694 #endif /* IXGBE_FCOE */
5696 if (skb
->protocol
== htons(ETH_P_IP
))
5697 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
5698 tso
= ixgbe_tso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
5700 dev_kfree_skb_any(skb
);
5701 return NETDEV_TX_OK
;
5705 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
5706 else if (ixgbe_tx_csum(adapter
, tx_ring
, skb
, tx_flags
) &&
5707 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
5708 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
5711 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
);
5713 /* add the ATR filter if ATR is on */
5714 if (tx_ring
->atr_sample_rate
) {
5715 ++tx_ring
->atr_count
;
5716 if ((tx_ring
->atr_count
>= tx_ring
->atr_sample_rate
) &&
5717 test_bit(__IXGBE_FDIR_INIT_DONE
,
5718 &tx_ring
->reinit_state
)) {
5719 ixgbe_atr(adapter
, skb
, tx_ring
->queue_index
,
5721 tx_ring
->atr_count
= 0;
5724 txq
= netdev_get_tx_queue(netdev
, tx_ring
->queue_index
);
5725 txq
->tx_bytes
+= skb
->len
;
5727 ixgbe_tx_queue(adapter
, tx_ring
, tx_flags
, count
, skb
->len
,
5729 ixgbe_maybe_stop_tx(netdev
, tx_ring
, DESC_NEEDED
);
5732 dev_kfree_skb_any(skb
);
5733 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
5734 tx_ring
->next_to_use
= first
;
5737 return NETDEV_TX_OK
;
5741 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5742 * @netdev: network interface device structure
5743 * @p: pointer to an address structure
5745 * Returns 0 on success, negative on failure
5747 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
5749 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5750 struct ixgbe_hw
*hw
= &adapter
->hw
;
5751 struct sockaddr
*addr
= p
;
5753 if (!is_valid_ether_addr(addr
->sa_data
))
5754 return -EADDRNOTAVAIL
;
5756 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
5757 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
5759 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
5766 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
5768 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5769 struct ixgbe_hw
*hw
= &adapter
->hw
;
5773 if (prtad
!= hw
->phy
.mdio
.prtad
)
5775 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
5781 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
5782 u16 addr
, u16 value
)
5784 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5785 struct ixgbe_hw
*hw
= &adapter
->hw
;
5787 if (prtad
!= hw
->phy
.mdio
.prtad
)
5789 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
5792 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
5794 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5796 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
5800 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5802 * @netdev: network interface device structure
5804 * Returns non-zero on failure
5806 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
5809 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
5810 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
5812 if (is_valid_ether_addr(mac
->san_addr
)) {
5814 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
5821 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5823 * @netdev: network interface device structure
5825 * Returns non-zero on failure
5827 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
5830 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
5831 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
5833 if (is_valid_ether_addr(mac
->san_addr
)) {
5835 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
5841 #ifdef CONFIG_NET_POLL_CONTROLLER
5843 * Polling 'interrupt' - used by things like netconsole to send skbs
5844 * without having to re-enable interrupts. It's not called while
5845 * the interrupt routine is executing.
5847 static void ixgbe_netpoll(struct net_device
*netdev
)
5849 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5852 /* if interface is down do nothing */
5853 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
5856 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
5857 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
5858 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
5859 for (i
= 0; i
< num_q_vectors
; i
++) {
5860 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
5861 ixgbe_msix_clean_many(0, q_vector
);
5864 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
5866 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
5870 static const struct net_device_ops ixgbe_netdev_ops
= {
5871 .ndo_open
= ixgbe_open
,
5872 .ndo_stop
= ixgbe_close
,
5873 .ndo_start_xmit
= ixgbe_xmit_frame
,
5874 .ndo_select_queue
= ixgbe_select_queue
,
5875 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
5876 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
5877 .ndo_validate_addr
= eth_validate_addr
,
5878 .ndo_set_mac_address
= ixgbe_set_mac
,
5879 .ndo_change_mtu
= ixgbe_change_mtu
,
5880 .ndo_tx_timeout
= ixgbe_tx_timeout
,
5881 .ndo_vlan_rx_register
= ixgbe_vlan_rx_register
,
5882 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
5883 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
5884 .ndo_do_ioctl
= ixgbe_ioctl
,
5885 #ifdef CONFIG_NET_POLL_CONTROLLER
5886 .ndo_poll_controller
= ixgbe_netpoll
,
5889 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
5890 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
5891 .ndo_fcoe_enable
= ixgbe_fcoe_enable
,
5892 .ndo_fcoe_disable
= ixgbe_fcoe_disable
,
5893 .ndo_fcoe_get_wwn
= ixgbe_fcoe_get_wwn
,
5894 #endif /* IXGBE_FCOE */
5897 static void __devinit
ixgbe_probe_vf(struct ixgbe_adapter
*adapter
,
5898 const struct ixgbe_info
*ii
)
5900 #ifdef CONFIG_PCI_IOV
5901 struct ixgbe_hw
*hw
= &adapter
->hw
;
5904 if (hw
->mac
.type
!= ixgbe_mac_82599EB
|| !max_vfs
)
5907 /* The 82599 supports up to 64 VFs per physical function
5908 * but this implementation limits allocation to 63 so that
5909 * basic networking resources are still available to the
5912 adapter
->num_vfs
= (max_vfs
> 63) ? 63 : max_vfs
;
5913 adapter
->flags
|= IXGBE_FLAG_SRIOV_ENABLED
;
5914 err
= pci_enable_sriov(adapter
->pdev
, adapter
->num_vfs
);
5917 "Failed to enable PCI sriov: %d\n", err
);
5920 /* If call to enable VFs succeeded then allocate memory
5921 * for per VF control structures.
5924 kcalloc(adapter
->num_vfs
,
5925 sizeof(struct vf_data_storage
), GFP_KERNEL
);
5926 if (adapter
->vfinfo
) {
5927 /* Now that we're sure SR-IOV is enabled
5928 * and memory allocated set up the mailbox parameters
5930 ixgbe_init_mbx_params_pf(hw
);
5931 memcpy(&hw
->mbx
.ops
, ii
->mbx_ops
,
5932 sizeof(hw
->mbx
.ops
));
5934 /* Disable RSC when in SR-IOV mode */
5935 adapter
->flags2
&= ~(IXGBE_FLAG2_RSC_CAPABLE
|
5936 IXGBE_FLAG2_RSC_ENABLED
);
5942 "Unable to allocate memory for VF "
5943 "Data Storage - SRIOV disabled\n");
5944 pci_disable_sriov(adapter
->pdev
);
5947 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
5948 adapter
->num_vfs
= 0;
5949 #endif /* CONFIG_PCI_IOV */
5953 * ixgbe_probe - Device Initialization Routine
5954 * @pdev: PCI device information struct
5955 * @ent: entry in ixgbe_pci_tbl
5957 * Returns 0 on success, negative on failure
5959 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5960 * The OS initialization, configuring of the adapter private structure,
5961 * and a hardware reset occur.
5963 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
5964 const struct pci_device_id
*ent
)
5966 struct net_device
*netdev
;
5967 struct ixgbe_adapter
*adapter
= NULL
;
5968 struct ixgbe_hw
*hw
;
5969 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
5970 static int cards_found
;
5971 int i
, err
, pci_using_dac
;
5977 err
= pci_enable_device_mem(pdev
);
5981 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) &&
5982 !pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64))) {
5985 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
5987 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
5989 dev_err(&pdev
->dev
, "No usable DMA "
5990 "configuration, aborting\n");
5997 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
5998 IORESOURCE_MEM
), ixgbe_driver_name
);
6001 "pci_request_selected_regions failed 0x%x\n", err
);
6005 pci_enable_pcie_error_reporting(pdev
);
6007 pci_set_master(pdev
);
6008 pci_save_state(pdev
);
6010 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), MAX_TX_QUEUES
);
6013 goto err_alloc_etherdev
;
6016 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
6018 pci_set_drvdata(pdev
, netdev
);
6019 adapter
= netdev_priv(netdev
);
6021 adapter
->netdev
= netdev
;
6022 adapter
->pdev
= pdev
;
6025 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
6027 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
6028 pci_resource_len(pdev
, 0));
6034 for (i
= 1; i
<= 5; i
++) {
6035 if (pci_resource_len(pdev
, i
) == 0)
6039 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
6040 ixgbe_set_ethtool_ops(netdev
);
6041 netdev
->watchdog_timeo
= 5 * HZ
;
6042 strcpy(netdev
->name
, pci_name(pdev
));
6044 adapter
->bd_number
= cards_found
;
6047 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
6048 hw
->mac
.type
= ii
->mac
;
6051 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
6052 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
6053 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6054 if (!(eec
& (1 << 8)))
6055 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
6058 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
6059 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
6060 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6061 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
6062 hw
->phy
.mdio
.mmds
= 0;
6063 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
6064 hw
->phy
.mdio
.dev
= netdev
;
6065 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
6066 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
6068 /* set up this timer and work struct before calling get_invariants
6069 * which might start the timer
6071 init_timer(&adapter
->sfp_timer
);
6072 adapter
->sfp_timer
.function
= &ixgbe_sfp_timer
;
6073 adapter
->sfp_timer
.data
= (unsigned long) adapter
;
6075 INIT_WORK(&adapter
->sfp_task
, ixgbe_sfp_task
);
6077 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6078 INIT_WORK(&adapter
->multispeed_fiber_task
, ixgbe_multispeed_fiber_task
);
6080 /* a new SFP+ module arrival, called from GPI SDP2 context */
6081 INIT_WORK(&adapter
->sfp_config_module_task
,
6082 ixgbe_sfp_config_module_task
);
6084 ii
->get_invariants(hw
);
6086 /* setup the private structure */
6087 err
= ixgbe_sw_init(adapter
);
6091 /* Make it possible the adapter to be woken up via WOL */
6092 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
6093 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
6096 * If there is a fan on this device and it has failed log the
6099 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
6100 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
6101 if (esdp
& IXGBE_ESDP_SDP1
)
6102 DPRINTK(PROBE
, CRIT
,
6103 "Fan has stopped, replace the adapter\n");
6106 /* reset_hw fills in the perm_addr as well */
6107 err
= hw
->mac
.ops
.reset_hw(hw
);
6108 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
6109 hw
->mac
.type
== ixgbe_mac_82598EB
) {
6111 * Start a kernel thread to watch for a module to arrive.
6112 * Only do this for 82598, since 82599 will generate
6113 * interrupts on module arrival.
6115 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6116 mod_timer(&adapter
->sfp_timer
,
6117 round_jiffies(jiffies
+ (2 * HZ
)));
6119 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
6120 dev_err(&adapter
->pdev
->dev
, "failed to initialize because "
6121 "an unsupported SFP+ module type was detected.\n"
6122 "Reload the driver after installing a supported "
6126 dev_err(&adapter
->pdev
->dev
, "HW Init failed: %d\n", err
);
6130 ixgbe_probe_vf(adapter
, ii
);
6132 netdev
->features
= NETIF_F_SG
|
6134 NETIF_F_HW_VLAN_TX
|
6135 NETIF_F_HW_VLAN_RX
|
6136 NETIF_F_HW_VLAN_FILTER
;
6138 netdev
->features
|= NETIF_F_IPV6_CSUM
;
6139 netdev
->features
|= NETIF_F_TSO
;
6140 netdev
->features
|= NETIF_F_TSO6
;
6141 netdev
->features
|= NETIF_F_GRO
;
6143 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
6144 netdev
->features
|= NETIF_F_SCTP_CSUM
;
6146 netdev
->vlan_features
|= NETIF_F_TSO
;
6147 netdev
->vlan_features
|= NETIF_F_TSO6
;
6148 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
6149 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
6150 netdev
->vlan_features
|= NETIF_F_SG
;
6152 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6153 adapter
->flags
&= ~(IXGBE_FLAG_RSS_ENABLED
|
6154 IXGBE_FLAG_DCB_ENABLED
);
6155 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
6156 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
6158 #ifdef CONFIG_IXGBE_DCB
6159 netdev
->dcbnl_ops
= &dcbnl_ops
;
6163 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
6164 if (hw
->mac
.ops
.get_device_caps
) {
6165 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
6166 if (device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)
6167 adapter
->flags
&= ~IXGBE_FLAG_FCOE_CAPABLE
;
6170 #endif /* IXGBE_FCOE */
6172 netdev
->features
|= NETIF_F_HIGHDMA
;
6174 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
6175 netdev
->features
|= NETIF_F_LRO
;
6177 /* make sure the EEPROM is good */
6178 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
6179 dev_err(&pdev
->dev
, "The EEPROM Checksum Is Not Valid\n");
6184 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
6185 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
6187 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
6188 dev_err(&pdev
->dev
, "invalid MAC address\n");
6193 init_timer(&adapter
->watchdog_timer
);
6194 adapter
->watchdog_timer
.function
= &ixgbe_watchdog
;
6195 adapter
->watchdog_timer
.data
= (unsigned long)adapter
;
6197 INIT_WORK(&adapter
->reset_task
, ixgbe_reset_task
);
6198 INIT_WORK(&adapter
->watchdog_task
, ixgbe_watchdog_task
);
6200 err
= ixgbe_init_interrupt_scheme(adapter
);
6204 switch (pdev
->device
) {
6205 case IXGBE_DEV_ID_82599_KX4
:
6206 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
6207 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
6208 /* Enable ACPI wakeup in GRC */
6209 IXGBE_WRITE_REG(hw
, IXGBE_GRC
,
6210 (IXGBE_READ_REG(hw
, IXGBE_GRC
) & ~IXGBE_GRC_APME
));
6216 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
6218 /* pick up the PCI bus settings for reporting later */
6219 hw
->mac
.ops
.get_bus_info(hw
);
6221 /* print bus type/speed/width info */
6222 dev_info(&pdev
->dev
, "(PCI Express:%s:%s) %pM\n",
6223 ((hw
->bus
.speed
== ixgbe_bus_speed_5000
) ? "5.0Gb/s":
6224 (hw
->bus
.speed
== ixgbe_bus_speed_2500
) ? "2.5Gb/s":"Unknown"),
6225 ((hw
->bus
.width
== ixgbe_bus_width_pcie_x8
) ? "Width x8" :
6226 (hw
->bus
.width
== ixgbe_bus_width_pcie_x4
) ? "Width x4" :
6227 (hw
->bus
.width
== ixgbe_bus_width_pcie_x1
) ? "Width x1" :
6230 ixgbe_read_pba_num_generic(hw
, &part_num
);
6231 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
6232 dev_info(&pdev
->dev
, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6233 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
6234 (part_num
>> 8), (part_num
& 0xff));
6236 dev_info(&pdev
->dev
, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6237 hw
->mac
.type
, hw
->phy
.type
,
6238 (part_num
>> 8), (part_num
& 0xff));
6240 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
6241 dev_warn(&pdev
->dev
, "PCI-Express bandwidth available for "
6242 "this card is not sufficient for optimal "
6244 dev_warn(&pdev
->dev
, "For optimal performance a x8 "
6245 "PCI-Express slot is required.\n");
6248 /* save off EEPROM version number */
6249 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
6251 /* reset the hardware with the new settings */
6252 err
= hw
->mac
.ops
.start_hw(hw
);
6254 if (err
== IXGBE_ERR_EEPROM_VERSION
) {
6255 /* We are running on a pre-production device, log a warning */
6256 dev_warn(&pdev
->dev
, "This device is a pre-production "
6257 "adapter/LOM. Please be aware there may be issues "
6258 "associated with your hardware. If you are "
6259 "experiencing problems please contact your Intel or "
6260 "hardware representative who provided you with this "
6263 strcpy(netdev
->name
, "eth%d");
6264 err
= register_netdev(netdev
);
6268 /* carrier off reporting is important to ethtool even BEFORE open */
6269 netif_carrier_off(netdev
);
6271 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
6272 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
6273 INIT_WORK(&adapter
->fdir_reinit_task
, ixgbe_fdir_reinit_task
);
6275 #ifdef CONFIG_IXGBE_DCA
6276 if (dca_add_requester(&pdev
->dev
) == 0) {
6277 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
6278 ixgbe_setup_dca(adapter
);
6281 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
6282 DPRINTK(PROBE
, INFO
, "IOV is enabled with %d VFs\n",
6284 for (i
= 0; i
< adapter
->num_vfs
; i
++)
6285 ixgbe_vf_configuration(pdev
, (i
| 0x10000000));
6288 /* add san mac addr to netdev */
6289 ixgbe_add_sanmac_netdev(netdev
);
6291 dev_info(&pdev
->dev
, "Intel(R) 10 Gigabit Network Connection\n");
6296 ixgbe_release_hw_control(adapter
);
6297 ixgbe_clear_interrupt_scheme(adapter
);
6300 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6301 ixgbe_disable_sriov(adapter
);
6302 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6303 del_timer_sync(&adapter
->sfp_timer
);
6304 cancel_work_sync(&adapter
->sfp_task
);
6305 cancel_work_sync(&adapter
->multispeed_fiber_task
);
6306 cancel_work_sync(&adapter
->sfp_config_module_task
);
6307 iounmap(hw
->hw_addr
);
6309 free_netdev(netdev
);
6311 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
6315 pci_disable_device(pdev
);
6320 * ixgbe_remove - Device Removal Routine
6321 * @pdev: PCI device information struct
6323 * ixgbe_remove is called by the PCI subsystem to alert the driver
6324 * that it should release a PCI device. The could be caused by a
6325 * Hot-Plug event, or because the driver is going to be removed from
6328 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
6330 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6331 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6333 set_bit(__IXGBE_DOWN
, &adapter
->state
);
6334 /* clear the module not found bit to make sure the worker won't
6337 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6338 del_timer_sync(&adapter
->watchdog_timer
);
6340 del_timer_sync(&adapter
->sfp_timer
);
6341 cancel_work_sync(&adapter
->watchdog_task
);
6342 cancel_work_sync(&adapter
->sfp_task
);
6343 cancel_work_sync(&adapter
->multispeed_fiber_task
);
6344 cancel_work_sync(&adapter
->sfp_config_module_task
);
6345 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
6346 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
6347 cancel_work_sync(&adapter
->fdir_reinit_task
);
6348 flush_scheduled_work();
6350 #ifdef CONFIG_IXGBE_DCA
6351 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
6352 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
6353 dca_remove_requester(&pdev
->dev
);
6354 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
6359 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
6360 ixgbe_cleanup_fcoe(adapter
);
6362 #endif /* IXGBE_FCOE */
6364 /* remove the added san mac */
6365 ixgbe_del_sanmac_netdev(netdev
);
6367 if (netdev
->reg_state
== NETREG_REGISTERED
)
6368 unregister_netdev(netdev
);
6370 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6371 ixgbe_disable_sriov(adapter
);
6373 ixgbe_clear_interrupt_scheme(adapter
);
6375 ixgbe_release_hw_control(adapter
);
6377 iounmap(adapter
->hw
.hw_addr
);
6378 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
6381 DPRINTK(PROBE
, INFO
, "complete\n");
6383 free_netdev(netdev
);
6385 pci_disable_pcie_error_reporting(pdev
);
6387 pci_disable_device(pdev
);
6391 * ixgbe_io_error_detected - called when PCI error is detected
6392 * @pdev: Pointer to PCI device
6393 * @state: The current pci connection state
6395 * This function is called after a PCI bus error affecting
6396 * this device has been detected.
6398 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
6399 pci_channel_state_t state
)
6401 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6402 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6404 netif_device_detach(netdev
);
6406 if (state
== pci_channel_io_perm_failure
)
6407 return PCI_ERS_RESULT_DISCONNECT
;
6409 if (netif_running(netdev
))
6410 ixgbe_down(adapter
);
6411 pci_disable_device(pdev
);
6413 /* Request a slot reset. */
6414 return PCI_ERS_RESULT_NEED_RESET
;
6418 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6419 * @pdev: Pointer to PCI device
6421 * Restart the card from scratch, as if from a cold-boot.
6423 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
6425 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6426 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6427 pci_ers_result_t result
;
6430 if (pci_enable_device_mem(pdev
)) {
6432 "Cannot re-enable PCI device after reset.\n");
6433 result
= PCI_ERS_RESULT_DISCONNECT
;
6435 pci_set_master(pdev
);
6436 pci_restore_state(pdev
);
6437 pci_save_state(pdev
);
6439 pci_wake_from_d3(pdev
, false);
6441 ixgbe_reset(adapter
);
6442 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
6443 result
= PCI_ERS_RESULT_RECOVERED
;
6446 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
6449 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err
);
6450 /* non-fatal, continue */
6457 * ixgbe_io_resume - called when traffic can start flowing again.
6458 * @pdev: Pointer to PCI device
6460 * This callback is called when the error recovery driver tells us that
6461 * its OK to resume normal operation.
6463 static void ixgbe_io_resume(struct pci_dev
*pdev
)
6465 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6466 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6468 if (netif_running(netdev
)) {
6469 if (ixgbe_up(adapter
)) {
6470 DPRINTK(PROBE
, INFO
, "ixgbe_up failed after reset\n");
6475 netif_device_attach(netdev
);
6478 static struct pci_error_handlers ixgbe_err_handler
= {
6479 .error_detected
= ixgbe_io_error_detected
,
6480 .slot_reset
= ixgbe_io_slot_reset
,
6481 .resume
= ixgbe_io_resume
,
6484 static struct pci_driver ixgbe_driver
= {
6485 .name
= ixgbe_driver_name
,
6486 .id_table
= ixgbe_pci_tbl
,
6487 .probe
= ixgbe_probe
,
6488 .remove
= __devexit_p(ixgbe_remove
),
6490 .suspend
= ixgbe_suspend
,
6491 .resume
= ixgbe_resume
,
6493 .shutdown
= ixgbe_shutdown
,
6494 .err_handler
= &ixgbe_err_handler
6498 * ixgbe_init_module - Driver Registration Routine
6500 * ixgbe_init_module is the first routine called when the driver is
6501 * loaded. All it does is register with the PCI subsystem.
6503 static int __init
ixgbe_init_module(void)
6506 printk(KERN_INFO
"%s: %s - version %s\n", ixgbe_driver_name
,
6507 ixgbe_driver_string
, ixgbe_driver_version
);
6509 printk(KERN_INFO
"%s: %s\n", ixgbe_driver_name
, ixgbe_copyright
);
6511 #ifdef CONFIG_IXGBE_DCA
6512 dca_register_notify(&dca_notifier
);
6515 ret
= pci_register_driver(&ixgbe_driver
);
6519 module_init(ixgbe_init_module
);
6522 * ixgbe_exit_module - Driver Exit Cleanup Routine
6524 * ixgbe_exit_module is called just before the driver is removed
6527 static void __exit
ixgbe_exit_module(void)
6529 #ifdef CONFIG_IXGBE_DCA
6530 dca_unregister_notify(&dca_notifier
);
6532 pci_unregister_driver(&ixgbe_driver
);
6535 #ifdef CONFIG_IXGBE_DCA
6536 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
6541 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
6542 __ixgbe_notify_dca
);
6544 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
6547 #endif /* CONFIG_IXGBE_DCA */
6550 * ixgbe_get_hw_dev_name - return device name string
6551 * used by hardware layer to print debugging information
6553 char *ixgbe_get_hw_dev_name(struct ixgbe_hw
*hw
)
6555 struct ixgbe_adapter
*adapter
= hw
->back
;
6556 return adapter
->netdev
->name
;
6560 module_exit(ixgbe_exit_module
);