Merge branch 'fixes' of git://git.armlinux.org.uk/~rmk/linux-arm
[deliverable/linux.git] / drivers / net / usb / r8152.c
1 /*
2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28 #include <linux/suspend.h>
29 #include <linux/acpi.h>
30
31 /* Information for net-next */
32 #define NETNEXT_VERSION "08"
33
34 /* Information for net */
35 #define NET_VERSION "6"
36
37 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
38 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40 #define MODULENAME "r8152"
41
42 #define R8152_PHY_ID 32
43
44 #define PLA_IDR 0xc000
45 #define PLA_RCR 0xc010
46 #define PLA_RMS 0xc016
47 #define PLA_RXFIFO_CTRL0 0xc0a0
48 #define PLA_RXFIFO_CTRL1 0xc0a4
49 #define PLA_RXFIFO_CTRL2 0xc0a8
50 #define PLA_DMY_REG0 0xc0b0
51 #define PLA_FMC 0xc0b4
52 #define PLA_CFG_WOL 0xc0b6
53 #define PLA_TEREDO_CFG 0xc0bc
54 #define PLA_MAR 0xcd00
55 #define PLA_BACKUP 0xd000
56 #define PAL_BDC_CR 0xd1a0
57 #define PLA_TEREDO_TIMER 0xd2cc
58 #define PLA_REALWOW_TIMER 0xd2e8
59 #define PLA_LEDSEL 0xdd90
60 #define PLA_LED_FEATURE 0xdd92
61 #define PLA_PHYAR 0xde00
62 #define PLA_BOOT_CTRL 0xe004
63 #define PLA_GPHY_INTR_IMR 0xe022
64 #define PLA_EEE_CR 0xe040
65 #define PLA_EEEP_CR 0xe080
66 #define PLA_MAC_PWR_CTRL 0xe0c0
67 #define PLA_MAC_PWR_CTRL2 0xe0ca
68 #define PLA_MAC_PWR_CTRL3 0xe0cc
69 #define PLA_MAC_PWR_CTRL4 0xe0ce
70 #define PLA_WDT6_CTRL 0xe428
71 #define PLA_TCR0 0xe610
72 #define PLA_TCR1 0xe612
73 #define PLA_MTPS 0xe615
74 #define PLA_TXFIFO_CTRL 0xe618
75 #define PLA_RSTTALLY 0xe800
76 #define PLA_CR 0xe813
77 #define PLA_CRWECR 0xe81c
78 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
79 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
80 #define PLA_CONFIG5 0xe822
81 #define PLA_PHY_PWR 0xe84c
82 #define PLA_OOB_CTRL 0xe84f
83 #define PLA_CPCR 0xe854
84 #define PLA_MISC_0 0xe858
85 #define PLA_MISC_1 0xe85a
86 #define PLA_OCP_GPHY_BASE 0xe86c
87 #define PLA_TALLYCNT 0xe890
88 #define PLA_SFF_STS_7 0xe8de
89 #define PLA_PHYSTATUS 0xe908
90 #define PLA_BP_BA 0xfc26
91 #define PLA_BP_0 0xfc28
92 #define PLA_BP_1 0xfc2a
93 #define PLA_BP_2 0xfc2c
94 #define PLA_BP_3 0xfc2e
95 #define PLA_BP_4 0xfc30
96 #define PLA_BP_5 0xfc32
97 #define PLA_BP_6 0xfc34
98 #define PLA_BP_7 0xfc36
99 #define PLA_BP_EN 0xfc38
100
101 #define USB_USB2PHY 0xb41e
102 #define USB_SSPHYLINK2 0xb428
103 #define USB_U2P3_CTRL 0xb460
104 #define USB_CSR_DUMMY1 0xb464
105 #define USB_CSR_DUMMY2 0xb466
106 #define USB_DEV_STAT 0xb808
107 #define USB_CONNECT_TIMER 0xcbf8
108 #define USB_BURST_SIZE 0xcfc0
109 #define USB_USB_CTRL 0xd406
110 #define USB_PHY_CTRL 0xd408
111 #define USB_TX_AGG 0xd40a
112 #define USB_RX_BUF_TH 0xd40c
113 #define USB_USB_TIMER 0xd428
114 #define USB_RX_EARLY_TIMEOUT 0xd42c
115 #define USB_RX_EARLY_SIZE 0xd42e
116 #define USB_PM_CTRL_STATUS 0xd432
117 #define USB_TX_DMA 0xd434
118 #define USB_TOLERANCE 0xd490
119 #define USB_LPM_CTRL 0xd41a
120 #define USB_BMU_RESET 0xd4b0
121 #define USB_UPS_CTRL 0xd800
122 #define USB_MISC_0 0xd81a
123 #define USB_POWER_CUT 0xd80a
124 #define USB_AFE_CTRL2 0xd824
125 #define USB_WDT11_CTRL 0xe43c
126 #define USB_BP_BA 0xfc26
127 #define USB_BP_0 0xfc28
128 #define USB_BP_1 0xfc2a
129 #define USB_BP_2 0xfc2c
130 #define USB_BP_3 0xfc2e
131 #define USB_BP_4 0xfc30
132 #define USB_BP_5 0xfc32
133 #define USB_BP_6 0xfc34
134 #define USB_BP_7 0xfc36
135 #define USB_BP_EN 0xfc38
136
137 /* OCP Registers */
138 #define OCP_ALDPS_CONFIG 0x2010
139 #define OCP_EEE_CONFIG1 0x2080
140 #define OCP_EEE_CONFIG2 0x2092
141 #define OCP_EEE_CONFIG3 0x2094
142 #define OCP_BASE_MII 0xa400
143 #define OCP_EEE_AR 0xa41a
144 #define OCP_EEE_DATA 0xa41c
145 #define OCP_PHY_STATUS 0xa420
146 #define OCP_POWER_CFG 0xa430
147 #define OCP_EEE_CFG 0xa432
148 #define OCP_SRAM_ADDR 0xa436
149 #define OCP_SRAM_DATA 0xa438
150 #define OCP_DOWN_SPEED 0xa442
151 #define OCP_EEE_ABLE 0xa5c4
152 #define OCP_EEE_ADV 0xa5d0
153 #define OCP_EEE_LPABLE 0xa5d2
154 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
155 #define OCP_ADC_CFG 0xbc06
156
157 /* SRAM Register */
158 #define SRAM_LPF_CFG 0x8012
159 #define SRAM_10M_AMP1 0x8080
160 #define SRAM_10M_AMP2 0x8082
161 #define SRAM_IMPEDANCE 0x8084
162
163 /* PLA_RCR */
164 #define RCR_AAP 0x00000001
165 #define RCR_APM 0x00000002
166 #define RCR_AM 0x00000004
167 #define RCR_AB 0x00000008
168 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
169
170 /* PLA_RXFIFO_CTRL0 */
171 #define RXFIFO_THR1_NORMAL 0x00080002
172 #define RXFIFO_THR1_OOB 0x01800003
173
174 /* PLA_RXFIFO_CTRL1 */
175 #define RXFIFO_THR2_FULL 0x00000060
176 #define RXFIFO_THR2_HIGH 0x00000038
177 #define RXFIFO_THR2_OOB 0x0000004a
178 #define RXFIFO_THR2_NORMAL 0x00a0
179
180 /* PLA_RXFIFO_CTRL2 */
181 #define RXFIFO_THR3_FULL 0x00000078
182 #define RXFIFO_THR3_HIGH 0x00000048
183 #define RXFIFO_THR3_OOB 0x0000005a
184 #define RXFIFO_THR3_NORMAL 0x0110
185
186 /* PLA_TXFIFO_CTRL */
187 #define TXFIFO_THR_NORMAL 0x00400008
188 #define TXFIFO_THR_NORMAL2 0x01000008
189
190 /* PLA_DMY_REG0 */
191 #define ECM_ALDPS 0x0002
192
193 /* PLA_FMC */
194 #define FMC_FCR_MCU_EN 0x0001
195
196 /* PLA_EEEP_CR */
197 #define EEEP_CR_EEEP_TX 0x0002
198
199 /* PLA_WDT6_CTRL */
200 #define WDT6_SET_MODE 0x0010
201
202 /* PLA_TCR0 */
203 #define TCR0_TX_EMPTY 0x0800
204 #define TCR0_AUTO_FIFO 0x0080
205
206 /* PLA_TCR1 */
207 #define VERSION_MASK 0x7cf0
208
209 /* PLA_MTPS */
210 #define MTPS_JUMBO (12 * 1024 / 64)
211 #define MTPS_DEFAULT (6 * 1024 / 64)
212
213 /* PLA_RSTTALLY */
214 #define TALLY_RESET 0x0001
215
216 /* PLA_CR */
217 #define CR_RST 0x10
218 #define CR_RE 0x08
219 #define CR_TE 0x04
220
221 /* PLA_CRWECR */
222 #define CRWECR_NORAML 0x00
223 #define CRWECR_CONFIG 0xc0
224
225 /* PLA_OOB_CTRL */
226 #define NOW_IS_OOB 0x80
227 #define TXFIFO_EMPTY 0x20
228 #define RXFIFO_EMPTY 0x10
229 #define LINK_LIST_READY 0x02
230 #define DIS_MCU_CLROOB 0x01
231 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
232
233 /* PLA_MISC_1 */
234 #define RXDY_GATED_EN 0x0008
235
236 /* PLA_SFF_STS_7 */
237 #define RE_INIT_LL 0x8000
238 #define MCU_BORW_EN 0x4000
239
240 /* PLA_CPCR */
241 #define CPCR_RX_VLAN 0x0040
242
243 /* PLA_CFG_WOL */
244 #define MAGIC_EN 0x0001
245
246 /* PLA_TEREDO_CFG */
247 #define TEREDO_SEL 0x8000
248 #define TEREDO_WAKE_MASK 0x7f00
249 #define TEREDO_RS_EVENT_MASK 0x00fe
250 #define OOB_TEREDO_EN 0x0001
251
252 /* PAL_BDC_CR */
253 #define ALDPS_PROXY_MODE 0x0001
254
255 /* PLA_CONFIG34 */
256 #define LINK_ON_WAKE_EN 0x0010
257 #define LINK_OFF_WAKE_EN 0x0008
258
259 /* PLA_CONFIG5 */
260 #define BWF_EN 0x0040
261 #define MWF_EN 0x0020
262 #define UWF_EN 0x0010
263 #define LAN_WAKE_EN 0x0002
264
265 /* PLA_LED_FEATURE */
266 #define LED_MODE_MASK 0x0700
267
268 /* PLA_PHY_PWR */
269 #define TX_10M_IDLE_EN 0x0080
270 #define PFM_PWM_SWITCH 0x0040
271
272 /* PLA_MAC_PWR_CTRL */
273 #define D3_CLK_GATED_EN 0x00004000
274 #define MCU_CLK_RATIO 0x07010f07
275 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
276 #define ALDPS_SPDWN_RATIO 0x0f87
277
278 /* PLA_MAC_PWR_CTRL2 */
279 #define EEE_SPDWN_RATIO 0x8007
280
281 /* PLA_MAC_PWR_CTRL3 */
282 #define PKT_AVAIL_SPDWN_EN 0x0100
283 #define SUSPEND_SPDWN_EN 0x0004
284 #define U1U2_SPDWN_EN 0x0002
285 #define L1_SPDWN_EN 0x0001
286
287 /* PLA_MAC_PWR_CTRL4 */
288 #define PWRSAVE_SPDWN_EN 0x1000
289 #define RXDV_SPDWN_EN 0x0800
290 #define TX10MIDLE_EN 0x0100
291 #define TP100_SPDWN_EN 0x0020
292 #define TP500_SPDWN_EN 0x0010
293 #define TP1000_SPDWN_EN 0x0008
294 #define EEE_SPDWN_EN 0x0001
295
296 /* PLA_GPHY_INTR_IMR */
297 #define GPHY_STS_MSK 0x0001
298 #define SPEED_DOWN_MSK 0x0002
299 #define SPDWN_RXDV_MSK 0x0004
300 #define SPDWN_LINKCHG_MSK 0x0008
301
302 /* PLA_PHYAR */
303 #define PHYAR_FLAG 0x80000000
304
305 /* PLA_EEE_CR */
306 #define EEE_RX_EN 0x0001
307 #define EEE_TX_EN 0x0002
308
309 /* PLA_BOOT_CTRL */
310 #define AUTOLOAD_DONE 0x0002
311
312 /* USB_USB2PHY */
313 #define USB2PHY_SUSPEND 0x0001
314 #define USB2PHY_L1 0x0002
315
316 /* USB_SSPHYLINK2 */
317 #define pwd_dn_scale_mask 0x3ffe
318 #define pwd_dn_scale(x) ((x) << 1)
319
320 /* USB_CSR_DUMMY1 */
321 #define DYNAMIC_BURST 0x0001
322
323 /* USB_CSR_DUMMY2 */
324 #define EP4_FULL_FC 0x0001
325
326 /* USB_DEV_STAT */
327 #define STAT_SPEED_MASK 0x0006
328 #define STAT_SPEED_HIGH 0x0000
329 #define STAT_SPEED_FULL 0x0002
330
331 /* USB_TX_AGG */
332 #define TX_AGG_MAX_THRESHOLD 0x03
333
334 /* USB_RX_BUF_TH */
335 #define RX_THR_SUPPER 0x0c350180
336 #define RX_THR_HIGH 0x7a120180
337 #define RX_THR_SLOW 0xffff0180
338
339 /* USB_TX_DMA */
340 #define TEST_MODE_DISABLE 0x00000001
341 #define TX_SIZE_ADJUST1 0x00000100
342
343 /* USB_BMU_RESET */
344 #define BMU_RESET_EP_IN 0x01
345 #define BMU_RESET_EP_OUT 0x02
346
347 /* USB_UPS_CTRL */
348 #define POWER_CUT 0x0100
349
350 /* USB_PM_CTRL_STATUS */
351 #define RESUME_INDICATE 0x0001
352
353 /* USB_USB_CTRL */
354 #define RX_AGG_DISABLE 0x0010
355 #define RX_ZERO_EN 0x0080
356
357 /* USB_U2P3_CTRL */
358 #define U2P3_ENABLE 0x0001
359
360 /* USB_POWER_CUT */
361 #define PWR_EN 0x0001
362 #define PHASE2_EN 0x0008
363
364 /* USB_MISC_0 */
365 #define PCUT_STATUS 0x0001
366
367 /* USB_RX_EARLY_TIMEOUT */
368 #define COALESCE_SUPER 85000U
369 #define COALESCE_HIGH 250000U
370 #define COALESCE_SLOW 524280U
371
372 /* USB_WDT11_CTRL */
373 #define TIMER11_EN 0x0001
374
375 /* USB_LPM_CTRL */
376 /* bit 4 ~ 5: fifo empty boundary */
377 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
378 /* bit 2 ~ 3: LMP timer */
379 #define LPM_TIMER_MASK 0x0c
380 #define LPM_TIMER_500MS 0x04 /* 500 ms */
381 #define LPM_TIMER_500US 0x0c /* 500 us */
382 #define ROK_EXIT_LPM 0x02
383
384 /* USB_AFE_CTRL2 */
385 #define SEN_VAL_MASK 0xf800
386 #define SEN_VAL_NORMAL 0xa000
387 #define SEL_RXIDLE 0x0100
388
389 /* OCP_ALDPS_CONFIG */
390 #define ENPWRSAVE 0x8000
391 #define ENPDNPS 0x0200
392 #define LINKENA 0x0100
393 #define DIS_SDSAVE 0x0010
394
395 /* OCP_PHY_STATUS */
396 #define PHY_STAT_MASK 0x0007
397 #define PHY_STAT_LAN_ON 3
398 #define PHY_STAT_PWRDN 5
399
400 /* OCP_POWER_CFG */
401 #define EEE_CLKDIV_EN 0x8000
402 #define EN_ALDPS 0x0004
403 #define EN_10M_PLLOFF 0x0001
404
405 /* OCP_EEE_CONFIG1 */
406 #define RG_TXLPI_MSK_HFDUP 0x8000
407 #define RG_MATCLR_EN 0x4000
408 #define EEE_10_CAP 0x2000
409 #define EEE_NWAY_EN 0x1000
410 #define TX_QUIET_EN 0x0200
411 #define RX_QUIET_EN 0x0100
412 #define sd_rise_time_mask 0x0070
413 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
414 #define RG_RXLPI_MSK_HFDUP 0x0008
415 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
416
417 /* OCP_EEE_CONFIG2 */
418 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
419 #define RG_DACQUIET_EN 0x0400
420 #define RG_LDVQUIET_EN 0x0200
421 #define RG_CKRSEL 0x0020
422 #define RG_EEEPRG_EN 0x0010
423
424 /* OCP_EEE_CONFIG3 */
425 #define fast_snr_mask 0xff80
426 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
427 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
428 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
429
430 /* OCP_EEE_AR */
431 /* bit[15:14] function */
432 #define FUN_ADDR 0x0000
433 #define FUN_DATA 0x4000
434 /* bit[4:0] device addr */
435
436 /* OCP_EEE_CFG */
437 #define CTAP_SHORT_EN 0x0040
438 #define EEE10_EN 0x0010
439
440 /* OCP_DOWN_SPEED */
441 #define EN_10M_BGOFF 0x0080
442
443 /* OCP_PHY_STATE */
444 #define TXDIS_STATE 0x01
445 #define ABD_STATE 0x02
446
447 /* OCP_ADC_CFG */
448 #define CKADSEL_L 0x0100
449 #define ADC_EN 0x0080
450 #define EN_EMI_L 0x0040
451
452 /* SRAM_LPF_CFG */
453 #define LPF_AUTO_TUNE 0x8000
454
455 /* SRAM_10M_AMP1 */
456 #define GDAC_IB_UPALL 0x0008
457
458 /* SRAM_10M_AMP2 */
459 #define AMP_DN 0x0200
460
461 /* SRAM_IMPEDANCE */
462 #define RX_DRIVING_MASK 0x6000
463
464 /* MAC PASSTHRU */
465 #define AD_MASK 0xfee0
466 #define EFUSE 0xcfdb
467 #define PASS_THRU_MASK 0x1
468
469 enum rtl_register_content {
470 _1000bps = 0x10,
471 _100bps = 0x08,
472 _10bps = 0x04,
473 LINK_STATUS = 0x02,
474 FULL_DUP = 0x01,
475 };
476
477 #define RTL8152_MAX_TX 4
478 #define RTL8152_MAX_RX 10
479 #define INTBUFSIZE 2
480 #define CRC_SIZE 4
481 #define TX_ALIGN 4
482 #define RX_ALIGN 8
483
484 #define INTR_LINK 0x0004
485
486 #define RTL8152_REQT_READ 0xc0
487 #define RTL8152_REQT_WRITE 0x40
488 #define RTL8152_REQ_GET_REGS 0x05
489 #define RTL8152_REQ_SET_REGS 0x05
490
491 #define BYTE_EN_DWORD 0xff
492 #define BYTE_EN_WORD 0x33
493 #define BYTE_EN_BYTE 0x11
494 #define BYTE_EN_SIX_BYTES 0x3f
495 #define BYTE_EN_START_MASK 0x0f
496 #define BYTE_EN_END_MASK 0xf0
497
498 #define RTL8153_MAX_PACKET 9216 /* 9K */
499 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
500 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
501 #define RTL8153_RMS RTL8153_MAX_PACKET
502 #define RTL8152_TX_TIMEOUT (5 * HZ)
503 #define RTL8152_NAPI_WEIGHT 64
504
505 /* rtl8152 flags */
506 enum rtl8152_flags {
507 RTL8152_UNPLUG = 0,
508 RTL8152_SET_RX_MODE,
509 WORK_ENABLE,
510 RTL8152_LINK_CHG,
511 SELECTIVE_SUSPEND,
512 PHY_RESET,
513 SCHEDULE_NAPI,
514 };
515
516 /* Define these values to match your device */
517 #define VENDOR_ID_REALTEK 0x0bda
518 #define VENDOR_ID_SAMSUNG 0x04e8
519 #define VENDOR_ID_LENOVO 0x17ef
520 #define VENDOR_ID_NVIDIA 0x0955
521
522 #define MCU_TYPE_PLA 0x0100
523 #define MCU_TYPE_USB 0x0000
524
525 struct tally_counter {
526 __le64 tx_packets;
527 __le64 rx_packets;
528 __le64 tx_errors;
529 __le32 rx_errors;
530 __le16 rx_missed;
531 __le16 align_errors;
532 __le32 tx_one_collision;
533 __le32 tx_multi_collision;
534 __le64 rx_unicast;
535 __le64 rx_broadcast;
536 __le32 rx_multicast;
537 __le16 tx_aborted;
538 __le16 tx_underrun;
539 };
540
541 struct rx_desc {
542 __le32 opts1;
543 #define RX_LEN_MASK 0x7fff
544
545 __le32 opts2;
546 #define RD_UDP_CS BIT(23)
547 #define RD_TCP_CS BIT(22)
548 #define RD_IPV6_CS BIT(20)
549 #define RD_IPV4_CS BIT(19)
550
551 __le32 opts3;
552 #define IPF BIT(23) /* IP checksum fail */
553 #define UDPF BIT(22) /* UDP checksum fail */
554 #define TCPF BIT(21) /* TCP checksum fail */
555 #define RX_VLAN_TAG BIT(16)
556
557 __le32 opts4;
558 __le32 opts5;
559 __le32 opts6;
560 };
561
562 struct tx_desc {
563 __le32 opts1;
564 #define TX_FS BIT(31) /* First segment of a packet */
565 #define TX_LS BIT(30) /* Final segment of a packet */
566 #define GTSENDV4 BIT(28)
567 #define GTSENDV6 BIT(27)
568 #define GTTCPHO_SHIFT 18
569 #define GTTCPHO_MAX 0x7fU
570 #define TX_LEN_MAX 0x3ffffU
571
572 __le32 opts2;
573 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
574 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
575 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
576 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
577 #define MSS_SHIFT 17
578 #define MSS_MAX 0x7ffU
579 #define TCPHO_SHIFT 17
580 #define TCPHO_MAX 0x7ffU
581 #define TX_VLAN_TAG BIT(16)
582 };
583
584 struct r8152;
585
586 struct rx_agg {
587 struct list_head list;
588 struct urb *urb;
589 struct r8152 *context;
590 void *buffer;
591 void *head;
592 };
593
594 struct tx_agg {
595 struct list_head list;
596 struct urb *urb;
597 struct r8152 *context;
598 void *buffer;
599 void *head;
600 u32 skb_num;
601 u32 skb_len;
602 };
603
604 struct r8152 {
605 unsigned long flags;
606 struct usb_device *udev;
607 struct napi_struct napi;
608 struct usb_interface *intf;
609 struct net_device *netdev;
610 struct urb *intr_urb;
611 struct tx_agg tx_info[RTL8152_MAX_TX];
612 struct rx_agg rx_info[RTL8152_MAX_RX];
613 struct list_head rx_done, tx_free;
614 struct sk_buff_head tx_queue, rx_queue;
615 spinlock_t rx_lock, tx_lock;
616 struct delayed_work schedule, hw_phy_work;
617 struct mii_if_info mii;
618 struct mutex control; /* use for hw setting */
619 #ifdef CONFIG_PM_SLEEP
620 struct notifier_block pm_notifier;
621 #endif
622
623 struct rtl_ops {
624 void (*init)(struct r8152 *);
625 int (*enable)(struct r8152 *);
626 void (*disable)(struct r8152 *);
627 void (*up)(struct r8152 *);
628 void (*down)(struct r8152 *);
629 void (*unload)(struct r8152 *);
630 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
631 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
632 bool (*in_nway)(struct r8152 *);
633 void (*hw_phy_cfg)(struct r8152 *);
634 void (*autosuspend_en)(struct r8152 *tp, bool enable);
635 } rtl_ops;
636
637 int intr_interval;
638 u32 saved_wolopts;
639 u32 msg_enable;
640 u32 tx_qlen;
641 u32 coalesce;
642 u16 ocp_base;
643 u16 speed;
644 u8 *intr_buff;
645 u8 version;
646 u8 duplex;
647 u8 autoneg;
648 };
649
650 enum rtl_version {
651 RTL_VER_UNKNOWN = 0,
652 RTL_VER_01,
653 RTL_VER_02,
654 RTL_VER_03,
655 RTL_VER_04,
656 RTL_VER_05,
657 RTL_VER_06,
658 RTL_VER_MAX
659 };
660
661 enum tx_csum_stat {
662 TX_CSUM_SUCCESS = 0,
663 TX_CSUM_TSO,
664 TX_CSUM_NONE
665 };
666
667 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
668 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
669 */
670 static const int multicast_filter_limit = 32;
671 static unsigned int agg_buf_sz = 16384;
672
673 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
674 VLAN_ETH_HLEN - VLAN_HLEN)
675
676 static
677 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
678 {
679 int ret;
680 void *tmp;
681
682 tmp = kmalloc(size, GFP_KERNEL);
683 if (!tmp)
684 return -ENOMEM;
685
686 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
687 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
688 value, index, tmp, size, 500);
689
690 memcpy(data, tmp, size);
691 kfree(tmp);
692
693 return ret;
694 }
695
696 static
697 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
698 {
699 int ret;
700 void *tmp;
701
702 tmp = kmemdup(data, size, GFP_KERNEL);
703 if (!tmp)
704 return -ENOMEM;
705
706 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
707 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
708 value, index, tmp, size, 500);
709
710 kfree(tmp);
711
712 return ret;
713 }
714
715 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
716 void *data, u16 type)
717 {
718 u16 limit = 64;
719 int ret = 0;
720
721 if (test_bit(RTL8152_UNPLUG, &tp->flags))
722 return -ENODEV;
723
724 /* both size and indix must be 4 bytes align */
725 if ((size & 3) || !size || (index & 3) || !data)
726 return -EPERM;
727
728 if ((u32)index + (u32)size > 0xffff)
729 return -EPERM;
730
731 while (size) {
732 if (size > limit) {
733 ret = get_registers(tp, index, type, limit, data);
734 if (ret < 0)
735 break;
736
737 index += limit;
738 data += limit;
739 size -= limit;
740 } else {
741 ret = get_registers(tp, index, type, size, data);
742 if (ret < 0)
743 break;
744
745 index += size;
746 data += size;
747 size = 0;
748 break;
749 }
750 }
751
752 if (ret == -ENODEV)
753 set_bit(RTL8152_UNPLUG, &tp->flags);
754
755 return ret;
756 }
757
758 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
759 u16 size, void *data, u16 type)
760 {
761 int ret;
762 u16 byteen_start, byteen_end, byen;
763 u16 limit = 512;
764
765 if (test_bit(RTL8152_UNPLUG, &tp->flags))
766 return -ENODEV;
767
768 /* both size and indix must be 4 bytes align */
769 if ((size & 3) || !size || (index & 3) || !data)
770 return -EPERM;
771
772 if ((u32)index + (u32)size > 0xffff)
773 return -EPERM;
774
775 byteen_start = byteen & BYTE_EN_START_MASK;
776 byteen_end = byteen & BYTE_EN_END_MASK;
777
778 byen = byteen_start | (byteen_start << 4);
779 ret = set_registers(tp, index, type | byen, 4, data);
780 if (ret < 0)
781 goto error1;
782
783 index += 4;
784 data += 4;
785 size -= 4;
786
787 if (size) {
788 size -= 4;
789
790 while (size) {
791 if (size > limit) {
792 ret = set_registers(tp, index,
793 type | BYTE_EN_DWORD,
794 limit, data);
795 if (ret < 0)
796 goto error1;
797
798 index += limit;
799 data += limit;
800 size -= limit;
801 } else {
802 ret = set_registers(tp, index,
803 type | BYTE_EN_DWORD,
804 size, data);
805 if (ret < 0)
806 goto error1;
807
808 index += size;
809 data += size;
810 size = 0;
811 break;
812 }
813 }
814
815 byen = byteen_end | (byteen_end >> 4);
816 ret = set_registers(tp, index, type | byen, 4, data);
817 if (ret < 0)
818 goto error1;
819 }
820
821 error1:
822 if (ret == -ENODEV)
823 set_bit(RTL8152_UNPLUG, &tp->flags);
824
825 return ret;
826 }
827
828 static inline
829 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
830 {
831 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
832 }
833
834 static inline
835 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
836 {
837 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
838 }
839
840 static inline
841 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
842 {
843 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
844 }
845
846 static inline
847 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
848 {
849 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
850 }
851
852 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
853 {
854 __le32 data;
855
856 generic_ocp_read(tp, index, sizeof(data), &data, type);
857
858 return __le32_to_cpu(data);
859 }
860
861 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
862 {
863 __le32 tmp = __cpu_to_le32(data);
864
865 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
866 }
867
868 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
869 {
870 u32 data;
871 __le32 tmp;
872 u8 shift = index & 2;
873
874 index &= ~3;
875
876 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
877
878 data = __le32_to_cpu(tmp);
879 data >>= (shift * 8);
880 data &= 0xffff;
881
882 return (u16)data;
883 }
884
885 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
886 {
887 u32 mask = 0xffff;
888 __le32 tmp;
889 u16 byen = BYTE_EN_WORD;
890 u8 shift = index & 2;
891
892 data &= mask;
893
894 if (index & 2) {
895 byen <<= shift;
896 mask <<= (shift * 8);
897 data <<= (shift * 8);
898 index &= ~3;
899 }
900
901 tmp = __cpu_to_le32(data);
902
903 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
904 }
905
906 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
907 {
908 u32 data;
909 __le32 tmp;
910 u8 shift = index & 3;
911
912 index &= ~3;
913
914 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
915
916 data = __le32_to_cpu(tmp);
917 data >>= (shift * 8);
918 data &= 0xff;
919
920 return (u8)data;
921 }
922
923 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
924 {
925 u32 mask = 0xff;
926 __le32 tmp;
927 u16 byen = BYTE_EN_BYTE;
928 u8 shift = index & 3;
929
930 data &= mask;
931
932 if (index & 3) {
933 byen <<= shift;
934 mask <<= (shift * 8);
935 data <<= (shift * 8);
936 index &= ~3;
937 }
938
939 tmp = __cpu_to_le32(data);
940
941 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
942 }
943
944 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
945 {
946 u16 ocp_base, ocp_index;
947
948 ocp_base = addr & 0xf000;
949 if (ocp_base != tp->ocp_base) {
950 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
951 tp->ocp_base = ocp_base;
952 }
953
954 ocp_index = (addr & 0x0fff) | 0xb000;
955 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
956 }
957
958 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
959 {
960 u16 ocp_base, ocp_index;
961
962 ocp_base = addr & 0xf000;
963 if (ocp_base != tp->ocp_base) {
964 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
965 tp->ocp_base = ocp_base;
966 }
967
968 ocp_index = (addr & 0x0fff) | 0xb000;
969 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
970 }
971
972 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
973 {
974 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
975 }
976
977 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
978 {
979 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
980 }
981
982 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
983 {
984 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
985 ocp_reg_write(tp, OCP_SRAM_DATA, data);
986 }
987
988 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
989 {
990 struct r8152 *tp = netdev_priv(netdev);
991 int ret;
992
993 if (test_bit(RTL8152_UNPLUG, &tp->flags))
994 return -ENODEV;
995
996 if (phy_id != R8152_PHY_ID)
997 return -EINVAL;
998
999 ret = r8152_mdio_read(tp, reg);
1000
1001 return ret;
1002 }
1003
1004 static
1005 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1006 {
1007 struct r8152 *tp = netdev_priv(netdev);
1008
1009 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1010 return;
1011
1012 if (phy_id != R8152_PHY_ID)
1013 return;
1014
1015 r8152_mdio_write(tp, reg, val);
1016 }
1017
1018 static int
1019 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1020
1021 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1022 {
1023 struct r8152 *tp = netdev_priv(netdev);
1024 struct sockaddr *addr = p;
1025 int ret = -EADDRNOTAVAIL;
1026
1027 if (!is_valid_ether_addr(addr->sa_data))
1028 goto out1;
1029
1030 ret = usb_autopm_get_interface(tp->intf);
1031 if (ret < 0)
1032 goto out1;
1033
1034 mutex_lock(&tp->control);
1035
1036 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1037
1038 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1039 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1040 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1041
1042 mutex_unlock(&tp->control);
1043
1044 usb_autopm_put_interface(tp->intf);
1045 out1:
1046 return ret;
1047 }
1048
1049 /* Devices containing RTL8153-AD can support a persistent
1050 * host system provided MAC address.
1051 * Examples of this are Dell TB15 and Dell WD15 docks
1052 */
1053 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1054 {
1055 acpi_status status;
1056 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1057 union acpi_object *obj;
1058 int ret = -EINVAL;
1059 u32 ocp_data;
1060 unsigned char buf[6];
1061
1062 /* test for -AD variant of RTL8153 */
1063 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1064 if ((ocp_data & AD_MASK) != 0x1000)
1065 return -ENODEV;
1066
1067 /* test for MAC address pass-through bit */
1068 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1069 if ((ocp_data & PASS_THRU_MASK) != 1)
1070 return -ENODEV;
1071
1072 /* returns _AUXMAC_#AABBCCDDEEFF# */
1073 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1074 obj = (union acpi_object *)buffer.pointer;
1075 if (!ACPI_SUCCESS(status))
1076 return -ENODEV;
1077 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1078 netif_warn(tp, probe, tp->netdev,
1079 "Invalid buffer when reading pass-thru MAC addr: "
1080 "(%d, %d)\n",
1081 obj->type, obj->string.length);
1082 goto amacout;
1083 }
1084 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1085 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1086 netif_warn(tp, probe, tp->netdev,
1087 "Invalid header when reading pass-thru MAC addr\n");
1088 goto amacout;
1089 }
1090 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1091 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1092 netif_warn(tp, probe, tp->netdev,
1093 "Invalid MAC when reading pass-thru MAC addr: "
1094 "%d, %pM\n", ret, buf);
1095 ret = -EINVAL;
1096 goto amacout;
1097 }
1098 memcpy(sa->sa_data, buf, 6);
1099 ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
1100 netif_info(tp, probe, tp->netdev,
1101 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1102
1103 amacout:
1104 kfree(obj);
1105 return ret;
1106 }
1107
1108 static int set_ethernet_addr(struct r8152 *tp)
1109 {
1110 struct net_device *dev = tp->netdev;
1111 struct sockaddr sa;
1112 int ret;
1113
1114 if (tp->version == RTL_VER_01)
1115 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1116 else {
1117 /* if this is not an RTL8153-AD, no eFuse mac pass thru set,
1118 * or system doesn't provide valid _SB.AMAC this will be
1119 * be expected to non-zero
1120 */
1121 ret = vendor_mac_passthru_addr_read(tp, &sa);
1122 if (ret < 0)
1123 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1124 }
1125
1126 if (ret < 0) {
1127 netif_err(tp, probe, dev, "Get ether addr fail\n");
1128 } else if (!is_valid_ether_addr(sa.sa_data)) {
1129 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1130 sa.sa_data);
1131 eth_hw_addr_random(dev);
1132 ether_addr_copy(sa.sa_data, dev->dev_addr);
1133 ret = rtl8152_set_mac_address(dev, &sa);
1134 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1135 sa.sa_data);
1136 } else {
1137 if (tp->version == RTL_VER_01)
1138 ether_addr_copy(dev->dev_addr, sa.sa_data);
1139 else
1140 ret = rtl8152_set_mac_address(dev, &sa);
1141 }
1142
1143 return ret;
1144 }
1145
1146 static void read_bulk_callback(struct urb *urb)
1147 {
1148 struct net_device *netdev;
1149 int status = urb->status;
1150 struct rx_agg *agg;
1151 struct r8152 *tp;
1152
1153 agg = urb->context;
1154 if (!agg)
1155 return;
1156
1157 tp = agg->context;
1158 if (!tp)
1159 return;
1160
1161 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1162 return;
1163
1164 if (!test_bit(WORK_ENABLE, &tp->flags))
1165 return;
1166
1167 netdev = tp->netdev;
1168
1169 /* When link down, the driver would cancel all bulks. */
1170 /* This avoid the re-submitting bulk */
1171 if (!netif_carrier_ok(netdev))
1172 return;
1173
1174 usb_mark_last_busy(tp->udev);
1175
1176 switch (status) {
1177 case 0:
1178 if (urb->actual_length < ETH_ZLEN)
1179 break;
1180
1181 spin_lock(&tp->rx_lock);
1182 list_add_tail(&agg->list, &tp->rx_done);
1183 spin_unlock(&tp->rx_lock);
1184 napi_schedule(&tp->napi);
1185 return;
1186 case -ESHUTDOWN:
1187 set_bit(RTL8152_UNPLUG, &tp->flags);
1188 netif_device_detach(tp->netdev);
1189 return;
1190 case -ENOENT:
1191 return; /* the urb is in unlink state */
1192 case -ETIME:
1193 if (net_ratelimit())
1194 netdev_warn(netdev, "maybe reset is needed?\n");
1195 break;
1196 default:
1197 if (net_ratelimit())
1198 netdev_warn(netdev, "Rx status %d\n", status);
1199 break;
1200 }
1201
1202 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1203 }
1204
1205 static void write_bulk_callback(struct urb *urb)
1206 {
1207 struct net_device_stats *stats;
1208 struct net_device *netdev;
1209 struct tx_agg *agg;
1210 struct r8152 *tp;
1211 int status = urb->status;
1212
1213 agg = urb->context;
1214 if (!agg)
1215 return;
1216
1217 tp = agg->context;
1218 if (!tp)
1219 return;
1220
1221 netdev = tp->netdev;
1222 stats = &netdev->stats;
1223 if (status) {
1224 if (net_ratelimit())
1225 netdev_warn(netdev, "Tx status %d\n", status);
1226 stats->tx_errors += agg->skb_num;
1227 } else {
1228 stats->tx_packets += agg->skb_num;
1229 stats->tx_bytes += agg->skb_len;
1230 }
1231
1232 spin_lock(&tp->tx_lock);
1233 list_add_tail(&agg->list, &tp->tx_free);
1234 spin_unlock(&tp->tx_lock);
1235
1236 usb_autopm_put_interface_async(tp->intf);
1237
1238 if (!netif_carrier_ok(netdev))
1239 return;
1240
1241 if (!test_bit(WORK_ENABLE, &tp->flags))
1242 return;
1243
1244 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1245 return;
1246
1247 if (!skb_queue_empty(&tp->tx_queue))
1248 napi_schedule(&tp->napi);
1249 }
1250
1251 static void intr_callback(struct urb *urb)
1252 {
1253 struct r8152 *tp;
1254 __le16 *d;
1255 int status = urb->status;
1256 int res;
1257
1258 tp = urb->context;
1259 if (!tp)
1260 return;
1261
1262 if (!test_bit(WORK_ENABLE, &tp->flags))
1263 return;
1264
1265 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1266 return;
1267
1268 switch (status) {
1269 case 0: /* success */
1270 break;
1271 case -ECONNRESET: /* unlink */
1272 case -ESHUTDOWN:
1273 netif_device_detach(tp->netdev);
1274 case -ENOENT:
1275 case -EPROTO:
1276 netif_info(tp, intr, tp->netdev,
1277 "Stop submitting intr, status %d\n", status);
1278 return;
1279 case -EOVERFLOW:
1280 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1281 goto resubmit;
1282 /* -EPIPE: should clear the halt */
1283 default:
1284 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1285 goto resubmit;
1286 }
1287
1288 d = urb->transfer_buffer;
1289 if (INTR_LINK & __le16_to_cpu(d[0])) {
1290 if (!netif_carrier_ok(tp->netdev)) {
1291 set_bit(RTL8152_LINK_CHG, &tp->flags);
1292 schedule_delayed_work(&tp->schedule, 0);
1293 }
1294 } else {
1295 if (netif_carrier_ok(tp->netdev)) {
1296 set_bit(RTL8152_LINK_CHG, &tp->flags);
1297 schedule_delayed_work(&tp->schedule, 0);
1298 }
1299 }
1300
1301 resubmit:
1302 res = usb_submit_urb(urb, GFP_ATOMIC);
1303 if (res == -ENODEV) {
1304 set_bit(RTL8152_UNPLUG, &tp->flags);
1305 netif_device_detach(tp->netdev);
1306 } else if (res) {
1307 netif_err(tp, intr, tp->netdev,
1308 "can't resubmit intr, status %d\n", res);
1309 }
1310 }
1311
1312 static inline void *rx_agg_align(void *data)
1313 {
1314 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1315 }
1316
1317 static inline void *tx_agg_align(void *data)
1318 {
1319 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1320 }
1321
1322 static void free_all_mem(struct r8152 *tp)
1323 {
1324 int i;
1325
1326 for (i = 0; i < RTL8152_MAX_RX; i++) {
1327 usb_free_urb(tp->rx_info[i].urb);
1328 tp->rx_info[i].urb = NULL;
1329
1330 kfree(tp->rx_info[i].buffer);
1331 tp->rx_info[i].buffer = NULL;
1332 tp->rx_info[i].head = NULL;
1333 }
1334
1335 for (i = 0; i < RTL8152_MAX_TX; i++) {
1336 usb_free_urb(tp->tx_info[i].urb);
1337 tp->tx_info[i].urb = NULL;
1338
1339 kfree(tp->tx_info[i].buffer);
1340 tp->tx_info[i].buffer = NULL;
1341 tp->tx_info[i].head = NULL;
1342 }
1343
1344 usb_free_urb(tp->intr_urb);
1345 tp->intr_urb = NULL;
1346
1347 kfree(tp->intr_buff);
1348 tp->intr_buff = NULL;
1349 }
1350
1351 static int alloc_all_mem(struct r8152 *tp)
1352 {
1353 struct net_device *netdev = tp->netdev;
1354 struct usb_interface *intf = tp->intf;
1355 struct usb_host_interface *alt = intf->cur_altsetting;
1356 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1357 struct urb *urb;
1358 int node, i;
1359 u8 *buf;
1360
1361 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1362
1363 spin_lock_init(&tp->rx_lock);
1364 spin_lock_init(&tp->tx_lock);
1365 INIT_LIST_HEAD(&tp->tx_free);
1366 skb_queue_head_init(&tp->tx_queue);
1367 skb_queue_head_init(&tp->rx_queue);
1368
1369 for (i = 0; i < RTL8152_MAX_RX; i++) {
1370 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1371 if (!buf)
1372 goto err1;
1373
1374 if (buf != rx_agg_align(buf)) {
1375 kfree(buf);
1376 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1377 node);
1378 if (!buf)
1379 goto err1;
1380 }
1381
1382 urb = usb_alloc_urb(0, GFP_KERNEL);
1383 if (!urb) {
1384 kfree(buf);
1385 goto err1;
1386 }
1387
1388 INIT_LIST_HEAD(&tp->rx_info[i].list);
1389 tp->rx_info[i].context = tp;
1390 tp->rx_info[i].urb = urb;
1391 tp->rx_info[i].buffer = buf;
1392 tp->rx_info[i].head = rx_agg_align(buf);
1393 }
1394
1395 for (i = 0; i < RTL8152_MAX_TX; i++) {
1396 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1397 if (!buf)
1398 goto err1;
1399
1400 if (buf != tx_agg_align(buf)) {
1401 kfree(buf);
1402 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1403 node);
1404 if (!buf)
1405 goto err1;
1406 }
1407
1408 urb = usb_alloc_urb(0, GFP_KERNEL);
1409 if (!urb) {
1410 kfree(buf);
1411 goto err1;
1412 }
1413
1414 INIT_LIST_HEAD(&tp->tx_info[i].list);
1415 tp->tx_info[i].context = tp;
1416 tp->tx_info[i].urb = urb;
1417 tp->tx_info[i].buffer = buf;
1418 tp->tx_info[i].head = tx_agg_align(buf);
1419
1420 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1421 }
1422
1423 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1424 if (!tp->intr_urb)
1425 goto err1;
1426
1427 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1428 if (!tp->intr_buff)
1429 goto err1;
1430
1431 tp->intr_interval = (int)ep_intr->desc.bInterval;
1432 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1433 tp->intr_buff, INTBUFSIZE, intr_callback,
1434 tp, tp->intr_interval);
1435
1436 return 0;
1437
1438 err1:
1439 free_all_mem(tp);
1440 return -ENOMEM;
1441 }
1442
1443 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1444 {
1445 struct tx_agg *agg = NULL;
1446 unsigned long flags;
1447
1448 if (list_empty(&tp->tx_free))
1449 return NULL;
1450
1451 spin_lock_irqsave(&tp->tx_lock, flags);
1452 if (!list_empty(&tp->tx_free)) {
1453 struct list_head *cursor;
1454
1455 cursor = tp->tx_free.next;
1456 list_del_init(cursor);
1457 agg = list_entry(cursor, struct tx_agg, list);
1458 }
1459 spin_unlock_irqrestore(&tp->tx_lock, flags);
1460
1461 return agg;
1462 }
1463
1464 /* r8152_csum_workaround()
1465 * The hw limites the value the transport offset. When the offset is out of the
1466 * range, calculate the checksum by sw.
1467 */
1468 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1469 struct sk_buff_head *list)
1470 {
1471 if (skb_shinfo(skb)->gso_size) {
1472 netdev_features_t features = tp->netdev->features;
1473 struct sk_buff_head seg_list;
1474 struct sk_buff *segs, *nskb;
1475
1476 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1477 segs = skb_gso_segment(skb, features);
1478 if (IS_ERR(segs) || !segs)
1479 goto drop;
1480
1481 __skb_queue_head_init(&seg_list);
1482
1483 do {
1484 nskb = segs;
1485 segs = segs->next;
1486 nskb->next = NULL;
1487 __skb_queue_tail(&seg_list, nskb);
1488 } while (segs);
1489
1490 skb_queue_splice(&seg_list, list);
1491 dev_kfree_skb(skb);
1492 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1493 if (skb_checksum_help(skb) < 0)
1494 goto drop;
1495
1496 __skb_queue_head(list, skb);
1497 } else {
1498 struct net_device_stats *stats;
1499
1500 drop:
1501 stats = &tp->netdev->stats;
1502 stats->tx_dropped++;
1503 dev_kfree_skb(skb);
1504 }
1505 }
1506
1507 /* msdn_giant_send_check()
1508 * According to the document of microsoft, the TCP Pseudo Header excludes the
1509 * packet length for IPv6 TCP large packets.
1510 */
1511 static int msdn_giant_send_check(struct sk_buff *skb)
1512 {
1513 const struct ipv6hdr *ipv6h;
1514 struct tcphdr *th;
1515 int ret;
1516
1517 ret = skb_cow_head(skb, 0);
1518 if (ret)
1519 return ret;
1520
1521 ipv6h = ipv6_hdr(skb);
1522 th = tcp_hdr(skb);
1523
1524 th->check = 0;
1525 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1526
1527 return ret;
1528 }
1529
1530 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1531 {
1532 if (skb_vlan_tag_present(skb)) {
1533 u32 opts2;
1534
1535 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1536 desc->opts2 |= cpu_to_le32(opts2);
1537 }
1538 }
1539
1540 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1541 {
1542 u32 opts2 = le32_to_cpu(desc->opts2);
1543
1544 if (opts2 & RX_VLAN_TAG)
1545 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1546 swab16(opts2 & 0xffff));
1547 }
1548
1549 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1550 struct sk_buff *skb, u32 len, u32 transport_offset)
1551 {
1552 u32 mss = skb_shinfo(skb)->gso_size;
1553 u32 opts1, opts2 = 0;
1554 int ret = TX_CSUM_SUCCESS;
1555
1556 WARN_ON_ONCE(len > TX_LEN_MAX);
1557
1558 opts1 = len | TX_FS | TX_LS;
1559
1560 if (mss) {
1561 if (transport_offset > GTTCPHO_MAX) {
1562 netif_warn(tp, tx_err, tp->netdev,
1563 "Invalid transport offset 0x%x for TSO\n",
1564 transport_offset);
1565 ret = TX_CSUM_TSO;
1566 goto unavailable;
1567 }
1568
1569 switch (vlan_get_protocol(skb)) {
1570 case htons(ETH_P_IP):
1571 opts1 |= GTSENDV4;
1572 break;
1573
1574 case htons(ETH_P_IPV6):
1575 if (msdn_giant_send_check(skb)) {
1576 ret = TX_CSUM_TSO;
1577 goto unavailable;
1578 }
1579 opts1 |= GTSENDV6;
1580 break;
1581
1582 default:
1583 WARN_ON_ONCE(1);
1584 break;
1585 }
1586
1587 opts1 |= transport_offset << GTTCPHO_SHIFT;
1588 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1589 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1590 u8 ip_protocol;
1591
1592 if (transport_offset > TCPHO_MAX) {
1593 netif_warn(tp, tx_err, tp->netdev,
1594 "Invalid transport offset 0x%x\n",
1595 transport_offset);
1596 ret = TX_CSUM_NONE;
1597 goto unavailable;
1598 }
1599
1600 switch (vlan_get_protocol(skb)) {
1601 case htons(ETH_P_IP):
1602 opts2 |= IPV4_CS;
1603 ip_protocol = ip_hdr(skb)->protocol;
1604 break;
1605
1606 case htons(ETH_P_IPV6):
1607 opts2 |= IPV6_CS;
1608 ip_protocol = ipv6_hdr(skb)->nexthdr;
1609 break;
1610
1611 default:
1612 ip_protocol = IPPROTO_RAW;
1613 break;
1614 }
1615
1616 if (ip_protocol == IPPROTO_TCP)
1617 opts2 |= TCP_CS;
1618 else if (ip_protocol == IPPROTO_UDP)
1619 opts2 |= UDP_CS;
1620 else
1621 WARN_ON_ONCE(1);
1622
1623 opts2 |= transport_offset << TCPHO_SHIFT;
1624 }
1625
1626 desc->opts2 = cpu_to_le32(opts2);
1627 desc->opts1 = cpu_to_le32(opts1);
1628
1629 unavailable:
1630 return ret;
1631 }
1632
1633 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1634 {
1635 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1636 int remain, ret;
1637 u8 *tx_data;
1638
1639 __skb_queue_head_init(&skb_head);
1640 spin_lock(&tx_queue->lock);
1641 skb_queue_splice_init(tx_queue, &skb_head);
1642 spin_unlock(&tx_queue->lock);
1643
1644 tx_data = agg->head;
1645 agg->skb_num = 0;
1646 agg->skb_len = 0;
1647 remain = agg_buf_sz;
1648
1649 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1650 struct tx_desc *tx_desc;
1651 struct sk_buff *skb;
1652 unsigned int len;
1653 u32 offset;
1654
1655 skb = __skb_dequeue(&skb_head);
1656 if (!skb)
1657 break;
1658
1659 len = skb->len + sizeof(*tx_desc);
1660
1661 if (len > remain) {
1662 __skb_queue_head(&skb_head, skb);
1663 break;
1664 }
1665
1666 tx_data = tx_agg_align(tx_data);
1667 tx_desc = (struct tx_desc *)tx_data;
1668
1669 offset = (u32)skb_transport_offset(skb);
1670
1671 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1672 r8152_csum_workaround(tp, skb, &skb_head);
1673 continue;
1674 }
1675
1676 rtl_tx_vlan_tag(tx_desc, skb);
1677
1678 tx_data += sizeof(*tx_desc);
1679
1680 len = skb->len;
1681 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1682 struct net_device_stats *stats = &tp->netdev->stats;
1683
1684 stats->tx_dropped++;
1685 dev_kfree_skb_any(skb);
1686 tx_data -= sizeof(*tx_desc);
1687 continue;
1688 }
1689
1690 tx_data += len;
1691 agg->skb_len += len;
1692 agg->skb_num++;
1693
1694 dev_kfree_skb_any(skb);
1695
1696 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1697 }
1698
1699 if (!skb_queue_empty(&skb_head)) {
1700 spin_lock(&tx_queue->lock);
1701 skb_queue_splice(&skb_head, tx_queue);
1702 spin_unlock(&tx_queue->lock);
1703 }
1704
1705 netif_tx_lock(tp->netdev);
1706
1707 if (netif_queue_stopped(tp->netdev) &&
1708 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1709 netif_wake_queue(tp->netdev);
1710
1711 netif_tx_unlock(tp->netdev);
1712
1713 ret = usb_autopm_get_interface_async(tp->intf);
1714 if (ret < 0)
1715 goto out_tx_fill;
1716
1717 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1718 agg->head, (int)(tx_data - (u8 *)agg->head),
1719 (usb_complete_t)write_bulk_callback, agg);
1720
1721 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1722 if (ret < 0)
1723 usb_autopm_put_interface_async(tp->intf);
1724
1725 out_tx_fill:
1726 return ret;
1727 }
1728
1729 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1730 {
1731 u8 checksum = CHECKSUM_NONE;
1732 u32 opts2, opts3;
1733
1734 if (tp->version == RTL_VER_01)
1735 goto return_result;
1736
1737 opts2 = le32_to_cpu(rx_desc->opts2);
1738 opts3 = le32_to_cpu(rx_desc->opts3);
1739
1740 if (opts2 & RD_IPV4_CS) {
1741 if (opts3 & IPF)
1742 checksum = CHECKSUM_NONE;
1743 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1744 checksum = CHECKSUM_NONE;
1745 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1746 checksum = CHECKSUM_NONE;
1747 else
1748 checksum = CHECKSUM_UNNECESSARY;
1749 } else if (RD_IPV6_CS) {
1750 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1751 checksum = CHECKSUM_UNNECESSARY;
1752 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1753 checksum = CHECKSUM_UNNECESSARY;
1754 }
1755
1756 return_result:
1757 return checksum;
1758 }
1759
1760 static int rx_bottom(struct r8152 *tp, int budget)
1761 {
1762 unsigned long flags;
1763 struct list_head *cursor, *next, rx_queue;
1764 int ret = 0, work_done = 0;
1765
1766 if (!skb_queue_empty(&tp->rx_queue)) {
1767 while (work_done < budget) {
1768 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1769 struct net_device *netdev = tp->netdev;
1770 struct net_device_stats *stats = &netdev->stats;
1771 unsigned int pkt_len;
1772
1773 if (!skb)
1774 break;
1775
1776 pkt_len = skb->len;
1777 napi_gro_receive(&tp->napi, skb);
1778 work_done++;
1779 stats->rx_packets++;
1780 stats->rx_bytes += pkt_len;
1781 }
1782 }
1783
1784 if (list_empty(&tp->rx_done))
1785 goto out1;
1786
1787 INIT_LIST_HEAD(&rx_queue);
1788 spin_lock_irqsave(&tp->rx_lock, flags);
1789 list_splice_init(&tp->rx_done, &rx_queue);
1790 spin_unlock_irqrestore(&tp->rx_lock, flags);
1791
1792 list_for_each_safe(cursor, next, &rx_queue) {
1793 struct rx_desc *rx_desc;
1794 struct rx_agg *agg;
1795 int len_used = 0;
1796 struct urb *urb;
1797 u8 *rx_data;
1798
1799 list_del_init(cursor);
1800
1801 agg = list_entry(cursor, struct rx_agg, list);
1802 urb = agg->urb;
1803 if (urb->actual_length < ETH_ZLEN)
1804 goto submit;
1805
1806 rx_desc = agg->head;
1807 rx_data = agg->head;
1808 len_used += sizeof(struct rx_desc);
1809
1810 while (urb->actual_length > len_used) {
1811 struct net_device *netdev = tp->netdev;
1812 struct net_device_stats *stats = &netdev->stats;
1813 unsigned int pkt_len;
1814 struct sk_buff *skb;
1815
1816 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1817 if (pkt_len < ETH_ZLEN)
1818 break;
1819
1820 len_used += pkt_len;
1821 if (urb->actual_length < len_used)
1822 break;
1823
1824 pkt_len -= CRC_SIZE;
1825 rx_data += sizeof(struct rx_desc);
1826
1827 skb = napi_alloc_skb(&tp->napi, pkt_len);
1828 if (!skb) {
1829 stats->rx_dropped++;
1830 goto find_next_rx;
1831 }
1832
1833 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1834 memcpy(skb->data, rx_data, pkt_len);
1835 skb_put(skb, pkt_len);
1836 skb->protocol = eth_type_trans(skb, netdev);
1837 rtl_rx_vlan_tag(rx_desc, skb);
1838 if (work_done < budget) {
1839 napi_gro_receive(&tp->napi, skb);
1840 work_done++;
1841 stats->rx_packets++;
1842 stats->rx_bytes += pkt_len;
1843 } else {
1844 __skb_queue_tail(&tp->rx_queue, skb);
1845 }
1846
1847 find_next_rx:
1848 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1849 rx_desc = (struct rx_desc *)rx_data;
1850 len_used = (int)(rx_data - (u8 *)agg->head);
1851 len_used += sizeof(struct rx_desc);
1852 }
1853
1854 submit:
1855 if (!ret) {
1856 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1857 } else {
1858 urb->actual_length = 0;
1859 list_add_tail(&agg->list, next);
1860 }
1861 }
1862
1863 if (!list_empty(&rx_queue)) {
1864 spin_lock_irqsave(&tp->rx_lock, flags);
1865 list_splice_tail(&rx_queue, &tp->rx_done);
1866 spin_unlock_irqrestore(&tp->rx_lock, flags);
1867 }
1868
1869 out1:
1870 return work_done;
1871 }
1872
1873 static void tx_bottom(struct r8152 *tp)
1874 {
1875 int res;
1876
1877 do {
1878 struct tx_agg *agg;
1879
1880 if (skb_queue_empty(&tp->tx_queue))
1881 break;
1882
1883 agg = r8152_get_tx_agg(tp);
1884 if (!agg)
1885 break;
1886
1887 res = r8152_tx_agg_fill(tp, agg);
1888 if (res) {
1889 struct net_device *netdev = tp->netdev;
1890
1891 if (res == -ENODEV) {
1892 set_bit(RTL8152_UNPLUG, &tp->flags);
1893 netif_device_detach(netdev);
1894 } else {
1895 struct net_device_stats *stats = &netdev->stats;
1896 unsigned long flags;
1897
1898 netif_warn(tp, tx_err, netdev,
1899 "failed tx_urb %d\n", res);
1900 stats->tx_dropped += agg->skb_num;
1901
1902 spin_lock_irqsave(&tp->tx_lock, flags);
1903 list_add_tail(&agg->list, &tp->tx_free);
1904 spin_unlock_irqrestore(&tp->tx_lock, flags);
1905 }
1906 }
1907 } while (res == 0);
1908 }
1909
1910 static void bottom_half(struct r8152 *tp)
1911 {
1912 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1913 return;
1914
1915 if (!test_bit(WORK_ENABLE, &tp->flags))
1916 return;
1917
1918 /* When link down, the driver would cancel all bulks. */
1919 /* This avoid the re-submitting bulk */
1920 if (!netif_carrier_ok(tp->netdev))
1921 return;
1922
1923 clear_bit(SCHEDULE_NAPI, &tp->flags);
1924
1925 tx_bottom(tp);
1926 }
1927
1928 static int r8152_poll(struct napi_struct *napi, int budget)
1929 {
1930 struct r8152 *tp = container_of(napi, struct r8152, napi);
1931 int work_done;
1932
1933 work_done = rx_bottom(tp, budget);
1934 bottom_half(tp);
1935
1936 if (work_done < budget) {
1937 napi_complete(napi);
1938 if (!list_empty(&tp->rx_done))
1939 napi_schedule(napi);
1940 }
1941
1942 return work_done;
1943 }
1944
1945 static
1946 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1947 {
1948 int ret;
1949
1950 /* The rx would be stopped, so skip submitting */
1951 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
1952 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
1953 return 0;
1954
1955 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1956 agg->head, agg_buf_sz,
1957 (usb_complete_t)read_bulk_callback, agg);
1958
1959 ret = usb_submit_urb(agg->urb, mem_flags);
1960 if (ret == -ENODEV) {
1961 set_bit(RTL8152_UNPLUG, &tp->flags);
1962 netif_device_detach(tp->netdev);
1963 } else if (ret) {
1964 struct urb *urb = agg->urb;
1965 unsigned long flags;
1966
1967 urb->actual_length = 0;
1968 spin_lock_irqsave(&tp->rx_lock, flags);
1969 list_add_tail(&agg->list, &tp->rx_done);
1970 spin_unlock_irqrestore(&tp->rx_lock, flags);
1971
1972 netif_err(tp, rx_err, tp->netdev,
1973 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
1974
1975 napi_schedule(&tp->napi);
1976 }
1977
1978 return ret;
1979 }
1980
1981 static void rtl_drop_queued_tx(struct r8152 *tp)
1982 {
1983 struct net_device_stats *stats = &tp->netdev->stats;
1984 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1985 struct sk_buff *skb;
1986
1987 if (skb_queue_empty(tx_queue))
1988 return;
1989
1990 __skb_queue_head_init(&skb_head);
1991 spin_lock_bh(&tx_queue->lock);
1992 skb_queue_splice_init(tx_queue, &skb_head);
1993 spin_unlock_bh(&tx_queue->lock);
1994
1995 while ((skb = __skb_dequeue(&skb_head))) {
1996 dev_kfree_skb(skb);
1997 stats->tx_dropped++;
1998 }
1999 }
2000
2001 static void rtl8152_tx_timeout(struct net_device *netdev)
2002 {
2003 struct r8152 *tp = netdev_priv(netdev);
2004
2005 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2006
2007 usb_queue_reset_device(tp->intf);
2008 }
2009
2010 static void rtl8152_set_rx_mode(struct net_device *netdev)
2011 {
2012 struct r8152 *tp = netdev_priv(netdev);
2013
2014 if (netif_carrier_ok(netdev)) {
2015 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2016 schedule_delayed_work(&tp->schedule, 0);
2017 }
2018 }
2019
2020 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2021 {
2022 struct r8152 *tp = netdev_priv(netdev);
2023 u32 mc_filter[2]; /* Multicast hash filter */
2024 __le32 tmp[2];
2025 u32 ocp_data;
2026
2027 netif_stop_queue(netdev);
2028 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2029 ocp_data &= ~RCR_ACPT_ALL;
2030 ocp_data |= RCR_AB | RCR_APM;
2031
2032 if (netdev->flags & IFF_PROMISC) {
2033 /* Unconditionally log net taps. */
2034 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2035 ocp_data |= RCR_AM | RCR_AAP;
2036 mc_filter[1] = 0xffffffff;
2037 mc_filter[0] = 0xffffffff;
2038 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2039 (netdev->flags & IFF_ALLMULTI)) {
2040 /* Too many to filter perfectly -- accept all multicasts. */
2041 ocp_data |= RCR_AM;
2042 mc_filter[1] = 0xffffffff;
2043 mc_filter[0] = 0xffffffff;
2044 } else {
2045 struct netdev_hw_addr *ha;
2046
2047 mc_filter[1] = 0;
2048 mc_filter[0] = 0;
2049 netdev_for_each_mc_addr(ha, netdev) {
2050 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2051
2052 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2053 ocp_data |= RCR_AM;
2054 }
2055 }
2056
2057 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2058 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2059
2060 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2061 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2062 netif_wake_queue(netdev);
2063 }
2064
2065 static netdev_features_t
2066 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2067 netdev_features_t features)
2068 {
2069 u32 mss = skb_shinfo(skb)->gso_size;
2070 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2071 int offset = skb_transport_offset(skb);
2072
2073 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2074 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2075 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2076 features &= ~NETIF_F_GSO_MASK;
2077
2078 return features;
2079 }
2080
2081 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2082 struct net_device *netdev)
2083 {
2084 struct r8152 *tp = netdev_priv(netdev);
2085
2086 skb_tx_timestamp(skb);
2087
2088 skb_queue_tail(&tp->tx_queue, skb);
2089
2090 if (!list_empty(&tp->tx_free)) {
2091 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2092 set_bit(SCHEDULE_NAPI, &tp->flags);
2093 schedule_delayed_work(&tp->schedule, 0);
2094 } else {
2095 usb_mark_last_busy(tp->udev);
2096 napi_schedule(&tp->napi);
2097 }
2098 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2099 netif_stop_queue(netdev);
2100 }
2101
2102 return NETDEV_TX_OK;
2103 }
2104
2105 static void r8152b_reset_packet_filter(struct r8152 *tp)
2106 {
2107 u32 ocp_data;
2108
2109 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2110 ocp_data &= ~FMC_FCR_MCU_EN;
2111 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2112 ocp_data |= FMC_FCR_MCU_EN;
2113 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2114 }
2115
2116 static void rtl8152_nic_reset(struct r8152 *tp)
2117 {
2118 int i;
2119
2120 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2121
2122 for (i = 0; i < 1000; i++) {
2123 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2124 break;
2125 usleep_range(100, 400);
2126 }
2127 }
2128
2129 static void set_tx_qlen(struct r8152 *tp)
2130 {
2131 struct net_device *netdev = tp->netdev;
2132
2133 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
2134 sizeof(struct tx_desc));
2135 }
2136
2137 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2138 {
2139 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2140 }
2141
2142 static void rtl_set_eee_plus(struct r8152 *tp)
2143 {
2144 u32 ocp_data;
2145 u8 speed;
2146
2147 speed = rtl8152_get_speed(tp);
2148 if (speed & _10bps) {
2149 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2150 ocp_data |= EEEP_CR_EEEP_TX;
2151 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2152 } else {
2153 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2154 ocp_data &= ~EEEP_CR_EEEP_TX;
2155 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2156 }
2157 }
2158
2159 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2160 {
2161 u32 ocp_data;
2162
2163 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2164 if (enable)
2165 ocp_data |= RXDY_GATED_EN;
2166 else
2167 ocp_data &= ~RXDY_GATED_EN;
2168 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2169 }
2170
2171 static int rtl_start_rx(struct r8152 *tp)
2172 {
2173 int i, ret = 0;
2174
2175 INIT_LIST_HEAD(&tp->rx_done);
2176 for (i = 0; i < RTL8152_MAX_RX; i++) {
2177 INIT_LIST_HEAD(&tp->rx_info[i].list);
2178 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2179 if (ret)
2180 break;
2181 }
2182
2183 if (ret && ++i < RTL8152_MAX_RX) {
2184 struct list_head rx_queue;
2185 unsigned long flags;
2186
2187 INIT_LIST_HEAD(&rx_queue);
2188
2189 do {
2190 struct rx_agg *agg = &tp->rx_info[i++];
2191 struct urb *urb = agg->urb;
2192
2193 urb->actual_length = 0;
2194 list_add_tail(&agg->list, &rx_queue);
2195 } while (i < RTL8152_MAX_RX);
2196
2197 spin_lock_irqsave(&tp->rx_lock, flags);
2198 list_splice_tail(&rx_queue, &tp->rx_done);
2199 spin_unlock_irqrestore(&tp->rx_lock, flags);
2200 }
2201
2202 return ret;
2203 }
2204
2205 static int rtl_stop_rx(struct r8152 *tp)
2206 {
2207 int i;
2208
2209 for (i = 0; i < RTL8152_MAX_RX; i++)
2210 usb_kill_urb(tp->rx_info[i].urb);
2211
2212 while (!skb_queue_empty(&tp->rx_queue))
2213 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2214
2215 return 0;
2216 }
2217
2218 static int rtl_enable(struct r8152 *tp)
2219 {
2220 u32 ocp_data;
2221
2222 r8152b_reset_packet_filter(tp);
2223
2224 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2225 ocp_data |= CR_RE | CR_TE;
2226 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2227
2228 rxdy_gated_en(tp, false);
2229
2230 return 0;
2231 }
2232
2233 static int rtl8152_enable(struct r8152 *tp)
2234 {
2235 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2236 return -ENODEV;
2237
2238 set_tx_qlen(tp);
2239 rtl_set_eee_plus(tp);
2240
2241 return rtl_enable(tp);
2242 }
2243
2244 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2245 {
2246 u32 ocp_data = tp->coalesce / 8;
2247
2248 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
2249 }
2250
2251 static void r8153_set_rx_early_size(struct r8152 *tp)
2252 {
2253 u32 mtu = tp->netdev->mtu;
2254 u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 8;
2255
2256 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
2257 }
2258
2259 static int rtl8153_enable(struct r8152 *tp)
2260 {
2261 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2262 return -ENODEV;
2263
2264 usb_disable_lpm(tp->udev);
2265 set_tx_qlen(tp);
2266 rtl_set_eee_plus(tp);
2267 r8153_set_rx_early_timeout(tp);
2268 r8153_set_rx_early_size(tp);
2269
2270 return rtl_enable(tp);
2271 }
2272
2273 static void rtl_disable(struct r8152 *tp)
2274 {
2275 u32 ocp_data;
2276 int i;
2277
2278 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2279 rtl_drop_queued_tx(tp);
2280 return;
2281 }
2282
2283 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2284 ocp_data &= ~RCR_ACPT_ALL;
2285 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2286
2287 rtl_drop_queued_tx(tp);
2288
2289 for (i = 0; i < RTL8152_MAX_TX; i++)
2290 usb_kill_urb(tp->tx_info[i].urb);
2291
2292 rxdy_gated_en(tp, true);
2293
2294 for (i = 0; i < 1000; i++) {
2295 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2296 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2297 break;
2298 usleep_range(1000, 2000);
2299 }
2300
2301 for (i = 0; i < 1000; i++) {
2302 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2303 break;
2304 usleep_range(1000, 2000);
2305 }
2306
2307 rtl_stop_rx(tp);
2308
2309 rtl8152_nic_reset(tp);
2310 }
2311
2312 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2313 {
2314 u32 ocp_data;
2315
2316 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2317 if (enable)
2318 ocp_data |= POWER_CUT;
2319 else
2320 ocp_data &= ~POWER_CUT;
2321 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2322
2323 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2324 ocp_data &= ~RESUME_INDICATE;
2325 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2326 }
2327
2328 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2329 {
2330 u32 ocp_data;
2331
2332 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2333 if (enable)
2334 ocp_data |= CPCR_RX_VLAN;
2335 else
2336 ocp_data &= ~CPCR_RX_VLAN;
2337 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2338 }
2339
2340 static int rtl8152_set_features(struct net_device *dev,
2341 netdev_features_t features)
2342 {
2343 netdev_features_t changed = features ^ dev->features;
2344 struct r8152 *tp = netdev_priv(dev);
2345 int ret;
2346
2347 ret = usb_autopm_get_interface(tp->intf);
2348 if (ret < 0)
2349 goto out;
2350
2351 mutex_lock(&tp->control);
2352
2353 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2354 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2355 rtl_rx_vlan_en(tp, true);
2356 else
2357 rtl_rx_vlan_en(tp, false);
2358 }
2359
2360 mutex_unlock(&tp->control);
2361
2362 usb_autopm_put_interface(tp->intf);
2363
2364 out:
2365 return ret;
2366 }
2367
2368 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2369
2370 static u32 __rtl_get_wol(struct r8152 *tp)
2371 {
2372 u32 ocp_data;
2373 u32 wolopts = 0;
2374
2375 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2376 if (ocp_data & LINK_ON_WAKE_EN)
2377 wolopts |= WAKE_PHY;
2378
2379 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2380 if (ocp_data & UWF_EN)
2381 wolopts |= WAKE_UCAST;
2382 if (ocp_data & BWF_EN)
2383 wolopts |= WAKE_BCAST;
2384 if (ocp_data & MWF_EN)
2385 wolopts |= WAKE_MCAST;
2386
2387 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2388 if (ocp_data & MAGIC_EN)
2389 wolopts |= WAKE_MAGIC;
2390
2391 return wolopts;
2392 }
2393
2394 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2395 {
2396 u32 ocp_data;
2397
2398 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2399
2400 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2401 ocp_data &= ~LINK_ON_WAKE_EN;
2402 if (wolopts & WAKE_PHY)
2403 ocp_data |= LINK_ON_WAKE_EN;
2404 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2405
2406 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2407 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2408 if (wolopts & WAKE_UCAST)
2409 ocp_data |= UWF_EN;
2410 if (wolopts & WAKE_BCAST)
2411 ocp_data |= BWF_EN;
2412 if (wolopts & WAKE_MCAST)
2413 ocp_data |= MWF_EN;
2414 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2415
2416 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2417
2418 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2419 ocp_data &= ~MAGIC_EN;
2420 if (wolopts & WAKE_MAGIC)
2421 ocp_data |= MAGIC_EN;
2422 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2423
2424 if (wolopts & WAKE_ANY)
2425 device_set_wakeup_enable(&tp->udev->dev, true);
2426 else
2427 device_set_wakeup_enable(&tp->udev->dev, false);
2428 }
2429
2430 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2431 {
2432 u8 u1u2[8];
2433
2434 if (enable)
2435 memset(u1u2, 0xff, sizeof(u1u2));
2436 else
2437 memset(u1u2, 0x00, sizeof(u1u2));
2438
2439 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2440 }
2441
2442 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2443 {
2444 u32 ocp_data;
2445
2446 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2447 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
2448 ocp_data |= U2P3_ENABLE;
2449 else
2450 ocp_data &= ~U2P3_ENABLE;
2451 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2452 }
2453
2454 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2455 {
2456 u32 ocp_data;
2457
2458 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2459 if (enable)
2460 ocp_data |= PWR_EN | PHASE2_EN;
2461 else
2462 ocp_data &= ~(PWR_EN | PHASE2_EN);
2463 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2464
2465 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2466 ocp_data &= ~PCUT_STATUS;
2467 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2468 }
2469
2470 static bool rtl_can_wakeup(struct r8152 *tp)
2471 {
2472 struct usb_device *udev = tp->udev;
2473
2474 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2475 }
2476
2477 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2478 {
2479 if (enable) {
2480 u32 ocp_data;
2481
2482 __rtl_set_wol(tp, WAKE_ANY);
2483
2484 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2485
2486 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2487 ocp_data |= LINK_OFF_WAKE_EN;
2488 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2489
2490 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2491 } else {
2492 u32 ocp_data;
2493
2494 __rtl_set_wol(tp, tp->saved_wolopts);
2495
2496 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2497
2498 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2499 ocp_data &= ~LINK_OFF_WAKE_EN;
2500 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2501
2502 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2503 }
2504 }
2505
2506 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2507 {
2508 rtl_runtime_suspend_enable(tp, enable);
2509
2510 if (enable) {
2511 r8153_u1u2en(tp, false);
2512 r8153_u2p3en(tp, false);
2513 } else {
2514 r8153_u2p3en(tp, true);
2515 r8153_u1u2en(tp, true);
2516 }
2517 }
2518
2519 static void r8153_teredo_off(struct r8152 *tp)
2520 {
2521 u32 ocp_data;
2522
2523 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2524 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2525 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2526
2527 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2528 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2529 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2530 }
2531
2532 static void rtl_reset_bmu(struct r8152 *tp)
2533 {
2534 u32 ocp_data;
2535
2536 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2537 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2538 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2539 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2540 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2541 }
2542
2543 static void r8152_aldps_en(struct r8152 *tp, bool enable)
2544 {
2545 if (enable) {
2546 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2547 LINKENA | DIS_SDSAVE);
2548 } else {
2549 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2550 DIS_SDSAVE);
2551 msleep(20);
2552 }
2553 }
2554
2555 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2556 {
2557 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2558 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2559 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2560 }
2561
2562 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2563 {
2564 u16 data;
2565
2566 r8152_mmd_indirect(tp, dev, reg);
2567 data = ocp_reg_read(tp, OCP_EEE_DATA);
2568 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2569
2570 return data;
2571 }
2572
2573 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2574 {
2575 r8152_mmd_indirect(tp, dev, reg);
2576 ocp_reg_write(tp, OCP_EEE_DATA, data);
2577 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2578 }
2579
2580 static void r8152_eee_en(struct r8152 *tp, bool enable)
2581 {
2582 u16 config1, config2, config3;
2583 u32 ocp_data;
2584
2585 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2586 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2587 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2588 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2589
2590 if (enable) {
2591 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2592 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2593 config1 |= sd_rise_time(1);
2594 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2595 config3 |= fast_snr(42);
2596 } else {
2597 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2598 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2599 RX_QUIET_EN);
2600 config1 |= sd_rise_time(7);
2601 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
2602 config3 |= fast_snr(511);
2603 }
2604
2605 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2606 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
2607 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
2608 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
2609 }
2610
2611 static void r8152b_enable_eee(struct r8152 *tp)
2612 {
2613 r8152_eee_en(tp, true);
2614 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
2615 }
2616
2617 static void r8152b_enable_fc(struct r8152 *tp)
2618 {
2619 u16 anar;
2620
2621 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2622 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2623 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2624 }
2625
2626 static void rtl8152_disable(struct r8152 *tp)
2627 {
2628 r8152_aldps_en(tp, false);
2629 rtl_disable(tp);
2630 r8152_aldps_en(tp, true);
2631 }
2632
2633 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2634 {
2635 r8152b_enable_eee(tp);
2636 r8152_aldps_en(tp, true);
2637 r8152b_enable_fc(tp);
2638
2639 set_bit(PHY_RESET, &tp->flags);
2640 }
2641
2642 static void r8152b_exit_oob(struct r8152 *tp)
2643 {
2644 u32 ocp_data;
2645 int i;
2646
2647 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2648 ocp_data &= ~RCR_ACPT_ALL;
2649 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2650
2651 rxdy_gated_en(tp, true);
2652 r8153_teredo_off(tp);
2653 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2654 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2655
2656 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2657 ocp_data &= ~NOW_IS_OOB;
2658 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2659
2660 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2661 ocp_data &= ~MCU_BORW_EN;
2662 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2663
2664 for (i = 0; i < 1000; i++) {
2665 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2666 if (ocp_data & LINK_LIST_READY)
2667 break;
2668 usleep_range(1000, 2000);
2669 }
2670
2671 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2672 ocp_data |= RE_INIT_LL;
2673 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2674
2675 for (i = 0; i < 1000; i++) {
2676 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2677 if (ocp_data & LINK_LIST_READY)
2678 break;
2679 usleep_range(1000, 2000);
2680 }
2681
2682 rtl8152_nic_reset(tp);
2683
2684 /* rx share fifo credit full threshold */
2685 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2686
2687 if (tp->udev->speed == USB_SPEED_FULL ||
2688 tp->udev->speed == USB_SPEED_LOW) {
2689 /* rx share fifo credit near full threshold */
2690 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2691 RXFIFO_THR2_FULL);
2692 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2693 RXFIFO_THR3_FULL);
2694 } else {
2695 /* rx share fifo credit near full threshold */
2696 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2697 RXFIFO_THR2_HIGH);
2698 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2699 RXFIFO_THR3_HIGH);
2700 }
2701
2702 /* TX share fifo free credit full threshold */
2703 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2704
2705 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2706 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2707 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2708 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2709
2710 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2711
2712 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2713
2714 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2715 ocp_data |= TCR0_AUTO_FIFO;
2716 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2717 }
2718
2719 static void r8152b_enter_oob(struct r8152 *tp)
2720 {
2721 u32 ocp_data;
2722 int i;
2723
2724 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2725 ocp_data &= ~NOW_IS_OOB;
2726 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2727
2728 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2729 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2730 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2731
2732 rtl_disable(tp);
2733
2734 for (i = 0; i < 1000; i++) {
2735 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2736 if (ocp_data & LINK_LIST_READY)
2737 break;
2738 usleep_range(1000, 2000);
2739 }
2740
2741 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2742 ocp_data |= RE_INIT_LL;
2743 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2744
2745 for (i = 0; i < 1000; i++) {
2746 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2747 if (ocp_data & LINK_LIST_READY)
2748 break;
2749 usleep_range(1000, 2000);
2750 }
2751
2752 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2753
2754 rtl_rx_vlan_en(tp, true);
2755
2756 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2757 ocp_data |= ALDPS_PROXY_MODE;
2758 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2759
2760 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2761 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2762 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2763
2764 rxdy_gated_en(tp, false);
2765
2766 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2767 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2768 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2769 }
2770
2771 static void r8153_aldps_en(struct r8152 *tp, bool enable)
2772 {
2773 u16 data;
2774
2775 data = ocp_reg_read(tp, OCP_POWER_CFG);
2776 if (enable) {
2777 data |= EN_ALDPS;
2778 ocp_reg_write(tp, OCP_POWER_CFG, data);
2779 } else {
2780 data &= ~EN_ALDPS;
2781 ocp_reg_write(tp, OCP_POWER_CFG, data);
2782 msleep(20);
2783 }
2784 }
2785
2786 static void r8153_eee_en(struct r8152 *tp, bool enable)
2787 {
2788 u32 ocp_data;
2789 u16 config;
2790
2791 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2792 config = ocp_reg_read(tp, OCP_EEE_CFG);
2793
2794 if (enable) {
2795 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2796 config |= EEE10_EN;
2797 } else {
2798 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2799 config &= ~EEE10_EN;
2800 }
2801
2802 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2803 ocp_reg_write(tp, OCP_EEE_CFG, config);
2804 }
2805
2806 static void r8153_hw_phy_cfg(struct r8152 *tp)
2807 {
2808 u32 ocp_data;
2809 u16 data;
2810
2811 /* disable ALDPS before updating the PHY parameters */
2812 r8153_aldps_en(tp, false);
2813
2814 /* disable EEE before updating the PHY parameters */
2815 r8153_eee_en(tp, false);
2816 ocp_reg_write(tp, OCP_EEE_ADV, 0);
2817
2818 if (tp->version == RTL_VER_03) {
2819 data = ocp_reg_read(tp, OCP_EEE_CFG);
2820 data &= ~CTAP_SHORT_EN;
2821 ocp_reg_write(tp, OCP_EEE_CFG, data);
2822 }
2823
2824 data = ocp_reg_read(tp, OCP_POWER_CFG);
2825 data |= EEE_CLKDIV_EN;
2826 ocp_reg_write(tp, OCP_POWER_CFG, data);
2827
2828 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2829 data |= EN_10M_BGOFF;
2830 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2831 data = ocp_reg_read(tp, OCP_POWER_CFG);
2832 data |= EN_10M_PLLOFF;
2833 ocp_reg_write(tp, OCP_POWER_CFG, data);
2834 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
2835
2836 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2837 ocp_data |= PFM_PWM_SWITCH;
2838 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2839
2840 /* Enable LPF corner auto tune */
2841 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
2842
2843 /* Adjust 10M Amplitude */
2844 sram_write(tp, SRAM_10M_AMP1, 0x00af);
2845 sram_write(tp, SRAM_10M_AMP2, 0x0208);
2846
2847 r8153_eee_en(tp, true);
2848 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
2849
2850 r8153_aldps_en(tp, true);
2851 r8152b_enable_fc(tp);
2852
2853 set_bit(PHY_RESET, &tp->flags);
2854 }
2855
2856 static void r8153_first_init(struct r8152 *tp)
2857 {
2858 u32 ocp_data;
2859 int i;
2860
2861 rxdy_gated_en(tp, true);
2862 r8153_teredo_off(tp);
2863
2864 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2865 ocp_data &= ~RCR_ACPT_ALL;
2866 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2867
2868 rtl8152_nic_reset(tp);
2869 rtl_reset_bmu(tp);
2870
2871 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2872 ocp_data &= ~NOW_IS_OOB;
2873 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2874
2875 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2876 ocp_data &= ~MCU_BORW_EN;
2877 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2878
2879 for (i = 0; i < 1000; i++) {
2880 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2881 if (ocp_data & LINK_LIST_READY)
2882 break;
2883 usleep_range(1000, 2000);
2884 }
2885
2886 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2887 ocp_data |= RE_INIT_LL;
2888 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2889
2890 for (i = 0; i < 1000; i++) {
2891 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2892 if (ocp_data & LINK_LIST_READY)
2893 break;
2894 usleep_range(1000, 2000);
2895 }
2896
2897 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2898
2899 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2900 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
2901
2902 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2903 ocp_data |= TCR0_AUTO_FIFO;
2904 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2905
2906 rtl8152_nic_reset(tp);
2907
2908 /* rx share fifo credit full threshold */
2909 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2910 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2911 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2912 /* TX share fifo free credit full threshold */
2913 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2914
2915 /* rx aggregation */
2916 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2917 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
2918 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2919 }
2920
2921 static void r8153_enter_oob(struct r8152 *tp)
2922 {
2923 u32 ocp_data;
2924 int i;
2925
2926 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2927 ocp_data &= ~NOW_IS_OOB;
2928 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2929
2930 rtl_disable(tp);
2931 rtl_reset_bmu(tp);
2932
2933 for (i = 0; i < 1000; i++) {
2934 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2935 if (ocp_data & LINK_LIST_READY)
2936 break;
2937 usleep_range(1000, 2000);
2938 }
2939
2940 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2941 ocp_data |= RE_INIT_LL;
2942 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2943
2944 for (i = 0; i < 1000; i++) {
2945 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2946 if (ocp_data & LINK_LIST_READY)
2947 break;
2948 usleep_range(1000, 2000);
2949 }
2950
2951 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2952
2953 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2954 ocp_data &= ~TEREDO_WAKE_MASK;
2955 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2956
2957 rtl_rx_vlan_en(tp, true);
2958
2959 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2960 ocp_data |= ALDPS_PROXY_MODE;
2961 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2962
2963 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2964 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2965 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2966
2967 rxdy_gated_en(tp, false);
2968
2969 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2970 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2971 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2972 }
2973
2974 static void rtl8153_disable(struct r8152 *tp)
2975 {
2976 r8153_aldps_en(tp, false);
2977 rtl_disable(tp);
2978 rtl_reset_bmu(tp);
2979 r8153_aldps_en(tp, true);
2980 usb_enable_lpm(tp->udev);
2981 }
2982
2983 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2984 {
2985 u16 bmcr, anar, gbcr;
2986 int ret = 0;
2987
2988 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2989 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2990 ADVERTISE_100HALF | ADVERTISE_100FULL);
2991 if (tp->mii.supports_gmii) {
2992 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2993 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2994 } else {
2995 gbcr = 0;
2996 }
2997
2998 if (autoneg == AUTONEG_DISABLE) {
2999 if (speed == SPEED_10) {
3000 bmcr = 0;
3001 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3002 } else if (speed == SPEED_100) {
3003 bmcr = BMCR_SPEED100;
3004 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3005 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3006 bmcr = BMCR_SPEED1000;
3007 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3008 } else {
3009 ret = -EINVAL;
3010 goto out;
3011 }
3012
3013 if (duplex == DUPLEX_FULL)
3014 bmcr |= BMCR_FULLDPLX;
3015 } else {
3016 if (speed == SPEED_10) {
3017 if (duplex == DUPLEX_FULL)
3018 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3019 else
3020 anar |= ADVERTISE_10HALF;
3021 } else if (speed == SPEED_100) {
3022 if (duplex == DUPLEX_FULL) {
3023 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3024 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3025 } else {
3026 anar |= ADVERTISE_10HALF;
3027 anar |= ADVERTISE_100HALF;
3028 }
3029 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3030 if (duplex == DUPLEX_FULL) {
3031 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3032 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3033 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3034 } else {
3035 anar |= ADVERTISE_10HALF;
3036 anar |= ADVERTISE_100HALF;
3037 gbcr |= ADVERTISE_1000HALF;
3038 }
3039 } else {
3040 ret = -EINVAL;
3041 goto out;
3042 }
3043
3044 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
3045 }
3046
3047 if (test_and_clear_bit(PHY_RESET, &tp->flags))
3048 bmcr |= BMCR_RESET;
3049
3050 if (tp->mii.supports_gmii)
3051 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
3052
3053 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3054 r8152_mdio_write(tp, MII_BMCR, bmcr);
3055
3056 if (bmcr & BMCR_RESET) {
3057 int i;
3058
3059 for (i = 0; i < 50; i++) {
3060 msleep(20);
3061 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3062 break;
3063 }
3064 }
3065
3066 out:
3067 return ret;
3068 }
3069
3070 static void rtl8152_up(struct r8152 *tp)
3071 {
3072 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3073 return;
3074
3075 r8152_aldps_en(tp, false);
3076 r8152b_exit_oob(tp);
3077 r8152_aldps_en(tp, true);
3078 }
3079
3080 static void rtl8152_down(struct r8152 *tp)
3081 {
3082 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3083 rtl_drop_queued_tx(tp);
3084 return;
3085 }
3086
3087 r8152_power_cut_en(tp, false);
3088 r8152_aldps_en(tp, false);
3089 r8152b_enter_oob(tp);
3090 r8152_aldps_en(tp, true);
3091 }
3092
3093 static void rtl8153_up(struct r8152 *tp)
3094 {
3095 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3096 return;
3097
3098 r8153_u1u2en(tp, false);
3099 r8153_aldps_en(tp, false);
3100 r8153_first_init(tp);
3101 r8153_aldps_en(tp, true);
3102 r8153_u2p3en(tp, true);
3103 r8153_u1u2en(tp, true);
3104 usb_enable_lpm(tp->udev);
3105 }
3106
3107 static void rtl8153_down(struct r8152 *tp)
3108 {
3109 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3110 rtl_drop_queued_tx(tp);
3111 return;
3112 }
3113
3114 r8153_u1u2en(tp, false);
3115 r8153_u2p3en(tp, false);
3116 r8153_power_cut_en(tp, false);
3117 r8153_aldps_en(tp, false);
3118 r8153_enter_oob(tp);
3119 r8153_aldps_en(tp, true);
3120 }
3121
3122 static bool rtl8152_in_nway(struct r8152 *tp)
3123 {
3124 u16 nway_state;
3125
3126 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3127 tp->ocp_base = 0x2000;
3128 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
3129 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3130
3131 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3132 if (nway_state & 0xc000)
3133 return false;
3134 else
3135 return true;
3136 }
3137
3138 static bool rtl8153_in_nway(struct r8152 *tp)
3139 {
3140 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3141
3142 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3143 return false;
3144 else
3145 return true;
3146 }
3147
3148 static void set_carrier(struct r8152 *tp)
3149 {
3150 struct net_device *netdev = tp->netdev;
3151 u8 speed;
3152
3153 speed = rtl8152_get_speed(tp);
3154
3155 if (speed & LINK_STATUS) {
3156 if (!netif_carrier_ok(netdev)) {
3157 tp->rtl_ops.enable(tp);
3158 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
3159 napi_disable(&tp->napi);
3160 netif_carrier_on(netdev);
3161 rtl_start_rx(tp);
3162 napi_enable(&tp->napi);
3163 }
3164 } else {
3165 if (netif_carrier_ok(netdev)) {
3166 netif_carrier_off(netdev);
3167 napi_disable(&tp->napi);
3168 tp->rtl_ops.disable(tp);
3169 napi_enable(&tp->napi);
3170 }
3171 }
3172 }
3173
3174 static void rtl_work_func_t(struct work_struct *work)
3175 {
3176 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3177
3178 /* If the device is unplugged or !netif_running(), the workqueue
3179 * doesn't need to wake the device, and could return directly.
3180 */
3181 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3182 return;
3183
3184 if (usb_autopm_get_interface(tp->intf) < 0)
3185 return;
3186
3187 if (!test_bit(WORK_ENABLE, &tp->flags))
3188 goto out1;
3189
3190 if (!mutex_trylock(&tp->control)) {
3191 schedule_delayed_work(&tp->schedule, 0);
3192 goto out1;
3193 }
3194
3195 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
3196 set_carrier(tp);
3197
3198 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
3199 _rtl8152_set_rx_mode(tp->netdev);
3200
3201 /* don't schedule napi before linking */
3202 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3203 netif_carrier_ok(tp->netdev))
3204 napi_schedule(&tp->napi);
3205
3206 mutex_unlock(&tp->control);
3207
3208 out1:
3209 usb_autopm_put_interface(tp->intf);
3210 }
3211
3212 static void rtl_hw_phy_work_func_t(struct work_struct *work)
3213 {
3214 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3215
3216 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3217 return;
3218
3219 if (usb_autopm_get_interface(tp->intf) < 0)
3220 return;
3221
3222 mutex_lock(&tp->control);
3223
3224 tp->rtl_ops.hw_phy_cfg(tp);
3225
3226 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
3227
3228 mutex_unlock(&tp->control);
3229
3230 usb_autopm_put_interface(tp->intf);
3231 }
3232
3233 #ifdef CONFIG_PM_SLEEP
3234 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3235 void *data)
3236 {
3237 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3238
3239 switch (action) {
3240 case PM_HIBERNATION_PREPARE:
3241 case PM_SUSPEND_PREPARE:
3242 usb_autopm_get_interface(tp->intf);
3243 break;
3244
3245 case PM_POST_HIBERNATION:
3246 case PM_POST_SUSPEND:
3247 usb_autopm_put_interface(tp->intf);
3248 break;
3249
3250 case PM_POST_RESTORE:
3251 case PM_RESTORE_PREPARE:
3252 default:
3253 break;
3254 }
3255
3256 return NOTIFY_DONE;
3257 }
3258 #endif
3259
3260 static int rtl8152_open(struct net_device *netdev)
3261 {
3262 struct r8152 *tp = netdev_priv(netdev);
3263 int res = 0;
3264
3265 res = alloc_all_mem(tp);
3266 if (res)
3267 goto out;
3268
3269 res = usb_autopm_get_interface(tp->intf);
3270 if (res < 0) {
3271 free_all_mem(tp);
3272 goto out;
3273 }
3274
3275 mutex_lock(&tp->control);
3276
3277 tp->rtl_ops.up(tp);
3278
3279 netif_carrier_off(netdev);
3280 netif_start_queue(netdev);
3281 set_bit(WORK_ENABLE, &tp->flags);
3282
3283 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3284 if (res) {
3285 if (res == -ENODEV)
3286 netif_device_detach(tp->netdev);
3287 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3288 res);
3289 free_all_mem(tp);
3290 } else {
3291 napi_enable(&tp->napi);
3292 }
3293
3294 mutex_unlock(&tp->control);
3295
3296 usb_autopm_put_interface(tp->intf);
3297 #ifdef CONFIG_PM_SLEEP
3298 tp->pm_notifier.notifier_call = rtl_notifier;
3299 register_pm_notifier(&tp->pm_notifier);
3300 #endif
3301
3302 out:
3303 return res;
3304 }
3305
3306 static int rtl8152_close(struct net_device *netdev)
3307 {
3308 struct r8152 *tp = netdev_priv(netdev);
3309 int res = 0;
3310
3311 #ifdef CONFIG_PM_SLEEP
3312 unregister_pm_notifier(&tp->pm_notifier);
3313 #endif
3314 napi_disable(&tp->napi);
3315 clear_bit(WORK_ENABLE, &tp->flags);
3316 usb_kill_urb(tp->intr_urb);
3317 cancel_delayed_work_sync(&tp->schedule);
3318 netif_stop_queue(netdev);
3319
3320 res = usb_autopm_get_interface(tp->intf);
3321 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3322 rtl_drop_queued_tx(tp);
3323 rtl_stop_rx(tp);
3324 } else {
3325 mutex_lock(&tp->control);
3326
3327 tp->rtl_ops.down(tp);
3328
3329 mutex_unlock(&tp->control);
3330
3331 usb_autopm_put_interface(tp->intf);
3332 }
3333
3334 free_all_mem(tp);
3335
3336 return res;
3337 }
3338
3339 static void rtl_tally_reset(struct r8152 *tp)
3340 {
3341 u32 ocp_data;
3342
3343 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3344 ocp_data |= TALLY_RESET;
3345 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3346 }
3347
3348 static void r8152b_init(struct r8152 *tp)
3349 {
3350 u32 ocp_data;
3351 u16 data;
3352
3353 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3354 return;
3355
3356 data = r8152_mdio_read(tp, MII_BMCR);
3357 if (data & BMCR_PDOWN) {
3358 data &= ~BMCR_PDOWN;
3359 r8152_mdio_write(tp, MII_BMCR, data);
3360 }
3361
3362 r8152_aldps_en(tp, false);
3363
3364 if (tp->version == RTL_VER_01) {
3365 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3366 ocp_data &= ~LED_MODE_MASK;
3367 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3368 }
3369
3370 r8152_power_cut_en(tp, false);
3371
3372 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3373 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3374 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3375 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3376 ocp_data &= ~MCU_CLK_RATIO_MASK;
3377 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3378 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3379 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3380 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3381 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3382
3383 rtl_tally_reset(tp);
3384
3385 /* enable rx aggregation */
3386 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3387 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
3388 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3389 }
3390
3391 static void r8153_init(struct r8152 *tp)
3392 {
3393 u32 ocp_data;
3394 u16 data;
3395 int i;
3396
3397 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3398 return;
3399
3400 r8153_u1u2en(tp, false);
3401
3402 for (i = 0; i < 500; i++) {
3403 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3404 AUTOLOAD_DONE)
3405 break;
3406 msleep(20);
3407 }
3408
3409 for (i = 0; i < 500; i++) {
3410 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3411 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3412 break;
3413 msleep(20);
3414 }
3415
3416 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
3417 tp->version == RTL_VER_05)
3418 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
3419
3420 data = r8152_mdio_read(tp, MII_BMCR);
3421 if (data & BMCR_PDOWN) {
3422 data &= ~BMCR_PDOWN;
3423 r8152_mdio_write(tp, MII_BMCR, data);
3424 }
3425
3426 for (i = 0; i < 500; i++) {
3427 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3428 if (ocp_data == PHY_STAT_LAN_ON)
3429 break;
3430 msleep(20);
3431 }
3432
3433 usb_disable_lpm(tp->udev);
3434 r8153_u2p3en(tp, false);
3435
3436 if (tp->version == RTL_VER_04) {
3437 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
3438 ocp_data &= ~pwd_dn_scale_mask;
3439 ocp_data |= pwd_dn_scale(96);
3440 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
3441
3442 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
3443 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
3444 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
3445 } else if (tp->version == RTL_VER_05) {
3446 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
3447 ocp_data &= ~ECM_ALDPS;
3448 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
3449
3450 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3451 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3452 ocp_data &= ~DYNAMIC_BURST;
3453 else
3454 ocp_data |= DYNAMIC_BURST;
3455 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3456 } else if (tp->version == RTL_VER_06) {
3457 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3458 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3459 ocp_data &= ~DYNAMIC_BURST;
3460 else
3461 ocp_data |= DYNAMIC_BURST;
3462 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3463 }
3464
3465 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
3466 ocp_data |= EP4_FULL_FC;
3467 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
3468
3469 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3470 ocp_data &= ~TIMER11_EN;
3471 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3472
3473 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3474 ocp_data &= ~LED_MODE_MASK;
3475 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3476
3477 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
3478 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
3479 ocp_data |= LPM_TIMER_500MS;
3480 else
3481 ocp_data |= LPM_TIMER_500US;
3482 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3483
3484 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3485 ocp_data &= ~SEN_VAL_MASK;
3486 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3487 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3488
3489 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
3490
3491 r8153_power_cut_en(tp, false);
3492 r8153_u1u2en(tp, true);
3493
3494 /* MAC clock speed down */
3495 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
3496 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
3497 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
3498 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
3499
3500 rtl_tally_reset(tp);
3501 r8153_u2p3en(tp, true);
3502 }
3503
3504 static int rtl8152_pre_reset(struct usb_interface *intf)
3505 {
3506 struct r8152 *tp = usb_get_intfdata(intf);
3507 struct net_device *netdev;
3508
3509 if (!tp)
3510 return 0;
3511
3512 netdev = tp->netdev;
3513 if (!netif_running(netdev))
3514 return 0;
3515
3516 napi_disable(&tp->napi);
3517 clear_bit(WORK_ENABLE, &tp->flags);
3518 usb_kill_urb(tp->intr_urb);
3519 cancel_delayed_work_sync(&tp->schedule);
3520 if (netif_carrier_ok(netdev)) {
3521 netif_stop_queue(netdev);
3522 mutex_lock(&tp->control);
3523 tp->rtl_ops.disable(tp);
3524 mutex_unlock(&tp->control);
3525 }
3526
3527 return 0;
3528 }
3529
3530 static int rtl8152_post_reset(struct usb_interface *intf)
3531 {
3532 struct r8152 *tp = usb_get_intfdata(intf);
3533 struct net_device *netdev;
3534
3535 if (!tp)
3536 return 0;
3537
3538 netdev = tp->netdev;
3539 if (!netif_running(netdev))
3540 return 0;
3541
3542 set_bit(WORK_ENABLE, &tp->flags);
3543 if (netif_carrier_ok(netdev)) {
3544 mutex_lock(&tp->control);
3545 tp->rtl_ops.enable(tp);
3546 rtl8152_set_rx_mode(netdev);
3547 mutex_unlock(&tp->control);
3548 netif_wake_queue(netdev);
3549 }
3550
3551 napi_enable(&tp->napi);
3552
3553 return 0;
3554 }
3555
3556 static bool delay_autosuspend(struct r8152 *tp)
3557 {
3558 bool sw_linking = !!netif_carrier_ok(tp->netdev);
3559 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
3560
3561 /* This means a linking change occurs and the driver doesn't detect it,
3562 * yet. If the driver has disabled tx/rx and hw is linking on, the
3563 * device wouldn't wake up by receiving any packet.
3564 */
3565 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
3566 return true;
3567
3568 /* If the linking down is occurred by nway, the device may miss the
3569 * linking change event. And it wouldn't wake when linking on.
3570 */
3571 if (!sw_linking && tp->rtl_ops.in_nway(tp))
3572 return true;
3573 else
3574 return false;
3575 }
3576
3577 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3578 {
3579 struct r8152 *tp = usb_get_intfdata(intf);
3580 struct net_device *netdev = tp->netdev;
3581 int ret = 0;
3582
3583 mutex_lock(&tp->control);
3584
3585 if (PMSG_IS_AUTO(message)) {
3586 if (netif_running(netdev) && delay_autosuspend(tp)) {
3587 ret = -EBUSY;
3588 goto out1;
3589 }
3590
3591 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3592 } else {
3593 netif_device_detach(netdev);
3594 }
3595
3596 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
3597 clear_bit(WORK_ENABLE, &tp->flags);
3598 usb_kill_urb(tp->intr_urb);
3599 napi_disable(&tp->napi);
3600 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3601 rtl_stop_rx(tp);
3602 tp->rtl_ops.autosuspend_en(tp, true);
3603 } else {
3604 cancel_delayed_work_sync(&tp->schedule);
3605 tp->rtl_ops.down(tp);
3606 }
3607 napi_enable(&tp->napi);
3608 }
3609 out1:
3610 mutex_unlock(&tp->control);
3611
3612 return ret;
3613 }
3614
3615 static int rtl8152_resume(struct usb_interface *intf)
3616 {
3617 struct r8152 *tp = usb_get_intfdata(intf);
3618
3619 mutex_lock(&tp->control);
3620
3621 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3622 tp->rtl_ops.init(tp);
3623 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
3624 netif_device_attach(tp->netdev);
3625 }
3626
3627 if (netif_running(tp->netdev) && tp->netdev->flags & IFF_UP) {
3628 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3629 tp->rtl_ops.autosuspend_en(tp, false);
3630 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3631 napi_disable(&tp->napi);
3632 set_bit(WORK_ENABLE, &tp->flags);
3633 if (netif_carrier_ok(tp->netdev))
3634 rtl_start_rx(tp);
3635 napi_enable(&tp->napi);
3636 } else {
3637 tp->rtl_ops.up(tp);
3638 netif_carrier_off(tp->netdev);
3639 set_bit(WORK_ENABLE, &tp->flags);
3640 }
3641 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3642 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3643 if (tp->netdev->flags & IFF_UP)
3644 tp->rtl_ops.autosuspend_en(tp, false);
3645 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3646 }
3647
3648 mutex_unlock(&tp->control);
3649
3650 return 0;
3651 }
3652
3653 static int rtl8152_reset_resume(struct usb_interface *intf)
3654 {
3655 struct r8152 *tp = usb_get_intfdata(intf);
3656
3657 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3658 return rtl8152_resume(intf);
3659 }
3660
3661 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3662 {
3663 struct r8152 *tp = netdev_priv(dev);
3664
3665 if (usb_autopm_get_interface(tp->intf) < 0)
3666 return;
3667
3668 if (!rtl_can_wakeup(tp)) {
3669 wol->supported = 0;
3670 wol->wolopts = 0;
3671 } else {
3672 mutex_lock(&tp->control);
3673 wol->supported = WAKE_ANY;
3674 wol->wolopts = __rtl_get_wol(tp);
3675 mutex_unlock(&tp->control);
3676 }
3677
3678 usb_autopm_put_interface(tp->intf);
3679 }
3680
3681 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3682 {
3683 struct r8152 *tp = netdev_priv(dev);
3684 int ret;
3685
3686 if (!rtl_can_wakeup(tp))
3687 return -EOPNOTSUPP;
3688
3689 ret = usb_autopm_get_interface(tp->intf);
3690 if (ret < 0)
3691 goto out_set_wol;
3692
3693 mutex_lock(&tp->control);
3694
3695 __rtl_set_wol(tp, wol->wolopts);
3696 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3697
3698 mutex_unlock(&tp->control);
3699
3700 usb_autopm_put_interface(tp->intf);
3701
3702 out_set_wol:
3703 return ret;
3704 }
3705
3706 static u32 rtl8152_get_msglevel(struct net_device *dev)
3707 {
3708 struct r8152 *tp = netdev_priv(dev);
3709
3710 return tp->msg_enable;
3711 }
3712
3713 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3714 {
3715 struct r8152 *tp = netdev_priv(dev);
3716
3717 tp->msg_enable = value;
3718 }
3719
3720 static void rtl8152_get_drvinfo(struct net_device *netdev,
3721 struct ethtool_drvinfo *info)
3722 {
3723 struct r8152 *tp = netdev_priv(netdev);
3724
3725 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3726 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3727 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3728 }
3729
3730 static
3731 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3732 {
3733 struct r8152 *tp = netdev_priv(netdev);
3734 int ret;
3735
3736 if (!tp->mii.mdio_read)
3737 return -EOPNOTSUPP;
3738
3739 ret = usb_autopm_get_interface(tp->intf);
3740 if (ret < 0)
3741 goto out;
3742
3743 mutex_lock(&tp->control);
3744
3745 ret = mii_ethtool_gset(&tp->mii, cmd);
3746
3747 mutex_unlock(&tp->control);
3748
3749 usb_autopm_put_interface(tp->intf);
3750
3751 out:
3752 return ret;
3753 }
3754
3755 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3756 {
3757 struct r8152 *tp = netdev_priv(dev);
3758 int ret;
3759
3760 ret = usb_autopm_get_interface(tp->intf);
3761 if (ret < 0)
3762 goto out;
3763
3764 mutex_lock(&tp->control);
3765
3766 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3767 if (!ret) {
3768 tp->autoneg = cmd->autoneg;
3769 tp->speed = cmd->speed;
3770 tp->duplex = cmd->duplex;
3771 }
3772
3773 mutex_unlock(&tp->control);
3774
3775 usb_autopm_put_interface(tp->intf);
3776
3777 out:
3778 return ret;
3779 }
3780
3781 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3782 "tx_packets",
3783 "rx_packets",
3784 "tx_errors",
3785 "rx_errors",
3786 "rx_missed",
3787 "align_errors",
3788 "tx_single_collisions",
3789 "tx_multi_collisions",
3790 "rx_unicast",
3791 "rx_broadcast",
3792 "rx_multicast",
3793 "tx_aborted",
3794 "tx_underrun",
3795 };
3796
3797 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3798 {
3799 switch (sset) {
3800 case ETH_SS_STATS:
3801 return ARRAY_SIZE(rtl8152_gstrings);
3802 default:
3803 return -EOPNOTSUPP;
3804 }
3805 }
3806
3807 static void rtl8152_get_ethtool_stats(struct net_device *dev,
3808 struct ethtool_stats *stats, u64 *data)
3809 {
3810 struct r8152 *tp = netdev_priv(dev);
3811 struct tally_counter tally;
3812
3813 if (usb_autopm_get_interface(tp->intf) < 0)
3814 return;
3815
3816 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3817
3818 usb_autopm_put_interface(tp->intf);
3819
3820 data[0] = le64_to_cpu(tally.tx_packets);
3821 data[1] = le64_to_cpu(tally.rx_packets);
3822 data[2] = le64_to_cpu(tally.tx_errors);
3823 data[3] = le32_to_cpu(tally.rx_errors);
3824 data[4] = le16_to_cpu(tally.rx_missed);
3825 data[5] = le16_to_cpu(tally.align_errors);
3826 data[6] = le32_to_cpu(tally.tx_one_collision);
3827 data[7] = le32_to_cpu(tally.tx_multi_collision);
3828 data[8] = le64_to_cpu(tally.rx_unicast);
3829 data[9] = le64_to_cpu(tally.rx_broadcast);
3830 data[10] = le32_to_cpu(tally.rx_multicast);
3831 data[11] = le16_to_cpu(tally.tx_aborted);
3832 data[12] = le16_to_cpu(tally.tx_underrun);
3833 }
3834
3835 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3836 {
3837 switch (stringset) {
3838 case ETH_SS_STATS:
3839 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3840 break;
3841 }
3842 }
3843
3844 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3845 {
3846 u32 ocp_data, lp, adv, supported = 0;
3847 u16 val;
3848
3849 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3850 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3851
3852 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3853 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3854
3855 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3856 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3857
3858 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3859 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3860
3861 eee->eee_enabled = !!ocp_data;
3862 eee->eee_active = !!(supported & adv & lp);
3863 eee->supported = supported;
3864 eee->advertised = adv;
3865 eee->lp_advertised = lp;
3866
3867 return 0;
3868 }
3869
3870 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3871 {
3872 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3873
3874 r8152_eee_en(tp, eee->eee_enabled);
3875
3876 if (!eee->eee_enabled)
3877 val = 0;
3878
3879 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3880
3881 return 0;
3882 }
3883
3884 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3885 {
3886 u32 ocp_data, lp, adv, supported = 0;
3887 u16 val;
3888
3889 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3890 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3891
3892 val = ocp_reg_read(tp, OCP_EEE_ADV);
3893 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3894
3895 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3896 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3897
3898 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3899 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3900
3901 eee->eee_enabled = !!ocp_data;
3902 eee->eee_active = !!(supported & adv & lp);
3903 eee->supported = supported;
3904 eee->advertised = adv;
3905 eee->lp_advertised = lp;
3906
3907 return 0;
3908 }
3909
3910 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3911 {
3912 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3913
3914 r8153_eee_en(tp, eee->eee_enabled);
3915
3916 if (!eee->eee_enabled)
3917 val = 0;
3918
3919 ocp_reg_write(tp, OCP_EEE_ADV, val);
3920
3921 return 0;
3922 }
3923
3924 static int
3925 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3926 {
3927 struct r8152 *tp = netdev_priv(net);
3928 int ret;
3929
3930 ret = usb_autopm_get_interface(tp->intf);
3931 if (ret < 0)
3932 goto out;
3933
3934 mutex_lock(&tp->control);
3935
3936 ret = tp->rtl_ops.eee_get(tp, edata);
3937
3938 mutex_unlock(&tp->control);
3939
3940 usb_autopm_put_interface(tp->intf);
3941
3942 out:
3943 return ret;
3944 }
3945
3946 static int
3947 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3948 {
3949 struct r8152 *tp = netdev_priv(net);
3950 int ret;
3951
3952 ret = usb_autopm_get_interface(tp->intf);
3953 if (ret < 0)
3954 goto out;
3955
3956 mutex_lock(&tp->control);
3957
3958 ret = tp->rtl_ops.eee_set(tp, edata);
3959 if (!ret)
3960 ret = mii_nway_restart(&tp->mii);
3961
3962 mutex_unlock(&tp->control);
3963
3964 usb_autopm_put_interface(tp->intf);
3965
3966 out:
3967 return ret;
3968 }
3969
3970 static int rtl8152_nway_reset(struct net_device *dev)
3971 {
3972 struct r8152 *tp = netdev_priv(dev);
3973 int ret;
3974
3975 ret = usb_autopm_get_interface(tp->intf);
3976 if (ret < 0)
3977 goto out;
3978
3979 mutex_lock(&tp->control);
3980
3981 ret = mii_nway_restart(&tp->mii);
3982
3983 mutex_unlock(&tp->control);
3984
3985 usb_autopm_put_interface(tp->intf);
3986
3987 out:
3988 return ret;
3989 }
3990
3991 static int rtl8152_get_coalesce(struct net_device *netdev,
3992 struct ethtool_coalesce *coalesce)
3993 {
3994 struct r8152 *tp = netdev_priv(netdev);
3995
3996 switch (tp->version) {
3997 case RTL_VER_01:
3998 case RTL_VER_02:
3999 return -EOPNOTSUPP;
4000 default:
4001 break;
4002 }
4003
4004 coalesce->rx_coalesce_usecs = tp->coalesce;
4005
4006 return 0;
4007 }
4008
4009 static int rtl8152_set_coalesce(struct net_device *netdev,
4010 struct ethtool_coalesce *coalesce)
4011 {
4012 struct r8152 *tp = netdev_priv(netdev);
4013 int ret;
4014
4015 switch (tp->version) {
4016 case RTL_VER_01:
4017 case RTL_VER_02:
4018 return -EOPNOTSUPP;
4019 default:
4020 break;
4021 }
4022
4023 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4024 return -EINVAL;
4025
4026 ret = usb_autopm_get_interface(tp->intf);
4027 if (ret < 0)
4028 return ret;
4029
4030 mutex_lock(&tp->control);
4031
4032 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4033 tp->coalesce = coalesce->rx_coalesce_usecs;
4034
4035 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
4036 r8153_set_rx_early_timeout(tp);
4037 }
4038
4039 mutex_unlock(&tp->control);
4040
4041 usb_autopm_put_interface(tp->intf);
4042
4043 return ret;
4044 }
4045
4046 static struct ethtool_ops ops = {
4047 .get_drvinfo = rtl8152_get_drvinfo,
4048 .get_settings = rtl8152_get_settings,
4049 .set_settings = rtl8152_set_settings,
4050 .get_link = ethtool_op_get_link,
4051 .nway_reset = rtl8152_nway_reset,
4052 .get_msglevel = rtl8152_get_msglevel,
4053 .set_msglevel = rtl8152_set_msglevel,
4054 .get_wol = rtl8152_get_wol,
4055 .set_wol = rtl8152_set_wol,
4056 .get_strings = rtl8152_get_strings,
4057 .get_sset_count = rtl8152_get_sset_count,
4058 .get_ethtool_stats = rtl8152_get_ethtool_stats,
4059 .get_coalesce = rtl8152_get_coalesce,
4060 .set_coalesce = rtl8152_set_coalesce,
4061 .get_eee = rtl_ethtool_get_eee,
4062 .set_eee = rtl_ethtool_set_eee,
4063 };
4064
4065 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4066 {
4067 struct r8152 *tp = netdev_priv(netdev);
4068 struct mii_ioctl_data *data = if_mii(rq);
4069 int res;
4070
4071 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4072 return -ENODEV;
4073
4074 res = usb_autopm_get_interface(tp->intf);
4075 if (res < 0)
4076 goto out;
4077
4078 switch (cmd) {
4079 case SIOCGMIIPHY:
4080 data->phy_id = R8152_PHY_ID; /* Internal PHY */
4081 break;
4082
4083 case SIOCGMIIREG:
4084 mutex_lock(&tp->control);
4085 data->val_out = r8152_mdio_read(tp, data->reg_num);
4086 mutex_unlock(&tp->control);
4087 break;
4088
4089 case SIOCSMIIREG:
4090 if (!capable(CAP_NET_ADMIN)) {
4091 res = -EPERM;
4092 break;
4093 }
4094 mutex_lock(&tp->control);
4095 r8152_mdio_write(tp, data->reg_num, data->val_in);
4096 mutex_unlock(&tp->control);
4097 break;
4098
4099 default:
4100 res = -EOPNOTSUPP;
4101 }
4102
4103 usb_autopm_put_interface(tp->intf);
4104
4105 out:
4106 return res;
4107 }
4108
4109 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4110 {
4111 struct r8152 *tp = netdev_priv(dev);
4112 int ret;
4113
4114 switch (tp->version) {
4115 case RTL_VER_01:
4116 case RTL_VER_02:
4117 return eth_change_mtu(dev, new_mtu);
4118 default:
4119 break;
4120 }
4121
4122 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
4123 return -EINVAL;
4124
4125 ret = usb_autopm_get_interface(tp->intf);
4126 if (ret < 0)
4127 return ret;
4128
4129 mutex_lock(&tp->control);
4130
4131 dev->mtu = new_mtu;
4132
4133 if (netif_running(dev) && netif_carrier_ok(dev))
4134 r8153_set_rx_early_size(tp);
4135
4136 mutex_unlock(&tp->control);
4137
4138 usb_autopm_put_interface(tp->intf);
4139
4140 return ret;
4141 }
4142
4143 static const struct net_device_ops rtl8152_netdev_ops = {
4144 .ndo_open = rtl8152_open,
4145 .ndo_stop = rtl8152_close,
4146 .ndo_do_ioctl = rtl8152_ioctl,
4147 .ndo_start_xmit = rtl8152_start_xmit,
4148 .ndo_tx_timeout = rtl8152_tx_timeout,
4149 .ndo_set_features = rtl8152_set_features,
4150 .ndo_set_rx_mode = rtl8152_set_rx_mode,
4151 .ndo_set_mac_address = rtl8152_set_mac_address,
4152 .ndo_change_mtu = rtl8152_change_mtu,
4153 .ndo_validate_addr = eth_validate_addr,
4154 .ndo_features_check = rtl8152_features_check,
4155 };
4156
4157 static void r8152b_get_version(struct r8152 *tp)
4158 {
4159 u32 ocp_data;
4160 u16 version;
4161
4162 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
4163 version = (u16)(ocp_data & VERSION_MASK);
4164
4165 switch (version) {
4166 case 0x4c00:
4167 tp->version = RTL_VER_01;
4168 break;
4169 case 0x4c10:
4170 tp->version = RTL_VER_02;
4171 break;
4172 case 0x5c00:
4173 tp->version = RTL_VER_03;
4174 tp->mii.supports_gmii = 1;
4175 break;
4176 case 0x5c10:
4177 tp->version = RTL_VER_04;
4178 tp->mii.supports_gmii = 1;
4179 break;
4180 case 0x5c20:
4181 tp->version = RTL_VER_05;
4182 tp->mii.supports_gmii = 1;
4183 break;
4184 case 0x5c30:
4185 tp->version = RTL_VER_06;
4186 tp->mii.supports_gmii = 1;
4187 break;
4188 default:
4189 netif_info(tp, probe, tp->netdev,
4190 "Unknown version 0x%04x\n", version);
4191 break;
4192 }
4193 }
4194
4195 static void rtl8152_unload(struct r8152 *tp)
4196 {
4197 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4198 return;
4199
4200 if (tp->version != RTL_VER_01)
4201 r8152_power_cut_en(tp, true);
4202 }
4203
4204 static void rtl8153_unload(struct r8152 *tp)
4205 {
4206 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4207 return;
4208
4209 r8153_power_cut_en(tp, false);
4210 }
4211
4212 static int rtl_ops_init(struct r8152 *tp)
4213 {
4214 struct rtl_ops *ops = &tp->rtl_ops;
4215 int ret = 0;
4216
4217 switch (tp->version) {
4218 case RTL_VER_01:
4219 case RTL_VER_02:
4220 ops->init = r8152b_init;
4221 ops->enable = rtl8152_enable;
4222 ops->disable = rtl8152_disable;
4223 ops->up = rtl8152_up;
4224 ops->down = rtl8152_down;
4225 ops->unload = rtl8152_unload;
4226 ops->eee_get = r8152_get_eee;
4227 ops->eee_set = r8152_set_eee;
4228 ops->in_nway = rtl8152_in_nway;
4229 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
4230 ops->autosuspend_en = rtl_runtime_suspend_enable;
4231 break;
4232
4233 case RTL_VER_03:
4234 case RTL_VER_04:
4235 case RTL_VER_05:
4236 case RTL_VER_06:
4237 ops->init = r8153_init;
4238 ops->enable = rtl8153_enable;
4239 ops->disable = rtl8153_disable;
4240 ops->up = rtl8153_up;
4241 ops->down = rtl8153_down;
4242 ops->unload = rtl8153_unload;
4243 ops->eee_get = r8153_get_eee;
4244 ops->eee_set = r8153_set_eee;
4245 ops->in_nway = rtl8153_in_nway;
4246 ops->hw_phy_cfg = r8153_hw_phy_cfg;
4247 ops->autosuspend_en = rtl8153_runtime_enable;
4248 break;
4249
4250 default:
4251 ret = -ENODEV;
4252 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
4253 break;
4254 }
4255
4256 return ret;
4257 }
4258
4259 static int rtl8152_probe(struct usb_interface *intf,
4260 const struct usb_device_id *id)
4261 {
4262 struct usb_device *udev = interface_to_usbdev(intf);
4263 struct r8152 *tp;
4264 struct net_device *netdev;
4265 int ret;
4266
4267 if (udev->actconfig->desc.bConfigurationValue != 1) {
4268 usb_driver_set_configuration(udev, 1);
4269 return -ENODEV;
4270 }
4271
4272 usb_reset_device(udev);
4273 netdev = alloc_etherdev(sizeof(struct r8152));
4274 if (!netdev) {
4275 dev_err(&intf->dev, "Out of memory\n");
4276 return -ENOMEM;
4277 }
4278
4279 SET_NETDEV_DEV(netdev, &intf->dev);
4280 tp = netdev_priv(netdev);
4281 tp->msg_enable = 0x7FFF;
4282
4283 tp->udev = udev;
4284 tp->netdev = netdev;
4285 tp->intf = intf;
4286
4287 r8152b_get_version(tp);
4288 ret = rtl_ops_init(tp);
4289 if (ret)
4290 goto out;
4291
4292 mutex_init(&tp->control);
4293 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
4294 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
4295
4296 netdev->netdev_ops = &rtl8152_netdev_ops;
4297 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
4298
4299 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
4300 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
4301 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
4302 NETIF_F_HW_VLAN_CTAG_TX;
4303 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
4304 NETIF_F_TSO | NETIF_F_FRAGLIST |
4305 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
4306 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
4307 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4308 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
4309 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
4310
4311 netdev->ethtool_ops = &ops;
4312 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
4313
4314 tp->mii.dev = netdev;
4315 tp->mii.mdio_read = read_mii_word;
4316 tp->mii.mdio_write = write_mii_word;
4317 tp->mii.phy_id_mask = 0x3f;
4318 tp->mii.reg_num_mask = 0x1f;
4319 tp->mii.phy_id = R8152_PHY_ID;
4320
4321 switch (udev->speed) {
4322 case USB_SPEED_SUPER:
4323 case USB_SPEED_SUPER_PLUS:
4324 tp->coalesce = COALESCE_SUPER;
4325 break;
4326 case USB_SPEED_HIGH:
4327 tp->coalesce = COALESCE_HIGH;
4328 break;
4329 default:
4330 tp->coalesce = COALESCE_SLOW;
4331 break;
4332 }
4333
4334 tp->autoneg = AUTONEG_ENABLE;
4335 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
4336 tp->duplex = DUPLEX_FULL;
4337
4338 intf->needs_remote_wakeup = 1;
4339
4340 tp->rtl_ops.init(tp);
4341 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
4342 set_ethernet_addr(tp);
4343
4344 usb_set_intfdata(intf, tp);
4345 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
4346
4347 ret = register_netdev(netdev);
4348 if (ret != 0) {
4349 netif_err(tp, probe, netdev, "couldn't register the device\n");
4350 goto out1;
4351 }
4352
4353 if (!rtl_can_wakeup(tp))
4354 __rtl_set_wol(tp, 0);
4355
4356 tp->saved_wolopts = __rtl_get_wol(tp);
4357 if (tp->saved_wolopts)
4358 device_set_wakeup_enable(&udev->dev, true);
4359 else
4360 device_set_wakeup_enable(&udev->dev, false);
4361
4362 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
4363
4364 return 0;
4365
4366 out1:
4367 netif_napi_del(&tp->napi);
4368 usb_set_intfdata(intf, NULL);
4369 out:
4370 free_netdev(netdev);
4371 return ret;
4372 }
4373
4374 static void rtl8152_disconnect(struct usb_interface *intf)
4375 {
4376 struct r8152 *tp = usb_get_intfdata(intf);
4377
4378 usb_set_intfdata(intf, NULL);
4379 if (tp) {
4380 struct usb_device *udev = tp->udev;
4381
4382 if (udev->state == USB_STATE_NOTATTACHED)
4383 set_bit(RTL8152_UNPLUG, &tp->flags);
4384
4385 netif_napi_del(&tp->napi);
4386 unregister_netdev(tp->netdev);
4387 cancel_delayed_work_sync(&tp->hw_phy_work);
4388 tp->rtl_ops.unload(tp);
4389 free_netdev(tp->netdev);
4390 }
4391 }
4392
4393 #define REALTEK_USB_DEVICE(vend, prod) \
4394 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
4395 USB_DEVICE_ID_MATCH_INT_CLASS, \
4396 .idVendor = (vend), \
4397 .idProduct = (prod), \
4398 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
4399 }, \
4400 { \
4401 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
4402 USB_DEVICE_ID_MATCH_DEVICE, \
4403 .idVendor = (vend), \
4404 .idProduct = (prod), \
4405 .bInterfaceClass = USB_CLASS_COMM, \
4406 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
4407 .bInterfaceProtocol = USB_CDC_PROTO_NONE
4408
4409 /* table of devices that work with this driver */
4410 static struct usb_device_id rtl8152_table[] = {
4411 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
4412 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
4413 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
4414 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
4415 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
4416 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
4417 {}
4418 };
4419
4420 MODULE_DEVICE_TABLE(usb, rtl8152_table);
4421
4422 static struct usb_driver rtl8152_driver = {
4423 .name = MODULENAME,
4424 .id_table = rtl8152_table,
4425 .probe = rtl8152_probe,
4426 .disconnect = rtl8152_disconnect,
4427 .suspend = rtl8152_suspend,
4428 .resume = rtl8152_resume,
4429 .reset_resume = rtl8152_reset_resume,
4430 .pre_reset = rtl8152_pre_reset,
4431 .post_reset = rtl8152_post_reset,
4432 .supports_autosuspend = 1,
4433 .disable_hub_initiated_lpm = 1,
4434 };
4435
4436 module_usb_driver(rtl8152_driver);
4437
4438 MODULE_AUTHOR(DRIVER_AUTHOR);
4439 MODULE_DESCRIPTION(DRIVER_DESC);
4440 MODULE_LICENSE("GPL");
4441 MODULE_VERSION(DRIVER_VERSION);
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