drivers/net/usb/smsc95xx.h

   1  /***************************************************************************
   2  *
   3  * Copyright (C) 2007-2008 SMSC
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  *****************************************************************************/
  19
  20 #ifndef _SMSC95XX_H
  21 #define _SMSC95XX_H
  22
  23 /* Tx command words */
  24 #define TX_CMD_A_DATA_OFFSET_           (0x001F0000)
  25 #define TX_CMD_A_FIRST_SEG_             (0x00002000)
  26 #define TX_CMD_A_LAST_SEG_              (0x00001000)
  27 #define TX_CMD_A_BUF_SIZE_              (0x000007FF)
  28
  29 #define TX_CMD_B_CSUM_ENABLE            (0x00004000)
  30 #define TX_CMD_B_ADD_CRC_DISABLE_       (0x00002000)
  31 #define TX_CMD_B_DISABLE_PADDING_       (0x00001000)
  32 #define TX_CMD_B_PKT_BYTE_LENGTH_       (0x000007FF)
  33
  34 /* Rx status word */
  35 #define RX_STS_FF_                      (0x40000000)    /* Filter Fail */
  36 #define RX_STS_FL_                      (0x3FFF0000)    /* Frame Length */
  37 #define RX_STS_ES_                      (0x00008000)    /* Error Summary */
  38 #define RX_STS_BF_                      (0x00002000)    /* Broadcast Frame */
  39 #define RX_STS_LE_                      (0x00001000)    /* Length Error */
  40 #define RX_STS_RF_                      (0x00000800)    /* Runt Frame */
  41 #define RX_STS_MF_                      (0x00000400)    /* Multicast Frame */
  42 #define RX_STS_TL_                      (0x00000080)    /* Frame too long */
  43 #define RX_STS_CS_                      (0x00000040)    /* Collision Seen */
  44 #define RX_STS_FT_                      (0x00000020)    /* Frame Type */
  45 #define RX_STS_RW_                      (0x00000010)    /* Receive Watchdog */
  46 #define RX_STS_ME_                      (0x00000008)    /* Mii Error */
  47 #define RX_STS_DB_                      (0x00000004)    /* Dribbling */
  48 #define RX_STS_CRC_                     (0x00000002)    /* CRC Error */
  49
  50 /* SCSRs */
  51 #define ID_REV                          (0x00)
  52 #define ID_REV_CHIP_ID_MASK_            (0xFFFF0000)
  53 #define ID_REV_CHIP_REV_MASK_           (0x0000FFFF)
  54 #define ID_REV_CHIP_ID_9500_            (0x9500)
  55 #define ID_REV_CHIP_ID_9500A_           (0x9E00)
  56 #define ID_REV_CHIP_ID_9512_            (0xEC00)
  57 #define ID_REV_CHIP_ID_9530_            (0x9530)
  58 #define ID_REV_CHIP_ID_89530_           (0x9E08)
  59 #define ID_REV_CHIP_ID_9730_            (0x9730)
  60
  61 #define INT_STS                         (0x08)
  62 #define INT_STS_TX_STOP_                (0x00020000)
  63 #define INT_STS_RX_STOP_                (0x00010000)
  64 #define INT_STS_PHY_INT_                (0x00008000)
  65 #define INT_STS_TXE_                    (0x00004000)
  66 #define INT_STS_TDFU_                   (0x00002000)
  67 #define INT_STS_TDFO_                   (0x00001000)
  68 #define INT_STS_RXDF_                   (0x00000800)
  69 #define INT_STS_GPIOS_                  (0x000007FF)
  70 #define INT_STS_CLEAR_ALL_              (0xFFFFFFFF)
  71
  72 #define RX_CFG                          (0x0C)
  73 #define RX_FIFO_FLUSH_                  (0x00000001)
  74
  75 #define TX_CFG                          (0x10)
  76 #define TX_CFG_ON_                      (0x00000004)
  77 #define TX_CFG_STOP_                    (0x00000002)
  78 #define TX_CFG_FIFO_FLUSH_              (0x00000001)
  79
  80 #define HW_CFG                          (0x14)
  81 #define HW_CFG_BIR_                     (0x00001000)
  82 #define HW_CFG_LEDB_                    (0x00000800)
  83 #define HW_CFG_RXDOFF_                  (0x00000600)
  84 #define HW_CFG_DRP_                     (0x00000040)
  85 #define HW_CFG_MEF_                     (0x00000020)
  86 #define HW_CFG_LRST_                    (0x00000008)
  87 #define HW_CFG_PSEL_                    (0x00000004)
  88 #define HW_CFG_BCE_                     (0x00000002)
  89 #define HW_CFG_SRST_                    (0x00000001)
  90
  91 #define RX_FIFO_INF                     (0x18)
  92
  93 #define PM_CTRL                         (0x20)
  94 #define PM_CTL_RES_CLR_WKP_STS          (0x00000200)
  95 #define PM_CTL_DEV_RDY_                 (0x00000080)
  96 #define PM_CTL_SUS_MODE_                (0x00000060)
  97 #define PM_CTL_SUS_MODE_0               (0x00000000)
  98 #define PM_CTL_SUS_MODE_1               (0x00000020)
  99 #define PM_CTL_SUS_MODE_2               (0x00000040)
 100 #define PM_CTL_SUS_MODE_3               (0x00000060)
 101 #define PM_CTL_PHY_RST_                 (0x00000010)
 102 #define PM_CTL_WOL_EN_                  (0x00000008)
 103 #define PM_CTL_ED_EN_                   (0x00000004)
 104 #define PM_CTL_WUPS_                    (0x00000003)
 105 #define PM_CTL_WUPS_NO_                 (0x00000000)
 106 #define PM_CTL_WUPS_ED_                 (0x00000001)
 107 #define PM_CTL_WUPS_WOL_                (0x00000002)
 108 #define PM_CTL_WUPS_MULTI_              (0x00000003)
 109
 110 #define LED_GPIO_CFG                    (0x24)
 111 #define LED_GPIO_CFG_SPD_LED            (0x01000000)
 112 #define LED_GPIO_CFG_LNK_LED            (0x00100000)
 113 #define LED_GPIO_CFG_FDX_LED            (0x00010000)
 114
 115 #define GPIO_CFG                        (0x28)
 116
 117 #define AFC_CFG                         (0x2C)
 118
 119 /* Hi watermark = 15.5Kb (~10 mtu pkts) */
 120 /* low watermark = 3k (~2 mtu pkts) */
 121 /* backpressure duration = ~ 350us */
 122 /* Apply FC on any frame. */
 123 #define AFC_CFG_DEFAULT                 (0x00F830A1)
 124
 125 #define E2P_CMD                         (0x30)
 126 #define E2P_CMD_BUSY_                   (0x80000000)
 127 #define E2P_CMD_MASK_                   (0x70000000)
 128 #define E2P_CMD_READ_                   (0x00000000)
 129 #define E2P_CMD_EWDS_                   (0x10000000)
 130 #define E2P_CMD_EWEN_                   (0x20000000)
 131 #define E2P_CMD_WRITE_                  (0x30000000)
 132 #define E2P_CMD_WRAL_                   (0x40000000)
 133 #define E2P_CMD_ERASE_                  (0x50000000)
 134 #define E2P_CMD_ERAL_                   (0x60000000)
 135 #define E2P_CMD_RELOAD_                 (0x70000000)
 136 #define E2P_CMD_TIMEOUT_                (0x00000400)
 137 #define E2P_CMD_LOADED_                 (0x00000200)
 138 #define E2P_CMD_ADDR_                   (0x000001FF)
 139
 140 #define MAX_EEPROM_SIZE                 (512)
 141
 142 #define E2P_DATA                        (0x34)
 143 #define E2P_DATA_MASK_                  (0x000000FF)
 144
 145 #define BURST_CAP                       (0x38)
 146
 147 #define STRAP_STATUS                    (0x3C)
 148 #define STRAP_STATUS_PWR_SEL_           (0x00000020)
 149 #define STRAP_STATUS_AMDIX_EN_          (0x00000010)
 150 #define STRAP_STATUS_PORT_SWAP_         (0x00000008)
 151 #define STRAP_STATUS_EEP_SIZE_          (0x00000004)
 152 #define STRAP_STATUS_RMT_WKP_           (0x00000002)
 153 #define STRAP_STATUS_EEP_DISABLE_       (0x00000001)
 154
 155 #define GPIO_WAKE                       (0x64)
 156
 157 #define INT_EP_CTL                      (0x68)
 158 #define INT_EP_CTL_INTEP_               (0x80000000)
 159 #define INT_EP_CTL_MACRTO_              (0x00080000)
 160 #define INT_EP_CTL_TX_STOP_             (0x00020000)
 161 #define INT_EP_CTL_RX_STOP_             (0x00010000)
 162 #define INT_EP_CTL_PHY_INT_             (0x00008000)
 163 #define INT_EP_CTL_TXE_                 (0x00004000)
 164 #define INT_EP_CTL_TDFU_                (0x00002000)
 165 #define INT_EP_CTL_TDFO_                (0x00001000)
 166 #define INT_EP_CTL_RXDF_                (0x00000800)
 167 #define INT_EP_CTL_GPIOS_               (0x000007FF)
 168
 169 #define BULK_IN_DLY                     (0x6C)
 170
 171 /* MAC CSRs */
 172 #define MAC_CR                          (0x100)
 173 #define MAC_CR_RXALL_                   (0x80000000)
 174 #define MAC_CR_RCVOWN_                  (0x00800000)
 175 #define MAC_CR_LOOPBK_                  (0x00200000)
 176 #define MAC_CR_FDPX_                    (0x00100000)
 177 #define MAC_CR_MCPAS_                   (0x00080000)
 178 #define MAC_CR_PRMS_                    (0x00040000)
 179 #define MAC_CR_INVFILT_                 (0x00020000)
 180 #define MAC_CR_PASSBAD_                 (0x00010000)
 181 #define MAC_CR_HFILT_                   (0x00008000)
 182 #define MAC_CR_HPFILT_                  (0x00002000)
 183 #define MAC_CR_LCOLL_                   (0x00001000)
 184 #define MAC_CR_BCAST_                   (0x00000800)
 185 #define MAC_CR_DISRTY_                  (0x00000400)
 186 #define MAC_CR_PADSTR_                  (0x00000100)
 187 #define MAC_CR_BOLMT_MASK               (0x000000C0)
 188 #define MAC_CR_DFCHK_                   (0x00000020)
 189 #define MAC_CR_TXEN_                    (0x00000008)
 190 #define MAC_CR_RXEN_                    (0x00000004)
 191
 192 #define ADDRH                           (0x104)
 193
 194 #define ADDRL                           (0x108)
 195
 196 #define HASHH                           (0x10C)
 197
 198 #define HASHL                           (0x110)
 199
 200 #define MII_ADDR                        (0x114)
 201 #define MII_WRITE_                      (0x02)
 202 #define MII_BUSY_                       (0x01)
 203 #define MII_READ_                       (0x00) /* ~of MII Write bit */
 204
 205 #define MII_DATA                        (0x118)
 206
 207 #define FLOW                            (0x11C)
 208 #define FLOW_FCPT_                      (0xFFFF0000)
 209 #define FLOW_FCPASS_                    (0x00000004)
 210 #define FLOW_FCEN_                      (0x00000002)
 211 #define FLOW_FCBSY_                     (0x00000001)
 212
 213 #define VLAN1                           (0x120)
 214
 215 #define VLAN2                           (0x124)
 216
 217 #define WUFF                            (0x128)
 218 #define LAN9500_WUFF_NUM                (4)
 219 #define LAN9500A_WUFF_NUM               (8)
 220
 221 #define WUCSR                           (0x12C)
 222 #define WUCSR_WFF_PTR_RST_              (0x80000000)
 223 #define WUCSR_GUE_                      (0x00000200)
 224 #define WUCSR_WUFR_                     (0x00000040)
 225 #define WUCSR_MPR_                      (0x00000020)
 226 #define WUCSR_WAKE_EN_                  (0x00000004)
 227 #define WUCSR_MPEN_                     (0x00000002)
 228
 229 #define COE_CR                          (0x130)
 230 #define Tx_COE_EN_                      (0x00010000)
 231 #define Rx_COE_MODE_                    (0x00000002)
 232 #define Rx_COE_EN_                      (0x00000001)
 233
 234 /* Vendor-specific PHY Definitions */
 235
 236 /* EDPD NLP / crossover time configuration (LAN9500A only) */
 237 #define PHY_EDPD_CONFIG                 (16)
 238 #define PHY_EDPD_CONFIG_TX_NLP_EN_      ((u16)0x8000)
 239 #define PHY_EDPD_CONFIG_TX_NLP_1000_    ((u16)0x0000)
 240 #define PHY_EDPD_CONFIG_TX_NLP_768_     ((u16)0x2000)
 241 #define PHY_EDPD_CONFIG_TX_NLP_512_     ((u16)0x4000)
 242 #define PHY_EDPD_CONFIG_TX_NLP_256_     ((u16)0x6000)
 243 #define PHY_EDPD_CONFIG_RX_1_NLP_       ((u16)0x1000)
 244 #define PHY_EDPD_CONFIG_RX_NLP_64_      ((u16)0x0000)
 245 #define PHY_EDPD_CONFIG_RX_NLP_256_     ((u16)0x0400)
 246 #define PHY_EDPD_CONFIG_RX_NLP_512_     ((u16)0x0800)
 247 #define PHY_EDPD_CONFIG_RX_NLP_1000_    ((u16)0x0C00)
 248 #define PHY_EDPD_CONFIG_EXT_CROSSOVER_  ((u16)0x0001)
 249 #define PHY_EDPD_CONFIG_DEFAULT         (PHY_EDPD_CONFIG_TX_NLP_EN_ | \
 250                                          PHY_EDPD_CONFIG_TX_NLP_768_ | \
 251                                          PHY_EDPD_CONFIG_RX_1_NLP_)
 252
 253 /* Mode Control/Status Register */
 254 #define PHY_MODE_CTRL_STS               (17)
 255 #define MODE_CTRL_STS_EDPWRDOWN_        ((u16)0x2000)
 256 #define MODE_CTRL_STS_ENERGYON_         ((u16)0x0002)
 257
 258 #define SPECIAL_CTRL_STS                (27)
 259 #define SPECIAL_CTRL_STS_OVRRD_AMDIX_   ((u16)0x8000)
 260 #define SPECIAL_CTRL_STS_AMDIX_ENABLE_  ((u16)0x4000)
 261 #define SPECIAL_CTRL_STS_AMDIX_STATE_   ((u16)0x2000)
 262
 263 #define PHY_INT_SRC                     (29)
 264 #define PHY_INT_SRC_ENERGY_ON_          ((u16)0x0080)
 265 #define PHY_INT_SRC_ANEG_COMP_          ((u16)0x0040)
 266 #define PHY_INT_SRC_REMOTE_FAULT_       ((u16)0x0020)
 267 #define PHY_INT_SRC_LINK_DOWN_          ((u16)0x0010)
 268
 269 #define PHY_INT_MASK                    (30)
 270 #define PHY_INT_MASK_ENERGY_ON_         ((u16)0x0080)
 271 #define PHY_INT_MASK_ANEG_COMP_         ((u16)0x0040)
 272 #define PHY_INT_MASK_REMOTE_FAULT_      ((u16)0x0020)
 273 #define PHY_INT_MASK_LINK_DOWN_         ((u16)0x0010)
 274 #define PHY_INT_MASK_DEFAULT_           (PHY_INT_MASK_ANEG_COMP_ | \
 275                                          PHY_INT_MASK_LINK_DOWN_)
 276
 277 #define PHY_SPECIAL                     (31)
 278 #define PHY_SPECIAL_SPD_                ((u16)0x001C)
 279 #define PHY_SPECIAL_SPD_10HALF_         ((u16)0x0004)
 280 #define PHY_SPECIAL_SPD_10FULL_         ((u16)0x0014)
 281 #define PHY_SPECIAL_SPD_100HALF_        ((u16)0x0008)
 282 #define PHY_SPECIAL_SPD_100FULL_        ((u16)0x0018)
 283
 284 /* USB Vendor Requests */
 285 #define USB_VENDOR_REQUEST_WRITE_REGISTER       0xA0
 286 #define USB_VENDOR_REQUEST_READ_REGISTER        0xA1
 287 #define USB_VENDOR_REQUEST_GET_STATS            0xA2
 288
 289 /* Interrupt Endpoint status word bitfields */
 290 #define INT_ENP_TX_STOP_                ((u32)BIT(17))
 291 #define INT_ENP_RX_STOP_                ((u32)BIT(16))
 292 #define INT_ENP_PHY_INT_                ((u32)BIT(15))
 293 #define INT_ENP_TXE_                    ((u32)BIT(14))
 294 #define INT_ENP_TDFU_                   ((u32)BIT(13))
 295 #define INT_ENP_TDFO_                   ((u32)BIT(12))
 296 #define INT_ENP_RXDF_                   ((u32)BIT(11))
 297
 298 #endif /* _SMSC95XX_H */