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[deliverable/linux.git] / drivers / net / wireless / ath / ath10k / pci.c
1 /*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include <linux/pci.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/bitops.h>
23
24 #include "core.h"
25 #include "debug.h"
26
27 #include "targaddrs.h"
28 #include "bmi.h"
29
30 #include "hif.h"
31 #include "htc.h"
32
33 #include "ce.h"
34 #include "pci.h"
35
36 enum ath10k_pci_reset_mode {
37 ATH10K_PCI_RESET_AUTO = 0,
38 ATH10K_PCI_RESET_WARM_ONLY = 1,
39 };
40
41 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
42 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
43
44 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
45 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
46
47 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
48 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
49
50 /* how long wait to wait for target to initialise, in ms */
51 #define ATH10K_PCI_TARGET_WAIT 3000
52 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
53
54 static const struct pci_device_id ath10k_pci_id_table[] = {
55 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
56 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
57 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
58 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
59 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */
60 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */
61 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */
62 { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */
63 {0}
64 };
65
66 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
67 /* QCA988X pre 2.0 chips are not supported because they need some nasty
68 * hacks. ath10k doesn't have them and these devices crash horribly
69 * because of that.
70 */
71 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV },
72
73 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
74 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
75 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
76 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
77 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
78
79 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
80 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
81 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
82 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
83 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
84
85 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV },
86
87 { QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV },
88
89 { QCA9888_2_0_DEVICE_ID, QCA9888_HW_2_0_CHIP_ID_REV },
90
91 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV },
92 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV },
93
94 { QCA9887_1_0_DEVICE_ID, QCA9887_HW_1_0_CHIP_ID_REV },
95 };
96
97 static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
98 static int ath10k_pci_cold_reset(struct ath10k *ar);
99 static int ath10k_pci_safe_chip_reset(struct ath10k *ar);
100 static int ath10k_pci_init_irq(struct ath10k *ar);
101 static int ath10k_pci_deinit_irq(struct ath10k *ar);
102 static int ath10k_pci_request_irq(struct ath10k *ar);
103 static void ath10k_pci_free_irq(struct ath10k *ar);
104 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
105 struct ath10k_ce_pipe *rx_pipe,
106 struct bmi_xfer *xfer);
107 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar);
108 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
109 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
110 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
111 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
112 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
113 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state);
114
115 static struct ce_attr host_ce_config_wlan[] = {
116 /* CE0: host->target HTC control and raw streams */
117 {
118 .flags = CE_ATTR_FLAGS,
119 .src_nentries = 16,
120 .src_sz_max = 256,
121 .dest_nentries = 0,
122 .send_cb = ath10k_pci_htc_tx_cb,
123 },
124
125 /* CE1: target->host HTT + HTC control */
126 {
127 .flags = CE_ATTR_FLAGS,
128 .src_nentries = 0,
129 .src_sz_max = 2048,
130 .dest_nentries = 512,
131 .recv_cb = ath10k_pci_htt_htc_rx_cb,
132 },
133
134 /* CE2: target->host WMI */
135 {
136 .flags = CE_ATTR_FLAGS,
137 .src_nentries = 0,
138 .src_sz_max = 2048,
139 .dest_nentries = 128,
140 .recv_cb = ath10k_pci_htc_rx_cb,
141 },
142
143 /* CE3: host->target WMI */
144 {
145 .flags = CE_ATTR_FLAGS,
146 .src_nentries = 32,
147 .src_sz_max = 2048,
148 .dest_nentries = 0,
149 .send_cb = ath10k_pci_htc_tx_cb,
150 },
151
152 /* CE4: host->target HTT */
153 {
154 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
155 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
156 .src_sz_max = 256,
157 .dest_nentries = 0,
158 .send_cb = ath10k_pci_htt_tx_cb,
159 },
160
161 /* CE5: target->host HTT (HIF->HTT) */
162 {
163 .flags = CE_ATTR_FLAGS,
164 .src_nentries = 0,
165 .src_sz_max = 512,
166 .dest_nentries = 512,
167 .recv_cb = ath10k_pci_htt_rx_cb,
168 },
169
170 /* CE6: target autonomous hif_memcpy */
171 {
172 .flags = CE_ATTR_FLAGS,
173 .src_nentries = 0,
174 .src_sz_max = 0,
175 .dest_nentries = 0,
176 },
177
178 /* CE7: ce_diag, the Diagnostic Window */
179 {
180 .flags = CE_ATTR_FLAGS,
181 .src_nentries = 2,
182 .src_sz_max = DIAG_TRANSFER_LIMIT,
183 .dest_nentries = 2,
184 },
185
186 /* CE8: target->host pktlog */
187 {
188 .flags = CE_ATTR_FLAGS,
189 .src_nentries = 0,
190 .src_sz_max = 2048,
191 .dest_nentries = 128,
192 .recv_cb = ath10k_pci_pktlog_rx_cb,
193 },
194
195 /* CE9 target autonomous qcache memcpy */
196 {
197 .flags = CE_ATTR_FLAGS,
198 .src_nentries = 0,
199 .src_sz_max = 0,
200 .dest_nentries = 0,
201 },
202
203 /* CE10: target autonomous hif memcpy */
204 {
205 .flags = CE_ATTR_FLAGS,
206 .src_nentries = 0,
207 .src_sz_max = 0,
208 .dest_nentries = 0,
209 },
210
211 /* CE11: target autonomous hif memcpy */
212 {
213 .flags = CE_ATTR_FLAGS,
214 .src_nentries = 0,
215 .src_sz_max = 0,
216 .dest_nentries = 0,
217 },
218 };
219
220 /* Target firmware's Copy Engine configuration. */
221 static struct ce_pipe_config target_ce_config_wlan[] = {
222 /* CE0: host->target HTC control and raw streams */
223 {
224 .pipenum = __cpu_to_le32(0),
225 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
226 .nentries = __cpu_to_le32(32),
227 .nbytes_max = __cpu_to_le32(256),
228 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
229 .reserved = __cpu_to_le32(0),
230 },
231
232 /* CE1: target->host HTT + HTC control */
233 {
234 .pipenum = __cpu_to_le32(1),
235 .pipedir = __cpu_to_le32(PIPEDIR_IN),
236 .nentries = __cpu_to_le32(32),
237 .nbytes_max = __cpu_to_le32(2048),
238 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
239 .reserved = __cpu_to_le32(0),
240 },
241
242 /* CE2: target->host WMI */
243 {
244 .pipenum = __cpu_to_le32(2),
245 .pipedir = __cpu_to_le32(PIPEDIR_IN),
246 .nentries = __cpu_to_le32(64),
247 .nbytes_max = __cpu_to_le32(2048),
248 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
249 .reserved = __cpu_to_le32(0),
250 },
251
252 /* CE3: host->target WMI */
253 {
254 .pipenum = __cpu_to_le32(3),
255 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
256 .nentries = __cpu_to_le32(32),
257 .nbytes_max = __cpu_to_le32(2048),
258 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
259 .reserved = __cpu_to_le32(0),
260 },
261
262 /* CE4: host->target HTT */
263 {
264 .pipenum = __cpu_to_le32(4),
265 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
266 .nentries = __cpu_to_le32(256),
267 .nbytes_max = __cpu_to_le32(256),
268 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
269 .reserved = __cpu_to_le32(0),
270 },
271
272 /* NB: 50% of src nentries, since tx has 2 frags */
273
274 /* CE5: target->host HTT (HIF->HTT) */
275 {
276 .pipenum = __cpu_to_le32(5),
277 .pipedir = __cpu_to_le32(PIPEDIR_IN),
278 .nentries = __cpu_to_le32(32),
279 .nbytes_max = __cpu_to_le32(512),
280 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
281 .reserved = __cpu_to_le32(0),
282 },
283
284 /* CE6: Reserved for target autonomous hif_memcpy */
285 {
286 .pipenum = __cpu_to_le32(6),
287 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
288 .nentries = __cpu_to_le32(32),
289 .nbytes_max = __cpu_to_le32(4096),
290 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
291 .reserved = __cpu_to_le32(0),
292 },
293
294 /* CE7 used only by Host */
295 {
296 .pipenum = __cpu_to_le32(7),
297 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
298 .nentries = __cpu_to_le32(0),
299 .nbytes_max = __cpu_to_le32(0),
300 .flags = __cpu_to_le32(0),
301 .reserved = __cpu_to_le32(0),
302 },
303
304 /* CE8 target->host packtlog */
305 {
306 .pipenum = __cpu_to_le32(8),
307 .pipedir = __cpu_to_le32(PIPEDIR_IN),
308 .nentries = __cpu_to_le32(64),
309 .nbytes_max = __cpu_to_le32(2048),
310 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
311 .reserved = __cpu_to_le32(0),
312 },
313
314 /* CE9 target autonomous qcache memcpy */
315 {
316 .pipenum = __cpu_to_le32(9),
317 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
318 .nentries = __cpu_to_le32(32),
319 .nbytes_max = __cpu_to_le32(2048),
320 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
321 .reserved = __cpu_to_le32(0),
322 },
323
324 /* It not necessary to send target wlan configuration for CE10 & CE11
325 * as these CEs are not actively used in target.
326 */
327 };
328
329 /*
330 * Map from service/endpoint to Copy Engine.
331 * This table is derived from the CE_PCI TABLE, above.
332 * It is passed to the Target at startup for use by firmware.
333 */
334 static struct service_to_pipe target_service_to_ce_map_wlan[] = {
335 {
336 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
337 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
338 __cpu_to_le32(3),
339 },
340 {
341 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
342 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
343 __cpu_to_le32(2),
344 },
345 {
346 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
347 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
348 __cpu_to_le32(3),
349 },
350 {
351 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
352 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
353 __cpu_to_le32(2),
354 },
355 {
356 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
357 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
358 __cpu_to_le32(3),
359 },
360 {
361 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
362 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
363 __cpu_to_le32(2),
364 },
365 {
366 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
367 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
368 __cpu_to_le32(3),
369 },
370 {
371 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
372 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
373 __cpu_to_le32(2),
374 },
375 {
376 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
377 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
378 __cpu_to_le32(3),
379 },
380 {
381 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
382 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
383 __cpu_to_le32(2),
384 },
385 {
386 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
387 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
388 __cpu_to_le32(0),
389 },
390 {
391 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
392 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
393 __cpu_to_le32(1),
394 },
395 { /* not used */
396 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
397 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
398 __cpu_to_le32(0),
399 },
400 { /* not used */
401 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
402 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
403 __cpu_to_le32(1),
404 },
405 {
406 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
407 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
408 __cpu_to_le32(4),
409 },
410 {
411 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
412 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
413 __cpu_to_le32(5),
414 },
415
416 /* (Additions here) */
417
418 { /* must be last */
419 __cpu_to_le32(0),
420 __cpu_to_le32(0),
421 __cpu_to_le32(0),
422 },
423 };
424
425 static bool ath10k_pci_is_awake(struct ath10k *ar)
426 {
427 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
428 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
429 RTC_STATE_ADDRESS);
430
431 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
432 }
433
434 static void __ath10k_pci_wake(struct ath10k *ar)
435 {
436 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
437
438 lockdep_assert_held(&ar_pci->ps_lock);
439
440 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n",
441 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
442
443 iowrite32(PCIE_SOC_WAKE_V_MASK,
444 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
445 PCIE_SOC_WAKE_ADDRESS);
446 }
447
448 static void __ath10k_pci_sleep(struct ath10k *ar)
449 {
450 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
451
452 lockdep_assert_held(&ar_pci->ps_lock);
453
454 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n",
455 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
456
457 iowrite32(PCIE_SOC_WAKE_RESET,
458 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
459 PCIE_SOC_WAKE_ADDRESS);
460 ar_pci->ps_awake = false;
461 }
462
463 static int ath10k_pci_wake_wait(struct ath10k *ar)
464 {
465 int tot_delay = 0;
466 int curr_delay = 5;
467
468 while (tot_delay < PCIE_WAKE_TIMEOUT) {
469 if (ath10k_pci_is_awake(ar)) {
470 if (tot_delay > PCIE_WAKE_LATE_US)
471 ath10k_warn(ar, "device wakeup took %d ms which is unusally long, otherwise it works normally.\n",
472 tot_delay / 1000);
473 return 0;
474 }
475
476 udelay(curr_delay);
477 tot_delay += curr_delay;
478
479 if (curr_delay < 50)
480 curr_delay += 5;
481 }
482
483 return -ETIMEDOUT;
484 }
485
486 static int ath10k_pci_force_wake(struct ath10k *ar)
487 {
488 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
489 unsigned long flags;
490 int ret = 0;
491
492 if (ar_pci->pci_ps)
493 return ret;
494
495 spin_lock_irqsave(&ar_pci->ps_lock, flags);
496
497 if (!ar_pci->ps_awake) {
498 iowrite32(PCIE_SOC_WAKE_V_MASK,
499 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
500 PCIE_SOC_WAKE_ADDRESS);
501
502 ret = ath10k_pci_wake_wait(ar);
503 if (ret == 0)
504 ar_pci->ps_awake = true;
505 }
506
507 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
508
509 return ret;
510 }
511
512 static void ath10k_pci_force_sleep(struct ath10k *ar)
513 {
514 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
515 unsigned long flags;
516
517 spin_lock_irqsave(&ar_pci->ps_lock, flags);
518
519 iowrite32(PCIE_SOC_WAKE_RESET,
520 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
521 PCIE_SOC_WAKE_ADDRESS);
522 ar_pci->ps_awake = false;
523
524 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
525 }
526
527 static int ath10k_pci_wake(struct ath10k *ar)
528 {
529 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
530 unsigned long flags;
531 int ret = 0;
532
533 if (ar_pci->pci_ps == 0)
534 return ret;
535
536 spin_lock_irqsave(&ar_pci->ps_lock, flags);
537
538 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n",
539 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
540
541 /* This function can be called very frequently. To avoid excessive
542 * CPU stalls for MMIO reads use a cache var to hold the device state.
543 */
544 if (!ar_pci->ps_awake) {
545 __ath10k_pci_wake(ar);
546
547 ret = ath10k_pci_wake_wait(ar);
548 if (ret == 0)
549 ar_pci->ps_awake = true;
550 }
551
552 if (ret == 0) {
553 ar_pci->ps_wake_refcount++;
554 WARN_ON(ar_pci->ps_wake_refcount == 0);
555 }
556
557 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
558
559 return ret;
560 }
561
562 static void ath10k_pci_sleep(struct ath10k *ar)
563 {
564 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
565 unsigned long flags;
566
567 if (ar_pci->pci_ps == 0)
568 return;
569
570 spin_lock_irqsave(&ar_pci->ps_lock, flags);
571
572 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n",
573 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
574
575 if (WARN_ON(ar_pci->ps_wake_refcount == 0))
576 goto skip;
577
578 ar_pci->ps_wake_refcount--;
579
580 mod_timer(&ar_pci->ps_timer, jiffies +
581 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC));
582
583 skip:
584 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
585 }
586
587 static void ath10k_pci_ps_timer(unsigned long ptr)
588 {
589 struct ath10k *ar = (void *)ptr;
590 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
591 unsigned long flags;
592
593 spin_lock_irqsave(&ar_pci->ps_lock, flags);
594
595 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n",
596 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
597
598 if (ar_pci->ps_wake_refcount > 0)
599 goto skip;
600
601 __ath10k_pci_sleep(ar);
602
603 skip:
604 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
605 }
606
607 static void ath10k_pci_sleep_sync(struct ath10k *ar)
608 {
609 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
610 unsigned long flags;
611
612 if (ar_pci->pci_ps == 0) {
613 ath10k_pci_force_sleep(ar);
614 return;
615 }
616
617 del_timer_sync(&ar_pci->ps_timer);
618
619 spin_lock_irqsave(&ar_pci->ps_lock, flags);
620 WARN_ON(ar_pci->ps_wake_refcount > 0);
621 __ath10k_pci_sleep(ar);
622 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
623 }
624
625 static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value)
626 {
627 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
628 int ret;
629
630 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) {
631 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
632 offset, offset + sizeof(value), ar_pci->mem_len);
633 return;
634 }
635
636 ret = ath10k_pci_wake(ar);
637 if (ret) {
638 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n",
639 value, offset, ret);
640 return;
641 }
642
643 iowrite32(value, ar_pci->mem + offset);
644 ath10k_pci_sleep(ar);
645 }
646
647 static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset)
648 {
649 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
650 u32 val;
651 int ret;
652
653 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) {
654 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
655 offset, offset + sizeof(val), ar_pci->mem_len);
656 return 0;
657 }
658
659 ret = ath10k_pci_wake(ar);
660 if (ret) {
661 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n",
662 offset, ret);
663 return 0xffffffff;
664 }
665
666 val = ioread32(ar_pci->mem + offset);
667 ath10k_pci_sleep(ar);
668
669 return val;
670 }
671
672 inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)
673 {
674 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
675
676 ar_pci->bus_ops->write32(ar, offset, value);
677 }
678
679 inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
680 {
681 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
682
683 return ar_pci->bus_ops->read32(ar, offset);
684 }
685
686 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
687 {
688 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
689 }
690
691 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
692 {
693 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
694 }
695
696 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
697 {
698 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr);
699 }
700
701 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
702 {
703 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val);
704 }
705
706 bool ath10k_pci_irq_pending(struct ath10k *ar)
707 {
708 u32 cause;
709
710 /* Check if the shared legacy irq is for us */
711 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
712 PCIE_INTR_CAUSE_ADDRESS);
713 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
714 return true;
715
716 return false;
717 }
718
719 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
720 {
721 /* IMPORTANT: INTR_CLR register has to be set after
722 * INTR_ENABLE is set to 0, otherwise interrupt can not be
723 * really cleared. */
724 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
725 0);
726 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
727 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
728
729 /* IMPORTANT: this extra read transaction is required to
730 * flush the posted write buffer. */
731 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
732 PCIE_INTR_ENABLE_ADDRESS);
733 }
734
735 void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
736 {
737 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
738 PCIE_INTR_ENABLE_ADDRESS,
739 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
740
741 /* IMPORTANT: this extra read transaction is required to
742 * flush the posted write buffer. */
743 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
744 PCIE_INTR_ENABLE_ADDRESS);
745 }
746
747 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)
748 {
749 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
750
751 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI)
752 return "msi";
753
754 return "legacy";
755 }
756
757 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
758 {
759 struct ath10k *ar = pipe->hif_ce_state;
760 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
761 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
762 struct sk_buff *skb;
763 dma_addr_t paddr;
764 int ret;
765
766 skb = dev_alloc_skb(pipe->buf_sz);
767 if (!skb)
768 return -ENOMEM;
769
770 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
771
772 paddr = dma_map_single(ar->dev, skb->data,
773 skb->len + skb_tailroom(skb),
774 DMA_FROM_DEVICE);
775 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
776 ath10k_warn(ar, "failed to dma map pci rx buf\n");
777 dev_kfree_skb_any(skb);
778 return -EIO;
779 }
780
781 ATH10K_SKB_RXCB(skb)->paddr = paddr;
782
783 spin_lock_bh(&ar_pci->ce_lock);
784 ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr);
785 spin_unlock_bh(&ar_pci->ce_lock);
786 if (ret) {
787 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
788 DMA_FROM_DEVICE);
789 dev_kfree_skb_any(skb);
790 return ret;
791 }
792
793 return 0;
794 }
795
796 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
797 {
798 struct ath10k *ar = pipe->hif_ce_state;
799 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
800 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
801 int ret, num;
802
803 if (pipe->buf_sz == 0)
804 return;
805
806 if (!ce_pipe->dest_ring)
807 return;
808
809 spin_lock_bh(&ar_pci->ce_lock);
810 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
811 spin_unlock_bh(&ar_pci->ce_lock);
812
813 while (num >= 0) {
814 ret = __ath10k_pci_rx_post_buf(pipe);
815 if (ret) {
816 if (ret == -ENOSPC)
817 break;
818 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
819 mod_timer(&ar_pci->rx_post_retry, jiffies +
820 ATH10K_PCI_RX_POST_RETRY_MS);
821 break;
822 }
823 num--;
824 }
825 }
826
827 void ath10k_pci_rx_post(struct ath10k *ar)
828 {
829 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
830 int i;
831
832 for (i = 0; i < CE_COUNT; i++)
833 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]);
834 }
835
836 void ath10k_pci_rx_replenish_retry(unsigned long ptr)
837 {
838 struct ath10k *ar = (void *)ptr;
839
840 ath10k_pci_rx_post(ar);
841 }
842
843 static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
844 {
845 u32 val = 0;
846
847 switch (ar->hw_rev) {
848 case ATH10K_HW_QCA988X:
849 case ATH10K_HW_QCA9887:
850 case ATH10K_HW_QCA6174:
851 case ATH10K_HW_QCA9377:
852 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
853 CORE_CTRL_ADDRESS) &
854 0x7ff) << 21;
855 break;
856 case ATH10K_HW_QCA9888:
857 case ATH10K_HW_QCA99X0:
858 case ATH10K_HW_QCA9984:
859 case ATH10K_HW_QCA4019:
860 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
861 break;
862 }
863
864 val |= 0x100000 | (addr & 0xfffff);
865 return val;
866 }
867
868 /*
869 * Diagnostic read/write access is provided for startup/config/debug usage.
870 * Caller must guarantee proper alignment, when applicable, and single user
871 * at any moment.
872 */
873 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
874 int nbytes)
875 {
876 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
877 int ret = 0;
878 u32 *buf;
879 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes;
880 struct ath10k_ce_pipe *ce_diag;
881 /* Host buffer address in CE space */
882 u32 ce_data;
883 dma_addr_t ce_data_base = 0;
884 void *data_buf = NULL;
885 int i;
886
887 spin_lock_bh(&ar_pci->ce_lock);
888
889 ce_diag = ar_pci->ce_diag;
890
891 /*
892 * Allocate a temporary bounce buffer to hold caller's data
893 * to be DMA'ed from Target. This guarantees
894 * 1) 4-byte alignment
895 * 2) Buffer in DMA-able space
896 */
897 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT);
898
899 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
900 alloc_nbytes,
901 &ce_data_base,
902 GFP_ATOMIC);
903
904 if (!data_buf) {
905 ret = -ENOMEM;
906 goto done;
907 }
908 memset(data_buf, 0, alloc_nbytes);
909
910 remaining_bytes = nbytes;
911 ce_data = ce_data_base;
912 while (remaining_bytes) {
913 nbytes = min_t(unsigned int, remaining_bytes,
914 DIAG_TRANSFER_LIMIT);
915
916 ret = __ath10k_ce_rx_post_buf(ce_diag, &ce_data, ce_data);
917 if (ret != 0)
918 goto done;
919
920 /* Request CE to send from Target(!) address to Host buffer */
921 /*
922 * The address supplied by the caller is in the
923 * Target CPU virtual address space.
924 *
925 * In order to use this address with the diagnostic CE,
926 * convert it from Target CPU virtual address space
927 * to CE address space
928 */
929 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
930
931 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0,
932 0);
933 if (ret)
934 goto done;
935
936 i = 0;
937 while (ath10k_ce_completed_send_next_nolock(ce_diag,
938 NULL) != 0) {
939 mdelay(1);
940 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
941 ret = -EBUSY;
942 goto done;
943 }
944 }
945
946 i = 0;
947 while (ath10k_ce_completed_recv_next_nolock(ce_diag,
948 (void **)&buf,
949 &completed_nbytes)
950 != 0) {
951 mdelay(1);
952
953 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
954 ret = -EBUSY;
955 goto done;
956 }
957 }
958
959 if (nbytes != completed_nbytes) {
960 ret = -EIO;
961 goto done;
962 }
963
964 if (*buf != ce_data) {
965 ret = -EIO;
966 goto done;
967 }
968
969 remaining_bytes -= nbytes;
970
971 if (ret) {
972 ath10k_warn(ar, "failed to read diag value at 0x%x: %d\n",
973 address, ret);
974 break;
975 }
976 memcpy(data, data_buf, nbytes);
977
978 address += nbytes;
979 data += nbytes;
980 }
981
982 done:
983
984 if (data_buf)
985 dma_free_coherent(ar->dev, alloc_nbytes, data_buf,
986 ce_data_base);
987
988 spin_unlock_bh(&ar_pci->ce_lock);
989
990 return ret;
991 }
992
993 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value)
994 {
995 __le32 val = 0;
996 int ret;
997
998 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val));
999 *value = __le32_to_cpu(val);
1000
1001 return ret;
1002 }
1003
1004 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest,
1005 u32 src, u32 len)
1006 {
1007 u32 host_addr, addr;
1008 int ret;
1009
1010 host_addr = host_interest_item_address(src);
1011
1012 ret = ath10k_pci_diag_read32(ar, host_addr, &addr);
1013 if (ret != 0) {
1014 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n",
1015 src, ret);
1016 return ret;
1017 }
1018
1019 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len);
1020 if (ret != 0) {
1021 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n",
1022 addr, len, ret);
1023 return ret;
1024 }
1025
1026 return 0;
1027 }
1028
1029 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \
1030 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
1031
1032 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
1033 const void *data, int nbytes)
1034 {
1035 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1036 int ret = 0;
1037 u32 *buf;
1038 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
1039 struct ath10k_ce_pipe *ce_diag;
1040 void *data_buf = NULL;
1041 u32 ce_data; /* Host buffer address in CE space */
1042 dma_addr_t ce_data_base = 0;
1043 int i;
1044
1045 spin_lock_bh(&ar_pci->ce_lock);
1046
1047 ce_diag = ar_pci->ce_diag;
1048
1049 /*
1050 * Allocate a temporary bounce buffer to hold caller's data
1051 * to be DMA'ed to Target. This guarantees
1052 * 1) 4-byte alignment
1053 * 2) Buffer in DMA-able space
1054 */
1055 orig_nbytes = nbytes;
1056 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
1057 orig_nbytes,
1058 &ce_data_base,
1059 GFP_ATOMIC);
1060 if (!data_buf) {
1061 ret = -ENOMEM;
1062 goto done;
1063 }
1064
1065 /* Copy caller's data to allocated DMA buf */
1066 memcpy(data_buf, data, orig_nbytes);
1067
1068 /*
1069 * The address supplied by the caller is in the
1070 * Target CPU virtual address space.
1071 *
1072 * In order to use this address with the diagnostic CE,
1073 * convert it from
1074 * Target CPU virtual address space
1075 * to
1076 * CE address space
1077 */
1078 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
1079
1080 remaining_bytes = orig_nbytes;
1081 ce_data = ce_data_base;
1082 while (remaining_bytes) {
1083 /* FIXME: check cast */
1084 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
1085
1086 /* Set up to receive directly into Target(!) address */
1087 ret = __ath10k_ce_rx_post_buf(ce_diag, &address, address);
1088 if (ret != 0)
1089 goto done;
1090
1091 /*
1092 * Request CE to send caller-supplied data that
1093 * was copied to bounce buffer to Target(!) address.
1094 */
1095 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)ce_data,
1096 nbytes, 0, 0);
1097 if (ret != 0)
1098 goto done;
1099
1100 i = 0;
1101 while (ath10k_ce_completed_send_next_nolock(ce_diag,
1102 NULL) != 0) {
1103 mdelay(1);
1104
1105 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
1106 ret = -EBUSY;
1107 goto done;
1108 }
1109 }
1110
1111 i = 0;
1112 while (ath10k_ce_completed_recv_next_nolock(ce_diag,
1113 (void **)&buf,
1114 &completed_nbytes)
1115 != 0) {
1116 mdelay(1);
1117
1118 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
1119 ret = -EBUSY;
1120 goto done;
1121 }
1122 }
1123
1124 if (nbytes != completed_nbytes) {
1125 ret = -EIO;
1126 goto done;
1127 }
1128
1129 if (*buf != address) {
1130 ret = -EIO;
1131 goto done;
1132 }
1133
1134 remaining_bytes -= nbytes;
1135 address += nbytes;
1136 ce_data += nbytes;
1137 }
1138
1139 done:
1140 if (data_buf) {
1141 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
1142 ce_data_base);
1143 }
1144
1145 if (ret != 0)
1146 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
1147 address, ret);
1148
1149 spin_unlock_bh(&ar_pci->ce_lock);
1150
1151 return ret;
1152 }
1153
1154 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value)
1155 {
1156 __le32 val = __cpu_to_le32(value);
1157
1158 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
1159 }
1160
1161 /* Called by lower (CE) layer when a send to Target completes. */
1162 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state)
1163 {
1164 struct ath10k *ar = ce_state->ar;
1165 struct sk_buff_head list;
1166 struct sk_buff *skb;
1167
1168 __skb_queue_head_init(&list);
1169 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1170 /* no need to call tx completion for NULL pointers */
1171 if (skb == NULL)
1172 continue;
1173
1174 __skb_queue_tail(&list, skb);
1175 }
1176
1177 while ((skb = __skb_dequeue(&list)))
1178 ath10k_htc_tx_completion_handler(ar, skb);
1179 }
1180
1181 static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state,
1182 void (*callback)(struct ath10k *ar,
1183 struct sk_buff *skb))
1184 {
1185 struct ath10k *ar = ce_state->ar;
1186 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1187 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1188 struct sk_buff *skb;
1189 struct sk_buff_head list;
1190 void *transfer_context;
1191 unsigned int nbytes, max_nbytes;
1192
1193 __skb_queue_head_init(&list);
1194 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
1195 &nbytes) == 0) {
1196 skb = transfer_context;
1197 max_nbytes = skb->len + skb_tailroom(skb);
1198 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1199 max_nbytes, DMA_FROM_DEVICE);
1200
1201 if (unlikely(max_nbytes < nbytes)) {
1202 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1203 nbytes, max_nbytes);
1204 dev_kfree_skb_any(skb);
1205 continue;
1206 }
1207
1208 skb_put(skb, nbytes);
1209 __skb_queue_tail(&list, skb);
1210 }
1211
1212 while ((skb = __skb_dequeue(&list))) {
1213 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1214 ce_state->id, skb->len);
1215 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1216 skb->data, skb->len);
1217
1218 callback(ar, skb);
1219 }
1220
1221 ath10k_pci_rx_post_pipe(pipe_info);
1222 }
1223
1224 static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state,
1225 void (*callback)(struct ath10k *ar,
1226 struct sk_buff *skb))
1227 {
1228 struct ath10k *ar = ce_state->ar;
1229 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1230 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1231 struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl;
1232 struct sk_buff *skb;
1233 struct sk_buff_head list;
1234 void *transfer_context;
1235 unsigned int nbytes, max_nbytes, nentries;
1236 int orig_len;
1237
1238 /* No need to aquire ce_lock for CE5, since this is the only place CE5
1239 * is processed other than init and deinit. Before releasing CE5
1240 * buffers, interrupts are disabled. Thus CE5 access is serialized.
1241 */
1242 __skb_queue_head_init(&list);
1243 while (ath10k_ce_completed_recv_next_nolock(ce_state, &transfer_context,
1244 &nbytes) == 0) {
1245 skb = transfer_context;
1246 max_nbytes = skb->len + skb_tailroom(skb);
1247
1248 if (unlikely(max_nbytes < nbytes)) {
1249 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1250 nbytes, max_nbytes);
1251 continue;
1252 }
1253
1254 dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1255 max_nbytes, DMA_FROM_DEVICE);
1256 skb_put(skb, nbytes);
1257 __skb_queue_tail(&list, skb);
1258 }
1259
1260 nentries = skb_queue_len(&list);
1261 while ((skb = __skb_dequeue(&list))) {
1262 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1263 ce_state->id, skb->len);
1264 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1265 skb->data, skb->len);
1266
1267 orig_len = skb->len;
1268 callback(ar, skb);
1269 skb_push(skb, orig_len - skb->len);
1270 skb_reset_tail_pointer(skb);
1271 skb_trim(skb, 0);
1272
1273 /*let device gain the buffer again*/
1274 dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1275 skb->len + skb_tailroom(skb),
1276 DMA_FROM_DEVICE);
1277 }
1278 ath10k_ce_rx_update_write_idx(ce_pipe, nentries);
1279 }
1280
1281 /* Called by lower (CE) layer when data is received from the Target. */
1282 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1283 {
1284 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1285 }
1286
1287 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1288 {
1289 /* CE4 polling needs to be done whenever CE pipe which transports
1290 * HTT Rx (target->host) is processed.
1291 */
1292 ath10k_ce_per_engine_service(ce_state->ar, 4);
1293
1294 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1295 }
1296
1297 /* Called by lower (CE) layer when data is received from the Target.
1298 * Only 10.4 firmware uses separate CE to transfer pktlog data.
1299 */
1300 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state)
1301 {
1302 ath10k_pci_process_rx_cb(ce_state,
1303 ath10k_htt_rx_pktlog_completion_handler);
1304 }
1305
1306 /* Called by lower (CE) layer when a send to HTT Target completes. */
1307 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
1308 {
1309 struct ath10k *ar = ce_state->ar;
1310 struct sk_buff *skb;
1311
1312 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1313 /* no need to call tx completion for NULL pointers */
1314 if (!skb)
1315 continue;
1316
1317 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
1318 skb->len, DMA_TO_DEVICE);
1319 ath10k_htt_hif_tx_complete(ar, skb);
1320 }
1321 }
1322
1323 static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb)
1324 {
1325 skb_pull(skb, sizeof(struct ath10k_htc_hdr));
1326 ath10k_htt_t2h_msg_handler(ar, skb);
1327 }
1328
1329 /* Called by lower (CE) layer when HTT data is received from the Target. */
1330 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
1331 {
1332 /* CE4 polling needs to be done whenever CE pipe which transports
1333 * HTT Rx (target->host) is processed.
1334 */
1335 ath10k_ce_per_engine_service(ce_state->ar, 4);
1336
1337 ath10k_pci_process_htt_rx_cb(ce_state, ath10k_pci_htt_rx_deliver);
1338 }
1339
1340 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
1341 struct ath10k_hif_sg_item *items, int n_items)
1342 {
1343 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1344 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
1345 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
1346 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
1347 unsigned int nentries_mask;
1348 unsigned int sw_index;
1349 unsigned int write_index;
1350 int err, i = 0;
1351
1352 spin_lock_bh(&ar_pci->ce_lock);
1353
1354 nentries_mask = src_ring->nentries_mask;
1355 sw_index = src_ring->sw_index;
1356 write_index = src_ring->write_index;
1357
1358 if (unlikely(CE_RING_DELTA(nentries_mask,
1359 write_index, sw_index - 1) < n_items)) {
1360 err = -ENOBUFS;
1361 goto err;
1362 }
1363
1364 for (i = 0; i < n_items - 1; i++) {
1365 ath10k_dbg(ar, ATH10K_DBG_PCI,
1366 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1367 i, items[i].paddr, items[i].len, n_items);
1368 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1369 items[i].vaddr, items[i].len);
1370
1371 err = ath10k_ce_send_nolock(ce_pipe,
1372 items[i].transfer_context,
1373 items[i].paddr,
1374 items[i].len,
1375 items[i].transfer_id,
1376 CE_SEND_FLAG_GATHER);
1377 if (err)
1378 goto err;
1379 }
1380
1381 /* `i` is equal to `n_items -1` after for() */
1382
1383 ath10k_dbg(ar, ATH10K_DBG_PCI,
1384 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1385 i, items[i].paddr, items[i].len, n_items);
1386 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1387 items[i].vaddr, items[i].len);
1388
1389 err = ath10k_ce_send_nolock(ce_pipe,
1390 items[i].transfer_context,
1391 items[i].paddr,
1392 items[i].len,
1393 items[i].transfer_id,
1394 0);
1395 if (err)
1396 goto err;
1397
1398 spin_unlock_bh(&ar_pci->ce_lock);
1399 return 0;
1400
1401 err:
1402 for (; i > 0; i--)
1403 __ath10k_ce_send_revert(ce_pipe);
1404
1405 spin_unlock_bh(&ar_pci->ce_lock);
1406 return err;
1407 }
1408
1409 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
1410 size_t buf_len)
1411 {
1412 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len);
1413 }
1414
1415 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
1416 {
1417 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1418
1419 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n");
1420
1421 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
1422 }
1423
1424 static void ath10k_pci_dump_registers(struct ath10k *ar,
1425 struct ath10k_fw_crash_data *crash_data)
1426 {
1427 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
1428 int i, ret;
1429
1430 lockdep_assert_held(&ar->data_lock);
1431
1432 ret = ath10k_pci_diag_read_hi(ar, &reg_dump_values[0],
1433 hi_failure_state,
1434 REG_DUMP_COUNT_QCA988X * sizeof(__le32));
1435 if (ret) {
1436 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret);
1437 return;
1438 }
1439
1440 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
1441
1442 ath10k_err(ar, "firmware register dump:\n");
1443 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
1444 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
1445 i,
1446 __le32_to_cpu(reg_dump_values[i]),
1447 __le32_to_cpu(reg_dump_values[i + 1]),
1448 __le32_to_cpu(reg_dump_values[i + 2]),
1449 __le32_to_cpu(reg_dump_values[i + 3]));
1450
1451 if (!crash_data)
1452 return;
1453
1454 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++)
1455 crash_data->registers[i] = reg_dump_values[i];
1456 }
1457
1458 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
1459 {
1460 struct ath10k_fw_crash_data *crash_data;
1461 char uuid[50];
1462
1463 spin_lock_bh(&ar->data_lock);
1464
1465 ar->stats.fw_crash_counter++;
1466
1467 crash_data = ath10k_debug_get_new_fw_crash_data(ar);
1468
1469 if (crash_data)
1470 scnprintf(uuid, sizeof(uuid), "%pUl", &crash_data->uuid);
1471 else
1472 scnprintf(uuid, sizeof(uuid), "n/a");
1473
1474 ath10k_err(ar, "firmware crashed! (uuid %s)\n", uuid);
1475 ath10k_print_driver_info(ar);
1476 ath10k_pci_dump_registers(ar, crash_data);
1477
1478 spin_unlock_bh(&ar->data_lock);
1479
1480 queue_work(ar->workqueue, &ar->restart_work);
1481 }
1482
1483 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
1484 int force)
1485 {
1486 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n");
1487
1488 if (!force) {
1489 int resources;
1490 /*
1491 * Decide whether to actually poll for completions, or just
1492 * wait for a later chance.
1493 * If there seem to be plenty of resources left, then just wait
1494 * since checking involves reading a CE register, which is a
1495 * relatively expensive operation.
1496 */
1497 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
1498
1499 /*
1500 * If at least 50% of the total resources are still available,
1501 * don't bother checking again yet.
1502 */
1503 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
1504 return;
1505 }
1506 ath10k_ce_per_engine_service(ar, pipe);
1507 }
1508
1509 void ath10k_pci_kill_tasklet(struct ath10k *ar)
1510 {
1511 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1512
1513 tasklet_kill(&ar_pci->intr_tq);
1514
1515 del_timer_sync(&ar_pci->rx_post_retry);
1516 }
1517
1518 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
1519 u8 *ul_pipe, u8 *dl_pipe)
1520 {
1521 const struct service_to_pipe *entry;
1522 bool ul_set = false, dl_set = false;
1523 int i;
1524
1525 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n");
1526
1527 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
1528 entry = &target_service_to_ce_map_wlan[i];
1529
1530 if (__le32_to_cpu(entry->service_id) != service_id)
1531 continue;
1532
1533 switch (__le32_to_cpu(entry->pipedir)) {
1534 case PIPEDIR_NONE:
1535 break;
1536 case PIPEDIR_IN:
1537 WARN_ON(dl_set);
1538 *dl_pipe = __le32_to_cpu(entry->pipenum);
1539 dl_set = true;
1540 break;
1541 case PIPEDIR_OUT:
1542 WARN_ON(ul_set);
1543 *ul_pipe = __le32_to_cpu(entry->pipenum);
1544 ul_set = true;
1545 break;
1546 case PIPEDIR_INOUT:
1547 WARN_ON(dl_set);
1548 WARN_ON(ul_set);
1549 *dl_pipe = __le32_to_cpu(entry->pipenum);
1550 *ul_pipe = __le32_to_cpu(entry->pipenum);
1551 dl_set = true;
1552 ul_set = true;
1553 break;
1554 }
1555 }
1556
1557 if (WARN_ON(!ul_set || !dl_set))
1558 return -ENOENT;
1559
1560 return 0;
1561 }
1562
1563 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1564 u8 *ul_pipe, u8 *dl_pipe)
1565 {
1566 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
1567
1568 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1569 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1570 ul_pipe, dl_pipe);
1571 }
1572
1573 static void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar)
1574 {
1575 u32 val;
1576
1577 switch (ar->hw_rev) {
1578 case ATH10K_HW_QCA988X:
1579 case ATH10K_HW_QCA9887:
1580 case ATH10K_HW_QCA6174:
1581 case ATH10K_HW_QCA9377:
1582 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1583 CORE_CTRL_ADDRESS);
1584 val &= ~CORE_CTRL_PCIE_REG_31_MASK;
1585 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1586 CORE_CTRL_ADDRESS, val);
1587 break;
1588 case ATH10K_HW_QCA99X0:
1589 case ATH10K_HW_QCA9984:
1590 case ATH10K_HW_QCA9888:
1591 case ATH10K_HW_QCA4019:
1592 /* TODO: Find appropriate register configuration for QCA99X0
1593 * to mask irq/MSI.
1594 */
1595 break;
1596 }
1597 }
1598
1599 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
1600 {
1601 u32 val;
1602
1603 switch (ar->hw_rev) {
1604 case ATH10K_HW_QCA988X:
1605 case ATH10K_HW_QCA9887:
1606 case ATH10K_HW_QCA6174:
1607 case ATH10K_HW_QCA9377:
1608 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1609 CORE_CTRL_ADDRESS);
1610 val |= CORE_CTRL_PCIE_REG_31_MASK;
1611 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1612 CORE_CTRL_ADDRESS, val);
1613 break;
1614 case ATH10K_HW_QCA99X0:
1615 case ATH10K_HW_QCA9984:
1616 case ATH10K_HW_QCA9888:
1617 case ATH10K_HW_QCA4019:
1618 /* TODO: Find appropriate register configuration for QCA99X0
1619 * to unmask irq/MSI.
1620 */
1621 break;
1622 }
1623 }
1624
1625 static void ath10k_pci_irq_disable(struct ath10k *ar)
1626 {
1627 ath10k_ce_disable_interrupts(ar);
1628 ath10k_pci_disable_and_clear_legacy_irq(ar);
1629 ath10k_pci_irq_msi_fw_mask(ar);
1630 }
1631
1632 static void ath10k_pci_irq_sync(struct ath10k *ar)
1633 {
1634 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1635
1636 synchronize_irq(ar_pci->pdev->irq);
1637 }
1638
1639 static void ath10k_pci_irq_enable(struct ath10k *ar)
1640 {
1641 ath10k_ce_enable_interrupts(ar);
1642 ath10k_pci_enable_legacy_irq(ar);
1643 ath10k_pci_irq_msi_fw_unmask(ar);
1644 }
1645
1646 static int ath10k_pci_hif_start(struct ath10k *ar)
1647 {
1648 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1649
1650 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
1651
1652 ath10k_pci_irq_enable(ar);
1653 ath10k_pci_rx_post(ar);
1654
1655 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
1656 ar_pci->link_ctl);
1657
1658 return 0;
1659 }
1660
1661 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1662 {
1663 struct ath10k *ar;
1664 struct ath10k_ce_pipe *ce_pipe;
1665 struct ath10k_ce_ring *ce_ring;
1666 struct sk_buff *skb;
1667 int i;
1668
1669 ar = pci_pipe->hif_ce_state;
1670 ce_pipe = pci_pipe->ce_hdl;
1671 ce_ring = ce_pipe->dest_ring;
1672
1673 if (!ce_ring)
1674 return;
1675
1676 if (!pci_pipe->buf_sz)
1677 return;
1678
1679 for (i = 0; i < ce_ring->nentries; i++) {
1680 skb = ce_ring->per_transfer_context[i];
1681 if (!skb)
1682 continue;
1683
1684 ce_ring->per_transfer_context[i] = NULL;
1685
1686 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1687 skb->len + skb_tailroom(skb),
1688 DMA_FROM_DEVICE);
1689 dev_kfree_skb_any(skb);
1690 }
1691 }
1692
1693 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1694 {
1695 struct ath10k *ar;
1696 struct ath10k_pci *ar_pci;
1697 struct ath10k_ce_pipe *ce_pipe;
1698 struct ath10k_ce_ring *ce_ring;
1699 struct sk_buff *skb;
1700 int i;
1701
1702 ar = pci_pipe->hif_ce_state;
1703 ar_pci = ath10k_pci_priv(ar);
1704 ce_pipe = pci_pipe->ce_hdl;
1705 ce_ring = ce_pipe->src_ring;
1706
1707 if (!ce_ring)
1708 return;
1709
1710 if (!pci_pipe->buf_sz)
1711 return;
1712
1713 for (i = 0; i < ce_ring->nentries; i++) {
1714 skb = ce_ring->per_transfer_context[i];
1715 if (!skb)
1716 continue;
1717
1718 ce_ring->per_transfer_context[i] = NULL;
1719
1720 ath10k_htc_tx_completion_handler(ar, skb);
1721 }
1722 }
1723
1724 /*
1725 * Cleanup residual buffers for device shutdown:
1726 * buffers that were enqueued for receive
1727 * buffers that were to be sent
1728 * Note: Buffers that had completed but which were
1729 * not yet processed are on a completion queue. They
1730 * are handled when the completion thread shuts down.
1731 */
1732 static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1733 {
1734 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1735 int pipe_num;
1736
1737 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1738 struct ath10k_pci_pipe *pipe_info;
1739
1740 pipe_info = &ar_pci->pipe_info[pipe_num];
1741 ath10k_pci_rx_pipe_cleanup(pipe_info);
1742 ath10k_pci_tx_pipe_cleanup(pipe_info);
1743 }
1744 }
1745
1746 void ath10k_pci_ce_deinit(struct ath10k *ar)
1747 {
1748 int i;
1749
1750 for (i = 0; i < CE_COUNT; i++)
1751 ath10k_ce_deinit_pipe(ar, i);
1752 }
1753
1754 void ath10k_pci_flush(struct ath10k *ar)
1755 {
1756 ath10k_pci_kill_tasklet(ar);
1757 ath10k_pci_buffer_cleanup(ar);
1758 }
1759
1760 static void ath10k_pci_hif_stop(struct ath10k *ar)
1761 {
1762 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1763 unsigned long flags;
1764
1765 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
1766
1767 /* Most likely the device has HTT Rx ring configured. The only way to
1768 * prevent the device from accessing (and possible corrupting) host
1769 * memory is to reset the chip now.
1770 *
1771 * There's also no known way of masking MSI interrupts on the device.
1772 * For ranged MSI the CE-related interrupts can be masked. However
1773 * regardless how many MSI interrupts are assigned the first one
1774 * is always used for firmware indications (crashes) and cannot be
1775 * masked. To prevent the device from asserting the interrupt reset it
1776 * before proceeding with cleanup.
1777 */
1778 ath10k_pci_safe_chip_reset(ar);
1779
1780 ath10k_pci_irq_disable(ar);
1781 ath10k_pci_irq_sync(ar);
1782 ath10k_pci_flush(ar);
1783
1784 spin_lock_irqsave(&ar_pci->ps_lock, flags);
1785 WARN_ON(ar_pci->ps_wake_refcount > 0);
1786 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
1787 }
1788
1789 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1790 void *req, u32 req_len,
1791 void *resp, u32 *resp_len)
1792 {
1793 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1794 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1795 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1796 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
1797 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
1798 dma_addr_t req_paddr = 0;
1799 dma_addr_t resp_paddr = 0;
1800 struct bmi_xfer xfer = {};
1801 void *treq, *tresp = NULL;
1802 int ret = 0;
1803
1804 might_sleep();
1805
1806 if (resp && !resp_len)
1807 return -EINVAL;
1808
1809 if (resp && resp_len && *resp_len == 0)
1810 return -EINVAL;
1811
1812 treq = kmemdup(req, req_len, GFP_KERNEL);
1813 if (!treq)
1814 return -ENOMEM;
1815
1816 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1817 ret = dma_mapping_error(ar->dev, req_paddr);
1818 if (ret) {
1819 ret = -EIO;
1820 goto err_dma;
1821 }
1822
1823 if (resp && resp_len) {
1824 tresp = kzalloc(*resp_len, GFP_KERNEL);
1825 if (!tresp) {
1826 ret = -ENOMEM;
1827 goto err_req;
1828 }
1829
1830 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1831 DMA_FROM_DEVICE);
1832 ret = dma_mapping_error(ar->dev, resp_paddr);
1833 if (ret) {
1834 ret = -EIO;
1835 goto err_req;
1836 }
1837
1838 xfer.wait_for_resp = true;
1839 xfer.resp_len = 0;
1840
1841 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr);
1842 }
1843
1844 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1845 if (ret)
1846 goto err_resp;
1847
1848 ret = ath10k_pci_bmi_wait(ce_tx, ce_rx, &xfer);
1849 if (ret) {
1850 u32 unused_buffer;
1851 unsigned int unused_nbytes;
1852 unsigned int unused_id;
1853
1854 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1855 &unused_nbytes, &unused_id);
1856 } else {
1857 /* non-zero means we did not time out */
1858 ret = 0;
1859 }
1860
1861 err_resp:
1862 if (resp) {
1863 u32 unused_buffer;
1864
1865 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1866 dma_unmap_single(ar->dev, resp_paddr,
1867 *resp_len, DMA_FROM_DEVICE);
1868 }
1869 err_req:
1870 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1871
1872 if (ret == 0 && resp_len) {
1873 *resp_len = min(*resp_len, xfer.resp_len);
1874 memcpy(resp, tresp, xfer.resp_len);
1875 }
1876 err_dma:
1877 kfree(treq);
1878 kfree(tresp);
1879
1880 return ret;
1881 }
1882
1883 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
1884 {
1885 struct bmi_xfer *xfer;
1886
1887 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer))
1888 return;
1889
1890 xfer->tx_done = true;
1891 }
1892
1893 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
1894 {
1895 struct ath10k *ar = ce_state->ar;
1896 struct bmi_xfer *xfer;
1897 unsigned int nbytes;
1898
1899 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer,
1900 &nbytes))
1901 return;
1902
1903 if (WARN_ON_ONCE(!xfer))
1904 return;
1905
1906 if (!xfer->wait_for_resp) {
1907 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n");
1908 return;
1909 }
1910
1911 xfer->resp_len = nbytes;
1912 xfer->rx_done = true;
1913 }
1914
1915 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
1916 struct ath10k_ce_pipe *rx_pipe,
1917 struct bmi_xfer *xfer)
1918 {
1919 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1920
1921 while (time_before_eq(jiffies, timeout)) {
1922 ath10k_pci_bmi_send_done(tx_pipe);
1923 ath10k_pci_bmi_recv_data(rx_pipe);
1924
1925 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp))
1926 return 0;
1927
1928 schedule();
1929 }
1930
1931 return -ETIMEDOUT;
1932 }
1933
1934 /*
1935 * Send an interrupt to the device to wake up the Target CPU
1936 * so it has an opportunity to notice any changed state.
1937 */
1938 static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1939 {
1940 u32 addr, val;
1941
1942 addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS;
1943 val = ath10k_pci_read32(ar, addr);
1944 val |= CORE_CTRL_CPU_INTR_MASK;
1945 ath10k_pci_write32(ar, addr, val);
1946
1947 return 0;
1948 }
1949
1950 static int ath10k_pci_get_num_banks(struct ath10k *ar)
1951 {
1952 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1953
1954 switch (ar_pci->pdev->device) {
1955 case QCA988X_2_0_DEVICE_ID:
1956 case QCA99X0_2_0_DEVICE_ID:
1957 case QCA9888_2_0_DEVICE_ID:
1958 case QCA9984_1_0_DEVICE_ID:
1959 case QCA9887_1_0_DEVICE_ID:
1960 return 1;
1961 case QCA6164_2_1_DEVICE_ID:
1962 case QCA6174_2_1_DEVICE_ID:
1963 switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) {
1964 case QCA6174_HW_1_0_CHIP_ID_REV:
1965 case QCA6174_HW_1_1_CHIP_ID_REV:
1966 case QCA6174_HW_2_1_CHIP_ID_REV:
1967 case QCA6174_HW_2_2_CHIP_ID_REV:
1968 return 3;
1969 case QCA6174_HW_1_3_CHIP_ID_REV:
1970 return 2;
1971 case QCA6174_HW_3_0_CHIP_ID_REV:
1972 case QCA6174_HW_3_1_CHIP_ID_REV:
1973 case QCA6174_HW_3_2_CHIP_ID_REV:
1974 return 9;
1975 }
1976 break;
1977 case QCA9377_1_0_DEVICE_ID:
1978 return 2;
1979 }
1980
1981 ath10k_warn(ar, "unknown number of banks, assuming 1\n");
1982 return 1;
1983 }
1984
1985 static int ath10k_bus_get_num_banks(struct ath10k *ar)
1986 {
1987 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1988
1989 return ar_pci->bus_ops->get_num_banks(ar);
1990 }
1991
1992 int ath10k_pci_init_config(struct ath10k *ar)
1993 {
1994 u32 interconnect_targ_addr;
1995 u32 pcie_state_targ_addr = 0;
1996 u32 pipe_cfg_targ_addr = 0;
1997 u32 svc_to_pipe_map = 0;
1998 u32 pcie_config_flags = 0;
1999 u32 ealloc_value;
2000 u32 ealloc_targ_addr;
2001 u32 flag2_value;
2002 u32 flag2_targ_addr;
2003 int ret = 0;
2004
2005 /* Download to Target the CE Config and the service-to-CE map */
2006 interconnect_targ_addr =
2007 host_interest_item_address(HI_ITEM(hi_interconnect_state));
2008
2009 /* Supply Target-side CE configuration */
2010 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr,
2011 &pcie_state_targ_addr);
2012 if (ret != 0) {
2013 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret);
2014 return ret;
2015 }
2016
2017 if (pcie_state_targ_addr == 0) {
2018 ret = -EIO;
2019 ath10k_err(ar, "Invalid pcie state addr\n");
2020 return ret;
2021 }
2022
2023 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2024 offsetof(struct pcie_state,
2025 pipe_cfg_addr)),
2026 &pipe_cfg_targ_addr);
2027 if (ret != 0) {
2028 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
2029 return ret;
2030 }
2031
2032 if (pipe_cfg_targ_addr == 0) {
2033 ret = -EIO;
2034 ath10k_err(ar, "Invalid pipe cfg addr\n");
2035 return ret;
2036 }
2037
2038 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
2039 target_ce_config_wlan,
2040 sizeof(struct ce_pipe_config) *
2041 NUM_TARGET_CE_CONFIG_WLAN);
2042
2043 if (ret != 0) {
2044 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
2045 return ret;
2046 }
2047
2048 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2049 offsetof(struct pcie_state,
2050 svc_to_pipe_map)),
2051 &svc_to_pipe_map);
2052 if (ret != 0) {
2053 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
2054 return ret;
2055 }
2056
2057 if (svc_to_pipe_map == 0) {
2058 ret = -EIO;
2059 ath10k_err(ar, "Invalid svc_to_pipe map\n");
2060 return ret;
2061 }
2062
2063 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
2064 target_service_to_ce_map_wlan,
2065 sizeof(target_service_to_ce_map_wlan));
2066 if (ret != 0) {
2067 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
2068 return ret;
2069 }
2070
2071 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2072 offsetof(struct pcie_state,
2073 config_flags)),
2074 &pcie_config_flags);
2075 if (ret != 0) {
2076 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret);
2077 return ret;
2078 }
2079
2080 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
2081
2082 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr +
2083 offsetof(struct pcie_state,
2084 config_flags)),
2085 pcie_config_flags);
2086 if (ret != 0) {
2087 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret);
2088 return ret;
2089 }
2090
2091 /* configure early allocation */
2092 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
2093
2094 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value);
2095 if (ret != 0) {
2096 ath10k_err(ar, "Faile to get early alloc val: %d\n", ret);
2097 return ret;
2098 }
2099
2100 /* first bank is switched to IRAM */
2101 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
2102 HI_EARLY_ALLOC_MAGIC_MASK);
2103 ealloc_value |= ((ath10k_bus_get_num_banks(ar) <<
2104 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
2105 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
2106
2107 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value);
2108 if (ret != 0) {
2109 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret);
2110 return ret;
2111 }
2112
2113 /* Tell Target to proceed with initialization */
2114 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
2115
2116 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value);
2117 if (ret != 0) {
2118 ath10k_err(ar, "Failed to get option val: %d\n", ret);
2119 return ret;
2120 }
2121
2122 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
2123
2124 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value);
2125 if (ret != 0) {
2126 ath10k_err(ar, "Failed to set option val: %d\n", ret);
2127 return ret;
2128 }
2129
2130 return 0;
2131 }
2132
2133 static void ath10k_pci_override_ce_config(struct ath10k *ar)
2134 {
2135 struct ce_attr *attr;
2136 struct ce_pipe_config *config;
2137
2138 /* For QCA6174 we're overriding the Copy Engine 5 configuration,
2139 * since it is currently used for other feature.
2140 */
2141
2142 /* Override Host's Copy Engine 5 configuration */
2143 attr = &host_ce_config_wlan[5];
2144 attr->src_sz_max = 0;
2145 attr->dest_nentries = 0;
2146
2147 /* Override Target firmware's Copy Engine configuration */
2148 config = &target_ce_config_wlan[5];
2149 config->pipedir = __cpu_to_le32(PIPEDIR_OUT);
2150 config->nbytes_max = __cpu_to_le32(2048);
2151
2152 /* Map from service/endpoint to Copy Engine */
2153 target_service_to_ce_map_wlan[15].pipenum = __cpu_to_le32(1);
2154 }
2155
2156 int ath10k_pci_alloc_pipes(struct ath10k *ar)
2157 {
2158 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2159 struct ath10k_pci_pipe *pipe;
2160 int i, ret;
2161
2162 for (i = 0; i < CE_COUNT; i++) {
2163 pipe = &ar_pci->pipe_info[i];
2164 pipe->ce_hdl = &ar_pci->ce_states[i];
2165 pipe->pipe_num = i;
2166 pipe->hif_ce_state = ar;
2167
2168 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
2169 if (ret) {
2170 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
2171 i, ret);
2172 return ret;
2173 }
2174
2175 /* Last CE is Diagnostic Window */
2176 if (i == CE_DIAG_PIPE) {
2177 ar_pci->ce_diag = pipe->ce_hdl;
2178 continue;
2179 }
2180
2181 pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max);
2182 }
2183
2184 return 0;
2185 }
2186
2187 void ath10k_pci_free_pipes(struct ath10k *ar)
2188 {
2189 int i;
2190
2191 for (i = 0; i < CE_COUNT; i++)
2192 ath10k_ce_free_pipe(ar, i);
2193 }
2194
2195 int ath10k_pci_init_pipes(struct ath10k *ar)
2196 {
2197 int i, ret;
2198
2199 for (i = 0; i < CE_COUNT; i++) {
2200 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
2201 if (ret) {
2202 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
2203 i, ret);
2204 return ret;
2205 }
2206 }
2207
2208 return 0;
2209 }
2210
2211 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar)
2212 {
2213 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &
2214 FW_IND_EVENT_PENDING;
2215 }
2216
2217 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar)
2218 {
2219 u32 val;
2220
2221 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2222 val &= ~FW_IND_EVENT_PENDING;
2223 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
2224 }
2225
2226 static bool ath10k_pci_has_device_gone(struct ath10k *ar)
2227 {
2228 u32 val;
2229
2230 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2231 return (val == 0xffffffff);
2232 }
2233
2234 /* this function effectively clears target memory controller assert line */
2235 static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
2236 {
2237 u32 val;
2238
2239 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2240 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2241 val | SOC_RESET_CONTROL_SI0_RST_MASK);
2242 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2243
2244 msleep(10);
2245
2246 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2247 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2248 val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
2249 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2250
2251 msleep(10);
2252 }
2253
2254 static void ath10k_pci_warm_reset_cpu(struct ath10k *ar)
2255 {
2256 u32 val;
2257
2258 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
2259
2260 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2261 SOC_RESET_CONTROL_ADDRESS);
2262 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2263 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
2264 }
2265
2266 static void ath10k_pci_warm_reset_ce(struct ath10k *ar)
2267 {
2268 u32 val;
2269
2270 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2271 SOC_RESET_CONTROL_ADDRESS);
2272
2273 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2274 val | SOC_RESET_CONTROL_CE_RST_MASK);
2275 msleep(10);
2276 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2277 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
2278 }
2279
2280 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar)
2281 {
2282 u32 val;
2283
2284 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2285 SOC_LF_TIMER_CONTROL0_ADDRESS);
2286 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
2287 SOC_LF_TIMER_CONTROL0_ADDRESS,
2288 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
2289 }
2290
2291 static int ath10k_pci_warm_reset(struct ath10k *ar)
2292 {
2293 int ret;
2294
2295 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
2296
2297 spin_lock_bh(&ar->data_lock);
2298 ar->stats.fw_warm_reset_counter++;
2299 spin_unlock_bh(&ar->data_lock);
2300
2301 ath10k_pci_irq_disable(ar);
2302
2303 /* Make sure the target CPU is not doing anything dangerous, e.g. if it
2304 * were to access copy engine while host performs copy engine reset
2305 * then it is possible for the device to confuse pci-e controller to
2306 * the point of bringing host system to a complete stop (i.e. hang).
2307 */
2308 ath10k_pci_warm_reset_si0(ar);
2309 ath10k_pci_warm_reset_cpu(ar);
2310 ath10k_pci_init_pipes(ar);
2311 ath10k_pci_wait_for_target_init(ar);
2312
2313 ath10k_pci_warm_reset_clear_lf(ar);
2314 ath10k_pci_warm_reset_ce(ar);
2315 ath10k_pci_warm_reset_cpu(ar);
2316 ath10k_pci_init_pipes(ar);
2317
2318 ret = ath10k_pci_wait_for_target_init(ar);
2319 if (ret) {
2320 ath10k_warn(ar, "failed to wait for target init: %d\n", ret);
2321 return ret;
2322 }
2323
2324 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
2325
2326 return 0;
2327 }
2328
2329 static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar)
2330 {
2331 ath10k_pci_irq_disable(ar);
2332 return ath10k_pci_qca99x0_chip_reset(ar);
2333 }
2334
2335 static int ath10k_pci_safe_chip_reset(struct ath10k *ar)
2336 {
2337 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2338
2339 if (!ar_pci->pci_soft_reset)
2340 return -ENOTSUPP;
2341
2342 return ar_pci->pci_soft_reset(ar);
2343 }
2344
2345 static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar)
2346 {
2347 int i, ret;
2348 u32 val;
2349
2350 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n");
2351
2352 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
2353 * It is thus preferred to use warm reset which is safer but may not be
2354 * able to recover the device from all possible fail scenarios.
2355 *
2356 * Warm reset doesn't always work on first try so attempt it a few
2357 * times before giving up.
2358 */
2359 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
2360 ret = ath10k_pci_warm_reset(ar);
2361 if (ret) {
2362 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n",
2363 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS,
2364 ret);
2365 continue;
2366 }
2367
2368 /* FIXME: Sometimes copy engine doesn't recover after warm
2369 * reset. In most cases this needs cold reset. In some of these
2370 * cases the device is in such a state that a cold reset may
2371 * lock up the host.
2372 *
2373 * Reading any host interest register via copy engine is
2374 * sufficient to verify if device is capable of booting
2375 * firmware blob.
2376 */
2377 ret = ath10k_pci_init_pipes(ar);
2378 if (ret) {
2379 ath10k_warn(ar, "failed to init copy engine: %d\n",
2380 ret);
2381 continue;
2382 }
2383
2384 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS,
2385 &val);
2386 if (ret) {
2387 ath10k_warn(ar, "failed to poke copy engine: %d\n",
2388 ret);
2389 continue;
2390 }
2391
2392 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n");
2393 return 0;
2394 }
2395
2396 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) {
2397 ath10k_warn(ar, "refusing cold reset as requested\n");
2398 return -EPERM;
2399 }
2400
2401 ret = ath10k_pci_cold_reset(ar);
2402 if (ret) {
2403 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2404 return ret;
2405 }
2406
2407 ret = ath10k_pci_wait_for_target_init(ar);
2408 if (ret) {
2409 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2410 ret);
2411 return ret;
2412 }
2413
2414 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n");
2415
2416 return 0;
2417 }
2418
2419 static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar)
2420 {
2421 int ret;
2422
2423 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n");
2424
2425 /* FIXME: QCA6174 requires cold + warm reset to work. */
2426
2427 ret = ath10k_pci_cold_reset(ar);
2428 if (ret) {
2429 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2430 return ret;
2431 }
2432
2433 ret = ath10k_pci_wait_for_target_init(ar);
2434 if (ret) {
2435 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2436 ret);
2437 return ret;
2438 }
2439
2440 ret = ath10k_pci_warm_reset(ar);
2441 if (ret) {
2442 ath10k_warn(ar, "failed to warm reset: %d\n", ret);
2443 return ret;
2444 }
2445
2446 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n");
2447
2448 return 0;
2449 }
2450
2451 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar)
2452 {
2453 int ret;
2454
2455 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n");
2456
2457 ret = ath10k_pci_cold_reset(ar);
2458 if (ret) {
2459 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2460 return ret;
2461 }
2462
2463 ret = ath10k_pci_wait_for_target_init(ar);
2464 if (ret) {
2465 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2466 ret);
2467 return ret;
2468 }
2469
2470 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n");
2471
2472 return 0;
2473 }
2474
2475 static int ath10k_pci_chip_reset(struct ath10k *ar)
2476 {
2477 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2478
2479 if (WARN_ON(!ar_pci->pci_hard_reset))
2480 return -ENOTSUPP;
2481
2482 return ar_pci->pci_hard_reset(ar);
2483 }
2484
2485 static int ath10k_pci_hif_power_up(struct ath10k *ar)
2486 {
2487 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2488 int ret;
2489
2490 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");
2491
2492 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2493 &ar_pci->link_ctl);
2494 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2495 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
2496
2497 /*
2498 * Bring the target up cleanly.
2499 *
2500 * The target may be in an undefined state with an AUX-powered Target
2501 * and a Host in WoW mode. If the Host crashes, loses power, or is
2502 * restarted (without unloading the driver) then the Target is left
2503 * (aux) powered and running. On a subsequent driver load, the Target
2504 * is in an unexpected state. We try to catch that here in order to
2505 * reset the Target and retry the probe.
2506 */
2507 ret = ath10k_pci_chip_reset(ar);
2508 if (ret) {
2509 if (ath10k_pci_has_fw_crashed(ar)) {
2510 ath10k_warn(ar, "firmware crashed during chip reset\n");
2511 ath10k_pci_fw_crashed_clear(ar);
2512 ath10k_pci_fw_crashed_dump(ar);
2513 }
2514
2515 ath10k_err(ar, "failed to reset chip: %d\n", ret);
2516 goto err_sleep;
2517 }
2518
2519 ret = ath10k_pci_init_pipes(ar);
2520 if (ret) {
2521 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
2522 goto err_sleep;
2523 }
2524
2525 ret = ath10k_pci_init_config(ar);
2526 if (ret) {
2527 ath10k_err(ar, "failed to setup init config: %d\n", ret);
2528 goto err_ce;
2529 }
2530
2531 ret = ath10k_pci_wake_target_cpu(ar);
2532 if (ret) {
2533 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
2534 goto err_ce;
2535 }
2536
2537 return 0;
2538
2539 err_ce:
2540 ath10k_pci_ce_deinit(ar);
2541
2542 err_sleep:
2543 return ret;
2544 }
2545
2546 void ath10k_pci_hif_power_down(struct ath10k *ar)
2547 {
2548 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
2549
2550 /* Currently hif_power_up performs effectively a reset and hif_stop
2551 * resets the chip as well so there's no point in resetting here.
2552 */
2553 }
2554
2555 #ifdef CONFIG_PM
2556
2557 static int ath10k_pci_hif_suspend(struct ath10k *ar)
2558 {
2559 /* The grace timer can still be counting down and ar->ps_awake be true.
2560 * It is known that the device may be asleep after resuming regardless
2561 * of the SoC powersave state before suspending. Hence make sure the
2562 * device is asleep before proceeding.
2563 */
2564 ath10k_pci_sleep_sync(ar);
2565
2566 return 0;
2567 }
2568
2569 static int ath10k_pci_hif_resume(struct ath10k *ar)
2570 {
2571 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2572 struct pci_dev *pdev = ar_pci->pdev;
2573 u32 val;
2574 int ret = 0;
2575
2576 ret = ath10k_pci_force_wake(ar);
2577 if (ret) {
2578 ath10k_err(ar, "failed to wake up target: %d\n", ret);
2579 return ret;
2580 }
2581
2582 /* Suspend/Resume resets the PCI configuration space, so we have to
2583 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
2584 * from interfering with C3 CPU state. pci_restore_state won't help
2585 * here since it only restores the first 64 bytes pci config header.
2586 */
2587 pci_read_config_dword(pdev, 0x40, &val);
2588 if ((val & 0x0000ff00) != 0)
2589 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2590
2591 return ret;
2592 }
2593 #endif
2594
2595 static bool ath10k_pci_validate_cal(void *data, size_t size)
2596 {
2597 __le16 *cal_words = data;
2598 u16 checksum = 0;
2599 size_t i;
2600
2601 if (size % 2 != 0)
2602 return false;
2603
2604 for (i = 0; i < size / 2; i++)
2605 checksum ^= le16_to_cpu(cal_words[i]);
2606
2607 return checksum == 0xffff;
2608 }
2609
2610 static void ath10k_pci_enable_eeprom(struct ath10k *ar)
2611 {
2612 /* Enable SI clock */
2613 ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0);
2614
2615 /* Configure GPIOs for I2C operation */
2616 ath10k_pci_write32(ar,
2617 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET +
2618 4 * QCA9887_1_0_I2C_SDA_GPIO_PIN,
2619 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG,
2620 GPIO_PIN0_CONFIG) |
2621 SM(1, GPIO_PIN0_PAD_PULL));
2622
2623 ath10k_pci_write32(ar,
2624 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET +
2625 4 * QCA9887_1_0_SI_CLK_GPIO_PIN,
2626 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) |
2627 SM(1, GPIO_PIN0_PAD_PULL));
2628
2629 ath10k_pci_write32(ar,
2630 GPIO_BASE_ADDRESS +
2631 QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS,
2632 1u << QCA9887_1_0_SI_CLK_GPIO_PIN);
2633
2634 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */
2635 ath10k_pci_write32(ar,
2636 SI_BASE_ADDRESS + SI_CONFIG_OFFSET,
2637 SM(1, SI_CONFIG_ERR_INT) |
2638 SM(1, SI_CONFIG_BIDIR_OD_DATA) |
2639 SM(1, SI_CONFIG_I2C) |
2640 SM(1, SI_CONFIG_POS_SAMPLE) |
2641 SM(1, SI_CONFIG_INACTIVE_DATA) |
2642 SM(1, SI_CONFIG_INACTIVE_CLK) |
2643 SM(8, SI_CONFIG_DIVIDER));
2644 }
2645
2646 static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out)
2647 {
2648 u32 reg;
2649 int wait_limit;
2650
2651 /* set device select byte and for the read operation */
2652 reg = QCA9887_EEPROM_SELECT_READ |
2653 SM(addr, QCA9887_EEPROM_ADDR_LO) |
2654 SM(addr >> 8, QCA9887_EEPROM_ADDR_HI);
2655 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg);
2656
2657 /* write transmit data, transfer length, and START bit */
2658 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET,
2659 SM(1, SI_CS_START) | SM(1, SI_CS_RX_CNT) |
2660 SM(4, SI_CS_TX_CNT));
2661
2662 /* wait max 1 sec */
2663 wait_limit = 100000;
2664
2665 /* wait for SI_CS_DONE_INT */
2666 do {
2667 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET);
2668 if (MS(reg, SI_CS_DONE_INT))
2669 break;
2670
2671 wait_limit--;
2672 udelay(10);
2673 } while (wait_limit > 0);
2674
2675 if (!MS(reg, SI_CS_DONE_INT)) {
2676 ath10k_err(ar, "timeout while reading device EEPROM at %04x\n",
2677 addr);
2678 return -ETIMEDOUT;
2679 }
2680
2681 /* clear SI_CS_DONE_INT */
2682 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg);
2683
2684 if (MS(reg, SI_CS_DONE_ERR)) {
2685 ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr);
2686 return -EIO;
2687 }
2688
2689 /* extract receive data */
2690 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET);
2691 *out = reg;
2692
2693 return 0;
2694 }
2695
2696 static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data,
2697 size_t *data_len)
2698 {
2699 u8 *caldata = NULL;
2700 size_t calsize, i;
2701 int ret;
2702
2703 if (!QCA_REV_9887(ar))
2704 return -EOPNOTSUPP;
2705
2706 calsize = ar->hw_params.cal_data_len;
2707 caldata = kmalloc(calsize, GFP_KERNEL);
2708 if (!caldata)
2709 return -ENOMEM;
2710
2711 ath10k_pci_enable_eeprom(ar);
2712
2713 for (i = 0; i < calsize; i++) {
2714 ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]);
2715 if (ret)
2716 goto err_free;
2717 }
2718
2719 if (!ath10k_pci_validate_cal(caldata, calsize))
2720 goto err_free;
2721
2722 *data = caldata;
2723 *data_len = calsize;
2724
2725 return 0;
2726
2727 err_free:
2728 kfree(data);
2729
2730 return -EINVAL;
2731 }
2732
2733 static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
2734 .tx_sg = ath10k_pci_hif_tx_sg,
2735 .diag_read = ath10k_pci_hif_diag_read,
2736 .diag_write = ath10k_pci_diag_write_mem,
2737 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
2738 .start = ath10k_pci_hif_start,
2739 .stop = ath10k_pci_hif_stop,
2740 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
2741 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
2742 .send_complete_check = ath10k_pci_hif_send_complete_check,
2743 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
2744 .power_up = ath10k_pci_hif_power_up,
2745 .power_down = ath10k_pci_hif_power_down,
2746 .read32 = ath10k_pci_read32,
2747 .write32 = ath10k_pci_write32,
2748 #ifdef CONFIG_PM
2749 .suspend = ath10k_pci_hif_suspend,
2750 .resume = ath10k_pci_hif_resume,
2751 #endif
2752 .fetch_cal_eeprom = ath10k_pci_hif_fetch_cal_eeprom,
2753 };
2754
2755 /*
2756 * Top-level interrupt handler for all PCI interrupts from a Target.
2757 * When a block of MSI interrupts is allocated, this top-level handler
2758 * is not used; instead, we directly call the correct sub-handler.
2759 */
2760 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
2761 {
2762 struct ath10k *ar = arg;
2763 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2764 int ret;
2765
2766 if (ath10k_pci_has_device_gone(ar))
2767 return IRQ_NONE;
2768
2769 ret = ath10k_pci_force_wake(ar);
2770 if (ret) {
2771 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret);
2772 return IRQ_NONE;
2773 }
2774
2775 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) {
2776 if (!ath10k_pci_irq_pending(ar))
2777 return IRQ_NONE;
2778
2779 ath10k_pci_disable_and_clear_legacy_irq(ar);
2780 }
2781
2782 tasklet_schedule(&ar_pci->intr_tq);
2783
2784 return IRQ_HANDLED;
2785 }
2786
2787 static void ath10k_pci_tasklet(unsigned long data)
2788 {
2789 struct ath10k *ar = (struct ath10k *)data;
2790 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2791
2792 if (ath10k_pci_has_fw_crashed(ar)) {
2793 ath10k_pci_irq_disable(ar);
2794 ath10k_pci_fw_crashed_clear(ar);
2795 ath10k_pci_fw_crashed_dump(ar);
2796 return;
2797 }
2798
2799 ath10k_ce_per_engine_service_any(ar);
2800
2801 /* Re-enable legacy irq that was disabled in the irq handler */
2802 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY)
2803 ath10k_pci_enable_legacy_irq(ar);
2804 }
2805
2806 static int ath10k_pci_request_irq_msi(struct ath10k *ar)
2807 {
2808 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2809 int ret;
2810
2811 ret = request_irq(ar_pci->pdev->irq,
2812 ath10k_pci_interrupt_handler,
2813 IRQF_SHARED, "ath10k_pci", ar);
2814 if (ret) {
2815 ath10k_warn(ar, "failed to request MSI irq %d: %d\n",
2816 ar_pci->pdev->irq, ret);
2817 return ret;
2818 }
2819
2820 return 0;
2821 }
2822
2823 static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
2824 {
2825 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2826 int ret;
2827
2828 ret = request_irq(ar_pci->pdev->irq,
2829 ath10k_pci_interrupt_handler,
2830 IRQF_SHARED, "ath10k_pci", ar);
2831 if (ret) {
2832 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
2833 ar_pci->pdev->irq, ret);
2834 return ret;
2835 }
2836
2837 return 0;
2838 }
2839
2840 static int ath10k_pci_request_irq(struct ath10k *ar)
2841 {
2842 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2843
2844 switch (ar_pci->oper_irq_mode) {
2845 case ATH10K_PCI_IRQ_LEGACY:
2846 return ath10k_pci_request_irq_legacy(ar);
2847 case ATH10K_PCI_IRQ_MSI:
2848 return ath10k_pci_request_irq_msi(ar);
2849 default:
2850 return -EINVAL;
2851 }
2852 }
2853
2854 static void ath10k_pci_free_irq(struct ath10k *ar)
2855 {
2856 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2857
2858 free_irq(ar_pci->pdev->irq, ar);
2859 }
2860
2861 void ath10k_pci_init_irq_tasklets(struct ath10k *ar)
2862 {
2863 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2864
2865 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long)ar);
2866 }
2867
2868 static int ath10k_pci_init_irq(struct ath10k *ar)
2869 {
2870 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2871 int ret;
2872
2873 ath10k_pci_init_irq_tasklets(ar);
2874
2875 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO)
2876 ath10k_info(ar, "limiting irq mode to: %d\n",
2877 ath10k_pci_irq_mode);
2878
2879 /* Try MSI */
2880 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
2881 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI;
2882 ret = pci_enable_msi(ar_pci->pdev);
2883 if (ret == 0)
2884 return 0;
2885
2886 /* fall-through */
2887 }
2888
2889 /* Try legacy irq
2890 *
2891 * A potential race occurs here: The CORE_BASE write
2892 * depends on target correctly decoding AXI address but
2893 * host won't know when target writes BAR to CORE_CTRL.
2894 * This write might get lost if target has NOT written BAR.
2895 * For now, fix the race by repeating the write in below
2896 * synchronization checking. */
2897 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY;
2898
2899 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2900 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
2901
2902 return 0;
2903 }
2904
2905 static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
2906 {
2907 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2908 0);
2909 }
2910
2911 static int ath10k_pci_deinit_irq(struct ath10k *ar)
2912 {
2913 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2914
2915 switch (ar_pci->oper_irq_mode) {
2916 case ATH10K_PCI_IRQ_LEGACY:
2917 ath10k_pci_deinit_irq_legacy(ar);
2918 break;
2919 default:
2920 pci_disable_msi(ar_pci->pdev);
2921 break;
2922 }
2923
2924 return 0;
2925 }
2926
2927 int ath10k_pci_wait_for_target_init(struct ath10k *ar)
2928 {
2929 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2930 unsigned long timeout;
2931 u32 val;
2932
2933 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
2934
2935 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
2936
2937 do {
2938 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2939
2940 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n",
2941 val);
2942
2943 /* target should never return this */
2944 if (val == 0xffffffff)
2945 continue;
2946
2947 /* the device has crashed so don't bother trying anymore */
2948 if (val & FW_IND_EVENT_PENDING)
2949 break;
2950
2951 if (val & FW_IND_INITIALIZED)
2952 break;
2953
2954 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY)
2955 /* Fix potential race by repeating CORE_BASE writes */
2956 ath10k_pci_enable_legacy_irq(ar);
2957
2958 mdelay(10);
2959 } while (time_before(jiffies, timeout));
2960
2961 ath10k_pci_disable_and_clear_legacy_irq(ar);
2962 ath10k_pci_irq_msi_fw_mask(ar);
2963
2964 if (val == 0xffffffff) {
2965 ath10k_err(ar, "failed to read device register, device is gone\n");
2966 return -EIO;
2967 }
2968
2969 if (val & FW_IND_EVENT_PENDING) {
2970 ath10k_warn(ar, "device has crashed during init\n");
2971 return -ECOMM;
2972 }
2973
2974 if (!(val & FW_IND_INITIALIZED)) {
2975 ath10k_err(ar, "failed to receive initialized event from target: %08x\n",
2976 val);
2977 return -ETIMEDOUT;
2978 }
2979
2980 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n");
2981 return 0;
2982 }
2983
2984 static int ath10k_pci_cold_reset(struct ath10k *ar)
2985 {
2986 u32 val;
2987
2988 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
2989
2990 spin_lock_bh(&ar->data_lock);
2991
2992 ar->stats.fw_cold_reset_counter++;
2993
2994 spin_unlock_bh(&ar->data_lock);
2995
2996 /* Put Target, including PCIe, into RESET. */
2997 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
2998 val |= 1;
2999 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3000
3001 /* After writing into SOC_GLOBAL_RESET to put device into
3002 * reset and pulling out of reset pcie may not be stable
3003 * for any immediate pcie register access and cause bus error,
3004 * add delay before any pcie access request to fix this issue.
3005 */
3006 msleep(20);
3007
3008 /* Pull Target, including PCIe, out of RESET. */
3009 val &= ~1;
3010 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3011
3012 msleep(20);
3013
3014 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
3015
3016 return 0;
3017 }
3018
3019 static int ath10k_pci_claim(struct ath10k *ar)
3020 {
3021 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3022 struct pci_dev *pdev = ar_pci->pdev;
3023 int ret;
3024
3025 pci_set_drvdata(pdev, ar);
3026
3027 ret = pci_enable_device(pdev);
3028 if (ret) {
3029 ath10k_err(ar, "failed to enable pci device: %d\n", ret);
3030 return ret;
3031 }
3032
3033 ret = pci_request_region(pdev, BAR_NUM, "ath");
3034 if (ret) {
3035 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM,
3036 ret);
3037 goto err_device;
3038 }
3039
3040 /* Target expects 32 bit DMA. Enforce it. */
3041 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3042 if (ret) {
3043 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret);
3044 goto err_region;
3045 }
3046
3047 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3048 if (ret) {
3049 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n",
3050 ret);
3051 goto err_region;
3052 }
3053
3054 pci_set_master(pdev);
3055
3056 /* Arrange for access to Target SoC registers. */
3057 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM);
3058 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
3059 if (!ar_pci->mem) {
3060 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM);
3061 ret = -EIO;
3062 goto err_master;
3063 }
3064
3065 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
3066 return 0;
3067
3068 err_master:
3069 pci_clear_master(pdev);
3070
3071 err_region:
3072 pci_release_region(pdev, BAR_NUM);
3073
3074 err_device:
3075 pci_disable_device(pdev);
3076
3077 return ret;
3078 }
3079
3080 static void ath10k_pci_release(struct ath10k *ar)
3081 {
3082 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3083 struct pci_dev *pdev = ar_pci->pdev;
3084
3085 pci_iounmap(pdev, ar_pci->mem);
3086 pci_release_region(pdev, BAR_NUM);
3087 pci_clear_master(pdev);
3088 pci_disable_device(pdev);
3089 }
3090
3091 static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id)
3092 {
3093 const struct ath10k_pci_supp_chip *supp_chip;
3094 int i;
3095 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV);
3096
3097 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) {
3098 supp_chip = &ath10k_pci_supp_chips[i];
3099
3100 if (supp_chip->dev_id == dev_id &&
3101 supp_chip->rev_id == rev_id)
3102 return true;
3103 }
3104
3105 return false;
3106 }
3107
3108 int ath10k_pci_setup_resource(struct ath10k *ar)
3109 {
3110 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3111 int ret;
3112
3113 spin_lock_init(&ar_pci->ce_lock);
3114 spin_lock_init(&ar_pci->ps_lock);
3115
3116 setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry,
3117 (unsigned long)ar);
3118
3119 if (QCA_REV_6174(ar))
3120 ath10k_pci_override_ce_config(ar);
3121
3122 ret = ath10k_pci_alloc_pipes(ar);
3123 if (ret) {
3124 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
3125 ret);
3126 return ret;
3127 }
3128
3129 return 0;
3130 }
3131
3132 void ath10k_pci_release_resource(struct ath10k *ar)
3133 {
3134 ath10k_pci_kill_tasklet(ar);
3135 ath10k_pci_ce_deinit(ar);
3136 ath10k_pci_free_pipes(ar);
3137 }
3138
3139 static const struct ath10k_bus_ops ath10k_pci_bus_ops = {
3140 .read32 = ath10k_bus_pci_read32,
3141 .write32 = ath10k_bus_pci_write32,
3142 .get_num_banks = ath10k_pci_get_num_banks,
3143 };
3144
3145 static int ath10k_pci_probe(struct pci_dev *pdev,
3146 const struct pci_device_id *pci_dev)
3147 {
3148 int ret = 0;
3149 struct ath10k *ar;
3150 struct ath10k_pci *ar_pci;
3151 enum ath10k_hw_rev hw_rev;
3152 u32 chip_id;
3153 bool pci_ps;
3154 int (*pci_soft_reset)(struct ath10k *ar);
3155 int (*pci_hard_reset)(struct ath10k *ar);
3156
3157 switch (pci_dev->device) {
3158 case QCA988X_2_0_DEVICE_ID:
3159 hw_rev = ATH10K_HW_QCA988X;
3160 pci_ps = false;
3161 pci_soft_reset = ath10k_pci_warm_reset;
3162 pci_hard_reset = ath10k_pci_qca988x_chip_reset;
3163 break;
3164 case QCA9887_1_0_DEVICE_ID:
3165 dev_warn(&pdev->dev, "QCA9887 support is still experimental, there are likely bugs. You have been warned.\n");
3166 hw_rev = ATH10K_HW_QCA9887;
3167 pci_ps = false;
3168 pci_soft_reset = ath10k_pci_warm_reset;
3169 pci_hard_reset = ath10k_pci_qca988x_chip_reset;
3170 break;
3171 case QCA6164_2_1_DEVICE_ID:
3172 case QCA6174_2_1_DEVICE_ID:
3173 hw_rev = ATH10K_HW_QCA6174;
3174 pci_ps = true;
3175 pci_soft_reset = ath10k_pci_warm_reset;
3176 pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3177 break;
3178 case QCA99X0_2_0_DEVICE_ID:
3179 hw_rev = ATH10K_HW_QCA99X0;
3180 pci_ps = false;
3181 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3182 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3183 break;
3184 case QCA9984_1_0_DEVICE_ID:
3185 hw_rev = ATH10K_HW_QCA9984;
3186 pci_ps = false;
3187 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3188 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3189 break;
3190 case QCA9888_2_0_DEVICE_ID:
3191 hw_rev = ATH10K_HW_QCA9888;
3192 pci_ps = false;
3193 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3194 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3195 break;
3196 case QCA9377_1_0_DEVICE_ID:
3197 hw_rev = ATH10K_HW_QCA9377;
3198 pci_ps = true;
3199 pci_soft_reset = NULL;
3200 pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3201 break;
3202 default:
3203 WARN_ON(1);
3204 return -ENOTSUPP;
3205 }
3206
3207 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI,
3208 hw_rev, &ath10k_pci_hif_ops);
3209 if (!ar) {
3210 dev_err(&pdev->dev, "failed to allocate core\n");
3211 return -ENOMEM;
3212 }
3213
3214 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
3215 pdev->vendor, pdev->device,
3216 pdev->subsystem_vendor, pdev->subsystem_device);
3217
3218 ar_pci = ath10k_pci_priv(ar);
3219 ar_pci->pdev = pdev;
3220 ar_pci->dev = &pdev->dev;
3221 ar_pci->ar = ar;
3222 ar->dev_id = pci_dev->device;
3223 ar_pci->pci_ps = pci_ps;
3224 ar_pci->bus_ops = &ath10k_pci_bus_ops;
3225 ar_pci->pci_soft_reset = pci_soft_reset;
3226 ar_pci->pci_hard_reset = pci_hard_reset;
3227
3228 ar->id.vendor = pdev->vendor;
3229 ar->id.device = pdev->device;
3230 ar->id.subsystem_vendor = pdev->subsystem_vendor;
3231 ar->id.subsystem_device = pdev->subsystem_device;
3232
3233 setup_timer(&ar_pci->ps_timer, ath10k_pci_ps_timer,
3234 (unsigned long)ar);
3235
3236 ret = ath10k_pci_setup_resource(ar);
3237 if (ret) {
3238 ath10k_err(ar, "failed to setup resource: %d\n", ret);
3239 goto err_core_destroy;
3240 }
3241
3242 ret = ath10k_pci_claim(ar);
3243 if (ret) {
3244 ath10k_err(ar, "failed to claim device: %d\n", ret);
3245 goto err_free_pipes;
3246 }
3247
3248 ret = ath10k_pci_force_wake(ar);
3249 if (ret) {
3250 ath10k_warn(ar, "failed to wake up device : %d\n", ret);
3251 goto err_sleep;
3252 }
3253
3254 ath10k_pci_ce_deinit(ar);
3255 ath10k_pci_irq_disable(ar);
3256
3257 ret = ath10k_pci_init_irq(ar);
3258 if (ret) {
3259 ath10k_err(ar, "failed to init irqs: %d\n", ret);
3260 goto err_sleep;
3261 }
3262
3263 ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n",
3264 ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode,
3265 ath10k_pci_irq_mode, ath10k_pci_reset_mode);
3266
3267 ret = ath10k_pci_request_irq(ar);
3268 if (ret) {
3269 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
3270 goto err_deinit_irq;
3271 }
3272
3273 ret = ath10k_pci_chip_reset(ar);
3274 if (ret) {
3275 ath10k_err(ar, "failed to reset chip: %d\n", ret);
3276 goto err_free_irq;
3277 }
3278
3279 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
3280 if (chip_id == 0xffffffff) {
3281 ath10k_err(ar, "failed to get chip id\n");
3282 goto err_free_irq;
3283 }
3284
3285 if (!ath10k_pci_chip_is_supported(pdev->device, chip_id)) {
3286 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
3287 pdev->device, chip_id);
3288 goto err_free_irq;
3289 }
3290
3291 ret = ath10k_core_register(ar, chip_id);
3292 if (ret) {
3293 ath10k_err(ar, "failed to register driver core: %d\n", ret);
3294 goto err_free_irq;
3295 }
3296
3297 return 0;
3298
3299 err_free_irq:
3300 ath10k_pci_free_irq(ar);
3301 ath10k_pci_kill_tasklet(ar);
3302
3303 err_deinit_irq:
3304 ath10k_pci_deinit_irq(ar);
3305
3306 err_sleep:
3307 ath10k_pci_sleep_sync(ar);
3308 ath10k_pci_release(ar);
3309
3310 err_free_pipes:
3311 ath10k_pci_free_pipes(ar);
3312
3313 err_core_destroy:
3314 ath10k_core_destroy(ar);
3315
3316 return ret;
3317 }
3318
3319 static void ath10k_pci_remove(struct pci_dev *pdev)
3320 {
3321 struct ath10k *ar = pci_get_drvdata(pdev);
3322 struct ath10k_pci *ar_pci;
3323
3324 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n");
3325
3326 if (!ar)
3327 return;
3328
3329 ar_pci = ath10k_pci_priv(ar);
3330
3331 if (!ar_pci)
3332 return;
3333
3334 ath10k_core_unregister(ar);
3335 ath10k_pci_free_irq(ar);
3336 ath10k_pci_deinit_irq(ar);
3337 ath10k_pci_release_resource(ar);
3338 ath10k_pci_sleep_sync(ar);
3339 ath10k_pci_release(ar);
3340 ath10k_core_destroy(ar);
3341 }
3342
3343 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
3344
3345 static struct pci_driver ath10k_pci_driver = {
3346 .name = "ath10k_pci",
3347 .id_table = ath10k_pci_id_table,
3348 .probe = ath10k_pci_probe,
3349 .remove = ath10k_pci_remove,
3350 };
3351
3352 static int __init ath10k_pci_init(void)
3353 {
3354 int ret;
3355
3356 ret = pci_register_driver(&ath10k_pci_driver);
3357 if (ret)
3358 printk(KERN_ERR "failed to register ath10k pci driver: %d\n",
3359 ret);
3360
3361 ret = ath10k_ahb_init();
3362 if (ret)
3363 printk(KERN_ERR "ahb init failed: %d\n", ret);
3364
3365 return ret;
3366 }
3367 module_init(ath10k_pci_init);
3368
3369 static void __exit ath10k_pci_exit(void)
3370 {
3371 pci_unregister_driver(&ath10k_pci_driver);
3372 ath10k_ahb_exit();
3373 }
3374
3375 module_exit(ath10k_pci_exit);
3376
3377 MODULE_AUTHOR("Qualcomm Atheros");
3378 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN PCIe/AHB devices");
3379 MODULE_LICENSE("Dual BSD/GPL");
3380
3381 /* QCA988x 2.0 firmware files */
3382 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE);
3383 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE);
3384 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3385 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3386 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
3387 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3388
3389 /* QCA9887 1.0 firmware files */
3390 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3391 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" QCA9887_HW_1_0_BOARD_DATA_FILE);
3392 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3393
3394 /* QCA6174 2.1 firmware files */
3395 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE);
3396 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE);
3397 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE);
3398 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3399
3400 /* QCA6174 3.1 firmware files */
3401 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3402 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3403 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE);
3404 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3405
3406 /* QCA9377 1.0 firmware files */
3407 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3408 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE);
Linux kernel - Deliverables
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