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Merge branch 'keys-asym-keyctl' into keys-next
[deliverable/linux.git] / drivers / net / wireless / broadcom / brcm80211 / brcmfmac / sdio.c
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/types.h>
18 #include <linux/atomic.h>
19 #include <linux/kernel.h>
20 #include <linux/kthread.h>
21 #include <linux/printk.h>
22 #include <linux/pci_ids.h>
23 #include <linux/netdevice.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched.h>
26 #include <linux/mmc/sdio.h>
27 #include <linux/mmc/sdio_ids.h>
28 #include <linux/mmc/sdio_func.h>
29 #include <linux/mmc/card.h>
30 #include <linux/semaphore.h>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <linux/bcma/bcma.h>
34 #include <linux/debugfs.h>
35 #include <linux/vmalloc.h>
36 #include <asm/unaligned.h>
37 #include <defs.h>
38 #include <brcmu_wifi.h>
39 #include <brcmu_utils.h>
40 #include <brcm_hw_ids.h>
41 #include <soc.h>
42 #include "sdio.h"
43 #include "chip.h"
44 #include "firmware.h"
45 #include "core.h"
46 #include "common.h"
47
48 #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500)
49 #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500)
50
51 #ifdef DEBUG
52
53 #define BRCMF_TRAP_INFO_SIZE 80
54
55 #define CBUF_LEN (128)
56
57 /* Device console log buffer state */
58 #define CONSOLE_BUFFER_MAX 2024
59
60 struct rte_log_le {
61 __le32 buf; /* Can't be pointer on (64-bit) hosts */
62 __le32 buf_size;
63 __le32 idx;
64 char *_buf_compat; /* Redundant pointer for backward compat. */
65 };
66
67 struct rte_console {
68 /* Virtual UART
69 * When there is no UART (e.g. Quickturn),
70 * the host should write a complete
71 * input line directly into cbuf and then write
72 * the length into vcons_in.
73 * This may also be used when there is a real UART
74 * (at risk of conflicting with
75 * the real UART). vcons_out is currently unused.
76 */
77 uint vcons_in;
78 uint vcons_out;
79
80 /* Output (logging) buffer
81 * Console output is written to a ring buffer log_buf at index log_idx.
82 * The host may read the output when it sees log_idx advance.
83 * Output will be lost if the output wraps around faster than the host
84 * polls.
85 */
86 struct rte_log_le log_le;
87
88 /* Console input line buffer
89 * Characters are read one at a time into cbuf
90 * until <CR> is received, then
91 * the buffer is processed as a command line.
92 * Also used for virtual UART.
93 */
94 uint cbuf_idx;
95 char cbuf[CBUF_LEN];
96 };
97
98 #endif /* DEBUG */
99 #include <chipcommon.h>
100
101 #include "bus.h"
102 #include "debug.h"
103 #include "tracepoint.h"
104
105 #define TXQLEN 2048 /* bulk tx queue length */
106 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
107 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
108 #define PRIOMASK 7
109
110 #define TXRETRIES 2 /* # of retries for tx frames */
111
112 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
113 one scheduling */
114
115 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
116 one scheduling */
117
118 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
119
120 #define MEMBLOCK 2048 /* Block size used for downloading
121 of dongle image */
122 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
123 biggest possible glom */
124
125 #define BRCMF_FIRSTREAD (1 << 6)
126
127 #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */
128
129 /* SBSDIO_DEVICE_CTL */
130
131 /* 1: device will assert busy signal when receiving CMD53 */
132 #define SBSDIO_DEVCTL_SETBUSY 0x01
133 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
134 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
135 /* 1: mask all interrupts to host except the chipActive (rev 8) */
136 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
137 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
138 * sdio bus power cycle to clear (rev 9) */
139 #define SBSDIO_DEVCTL_PADS_ISO 0x08
140 /* Force SD->SB reset mapping (rev 11) */
141 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
142 /* Determined by CoreControl bit */
143 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
144 /* Force backplane reset */
145 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
146 /* Force no backplane reset */
147 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
148
149 /* direct(mapped) cis space */
150
151 /* MAPPED common CIS address */
152 #define SBSDIO_CIS_BASE_COMMON 0x1000
153 /* maximum bytes in one CIS */
154 #define SBSDIO_CIS_SIZE_LIMIT 0x200
155 /* cis offset addr is < 17 bits */
156 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
157
158 /* manfid tuple length, include tuple, link bytes */
159 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
160
161 #define CORE_BUS_REG(base, field) \
162 (base + offsetof(struct sdpcmd_regs, field))
163
164 /* SDIO function 1 register CHIPCLKCSR */
165 /* Force ALP request to backplane */
166 #define SBSDIO_FORCE_ALP 0x01
167 /* Force HT request to backplane */
168 #define SBSDIO_FORCE_HT 0x02
169 /* Force ILP request to backplane */
170 #define SBSDIO_FORCE_ILP 0x04
171 /* Make ALP ready (power up xtal) */
172 #define SBSDIO_ALP_AVAIL_REQ 0x08
173 /* Make HT ready (power up PLL) */
174 #define SBSDIO_HT_AVAIL_REQ 0x10
175 /* Squelch clock requests from HW */
176 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
177 /* Status: ALP is ready */
178 #define SBSDIO_ALP_AVAIL 0x40
179 /* Status: HT is ready */
180 #define SBSDIO_HT_AVAIL 0x80
181 #define SBSDIO_CSR_MASK 0x1F
182 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
183 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
184 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
185 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
186 #define SBSDIO_CLKAV(regval, alponly) \
187 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
188
189 /* intstatus */
190 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
191 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
192 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
193 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
194 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
195 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
196 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
197 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
198 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
199 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
200 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
201 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
202 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
203 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
204 #define I_PC (1 << 10) /* descriptor error */
205 #define I_PD (1 << 11) /* data error */
206 #define I_DE (1 << 12) /* Descriptor protocol Error */
207 #define I_RU (1 << 13) /* Receive descriptor Underflow */
208 #define I_RO (1 << 14) /* Receive fifo Overflow */
209 #define I_XU (1 << 15) /* Transmit fifo Underflow */
210 #define I_RI (1 << 16) /* Receive Interrupt */
211 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
212 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
213 #define I_XI (1 << 24) /* Transmit Interrupt */
214 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
215 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
216 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
217 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
218 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
219 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
220 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
221 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
222 #define I_DMA (I_RI | I_XI | I_ERRORS)
223
224 /* corecontrol */
225 #define CC_CISRDY (1 << 0) /* CIS Ready */
226 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
227 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
228 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
229 #define CC_XMTDATAAVAIL_MODE (1 << 4)
230 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
231
232 /* SDA_FRAMECTRL */
233 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
234 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
235 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
236 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
237
238 /*
239 * Software allocation of To SB Mailbox resources
240 */
241
242 /* tosbmailbox bits corresponding to intstatus bits */
243 #define SMB_NAK (1 << 0) /* Frame NAK */
244 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
245 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
246 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
247
248 /* tosbmailboxdata */
249 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
250
251 /*
252 * Software allocation of To Host Mailbox resources
253 */
254
255 /* intstatus bits */
256 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
257 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
258 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
259 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
260
261 /* tohostmailboxdata */
262 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
263 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
264 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
265 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
266
267 #define HMB_DATA_FCDATA_MASK 0xff000000
268 #define HMB_DATA_FCDATA_SHIFT 24
269
270 #define HMB_DATA_VERSION_MASK 0x00ff0000
271 #define HMB_DATA_VERSION_SHIFT 16
272
273 /*
274 * Software-defined protocol header
275 */
276
277 /* Current protocol version */
278 #define SDPCM_PROT_VERSION 4
279
280 /*
281 * Shared structure between dongle and the host.
282 * The structure contains pointers to trap or assert information.
283 */
284 #define SDPCM_SHARED_VERSION 0x0003
285 #define SDPCM_SHARED_VERSION_MASK 0x00FF
286 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
287 #define SDPCM_SHARED_ASSERT 0x0200
288 #define SDPCM_SHARED_TRAP 0x0400
289
290 /* Space for header read, limit for data packets */
291 #define MAX_HDR_READ (1 << 6)
292 #define MAX_RX_DATASZ 2048
293
294 /* Bump up limit on waiting for HT to account for first startup;
295 * if the image is doing a CRC calculation before programming the PMU
296 * for HT availability, it could take a couple hundred ms more, so
297 * max out at a 1 second (1000000us).
298 */
299 #undef PMU_MAX_TRANSITION_DLY
300 #define PMU_MAX_TRANSITION_DLY 1000000
301
302 /* Value for ChipClockCSR during initial setup */
303 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
304 SBSDIO_ALP_AVAIL_REQ)
305
306 /* Flags for SDH calls */
307 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
308
309 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
310 * when idle
311 */
312 #define BRCMF_IDLE_INTERVAL 1
313
314 #define KSO_WAIT_US 50
315 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
316
317 /*
318 * Conversion of 802.1D priority to precedence level
319 */
320 static uint prio2prec(u32 prio)
321 {
322 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
323 (prio^2) : prio;
324 }
325
326 #ifdef DEBUG
327 /* Device console log buffer state */
328 struct brcmf_console {
329 uint count; /* Poll interval msec counter */
330 uint log_addr; /* Log struct address (fixed) */
331 struct rte_log_le log_le; /* Log struct (host copy) */
332 uint bufsize; /* Size of log buffer */
333 u8 *buf; /* Log buffer (host copy) */
334 uint last; /* Last buffer read index */
335 };
336
337 struct brcmf_trap_info {
338 __le32 type;
339 __le32 epc;
340 __le32 cpsr;
341 __le32 spsr;
342 __le32 r0; /* a1 */
343 __le32 r1; /* a2 */
344 __le32 r2; /* a3 */
345 __le32 r3; /* a4 */
346 __le32 r4; /* v1 */
347 __le32 r5; /* v2 */
348 __le32 r6; /* v3 */
349 __le32 r7; /* v4 */
350 __le32 r8; /* v5 */
351 __le32 r9; /* sb/v6 */
352 __le32 r10; /* sl/v7 */
353 __le32 r11; /* fp/v8 */
354 __le32 r12; /* ip */
355 __le32 r13; /* sp */
356 __le32 r14; /* lr */
357 __le32 pc; /* r15 */
358 };
359 #endif /* DEBUG */
360
361 struct sdpcm_shared {
362 u32 flags;
363 u32 trap_addr;
364 u32 assert_exp_addr;
365 u32 assert_file_addr;
366 u32 assert_line;
367 u32 console_addr; /* Address of struct rte_console */
368 u32 msgtrace_addr;
369 u8 tag[32];
370 u32 brpt_addr;
371 };
372
373 struct sdpcm_shared_le {
374 __le32 flags;
375 __le32 trap_addr;
376 __le32 assert_exp_addr;
377 __le32 assert_file_addr;
378 __le32 assert_line;
379 __le32 console_addr; /* Address of struct rte_console */
380 __le32 msgtrace_addr;
381 u8 tag[32];
382 __le32 brpt_addr;
383 };
384
385 /* dongle SDIO bus specific header info */
386 struct brcmf_sdio_hdrinfo {
387 u8 seq_num;
388 u8 channel;
389 u16 len;
390 u16 len_left;
391 u16 len_nxtfrm;
392 u8 dat_offset;
393 bool lastfrm;
394 u16 tail_pad;
395 };
396
397 /*
398 * hold counter variables
399 */
400 struct brcmf_sdio_count {
401 uint intrcount; /* Count of device interrupt callbacks */
402 uint lastintrs; /* Count as of last watchdog timer */
403 uint pollcnt; /* Count of active polls */
404 uint regfails; /* Count of R_REG failures */
405 uint tx_sderrs; /* Count of tx attempts with sd errors */
406 uint fcqueued; /* Tx packets that got queued */
407 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
408 uint rx_toolong; /* Receive frames too long to receive */
409 uint rxc_errors; /* SDIO errors when reading control frames */
410 uint rx_hdrfail; /* SDIO errors on header reads */
411 uint rx_badhdr; /* Bad received headers (roosync?) */
412 uint rx_badseq; /* Mismatched rx sequence number */
413 uint fc_rcvd; /* Number of flow-control events received */
414 uint fc_xoff; /* Number which turned on flow-control */
415 uint fc_xon; /* Number which turned off flow-control */
416 uint rxglomfail; /* Failed deglom attempts */
417 uint rxglomframes; /* Number of glom frames (superframes) */
418 uint rxglompkts; /* Number of packets from glom frames */
419 uint f2rxhdrs; /* Number of header reads */
420 uint f2rxdata; /* Number of frame data reads */
421 uint f2txdata; /* Number of f2 frame writes */
422 uint f1regdata; /* Number of f1 register accesses */
423 uint tickcnt; /* Number of watchdog been schedule */
424 ulong tx_ctlerrs; /* Err of sending ctrl frames */
425 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
426 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
427 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
428 ulong rx_readahead_cnt; /* packets where header read-ahead was used */
429 };
430
431 /* misc chip info needed by some of the routines */
432 /* Private data for SDIO bus interaction */
433 struct brcmf_sdio {
434 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
435 struct brcmf_chip *ci; /* Chip info struct */
436
437 u32 hostintmask; /* Copy of Host Interrupt Mask */
438 atomic_t intstatus; /* Intstatus bits (events) pending */
439 atomic_t fcstate; /* State of dongle flow-control */
440
441 uint blocksize; /* Block size of SDIO transfers */
442 uint roundup; /* Max roundup limit */
443
444 struct pktq txq; /* Queue length used for flow-control */
445 u8 flowcontrol; /* per prio flow control bitmask */
446 u8 tx_seq; /* Transmit sequence number (next) */
447 u8 tx_max; /* Maximum transmit sequence allowed */
448
449 u8 *hdrbuf; /* buffer for handling rx frame */
450 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
451 u8 rx_seq; /* Receive sequence number (expected) */
452 struct brcmf_sdio_hdrinfo cur_read;
453 /* info of current read frame */
454 bool rxskip; /* Skip receive (awaiting NAK ACK) */
455 bool rxpending; /* Data frame pending in dongle */
456
457 uint rxbound; /* Rx frames to read before resched */
458 uint txbound; /* Tx frames to send before resched */
459 uint txminmax;
460
461 struct sk_buff *glomd; /* Packet containing glomming descriptor */
462 struct sk_buff_head glom; /* Packet list for glommed superframe */
463
464 u8 *rxbuf; /* Buffer for receiving control packets */
465 uint rxblen; /* Allocated length of rxbuf */
466 u8 *rxctl; /* Aligned pointer into rxbuf */
467 u8 *rxctl_orig; /* pointer for freeing rxctl */
468 uint rxlen; /* Length of valid data in buffer */
469 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
470
471 u8 sdpcm_ver; /* Bus protocol reported by dongle */
472
473 bool intr; /* Use interrupts */
474 bool poll; /* Use polling */
475 atomic_t ipend; /* Device interrupt is pending */
476 uint spurious; /* Count of spurious interrupts */
477 uint pollrate; /* Ticks between device polls */
478 uint polltick; /* Tick counter */
479
480 #ifdef DEBUG
481 uint console_interval;
482 struct brcmf_console console; /* Console output polling support */
483 uint console_addr; /* Console address from shared struct */
484 #endif /* DEBUG */
485
486 uint clkstate; /* State of sd and backplane clock(s) */
487 s32 idletime; /* Control for activity timeout */
488 s32 idlecount; /* Activity timeout counter */
489 s32 idleclock; /* How to set bus driver when idle */
490 bool rxflow_mode; /* Rx flow control mode */
491 bool rxflow; /* Is rx flow control on */
492 bool alp_only; /* Don't use HT clock (ALP only) */
493
494 u8 *ctrl_frame_buf;
495 u16 ctrl_frame_len;
496 bool ctrl_frame_stat;
497 int ctrl_frame_err;
498
499 spinlock_t txq_lock; /* protect bus->txq */
500 wait_queue_head_t ctrl_wait;
501 wait_queue_head_t dcmd_resp_wait;
502
503 struct timer_list timer;
504 struct completion watchdog_wait;
505 struct task_struct *watchdog_tsk;
506 bool wd_active;
507
508 struct workqueue_struct *brcmf_wq;
509 struct work_struct datawork;
510 bool dpc_triggered;
511 bool dpc_running;
512
513 bool txoff; /* Transmit flow-controlled */
514 struct brcmf_sdio_count sdcnt;
515 bool sr_enabled; /* SaveRestore enabled */
516 bool sleeping;
517
518 u8 tx_hdrlen; /* sdio bus header length for tx packet */
519 bool txglom; /* host tx glomming enable flag */
520 u16 head_align; /* buffer pointer alignment */
521 u16 sgentry_align; /* scatter-gather buffer alignment */
522 };
523
524 /* clkstate */
525 #define CLK_NONE 0
526 #define CLK_SDONLY 1
527 #define CLK_PENDING 2
528 #define CLK_AVAIL 3
529
530 #ifdef DEBUG
531 static int qcount[NUMPRIO];
532 #endif /* DEBUG */
533
534 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
535
536 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
537
538 /* Limit on rounding up frames */
539 static const uint max_roundup = 512;
540
541 #define ALIGNMENT 4
542
543 enum brcmf_sdio_frmtype {
544 BRCMF_SDIO_FT_NORMAL,
545 BRCMF_SDIO_FT_SUPER,
546 BRCMF_SDIO_FT_SUB,
547 };
548
549 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
550
551 /* SDIO Pad drive strength to select value mappings */
552 struct sdiod_drive_str {
553 u8 strength; /* Pad Drive Strength in mA */
554 u8 sel; /* Chip-specific select value */
555 };
556
557 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
558 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
559 {32, 0x6},
560 {26, 0x7},
561 {22, 0x4},
562 {16, 0x5},
563 {12, 0x2},
564 {8, 0x3},
565 {4, 0x0},
566 {0, 0x1}
567 };
568
569 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
570 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
571 {6, 0x7},
572 {5, 0x6},
573 {4, 0x5},
574 {3, 0x4},
575 {2, 0x2},
576 {1, 0x1},
577 {0, 0x0}
578 };
579
580 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
581 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
582 {3, 0x3},
583 {2, 0x2},
584 {1, 0x1},
585 {0, 0x0} };
586
587 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
588 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
589 {16, 0x7},
590 {12, 0x5},
591 {8, 0x3},
592 {4, 0x1}
593 };
594
595 BRCMF_FW_NVRAM_DEF(43143, "brcmfmac43143-sdio.bin", "brcmfmac43143-sdio.txt");
596 BRCMF_FW_NVRAM_DEF(43241B0, "brcmfmac43241b0-sdio.bin",
597 "brcmfmac43241b0-sdio.txt");
598 BRCMF_FW_NVRAM_DEF(43241B4, "brcmfmac43241b4-sdio.bin",
599 "brcmfmac43241b4-sdio.txt");
600 BRCMF_FW_NVRAM_DEF(43241B5, "brcmfmac43241b5-sdio.bin",
601 "brcmfmac43241b5-sdio.txt");
602 BRCMF_FW_NVRAM_DEF(4329, "brcmfmac4329-sdio.bin", "brcmfmac4329-sdio.txt");
603 BRCMF_FW_NVRAM_DEF(4330, "brcmfmac4330-sdio.bin", "brcmfmac4330-sdio.txt");
604 BRCMF_FW_NVRAM_DEF(4334, "brcmfmac4334-sdio.bin", "brcmfmac4334-sdio.txt");
605 BRCMF_FW_NVRAM_DEF(43340, "brcmfmac43340-sdio.bin", "brcmfmac43340-sdio.txt");
606 BRCMF_FW_NVRAM_DEF(4335, "brcmfmac4335-sdio.bin", "brcmfmac4335-sdio.txt");
607 BRCMF_FW_NVRAM_DEF(43362, "brcmfmac43362-sdio.bin", "brcmfmac43362-sdio.txt");
608 BRCMF_FW_NVRAM_DEF(4339, "brcmfmac4339-sdio.bin", "brcmfmac4339-sdio.txt");
609 BRCMF_FW_NVRAM_DEF(43430, "brcmfmac43430-sdio.bin", "brcmfmac43430-sdio.txt");
610 BRCMF_FW_NVRAM_DEF(43455, "brcmfmac43455-sdio.bin", "brcmfmac43455-sdio.txt");
611 BRCMF_FW_NVRAM_DEF(4354, "brcmfmac4354-sdio.bin", "brcmfmac4354-sdio.txt");
612 BRCMF_FW_NVRAM_DEF(4356, "brcmfmac4356-sdio.bin", "brcmfmac4356-sdio.txt");
613
614 static struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
615 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
616 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0),
617 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4),
618 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5),
619 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329),
620 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330),
621 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
622 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
623 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335),
624 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
625 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
626 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFF, 43430),
627 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, 43455),
628 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354),
629 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356)
630 };
631
632 static void pkt_align(struct sk_buff *p, int len, int align)
633 {
634 uint datalign;
635 datalign = (unsigned long)(p->data);
636 datalign = roundup(datalign, (align)) - datalign;
637 if (datalign)
638 skb_pull(p, datalign);
639 __skb_trim(p, len);
640 }
641
642 /* To check if there's window offered */
643 static bool data_ok(struct brcmf_sdio *bus)
644 {
645 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
646 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
647 }
648
649 /*
650 * Reads a register in the SDIO hardware block. This block occupies a series of
651 * adresses on the 32 bit backplane bus.
652 */
653 static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
654 {
655 struct brcmf_core *core;
656 int ret;
657
658 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
659 *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret);
660
661 return ret;
662 }
663
664 static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
665 {
666 struct brcmf_core *core;
667 int ret;
668
669 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
670 brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret);
671
672 return ret;
673 }
674
675 static int
676 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
677 {
678 u8 wr_val = 0, rd_val, cmp_val, bmask;
679 int err = 0;
680 int try_cnt = 0;
681
682 brcmf_dbg(TRACE, "Enter: on=%d\n", on);
683
684 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
685 /* 1st KSO write goes to AOS wake up core if device is asleep */
686 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
687 wr_val, &err);
688
689 if (on) {
690 /* device WAKEUP through KSO:
691 * write bit 0 & read back until
692 * both bits 0 (kso bit) & 1 (dev on status) are set
693 */
694 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
695 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
696 bmask = cmp_val;
697 usleep_range(2000, 3000);
698 } else {
699 /* Put device to sleep, turn off KSO */
700 cmp_val = 0;
701 /* only check for bit0, bit1(dev on status) may not
702 * get cleared right away
703 */
704 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
705 }
706
707 do {
708 /* reliable KSO bit set/clr:
709 * the sdiod sleep write access is synced to PMU 32khz clk
710 * just one write attempt may fail,
711 * read it back until it matches written value
712 */
713 rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
714 &err);
715 if (((rd_val & bmask) == cmp_val) && !err)
716 break;
717
718 udelay(KSO_WAIT_US);
719 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
720 wr_val, &err);
721 } while (try_cnt++ < MAX_KSO_ATTEMPTS);
722
723 if (try_cnt > 2)
724 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
725 rd_val, err);
726
727 if (try_cnt > MAX_KSO_ATTEMPTS)
728 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);
729
730 return err;
731 }
732
733 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
734
735 /* Turn backplane clock on or off */
736 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
737 {
738 int err;
739 u8 clkctl, clkreq, devctl;
740 unsigned long timeout;
741
742 brcmf_dbg(SDIO, "Enter\n");
743
744 clkctl = 0;
745
746 if (bus->sr_enabled) {
747 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
748 return 0;
749 }
750
751 if (on) {
752 /* Request HT Avail */
753 clkreq =
754 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
755
756 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
757 clkreq, &err);
758 if (err) {
759 brcmf_err("HT Avail request error: %d\n", err);
760 return -EBADE;
761 }
762
763 /* Check current status */
764 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
765 SBSDIO_FUNC1_CHIPCLKCSR, &err);
766 if (err) {
767 brcmf_err("HT Avail read error: %d\n", err);
768 return -EBADE;
769 }
770
771 /* Go to pending and await interrupt if appropriate */
772 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
773 /* Allow only clock-available interrupt */
774 devctl = brcmf_sdiod_regrb(bus->sdiodev,
775 SBSDIO_DEVICE_CTL, &err);
776 if (err) {
777 brcmf_err("Devctl error setting CA: %d\n",
778 err);
779 return -EBADE;
780 }
781
782 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
783 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
784 devctl, &err);
785 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
786 bus->clkstate = CLK_PENDING;
787
788 return 0;
789 } else if (bus->clkstate == CLK_PENDING) {
790 /* Cancel CA-only interrupt filter */
791 devctl = brcmf_sdiod_regrb(bus->sdiodev,
792 SBSDIO_DEVICE_CTL, &err);
793 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
794 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
795 devctl, &err);
796 }
797
798 /* Otherwise, wait here (polling) for HT Avail */
799 timeout = jiffies +
800 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
801 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
802 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
803 SBSDIO_FUNC1_CHIPCLKCSR,
804 &err);
805 if (time_after(jiffies, timeout))
806 break;
807 else
808 usleep_range(5000, 10000);
809 }
810 if (err) {
811 brcmf_err("HT Avail request error: %d\n", err);
812 return -EBADE;
813 }
814 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
815 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
816 PMU_MAX_TRANSITION_DLY, clkctl);
817 return -EBADE;
818 }
819
820 /* Mark clock available */
821 bus->clkstate = CLK_AVAIL;
822 brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
823
824 #if defined(DEBUG)
825 if (!bus->alp_only) {
826 if (SBSDIO_ALPONLY(clkctl))
827 brcmf_err("HT Clock should be on\n");
828 }
829 #endif /* defined (DEBUG) */
830
831 } else {
832 clkreq = 0;
833
834 if (bus->clkstate == CLK_PENDING) {
835 /* Cancel CA-only interrupt filter */
836 devctl = brcmf_sdiod_regrb(bus->sdiodev,
837 SBSDIO_DEVICE_CTL, &err);
838 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
839 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
840 devctl, &err);
841 }
842
843 bus->clkstate = CLK_SDONLY;
844 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
845 clkreq, &err);
846 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
847 if (err) {
848 brcmf_err("Failed access turning clock off: %d\n",
849 err);
850 return -EBADE;
851 }
852 }
853 return 0;
854 }
855
856 /* Change idle/active SD state */
857 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
858 {
859 brcmf_dbg(SDIO, "Enter\n");
860
861 if (on)
862 bus->clkstate = CLK_SDONLY;
863 else
864 bus->clkstate = CLK_NONE;
865
866 return 0;
867 }
868
869 /* Transition SD and backplane clock readiness */
870 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
871 {
872 #ifdef DEBUG
873 uint oldstate = bus->clkstate;
874 #endif /* DEBUG */
875
876 brcmf_dbg(SDIO, "Enter\n");
877
878 /* Early exit if we're already there */
879 if (bus->clkstate == target)
880 return 0;
881
882 switch (target) {
883 case CLK_AVAIL:
884 /* Make sure SD clock is available */
885 if (bus->clkstate == CLK_NONE)
886 brcmf_sdio_sdclk(bus, true);
887 /* Now request HT Avail on the backplane */
888 brcmf_sdio_htclk(bus, true, pendok);
889 break;
890
891 case CLK_SDONLY:
892 /* Remove HT request, or bring up SD clock */
893 if (bus->clkstate == CLK_NONE)
894 brcmf_sdio_sdclk(bus, true);
895 else if (bus->clkstate == CLK_AVAIL)
896 brcmf_sdio_htclk(bus, false, false);
897 else
898 brcmf_err("request for %d -> %d\n",
899 bus->clkstate, target);
900 break;
901
902 case CLK_NONE:
903 /* Make sure to remove HT request */
904 if (bus->clkstate == CLK_AVAIL)
905 brcmf_sdio_htclk(bus, false, false);
906 /* Now remove the SD clock */
907 brcmf_sdio_sdclk(bus, false);
908 break;
909 }
910 #ifdef DEBUG
911 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
912 #endif /* DEBUG */
913
914 return 0;
915 }
916
917 static int
918 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
919 {
920 int err = 0;
921 u8 clkcsr;
922
923 brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
924 (sleep ? "SLEEP" : "WAKE"),
925 (bus->sleeping ? "SLEEP" : "WAKE"));
926
927 /* If SR is enabled control bus state with KSO */
928 if (bus->sr_enabled) {
929 /* Done if we're already in the requested state */
930 if (sleep == bus->sleeping)
931 goto end;
932
933 /* Going to sleep */
934 if (sleep) {
935 clkcsr = brcmf_sdiod_regrb(bus->sdiodev,
936 SBSDIO_FUNC1_CHIPCLKCSR,
937 &err);
938 if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
939 brcmf_dbg(SDIO, "no clock, set ALP\n");
940 brcmf_sdiod_regwb(bus->sdiodev,
941 SBSDIO_FUNC1_CHIPCLKCSR,
942 SBSDIO_ALP_AVAIL_REQ, &err);
943 }
944 err = brcmf_sdio_kso_control(bus, false);
945 } else {
946 err = brcmf_sdio_kso_control(bus, true);
947 }
948 if (err) {
949 brcmf_err("error while changing bus sleep state %d\n",
950 err);
951 goto done;
952 }
953 }
954
955 end:
956 /* control clocks */
957 if (sleep) {
958 if (!bus->sr_enabled)
959 brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
960 } else {
961 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
962 brcmf_sdio_wd_timer(bus, true);
963 }
964 bus->sleeping = sleep;
965 brcmf_dbg(SDIO, "new state %s\n",
966 (sleep ? "SLEEP" : "WAKE"));
967 done:
968 brcmf_dbg(SDIO, "Exit: err=%d\n", err);
969 return err;
970
971 }
972
973 #ifdef DEBUG
974 static inline bool brcmf_sdio_valid_shared_address(u32 addr)
975 {
976 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
977 }
978
979 static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
980 struct sdpcm_shared *sh)
981 {
982 u32 addr = 0;
983 int rv;
984 u32 shaddr = 0;
985 struct sdpcm_shared_le sh_le;
986 __le32 addr_le;
987
988 sdio_claim_host(bus->sdiodev->func[1]);
989 brcmf_sdio_bus_sleep(bus, false, false);
990
991 /*
992 * Read last word in socram to determine
993 * address of sdpcm_shared structure
994 */
995 shaddr = bus->ci->rambase + bus->ci->ramsize - 4;
996 if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci))
997 shaddr -= bus->ci->srsize;
998 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr,
999 (u8 *)&addr_le, 4);
1000 if (rv < 0)
1001 goto fail;
1002
1003 /*
1004 * Check if addr is valid.
1005 * NVRAM length at the end of memory should have been overwritten.
1006 */
1007 addr = le32_to_cpu(addr_le);
1008 if (!brcmf_sdio_valid_shared_address(addr)) {
1009 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr);
1010 rv = -EINVAL;
1011 goto fail;
1012 }
1013
1014 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
1015
1016 /* Read hndrte_shared structure */
1017 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
1018 sizeof(struct sdpcm_shared_le));
1019 if (rv < 0)
1020 goto fail;
1021
1022 sdio_release_host(bus->sdiodev->func[1]);
1023
1024 /* Endianness */
1025 sh->flags = le32_to_cpu(sh_le.flags);
1026 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
1027 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
1028 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
1029 sh->assert_line = le32_to_cpu(sh_le.assert_line);
1030 sh->console_addr = le32_to_cpu(sh_le.console_addr);
1031 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
1032
1033 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
1034 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
1035 SDPCM_SHARED_VERSION,
1036 sh->flags & SDPCM_SHARED_VERSION_MASK);
1037 return -EPROTO;
1038 }
1039 return 0;
1040
1041 fail:
1042 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n",
1043 rv, addr);
1044 sdio_release_host(bus->sdiodev->func[1]);
1045 return rv;
1046 }
1047
1048 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1049 {
1050 struct sdpcm_shared sh;
1051
1052 if (brcmf_sdio_readshared(bus, &sh) == 0)
1053 bus->console_addr = sh.console_addr;
1054 }
1055 #else
1056 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1057 {
1058 }
1059 #endif /* DEBUG */
1060
1061 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
1062 {
1063 u32 intstatus = 0;
1064 u32 hmb_data;
1065 u8 fcbits;
1066 int ret;
1067
1068 brcmf_dbg(SDIO, "Enter\n");
1069
1070 /* Read mailbox data and ack that we did so */
1071 ret = r_sdreg32(bus, &hmb_data,
1072 offsetof(struct sdpcmd_regs, tohostmailboxdata));
1073
1074 if (ret == 0)
1075 w_sdreg32(bus, SMB_INT_ACK,
1076 offsetof(struct sdpcmd_regs, tosbmailbox));
1077 bus->sdcnt.f1regdata += 2;
1078
1079 /* Dongle recomposed rx frames, accept them again */
1080 if (hmb_data & HMB_DATA_NAKHANDLED) {
1081 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
1082 bus->rx_seq);
1083 if (!bus->rxskip)
1084 brcmf_err("unexpected NAKHANDLED!\n");
1085
1086 bus->rxskip = false;
1087 intstatus |= I_HMB_FRAME_IND;
1088 }
1089
1090 /*
1091 * DEVREADY does not occur with gSPI.
1092 */
1093 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1094 bus->sdpcm_ver =
1095 (hmb_data & HMB_DATA_VERSION_MASK) >>
1096 HMB_DATA_VERSION_SHIFT;
1097 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1098 brcmf_err("Version mismatch, dongle reports %d, "
1099 "expecting %d\n",
1100 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1101 else
1102 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
1103 bus->sdpcm_ver);
1104
1105 /*
1106 * Retrieve console state address now that firmware should have
1107 * updated it.
1108 */
1109 brcmf_sdio_get_console_addr(bus);
1110 }
1111
1112 /*
1113 * Flow Control has been moved into the RX headers and this out of band
1114 * method isn't used any more.
1115 * remaining backward compatible with older dongles.
1116 */
1117 if (hmb_data & HMB_DATA_FC) {
1118 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1119 HMB_DATA_FCDATA_SHIFT;
1120
1121 if (fcbits & ~bus->flowcontrol)
1122 bus->sdcnt.fc_xoff++;
1123
1124 if (bus->flowcontrol & ~fcbits)
1125 bus->sdcnt.fc_xon++;
1126
1127 bus->sdcnt.fc_rcvd++;
1128 bus->flowcontrol = fcbits;
1129 }
1130
1131 /* Shouldn't be any others */
1132 if (hmb_data & ~(HMB_DATA_DEVREADY |
1133 HMB_DATA_NAKHANDLED |
1134 HMB_DATA_FC |
1135 HMB_DATA_FWREADY |
1136 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1137 brcmf_err("Unknown mailbox data content: 0x%02x\n",
1138 hmb_data);
1139
1140 return intstatus;
1141 }
1142
1143 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
1144 {
1145 uint retries = 0;
1146 u16 lastrbc;
1147 u8 hi, lo;
1148 int err;
1149
1150 brcmf_err("%sterminate frame%s\n",
1151 abort ? "abort command, " : "",
1152 rtx ? ", send NAK" : "");
1153
1154 if (abort)
1155 brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
1156
1157 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
1158 SFC_RF_TERM, &err);
1159 bus->sdcnt.f1regdata++;
1160
1161 /* Wait until the packet has been flushed (device/FIFO stable) */
1162 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1163 hi = brcmf_sdiod_regrb(bus->sdiodev,
1164 SBSDIO_FUNC1_RFRAMEBCHI, &err);
1165 lo = brcmf_sdiod_regrb(bus->sdiodev,
1166 SBSDIO_FUNC1_RFRAMEBCLO, &err);
1167 bus->sdcnt.f1regdata += 2;
1168
1169 if ((hi == 0) && (lo == 0))
1170 break;
1171
1172 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1173 brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1174 lastrbc, (hi << 8) + lo);
1175 }
1176 lastrbc = (hi << 8) + lo;
1177 }
1178
1179 if (!retries)
1180 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
1181 else
1182 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
1183
1184 if (rtx) {
1185 bus->sdcnt.rxrtx++;
1186 err = w_sdreg32(bus, SMB_NAK,
1187 offsetof(struct sdpcmd_regs, tosbmailbox));
1188
1189 bus->sdcnt.f1regdata++;
1190 if (err == 0)
1191 bus->rxskip = true;
1192 }
1193
1194 /* Clear partial in any case */
1195 bus->cur_read.len = 0;
1196 }
1197
1198 static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
1199 {
1200 struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
1201 u8 i, hi, lo;
1202
1203 /* On failure, abort the command and terminate the frame */
1204 brcmf_err("sdio error, abort command and terminate frame\n");
1205 bus->sdcnt.tx_sderrs++;
1206
1207 brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2);
1208 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
1209 bus->sdcnt.f1regdata++;
1210
1211 for (i = 0; i < 3; i++) {
1212 hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
1213 lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
1214 bus->sdcnt.f1regdata += 2;
1215 if ((hi == 0) && (lo == 0))
1216 break;
1217 }
1218 }
1219
1220 /* return total length of buffer chain */
1221 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
1222 {
1223 struct sk_buff *p;
1224 uint total;
1225
1226 total = 0;
1227 skb_queue_walk(&bus->glom, p)
1228 total += p->len;
1229 return total;
1230 }
1231
1232 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
1233 {
1234 struct sk_buff *cur, *next;
1235
1236 skb_queue_walk_safe(&bus->glom, cur, next) {
1237 skb_unlink(cur, &bus->glom);
1238 brcmu_pkt_buf_free_skb(cur);
1239 }
1240 }
1241
1242 /**
1243 * brcmfmac sdio bus specific header
1244 * This is the lowest layer header wrapped on the packets transmitted between
1245 * host and WiFi dongle which contains information needed for SDIO core and
1246 * firmware
1247 *
1248 * It consists of 3 parts: hardware header, hardware extension header and
1249 * software header
1250 * hardware header (frame tag) - 4 bytes
1251 * Byte 0~1: Frame length
1252 * Byte 2~3: Checksum, bit-wise inverse of frame length
1253 * hardware extension header - 8 bytes
1254 * Tx glom mode only, N/A for Rx or normal Tx
1255 * Byte 0~1: Packet length excluding hw frame tag
1256 * Byte 2: Reserved
1257 * Byte 3: Frame flags, bit 0: last frame indication
1258 * Byte 4~5: Reserved
1259 * Byte 6~7: Tail padding length
1260 * software header - 8 bytes
1261 * Byte 0: Rx/Tx sequence number
1262 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1263 * Byte 2: Length of next data frame, reserved for Tx
1264 * Byte 3: Data offset
1265 * Byte 4: Flow control bits, reserved for Tx
1266 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
1267 * Byte 6~7: Reserved
1268 */
1269 #define SDPCM_HWHDR_LEN 4
1270 #define SDPCM_HWEXT_LEN 8
1271 #define SDPCM_SWHDR_LEN 8
1272 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
1273 /* software header */
1274 #define SDPCM_SEQ_MASK 0x000000ff
1275 #define SDPCM_SEQ_WRAP 256
1276 #define SDPCM_CHANNEL_MASK 0x00000f00
1277 #define SDPCM_CHANNEL_SHIFT 8
1278 #define SDPCM_CONTROL_CHANNEL 0 /* Control */
1279 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
1280 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
1281 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
1282 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
1283 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
1284 #define SDPCM_NEXTLEN_MASK 0x00ff0000
1285 #define SDPCM_NEXTLEN_SHIFT 16
1286 #define SDPCM_DOFFSET_MASK 0xff000000
1287 #define SDPCM_DOFFSET_SHIFT 24
1288 #define SDPCM_FCMASK_MASK 0x000000ff
1289 #define SDPCM_WINDOW_MASK 0x0000ff00
1290 #define SDPCM_WINDOW_SHIFT 8
1291
1292 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
1293 {
1294 u32 hdrvalue;
1295 hdrvalue = *(u32 *)swheader;
1296 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
1297 }
1298
1299 static inline bool brcmf_sdio_fromevntchan(u8 *swheader)
1300 {
1301 u32 hdrvalue;
1302 u8 ret;
1303
1304 hdrvalue = *(u32 *)swheader;
1305 ret = (u8)((hdrvalue & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT);
1306
1307 return (ret == SDPCM_EVENT_CHANNEL);
1308 }
1309
1310 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
1311 struct brcmf_sdio_hdrinfo *rd,
1312 enum brcmf_sdio_frmtype type)
1313 {
1314 u16 len, checksum;
1315 u8 rx_seq, fc, tx_seq_max;
1316 u32 swheader;
1317
1318 trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
1319
1320 /* hw header */
1321 len = get_unaligned_le16(header);
1322 checksum = get_unaligned_le16(header + sizeof(u16));
1323 /* All zero means no more to read */
1324 if (!(len | checksum)) {
1325 bus->rxpending = false;
1326 return -ENODATA;
1327 }
1328 if ((u16)(~(len ^ checksum))) {
1329 brcmf_err("HW header checksum error\n");
1330 bus->sdcnt.rx_badhdr++;
1331 brcmf_sdio_rxfail(bus, false, false);
1332 return -EIO;
1333 }
1334 if (len < SDPCM_HDRLEN) {
1335 brcmf_err("HW header length error\n");
1336 return -EPROTO;
1337 }
1338 if (type == BRCMF_SDIO_FT_SUPER &&
1339 (roundup(len, bus->blocksize) != rd->len)) {
1340 brcmf_err("HW superframe header length error\n");
1341 return -EPROTO;
1342 }
1343 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
1344 brcmf_err("HW subframe header length error\n");
1345 return -EPROTO;
1346 }
1347 rd->len = len;
1348
1349 /* software header */
1350 header += SDPCM_HWHDR_LEN;
1351 swheader = le32_to_cpu(*(__le32 *)header);
1352 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
1353 brcmf_err("Glom descriptor found in superframe head\n");
1354 rd->len = 0;
1355 return -EINVAL;
1356 }
1357 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
1358 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
1359 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
1360 type != BRCMF_SDIO_FT_SUPER) {
1361 brcmf_err("HW header length too long\n");
1362 bus->sdcnt.rx_toolong++;
1363 brcmf_sdio_rxfail(bus, false, false);
1364 rd->len = 0;
1365 return -EPROTO;
1366 }
1367 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
1368 brcmf_err("Wrong channel for superframe\n");
1369 rd->len = 0;
1370 return -EINVAL;
1371 }
1372 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
1373 rd->channel != SDPCM_EVENT_CHANNEL) {
1374 brcmf_err("Wrong channel for subframe\n");
1375 rd->len = 0;
1376 return -EINVAL;
1377 }
1378 rd->dat_offset = brcmf_sdio_getdatoffset(header);
1379 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
1380 brcmf_err("seq %d: bad data offset\n", rx_seq);
1381 bus->sdcnt.rx_badhdr++;
1382 brcmf_sdio_rxfail(bus, false, false);
1383 rd->len = 0;
1384 return -ENXIO;
1385 }
1386 if (rd->seq_num != rx_seq) {
1387 brcmf_dbg(SDIO, "seq %d, expected %d\n", rx_seq, rd->seq_num);
1388 bus->sdcnt.rx_badseq++;
1389 rd->seq_num = rx_seq;
1390 }
1391 /* no need to check the reset for subframe */
1392 if (type == BRCMF_SDIO_FT_SUB)
1393 return 0;
1394 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
1395 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
1396 /* only warm for NON glom packet */
1397 if (rd->channel != SDPCM_GLOM_CHANNEL)
1398 brcmf_err("seq %d: next length error\n", rx_seq);
1399 rd->len_nxtfrm = 0;
1400 }
1401 swheader = le32_to_cpu(*(__le32 *)(header + 4));
1402 fc = swheader & SDPCM_FCMASK_MASK;
1403 if (bus->flowcontrol != fc) {
1404 if (~bus->flowcontrol & fc)
1405 bus->sdcnt.fc_xoff++;
1406 if (bus->flowcontrol & ~fc)
1407 bus->sdcnt.fc_xon++;
1408 bus->sdcnt.fc_rcvd++;
1409 bus->flowcontrol = fc;
1410 }
1411 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
1412 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
1413 brcmf_err("seq %d: max tx seq number error\n", rx_seq);
1414 tx_seq_max = bus->tx_seq + 2;
1415 }
1416 bus->tx_max = tx_seq_max;
1417
1418 return 0;
1419 }
1420
1421 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
1422 {
1423 *(__le16 *)header = cpu_to_le16(frm_length);
1424 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
1425 }
1426
1427 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
1428 struct brcmf_sdio_hdrinfo *hd_info)
1429 {
1430 u32 hdrval;
1431 u8 hdr_offset;
1432
1433 brcmf_sdio_update_hwhdr(header, hd_info->len);
1434 hdr_offset = SDPCM_HWHDR_LEN;
1435
1436 if (bus->txglom) {
1437 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
1438 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1439 hdrval = (u16)hd_info->tail_pad << 16;
1440 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
1441 hdr_offset += SDPCM_HWEXT_LEN;
1442 }
1443
1444 hdrval = hd_info->seq_num;
1445 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
1446 SDPCM_CHANNEL_MASK;
1447 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
1448 SDPCM_DOFFSET_MASK;
1449 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1450 *(((__le32 *)(header + hdr_offset)) + 1) = 0;
1451 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
1452 }
1453
1454 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
1455 {
1456 u16 dlen, totlen;
1457 u8 *dptr, num = 0;
1458 u16 sublen;
1459 struct sk_buff *pfirst, *pnext;
1460
1461 int errcode;
1462 u8 doff, sfdoff;
1463
1464 struct brcmf_sdio_hdrinfo rd_new;
1465
1466 /* If packets, issue read(s) and send up packet chain */
1467 /* Return sequence numbers consumed? */
1468
1469 brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
1470 bus->glomd, skb_peek(&bus->glom));
1471
1472 /* If there's a descriptor, generate the packet chain */
1473 if (bus->glomd) {
1474 pfirst = pnext = NULL;
1475 dlen = (u16) (bus->glomd->len);
1476 dptr = bus->glomd->data;
1477 if (!dlen || (dlen & 1)) {
1478 brcmf_err("bad glomd len(%d), ignore descriptor\n",
1479 dlen);
1480 dlen = 0;
1481 }
1482
1483 for (totlen = num = 0; dlen; num++) {
1484 /* Get (and move past) next length */
1485 sublen = get_unaligned_le16(dptr);
1486 dlen -= sizeof(u16);
1487 dptr += sizeof(u16);
1488 if ((sublen < SDPCM_HDRLEN) ||
1489 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1490 brcmf_err("descriptor len %d bad: %d\n",
1491 num, sublen);
1492 pnext = NULL;
1493 break;
1494 }
1495 if (sublen % bus->sgentry_align) {
1496 brcmf_err("sublen %d not multiple of %d\n",
1497 sublen, bus->sgentry_align);
1498 }
1499 totlen += sublen;
1500
1501 /* For last frame, adjust read len so total
1502 is a block multiple */
1503 if (!dlen) {
1504 sublen +=
1505 (roundup(totlen, bus->blocksize) - totlen);
1506 totlen = roundup(totlen, bus->blocksize);
1507 }
1508
1509 /* Allocate/chain packet for next subframe */
1510 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
1511 if (pnext == NULL) {
1512 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
1513 num, sublen);
1514 break;
1515 }
1516 skb_queue_tail(&bus->glom, pnext);
1517
1518 /* Adhere to start alignment requirements */
1519 pkt_align(pnext, sublen, bus->sgentry_align);
1520 }
1521
1522 /* If all allocations succeeded, save packet chain
1523 in bus structure */
1524 if (pnext) {
1525 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1526 totlen, num);
1527 if (BRCMF_GLOM_ON() && bus->cur_read.len &&
1528 totlen != bus->cur_read.len) {
1529 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1530 bus->cur_read.len, totlen, rxseq);
1531 }
1532 pfirst = pnext = NULL;
1533 } else {
1534 brcmf_sdio_free_glom(bus);
1535 num = 0;
1536 }
1537
1538 /* Done with descriptor packet */
1539 brcmu_pkt_buf_free_skb(bus->glomd);
1540 bus->glomd = NULL;
1541 bus->cur_read.len = 0;
1542 }
1543
1544 /* Ok -- either we just generated a packet chain,
1545 or had one from before */
1546 if (!skb_queue_empty(&bus->glom)) {
1547 if (BRCMF_GLOM_ON()) {
1548 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1549 skb_queue_walk(&bus->glom, pnext) {
1550 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1551 pnext, (u8 *) (pnext->data),
1552 pnext->len, pnext->len);
1553 }
1554 }
1555
1556 pfirst = skb_peek(&bus->glom);
1557 dlen = (u16) brcmf_sdio_glom_len(bus);
1558
1559 /* Do an SDIO read for the superframe. Configurable iovar to
1560 * read directly into the chained packet, or allocate a large
1561 * packet and and copy into the chain.
1562 */
1563 sdio_claim_host(bus->sdiodev->func[1]);
1564 errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
1565 &bus->glom, dlen);
1566 sdio_release_host(bus->sdiodev->func[1]);
1567 bus->sdcnt.f2rxdata++;
1568
1569 /* On failure, kill the superframe */
1570 if (errcode < 0) {
1571 brcmf_err("glom read of %d bytes failed: %d\n",
1572 dlen, errcode);
1573
1574 sdio_claim_host(bus->sdiodev->func[1]);
1575 brcmf_sdio_rxfail(bus, true, false);
1576 bus->sdcnt.rxglomfail++;
1577 brcmf_sdio_free_glom(bus);
1578 sdio_release_host(bus->sdiodev->func[1]);
1579 return 0;
1580 }
1581
1582 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1583 pfirst->data, min_t(int, pfirst->len, 48),
1584 "SUPERFRAME:\n");
1585
1586 rd_new.seq_num = rxseq;
1587 rd_new.len = dlen;
1588 sdio_claim_host(bus->sdiodev->func[1]);
1589 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
1590 BRCMF_SDIO_FT_SUPER);
1591 sdio_release_host(bus->sdiodev->func[1]);
1592 bus->cur_read.len = rd_new.len_nxtfrm << 4;
1593
1594 /* Remove superframe header, remember offset */
1595 skb_pull(pfirst, rd_new.dat_offset);
1596 sfdoff = rd_new.dat_offset;
1597 num = 0;
1598
1599 /* Validate all the subframe headers */
1600 skb_queue_walk(&bus->glom, pnext) {
1601 /* leave when invalid subframe is found */
1602 if (errcode)
1603 break;
1604
1605 rd_new.len = pnext->len;
1606 rd_new.seq_num = rxseq++;
1607 sdio_claim_host(bus->sdiodev->func[1]);
1608 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
1609 BRCMF_SDIO_FT_SUB);
1610 sdio_release_host(bus->sdiodev->func[1]);
1611 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1612 pnext->data, 32, "subframe:\n");
1613
1614 num++;
1615 }
1616
1617 if (errcode) {
1618 /* Terminate frame on error */
1619 sdio_claim_host(bus->sdiodev->func[1]);
1620 brcmf_sdio_rxfail(bus, true, false);
1621 bus->sdcnt.rxglomfail++;
1622 brcmf_sdio_free_glom(bus);
1623 sdio_release_host(bus->sdiodev->func[1]);
1624 bus->cur_read.len = 0;
1625 return 0;
1626 }
1627
1628 /* Basic SD framing looks ok - process each packet (header) */
1629
1630 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1631 dptr = (u8 *) (pfirst->data);
1632 sublen = get_unaligned_le16(dptr);
1633 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
1634
1635 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1636 dptr, pfirst->len,
1637 "Rx Subframe Data:\n");
1638
1639 __skb_trim(pfirst, sublen);
1640 skb_pull(pfirst, doff);
1641
1642 if (pfirst->len == 0) {
1643 skb_unlink(pfirst, &bus->glom);
1644 brcmu_pkt_buf_free_skb(pfirst);
1645 continue;
1646 }
1647
1648 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1649 pfirst->data,
1650 min_t(int, pfirst->len, 32),
1651 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1652 bus->glom.qlen, pfirst, pfirst->data,
1653 pfirst->len, pfirst->next,
1654 pfirst->prev);
1655 skb_unlink(pfirst, &bus->glom);
1656 if (brcmf_sdio_fromevntchan(pfirst->data))
1657 brcmf_rx_event(bus->sdiodev->dev, pfirst);
1658 else
1659 brcmf_rx_frame(bus->sdiodev->dev, pfirst,
1660 false);
1661 bus->sdcnt.rxglompkts++;
1662 }
1663
1664 bus->sdcnt.rxglomframes++;
1665 }
1666 return num;
1667 }
1668
1669 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
1670 bool *pending)
1671 {
1672 DECLARE_WAITQUEUE(wait, current);
1673 int timeout = DCMD_RESP_TIMEOUT;
1674
1675 /* Wait until control frame is available */
1676 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1677 set_current_state(TASK_INTERRUPTIBLE);
1678
1679 while (!(*condition) && (!signal_pending(current) && timeout))
1680 timeout = schedule_timeout(timeout);
1681
1682 if (signal_pending(current))
1683 *pending = true;
1684
1685 set_current_state(TASK_RUNNING);
1686 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1687
1688 return timeout;
1689 }
1690
1691 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
1692 {
1693 wake_up_interruptible(&bus->dcmd_resp_wait);
1694
1695 return 0;
1696 }
1697 static void
1698 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
1699 {
1700 uint rdlen, pad;
1701 u8 *buf = NULL, *rbuf;
1702 int sdret;
1703
1704 brcmf_dbg(TRACE, "Enter\n");
1705
1706 if (bus->rxblen)
1707 buf = vzalloc(bus->rxblen);
1708 if (!buf)
1709 goto done;
1710
1711 rbuf = bus->rxbuf;
1712 pad = ((unsigned long)rbuf % bus->head_align);
1713 if (pad)
1714 rbuf += (bus->head_align - pad);
1715
1716 /* Copy the already-read portion over */
1717 memcpy(buf, hdr, BRCMF_FIRSTREAD);
1718 if (len <= BRCMF_FIRSTREAD)
1719 goto gotpkt;
1720
1721 /* Raise rdlen to next SDIO block to avoid tail command */
1722 rdlen = len - BRCMF_FIRSTREAD;
1723 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1724 pad = bus->blocksize - (rdlen % bus->blocksize);
1725 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1726 ((len + pad) < bus->sdiodev->bus_if->maxctl))
1727 rdlen += pad;
1728 } else if (rdlen % bus->head_align) {
1729 rdlen += bus->head_align - (rdlen % bus->head_align);
1730 }
1731
1732 /* Drop if the read is too big or it exceeds our maximum */
1733 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
1734 brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
1735 rdlen, bus->sdiodev->bus_if->maxctl);
1736 brcmf_sdio_rxfail(bus, false, false);
1737 goto done;
1738 }
1739
1740 if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
1741 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1742 len, len - doff, bus->sdiodev->bus_if->maxctl);
1743 bus->sdcnt.rx_toolong++;
1744 brcmf_sdio_rxfail(bus, false, false);
1745 goto done;
1746 }
1747
1748 /* Read remain of frame body */
1749 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
1750 bus->sdcnt.f2rxdata++;
1751
1752 /* Control frame failures need retransmission */
1753 if (sdret < 0) {
1754 brcmf_err("read %d control bytes failed: %d\n",
1755 rdlen, sdret);
1756 bus->sdcnt.rxc_errors++;
1757 brcmf_sdio_rxfail(bus, true, true);
1758 goto done;
1759 } else
1760 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
1761
1762 gotpkt:
1763
1764 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1765 buf, len, "RxCtrl:\n");
1766
1767 /* Point to valid data and indicate its length */
1768 spin_lock_bh(&bus->rxctl_lock);
1769 if (bus->rxctl) {
1770 brcmf_err("last control frame is being processed.\n");
1771 spin_unlock_bh(&bus->rxctl_lock);
1772 vfree(buf);
1773 goto done;
1774 }
1775 bus->rxctl = buf + doff;
1776 bus->rxctl_orig = buf;
1777 bus->rxlen = len - doff;
1778 spin_unlock_bh(&bus->rxctl_lock);
1779
1780 done:
1781 /* Awake any waiters */
1782 brcmf_sdio_dcmd_resp_wake(bus);
1783 }
1784
1785 /* Pad read to blocksize for efficiency */
1786 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
1787 {
1788 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1789 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1790 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1791 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1792 *rdlen += *pad;
1793 } else if (*rdlen % bus->head_align) {
1794 *rdlen += bus->head_align - (*rdlen % bus->head_align);
1795 }
1796 }
1797
1798 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
1799 {
1800 struct sk_buff *pkt; /* Packet for event or data frames */
1801 u16 pad; /* Number of pad bytes to read */
1802 uint rxleft = 0; /* Remaining number of frames allowed */
1803 int ret; /* Return code from calls */
1804 uint rxcount = 0; /* Total frames read */
1805 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
1806 u8 head_read = 0;
1807
1808 brcmf_dbg(TRACE, "Enter\n");
1809
1810 /* Not finished unless we encounter no more frames indication */
1811 bus->rxpending = true;
1812
1813 for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
1814 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA;
1815 rd->seq_num++, rxleft--) {
1816
1817 /* Handle glomming separately */
1818 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1819 u8 cnt;
1820 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1821 bus->glomd, skb_peek(&bus->glom));
1822 cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
1823 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1824 rd->seq_num += cnt - 1;
1825 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1826 continue;
1827 }
1828
1829 rd->len_left = rd->len;
1830 /* read header first for unknow frame length */
1831 sdio_claim_host(bus->sdiodev->func[1]);
1832 if (!rd->len) {
1833 ret = brcmf_sdiod_recv_buf(bus->sdiodev,
1834 bus->rxhdr, BRCMF_FIRSTREAD);
1835 bus->sdcnt.f2rxhdrs++;
1836 if (ret < 0) {
1837 brcmf_err("RXHEADER FAILED: %d\n",
1838 ret);
1839 bus->sdcnt.rx_hdrfail++;
1840 brcmf_sdio_rxfail(bus, true, true);
1841 sdio_release_host(bus->sdiodev->func[1]);
1842 continue;
1843 }
1844
1845 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1846 bus->rxhdr, SDPCM_HDRLEN,
1847 "RxHdr:\n");
1848
1849 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
1850 BRCMF_SDIO_FT_NORMAL)) {
1851 sdio_release_host(bus->sdiodev->func[1]);
1852 if (!bus->rxpending)
1853 break;
1854 else
1855 continue;
1856 }
1857
1858 if (rd->channel == SDPCM_CONTROL_CHANNEL) {
1859 brcmf_sdio_read_control(bus, bus->rxhdr,
1860 rd->len,
1861 rd->dat_offset);
1862 /* prepare the descriptor for the next read */
1863 rd->len = rd->len_nxtfrm << 4;
1864 rd->len_nxtfrm = 0;
1865 /* treat all packet as event if we don't know */
1866 rd->channel = SDPCM_EVENT_CHANNEL;
1867 sdio_release_host(bus->sdiodev->func[1]);
1868 continue;
1869 }
1870 rd->len_left = rd->len > BRCMF_FIRSTREAD ?
1871 rd->len - BRCMF_FIRSTREAD : 0;
1872 head_read = BRCMF_FIRSTREAD;
1873 }
1874
1875 brcmf_sdio_pad(bus, &pad, &rd->len_left);
1876
1877 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
1878 bus->head_align);
1879 if (!pkt) {
1880 /* Give up on data, request rtx of events */
1881 brcmf_err("brcmu_pkt_buf_get_skb failed\n");
1882 brcmf_sdio_rxfail(bus, false,
1883 RETRYCHAN(rd->channel));
1884 sdio_release_host(bus->sdiodev->func[1]);
1885 continue;
1886 }
1887 skb_pull(pkt, head_read);
1888 pkt_align(pkt, rd->len_left, bus->head_align);
1889
1890 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
1891 bus->sdcnt.f2rxdata++;
1892 sdio_release_host(bus->sdiodev->func[1]);
1893
1894 if (ret < 0) {
1895 brcmf_err("read %d bytes from channel %d failed: %d\n",
1896 rd->len, rd->channel, ret);
1897 brcmu_pkt_buf_free_skb(pkt);
1898 sdio_claim_host(bus->sdiodev->func[1]);
1899 brcmf_sdio_rxfail(bus, true,
1900 RETRYCHAN(rd->channel));
1901 sdio_release_host(bus->sdiodev->func[1]);
1902 continue;
1903 }
1904
1905 if (head_read) {
1906 skb_push(pkt, head_read);
1907 memcpy(pkt->data, bus->rxhdr, head_read);
1908 head_read = 0;
1909 } else {
1910 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
1911 rd_new.seq_num = rd->seq_num;
1912 sdio_claim_host(bus->sdiodev->func[1]);
1913 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
1914 BRCMF_SDIO_FT_NORMAL)) {
1915 rd->len = 0;
1916 brcmu_pkt_buf_free_skb(pkt);
1917 }
1918 bus->sdcnt.rx_readahead_cnt++;
1919 if (rd->len != roundup(rd_new.len, 16)) {
1920 brcmf_err("frame length mismatch:read %d, should be %d\n",
1921 rd->len,
1922 roundup(rd_new.len, 16) >> 4);
1923 rd->len = 0;
1924 brcmf_sdio_rxfail(bus, true, true);
1925 sdio_release_host(bus->sdiodev->func[1]);
1926 brcmu_pkt_buf_free_skb(pkt);
1927 continue;
1928 }
1929 sdio_release_host(bus->sdiodev->func[1]);
1930 rd->len_nxtfrm = rd_new.len_nxtfrm;
1931 rd->channel = rd_new.channel;
1932 rd->dat_offset = rd_new.dat_offset;
1933
1934 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
1935 BRCMF_DATA_ON()) &&
1936 BRCMF_HDRS_ON(),
1937 bus->rxhdr, SDPCM_HDRLEN,
1938 "RxHdr:\n");
1939
1940 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
1941 brcmf_err("readahead on control packet %d?\n",
1942 rd_new.seq_num);
1943 /* Force retry w/normal header read */
1944 rd->len = 0;
1945 sdio_claim_host(bus->sdiodev->func[1]);
1946 brcmf_sdio_rxfail(bus, false, true);
1947 sdio_release_host(bus->sdiodev->func[1]);
1948 brcmu_pkt_buf_free_skb(pkt);
1949 continue;
1950 }
1951 }
1952
1953 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1954 pkt->data, rd->len, "Rx Data:\n");
1955
1956 /* Save superframe descriptor and allocate packet frame */
1957 if (rd->channel == SDPCM_GLOM_CHANNEL) {
1958 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
1959 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
1960 rd->len);
1961 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1962 pkt->data, rd->len,
1963 "Glom Data:\n");
1964 __skb_trim(pkt, rd->len);
1965 skb_pull(pkt, SDPCM_HDRLEN);
1966 bus->glomd = pkt;
1967 } else {
1968 brcmf_err("%s: glom superframe w/o "
1969 "descriptor!\n", __func__);
1970 sdio_claim_host(bus->sdiodev->func[1]);
1971 brcmf_sdio_rxfail(bus, false, false);
1972 sdio_release_host(bus->sdiodev->func[1]);
1973 }
1974 /* prepare the descriptor for the next read */
1975 rd->len = rd->len_nxtfrm << 4;
1976 rd->len_nxtfrm = 0;
1977 /* treat all packet as event if we don't know */
1978 rd->channel = SDPCM_EVENT_CHANNEL;
1979 continue;
1980 }
1981
1982 /* Fill in packet len and prio, deliver upward */
1983 __skb_trim(pkt, rd->len);
1984 skb_pull(pkt, rd->dat_offset);
1985
1986 if (pkt->len == 0)
1987 brcmu_pkt_buf_free_skb(pkt);
1988 else if (rd->channel == SDPCM_EVENT_CHANNEL)
1989 brcmf_rx_event(bus->sdiodev->dev, pkt);
1990 else
1991 brcmf_rx_frame(bus->sdiodev->dev, pkt,
1992 false);
1993
1994 /* prepare the descriptor for the next read */
1995 rd->len = rd->len_nxtfrm << 4;
1996 rd->len_nxtfrm = 0;
1997 /* treat all packet as event if we don't know */
1998 rd->channel = SDPCM_EVENT_CHANNEL;
1999 }
2000
2001 rxcount = maxframes - rxleft;
2002 /* Message if we hit the limit */
2003 if (!rxleft)
2004 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
2005 else
2006 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2007 /* Back off rxseq if awaiting rtx, update rx_seq */
2008 if (bus->rxskip)
2009 rd->seq_num--;
2010 bus->rx_seq = rd->seq_num;
2011
2012 return rxcount;
2013 }
2014
2015 static void
2016 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
2017 {
2018 wake_up_interruptible(&bus->ctrl_wait);
2019 return;
2020 }
2021
2022 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
2023 {
2024 u16 head_pad;
2025 u8 *dat_buf;
2026
2027 dat_buf = (u8 *)(pkt->data);
2028
2029 /* Check head padding */
2030 head_pad = ((unsigned long)dat_buf % bus->head_align);
2031 if (head_pad) {
2032 if (skb_headroom(pkt) < head_pad) {
2033 bus->sdiodev->bus_if->tx_realloc++;
2034 head_pad = 0;
2035 if (skb_cow(pkt, head_pad))
2036 return -ENOMEM;
2037 }
2038 skb_push(pkt, head_pad);
2039 dat_buf = (u8 *)(pkt->data);
2040 memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
2041 }
2042 return head_pad;
2043 }
2044
2045 /**
2046 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
2047 * bus layer usage.
2048 */
2049 /* flag marking a dummy skb added for DMA alignment requirement */
2050 #define ALIGN_SKB_FLAG 0x8000
2051 /* bit mask of data length chopped from the previous packet */
2052 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
2053
2054 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
2055 struct sk_buff_head *pktq,
2056 struct sk_buff *pkt, u16 total_len)
2057 {
2058 struct brcmf_sdio_dev *sdiodev;
2059 struct sk_buff *pkt_pad;
2060 u16 tail_pad, tail_chop, chain_pad;
2061 unsigned int blksize;
2062 bool lastfrm;
2063 int ntail, ret;
2064
2065 sdiodev = bus->sdiodev;
2066 blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize;
2067 /* sg entry alignment should be a divisor of block size */
2068 WARN_ON(blksize % bus->sgentry_align);
2069
2070 /* Check tail padding */
2071 lastfrm = skb_queue_is_last(pktq, pkt);
2072 tail_pad = 0;
2073 tail_chop = pkt->len % bus->sgentry_align;
2074 if (tail_chop)
2075 tail_pad = bus->sgentry_align - tail_chop;
2076 chain_pad = (total_len + tail_pad) % blksize;
2077 if (lastfrm && chain_pad)
2078 tail_pad += blksize - chain_pad;
2079 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
2080 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
2081 bus->head_align);
2082 if (pkt_pad == NULL)
2083 return -ENOMEM;
2084 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
2085 if (unlikely(ret < 0)) {
2086 kfree_skb(pkt_pad);
2087 return ret;
2088 }
2089 memcpy(pkt_pad->data,
2090 pkt->data + pkt->len - tail_chop,
2091 tail_chop);
2092 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
2093 skb_trim(pkt, pkt->len - tail_chop);
2094 skb_trim(pkt_pad, tail_pad + tail_chop);
2095 __skb_queue_after(pktq, pkt, pkt_pad);
2096 } else {
2097 ntail = pkt->data_len + tail_pad -
2098 (pkt->end - pkt->tail);
2099 if (skb_cloned(pkt) || ntail > 0)
2100 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
2101 return -ENOMEM;
2102 if (skb_linearize(pkt))
2103 return -ENOMEM;
2104 __skb_put(pkt, tail_pad);
2105 }
2106
2107 return tail_pad;
2108 }
2109
2110 /**
2111 * brcmf_sdio_txpkt_prep - packet preparation for transmit
2112 * @bus: brcmf_sdio structure pointer
2113 * @pktq: packet list pointer
2114 * @chan: virtual channel to transmit the packet
2115 *
2116 * Processes to be applied to the packet
2117 * - Align data buffer pointer
2118 * - Align data buffer length
2119 * - Prepare header
2120 * Return: negative value if there is error
2121 */
2122 static int
2123 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2124 uint chan)
2125 {
2126 u16 head_pad, total_len;
2127 struct sk_buff *pkt_next;
2128 u8 txseq;
2129 int ret;
2130 struct brcmf_sdio_hdrinfo hd_info = {0};
2131
2132 txseq = bus->tx_seq;
2133 total_len = 0;
2134 skb_queue_walk(pktq, pkt_next) {
2135 /* alignment packet inserted in previous
2136 * loop cycle can be skipped as it is
2137 * already properly aligned and does not
2138 * need an sdpcm header.
2139 */
2140 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
2141 continue;
2142
2143 /* align packet data pointer */
2144 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
2145 if (ret < 0)
2146 return ret;
2147 head_pad = (u16)ret;
2148 if (head_pad)
2149 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
2150
2151 total_len += pkt_next->len;
2152
2153 hd_info.len = pkt_next->len;
2154 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
2155 if (bus->txglom && pktq->qlen > 1) {
2156 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
2157 pkt_next, total_len);
2158 if (ret < 0)
2159 return ret;
2160 hd_info.tail_pad = (u16)ret;
2161 total_len += (u16)ret;
2162 }
2163
2164 hd_info.channel = chan;
2165 hd_info.dat_offset = head_pad + bus->tx_hdrlen;
2166 hd_info.seq_num = txseq++;
2167
2168 /* Now fill the header */
2169 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
2170
2171 if (BRCMF_BYTES_ON() &&
2172 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
2173 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
2174 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len,
2175 "Tx Frame:\n");
2176 else if (BRCMF_HDRS_ON())
2177 brcmf_dbg_hex_dump(true, pkt_next->data,
2178 head_pad + bus->tx_hdrlen,
2179 "Tx Header:\n");
2180 }
2181 /* Hardware length tag of the first packet should be total
2182 * length of the chain (including padding)
2183 */
2184 if (bus->txglom)
2185 brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
2186 return 0;
2187 }
2188
2189 /**
2190 * brcmf_sdio_txpkt_postp - packet post processing for transmit
2191 * @bus: brcmf_sdio structure pointer
2192 * @pktq: packet list pointer
2193 *
2194 * Processes to be applied to the packet
2195 * - Remove head padding
2196 * - Remove tail padding
2197 */
2198 static void
2199 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
2200 {
2201 u8 *hdr;
2202 u32 dat_offset;
2203 u16 tail_pad;
2204 u16 dummy_flags, chop_len;
2205 struct sk_buff *pkt_next, *tmp, *pkt_prev;
2206
2207 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2208 dummy_flags = *(u16 *)(pkt_next->cb);
2209 if (dummy_flags & ALIGN_SKB_FLAG) {
2210 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
2211 if (chop_len) {
2212 pkt_prev = pkt_next->prev;
2213 skb_put(pkt_prev, chop_len);
2214 }
2215 __skb_unlink(pkt_next, pktq);
2216 brcmu_pkt_buf_free_skb(pkt_next);
2217 } else {
2218 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
2219 dat_offset = le32_to_cpu(*(__le32 *)hdr);
2220 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
2221 SDPCM_DOFFSET_SHIFT;
2222 skb_pull(pkt_next, dat_offset);
2223 if (bus->txglom) {
2224 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
2225 skb_trim(pkt_next, pkt_next->len - tail_pad);
2226 }
2227 }
2228 }
2229 }
2230
2231 /* Writes a HW/SW header into the packet and sends it. */
2232 /* Assumes: (a) header space already there, (b) caller holds lock */
2233 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2234 uint chan)
2235 {
2236 int ret;
2237 struct sk_buff *pkt_next, *tmp;
2238
2239 brcmf_dbg(TRACE, "Enter\n");
2240
2241 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
2242 if (ret)
2243 goto done;
2244
2245 sdio_claim_host(bus->sdiodev->func[1]);
2246 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
2247 bus->sdcnt.f2txdata++;
2248
2249 if (ret < 0)
2250 brcmf_sdio_txfail(bus);
2251
2252 sdio_release_host(bus->sdiodev->func[1]);
2253
2254 done:
2255 brcmf_sdio_txpkt_postp(bus, pktq);
2256 if (ret == 0)
2257 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
2258 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2259 __skb_unlink(pkt_next, pktq);
2260 brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0);
2261 }
2262 return ret;
2263 }
2264
2265 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
2266 {
2267 struct sk_buff *pkt;
2268 struct sk_buff_head pktq;
2269 u32 intstatus = 0;
2270 int ret = 0, prec_out, i;
2271 uint cnt = 0;
2272 u8 tx_prec_map, pkt_num;
2273
2274 brcmf_dbg(TRACE, "Enter\n");
2275
2276 tx_prec_map = ~bus->flowcontrol;
2277
2278 /* Send frames until the limit or some other event */
2279 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
2280 pkt_num = 1;
2281 if (bus->txglom)
2282 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
2283 bus->sdiodev->txglomsz);
2284 pkt_num = min_t(u32, pkt_num,
2285 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
2286 __skb_queue_head_init(&pktq);
2287 spin_lock_bh(&bus->txq_lock);
2288 for (i = 0; i < pkt_num; i++) {
2289 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
2290 &prec_out);
2291 if (pkt == NULL)
2292 break;
2293 __skb_queue_tail(&pktq, pkt);
2294 }
2295 spin_unlock_bh(&bus->txq_lock);
2296 if (i == 0)
2297 break;
2298
2299 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
2300
2301 cnt += i;
2302
2303 /* In poll mode, need to check for other events */
2304 if (!bus->intr) {
2305 /* Check device status, signal pending interrupt */
2306 sdio_claim_host(bus->sdiodev->func[1]);
2307 ret = r_sdreg32(bus, &intstatus,
2308 offsetof(struct sdpcmd_regs,
2309 intstatus));
2310 sdio_release_host(bus->sdiodev->func[1]);
2311 bus->sdcnt.f2txdata++;
2312 if (ret != 0)
2313 break;
2314 if (intstatus & bus->hostintmask)
2315 atomic_set(&bus->ipend, 1);
2316 }
2317 }
2318
2319 /* Deflow-control stack if needed */
2320 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) &&
2321 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
2322 bus->txoff = false;
2323 brcmf_txflowblock(bus->sdiodev->dev, false);
2324 }
2325
2326 return cnt;
2327 }
2328
2329 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
2330 {
2331 u8 doff;
2332 u16 pad;
2333 uint retries = 0;
2334 struct brcmf_sdio_hdrinfo hd_info = {0};
2335 int ret;
2336
2337 brcmf_dbg(TRACE, "Enter\n");
2338
2339 /* Back the pointer to make room for bus header */
2340 frame -= bus->tx_hdrlen;
2341 len += bus->tx_hdrlen;
2342
2343 /* Add alignment padding (optional for ctl frames) */
2344 doff = ((unsigned long)frame % bus->head_align);
2345 if (doff) {
2346 frame -= doff;
2347 len += doff;
2348 memset(frame + bus->tx_hdrlen, 0, doff);
2349 }
2350
2351 /* Round send length to next SDIO block */
2352 pad = 0;
2353 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2354 pad = bus->blocksize - (len % bus->blocksize);
2355 if ((pad > bus->roundup) || (pad >= bus->blocksize))
2356 pad = 0;
2357 } else if (len % bus->head_align) {
2358 pad = bus->head_align - (len % bus->head_align);
2359 }
2360 len += pad;
2361
2362 hd_info.len = len - pad;
2363 hd_info.channel = SDPCM_CONTROL_CHANNEL;
2364 hd_info.dat_offset = doff + bus->tx_hdrlen;
2365 hd_info.seq_num = bus->tx_seq;
2366 hd_info.lastfrm = true;
2367 hd_info.tail_pad = pad;
2368 brcmf_sdio_hdpack(bus, frame, &hd_info);
2369
2370 if (bus->txglom)
2371 brcmf_sdio_update_hwhdr(frame, len);
2372
2373 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2374 frame, len, "Tx Frame:\n");
2375 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2376 BRCMF_HDRS_ON(),
2377 frame, min_t(u16, len, 16), "TxHdr:\n");
2378
2379 do {
2380 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
2381
2382 if (ret < 0)
2383 brcmf_sdio_txfail(bus);
2384 else
2385 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2386 } while (ret < 0 && retries++ < TXRETRIES);
2387
2388 return ret;
2389 }
2390
2391 static void brcmf_sdio_bus_stop(struct device *dev)
2392 {
2393 u32 local_hostintmask;
2394 u8 saveclk;
2395 int err;
2396 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2397 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2398 struct brcmf_sdio *bus = sdiodev->bus;
2399
2400 brcmf_dbg(TRACE, "Enter\n");
2401
2402 if (bus->watchdog_tsk) {
2403 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2404 kthread_stop(bus->watchdog_tsk);
2405 bus->watchdog_tsk = NULL;
2406 }
2407
2408 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
2409 sdio_claim_host(sdiodev->func[1]);
2410
2411 /* Enable clock for device interrupts */
2412 brcmf_sdio_bus_sleep(bus, false, false);
2413
2414 /* Disable and clear interrupts at the chip level also */
2415 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
2416 local_hostintmask = bus->hostintmask;
2417 bus->hostintmask = 0;
2418
2419 /* Force backplane clocks to assure F2 interrupt propagates */
2420 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2421 &err);
2422 if (!err)
2423 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2424 (saveclk | SBSDIO_FORCE_HT), &err);
2425 if (err)
2426 brcmf_err("Failed to force clock for F2: err %d\n",
2427 err);
2428
2429 /* Turn off the bus (F2), free any pending packets */
2430 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2431 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
2432
2433 /* Clear any pending interrupts now that F2 is disabled */
2434 w_sdreg32(bus, local_hostintmask,
2435 offsetof(struct sdpcmd_regs, intstatus));
2436
2437 sdio_release_host(sdiodev->func[1]);
2438 }
2439 /* Clear the data packet queues */
2440 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2441
2442 /* Clear any held glomming stuff */
2443 brcmu_pkt_buf_free_skb(bus->glomd);
2444 brcmf_sdio_free_glom(bus);
2445
2446 /* Clear rx control and wake any waiters */
2447 spin_lock_bh(&bus->rxctl_lock);
2448 bus->rxlen = 0;
2449 spin_unlock_bh(&bus->rxctl_lock);
2450 brcmf_sdio_dcmd_resp_wake(bus);
2451
2452 /* Reset some F2 state stuff */
2453 bus->rxskip = false;
2454 bus->tx_seq = bus->rx_seq = 0;
2455 }
2456
2457 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
2458 {
2459 struct brcmf_sdio_dev *sdiodev;
2460 unsigned long flags;
2461
2462 sdiodev = bus->sdiodev;
2463 if (sdiodev->oob_irq_requested) {
2464 spin_lock_irqsave(&sdiodev->irq_en_lock, flags);
2465 if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) {
2466 enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr);
2467 sdiodev->irq_en = true;
2468 }
2469 spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags);
2470 }
2471 }
2472
2473 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
2474 {
2475 struct brcmf_core *buscore;
2476 u32 addr;
2477 unsigned long val;
2478 int ret;
2479
2480 buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
2481 addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus);
2482
2483 val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret);
2484 bus->sdcnt.f1regdata++;
2485 if (ret != 0)
2486 return ret;
2487
2488 val &= bus->hostintmask;
2489 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
2490
2491 /* Clear interrupts */
2492 if (val) {
2493 brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret);
2494 bus->sdcnt.f1regdata++;
2495 atomic_or(val, &bus->intstatus);
2496 }
2497
2498 return ret;
2499 }
2500
2501 static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
2502 {
2503 u32 newstatus = 0;
2504 unsigned long intstatus;
2505 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2506 uint framecnt; /* Temporary counter of tx/rx frames */
2507 int err = 0;
2508
2509 brcmf_dbg(TRACE, "Enter\n");
2510
2511 sdio_claim_host(bus->sdiodev->func[1]);
2512
2513 /* If waiting for HTAVAIL, check status */
2514 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
2515 u8 clkctl, devctl = 0;
2516
2517 #ifdef DEBUG
2518 /* Check for inconsistent device control */
2519 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2520 SBSDIO_DEVICE_CTL, &err);
2521 #endif /* DEBUG */
2522
2523 /* Read CSR, if clock on switch to AVAIL, else ignore */
2524 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
2525 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2526
2527 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2528 devctl, clkctl);
2529
2530 if (SBSDIO_HTAV(clkctl)) {
2531 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2532 SBSDIO_DEVICE_CTL, &err);
2533 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2534 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
2535 devctl, &err);
2536 bus->clkstate = CLK_AVAIL;
2537 }
2538 }
2539
2540 /* Make sure backplane clock is on */
2541 brcmf_sdio_bus_sleep(bus, false, true);
2542
2543 /* Pending interrupt indicates new device status */
2544 if (atomic_read(&bus->ipend) > 0) {
2545 atomic_set(&bus->ipend, 0);
2546 err = brcmf_sdio_intr_rstatus(bus);
2547 }
2548
2549 /* Start with leftover status bits */
2550 intstatus = atomic_xchg(&bus->intstatus, 0);
2551
2552 /* Handle flow-control change: read new state in case our ack
2553 * crossed another change interrupt. If change still set, assume
2554 * FC ON for safety, let next loop through do the debounce.
2555 */
2556 if (intstatus & I_HMB_FC_CHANGE) {
2557 intstatus &= ~I_HMB_FC_CHANGE;
2558 err = w_sdreg32(bus, I_HMB_FC_CHANGE,
2559 offsetof(struct sdpcmd_regs, intstatus));
2560
2561 err = r_sdreg32(bus, &newstatus,
2562 offsetof(struct sdpcmd_regs, intstatus));
2563 bus->sdcnt.f1regdata += 2;
2564 atomic_set(&bus->fcstate,
2565 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
2566 intstatus |= (newstatus & bus->hostintmask);
2567 }
2568
2569 /* Handle host mailbox indication */
2570 if (intstatus & I_HMB_HOST_INT) {
2571 intstatus &= ~I_HMB_HOST_INT;
2572 intstatus |= brcmf_sdio_hostmail(bus);
2573 }
2574
2575 sdio_release_host(bus->sdiodev->func[1]);
2576
2577 /* Generally don't ask for these, can get CRC errors... */
2578 if (intstatus & I_WR_OOSYNC) {
2579 brcmf_err("Dongle reports WR_OOSYNC\n");
2580 intstatus &= ~I_WR_OOSYNC;
2581 }
2582
2583 if (intstatus & I_RD_OOSYNC) {
2584 brcmf_err("Dongle reports RD_OOSYNC\n");
2585 intstatus &= ~I_RD_OOSYNC;
2586 }
2587
2588 if (intstatus & I_SBINT) {
2589 brcmf_err("Dongle reports SBINT\n");
2590 intstatus &= ~I_SBINT;
2591 }
2592
2593 /* Would be active due to wake-wlan in gSPI */
2594 if (intstatus & I_CHIPACTIVE) {
2595 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2596 intstatus &= ~I_CHIPACTIVE;
2597 }
2598
2599 /* Ignore frame indications if rxskip is set */
2600 if (bus->rxskip)
2601 intstatus &= ~I_HMB_FRAME_IND;
2602
2603 /* On frame indication, read available frames */
2604 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) {
2605 brcmf_sdio_readframes(bus, bus->rxbound);
2606 if (!bus->rxpending)
2607 intstatus &= ~I_HMB_FRAME_IND;
2608 }
2609
2610 /* Keep still-pending events for next scheduling */
2611 if (intstatus)
2612 atomic_or(intstatus, &bus->intstatus);
2613
2614 brcmf_sdio_clrintr(bus);
2615
2616 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) &&
2617 data_ok(bus)) {
2618 sdio_claim_host(bus->sdiodev->func[1]);
2619 if (bus->ctrl_frame_stat) {
2620 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf,
2621 bus->ctrl_frame_len);
2622 bus->ctrl_frame_err = err;
2623 wmb();
2624 bus->ctrl_frame_stat = false;
2625 }
2626 sdio_release_host(bus->sdiodev->func[1]);
2627 brcmf_sdio_wait_event_wakeup(bus);
2628 }
2629 /* Send queued frames (limit 1 if rx may still be pending) */
2630 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
2631 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit &&
2632 data_ok(bus)) {
2633 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
2634 txlimit;
2635 brcmf_sdio_sendfromq(bus, framecnt);
2636 }
2637
2638 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) {
2639 brcmf_err("failed backplane access over SDIO, halting operation\n");
2640 atomic_set(&bus->intstatus, 0);
2641 if (bus->ctrl_frame_stat) {
2642 sdio_claim_host(bus->sdiodev->func[1]);
2643 if (bus->ctrl_frame_stat) {
2644 bus->ctrl_frame_err = -ENODEV;
2645 wmb();
2646 bus->ctrl_frame_stat = false;
2647 brcmf_sdio_wait_event_wakeup(bus);
2648 }
2649 sdio_release_host(bus->sdiodev->func[1]);
2650 }
2651 } else if (atomic_read(&bus->intstatus) ||
2652 atomic_read(&bus->ipend) > 0 ||
2653 (!atomic_read(&bus->fcstate) &&
2654 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
2655 data_ok(bus))) {
2656 bus->dpc_triggered = true;
2657 }
2658 }
2659
2660 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
2661 {
2662 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2663 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2664 struct brcmf_sdio *bus = sdiodev->bus;
2665
2666 return &bus->txq;
2667 }
2668
2669 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec)
2670 {
2671 struct sk_buff *p;
2672 int eprec = -1; /* precedence to evict from */
2673
2674 /* Fast case, precedence queue is not full and we are also not
2675 * exceeding total queue length
2676 */
2677 if (!pktq_pfull(q, prec) && !pktq_full(q)) {
2678 brcmu_pktq_penq(q, prec, pkt);
2679 return true;
2680 }
2681
2682 /* Determine precedence from which to evict packet, if any */
2683 if (pktq_pfull(q, prec)) {
2684 eprec = prec;
2685 } else if (pktq_full(q)) {
2686 p = brcmu_pktq_peek_tail(q, &eprec);
2687 if (eprec > prec)
2688 return false;
2689 }
2690
2691 /* Evict if needed */
2692 if (eprec >= 0) {
2693 /* Detect queueing to unconfigured precedence */
2694 if (eprec == prec)
2695 return false; /* refuse newer (incoming) packet */
2696 /* Evict packet according to discard policy */
2697 p = brcmu_pktq_pdeq_tail(q, eprec);
2698 if (p == NULL)
2699 brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
2700 brcmu_pkt_buf_free_skb(p);
2701 }
2702
2703 /* Enqueue */
2704 p = brcmu_pktq_penq(q, prec, pkt);
2705 if (p == NULL)
2706 brcmf_err("brcmu_pktq_penq() failed\n");
2707
2708 return p != NULL;
2709 }
2710
2711 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
2712 {
2713 int ret = -EBADE;
2714 uint prec;
2715 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2716 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2717 struct brcmf_sdio *bus = sdiodev->bus;
2718
2719 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len);
2720 if (sdiodev->state != BRCMF_SDIOD_DATA)
2721 return -EIO;
2722
2723 /* Add space for the header */
2724 skb_push(pkt, bus->tx_hdrlen);
2725 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2726
2727 prec = prio2prec((pkt->priority & PRIOMASK));
2728
2729 /* Check for existing queue, current flow-control,
2730 pending event, or pending clock */
2731 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2732 bus->sdcnt.fcqueued++;
2733
2734 /* Priority based enq */
2735 spin_lock_bh(&bus->txq_lock);
2736 /* reset bus_flags in packet cb */
2737 *(u16 *)(pkt->cb) = 0;
2738 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) {
2739 skb_pull(pkt, bus->tx_hdrlen);
2740 brcmf_err("out of bus->txq !!!\n");
2741 ret = -ENOSR;
2742 } else {
2743 ret = 0;
2744 }
2745
2746 if (pktq_len(&bus->txq) >= TXHI) {
2747 bus->txoff = true;
2748 brcmf_txflowblock(dev, true);
2749 }
2750 spin_unlock_bh(&bus->txq_lock);
2751
2752 #ifdef DEBUG
2753 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2754 qcount[prec] = pktq_plen(&bus->txq, prec);
2755 #endif
2756
2757 brcmf_sdio_trigger_dpc(bus);
2758 return ret;
2759 }
2760
2761 #ifdef DEBUG
2762 #define CONSOLE_LINE_MAX 192
2763
2764 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
2765 {
2766 struct brcmf_console *c = &bus->console;
2767 u8 line[CONSOLE_LINE_MAX], ch;
2768 u32 n, idx, addr;
2769 int rv;
2770
2771 /* Don't do anything until FWREADY updates console address */
2772 if (bus->console_addr == 0)
2773 return 0;
2774
2775 /* Read console log struct */
2776 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2777 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
2778 sizeof(c->log_le));
2779 if (rv < 0)
2780 return rv;
2781
2782 /* Allocate console buffer (one time only) */
2783 if (c->buf == NULL) {
2784 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2785 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2786 if (c->buf == NULL)
2787 return -ENOMEM;
2788 }
2789
2790 idx = le32_to_cpu(c->log_le.idx);
2791
2792 /* Protect against corrupt value */
2793 if (idx > c->bufsize)
2794 return -EBADE;
2795
2796 /* Skip reading the console buffer if the index pointer
2797 has not moved */
2798 if (idx == c->last)
2799 return 0;
2800
2801 /* Read the console buffer */
2802 addr = le32_to_cpu(c->log_le.buf);
2803 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
2804 if (rv < 0)
2805 return rv;
2806
2807 while (c->last != idx) {
2808 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2809 if (c->last == idx) {
2810 /* This would output a partial line.
2811 * Instead, back up
2812 * the buffer pointer and output this
2813 * line next time around.
2814 */
2815 if (c->last >= n)
2816 c->last -= n;
2817 else
2818 c->last = c->bufsize - n;
2819 goto break2;
2820 }
2821 ch = c->buf[c->last];
2822 c->last = (c->last + 1) % c->bufsize;
2823 if (ch == '\n')
2824 break;
2825 line[n] = ch;
2826 }
2827
2828 if (n > 0) {
2829 if (line[n - 1] == '\r')
2830 n--;
2831 line[n] = 0;
2832 pr_debug("CONSOLE: %s\n", line);
2833 }
2834 }
2835 break2:
2836
2837 return 0;
2838 }
2839 #endif /* DEBUG */
2840
2841 static int
2842 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2843 {
2844 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2845 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2846 struct brcmf_sdio *bus = sdiodev->bus;
2847 int ret;
2848
2849 brcmf_dbg(TRACE, "Enter\n");
2850 if (sdiodev->state != BRCMF_SDIOD_DATA)
2851 return -EIO;
2852
2853 /* Send from dpc */
2854 bus->ctrl_frame_buf = msg;
2855 bus->ctrl_frame_len = msglen;
2856 wmb();
2857 bus->ctrl_frame_stat = true;
2858
2859 brcmf_sdio_trigger_dpc(bus);
2860 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat,
2861 CTL_DONE_TIMEOUT);
2862 ret = 0;
2863 if (bus->ctrl_frame_stat) {
2864 sdio_claim_host(bus->sdiodev->func[1]);
2865 if (bus->ctrl_frame_stat) {
2866 brcmf_dbg(SDIO, "ctrl_frame timeout\n");
2867 bus->ctrl_frame_stat = false;
2868 ret = -ETIMEDOUT;
2869 }
2870 sdio_release_host(bus->sdiodev->func[1]);
2871 }
2872 if (!ret) {
2873 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n",
2874 bus->ctrl_frame_err);
2875 rmb();
2876 ret = bus->ctrl_frame_err;
2877 }
2878
2879 if (ret)
2880 bus->sdcnt.tx_ctlerrs++;
2881 else
2882 bus->sdcnt.tx_ctlpkts++;
2883
2884 return ret;
2885 }
2886
2887 #ifdef DEBUG
2888 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus,
2889 struct sdpcm_shared *sh)
2890 {
2891 u32 addr, console_ptr, console_size, console_index;
2892 char *conbuf = NULL;
2893 __le32 sh_val;
2894 int rv;
2895
2896 /* obtain console information from device memory */
2897 addr = sh->console_addr + offsetof(struct rte_console, log_le);
2898 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2899 (u8 *)&sh_val, sizeof(u32));
2900 if (rv < 0)
2901 return rv;
2902 console_ptr = le32_to_cpu(sh_val);
2903
2904 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
2905 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2906 (u8 *)&sh_val, sizeof(u32));
2907 if (rv < 0)
2908 return rv;
2909 console_size = le32_to_cpu(sh_val);
2910
2911 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
2912 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2913 (u8 *)&sh_val, sizeof(u32));
2914 if (rv < 0)
2915 return rv;
2916 console_index = le32_to_cpu(sh_val);
2917
2918 /* allocate buffer for console data */
2919 if (console_size <= CONSOLE_BUFFER_MAX)
2920 conbuf = vzalloc(console_size+1);
2921
2922 if (!conbuf)
2923 return -ENOMEM;
2924
2925 /* obtain the console data from device */
2926 conbuf[console_size] = '\0';
2927 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
2928 console_size);
2929 if (rv < 0)
2930 goto done;
2931
2932 rv = seq_write(seq, conbuf + console_index,
2933 console_size - console_index);
2934 if (rv < 0)
2935 goto done;
2936
2937 if (console_index > 0)
2938 rv = seq_write(seq, conbuf, console_index - 1);
2939
2940 done:
2941 vfree(conbuf);
2942 return rv;
2943 }
2944
2945 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus,
2946 struct sdpcm_shared *sh)
2947 {
2948 int error;
2949 struct brcmf_trap_info tr;
2950
2951 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
2952 brcmf_dbg(INFO, "no trap in firmware\n");
2953 return 0;
2954 }
2955
2956 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
2957 sizeof(struct brcmf_trap_info));
2958 if (error < 0)
2959 return error;
2960
2961 seq_printf(seq,
2962 "dongle trap info: type 0x%x @ epc 0x%08x\n"
2963 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
2964 " lr 0x%08x pc 0x%08x offset 0x%x\n"
2965 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
2966 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
2967 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
2968 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
2969 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
2970 le32_to_cpu(tr.pc), sh->trap_addr,
2971 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
2972 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
2973 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
2974 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
2975
2976 return 0;
2977 }
2978
2979 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus,
2980 struct sdpcm_shared *sh)
2981 {
2982 int error = 0;
2983 char file[80] = "?";
2984 char expr[80] = "<???>";
2985
2986 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
2987 brcmf_dbg(INFO, "firmware not built with -assert\n");
2988 return 0;
2989 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
2990 brcmf_dbg(INFO, "no assert in dongle\n");
2991 return 0;
2992 }
2993
2994 sdio_claim_host(bus->sdiodev->func[1]);
2995 if (sh->assert_file_addr != 0) {
2996 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
2997 sh->assert_file_addr, (u8 *)file, 80);
2998 if (error < 0)
2999 return error;
3000 }
3001 if (sh->assert_exp_addr != 0) {
3002 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3003 sh->assert_exp_addr, (u8 *)expr, 80);
3004 if (error < 0)
3005 return error;
3006 }
3007 sdio_release_host(bus->sdiodev->func[1]);
3008
3009 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n",
3010 file, sh->assert_line, expr);
3011 return 0;
3012 }
3013
3014 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3015 {
3016 int error;
3017 struct sdpcm_shared sh;
3018
3019 error = brcmf_sdio_readshared(bus, &sh);
3020
3021 if (error < 0)
3022 return error;
3023
3024 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
3025 brcmf_dbg(INFO, "firmware not built with -assert\n");
3026 else if (sh.flags & SDPCM_SHARED_ASSERT)
3027 brcmf_err("assertion in dongle\n");
3028
3029 if (sh.flags & SDPCM_SHARED_TRAP)
3030 brcmf_err("firmware trap in dongle\n");
3031
3032 return 0;
3033 }
3034
3035 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus)
3036 {
3037 int error = 0;
3038 struct sdpcm_shared sh;
3039
3040 error = brcmf_sdio_readshared(bus, &sh);
3041 if (error < 0)
3042 goto done;
3043
3044 error = brcmf_sdio_assert_info(seq, bus, &sh);
3045 if (error < 0)
3046 goto done;
3047
3048 error = brcmf_sdio_trap_info(seq, bus, &sh);
3049 if (error < 0)
3050 goto done;
3051
3052 error = brcmf_sdio_dump_console(seq, bus, &sh);
3053
3054 done:
3055 return error;
3056 }
3057
3058 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data)
3059 {
3060 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3061 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus;
3062
3063 return brcmf_sdio_died_dump(seq, bus);
3064 }
3065
3066 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data)
3067 {
3068 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3069 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3070 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt;
3071
3072 seq_printf(seq,
3073 "intrcount: %u\nlastintrs: %u\n"
3074 "pollcnt: %u\nregfails: %u\n"
3075 "tx_sderrs: %u\nfcqueued: %u\n"
3076 "rxrtx: %u\nrx_toolong: %u\n"
3077 "rxc_errors: %u\nrx_hdrfail: %u\n"
3078 "rx_badhdr: %u\nrx_badseq: %u\n"
3079 "fc_rcvd: %u\nfc_xoff: %u\n"
3080 "fc_xon: %u\nrxglomfail: %u\n"
3081 "rxglomframes: %u\nrxglompkts: %u\n"
3082 "f2rxhdrs: %u\nf2rxdata: %u\n"
3083 "f2txdata: %u\nf1regdata: %u\n"
3084 "tickcnt: %u\ntx_ctlerrs: %lu\n"
3085 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
3086 "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
3087 sdcnt->intrcount, sdcnt->lastintrs,
3088 sdcnt->pollcnt, sdcnt->regfails,
3089 sdcnt->tx_sderrs, sdcnt->fcqueued,
3090 sdcnt->rxrtx, sdcnt->rx_toolong,
3091 sdcnt->rxc_errors, sdcnt->rx_hdrfail,
3092 sdcnt->rx_badhdr, sdcnt->rx_badseq,
3093 sdcnt->fc_rcvd, sdcnt->fc_xoff,
3094 sdcnt->fc_xon, sdcnt->rxglomfail,
3095 sdcnt->rxglomframes, sdcnt->rxglompkts,
3096 sdcnt->f2rxhdrs, sdcnt->f2rxdata,
3097 sdcnt->f2txdata, sdcnt->f1regdata,
3098 sdcnt->tickcnt, sdcnt->tx_ctlerrs,
3099 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
3100 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
3101
3102 return 0;
3103 }
3104
3105 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3106 {
3107 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
3108 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
3109
3110 if (IS_ERR_OR_NULL(dentry))
3111 return;
3112
3113 bus->console_interval = BRCMF_CONSOLE;
3114
3115 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read);
3116 brcmf_debugfs_add_entry(drvr, "counters",
3117 brcmf_debugfs_sdio_count_read);
3118 debugfs_create_u32("console_interval", 0644, dentry,
3119 &bus->console_interval);
3120 }
3121 #else
3122 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3123 {
3124 return 0;
3125 }
3126
3127 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3128 {
3129 }
3130 #endif /* DEBUG */
3131
3132 static int
3133 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
3134 {
3135 int timeleft;
3136 uint rxlen = 0;
3137 bool pending;
3138 u8 *buf;
3139 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3140 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3141 struct brcmf_sdio *bus = sdiodev->bus;
3142
3143 brcmf_dbg(TRACE, "Enter\n");
3144 if (sdiodev->state != BRCMF_SDIOD_DATA)
3145 return -EIO;
3146
3147 /* Wait until control frame is available */
3148 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3149
3150 spin_lock_bh(&bus->rxctl_lock);
3151 rxlen = bus->rxlen;
3152 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3153 bus->rxctl = NULL;
3154 buf = bus->rxctl_orig;
3155 bus->rxctl_orig = NULL;
3156 bus->rxlen = 0;
3157 spin_unlock_bh(&bus->rxctl_lock);
3158 vfree(buf);
3159
3160 if (rxlen) {
3161 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3162 rxlen, msglen);
3163 } else if (timeleft == 0) {
3164 brcmf_err("resumed on timeout\n");
3165 brcmf_sdio_checkdied(bus);
3166 } else if (pending) {
3167 brcmf_dbg(CTL, "cancelled\n");
3168 return -ERESTARTSYS;
3169 } else {
3170 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3171 brcmf_sdio_checkdied(bus);
3172 }
3173
3174 if (rxlen)
3175 bus->sdcnt.rx_ctlpkts++;
3176 else
3177 bus->sdcnt.rx_ctlerrs++;
3178
3179 return rxlen ? (int)rxlen : -ETIMEDOUT;
3180 }
3181
3182 #ifdef DEBUG
3183 static bool
3184 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3185 u8 *ram_data, uint ram_sz)
3186 {
3187 char *ram_cmp;
3188 int err;
3189 bool ret = true;
3190 int address;
3191 int offset;
3192 int len;
3193
3194 /* read back and verify */
3195 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
3196 ram_sz);
3197 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
3198 /* do not proceed while no memory but */
3199 if (!ram_cmp)
3200 return true;
3201
3202 address = ram_addr;
3203 offset = 0;
3204 while (offset < ram_sz) {
3205 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
3206 ram_sz - offset;
3207 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
3208 if (err) {
3209 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3210 err, len, address);
3211 ret = false;
3212 break;
3213 } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
3214 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
3215 offset, len);
3216 ret = false;
3217 break;
3218 }
3219 offset += len;
3220 address += len;
3221 }
3222
3223 kfree(ram_cmp);
3224
3225 return ret;
3226 }
3227 #else /* DEBUG */
3228 static bool
3229 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3230 u8 *ram_data, uint ram_sz)
3231 {
3232 return true;
3233 }
3234 #endif /* DEBUG */
3235
3236 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
3237 const struct firmware *fw)
3238 {
3239 int err;
3240
3241 brcmf_dbg(TRACE, "Enter\n");
3242
3243 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
3244 (u8 *)fw->data, fw->size);
3245 if (err)
3246 brcmf_err("error %d on writing %d membytes at 0x%08x\n",
3247 err, (int)fw->size, bus->ci->rambase);
3248 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
3249 (u8 *)fw->data, fw->size))
3250 err = -EIO;
3251
3252 return err;
3253 }
3254
3255 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
3256 void *vars, u32 varsz)
3257 {
3258 int address;
3259 int err;
3260
3261 brcmf_dbg(TRACE, "Enter\n");
3262
3263 address = bus->ci->ramsize - varsz + bus->ci->rambase;
3264 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
3265 if (err)
3266 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
3267 err, varsz, address);
3268 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
3269 err = -EIO;
3270
3271 return err;
3272 }
3273
3274 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
3275 const struct firmware *fw,
3276 void *nvram, u32 nvlen)
3277 {
3278 int bcmerror;
3279 u32 rstvec;
3280
3281 sdio_claim_host(bus->sdiodev->func[1]);
3282 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3283
3284 rstvec = get_unaligned_le32(fw->data);
3285 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
3286
3287 bcmerror = brcmf_sdio_download_code_file(bus, fw);
3288 release_firmware(fw);
3289 if (bcmerror) {
3290 brcmf_err("dongle image file download failed\n");
3291 brcmf_fw_nvram_free(nvram);
3292 goto err;
3293 }
3294
3295 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen);
3296 brcmf_fw_nvram_free(nvram);
3297 if (bcmerror) {
3298 brcmf_err("dongle nvram file download failed\n");
3299 goto err;
3300 }
3301
3302 /* Take arm out of reset */
3303 if (!brcmf_chip_set_active(bus->ci, rstvec)) {
3304 brcmf_err("error getting out of ARM core reset\n");
3305 goto err;
3306 }
3307
3308 err:
3309 brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
3310 sdio_release_host(bus->sdiodev->func[1]);
3311 return bcmerror;
3312 }
3313
3314 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
3315 {
3316 int err = 0;
3317 u8 val;
3318
3319 brcmf_dbg(TRACE, "Enter\n");
3320
3321 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
3322 if (err) {
3323 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
3324 return;
3325 }
3326
3327 val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
3328 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
3329 if (err) {
3330 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
3331 return;
3332 }
3333
3334 /* Add CMD14 Support */
3335 brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
3336 (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
3337 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
3338 &err);
3339 if (err) {
3340 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
3341 return;
3342 }
3343
3344 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3345 SBSDIO_FORCE_HT, &err);
3346 if (err) {
3347 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
3348 return;
3349 }
3350
3351 /* set flag */
3352 bus->sr_enabled = true;
3353 brcmf_dbg(INFO, "SR enabled\n");
3354 }
3355
3356 /* enable KSO bit */
3357 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
3358 {
3359 u8 val;
3360 int err = 0;
3361
3362 brcmf_dbg(TRACE, "Enter\n");
3363
3364 /* KSO bit added in SDIO core rev 12 */
3365 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12)
3366 return 0;
3367
3368 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
3369 if (err) {
3370 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
3371 return err;
3372 }
3373
3374 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
3375 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
3376 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
3377 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
3378 val, &err);
3379 if (err) {
3380 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
3381 return err;
3382 }
3383 }
3384
3385 return 0;
3386 }
3387
3388
3389 static int brcmf_sdio_bus_preinit(struct device *dev)
3390 {
3391 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3392 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3393 struct brcmf_sdio *bus = sdiodev->bus;
3394 uint pad_size;
3395 u32 value;
3396 int err;
3397
3398 /* the commands below use the terms tx and rx from
3399 * a device perspective, ie. bus:txglom affects the
3400 * bus transfers from device to host.
3401 */
3402 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) {
3403 /* for sdio core rev < 12, disable txgloming */
3404 value = 0;
3405 err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
3406 sizeof(u32));
3407 } else {
3408 /* otherwise, set txglomalign */
3409 value = sdiodev->settings->bus.sdio.sd_sgentry_align;
3410 /* SDIO ADMA requires at least 32 bit alignment */
3411 value = max_t(u32, value, 4);
3412 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
3413 sizeof(u32));
3414 }
3415
3416 if (err < 0)
3417 goto done;
3418
3419 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
3420 if (sdiodev->sg_support) {
3421 bus->txglom = false;
3422 value = 1;
3423 pad_size = bus->sdiodev->func[2]->cur_blksize << 1;
3424 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
3425 &value, sizeof(u32));
3426 if (err < 0) {
3427 /* bus:rxglom is allowed to fail */
3428 err = 0;
3429 } else {
3430 bus->txglom = true;
3431 bus->tx_hdrlen += SDPCM_HWEXT_LEN;
3432 }
3433 }
3434 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
3435
3436 done:
3437 return err;
3438 }
3439
3440 static size_t brcmf_sdio_bus_get_ramsize(struct device *dev)
3441 {
3442 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3443 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3444 struct brcmf_sdio *bus = sdiodev->bus;
3445
3446 return bus->ci->ramsize - bus->ci->srsize;
3447 }
3448
3449 static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data,
3450 size_t mem_size)
3451 {
3452 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3453 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3454 struct brcmf_sdio *bus = sdiodev->bus;
3455 int err;
3456 int address;
3457 int offset;
3458 int len;
3459
3460 brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase,
3461 mem_size);
3462
3463 address = bus->ci->rambase;
3464 offset = err = 0;
3465 sdio_claim_host(sdiodev->func[1]);
3466 while (offset < mem_size) {
3467 len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK :
3468 mem_size - offset;
3469 err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len);
3470 if (err) {
3471 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3472 err, len, address);
3473 goto done;
3474 }
3475 data += len;
3476 offset += len;
3477 address += len;
3478 }
3479
3480 done:
3481 sdio_release_host(sdiodev->func[1]);
3482 return err;
3483 }
3484
3485 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus)
3486 {
3487 if (!bus->dpc_triggered) {
3488 bus->dpc_triggered = true;
3489 queue_work(bus->brcmf_wq, &bus->datawork);
3490 }
3491 }
3492
3493 void brcmf_sdio_isr(struct brcmf_sdio *bus)
3494 {
3495 brcmf_dbg(TRACE, "Enter\n");
3496
3497 if (!bus) {
3498 brcmf_err("bus is null pointer, exiting\n");
3499 return;
3500 }
3501
3502 /* Count the interrupt call */
3503 bus->sdcnt.intrcount++;
3504 if (in_interrupt())
3505 atomic_set(&bus->ipend, 1);
3506 else
3507 if (brcmf_sdio_intr_rstatus(bus)) {
3508 brcmf_err("failed backplane access\n");
3509 }
3510
3511 /* Disable additional interrupts (is this needed now)? */
3512 if (!bus->intr)
3513 brcmf_err("isr w/o interrupt configured!\n");
3514
3515 bus->dpc_triggered = true;
3516 queue_work(bus->brcmf_wq, &bus->datawork);
3517 }
3518
3519 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
3520 {
3521 brcmf_dbg(TIMER, "Enter\n");
3522
3523 /* Poll period: check device if appropriate. */
3524 if (!bus->sr_enabled &&
3525 bus->poll && (++bus->polltick >= bus->pollrate)) {
3526 u32 intstatus = 0;
3527
3528 /* Reset poll tick */
3529 bus->polltick = 0;
3530
3531 /* Check device if no interrupts */
3532 if (!bus->intr ||
3533 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
3534
3535 if (!bus->dpc_triggered) {
3536 u8 devpend;
3537
3538 sdio_claim_host(bus->sdiodev->func[1]);
3539 devpend = brcmf_sdiod_regrb(bus->sdiodev,
3540 SDIO_CCCR_INTx,
3541 NULL);
3542 sdio_release_host(bus->sdiodev->func[1]);
3543 intstatus = devpend & (INTR_STATUS_FUNC1 |
3544 INTR_STATUS_FUNC2);
3545 }
3546
3547 /* If there is something, make like the ISR and
3548 schedule the DPC */
3549 if (intstatus) {
3550 bus->sdcnt.pollcnt++;
3551 atomic_set(&bus->ipend, 1);
3552
3553 bus->dpc_triggered = true;
3554 queue_work(bus->brcmf_wq, &bus->datawork);
3555 }
3556 }
3557
3558 /* Update interrupt tracking */
3559 bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
3560 }
3561 #ifdef DEBUG
3562 /* Poll for console output periodically */
3563 if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() &&
3564 bus->console_interval != 0) {
3565 bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL);
3566 if (bus->console.count >= bus->console_interval) {
3567 bus->console.count -= bus->console_interval;
3568 sdio_claim_host(bus->sdiodev->func[1]);
3569 /* Make sure backplane clock is on */
3570 brcmf_sdio_bus_sleep(bus, false, false);
3571 if (brcmf_sdio_readconsole(bus) < 0)
3572 /* stop on error */
3573 bus->console_interval = 0;
3574 sdio_release_host(bus->sdiodev->func[1]);
3575 }
3576 }
3577 #endif /* DEBUG */
3578
3579 /* On idle timeout clear activity flag and/or turn off clock */
3580 if (!bus->dpc_triggered) {
3581 rmb();
3582 if ((!bus->dpc_running) && (bus->idletime > 0) &&
3583 (bus->clkstate == CLK_AVAIL)) {
3584 bus->idlecount++;
3585 if (bus->idlecount > bus->idletime) {
3586 brcmf_dbg(SDIO, "idle\n");
3587 sdio_claim_host(bus->sdiodev->func[1]);
3588 brcmf_sdio_wd_timer(bus, false);
3589 bus->idlecount = 0;
3590 brcmf_sdio_bus_sleep(bus, true, false);
3591 sdio_release_host(bus->sdiodev->func[1]);
3592 }
3593 } else {
3594 bus->idlecount = 0;
3595 }
3596 } else {
3597 bus->idlecount = 0;
3598 }
3599 }
3600
3601 static void brcmf_sdio_dataworker(struct work_struct *work)
3602 {
3603 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
3604 datawork);
3605
3606 bus->dpc_running = true;
3607 wmb();
3608 while (ACCESS_ONCE(bus->dpc_triggered)) {
3609 bus->dpc_triggered = false;
3610 brcmf_sdio_dpc(bus);
3611 bus->idlecount = 0;
3612 }
3613 bus->dpc_running = false;
3614 if (brcmf_sdiod_freezing(bus->sdiodev)) {
3615 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN);
3616 brcmf_sdiod_try_freeze(bus->sdiodev);
3617 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3618 }
3619 }
3620
3621 static void
3622 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
3623 struct brcmf_chip *ci, u32 drivestrength)
3624 {
3625 const struct sdiod_drive_str *str_tab = NULL;
3626 u32 str_mask;
3627 u32 str_shift;
3628 u32 i;
3629 u32 drivestrength_sel = 0;
3630 u32 cc_data_temp;
3631 u32 addr;
3632
3633 if (!(ci->cc_caps & CC_CAP_PMU))
3634 return;
3635
3636 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
3637 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12):
3638 str_tab = sdiod_drvstr_tab1_1v8;
3639 str_mask = 0x00003800;
3640 str_shift = 11;
3641 break;
3642 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17):
3643 str_tab = sdiod_drvstr_tab6_1v8;
3644 str_mask = 0x00001800;
3645 str_shift = 11;
3646 break;
3647 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17):
3648 /* note: 43143 does not support tristate */
3649 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
3650 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
3651 str_tab = sdiod_drvstr_tab2_3v3;
3652 str_mask = 0x00000007;
3653 str_shift = 0;
3654 } else
3655 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
3656 ci->name, drivestrength);
3657 break;
3658 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13):
3659 str_tab = sdiod_drive_strength_tab5_1v8;
3660 str_mask = 0x00003800;
3661 str_shift = 11;
3662 break;
3663 default:
3664 brcmf_dbg(INFO, "No SDIO driver strength init needed for chip %s rev %d pmurev %d\n",
3665 ci->name, ci->chiprev, ci->pmurev);
3666 break;
3667 }
3668
3669 if (str_tab != NULL) {
3670 struct brcmf_core *pmu = brcmf_chip_get_pmu(ci);
3671
3672 for (i = 0; str_tab[i].strength != 0; i++) {
3673 if (drivestrength >= str_tab[i].strength) {
3674 drivestrength_sel = str_tab[i].sel;
3675 break;
3676 }
3677 }
3678 addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
3679 brcmf_sdiod_regwl(sdiodev, addr, 1, NULL);
3680 cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3681 cc_data_temp &= ~str_mask;
3682 drivestrength_sel <<= str_shift;
3683 cc_data_temp |= drivestrength_sel;
3684 brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL);
3685
3686 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
3687 str_tab[i].strength, drivestrength, cc_data_temp);
3688 }
3689 }
3690
3691 static int brcmf_sdio_buscoreprep(void *ctx)
3692 {
3693 struct brcmf_sdio_dev *sdiodev = ctx;
3694 int err = 0;
3695 u8 clkval, clkset;
3696
3697 /* Try forcing SDIO core to do ALPAvail request only */
3698 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
3699 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3700 if (err) {
3701 brcmf_err("error writing for HT off\n");
3702 return err;
3703 }
3704
3705 /* If register supported, wait for ALPAvail and then force ALP */
3706 /* This may take up to 15 milliseconds */
3707 clkval = brcmf_sdiod_regrb(sdiodev,
3708 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
3709
3710 if ((clkval & ~SBSDIO_AVBITS) != clkset) {
3711 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
3712 clkset, clkval);
3713 return -EACCES;
3714 }
3715
3716 SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev,
3717 SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
3718 !SBSDIO_ALPAV(clkval)),
3719 PMU_MAX_TRANSITION_DLY);
3720 if (!SBSDIO_ALPAV(clkval)) {
3721 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
3722 clkval);
3723 return -EBUSY;
3724 }
3725
3726 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
3727 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3728 udelay(65);
3729
3730 /* Also, disable the extra SDIO pull-ups */
3731 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
3732
3733 return 0;
3734 }
3735
3736 static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip,
3737 u32 rstvec)
3738 {
3739 struct brcmf_sdio_dev *sdiodev = ctx;
3740 struct brcmf_core *core;
3741 u32 reg_addr;
3742
3743 /* clear all interrupts */
3744 core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV);
3745 reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus);
3746 brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
3747
3748 if (rstvec)
3749 /* Write reset vector to address 0 */
3750 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
3751 sizeof(rstvec));
3752 }
3753
3754 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
3755 {
3756 struct brcmf_sdio_dev *sdiodev = ctx;
3757 u32 val, rev;
3758
3759 val = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3760 if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 &&
3761 addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) {
3762 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
3763 if (rev >= 2) {
3764 val &= ~CID_ID_MASK;
3765 val |= BRCM_CC_4339_CHIP_ID;
3766 }
3767 }
3768 return val;
3769 }
3770
3771 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
3772 {
3773 struct brcmf_sdio_dev *sdiodev = ctx;
3774
3775 brcmf_sdiod_regwl(sdiodev, addr, val, NULL);
3776 }
3777
3778 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
3779 .prepare = brcmf_sdio_buscoreprep,
3780 .activate = brcmf_sdio_buscore_activate,
3781 .read32 = brcmf_sdio_buscore_read32,
3782 .write32 = brcmf_sdio_buscore_write32,
3783 };
3784
3785 static bool
3786 brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
3787 {
3788 struct brcmf_sdio_dev *sdiodev;
3789 u8 clkctl = 0;
3790 int err = 0;
3791 int reg_addr;
3792 u32 reg_val;
3793 u32 drivestrength;
3794
3795 sdiodev = bus->sdiodev;
3796 sdio_claim_host(sdiodev->func[1]);
3797
3798 pr_debug("F1 signature read @0x18000000=0x%4x\n",
3799 brcmf_sdiod_regrl(sdiodev, SI_ENUM_BASE, NULL));
3800
3801 /*
3802 * Force PLL off until brcmf_chip_attach()
3803 * programs PLL control regs
3804 */
3805
3806 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3807 BRCMF_INIT_CLKCTL1, &err);
3808 if (!err)
3809 clkctl = brcmf_sdiod_regrb(sdiodev,
3810 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3811
3812 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3813 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3814 err, BRCMF_INIT_CLKCTL1, clkctl);
3815 goto fail;
3816 }
3817
3818 bus->ci = brcmf_chip_attach(sdiodev, &brcmf_sdio_buscore_ops);
3819 if (IS_ERR(bus->ci)) {
3820 brcmf_err("brcmf_chip_attach failed!\n");
3821 bus->ci = NULL;
3822 goto fail;
3823 }
3824 sdiodev->settings = brcmf_get_module_param(sdiodev->dev,
3825 BRCMF_BUSTYPE_SDIO,
3826 bus->ci->chip,
3827 bus->ci->chiprev);
3828 if (!sdiodev->settings) {
3829 brcmf_err("Failed to get device parameters\n");
3830 goto fail;
3831 }
3832 /* platform specific configuration:
3833 * alignments must be at least 4 bytes for ADMA
3834 */
3835 bus->head_align = ALIGNMENT;
3836 bus->sgentry_align = ALIGNMENT;
3837 if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT)
3838 bus->head_align = sdiodev->settings->bus.sdio.sd_head_align;
3839 if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT)
3840 bus->sgentry_align =
3841 sdiodev->settings->bus.sdio.sd_sgentry_align;
3842
3843 /* allocate scatter-gather table. sg support
3844 * will be disabled upon allocation failure.
3845 */
3846 brcmf_sdiod_sgtable_alloc(sdiodev);
3847
3848 #ifdef CONFIG_PM_SLEEP
3849 /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ
3850 * is true or when platform data OOB irq is true).
3851 */
3852 if ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_KEEP_POWER) &&
3853 ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_WAKE_SDIO_IRQ) ||
3854 (sdiodev->settings->bus.sdio.oob_irq_supported)))
3855 sdiodev->bus_if->wowl_supported = true;
3856 #endif
3857
3858 if (brcmf_sdio_kso_init(bus)) {
3859 brcmf_err("error enabling KSO\n");
3860 goto fail;
3861 }
3862
3863 if (sdiodev->settings->bus.sdio.drive_strength)
3864 drivestrength = sdiodev->settings->bus.sdio.drive_strength;
3865 else
3866 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
3867 brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength);
3868
3869 /* Set card control so an SDIO card reset does a WLAN backplane reset */
3870 reg_val = brcmf_sdiod_regrb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err);
3871 if (err)
3872 goto fail;
3873
3874 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
3875
3876 brcmf_sdiod_regwb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
3877 if (err)
3878 goto fail;
3879
3880 /* set PMUControl so a backplane reset does PMU state reload */
3881 reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol);
3882 reg_val = brcmf_sdiod_regrl(sdiodev, reg_addr, &err);
3883 if (err)
3884 goto fail;
3885
3886 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
3887
3888 brcmf_sdiod_regwl(sdiodev, reg_addr, reg_val, &err);
3889 if (err)
3890 goto fail;
3891
3892 sdio_release_host(sdiodev->func[1]);
3893
3894 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
3895
3896 /* allocate header buffer */
3897 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
3898 if (!bus->hdrbuf)
3899 return false;
3900 /* Locate an appropriately-aligned portion of hdrbuf */
3901 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
3902 bus->head_align);
3903
3904 /* Set the poll and/or interrupt flags */
3905 bus->intr = true;
3906 bus->poll = false;
3907 if (bus->poll)
3908 bus->pollrate = 1;
3909
3910 return true;
3911
3912 fail:
3913 sdio_release_host(sdiodev->func[1]);
3914 return false;
3915 }
3916
3917 static int
3918 brcmf_sdio_watchdog_thread(void *data)
3919 {
3920 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3921 int wait;
3922
3923 allow_signal(SIGTERM);
3924 /* Run until signal received */
3925 brcmf_sdiod_freezer_count(bus->sdiodev);
3926 while (1) {
3927 if (kthread_should_stop())
3928 break;
3929 brcmf_sdiod_freezer_uncount(bus->sdiodev);
3930 wait = wait_for_completion_interruptible(&bus->watchdog_wait);
3931 brcmf_sdiod_freezer_count(bus->sdiodev);
3932 brcmf_sdiod_try_freeze(bus->sdiodev);
3933 if (!wait) {
3934 brcmf_sdio_bus_watchdog(bus);
3935 /* Count the tick for reference */
3936 bus->sdcnt.tickcnt++;
3937 reinit_completion(&bus->watchdog_wait);
3938 } else
3939 break;
3940 }
3941 return 0;
3942 }
3943
3944 static void
3945 brcmf_sdio_watchdog(unsigned long data)
3946 {
3947 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3948
3949 if (bus->watchdog_tsk) {
3950 complete(&bus->watchdog_wait);
3951 /* Reschedule the watchdog */
3952 if (bus->wd_active)
3953 mod_timer(&bus->timer,
3954 jiffies + BRCMF_WD_POLL);
3955 }
3956 }
3957
3958 static const struct brcmf_bus_ops brcmf_sdio_bus_ops = {
3959 .stop = brcmf_sdio_bus_stop,
3960 .preinit = brcmf_sdio_bus_preinit,
3961 .txdata = brcmf_sdio_bus_txdata,
3962 .txctl = brcmf_sdio_bus_txctl,
3963 .rxctl = brcmf_sdio_bus_rxctl,
3964 .gettxq = brcmf_sdio_bus_gettxq,
3965 .wowl_config = brcmf_sdio_wowl_config,
3966 .get_ramsize = brcmf_sdio_bus_get_ramsize,
3967 .get_memdump = brcmf_sdio_bus_get_memdump,
3968 };
3969
3970 static void brcmf_sdio_firmware_callback(struct device *dev,
3971 const struct firmware *code,
3972 void *nvram, u32 nvram_len)
3973 {
3974 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3975 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3976 struct brcmf_sdio *bus = sdiodev->bus;
3977 int err = 0;
3978 u8 saveclk;
3979
3980 brcmf_dbg(TRACE, "Enter: dev=%s\n", dev_name(dev));
3981
3982 if (!bus_if->drvr)
3983 return;
3984
3985 /* try to download image and nvram to the dongle */
3986 bus->alp_only = true;
3987 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len);
3988 if (err)
3989 goto fail;
3990 bus->alp_only = false;
3991
3992 /* Start the watchdog timer */
3993 bus->sdcnt.tickcnt = 0;
3994 brcmf_sdio_wd_timer(bus, true);
3995
3996 sdio_claim_host(sdiodev->func[1]);
3997
3998 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3999 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4000 if (bus->clkstate != CLK_AVAIL)
4001 goto release;
4002
4003 /* Force clocks on backplane to be sure F2 interrupt propagates */
4004 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err);
4005 if (!err) {
4006 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4007 (saveclk | SBSDIO_FORCE_HT), &err);
4008 }
4009 if (err) {
4010 brcmf_err("Failed to force clock for F2: err %d\n", err);
4011 goto release;
4012 }
4013
4014 /* Enable function 2 (frame transfers) */
4015 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
4016 offsetof(struct sdpcmd_regs, tosbmailboxdata));
4017 err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]);
4018
4019
4020 brcmf_dbg(INFO, "enable F2: err=%d\n", err);
4021
4022 /* If F2 successfully enabled, set core and enable interrupts */
4023 if (!err) {
4024 /* Set up the interrupt mask and enable interrupts */
4025 bus->hostintmask = HOSTINTMASK;
4026 w_sdreg32(bus, bus->hostintmask,
4027 offsetof(struct sdpcmd_regs, hostintmask));
4028
4029 brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err);
4030 } else {
4031 /* Disable F2 again */
4032 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
4033 goto release;
4034 }
4035
4036 if (brcmf_chip_sr_capable(bus->ci)) {
4037 brcmf_sdio_sr_init(bus);
4038 } else {
4039 /* Restore previous clock setting */
4040 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4041 saveclk, &err);
4042 }
4043
4044 if (err == 0) {
4045 /* Allow full data communication using DPC from now on. */
4046 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
4047
4048 err = brcmf_sdiod_intr_register(sdiodev);
4049 if (err != 0)
4050 brcmf_err("intr register failed:%d\n", err);
4051 }
4052
4053 /* If we didn't come up, turn off backplane clock */
4054 if (err != 0)
4055 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4056
4057 sdio_release_host(sdiodev->func[1]);
4058
4059 err = brcmf_bus_start(dev);
4060 if (err != 0) {
4061 brcmf_err("dongle is not responding\n");
4062 goto fail;
4063 }
4064 return;
4065
4066 release:
4067 sdio_release_host(sdiodev->func[1]);
4068 fail:
4069 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err);
4070 device_release_driver(dev);
4071 }
4072
4073 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
4074 {
4075 int ret;
4076 struct brcmf_sdio *bus;
4077 struct workqueue_struct *wq;
4078
4079 brcmf_dbg(TRACE, "Enter\n");
4080
4081 /* Allocate private bus interface state */
4082 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
4083 if (!bus)
4084 goto fail;
4085
4086 bus->sdiodev = sdiodev;
4087 sdiodev->bus = bus;
4088 skb_queue_head_init(&bus->glom);
4089 bus->txbound = BRCMF_TXBOUND;
4090 bus->rxbound = BRCMF_RXBOUND;
4091 bus->txminmax = BRCMF_TXMINMAX;
4092 bus->tx_seq = SDPCM_SEQ_WRAP - 1;
4093
4094 /* single-threaded workqueue */
4095 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM,
4096 dev_name(&sdiodev->func[1]->dev));
4097 if (!wq) {
4098 brcmf_err("insufficient memory to create txworkqueue\n");
4099 goto fail;
4100 }
4101 brcmf_sdiod_freezer_count(sdiodev);
4102 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
4103 bus->brcmf_wq = wq;
4104
4105 /* attempt to attach to the dongle */
4106 if (!(brcmf_sdio_probe_attach(bus))) {
4107 brcmf_err("brcmf_sdio_probe_attach failed\n");
4108 goto fail;
4109 }
4110
4111 spin_lock_init(&bus->rxctl_lock);
4112 spin_lock_init(&bus->txq_lock);
4113 init_waitqueue_head(&bus->ctrl_wait);
4114 init_waitqueue_head(&bus->dcmd_resp_wait);
4115
4116 /* Set up the watchdog timer */
4117 init_timer(&bus->timer);
4118 bus->timer.data = (unsigned long)bus;
4119 bus->timer.function = brcmf_sdio_watchdog;
4120
4121 /* Initialize watchdog thread */
4122 init_completion(&bus->watchdog_wait);
4123 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
4124 bus, "brcmf_wdog/%s",
4125 dev_name(&sdiodev->func[1]->dev));
4126 if (IS_ERR(bus->watchdog_tsk)) {
4127 pr_warn("brcmf_watchdog thread failed to start\n");
4128 bus->watchdog_tsk = NULL;
4129 }
4130 /* Initialize DPC thread */
4131 bus->dpc_triggered = false;
4132 bus->dpc_running = false;
4133
4134 /* Assign bus interface call back */
4135 bus->sdiodev->bus_if->dev = bus->sdiodev->dev;
4136 bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops;
4137 bus->sdiodev->bus_if->chip = bus->ci->chip;
4138 bus->sdiodev->bus_if->chiprev = bus->ci->chiprev;
4139
4140 /* default sdio bus header length for tx packet */
4141 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
4142
4143 /* Attach to the common layer, reserve hdr space */
4144 ret = brcmf_attach(bus->sdiodev->dev, bus->sdiodev->settings);
4145 if (ret != 0) {
4146 brcmf_err("brcmf_attach failed\n");
4147 goto fail;
4148 }
4149
4150 /* allocate scatter-gather table. sg support
4151 * will be disabled upon allocation failure.
4152 */
4153 brcmf_sdiod_sgtable_alloc(bus->sdiodev);
4154
4155 /* Query the F2 block size, set roundup accordingly */
4156 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4157 bus->roundup = min(max_roundup, bus->blocksize);
4158
4159 /* Allocate buffers */
4160 if (bus->sdiodev->bus_if->maxctl) {
4161 bus->sdiodev->bus_if->maxctl += bus->roundup;
4162 bus->rxblen =
4163 roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
4164 ALIGNMENT) + bus->head_align;
4165 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
4166 if (!(bus->rxbuf)) {
4167 brcmf_err("rxbuf allocation failed\n");
4168 goto fail;
4169 }
4170 }
4171
4172 sdio_claim_host(bus->sdiodev->func[1]);
4173
4174 /* Disable F2 to clear any intermediate frame state on the dongle */
4175 sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
4176
4177 bus->rxflow = false;
4178
4179 /* Done with backplane-dependent accesses, can drop clock... */
4180 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4181
4182 sdio_release_host(bus->sdiodev->func[1]);
4183
4184 /* ...and initialize clock/power states */
4185 bus->clkstate = CLK_SDONLY;
4186 bus->idletime = BRCMF_IDLE_INTERVAL;
4187 bus->idleclock = BRCMF_IDLE_ACTIVE;
4188
4189 /* SR state */
4190 bus->sr_enabled = false;
4191
4192 brcmf_sdio_debugfs_create(bus);
4193 brcmf_dbg(INFO, "completed!!\n");
4194
4195 ret = brcmf_fw_map_chip_to_name(bus->ci->chip, bus->ci->chiprev,
4196 brcmf_sdio_fwnames,
4197 ARRAY_SIZE(brcmf_sdio_fwnames),
4198 sdiodev->fw_name, sdiodev->nvram_name);
4199 if (ret)
4200 goto fail;
4201
4202 ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM,
4203 sdiodev->fw_name, sdiodev->nvram_name,
4204 brcmf_sdio_firmware_callback);
4205 if (ret != 0) {
4206 brcmf_err("async firmware request failed: %d\n", ret);
4207 goto fail;
4208 }
4209
4210 return bus;
4211
4212 fail:
4213 brcmf_sdio_remove(bus);
4214 return NULL;
4215 }
4216
4217 /* Detach and free everything */
4218 void brcmf_sdio_remove(struct brcmf_sdio *bus)
4219 {
4220 brcmf_dbg(TRACE, "Enter\n");
4221
4222 if (bus) {
4223 /* De-register interrupt handler */
4224 brcmf_sdiod_intr_unregister(bus->sdiodev);
4225
4226 brcmf_detach(bus->sdiodev->dev);
4227
4228 cancel_work_sync(&bus->datawork);
4229 if (bus->brcmf_wq)
4230 destroy_workqueue(bus->brcmf_wq);
4231
4232 if (bus->ci) {
4233 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
4234 sdio_claim_host(bus->sdiodev->func[1]);
4235 brcmf_sdio_wd_timer(bus, false);
4236 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4237 /* Leave the device in state where it is
4238 * 'passive'. This is done by resetting all
4239 * necessary cores.
4240 */
4241 msleep(20);
4242 brcmf_chip_set_passive(bus->ci);
4243 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4244 sdio_release_host(bus->sdiodev->func[1]);
4245 }
4246 brcmf_chip_detach(bus->ci);
4247 }
4248 if (bus->sdiodev->settings)
4249 brcmf_release_module_param(bus->sdiodev->settings);
4250
4251 kfree(bus->rxbuf);
4252 kfree(bus->hdrbuf);
4253 kfree(bus);
4254 }
4255
4256 brcmf_dbg(TRACE, "Disconnected\n");
4257 }
4258
4259 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active)
4260 {
4261 /* Totally stop the timer */
4262 if (!active && bus->wd_active) {
4263 del_timer_sync(&bus->timer);
4264 bus->wd_active = false;
4265 return;
4266 }
4267
4268 /* don't start the wd until fw is loaded */
4269 if (bus->sdiodev->state != BRCMF_SDIOD_DATA)
4270 return;
4271
4272 if (active) {
4273 if (!bus->wd_active) {
4274 /* Create timer again when watchdog period is
4275 dynamically changed or in the first instance
4276 */
4277 bus->timer.expires = jiffies + BRCMF_WD_POLL;
4278 add_timer(&bus->timer);
4279 bus->wd_active = true;
4280 } else {
4281 /* Re arm the timer, at last watchdog period */
4282 mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL);
4283 }
4284 }
4285 }
4286
4287 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
4288 {
4289 int ret;
4290
4291 sdio_claim_host(bus->sdiodev->func[1]);
4292 ret = brcmf_sdio_bus_sleep(bus, sleep, false);
4293 sdio_release_host(bus->sdiodev->func[1]);
4294
4295 return ret;
4296 }
4297
Linux kernel - Deliverables
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