drivers/net/wireless/cw1200/hwio.h

   1 /*
   2  * Low-level API for mac80211 ST-Ericsson CW1200 drivers
   3  *
   4  * Copyright (c) 2010, ST-Ericsson
   5  * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
   6  *
   7  * Based on:
   8  * ST-Ericsson UMAC CW1200 driver which is
   9  * Copyright (c) 2010, ST-Ericsson
  10  * Author: Ajitpal Singh <ajitpal.singh@stericsson.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #ifndef CW1200_HWIO_H_INCLUDED
  18 #define CW1200_HWIO_H_INCLUDED
  19
  20 /* extern */ struct cw1200_common;
  21
  22 #define CW1200_CUT_11_ID_STR            (0x302E3830)
  23 #define CW1200_CUT_22_ID_STR1           (0x302e3132)
  24 #define CW1200_CUT_22_ID_STR2           (0x32302e30)
  25 #define CW1200_CUT_22_ID_STR3           (0x3335)
  26 #define CW1200_CUT_ID_ADDR              (0xFFF17F90)
  27 #define CW1200_CUT2_ID_ADDR             (0xFFF1FF90)
  28
  29 /* Download control area */
  30 /* boot loader start address in SRAM */
  31 #define DOWNLOAD_BOOT_LOADER_OFFSET     (0x00000000)
  32 /* 32K, 0x4000 to 0xDFFF */
  33 #define DOWNLOAD_FIFO_OFFSET            (0x00004000)
  34 /* 32K */
  35 #define DOWNLOAD_FIFO_SIZE              (0x00008000)
  36 /* 128 bytes, 0xFF80 to 0xFFFF */
  37 #define DOWNLOAD_CTRL_OFFSET            (0x0000FF80)
  38 #define DOWNLOAD_CTRL_DATA_DWORDS       (32-6)
  39
  40 struct download_cntl_t {
  41         /* size of whole firmware file (including Cheksum), host init */
  42         u32 image_size;
  43         /* downloading flags */
  44         u32 flags;
  45         /* No. of bytes put into the download, init & updated by host */
  46         u32 put;
  47         /* last traced program counter, last ARM reg_pc */
  48         u32 trace_pc;
  49         /* No. of bytes read from the download, host init, device updates */
  50         u32 get;
  51         /* r0, boot losader status, host init to pending, device updates */
  52         u32 status;
  53         /* Extra debug info, r1 to r14 if status=r0=DOWNLOAD_EXCEPTION */
  54         u32 debug_data[DOWNLOAD_CTRL_DATA_DWORDS];
  55 };
  56
  57 #define DOWNLOAD_IMAGE_SIZE_REG         \
  58         (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, image_size))
  59 #define DOWNLOAD_FLAGS_REG              \
  60         (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, flags))
  61 #define DOWNLOAD_PUT_REG                \
  62         (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, put))
  63 #define DOWNLOAD_TRACE_PC_REG           \
  64         (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, trace_pc))
  65 #define DOWNLOAD_GET_REG                \
  66         (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, get))
  67 #define DOWNLOAD_STATUS_REG             \
  68         (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, status))
  69 #define DOWNLOAD_DEBUG_DATA_REG         \
  70         (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, debug_data))
  71 #define DOWNLOAD_DEBUG_DATA_LEN         (108)
  72
  73 #define DOWNLOAD_BLOCK_SIZE             (1024)
  74
  75 /* For boot loader detection */
  76 #define DOWNLOAD_ARE_YOU_HERE           (0x87654321)
  77 #define DOWNLOAD_I_AM_HERE              (0x12345678)
  78
  79 /* Download error code */
  80 #define DOWNLOAD_PENDING                (0xFFFFFFFF)
  81 #define DOWNLOAD_SUCCESS                (0)
  82 #define DOWNLOAD_EXCEPTION              (1)
  83 #define DOWNLOAD_ERR_MEM_1              (2)
  84 #define DOWNLOAD_ERR_MEM_2              (3)
  85 #define DOWNLOAD_ERR_SOFTWARE           (4)
  86 #define DOWNLOAD_ERR_FILE_SIZE          (5)
  87 #define DOWNLOAD_ERR_CHECKSUM           (6)
  88 #define DOWNLOAD_ERR_OVERFLOW           (7)
  89 #define DOWNLOAD_ERR_IMAGE              (8)
  90 #define DOWNLOAD_ERR_HOST               (9)
  91 #define DOWNLOAD_ERR_ABORT              (10)
  92
  93
  94 #define SYS_BASE_ADDR_SILICON           (0)
  95 #define PAC_BASE_ADDRESS_SILICON        (SYS_BASE_ADDR_SILICON + 0x09000000)
  96 #define PAC_SHARED_MEMORY_SILICON       (PAC_BASE_ADDRESS_SILICON)
  97
  98 #define CW1200_APB(addr)                (PAC_SHARED_MEMORY_SILICON + (addr))
  99
 100 /* ***************************************************************
 101 *Device register definitions
 102 *************************************************************** */
 103 /* WBF - SPI Register Addresses */
 104 #define ST90TDS_ADDR_ID_BASE            (0x0000)
 105 /* 16/32 bits */
 106 #define ST90TDS_CONFIG_REG_ID           (0x0000)
 107 /* 16/32 bits */
 108 #define ST90TDS_CONTROL_REG_ID          (0x0001)
 109 /* 16 bits, Q mode W/R */
 110 #define ST90TDS_IN_OUT_QUEUE_REG_ID     (0x0002)
 111 /* 32 bits, AHB bus R/W */
 112 #define ST90TDS_AHB_DPORT_REG_ID        (0x0003)
 113 /* 16/32 bits */
 114 #define ST90TDS_SRAM_BASE_ADDR_REG_ID   (0x0004)
 115 /* 32 bits, APB bus R/W */
 116 #define ST90TDS_SRAM_DPORT_REG_ID       (0x0005)
 117 /* 32 bits, t_settle/general */
 118 #define ST90TDS_TSET_GEN_R_W_REG_ID     (0x0006)
 119 /* 16 bits, Q mode read, no length */
 120 #define ST90TDS_FRAME_OUT_REG_ID        (0x0007)
 121 #define ST90TDS_ADDR_ID_MAX             (ST90TDS_FRAME_OUT_REG_ID)
 122
 123 /* WBF - Control register bit set */
 124 /* next o/p length, bit 11 to 0 */
 125 #define ST90TDS_CONT_NEXT_LEN_MASK      (0x0FFF)
 126 #define ST90TDS_CONT_WUP_BIT            (BIT(12))
 127 #define ST90TDS_CONT_RDY_BIT            (BIT(13))
 128 #define ST90TDS_CONT_IRQ_ENABLE         (BIT(14))
 129 #define ST90TDS_CONT_RDY_ENABLE         (BIT(15))
 130 #define ST90TDS_CONT_IRQ_RDY_ENABLE     (BIT(14)|BIT(15))
 131
 132 /* SPI Config register bit set */
 133 #define ST90TDS_CONFIG_FRAME_BIT        (BIT(2))
 134 #define ST90TDS_CONFIG_WORD_MODE_BITS   (BIT(3)|BIT(4))
 135 #define ST90TDS_CONFIG_WORD_MODE_1      (BIT(3))
 136 #define ST90TDS_CONFIG_WORD_MODE_2      (BIT(4))
 137 #define ST90TDS_CONFIG_ERROR_0_BIT      (BIT(5))
 138 #define ST90TDS_CONFIG_ERROR_1_BIT      (BIT(6))
 139 #define ST90TDS_CONFIG_ERROR_2_BIT      (BIT(7))
 140 /* TBD: Sure??? */
 141 #define ST90TDS_CONFIG_CSN_FRAME_BIT    (BIT(7))
 142 #define ST90TDS_CONFIG_ERROR_3_BIT      (BIT(8))
 143 #define ST90TDS_CONFIG_ERROR_4_BIT      (BIT(9))
 144 /* QueueM */
 145 #define ST90TDS_CONFIG_ACCESS_MODE_BIT  (BIT(10))
 146 /* AHB bus */
 147 #define ST90TDS_CONFIG_AHB_PRFETCH_BIT  (BIT(11))
 148 #define ST90TDS_CONFIG_CPU_CLK_DIS_BIT  (BIT(12))
 149 /* APB bus */
 150 #define ST90TDS_CONFIG_PRFETCH_BIT      (BIT(13))
 151 /* cpu reset */
 152 #define ST90TDS_CONFIG_CPU_RESET_BIT    (BIT(14))
 153 #define ST90TDS_CONFIG_CLEAR_INT_BIT    (BIT(15))
 154
 155 /* For CW1200 the IRQ Enable and Ready Bits are in CONFIG register */
 156 #define ST90TDS_CONF_IRQ_ENABLE         (BIT(16))
 157 #define ST90TDS_CONF_RDY_ENABLE         (BIT(17))
 158 #define ST90TDS_CONF_IRQ_RDY_ENABLE     (BIT(16)|BIT(17))
 159
 160 int cw1200_data_read(struct cw1200_common *priv,
 161                      void *buf, size_t buf_len);
 162 int cw1200_data_write(struct cw1200_common *priv,
 163                       const void *buf, size_t buf_len);
 164
 165 int cw1200_reg_read(struct cw1200_common *priv, u16 addr,
 166                     void *buf, size_t buf_len);
 167 int cw1200_reg_write(struct cw1200_common *priv, u16 addr,
 168                      const void *buf, size_t buf_len);
 169
 170 static inline int cw1200_reg_read_16(struct cw1200_common *priv,
 171                                      u16 addr, u16 *val)
 172 {
 173         u32 tmp;
 174         int i;
 175         i = cw1200_reg_read(priv, addr, &tmp, sizeof(tmp));
 176         tmp = le32_to_cpu(tmp);
 177         *val = tmp & 0xffff;
 178         return i;
 179 }
 180
 181 static inline int cw1200_reg_write_16(struct cw1200_common *priv,
 182                                       u16 addr, u16 val)
 183 {
 184         u32 tmp = val;
 185         tmp = cpu_to_le32(tmp);
 186         return cw1200_reg_write(priv, addr, &tmp, sizeof(tmp));
 187 }
 188
 189 static inline int cw1200_reg_read_32(struct cw1200_common *priv,
 190                                      u16 addr, u32 *val)
 191 {
 192         int i = cw1200_reg_read(priv, addr, val, sizeof(*val));
 193         *val = le32_to_cpu(*val);
 194         return i;
 195 }
 196
 197 static inline int cw1200_reg_write_32(struct cw1200_common *priv,
 198                                       u16 addr, u32 val)
 199 {
 200         val = cpu_to_le32(val);
 201         return cw1200_reg_write(priv, addr, &val, sizeof(val));
 202 }
 203
 204 int cw1200_indirect_read(struct cw1200_common *priv, u32 addr, void *buf,
 205                          size_t buf_len, u32 prefetch, u16 port_addr);
 206 int cw1200_apb_write(struct cw1200_common *priv, u32 addr, const void *buf,
 207                      size_t buf_len);
 208
 209 static inline int cw1200_apb_read(struct cw1200_common *priv, u32 addr,
 210                                   void *buf, size_t buf_len)
 211 {
 212         return cw1200_indirect_read(priv, addr, buf, buf_len,
 213                                     ST90TDS_CONFIG_PRFETCH_BIT,
 214                                     ST90TDS_SRAM_DPORT_REG_ID);
 215 }
 216
 217 static inline int cw1200_ahb_read(struct cw1200_common *priv, u32 addr,
 218                                   void *buf, size_t buf_len)
 219 {
 220         return cw1200_indirect_read(priv, addr, buf, buf_len,
 221                                     ST90TDS_CONFIG_AHB_PRFETCH_BIT,
 222                                     ST90TDS_AHB_DPORT_REG_ID);
 223 }
 224
 225 static inline int cw1200_apb_read_32(struct cw1200_common *priv,
 226                                      u32 addr, u32 *val)
 227 {
 228         int i = cw1200_apb_read(priv, addr, val, sizeof(*val));
 229         *val = le32_to_cpu(*val);
 230         return i;
 231 }
 232
 233 static inline int cw1200_apb_write_32(struct cw1200_common *priv,
 234                                       u32 addr, u32 val)
 235 {
 236         val = cpu_to_le32(val);
 237         return cw1200_apb_write(priv, addr, &val, sizeof(val));
 238 }
 239 static inline int cw1200_ahb_read_32(struct cw1200_common *priv,
 240                                      u32 addr, u32 *val)
 241 {
 242         int i = cw1200_ahb_read(priv, addr, val, sizeof(*val));
 243         *val = le32_to_cpu(*val);
 244         return i;
 245 }
 246
 247 #endif /* CW1200_HWIO_H_INCLUDED */