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iwlwifi: mvm: rs: organize and cleanup consts
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
26 * in the file called COPYING.
27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
35 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
65 #include <linux/pci.h>
66 #include <linux/pci-aspm.h>
67 #include <linux/interrupt.h>
68 #include <linux/debugfs.h>
69 #include <linux/sched.h>
70 #include <linux/bitops.h>
71 #include <linux/gfp.h>
72 #include <linux/vmalloc.h>
73
74 #include "iwl-drv.h"
75 #include "iwl-trans.h"
76 #include "iwl-csr.h"
77 #include "iwl-prph.h"
78 #include "iwl-agn-hw.h"
79 #include "iwl-fw-error-dump.h"
80 #include "internal.h"
81 #include "iwl-fh.h"
82
83 /* extended range in FW SRAM */
84 #define IWL_FW_MEM_EXTENDED_START 0x40000
85 #define IWL_FW_MEM_EXTENDED_END 0x57FFF
86
87 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
88 {
89 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
90
91 if (!trans_pcie->fw_mon_page)
92 return;
93
94 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
95 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
96 __free_pages(trans_pcie->fw_mon_page,
97 get_order(trans_pcie->fw_mon_size));
98 trans_pcie->fw_mon_page = NULL;
99 trans_pcie->fw_mon_phys = 0;
100 trans_pcie->fw_mon_size = 0;
101 }
102
103 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans)
104 {
105 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
106 struct page *page;
107 dma_addr_t phys;
108 u32 size;
109 u8 power;
110
111 if (trans_pcie->fw_mon_page) {
112 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
113 trans_pcie->fw_mon_size,
114 DMA_FROM_DEVICE);
115 return;
116 }
117
118 phys = 0;
119 for (power = 26; power >= 11; power--) {
120 int order;
121
122 size = BIT(power);
123 order = get_order(size);
124 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
125 order);
126 if (!page)
127 continue;
128
129 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
130 DMA_FROM_DEVICE);
131 if (dma_mapping_error(trans->dev, phys)) {
132 __free_pages(page, order);
133 continue;
134 }
135 IWL_INFO(trans,
136 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
137 size, order);
138 break;
139 }
140
141 if (WARN_ON_ONCE(!page))
142 return;
143
144 trans_pcie->fw_mon_page = page;
145 trans_pcie->fw_mon_phys = phys;
146 trans_pcie->fw_mon_size = size;
147 }
148
149 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
150 {
151 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
152 ((reg & 0x0000ffff) | (2 << 28)));
153 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
154 }
155
156 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
157 {
158 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
159 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
160 ((reg & 0x0000ffff) | (3 << 28)));
161 }
162
163 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
164 {
165 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
166 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
167 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
168 ~APMG_PS_CTRL_MSK_PWR_SRC);
169 else
170 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
171 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
172 ~APMG_PS_CTRL_MSK_PWR_SRC);
173 }
174
175 /* PCI registers */
176 #define PCI_CFG_RETRY_TIMEOUT 0x041
177
178 static void iwl_pcie_apm_config(struct iwl_trans *trans)
179 {
180 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
181 u16 lctl;
182 u16 cap;
183
184 /*
185 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
186 * Check if BIOS (or OS) enabled L1-ASPM on this device.
187 * If so (likely), disable L0S, so device moves directly L0->L1;
188 * costs negligible amount of power savings.
189 * If not (unlikely), enable L0S, so there is at least some
190 * power savings, even without L1.
191 */
192 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
193 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
194 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
195 else
196 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
197 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
198
199 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
200 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
201 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
202 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
203 trans->ltr_enabled ? "En" : "Dis");
204 }
205
206 /*
207 * Start up NIC's basic functionality after it has been reset
208 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
209 * NOTE: This does not load uCode nor start the embedded processor
210 */
211 static int iwl_pcie_apm_init(struct iwl_trans *trans)
212 {
213 int ret = 0;
214 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
215
216 /*
217 * Use "set_bit" below rather than "write", to preserve any hardware
218 * bits already set by default after reset.
219 */
220
221 /* Disable L0S exit timer (platform NMI Work/Around) */
222 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
223 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
224 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
225
226 /*
227 * Disable L0s without affecting L1;
228 * don't wait for ICH L0s (ICH bug W/A)
229 */
230 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
231 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
232
233 /* Set FH wait threshold to maximum (HW error during stress W/A) */
234 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
235
236 /*
237 * Enable HAP INTA (interrupt from management bus) to
238 * wake device's PCI Express link L1a -> L0s
239 */
240 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
241 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
242
243 iwl_pcie_apm_config(trans);
244
245 /* Configure analog phase-lock-loop before activating to D0A */
246 if (trans->cfg->base_params->pll_cfg_val)
247 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
248 trans->cfg->base_params->pll_cfg_val);
249
250 /*
251 * Set "initialization complete" bit to move adapter from
252 * D0U* --> D0A* (powered-up active) state.
253 */
254 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
255
256 /*
257 * Wait for clock stabilization; once stabilized, access to
258 * device-internal resources is supported, e.g. iwl_write_prph()
259 * and accesses to uCode SRAM.
260 */
261 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
262 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
263 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
264 if (ret < 0) {
265 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
266 goto out;
267 }
268
269 if (trans->cfg->host_interrupt_operation_mode) {
270 /*
271 * This is a bit of an abuse - This is needed for 7260 / 3160
272 * only check host_interrupt_operation_mode even if this is
273 * not related to host_interrupt_operation_mode.
274 *
275 * Enable the oscillator to count wake up time for L1 exit. This
276 * consumes slightly more power (100uA) - but allows to be sure
277 * that we wake up from L1 on time.
278 *
279 * This looks weird: read twice the same register, discard the
280 * value, set a bit, and yet again, read that same register
281 * just to discard the value. But that's the way the hardware
282 * seems to like it.
283 */
284 iwl_read_prph(trans, OSC_CLK);
285 iwl_read_prph(trans, OSC_CLK);
286 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
287 iwl_read_prph(trans, OSC_CLK);
288 iwl_read_prph(trans, OSC_CLK);
289 }
290
291 /*
292 * Enable DMA clock and wait for it to stabilize.
293 *
294 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
295 * bits do not disable clocks. This preserves any hardware
296 * bits already set by default in "CLK_CTRL_REG" after reset.
297 */
298 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
299 iwl_write_prph(trans, APMG_CLK_EN_REG,
300 APMG_CLK_VAL_DMA_CLK_RQT);
301 udelay(20);
302
303 /* Disable L1-Active */
304 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
305 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
306
307 /* Clear the interrupt in APMG if the NIC is in RFKILL */
308 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
309 APMG_RTC_INT_STT_RFKILL);
310 }
311
312 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
313
314 out:
315 return ret;
316 }
317
318 /*
319 * Enable LP XTAL to avoid HW bug where device may consume much power if
320 * FW is not loaded after device reset. LP XTAL is disabled by default
321 * after device HW reset. Do it only if XTAL is fed by internal source.
322 * Configure device's "persistence" mode to avoid resetting XTAL again when
323 * SHRD_HW_RST occurs in S3.
324 */
325 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
326 {
327 int ret;
328 u32 apmg_gp1_reg;
329 u32 apmg_xtal_cfg_reg;
330 u32 dl_cfg_reg;
331
332 /* Force XTAL ON */
333 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
334 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
335
336 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
337 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
338
339 udelay(10);
340
341 /*
342 * Set "initialization complete" bit to move adapter from
343 * D0U* --> D0A* (powered-up active) state.
344 */
345 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
346
347 /*
348 * Wait for clock stabilization; once stabilized, access to
349 * device-internal resources is possible.
350 */
351 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
352 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
353 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
354 25000);
355 if (WARN_ON(ret < 0)) {
356 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
357 /* Release XTAL ON request */
358 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
360 return;
361 }
362
363 /*
364 * Clear "disable persistence" to avoid LP XTAL resetting when
365 * SHRD_HW_RST is applied in S3.
366 */
367 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
368 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
369
370 /*
371 * Force APMG XTAL to be active to prevent its disabling by HW
372 * caused by APMG idle state.
373 */
374 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
375 SHR_APMG_XTAL_CFG_REG);
376 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
377 apmg_xtal_cfg_reg |
378 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
379
380 /*
381 * Reset entire device again - do controller reset (results in
382 * SHRD_HW_RST). Turn MAC off before proceeding.
383 */
384 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
385
386 udelay(10);
387
388 /* Enable LP XTAL by indirect access through CSR */
389 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
390 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
391 SHR_APMG_GP1_WF_XTAL_LP_EN |
392 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
393
394 /* Clear delay line clock power up */
395 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
396 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
397 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
398
399 /*
400 * Enable persistence mode to avoid LP XTAL resetting when
401 * SHRD_HW_RST is applied in S3.
402 */
403 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
404 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
405
406 /*
407 * Clear "initialization complete" bit to move adapter from
408 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
409 */
410 iwl_clear_bit(trans, CSR_GP_CNTRL,
411 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
412
413 /* Activates XTAL resources monitor */
414 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
415 CSR_MONITOR_XTAL_RESOURCES);
416
417 /* Release XTAL ON request */
418 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
419 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
420 udelay(10);
421
422 /* Release APMG XTAL */
423 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
424 apmg_xtal_cfg_reg &
425 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
426 }
427
428 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
429 {
430 int ret = 0;
431
432 /* stop device's busmaster DMA activity */
433 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
434
435 ret = iwl_poll_bit(trans, CSR_RESET,
436 CSR_RESET_REG_FLAG_MASTER_DISABLED,
437 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
438 if (ret < 0)
439 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
440
441 IWL_DEBUG_INFO(trans, "stop master\n");
442
443 return ret;
444 }
445
446 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
447 {
448 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
449
450 if (op_mode_leave) {
451 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
452 iwl_pcie_apm_init(trans);
453
454 /* inform ME that we are leaving */
455 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
456 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
457 APMG_PCIDEV_STT_VAL_WAKE_ME);
458 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
459 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
460 CSR_HW_IF_CONFIG_REG_PREPARE |
461 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
462 mdelay(5);
463 }
464
465 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
466
467 /* Stop device's DMA activity */
468 iwl_pcie_apm_stop_master(trans);
469
470 if (trans->cfg->lp_xtal_workaround) {
471 iwl_pcie_apm_lp_xtal_enable(trans);
472 return;
473 }
474
475 /* Reset the entire device */
476 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
477
478 udelay(10);
479
480 /*
481 * Clear "initialization complete" bit to move adapter from
482 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
483 */
484 iwl_clear_bit(trans, CSR_GP_CNTRL,
485 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
486 }
487
488 static int iwl_pcie_nic_init(struct iwl_trans *trans)
489 {
490 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
491
492 /* nic_init */
493 spin_lock(&trans_pcie->irq_lock);
494 iwl_pcie_apm_init(trans);
495
496 spin_unlock(&trans_pcie->irq_lock);
497
498 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
499 iwl_pcie_set_pwr(trans, false);
500
501 iwl_op_mode_nic_config(trans->op_mode);
502
503 /* Allocate the RX queue, or reset if it is already allocated */
504 iwl_pcie_rx_init(trans);
505
506 /* Allocate or reset and init all Tx and Command queues */
507 if (iwl_pcie_tx_init(trans))
508 return -ENOMEM;
509
510 if (trans->cfg->base_params->shadow_reg_enable) {
511 /* enable shadow regs in HW */
512 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
513 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
514 }
515
516 return 0;
517 }
518
519 #define HW_READY_TIMEOUT (50)
520
521 /* Note: returns poll_bit return value, which is >= 0 if success */
522 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
523 {
524 int ret;
525
526 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
527 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
528
529 /* See if we got it */
530 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
531 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
532 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
533 HW_READY_TIMEOUT);
534
535 if (ret >= 0)
536 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
537
538 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
539 return ret;
540 }
541
542 /* Note: returns standard 0/-ERROR code */
543 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
544 {
545 int ret;
546 int t = 0;
547 int iter;
548
549 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
550
551 ret = iwl_pcie_set_hw_ready(trans);
552 /* If the card is ready, exit 0 */
553 if (ret >= 0)
554 return 0;
555
556 for (iter = 0; iter < 10; iter++) {
557 /* If HW is not ready, prepare the conditions to check again */
558 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
559 CSR_HW_IF_CONFIG_REG_PREPARE);
560
561 do {
562 ret = iwl_pcie_set_hw_ready(trans);
563 if (ret >= 0)
564 return 0;
565
566 usleep_range(200, 1000);
567 t += 200;
568 } while (t < 150000);
569 msleep(25);
570 }
571
572 IWL_ERR(trans, "Couldn't prepare the card\n");
573
574 return ret;
575 }
576
577 /*
578 * ucode
579 */
580 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
581 dma_addr_t phy_addr, u32 byte_cnt)
582 {
583 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
584 int ret;
585
586 trans_pcie->ucode_write_complete = false;
587
588 iwl_write_direct32(trans,
589 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
590 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
591
592 iwl_write_direct32(trans,
593 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
594 dst_addr);
595
596 iwl_write_direct32(trans,
597 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
598 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
599
600 iwl_write_direct32(trans,
601 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
602 (iwl_get_dma_hi_addr(phy_addr)
603 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
604
605 iwl_write_direct32(trans,
606 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
607 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
608 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
609 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
610
611 iwl_write_direct32(trans,
612 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
613 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
614 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
615 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
616
617 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
618 trans_pcie->ucode_write_complete, 5 * HZ);
619 if (!ret) {
620 IWL_ERR(trans, "Failed to load firmware chunk!\n");
621 return -ETIMEDOUT;
622 }
623
624 return 0;
625 }
626
627 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
628 const struct fw_desc *section)
629 {
630 u8 *v_addr;
631 dma_addr_t p_addr;
632 u32 offset, chunk_sz = section->len;
633 int ret = 0;
634
635 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
636 section_num);
637
638 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
639 GFP_KERNEL | __GFP_NOWARN);
640 if (!v_addr) {
641 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
642 chunk_sz = PAGE_SIZE;
643 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
644 &p_addr, GFP_KERNEL);
645 if (!v_addr)
646 return -ENOMEM;
647 }
648
649 for (offset = 0; offset < section->len; offset += chunk_sz) {
650 u32 copy_size, dst_addr;
651 bool extended_addr = false;
652
653 copy_size = min_t(u32, chunk_sz, section->len - offset);
654 dst_addr = section->offset + offset;
655
656 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
657 dst_addr <= IWL_FW_MEM_EXTENDED_END)
658 extended_addr = true;
659
660 if (extended_addr)
661 iwl_set_bits_prph(trans, LMPM_CHICK,
662 LMPM_CHICK_EXTENDED_ADDR_SPACE);
663
664 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
665 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
666 copy_size);
667
668 if (extended_addr)
669 iwl_clear_bits_prph(trans, LMPM_CHICK,
670 LMPM_CHICK_EXTENDED_ADDR_SPACE);
671
672 if (ret) {
673 IWL_ERR(trans,
674 "Could not load the [%d] uCode section\n",
675 section_num);
676 break;
677 }
678 }
679
680 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
681 return ret;
682 }
683
684 static int iwl_pcie_load_cpu_sections_8000b(struct iwl_trans *trans,
685 const struct fw_img *image,
686 int cpu,
687 int *first_ucode_section)
688 {
689 int shift_param;
690 int i, ret = 0, sec_num = 0x1;
691 u32 val, last_read_idx = 0;
692
693 if (cpu == 1) {
694 shift_param = 0;
695 *first_ucode_section = 0;
696 } else {
697 shift_param = 16;
698 (*first_ucode_section)++;
699 }
700
701 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
702 last_read_idx = i;
703
704 if (!image->sec[i].data ||
705 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
706 IWL_DEBUG_FW(trans,
707 "Break since Data not valid or Empty section, sec = %d\n",
708 i);
709 break;
710 }
711
712 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
713 if (ret)
714 return ret;
715
716 /* Notify the ucode of the loaded section number and status */
717 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
718 val = val | (sec_num << shift_param);
719 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
720 sec_num = (sec_num << 1) | 0x1;
721 }
722
723 *first_ucode_section = last_read_idx;
724
725 return 0;
726 }
727
728 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
729 const struct fw_img *image,
730 int cpu,
731 int *first_ucode_section)
732 {
733 int shift_param;
734 int i, ret = 0;
735 u32 last_read_idx = 0;
736
737 if (cpu == 1) {
738 shift_param = 0;
739 *first_ucode_section = 0;
740 } else {
741 shift_param = 16;
742 (*first_ucode_section)++;
743 }
744
745 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
746 last_read_idx = i;
747
748 if (!image->sec[i].data ||
749 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION) {
750 IWL_DEBUG_FW(trans,
751 "Break since Data not valid or Empty section, sec = %d\n",
752 i);
753 break;
754 }
755
756 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
757 if (ret)
758 return ret;
759 }
760
761 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
762 iwl_set_bits_prph(trans,
763 CSR_UCODE_LOAD_STATUS_ADDR,
764 (LMPM_CPU_UCODE_LOADING_COMPLETED |
765 LMPM_CPU_HDRS_LOADING_COMPLETED |
766 LMPM_CPU_UCODE_LOADING_STARTED) <<
767 shift_param);
768
769 *first_ucode_section = last_read_idx;
770
771 return 0;
772 }
773
774 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
775 {
776 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
777 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
778 int i;
779
780 if (dest->version)
781 IWL_ERR(trans,
782 "DBG DEST version is %d - expect issues\n",
783 dest->version);
784
785 IWL_INFO(trans, "Applying debug destination %s\n",
786 get_fw_dbg_mode_string(dest->monitor_mode));
787
788 if (dest->monitor_mode == EXTERNAL_MODE)
789 iwl_pcie_alloc_fw_monitor(trans);
790 else
791 IWL_WARN(trans, "PCI should have external buffer debug\n");
792
793 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
794 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
795 u32 val = le32_to_cpu(dest->reg_ops[i].val);
796
797 switch (dest->reg_ops[i].op) {
798 case CSR_ASSIGN:
799 iwl_write32(trans, addr, val);
800 break;
801 case CSR_SETBIT:
802 iwl_set_bit(trans, addr, BIT(val));
803 break;
804 case CSR_CLEARBIT:
805 iwl_clear_bit(trans, addr, BIT(val));
806 break;
807 case PRPH_ASSIGN:
808 iwl_write_prph(trans, addr, val);
809 break;
810 case PRPH_SETBIT:
811 iwl_set_bits_prph(trans, addr, BIT(val));
812 break;
813 case PRPH_CLEARBIT:
814 iwl_clear_bits_prph(trans, addr, BIT(val));
815 break;
816 default:
817 IWL_ERR(trans, "FW debug - unknown OP %d\n",
818 dest->reg_ops[i].op);
819 break;
820 }
821 }
822
823 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
824 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
825 trans_pcie->fw_mon_phys >> dest->base_shift);
826 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
827 (trans_pcie->fw_mon_phys +
828 trans_pcie->fw_mon_size) >> dest->end_shift);
829 }
830 }
831
832 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
833 const struct fw_img *image)
834 {
835 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
836 int ret = 0;
837 int first_ucode_section;
838
839 IWL_DEBUG_FW(trans, "working with %s CPU\n",
840 image->is_dual_cpus ? "Dual" : "Single");
841
842 /* load to FW the binary non secured sections of CPU1 */
843 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
844 if (ret)
845 return ret;
846
847 if (image->is_dual_cpus) {
848 /* set CPU2 header address */
849 iwl_write_prph(trans,
850 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
851 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
852
853 /* load to FW the binary sections of CPU2 */
854 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
855 &first_ucode_section);
856 if (ret)
857 return ret;
858 }
859
860 /* supported for 7000 only for the moment */
861 if (iwlwifi_mod_params.fw_monitor &&
862 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
863 iwl_pcie_alloc_fw_monitor(trans);
864
865 if (trans_pcie->fw_mon_size) {
866 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
867 trans_pcie->fw_mon_phys >> 4);
868 iwl_write_prph(trans, MON_BUFF_END_ADDR,
869 (trans_pcie->fw_mon_phys +
870 trans_pcie->fw_mon_size) >> 4);
871 }
872 } else if (trans->dbg_dest_tlv) {
873 iwl_pcie_apply_destination(trans);
874 }
875
876 /* release CPU reset */
877 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
878 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
879 else
880 iwl_write32(trans, CSR_RESET, 0);
881
882 return 0;
883 }
884
885 static int iwl_pcie_load_given_ucode_8000b(struct iwl_trans *trans,
886 const struct fw_img *image)
887 {
888 int ret = 0;
889 int first_ucode_section;
890 u32 reg;
891
892 IWL_DEBUG_FW(trans, "working with %s CPU\n",
893 image->is_dual_cpus ? "Dual" : "Single");
894
895 /* configure the ucode to be ready to get the secured image */
896 /* release CPU reset */
897 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
898
899 /* load to FW the binary Secured sections of CPU1 */
900 ret = iwl_pcie_load_cpu_sections_8000b(trans, image, 1,
901 &first_ucode_section);
902 if (ret)
903 return ret;
904
905 /* load to FW the binary sections of CPU2 */
906 ret = iwl_pcie_load_cpu_sections_8000b(trans, image, 2,
907 &first_ucode_section);
908 if (ret)
909 return ret;
910
911 if (trans->dbg_dest_tlv)
912 iwl_pcie_apply_destination(trans);
913
914 /* Notify FW loading is done */
915 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);
916
917 /* wait for image verification to complete */
918 ret = iwl_poll_prph_bit(trans, LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0,
919 LMPM_SECURE_BOOT_STATUS_SUCCESS,
920 LMPM_SECURE_BOOT_STATUS_SUCCESS,
921 LMPM_SECURE_TIME_OUT);
922 if (ret < 0) {
923 reg = iwl_read_prph(trans,
924 LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0);
925
926 IWL_ERR(trans, "Timeout on secure boot process, reg = %x\n",
927 reg);
928 return ret;
929 }
930
931 return 0;
932 }
933
934 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
935 const struct fw_img *fw, bool run_in_rfkill)
936 {
937 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
938 int ret;
939 bool hw_rfkill;
940
941 /* This may fail if AMT took ownership of the device */
942 if (iwl_pcie_prepare_card_hw(trans)) {
943 IWL_WARN(trans, "Exit HW not ready\n");
944 return -EIO;
945 }
946
947 iwl_enable_rfkill_int(trans);
948
949 /* If platform's RF_KILL switch is NOT set to KILL */
950 hw_rfkill = iwl_is_rfkill_set(trans);
951 if (hw_rfkill)
952 set_bit(STATUS_RFKILL, &trans->status);
953 else
954 clear_bit(STATUS_RFKILL, &trans->status);
955 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
956 if (hw_rfkill && !run_in_rfkill)
957 return -ERFKILL;
958
959 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
960
961 ret = iwl_pcie_nic_init(trans);
962 if (ret) {
963 IWL_ERR(trans, "Unable to init nic\n");
964 return ret;
965 }
966
967 /* init ref_count to 1 (should be cleared when ucode is loaded) */
968 trans_pcie->ref_count = 1;
969
970 /* make sure rfkill handshake bits are cleared */
971 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
972 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
973 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
974
975 /* clear (again), then enable host interrupts */
976 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
977 iwl_enable_interrupts(trans);
978
979 /* really make sure rfkill handshake bits are cleared */
980 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
981 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
982
983 /* Load the given image to the HW */
984 if ((trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) &&
985 (CSR_HW_REV_STEP(trans->hw_rev) == SILICON_B_STEP))
986 return iwl_pcie_load_given_ucode_8000b(trans, fw);
987 else
988 return iwl_pcie_load_given_ucode(trans, fw);
989 }
990
991 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
992 {
993 iwl_pcie_reset_ict(trans);
994 iwl_pcie_tx_start(trans, scd_addr);
995 }
996
997 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
998 {
999 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1000 bool hw_rfkill, was_hw_rfkill;
1001
1002 was_hw_rfkill = iwl_is_rfkill_set(trans);
1003
1004 /* tell the device to stop sending interrupts */
1005 spin_lock(&trans_pcie->irq_lock);
1006 iwl_disable_interrupts(trans);
1007 spin_unlock(&trans_pcie->irq_lock);
1008
1009 /* device going down, Stop using ICT table */
1010 iwl_pcie_disable_ict(trans);
1011
1012 /*
1013 * If a HW restart happens during firmware loading,
1014 * then the firmware loading might call this function
1015 * and later it might be called again due to the
1016 * restart. So don't process again if the device is
1017 * already dead.
1018 */
1019 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1020 IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n");
1021 iwl_pcie_tx_stop(trans);
1022 iwl_pcie_rx_stop(trans);
1023
1024 /* Power-down device's busmaster DMA clocks */
1025 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1026 APMG_CLK_VAL_DMA_CLK_RQT);
1027 udelay(5);
1028 }
1029
1030 /* Make sure (redundant) we've released our request to stay awake */
1031 iwl_clear_bit(trans, CSR_GP_CNTRL,
1032 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1033
1034 /* Stop the device, and put it in low power state */
1035 iwl_pcie_apm_stop(trans, false);
1036
1037 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1038 * Clean again the interrupt here
1039 */
1040 spin_lock(&trans_pcie->irq_lock);
1041 iwl_disable_interrupts(trans);
1042 spin_unlock(&trans_pcie->irq_lock);
1043
1044 /* stop and reset the on-board processor */
1045 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1046 udelay(20);
1047
1048 /* clear all status bits */
1049 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1050 clear_bit(STATUS_INT_ENABLED, &trans->status);
1051 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1052 clear_bit(STATUS_RFKILL, &trans->status);
1053
1054 /*
1055 * Even if we stop the HW, we still want the RF kill
1056 * interrupt
1057 */
1058 iwl_enable_rfkill_int(trans);
1059
1060 /*
1061 * Check again since the RF kill state may have changed while
1062 * all the interrupts were disabled, in this case we couldn't
1063 * receive the RF kill interrupt and update the state in the
1064 * op_mode.
1065 * Don't call the op_mode if the rkfill state hasn't changed.
1066 * This allows the op_mode to call stop_device from the rfkill
1067 * notification without endless recursion. Under very rare
1068 * circumstances, we might have a small recursion if the rfkill
1069 * state changed exactly now while we were called from stop_device.
1070 * This is very unlikely but can happen and is supported.
1071 */
1072 hw_rfkill = iwl_is_rfkill_set(trans);
1073 if (hw_rfkill)
1074 set_bit(STATUS_RFKILL, &trans->status);
1075 else
1076 clear_bit(STATUS_RFKILL, &trans->status);
1077 if (hw_rfkill != was_hw_rfkill)
1078 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1079
1080 /* re-take ownership to prevent other users from stealing the deivce */
1081 iwl_pcie_prepare_card_hw(trans);
1082 }
1083
1084 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1085 {
1086 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1087 iwl_trans_pcie_stop_device(trans);
1088 }
1089
1090 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
1091 {
1092 iwl_disable_interrupts(trans);
1093
1094 /*
1095 * in testing mode, the host stays awake and the
1096 * hardware won't be reset (not even partially)
1097 */
1098 if (test)
1099 return;
1100
1101 iwl_pcie_disable_ict(trans);
1102
1103 iwl_clear_bit(trans, CSR_GP_CNTRL,
1104 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1105 iwl_clear_bit(trans, CSR_GP_CNTRL,
1106 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1107
1108 /*
1109 * reset TX queues -- some of their registers reset during S3
1110 * so if we don't reset everything here the D3 image would try
1111 * to execute some invalid memory upon resume
1112 */
1113 iwl_trans_pcie_tx_reset(trans);
1114
1115 iwl_pcie_set_pwr(trans, true);
1116 }
1117
1118 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1119 enum iwl_d3_status *status,
1120 bool test)
1121 {
1122 u32 val;
1123 int ret;
1124
1125 if (test) {
1126 iwl_enable_interrupts(trans);
1127 *status = IWL_D3_STATUS_ALIVE;
1128 return 0;
1129 }
1130
1131 /*
1132 * Also enables interrupts - none will happen as the device doesn't
1133 * know we're waking it up, only when the opmode actually tells it
1134 * after this call.
1135 */
1136 iwl_pcie_reset_ict(trans);
1137
1138 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1139 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1140
1141 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1142 udelay(2);
1143
1144 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1145 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1146 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1147 25000);
1148 if (ret < 0) {
1149 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1150 return ret;
1151 }
1152
1153 iwl_pcie_set_pwr(trans, false);
1154
1155 iwl_trans_pcie_tx_reset(trans);
1156
1157 ret = iwl_pcie_rx_init(trans);
1158 if (ret) {
1159 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
1160 return ret;
1161 }
1162
1163 val = iwl_read32(trans, CSR_RESET);
1164 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1165 *status = IWL_D3_STATUS_RESET;
1166 else
1167 *status = IWL_D3_STATUS_ALIVE;
1168
1169 return 0;
1170 }
1171
1172 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1173 {
1174 bool hw_rfkill;
1175 int err;
1176
1177 err = iwl_pcie_prepare_card_hw(trans);
1178 if (err) {
1179 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1180 return err;
1181 }
1182
1183 /* Reset the entire device */
1184 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1185
1186 usleep_range(10, 15);
1187
1188 iwl_pcie_apm_init(trans);
1189
1190 /* From now on, the op_mode will be kept updated about RF kill state */
1191 iwl_enable_rfkill_int(trans);
1192
1193 hw_rfkill = iwl_is_rfkill_set(trans);
1194 if (hw_rfkill)
1195 set_bit(STATUS_RFKILL, &trans->status);
1196 else
1197 clear_bit(STATUS_RFKILL, &trans->status);
1198 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1199
1200 return 0;
1201 }
1202
1203 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1204 {
1205 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1206
1207 /* disable interrupts - don't enable HW RF kill interrupt */
1208 spin_lock(&trans_pcie->irq_lock);
1209 iwl_disable_interrupts(trans);
1210 spin_unlock(&trans_pcie->irq_lock);
1211
1212 iwl_pcie_apm_stop(trans, true);
1213
1214 spin_lock(&trans_pcie->irq_lock);
1215 iwl_disable_interrupts(trans);
1216 spin_unlock(&trans_pcie->irq_lock);
1217
1218 iwl_pcie_disable_ict(trans);
1219 }
1220
1221 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1222 {
1223 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1224 }
1225
1226 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1227 {
1228 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1229 }
1230
1231 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1232 {
1233 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1234 }
1235
1236 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1237 {
1238 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1239 ((reg & 0x000FFFFF) | (3 << 24)));
1240 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1241 }
1242
1243 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1244 u32 val)
1245 {
1246 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1247 ((addr & 0x000FFFFF) | (3 << 24)));
1248 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1249 }
1250
1251 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1252 {
1253 WARN_ON(1);
1254 return 0;
1255 }
1256
1257 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1258 const struct iwl_trans_config *trans_cfg)
1259 {
1260 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1261
1262 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1263 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1264 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1265 trans_pcie->n_no_reclaim_cmds = 0;
1266 else
1267 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1268 if (trans_pcie->n_no_reclaim_cmds)
1269 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1270 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1271
1272 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1273 if (trans_pcie->rx_buf_size_8k)
1274 trans_pcie->rx_page_order = get_order(8 * 1024);
1275 else
1276 trans_pcie->rx_page_order = get_order(4 * 1024);
1277
1278 trans_pcie->wd_timeout =
1279 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1280
1281 trans_pcie->command_names = trans_cfg->command_names;
1282 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1283 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1284
1285 /* Initialize NAPI here - it should be before registering to mac80211
1286 * in the opmode but after the HW struct is allocated.
1287 * As this function may be called again in some corner cases don't
1288 * do anything if NAPI was already initialized.
1289 */
1290 if (!trans_pcie->napi.poll && trans->op_mode->ops->napi_add) {
1291 init_dummy_netdev(&trans_pcie->napi_dev);
1292 iwl_op_mode_napi_add(trans->op_mode, &trans_pcie->napi,
1293 &trans_pcie->napi_dev,
1294 iwl_pcie_dummy_napi_poll, 64);
1295 }
1296 }
1297
1298 void iwl_trans_pcie_free(struct iwl_trans *trans)
1299 {
1300 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1301
1302 synchronize_irq(trans_pcie->pci_dev->irq);
1303
1304 iwl_pcie_tx_free(trans);
1305 iwl_pcie_rx_free(trans);
1306
1307 free_irq(trans_pcie->pci_dev->irq, trans);
1308 iwl_pcie_free_ict(trans);
1309
1310 pci_disable_msi(trans_pcie->pci_dev);
1311 iounmap(trans_pcie->hw_base);
1312 pci_release_regions(trans_pcie->pci_dev);
1313 pci_disable_device(trans_pcie->pci_dev);
1314 kmem_cache_destroy(trans->dev_cmd_pool);
1315
1316 if (trans_pcie->napi.poll)
1317 netif_napi_del(&trans_pcie->napi);
1318
1319 iwl_pcie_free_fw_monitor(trans);
1320
1321 kfree(trans);
1322 }
1323
1324 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1325 {
1326 if (state)
1327 set_bit(STATUS_TPOWER_PMI, &trans->status);
1328 else
1329 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1330 }
1331
1332 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
1333 unsigned long *flags)
1334 {
1335 int ret;
1336 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1337
1338 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1339
1340 if (trans_pcie->cmd_in_flight)
1341 goto out;
1342
1343 /* this bit wakes up the NIC */
1344 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1345 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1346 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1347 udelay(2);
1348
1349 /*
1350 * These bits say the device is running, and should keep running for
1351 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1352 * but they do not indicate that embedded SRAM is restored yet;
1353 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1354 * to/from host DRAM when sleeping/waking for power-saving.
1355 * Each direction takes approximately 1/4 millisecond; with this
1356 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1357 * series of register accesses are expected (e.g. reading Event Log),
1358 * to keep device from sleeping.
1359 *
1360 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1361 * SRAM is okay/restored. We don't check that here because this call
1362 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1363 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1364 *
1365 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1366 * and do not save/restore SRAM when power cycling.
1367 */
1368 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1369 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1370 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1371 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1372 if (unlikely(ret < 0)) {
1373 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1374 if (!silent) {
1375 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
1376 WARN_ONCE(1,
1377 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1378 val);
1379 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1380 return false;
1381 }
1382 }
1383
1384 out:
1385 /*
1386 * Fool sparse by faking we release the lock - sparse will
1387 * track nic_access anyway.
1388 */
1389 __release(&trans_pcie->reg_lock);
1390 return true;
1391 }
1392
1393 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1394 unsigned long *flags)
1395 {
1396 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1397
1398 lockdep_assert_held(&trans_pcie->reg_lock);
1399
1400 /*
1401 * Fool sparse by faking we acquiring the lock - sparse will
1402 * track nic_access anyway.
1403 */
1404 __acquire(&trans_pcie->reg_lock);
1405
1406 if (trans_pcie->cmd_in_flight)
1407 goto out;
1408
1409 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1410 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1411 /*
1412 * Above we read the CSR_GP_CNTRL register, which will flush
1413 * any previous writes, but we need the write that clears the
1414 * MAC_ACCESS_REQ bit to be performed before any other writes
1415 * scheduled on different CPUs (after we drop reg_lock).
1416 */
1417 mmiowb();
1418 out:
1419 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1420 }
1421
1422 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1423 void *buf, int dwords)
1424 {
1425 unsigned long flags;
1426 int offs, ret = 0;
1427 u32 *vals = buf;
1428
1429 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1430 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1431 for (offs = 0; offs < dwords; offs++)
1432 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1433 iwl_trans_release_nic_access(trans, &flags);
1434 } else {
1435 ret = -EBUSY;
1436 }
1437 return ret;
1438 }
1439
1440 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1441 const void *buf, int dwords)
1442 {
1443 unsigned long flags;
1444 int offs, ret = 0;
1445 const u32 *vals = buf;
1446
1447 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1448 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1449 for (offs = 0; offs < dwords; offs++)
1450 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1451 vals ? vals[offs] : 0);
1452 iwl_trans_release_nic_access(trans, &flags);
1453 } else {
1454 ret = -EBUSY;
1455 }
1456 return ret;
1457 }
1458
1459 #define IWL_FLUSH_WAIT_MS 2000
1460
1461 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
1462 {
1463 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1464 struct iwl_txq *txq;
1465 struct iwl_queue *q;
1466 int cnt;
1467 unsigned long now = jiffies;
1468 u32 scd_sram_addr;
1469 u8 buf[16];
1470 int ret = 0;
1471
1472 /* waiting for all the tx frames complete might take a while */
1473 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1474 u8 wr_ptr;
1475
1476 if (cnt == trans_pcie->cmd_queue)
1477 continue;
1478 if (!test_bit(cnt, trans_pcie->queue_used))
1479 continue;
1480 if (!(BIT(cnt) & txq_bm))
1481 continue;
1482
1483 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
1484 txq = &trans_pcie->txq[cnt];
1485 q = &txq->q;
1486 wr_ptr = ACCESS_ONCE(q->write_ptr);
1487
1488 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) &&
1489 !time_after(jiffies,
1490 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
1491 u8 write_ptr = ACCESS_ONCE(q->write_ptr);
1492
1493 if (WARN_ONCE(wr_ptr != write_ptr,
1494 "WR pointer moved while flushing %d -> %d\n",
1495 wr_ptr, write_ptr))
1496 return -ETIMEDOUT;
1497 msleep(1);
1498 }
1499
1500 if (q->read_ptr != q->write_ptr) {
1501 IWL_ERR(trans,
1502 "fail to flush all tx fifo queues Q %d\n", cnt);
1503 ret = -ETIMEDOUT;
1504 break;
1505 }
1506 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
1507 }
1508
1509 if (!ret)
1510 return 0;
1511
1512 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1513 txq->q.read_ptr, txq->q.write_ptr);
1514
1515 scd_sram_addr = trans_pcie->scd_base_addr +
1516 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1517 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1518
1519 iwl_print_hex_error(trans, buf, sizeof(buf));
1520
1521 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1522 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1523 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1524
1525 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1526 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1527 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1528 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1529 u32 tbl_dw =
1530 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1531 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1532
1533 if (cnt & 0x1)
1534 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1535 else
1536 tbl_dw = tbl_dw & 0x0000FFFF;
1537
1538 IWL_ERR(trans,
1539 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1540 cnt, active ? "" : "in", fifo, tbl_dw,
1541 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
1542 (TFD_QUEUE_SIZE_MAX - 1),
1543 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1544 }
1545
1546 return ret;
1547 }
1548
1549 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1550 u32 mask, u32 value)
1551 {
1552 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1553 unsigned long flags;
1554
1555 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1556 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1557 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1558 }
1559
1560 void iwl_trans_pcie_ref(struct iwl_trans *trans)
1561 {
1562 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1563 unsigned long flags;
1564
1565 if (iwlwifi_mod_params.d0i3_disable)
1566 return;
1567
1568 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1569 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1570 trans_pcie->ref_count++;
1571 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1572 }
1573
1574 void iwl_trans_pcie_unref(struct iwl_trans *trans)
1575 {
1576 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1577 unsigned long flags;
1578
1579 if (iwlwifi_mod_params.d0i3_disable)
1580 return;
1581
1582 spin_lock_irqsave(&trans_pcie->ref_lock, flags);
1583 IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count);
1584 if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) {
1585 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1586 return;
1587 }
1588 trans_pcie->ref_count--;
1589 spin_unlock_irqrestore(&trans_pcie->ref_lock, flags);
1590 }
1591
1592 static const char *get_csr_string(int cmd)
1593 {
1594 #define IWL_CMD(x) case x: return #x
1595 switch (cmd) {
1596 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1597 IWL_CMD(CSR_INT_COALESCING);
1598 IWL_CMD(CSR_INT);
1599 IWL_CMD(CSR_INT_MASK);
1600 IWL_CMD(CSR_FH_INT_STATUS);
1601 IWL_CMD(CSR_GPIO_IN);
1602 IWL_CMD(CSR_RESET);
1603 IWL_CMD(CSR_GP_CNTRL);
1604 IWL_CMD(CSR_HW_REV);
1605 IWL_CMD(CSR_EEPROM_REG);
1606 IWL_CMD(CSR_EEPROM_GP);
1607 IWL_CMD(CSR_OTP_GP_REG);
1608 IWL_CMD(CSR_GIO_REG);
1609 IWL_CMD(CSR_GP_UCODE_REG);
1610 IWL_CMD(CSR_GP_DRIVER_REG);
1611 IWL_CMD(CSR_UCODE_DRV_GP1);
1612 IWL_CMD(CSR_UCODE_DRV_GP2);
1613 IWL_CMD(CSR_LED_REG);
1614 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1615 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1616 IWL_CMD(CSR_ANA_PLL_CFG);
1617 IWL_CMD(CSR_HW_REV_WA_REG);
1618 IWL_CMD(CSR_MONITOR_STATUS_REG);
1619 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1620 default:
1621 return "UNKNOWN";
1622 }
1623 #undef IWL_CMD
1624 }
1625
1626 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1627 {
1628 int i;
1629 static const u32 csr_tbl[] = {
1630 CSR_HW_IF_CONFIG_REG,
1631 CSR_INT_COALESCING,
1632 CSR_INT,
1633 CSR_INT_MASK,
1634 CSR_FH_INT_STATUS,
1635 CSR_GPIO_IN,
1636 CSR_RESET,
1637 CSR_GP_CNTRL,
1638 CSR_HW_REV,
1639 CSR_EEPROM_REG,
1640 CSR_EEPROM_GP,
1641 CSR_OTP_GP_REG,
1642 CSR_GIO_REG,
1643 CSR_GP_UCODE_REG,
1644 CSR_GP_DRIVER_REG,
1645 CSR_UCODE_DRV_GP1,
1646 CSR_UCODE_DRV_GP2,
1647 CSR_LED_REG,
1648 CSR_DRAM_INT_TBL_REG,
1649 CSR_GIO_CHICKEN_BITS,
1650 CSR_ANA_PLL_CFG,
1651 CSR_MONITOR_STATUS_REG,
1652 CSR_HW_REV_WA_REG,
1653 CSR_DBG_HPET_MEM_REG
1654 };
1655 IWL_ERR(trans, "CSR values:\n");
1656 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1657 "CSR_INT_PERIODIC_REG)\n");
1658 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1659 IWL_ERR(trans, " %25s: 0X%08x\n",
1660 get_csr_string(csr_tbl[i]),
1661 iwl_read32(trans, csr_tbl[i]));
1662 }
1663 }
1664
1665 #ifdef CONFIG_IWLWIFI_DEBUGFS
1666 /* create and remove of files */
1667 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1668 if (!debugfs_create_file(#name, mode, parent, trans, \
1669 &iwl_dbgfs_##name##_ops)) \
1670 goto err; \
1671 } while (0)
1672
1673 /* file operation */
1674 #define DEBUGFS_READ_FILE_OPS(name) \
1675 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1676 .read = iwl_dbgfs_##name##_read, \
1677 .open = simple_open, \
1678 .llseek = generic_file_llseek, \
1679 };
1680
1681 #define DEBUGFS_WRITE_FILE_OPS(name) \
1682 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1683 .write = iwl_dbgfs_##name##_write, \
1684 .open = simple_open, \
1685 .llseek = generic_file_llseek, \
1686 };
1687
1688 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1689 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1690 .write = iwl_dbgfs_##name##_write, \
1691 .read = iwl_dbgfs_##name##_read, \
1692 .open = simple_open, \
1693 .llseek = generic_file_llseek, \
1694 };
1695
1696 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1697 char __user *user_buf,
1698 size_t count, loff_t *ppos)
1699 {
1700 struct iwl_trans *trans = file->private_data;
1701 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1702 struct iwl_txq *txq;
1703 struct iwl_queue *q;
1704 char *buf;
1705 int pos = 0;
1706 int cnt;
1707 int ret;
1708 size_t bufsz;
1709
1710 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1711
1712 if (!trans_pcie->txq)
1713 return -EAGAIN;
1714
1715 buf = kzalloc(bufsz, GFP_KERNEL);
1716 if (!buf)
1717 return -ENOMEM;
1718
1719 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1720 txq = &trans_pcie->txq[cnt];
1721 q = &txq->q;
1722 pos += scnprintf(buf + pos, bufsz - pos,
1723 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d%s\n",
1724 cnt, q->read_ptr, q->write_ptr,
1725 !!test_bit(cnt, trans_pcie->queue_used),
1726 !!test_bit(cnt, trans_pcie->queue_stopped),
1727 txq->need_update,
1728 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
1729 }
1730 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1731 kfree(buf);
1732 return ret;
1733 }
1734
1735 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1736 char __user *user_buf,
1737 size_t count, loff_t *ppos)
1738 {
1739 struct iwl_trans *trans = file->private_data;
1740 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1741 struct iwl_rxq *rxq = &trans_pcie->rxq;
1742 char buf[256];
1743 int pos = 0;
1744 const size_t bufsz = sizeof(buf);
1745
1746 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1747 rxq->read);
1748 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1749 rxq->write);
1750 pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n",
1751 rxq->write_actual);
1752 pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n",
1753 rxq->need_update);
1754 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1755 rxq->free_count);
1756 if (rxq->rb_stts) {
1757 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1758 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1759 } else {
1760 pos += scnprintf(buf + pos, bufsz - pos,
1761 "closed_rb_num: Not Allocated\n");
1762 }
1763 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1764 }
1765
1766 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1767 char __user *user_buf,
1768 size_t count, loff_t *ppos)
1769 {
1770 struct iwl_trans *trans = file->private_data;
1771 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1772 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1773
1774 int pos = 0;
1775 char *buf;
1776 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1777 ssize_t ret;
1778
1779 buf = kzalloc(bufsz, GFP_KERNEL);
1780 if (!buf)
1781 return -ENOMEM;
1782
1783 pos += scnprintf(buf + pos, bufsz - pos,
1784 "Interrupt Statistics Report:\n");
1785
1786 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1787 isr_stats->hw);
1788 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1789 isr_stats->sw);
1790 if (isr_stats->sw || isr_stats->hw) {
1791 pos += scnprintf(buf + pos, bufsz - pos,
1792 "\tLast Restarting Code: 0x%X\n",
1793 isr_stats->err_code);
1794 }
1795 #ifdef CONFIG_IWLWIFI_DEBUG
1796 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1797 isr_stats->sch);
1798 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1799 isr_stats->alive);
1800 #endif
1801 pos += scnprintf(buf + pos, bufsz - pos,
1802 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1803
1804 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1805 isr_stats->ctkill);
1806
1807 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1808 isr_stats->wakeup);
1809
1810 pos += scnprintf(buf + pos, bufsz - pos,
1811 "Rx command responses:\t\t %u\n", isr_stats->rx);
1812
1813 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1814 isr_stats->tx);
1815
1816 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1817 isr_stats->unhandled);
1818
1819 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1820 kfree(buf);
1821 return ret;
1822 }
1823
1824 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1825 const char __user *user_buf,
1826 size_t count, loff_t *ppos)
1827 {
1828 struct iwl_trans *trans = file->private_data;
1829 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1830 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1831
1832 char buf[8];
1833 int buf_size;
1834 u32 reset_flag;
1835
1836 memset(buf, 0, sizeof(buf));
1837 buf_size = min(count, sizeof(buf) - 1);
1838 if (copy_from_user(buf, user_buf, buf_size))
1839 return -EFAULT;
1840 if (sscanf(buf, "%x", &reset_flag) != 1)
1841 return -EFAULT;
1842 if (reset_flag == 0)
1843 memset(isr_stats, 0, sizeof(*isr_stats));
1844
1845 return count;
1846 }
1847
1848 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1849 const char __user *user_buf,
1850 size_t count, loff_t *ppos)
1851 {
1852 struct iwl_trans *trans = file->private_data;
1853 char buf[8];
1854 int buf_size;
1855 int csr;
1856
1857 memset(buf, 0, sizeof(buf));
1858 buf_size = min(count, sizeof(buf) - 1);
1859 if (copy_from_user(buf, user_buf, buf_size))
1860 return -EFAULT;
1861 if (sscanf(buf, "%d", &csr) != 1)
1862 return -EFAULT;
1863
1864 iwl_pcie_dump_csr(trans);
1865
1866 return count;
1867 }
1868
1869 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1870 char __user *user_buf,
1871 size_t count, loff_t *ppos)
1872 {
1873 struct iwl_trans *trans = file->private_data;
1874 char *buf = NULL;
1875 ssize_t ret;
1876
1877 ret = iwl_dump_fh(trans, &buf);
1878 if (ret < 0)
1879 return ret;
1880 if (!buf)
1881 return -EINVAL;
1882 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1883 kfree(buf);
1884 return ret;
1885 }
1886
1887 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1888 DEBUGFS_READ_FILE_OPS(fh_reg);
1889 DEBUGFS_READ_FILE_OPS(rx_queue);
1890 DEBUGFS_READ_FILE_OPS(tx_queue);
1891 DEBUGFS_WRITE_FILE_OPS(csr);
1892
1893 /*
1894 * Create the debugfs files and directories
1895 *
1896 */
1897 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1898 struct dentry *dir)
1899 {
1900 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1901 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1902 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1903 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1904 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1905 return 0;
1906
1907 err:
1908 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1909 return -ENOMEM;
1910 }
1911 #else
1912 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1913 struct dentry *dir)
1914 {
1915 return 0;
1916 }
1917 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1918
1919 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd)
1920 {
1921 u32 cmdlen = 0;
1922 int i;
1923
1924 for (i = 0; i < IWL_NUM_OF_TBS; i++)
1925 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i);
1926
1927 return cmdlen;
1928 }
1929
1930 static const struct {
1931 u32 start, end;
1932 } iwl_prph_dump_addr[] = {
1933 { .start = 0x00a00000, .end = 0x00a00000 },
1934 { .start = 0x00a0000c, .end = 0x00a00024 },
1935 { .start = 0x00a0002c, .end = 0x00a0003c },
1936 { .start = 0x00a00410, .end = 0x00a00418 },
1937 { .start = 0x00a00420, .end = 0x00a00420 },
1938 { .start = 0x00a00428, .end = 0x00a00428 },
1939 { .start = 0x00a00430, .end = 0x00a0043c },
1940 { .start = 0x00a00444, .end = 0x00a00444 },
1941 { .start = 0x00a004c0, .end = 0x00a004cc },
1942 { .start = 0x00a004d8, .end = 0x00a004d8 },
1943 { .start = 0x00a004e0, .end = 0x00a004f0 },
1944 { .start = 0x00a00840, .end = 0x00a00840 },
1945 { .start = 0x00a00850, .end = 0x00a00858 },
1946 { .start = 0x00a01004, .end = 0x00a01008 },
1947 { .start = 0x00a01010, .end = 0x00a01010 },
1948 { .start = 0x00a01018, .end = 0x00a01018 },
1949 { .start = 0x00a01024, .end = 0x00a01024 },
1950 { .start = 0x00a0102c, .end = 0x00a01034 },
1951 { .start = 0x00a0103c, .end = 0x00a01040 },
1952 { .start = 0x00a01048, .end = 0x00a01094 },
1953 { .start = 0x00a01c00, .end = 0x00a01c20 },
1954 { .start = 0x00a01c58, .end = 0x00a01c58 },
1955 { .start = 0x00a01c7c, .end = 0x00a01c7c },
1956 { .start = 0x00a01c28, .end = 0x00a01c54 },
1957 { .start = 0x00a01c5c, .end = 0x00a01c5c },
1958 { .start = 0x00a01c84, .end = 0x00a01c84 },
1959 { .start = 0x00a01ce0, .end = 0x00a01d0c },
1960 { .start = 0x00a01d18, .end = 0x00a01d20 },
1961 { .start = 0x00a01d2c, .end = 0x00a01d30 },
1962 { .start = 0x00a01d40, .end = 0x00a01d5c },
1963 { .start = 0x00a01d80, .end = 0x00a01d80 },
1964 { .start = 0x00a01d98, .end = 0x00a01d98 },
1965 { .start = 0x00a01dc0, .end = 0x00a01dfc },
1966 { .start = 0x00a01e00, .end = 0x00a01e2c },
1967 { .start = 0x00a01e40, .end = 0x00a01e60 },
1968 { .start = 0x00a01e84, .end = 0x00a01e90 },
1969 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
1970 { .start = 0x00a01ed0, .end = 0x00a01ed0 },
1971 { .start = 0x00a01f00, .end = 0x00a01f14 },
1972 { .start = 0x00a01f44, .end = 0x00a01f58 },
1973 { .start = 0x00a01f80, .end = 0x00a01fa8 },
1974 { .start = 0x00a01fb0, .end = 0x00a01fbc },
1975 { .start = 0x00a01ff8, .end = 0x00a01ffc },
1976 { .start = 0x00a02000, .end = 0x00a02048 },
1977 { .start = 0x00a02068, .end = 0x00a020f0 },
1978 { .start = 0x00a02100, .end = 0x00a02118 },
1979 { .start = 0x00a02140, .end = 0x00a0214c },
1980 { .start = 0x00a02168, .end = 0x00a0218c },
1981 { .start = 0x00a021c0, .end = 0x00a021c0 },
1982 { .start = 0x00a02400, .end = 0x00a02410 },
1983 { .start = 0x00a02418, .end = 0x00a02420 },
1984 { .start = 0x00a02428, .end = 0x00a0242c },
1985 { .start = 0x00a02434, .end = 0x00a02434 },
1986 { .start = 0x00a02440, .end = 0x00a02460 },
1987 { .start = 0x00a02468, .end = 0x00a024b0 },
1988 { .start = 0x00a024c8, .end = 0x00a024cc },
1989 { .start = 0x00a02500, .end = 0x00a02504 },
1990 { .start = 0x00a0250c, .end = 0x00a02510 },
1991 { .start = 0x00a02540, .end = 0x00a02554 },
1992 { .start = 0x00a02580, .end = 0x00a025f4 },
1993 { .start = 0x00a02600, .end = 0x00a0260c },
1994 { .start = 0x00a02648, .end = 0x00a02650 },
1995 { .start = 0x00a02680, .end = 0x00a02680 },
1996 { .start = 0x00a026c0, .end = 0x00a026d0 },
1997 { .start = 0x00a02700, .end = 0x00a0270c },
1998 { .start = 0x00a02804, .end = 0x00a02804 },
1999 { .start = 0x00a02818, .end = 0x00a0281c },
2000 { .start = 0x00a02c00, .end = 0x00a02db4 },
2001 { .start = 0x00a02df4, .end = 0x00a02fb0 },
2002 { .start = 0x00a03000, .end = 0x00a03014 },
2003 { .start = 0x00a0301c, .end = 0x00a0302c },
2004 { .start = 0x00a03034, .end = 0x00a03038 },
2005 { .start = 0x00a03040, .end = 0x00a03048 },
2006 { .start = 0x00a03060, .end = 0x00a03068 },
2007 { .start = 0x00a03070, .end = 0x00a03074 },
2008 { .start = 0x00a0307c, .end = 0x00a0307c },
2009 { .start = 0x00a03080, .end = 0x00a03084 },
2010 { .start = 0x00a0308c, .end = 0x00a03090 },
2011 { .start = 0x00a03098, .end = 0x00a03098 },
2012 { .start = 0x00a030a0, .end = 0x00a030a0 },
2013 { .start = 0x00a030a8, .end = 0x00a030b4 },
2014 { .start = 0x00a030bc, .end = 0x00a030bc },
2015 { .start = 0x00a030c0, .end = 0x00a0312c },
2016 { .start = 0x00a03c00, .end = 0x00a03c5c },
2017 { .start = 0x00a04400, .end = 0x00a04454 },
2018 { .start = 0x00a04460, .end = 0x00a04474 },
2019 { .start = 0x00a044c0, .end = 0x00a044ec },
2020 { .start = 0x00a04500, .end = 0x00a04504 },
2021 { .start = 0x00a04510, .end = 0x00a04538 },
2022 { .start = 0x00a04540, .end = 0x00a04548 },
2023 { .start = 0x00a04560, .end = 0x00a0457c },
2024 { .start = 0x00a04590, .end = 0x00a04598 },
2025 { .start = 0x00a045c0, .end = 0x00a045f4 },
2026 };
2027
2028 static u32 iwl_trans_pcie_dump_prph(struct iwl_trans *trans,
2029 struct iwl_fw_error_dump_data **data)
2030 {
2031 struct iwl_fw_error_dump_prph *prph;
2032 unsigned long flags;
2033 u32 prph_len = 0, i;
2034
2035 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2036 return 0;
2037
2038 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2039 /* The range includes both boundaries */
2040 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2041 iwl_prph_dump_addr[i].start + 4;
2042 int reg;
2043 __le32 *val;
2044
2045 prph_len += sizeof(**data) + sizeof(*prph) + num_bytes_in_chunk;
2046
2047 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH);
2048 (*data)->len = cpu_to_le32(sizeof(*prph) +
2049 num_bytes_in_chunk);
2050 prph = (void *)(*data)->data;
2051 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start);
2052 val = (void *)prph->data;
2053
2054 for (reg = iwl_prph_dump_addr[i].start;
2055 reg <= iwl_prph_dump_addr[i].end;
2056 reg += 4)
2057 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2058 reg));
2059 *data = iwl_fw_error_next_data(*data);
2060 }
2061
2062 iwl_trans_release_nic_access(trans, &flags);
2063
2064 return prph_len;
2065 }
2066
2067 #define IWL_CSR_TO_DUMP (0x250)
2068
2069 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2070 struct iwl_fw_error_dump_data **data)
2071 {
2072 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2073 __le32 *val;
2074 int i;
2075
2076 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2077 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2078 val = (void *)(*data)->data;
2079
2080 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2081 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2082
2083 *data = iwl_fw_error_next_data(*data);
2084
2085 return csr_len;
2086 }
2087
2088 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2089 struct iwl_fw_error_dump_data **data)
2090 {
2091 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2092 unsigned long flags;
2093 __le32 *val;
2094 int i;
2095
2096 if (!iwl_trans_grab_nic_access(trans, false, &flags))
2097 return 0;
2098
2099 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2100 (*data)->len = cpu_to_le32(fh_regs_len);
2101 val = (void *)(*data)->data;
2102
2103 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2104 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2105
2106 iwl_trans_release_nic_access(trans, &flags);
2107
2108 *data = iwl_fw_error_next_data(*data);
2109
2110 return sizeof(**data) + fh_regs_len;
2111 }
2112
2113 static
2114 struct iwl_trans_dump_data *iwl_trans_pcie_dump_data(struct iwl_trans *trans)
2115 {
2116 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2117 struct iwl_fw_error_dump_data *data;
2118 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2119 struct iwl_fw_error_dump_txcmd *txcmd;
2120 struct iwl_trans_dump_data *dump_data;
2121 u32 len;
2122 u32 monitor_len;
2123 int i, ptr;
2124
2125 /* transport dump header */
2126 len = sizeof(*dump_data);
2127
2128 /* host commands */
2129 len += sizeof(*data) +
2130 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2131
2132 /* CSR registers */
2133 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2134
2135 /* PRPH registers */
2136 for (i = 0; i < ARRAY_SIZE(iwl_prph_dump_addr); i++) {
2137 /* The range includes both boundaries */
2138 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end -
2139 iwl_prph_dump_addr[i].start + 4;
2140
2141 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_prph) +
2142 num_bytes_in_chunk;
2143 }
2144
2145 /* FH registers */
2146 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2147
2148 /* FW monitor */
2149 if (trans_pcie->fw_mon_page) {
2150 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2151 trans_pcie->fw_mon_size;
2152 monitor_len = trans_pcie->fw_mon_size;
2153 } else if (trans->dbg_dest_tlv) {
2154 u32 base, end;
2155
2156 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2157 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2158
2159 base = iwl_read_prph(trans, base) <<
2160 trans->dbg_dest_tlv->base_shift;
2161 end = iwl_read_prph(trans, end) <<
2162 trans->dbg_dest_tlv->end_shift;
2163
2164 /* Make "end" point to the actual end */
2165 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2166 end += (1 << trans->dbg_dest_tlv->end_shift);
2167 monitor_len = end - base;
2168 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2169 monitor_len;
2170 } else {
2171 monitor_len = 0;
2172 }
2173
2174 dump_data = vzalloc(len);
2175 if (!dump_data)
2176 return NULL;
2177
2178 len = 0;
2179 data = (void *)dump_data->data;
2180 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2181 txcmd = (void *)data->data;
2182 spin_lock_bh(&cmdq->lock);
2183 ptr = cmdq->q.write_ptr;
2184 for (i = 0; i < cmdq->q.n_window; i++) {
2185 u8 idx = get_cmd_index(&cmdq->q, ptr);
2186 u32 caplen, cmdlen;
2187
2188 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]);
2189 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2190
2191 if (cmdlen) {
2192 len += sizeof(*txcmd) + caplen;
2193 txcmd->cmdlen = cpu_to_le32(cmdlen);
2194 txcmd->caplen = cpu_to_le32(caplen);
2195 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2196 txcmd = (void *)((u8 *)txcmd->data + caplen);
2197 }
2198
2199 ptr = iwl_queue_dec_wrap(ptr);
2200 }
2201 spin_unlock_bh(&cmdq->lock);
2202
2203 data->len = cpu_to_le32(len);
2204 len += sizeof(*data);
2205 data = iwl_fw_error_next_data(data);
2206
2207 len += iwl_trans_pcie_dump_prph(trans, &data);
2208 len += iwl_trans_pcie_dump_csr(trans, &data);
2209 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2210 /* data is already pointing to the next section */
2211
2212 if ((trans_pcie->fw_mon_page &&
2213 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2214 trans->dbg_dest_tlv) {
2215 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2216 u32 base, write_ptr, wrap_cnt;
2217
2218 /* If there was a dest TLV - use the values from there */
2219 if (trans->dbg_dest_tlv) {
2220 write_ptr =
2221 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2222 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2223 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2224 } else {
2225 base = MON_BUFF_BASE_ADDR;
2226 write_ptr = MON_BUFF_WRPTR;
2227 wrap_cnt = MON_BUFF_CYCLE_CNT;
2228 }
2229
2230 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2231 fw_mon_data = (void *)data->data;
2232 fw_mon_data->fw_mon_wr_ptr =
2233 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2234 fw_mon_data->fw_mon_cycle_cnt =
2235 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2236 fw_mon_data->fw_mon_base_ptr =
2237 cpu_to_le32(iwl_read_prph(trans, base));
2238
2239 len += sizeof(*data) + sizeof(*fw_mon_data);
2240 if (trans_pcie->fw_mon_page) {
2241 data->len = cpu_to_le32(trans_pcie->fw_mon_size +
2242 sizeof(*fw_mon_data));
2243
2244 /*
2245 * The firmware is now asserted, it won't write anything
2246 * to the buffer. CPU can take ownership to fetch the
2247 * data. The buffer will be handed back to the device
2248 * before the firmware will be restarted.
2249 */
2250 dma_sync_single_for_cpu(trans->dev,
2251 trans_pcie->fw_mon_phys,
2252 trans_pcie->fw_mon_size,
2253 DMA_FROM_DEVICE);
2254 memcpy(fw_mon_data->data,
2255 page_address(trans_pcie->fw_mon_page),
2256 trans_pcie->fw_mon_size);
2257
2258 len += trans_pcie->fw_mon_size;
2259 } else {
2260 /* If we are here then the buffer is internal */
2261
2262 /*
2263 * Update pointers to reflect actual values after
2264 * shifting
2265 */
2266 base = iwl_read_prph(trans, base) <<
2267 trans->dbg_dest_tlv->base_shift;
2268 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2269 monitor_len / sizeof(u32));
2270 data->len = cpu_to_le32(sizeof(*fw_mon_data) +
2271 monitor_len);
2272 len += monitor_len;
2273 }
2274 }
2275
2276 dump_data->len = len;
2277
2278 return dump_data;
2279 }
2280
2281 static const struct iwl_trans_ops trans_ops_pcie = {
2282 .start_hw = iwl_trans_pcie_start_hw,
2283 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2284 .fw_alive = iwl_trans_pcie_fw_alive,
2285 .start_fw = iwl_trans_pcie_start_fw,
2286 .stop_device = iwl_trans_pcie_stop_device,
2287
2288 .d3_suspend = iwl_trans_pcie_d3_suspend,
2289 .d3_resume = iwl_trans_pcie_d3_resume,
2290
2291 .send_cmd = iwl_trans_pcie_send_hcmd,
2292
2293 .tx = iwl_trans_pcie_tx,
2294 .reclaim = iwl_trans_pcie_reclaim,
2295
2296 .txq_disable = iwl_trans_pcie_txq_disable,
2297 .txq_enable = iwl_trans_pcie_txq_enable,
2298
2299 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2300
2301 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2302
2303 .write8 = iwl_trans_pcie_write8,
2304 .write32 = iwl_trans_pcie_write32,
2305 .read32 = iwl_trans_pcie_read32,
2306 .read_prph = iwl_trans_pcie_read_prph,
2307 .write_prph = iwl_trans_pcie_write_prph,
2308 .read_mem = iwl_trans_pcie_read_mem,
2309 .write_mem = iwl_trans_pcie_write_mem,
2310 .configure = iwl_trans_pcie_configure,
2311 .set_pmi = iwl_trans_pcie_set_pmi,
2312 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2313 .release_nic_access = iwl_trans_pcie_release_nic_access,
2314 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2315
2316 .ref = iwl_trans_pcie_ref,
2317 .unref = iwl_trans_pcie_unref,
2318
2319 .dump_data = iwl_trans_pcie_dump_data,
2320 };
2321
2322 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2323 const struct pci_device_id *ent,
2324 const struct iwl_cfg *cfg)
2325 {
2326 struct iwl_trans_pcie *trans_pcie;
2327 struct iwl_trans *trans;
2328 u16 pci_cmd;
2329 int err;
2330
2331 trans = kzalloc(sizeof(struct iwl_trans) +
2332 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2333 if (!trans) {
2334 err = -ENOMEM;
2335 goto out;
2336 }
2337
2338 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2339
2340 trans->ops = &trans_ops_pcie;
2341 trans->cfg = cfg;
2342 trans_lockdep_init(trans);
2343 trans_pcie->trans = trans;
2344 spin_lock_init(&trans_pcie->irq_lock);
2345 spin_lock_init(&trans_pcie->reg_lock);
2346 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2347
2348 err = pci_enable_device(pdev);
2349 if (err)
2350 goto out_no_pci;
2351
2352 if (!cfg->base_params->pcie_l1_allowed) {
2353 /*
2354 * W/A - seems to solve weird behavior. We need to remove this
2355 * if we don't want to stay in L1 all the time. This wastes a
2356 * lot of power.
2357 */
2358 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2359 PCIE_LINK_STATE_L1 |
2360 PCIE_LINK_STATE_CLKPM);
2361 }
2362
2363 pci_set_master(pdev);
2364
2365 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2366 if (!err)
2367 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2368 if (err) {
2369 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2370 if (!err)
2371 err = pci_set_consistent_dma_mask(pdev,
2372 DMA_BIT_MASK(32));
2373 /* both attempts failed: */
2374 if (err) {
2375 dev_err(&pdev->dev, "No suitable DMA available\n");
2376 goto out_pci_disable_device;
2377 }
2378 }
2379
2380 err = pci_request_regions(pdev, DRV_NAME);
2381 if (err) {
2382 dev_err(&pdev->dev, "pci_request_regions failed\n");
2383 goto out_pci_disable_device;
2384 }
2385
2386 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2387 if (!trans_pcie->hw_base) {
2388 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
2389 err = -ENODEV;
2390 goto out_pci_release_regions;
2391 }
2392
2393 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2394 * PCI Tx retries from interfering with C3 CPU state */
2395 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2396
2397 trans->dev = &pdev->dev;
2398 trans_pcie->pci_dev = pdev;
2399 iwl_disable_interrupts(trans);
2400
2401 err = pci_enable_msi(pdev);
2402 if (err) {
2403 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
2404 /* enable rfkill interrupt: hw bug w/a */
2405 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2406 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2407 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2408 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2409 }
2410 }
2411
2412 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2413 /*
2414 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2415 * changed, and now the revision step also includes bit 0-1 (no more
2416 * "dash" value). To keep hw_rev backwards compatible - we'll store it
2417 * in the old format.
2418 */
2419 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
2420 trans->hw_rev = (trans->hw_rev & 0xfff0) |
2421 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
2422
2423 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2424 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2425 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2426
2427 /* Initialize the wait queue for commands */
2428 init_waitqueue_head(&trans_pcie->wait_command_queue);
2429
2430 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2431 "iwl_cmd_pool:%s", dev_name(trans->dev));
2432
2433 trans->dev_cmd_headroom = 0;
2434 trans->dev_cmd_pool =
2435 kmem_cache_create(trans->dev_cmd_pool_name,
2436 sizeof(struct iwl_device_cmd)
2437 + trans->dev_cmd_headroom,
2438 sizeof(void *),
2439 SLAB_HWCACHE_ALIGN,
2440 NULL);
2441
2442 if (!trans->dev_cmd_pool) {
2443 err = -ENOMEM;
2444 goto out_pci_disable_msi;
2445 }
2446
2447 if (iwl_pcie_alloc_ict(trans))
2448 goto out_free_cmd_pool;
2449
2450 err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
2451 iwl_pcie_irq_handler,
2452 IRQF_SHARED, DRV_NAME, trans);
2453 if (err) {
2454 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
2455 goto out_free_ict;
2456 }
2457
2458 trans_pcie->inta_mask = CSR_INI_SET_MASK;
2459 trans->d0i3_mode = IWL_D0I3_MODE_ON_SUSPEND;
2460
2461 return trans;
2462
2463 out_free_ict:
2464 iwl_pcie_free_ict(trans);
2465 out_free_cmd_pool:
2466 kmem_cache_destroy(trans->dev_cmd_pool);
2467 out_pci_disable_msi:
2468 pci_disable_msi(pdev);
2469 out_pci_release_regions:
2470 pci_release_regions(pdev);
2471 out_pci_disable_device:
2472 pci_disable_device(pdev);
2473 out_no_pci:
2474 kfree(trans);
2475 out:
2476 return ERR_PTR(err);
2477 }
Linux kernel - Deliverables
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