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Merge remote-tracking branch 'mfd/for-mfd-next'
[deliverable/linux.git] / drivers / net / wireless / realtek / rtlwifi / rtl8723ae / hw.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "../wifi.h"
27 #include "../efuse.h"
28 #include "../base.h"
29 #include "../regd.h"
30 #include "../cam.h"
31 #include "../ps.h"
32 #include "../pci.h"
33 #include "reg.h"
34 #include "def.h"
35 #include "phy.h"
36 #include "../rtl8723com/phy_common.h"
37 #include "dm.h"
38 #include "../rtl8723com/dm_common.h"
39 #include "fw.h"
40 #include "../rtl8723com/fw_common.h"
41 #include "led.h"
42 #include "hw.h"
43 #include "../pwrseqcmd.h"
44 #include "pwrseq.h"
45 #include "btc.h"
46
47 #define LLT_CONFIG 5
48
49 static void _rtl8723e_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
50 u8 set_bits, u8 clear_bits)
51 {
52 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
53 struct rtl_priv *rtlpriv = rtl_priv(hw);
54
55 rtlpci->reg_bcn_ctrl_val |= set_bits;
56 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
57
58 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
59 }
60
61 static void _rtl8723e_stop_tx_beacon(struct ieee80211_hw *hw)
62 {
63 struct rtl_priv *rtlpriv = rtl_priv(hw);
64 u8 tmp1byte;
65
66 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
67 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
68 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
69 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
70 tmp1byte &= ~(BIT(0));
71 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
72 }
73
74 static void _rtl8723e_resume_tx_beacon(struct ieee80211_hw *hw)
75 {
76 struct rtl_priv *rtlpriv = rtl_priv(hw);
77 u8 tmp1byte;
78
79 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
80 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
81 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
82 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
83 tmp1byte |= BIT(1);
84 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
85 }
86
87 static void _rtl8723e_enable_bcn_sub_func(struct ieee80211_hw *hw)
88 {
89 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(1));
90 }
91
92 static void _rtl8723e_disable_bcn_sub_func(struct ieee80211_hw *hw)
93 {
94 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(1), 0);
95 }
96
97 void rtl8723e_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
98 {
99 struct rtl_priv *rtlpriv = rtl_priv(hw);
100 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
101 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
102
103 switch (variable) {
104 case HW_VAR_RCR:
105 *((u32 *)(val)) = rtlpci->receive_config;
106 break;
107 case HW_VAR_RF_STATE:
108 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
109 break;
110 case HW_VAR_FWLPS_RF_ON:{
111 enum rf_pwrstate rfstate;
112 u32 val_rcr;
113
114 rtlpriv->cfg->ops->get_hw_reg(hw,
115 HW_VAR_RF_STATE,
116 (u8 *)(&rfstate));
117 if (rfstate == ERFOFF) {
118 *((bool *)(val)) = true;
119 } else {
120 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
121 val_rcr &= 0x00070000;
122 if (val_rcr)
123 *((bool *)(val)) = false;
124 else
125 *((bool *)(val)) = true;
126 }
127 break;
128 }
129 case HW_VAR_FW_PSMODE_STATUS:
130 *((bool *)(val)) = ppsc->fw_current_inpsmode;
131 break;
132 case HW_VAR_CORRECT_TSF:{
133 u64 tsf;
134 u32 *ptsf_low = (u32 *)&tsf;
135 u32 *ptsf_high = ((u32 *)&tsf) + 1;
136
137 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
138 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
139
140 *((u64 *)(val)) = tsf;
141
142 break;
143 }
144 default:
145 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
146 "switch case not process\n");
147 break;
148 }
149 }
150
151 void rtl8723e_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
152 {
153 struct rtl_priv *rtlpriv = rtl_priv(hw);
154 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
155 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
156 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
157 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
158 u8 idx;
159
160 switch (variable) {
161 case HW_VAR_ETHER_ADDR:{
162 for (idx = 0; idx < ETH_ALEN; idx++) {
163 rtl_write_byte(rtlpriv, (REG_MACID + idx),
164 val[idx]);
165 }
166 break;
167 }
168 case HW_VAR_BASIC_RATE:{
169 u16 b_rate_cfg = ((u16 *)val)[0];
170 u8 rate_index = 0;
171
172 b_rate_cfg = b_rate_cfg & 0x15f;
173 b_rate_cfg |= 0x01;
174 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
175 rtl_write_byte(rtlpriv, REG_RRSR + 1,
176 (b_rate_cfg >> 8) & 0xff);
177 while (b_rate_cfg > 0x1) {
178 b_rate_cfg = (b_rate_cfg >> 1);
179 rate_index++;
180 }
181 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
182 rate_index);
183 break;
184 }
185 case HW_VAR_BSSID:{
186 for (idx = 0; idx < ETH_ALEN; idx++) {
187 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
188 val[idx]);
189 }
190 break;
191 }
192 case HW_VAR_SIFS:{
193 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
194 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
195
196 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
197 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
198
199 if (!mac->ht_enable)
200 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
201 0x0e0e);
202 else
203 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
204 *((u16 *)val));
205 break;
206 }
207 case HW_VAR_SLOT_TIME:{
208 u8 e_aci;
209
210 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
211 "HW_VAR_SLOT_TIME %x\n", val[0]);
212
213 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
214
215 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
216 rtlpriv->cfg->ops->set_hw_reg(hw,
217 HW_VAR_AC_PARAM,
218 (u8 *)(&e_aci));
219 }
220 break;
221 }
222 case HW_VAR_ACK_PREAMBLE:{
223 u8 reg_tmp;
224 u8 short_preamble = (bool)(*(u8 *)val);
225
226 reg_tmp = (mac->cur_40_prime_sc) << 5;
227 if (short_preamble)
228 reg_tmp |= 0x80;
229
230 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
231 break;
232 }
233 case HW_VAR_AMPDU_MIN_SPACE:{
234 u8 min_spacing_to_set;
235 u8 sec_min_space;
236
237 min_spacing_to_set = *((u8 *)val);
238 if (min_spacing_to_set <= 7) {
239 sec_min_space = 0;
240
241 if (min_spacing_to_set < sec_min_space)
242 min_spacing_to_set = sec_min_space;
243
244 mac->min_space_cfg = ((mac->min_space_cfg &
245 0xf8) |
246 min_spacing_to_set);
247
248 *val = min_spacing_to_set;
249
250 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
251 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
252 mac->min_space_cfg);
253
254 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
255 mac->min_space_cfg);
256 }
257 break;
258 }
259 case HW_VAR_SHORTGI_DENSITY:{
260 u8 density_to_set;
261
262 density_to_set = *((u8 *)val);
263 mac->min_space_cfg |= (density_to_set << 3);
264
265 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
266 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
267 mac->min_space_cfg);
268
269 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
270 mac->min_space_cfg);
271
272 break;
273 }
274 case HW_VAR_AMPDU_FACTOR:{
275 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
276 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
277 u8 factor_toset;
278 u8 *p_regtoset = NULL;
279 u8 index = 0;
280
281 if ((rtlpriv->btcoexist.bt_coexistence) &&
282 (rtlpriv->btcoexist.bt_coexist_type ==
283 BT_CSR_BC4))
284 p_regtoset = regtoset_bt;
285 else
286 p_regtoset = regtoset_normal;
287
288 factor_toset = *((u8 *)val);
289 if (factor_toset <= 3) {
290 factor_toset = (1 << (factor_toset + 2));
291 if (factor_toset > 0xf)
292 factor_toset = 0xf;
293
294 for (index = 0; index < 4; index++) {
295 if ((p_regtoset[index] & 0xf0) >
296 (factor_toset << 4))
297 p_regtoset[index] =
298 (p_regtoset[index] & 0x0f) |
299 (factor_toset << 4);
300
301 if ((p_regtoset[index] & 0x0f) >
302 factor_toset)
303 p_regtoset[index] =
304 (p_regtoset[index] & 0xf0) |
305 (factor_toset);
306
307 rtl_write_byte(rtlpriv,
308 (REG_AGGLEN_LMT + index),
309 p_regtoset[index]);
310 }
311
312 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
313 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
314 factor_toset);
315 }
316 break;
317 }
318 case HW_VAR_AC_PARAM:{
319 u8 e_aci = *((u8 *)val);
320
321 rtl8723_dm_init_edca_turbo(hw);
322
323 if (rtlpci->acm_method != EACMWAY2_SW)
324 rtlpriv->cfg->ops->set_hw_reg(hw,
325 HW_VAR_ACM_CTRL,
326 (u8 *)(&e_aci));
327 break;
328 }
329 case HW_VAR_ACM_CTRL:{
330 u8 e_aci = *((u8 *)val);
331 union aci_aifsn *p_aci_aifsn =
332 (union aci_aifsn *)(&mac->ac[0].aifs);
333 u8 acm = p_aci_aifsn->f.acm;
334 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
335
336 acm_ctrl =
337 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
338
339 if (acm) {
340 switch (e_aci) {
341 case AC0_BE:
342 acm_ctrl |= ACMHW_BEQEN;
343 break;
344 case AC2_VI:
345 acm_ctrl |= ACMHW_VIQEN;
346 break;
347 case AC3_VO:
348 acm_ctrl |= ACMHW_VOQEN;
349 break;
350 default:
351 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
352 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
353 acm);
354 break;
355 }
356 } else {
357 switch (e_aci) {
358 case AC0_BE:
359 acm_ctrl &= (~ACMHW_BEQEN);
360 break;
361 case AC2_VI:
362 acm_ctrl &= (~ACMHW_VIQEN);
363 break;
364 case AC3_VO:
365 acm_ctrl &= (~ACMHW_VOQEN);
366 break;
367 default:
368 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
369 "switch case not process\n");
370 break;
371 }
372 }
373
374 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
375 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
376 acm_ctrl);
377 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
378 break;
379 }
380 case HW_VAR_RCR:{
381 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
382 rtlpci->receive_config = ((u32 *)(val))[0];
383 break;
384 }
385 case HW_VAR_RETRY_LIMIT:{
386 u8 retry_limit = ((u8 *)(val))[0];
387
388 rtl_write_word(rtlpriv, REG_RL,
389 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
390 retry_limit << RETRY_LIMIT_LONG_SHIFT);
391 break;
392 }
393 case HW_VAR_DUAL_TSF_RST:
394 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
395 break;
396 case HW_VAR_EFUSE_BYTES:
397 rtlefuse->efuse_usedbytes = *((u16 *)val);
398 break;
399 case HW_VAR_EFUSE_USAGE:
400 rtlefuse->efuse_usedpercentage = *((u8 *)val);
401 break;
402 case HW_VAR_IO_CMD:
403 rtl8723e_phy_set_io_cmd(hw, (*(enum io_type *)val));
404 break;
405 case HW_VAR_WPA_CONFIG:
406 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
407 break;
408 case HW_VAR_SET_RPWM:{
409 u8 rpwm_val;
410
411 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
412 udelay(1);
413
414 if (rpwm_val & BIT(7)) {
415 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
416 (*(u8 *)val));
417 } else {
418 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
419 ((*(u8 *)val) | BIT(7)));
420 }
421
422 break;
423 }
424 case HW_VAR_H2C_FW_PWRMODE:{
425 u8 psmode = (*(u8 *)val);
426
427 if (psmode != FW_PS_ACTIVE_MODE)
428 rtl8723e_dm_rf_saving(hw, true);
429
430 rtl8723e_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
431 break;
432 }
433 case HW_VAR_FW_PSMODE_STATUS:
434 ppsc->fw_current_inpsmode = *((bool *)val);
435 break;
436 case HW_VAR_H2C_FW_JOINBSSRPT:{
437 u8 mstatus = (*(u8 *)val);
438 u8 tmp_regcr, tmp_reg422;
439 bool b_recover = false;
440
441 if (mstatus == RT_MEDIA_CONNECT) {
442 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
443 NULL);
444
445 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
446 rtl_write_byte(rtlpriv, REG_CR + 1,
447 (tmp_regcr | BIT(0)));
448
449 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3));
450 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0);
451
452 tmp_reg422 =
453 rtl_read_byte(rtlpriv,
454 REG_FWHW_TXQ_CTRL + 2);
455 if (tmp_reg422 & BIT(6))
456 b_recover = true;
457 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
458 tmp_reg422 & (~BIT(6)));
459
460 rtl8723e_set_fw_rsvdpagepkt(hw, 0);
461
462 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0);
463 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4));
464
465 if (b_recover) {
466 rtl_write_byte(rtlpriv,
467 REG_FWHW_TXQ_CTRL + 2,
468 tmp_reg422);
469 }
470
471 rtl_write_byte(rtlpriv, REG_CR + 1,
472 (tmp_regcr & ~(BIT(0))));
473 }
474 rtl8723e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
475
476 break;
477 }
478 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:{
479 rtl8723e_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
480 break;
481 }
482 case HW_VAR_AID:{
483 u16 u2btmp;
484
485 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
486 u2btmp &= 0xC000;
487 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
488 (u2btmp | mac->assoc_id));
489
490 break;
491 }
492 case HW_VAR_CORRECT_TSF:{
493 u8 btype_ibss = ((u8 *)(val))[0];
494
495 if (btype_ibss)
496 _rtl8723e_stop_tx_beacon(hw);
497
498 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3));
499
500 rtl_write_dword(rtlpriv, REG_TSFTR,
501 (u32)(mac->tsf & 0xffffffff));
502 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
503 (u32)((mac->tsf >> 32) & 0xffffffff));
504
505 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0);
506
507 if (btype_ibss)
508 _rtl8723e_resume_tx_beacon(hw);
509
510 break;
511 }
512 case HW_VAR_FW_LPS_ACTION:{
513 bool b_enter_fwlps = *((bool *)val);
514 u8 rpwm_val, fw_pwrmode;
515 bool fw_current_inps;
516
517 if (b_enter_fwlps) {
518 rpwm_val = 0x02; /* RF off */
519 fw_current_inps = true;
520 rtlpriv->cfg->ops->set_hw_reg(hw,
521 HW_VAR_FW_PSMODE_STATUS,
522 (u8 *)(&fw_current_inps));
523 rtlpriv->cfg->ops->set_hw_reg(hw,
524 HW_VAR_H2C_FW_PWRMODE,
525 (u8 *)(&ppsc->fwctrl_psmode));
526
527 rtlpriv->cfg->ops->set_hw_reg(hw,
528 HW_VAR_SET_RPWM,
529 (u8 *)(&rpwm_val));
530 } else {
531 rpwm_val = 0x0C; /* RF on */
532 fw_pwrmode = FW_PS_ACTIVE_MODE;
533 fw_current_inps = false;
534 rtlpriv->cfg->ops->set_hw_reg(hw,
535 HW_VAR_SET_RPWM,
536 (u8 *)(&rpwm_val));
537 rtlpriv->cfg->ops->set_hw_reg(hw,
538 HW_VAR_H2C_FW_PWRMODE,
539 (u8 *)(&fw_pwrmode));
540
541 rtlpriv->cfg->ops->set_hw_reg(hw,
542 HW_VAR_FW_PSMODE_STATUS,
543 (u8 *)(&fw_current_inps));
544 }
545 break;
546 }
547 default:
548 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
549 "switch case not process\n");
550 break;
551 }
552 }
553
554 static bool _rtl8723e_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
555 {
556 struct rtl_priv *rtlpriv = rtl_priv(hw);
557 bool status = true;
558 long count = 0;
559 u32 value = _LLT_INIT_ADDR(address) |
560 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
561
562 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
563
564 do {
565 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
566 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
567 break;
568
569 if (count > POLLING_LLT_THRESHOLD) {
570 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
571 "Failed to polling write LLT done at address %d!\n",
572 address);
573 status = false;
574 break;
575 }
576 } while (++count);
577
578 return status;
579 }
580
581 static bool _rtl8723e_llt_table_init(struct ieee80211_hw *hw)
582 {
583 struct rtl_priv *rtlpriv = rtl_priv(hw);
584 unsigned short i;
585 u8 txpktbuf_bndy;
586 u8 maxpage;
587 bool status;
588 u8 ubyte;
589
590 #if LLT_CONFIG == 1
591 maxpage = 255;
592 txpktbuf_bndy = 252;
593 #elif LLT_CONFIG == 2
594 maxpage = 127;
595 txpktbuf_bndy = 124;
596 #elif LLT_CONFIG == 3
597 maxpage = 255;
598 txpktbuf_bndy = 174;
599 #elif LLT_CONFIG == 4
600 maxpage = 255;
601 txpktbuf_bndy = 246;
602 #elif LLT_CONFIG == 5
603 maxpage = 255;
604 txpktbuf_bndy = 246;
605 #endif
606
607 rtl_write_byte(rtlpriv, REG_CR, 0x8B);
608
609 #if LLT_CONFIG == 1
610 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
611 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
612 #elif LLT_CONFIG == 2
613 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
614 #elif LLT_CONFIG == 3
615 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
616 #elif LLT_CONFIG == 4
617 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
618 #elif LLT_CONFIG == 5
619 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
620
621 rtl_write_dword(rtlpriv, REG_RQPN, 0x80ac1c29);
622 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x03);
623 #endif
624
625 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
626 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
627
628 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
629 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
630
631 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
632 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
633 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
634
635 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
636 status = _rtl8723e_llt_write(hw, i, i + 1);
637 if (true != status)
638 return status;
639 }
640
641 status = _rtl8723e_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
642 if (true != status)
643 return status;
644
645 for (i = txpktbuf_bndy; i < maxpage; i++) {
646 status = _rtl8723e_llt_write(hw, i, (i + 1));
647 if (true != status)
648 return status;
649 }
650
651 status = _rtl8723e_llt_write(hw, maxpage, txpktbuf_bndy);
652 if (true != status)
653 return status;
654
655 rtl_write_byte(rtlpriv, REG_CR, 0xff);
656 ubyte = rtl_read_byte(rtlpriv, REG_RQPN + 3);
657 rtl_write_byte(rtlpriv, REG_RQPN + 3, ubyte | BIT(7));
658
659 return true;
660 }
661
662 static void _rtl8723e_gen_refresh_led_state(struct ieee80211_hw *hw)
663 {
664 struct rtl_priv *rtlpriv = rtl_priv(hw);
665 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
666 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
667 struct rtl_led *pled0 = &pcipriv->ledctl.sw_led0;
668
669 if (rtlpriv->rtlhal.up_first_time)
670 return;
671
672 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
673 rtl8723e_sw_led_on(hw, pled0);
674 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
675 rtl8723e_sw_led_on(hw, pled0);
676 else
677 rtl8723e_sw_led_off(hw, pled0);
678 }
679
680 static bool _rtl8712e_init_mac(struct ieee80211_hw *hw)
681 {
682 struct rtl_priv *rtlpriv = rtl_priv(hw);
683 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
684
685 unsigned char bytetmp;
686 unsigned short wordtmp;
687 u16 retry = 0;
688 u16 tmpu2b;
689 bool mac_func_enable;
690
691 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
692 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
693 if (bytetmp == 0xFF)
694 mac_func_enable = true;
695 else
696 mac_func_enable = false;
697
698 /* HW Power on sequence */
699 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
700 PWR_INTF_PCI_MSK, Rtl8723_NIC_ENABLE_FLOW))
701 return false;
702
703 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
704 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp | BIT(4));
705
706 /* eMAC time out function enable, 0x369[7]=1 */
707 bytetmp = rtl_read_byte(rtlpriv, 0x369);
708 rtl_write_byte(rtlpriv, 0x369, bytetmp | BIT(7));
709
710 /* ePHY reg 0x1e bit[4]=1 using MDIO interface,
711 * we should do this before Enabling ASPM backdoor.
712 */
713 do {
714 rtl_write_word(rtlpriv, 0x358, 0x5e);
715 udelay(100);
716 rtl_write_word(rtlpriv, 0x356, 0xc280);
717 rtl_write_word(rtlpriv, 0x354, 0xc290);
718 rtl_write_word(rtlpriv, 0x358, 0x3e);
719 udelay(100);
720 rtl_write_word(rtlpriv, 0x358, 0x5e);
721 udelay(100);
722 tmpu2b = rtl_read_word(rtlpriv, 0x356);
723 retry++;
724 } while (tmpu2b != 0xc290 && retry < 100);
725
726 if (retry >= 100) {
727 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
728 "InitMAC(): ePHY configure fail!!!\n");
729 return false;
730 }
731
732 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
733 rtl_write_word(rtlpriv, REG_CR + 1, 0x06);
734
735 if (!mac_func_enable) {
736 if (!_rtl8723e_llt_table_init(hw))
737 return false;
738 }
739
740 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
741 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
742
743 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
744
745 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
746 wordtmp &= 0xf;
747 wordtmp |= 0xF771;
748 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
749
750 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
751 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
752 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
753 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
754
755 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
756
757 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
758 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
759 DMA_BIT_MASK(32));
760 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
761 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
762 DMA_BIT_MASK(32));
763 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
764 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
765 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
766 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
767 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
768 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
769 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
770 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
771 rtl_write_dword(rtlpriv, REG_HQ_DESA,
772 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
773 DMA_BIT_MASK(32));
774 rtl_write_dword(rtlpriv, REG_RX_DESA,
775 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
776 DMA_BIT_MASK(32));
777
778 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x74);
779
780 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
781
782 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
783 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
784 do {
785 retry++;
786 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
787 } while ((retry < 200) && (bytetmp & BIT(7)));
788
789 _rtl8723e_gen_refresh_led_state(hw);
790
791 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
792
793 return true;
794 }
795
796 static void _rtl8723e_hw_configure(struct ieee80211_hw *hw)
797 {
798 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
799 struct rtl_priv *rtlpriv = rtl_priv(hw);
800 u8 reg_bw_opmode;
801 u32 reg_ratr, reg_prsr;
802
803 reg_bw_opmode = BW_OPMODE_20MHZ;
804 reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
805 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
806 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
807
808 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
809
810 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
811
812 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
813
814 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
815
816 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
817
818 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
819
820 rtl_write_word(rtlpriv, REG_RL, 0x0707);
821
822 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
823
824 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
825
826 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
827 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
828 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
829 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
830
831 if ((rtlpriv->btcoexist.bt_coexistence) &&
832 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
833 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
834 else
835 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
836
837 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
838
839 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
840
841 rtlpci->reg_bcn_ctrl_val = 0x1f;
842 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
843
844 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
845
846 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
847
848 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
849 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
850
851 if ((rtlpriv->btcoexist.bt_coexistence) &&
852 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) {
853 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
854 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
855 } else {
856 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
857 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
858 }
859
860 if ((rtlpriv->btcoexist.bt_coexistence) &&
861 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
862 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
863 else
864 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
865
866 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
867
868 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
869 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
870
871 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
872
873 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
874
875 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
876 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
877
878 rtl_write_dword(rtlpriv, 0x394, 0x1);
879 }
880
881 static void _rtl8723e_enable_aspm_back_door(struct ieee80211_hw *hw)
882 {
883 struct rtl_priv *rtlpriv = rtl_priv(hw);
884 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
885
886 rtl_write_byte(rtlpriv, 0x34b, 0x93);
887 rtl_write_word(rtlpriv, 0x350, 0x870c);
888 rtl_write_byte(rtlpriv, 0x352, 0x1);
889
890 if (ppsc->support_backdoor)
891 rtl_write_byte(rtlpriv, 0x349, 0x1b);
892 else
893 rtl_write_byte(rtlpriv, 0x349, 0x03);
894
895 rtl_write_word(rtlpriv, 0x350, 0x2718);
896 rtl_write_byte(rtlpriv, 0x352, 0x1);
897 }
898
899 void rtl8723e_enable_hw_security_config(struct ieee80211_hw *hw)
900 {
901 struct rtl_priv *rtlpriv = rtl_priv(hw);
902 u8 sec_reg_value;
903
904 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
905 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
906 rtlpriv->sec.pairwise_enc_algorithm,
907 rtlpriv->sec.group_enc_algorithm);
908
909 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
910 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
911 "not open hw encryption\n");
912 return;
913 }
914
915 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
916
917 if (rtlpriv->sec.use_defaultkey) {
918 sec_reg_value |= SCR_TXUSEDK;
919 sec_reg_value |= SCR_RXUSEDK;
920 }
921
922 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
923
924 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
925
926 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
927 "The SECR-value %x\n", sec_reg_value);
928
929 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
930
931 }
932
933 int rtl8723e_hw_init(struct ieee80211_hw *hw)
934 {
935 struct rtl_priv *rtlpriv = rtl_priv(hw);
936 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
937 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
938 struct rtl_phy *rtlphy = &(rtlpriv->phy);
939 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
940 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
941 bool rtstatus = true;
942 int err;
943 u8 tmp_u1b;
944 unsigned long flags;
945
946 rtlpriv->rtlhal.being_init_adapter = true;
947 /* As this function can take a very long time (up to 350 ms)
948 * and can be called with irqs disabled, reenable the irqs
949 * to let the other devices continue being serviced.
950 *
951 * It is safe doing so since our own interrupts will only be enabled
952 * in a subsequent step.
953 */
954 local_save_flags(flags);
955 local_irq_enable();
956 rtlhal->fw_ready = false;
957
958 rtlpriv->intf_ops->disable_aspm(hw);
959 rtstatus = _rtl8712e_init_mac(hw);
960 if (rtstatus != true) {
961 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
962 err = 1;
963 goto exit;
964 }
965
966 err = rtl8723_download_fw(hw, false, FW_8723A_POLLING_TIMEOUT_COUNT);
967 if (err) {
968 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
969 "Failed to download FW. Init HW without FW now..\n");
970 err = 1;
971 goto exit;
972 }
973 rtlhal->fw_ready = true;
974
975 rtlhal->last_hmeboxnum = 0;
976 rtl8723e_phy_mac_config(hw);
977 /* because last function modify RCR, so we update
978 * rcr var here, or TP will unstable for receive_config
979 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
980 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
981 */
982 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
983 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
984 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
985
986 rtl8723e_phy_bb_config(hw);
987 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
988 rtl8723e_phy_rf_config(hw);
989 if (IS_VENDOR_UMC_A_CUT(rtlhal->version)) {
990 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
991 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
992 } else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
993 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
994 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
995 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
996 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
997 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
998 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
999 }
1000 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1001 RF_CHNLBW, RFREG_OFFSET_MASK);
1002 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1003 RF_CHNLBW, RFREG_OFFSET_MASK);
1004 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1005 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1006 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
1007 _rtl8723e_hw_configure(hw);
1008 rtl_cam_reset_all_entry(hw);
1009 rtl8723e_enable_hw_security_config(hw);
1010
1011 ppsc->rfpwr_state = ERFON;
1012
1013 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1014 _rtl8723e_enable_aspm_back_door(hw);
1015 rtlpriv->intf_ops->enable_aspm(hw);
1016
1017 rtl8723e_bt_hw_init(hw);
1018
1019 if (ppsc->rfpwr_state == ERFON) {
1020 rtl8723e_phy_set_rfpath_switch(hw, 1);
1021 if (rtlphy->iqk_initialized) {
1022 rtl8723e_phy_iq_calibrate(hw, true);
1023 } else {
1024 rtl8723e_phy_iq_calibrate(hw, false);
1025 rtlphy->iqk_initialized = true;
1026 }
1027
1028 rtl8723e_dm_check_txpower_tracking(hw);
1029 rtl8723e_phy_lc_calibrate(hw);
1030 }
1031
1032 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1033 if (!(tmp_u1b & BIT(0))) {
1034 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1035 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
1036 }
1037
1038 if (!(tmp_u1b & BIT(4))) {
1039 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1040 tmp_u1b &= 0x0F;
1041 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1042 udelay(10);
1043 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1044 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
1045 }
1046 rtl8723e_dm_init(hw);
1047 exit:
1048 local_irq_restore(flags);
1049 rtlpriv->rtlhal.being_init_adapter = false;
1050 return err;
1051 }
1052
1053 static enum version_8723e _rtl8723e_read_chip_version(struct ieee80211_hw *hw)
1054 {
1055 struct rtl_priv *rtlpriv = rtl_priv(hw);
1056 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1057 enum version_8723e version = 0x0000;
1058 u32 value32;
1059
1060 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1061 if (value32 & TRP_VAUX_EN) {
1062 version = (enum version_8723e)(version |
1063 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1064 /* RTL8723 with BT function. */
1065 version = (enum version_8723e)(version |
1066 ((value32 & BT_FUNC) ? CHIP_8723 : 0));
1067
1068 } else {
1069 /* Normal mass production chip. */
1070 version = (enum version_8723e) NORMAL_CHIP;
1071 version = (enum version_8723e)(version |
1072 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1073 /* RTL8723 with BT function. */
1074 version = (enum version_8723e)(version |
1075 ((value32 & BT_FUNC) ? CHIP_8723 : 0));
1076 if (IS_CHIP_VENDOR_UMC(version))
1077 version = (enum version_8723e)(version |
1078 ((value32 & CHIP_VER_RTL_MASK)));/* IC version (CUT) */
1079 if (IS_8723_SERIES(version)) {
1080 value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS);
1081 /* ROM code version. */
1082 version = (enum version_8723e)(version |
1083 ((value32 & RF_RL_ID)>>20));
1084 }
1085 }
1086
1087 if (IS_8723_SERIES(version)) {
1088 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
1089 rtlphy->polarity_ctl = ((value32 & WL_HWPDN_SL) ?
1090 RT_POLARITY_HIGH_ACT :
1091 RT_POLARITY_LOW_ACT);
1092 }
1093 switch (version) {
1094 case VERSION_TEST_UMC_CHIP_8723:
1095 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1096 "Chip Version ID: VERSION_TEST_UMC_CHIP_8723.\n");
1097 break;
1098 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT:
1099 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1100 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT.\n");
1101 break;
1102 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT:
1103 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1104 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT.\n");
1105 break;
1106 default:
1107 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1108 "Chip Version ID: Unknown. Bug?\n");
1109 break;
1110 }
1111
1112 if (IS_8723_SERIES(version))
1113 rtlphy->rf_type = RF_1T1R;
1114
1115 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1116 (rtlphy->rf_type == RF_2T2R) ? "RF_2T2R" : "RF_1T1R");
1117
1118 return version;
1119 }
1120
1121 static int _rtl8723e_set_media_status(struct ieee80211_hw *hw,
1122 enum nl80211_iftype type)
1123 {
1124 struct rtl_priv *rtlpriv = rtl_priv(hw);
1125 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1126 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1127 u8 mode = MSR_NOLINK;
1128
1129 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
1130 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
1131 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
1132
1133 switch (type) {
1134 case NL80211_IFTYPE_UNSPECIFIED:
1135 mode = MSR_NOLINK;
1136 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1137 "Set Network type to NO LINK!\n");
1138 break;
1139 case NL80211_IFTYPE_ADHOC:
1140 mode = MSR_ADHOC;
1141 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1142 "Set Network type to Ad Hoc!\n");
1143 break;
1144 case NL80211_IFTYPE_STATION:
1145 mode = MSR_INFRA;
1146 ledaction = LED_CTL_LINK;
1147 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1148 "Set Network type to STA!\n");
1149 break;
1150 case NL80211_IFTYPE_AP:
1151 mode = MSR_AP;
1152 ledaction = LED_CTL_LINK;
1153 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1154 "Set Network type to AP!\n");
1155 break;
1156 default:
1157 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1158 "Network type %d not support!\n", type);
1159 return 1;
1160 break;
1161 }
1162
1163 /* MSR_INFRA == Link in infrastructure network;
1164 * MSR_ADHOC == Link in ad hoc network;
1165 * Therefore, check link state is necessary.
1166 *
1167 * MSR_AP == AP mode; link state is not cared here.
1168 */
1169 if (mode != MSR_AP &&
1170 rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1171 mode = MSR_NOLINK;
1172 ledaction = LED_CTL_NO_LINK;
1173 }
1174 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1175 _rtl8723e_stop_tx_beacon(hw);
1176 _rtl8723e_enable_bcn_sub_func(hw);
1177 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1178 _rtl8723e_resume_tx_beacon(hw);
1179 _rtl8723e_disable_bcn_sub_func(hw);
1180 } else {
1181 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1182 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1183 mode);
1184 }
1185
1186 rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1187 rtlpriv->cfg->ops->led_control(hw, ledaction);
1188 if (mode == MSR_AP)
1189 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1190 else
1191 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1192 return 0;
1193 }
1194
1195 void rtl8723e_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1196 {
1197 struct rtl_priv *rtlpriv = rtl_priv(hw);
1198 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1199 u32 reg_rcr = rtlpci->receive_config;
1200
1201 if (rtlpriv->psc.rfpwr_state != ERFON)
1202 return;
1203
1204 if (check_bssid) {
1205 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1206 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1207 (u8 *)(&reg_rcr));
1208 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4));
1209 } else if (!check_bssid) {
1210 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1211 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0);
1212 rtlpriv->cfg->ops->set_hw_reg(hw,
1213 HW_VAR_RCR, (u8 *)(&reg_rcr));
1214 }
1215 }
1216
1217 int rtl8723e_set_network_type(struct ieee80211_hw *hw,
1218 enum nl80211_iftype type)
1219 {
1220 struct rtl_priv *rtlpriv = rtl_priv(hw);
1221
1222 if (_rtl8723e_set_media_status(hw, type))
1223 return -EOPNOTSUPP;
1224
1225 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1226 if (type != NL80211_IFTYPE_AP)
1227 rtl8723e_set_check_bssid(hw, true);
1228 } else {
1229 rtl8723e_set_check_bssid(hw, false);
1230 }
1231
1232 return 0;
1233 }
1234
1235 /* don't set REG_EDCA_BE_PARAM here
1236 * because mac80211 will send pkt when scan
1237 */
1238 void rtl8723e_set_qos(struct ieee80211_hw *hw, int aci)
1239 {
1240 struct rtl_priv *rtlpriv = rtl_priv(hw);
1241
1242 rtl8723_dm_init_edca_turbo(hw);
1243 switch (aci) {
1244 case AC1_BK:
1245 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1246 break;
1247 case AC0_BE:
1248 break;
1249 case AC2_VI:
1250 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1251 break;
1252 case AC3_VO:
1253 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1254 break;
1255 default:
1256 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1257 break;
1258 }
1259 }
1260
1261 void rtl8723e_enable_interrupt(struct ieee80211_hw *hw)
1262 {
1263 struct rtl_priv *rtlpriv = rtl_priv(hw);
1264 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1265
1266 rtl_write_dword(rtlpriv, 0x3a8, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1267 rtl_write_dword(rtlpriv, 0x3ac, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1268 rtlpci->irq_enabled = true;
1269 }
1270
1271 void rtl8723e_disable_interrupt(struct ieee80211_hw *hw)
1272 {
1273 struct rtl_priv *rtlpriv = rtl_priv(hw);
1274 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1275 rtl_write_dword(rtlpriv, 0x3a8, IMR8190_DISABLED);
1276 rtl_write_dword(rtlpriv, 0x3ac, IMR8190_DISABLED);
1277 rtlpci->irq_enabled = false;
1278 /*synchronize_irq(rtlpci->pdev->irq);*/
1279 }
1280
1281 static void _rtl8723e_poweroff_adapter(struct ieee80211_hw *hw)
1282 {
1283 struct rtl_priv *rtlpriv = rtl_priv(hw);
1284 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1285 u8 u1b_tmp;
1286
1287 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1288 /* 1. Run LPS WL RFOFF flow */
1289 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1290 PWR_INTF_PCI_MSK, Rtl8723_NIC_LPS_ENTER_FLOW);
1291
1292 /* 2. 0x1F[7:0] = 0 */
1293 /* turn off RF */
1294 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1295 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1296 rtlhal->fw_ready) {
1297 rtl8723ae_firmware_selfreset(hw);
1298 }
1299
1300 /* Reset MCU. Suggested by Filen. */
1301 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1302 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1303
1304 /* g. MCUFWDL 0x80[1:0]=0 */
1305 /* reset MCU ready status */
1306 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1307
1308 /* HW card disable configuration. */
1309 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1310 PWR_INTF_PCI_MSK, Rtl8723_NIC_DISABLE_FLOW);
1311
1312 /* Reset MCU IO Wrapper */
1313 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1314 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1315 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1316 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1317
1318 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1319 /* lock ISO/CLK/Power control register */
1320 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1321 }
1322
1323 void rtl8723e_card_disable(struct ieee80211_hw *hw)
1324 {
1325 struct rtl_priv *rtlpriv = rtl_priv(hw);
1326 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1327 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1328 enum nl80211_iftype opmode;
1329
1330 mac->link_state = MAC80211_NOLINK;
1331 opmode = NL80211_IFTYPE_UNSPECIFIED;
1332 _rtl8723e_set_media_status(hw, opmode);
1333 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1334 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1335 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1336 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1337 _rtl8723e_poweroff_adapter(hw);
1338
1339 /* after power off we should do iqk again */
1340 rtlpriv->phy.iqk_initialized = false;
1341 }
1342
1343 void rtl8723e_interrupt_recognized(struct ieee80211_hw *hw,
1344 u32 *p_inta, u32 *p_intb)
1345 {
1346 struct rtl_priv *rtlpriv = rtl_priv(hw);
1347 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1348
1349 *p_inta = rtl_read_dword(rtlpriv, 0x3a0) & rtlpci->irq_mask[0];
1350 rtl_write_dword(rtlpriv, 0x3a0, *p_inta);
1351 }
1352
1353 void rtl8723e_set_beacon_related_registers(struct ieee80211_hw *hw)
1354 {
1355
1356 struct rtl_priv *rtlpriv = rtl_priv(hw);
1357 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1358 u16 bcn_interval, atim_window;
1359
1360 bcn_interval = mac->beacon_interval;
1361 atim_window = 2; /*FIX MERGE */
1362 rtl8723e_disable_interrupt(hw);
1363 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1364 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1365 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1366 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1367 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1368 rtl_write_byte(rtlpriv, 0x606, 0x30);
1369 rtl8723e_enable_interrupt(hw);
1370 }
1371
1372 void rtl8723e_set_beacon_interval(struct ieee80211_hw *hw)
1373 {
1374 struct rtl_priv *rtlpriv = rtl_priv(hw);
1375 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1376 u16 bcn_interval = mac->beacon_interval;
1377
1378 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1379 "beacon_interval:%d\n", bcn_interval);
1380 rtl8723e_disable_interrupt(hw);
1381 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1382 rtl8723e_enable_interrupt(hw);
1383 }
1384
1385 void rtl8723e_update_interrupt_mask(struct ieee80211_hw *hw,
1386 u32 add_msr, u32 rm_msr)
1387 {
1388 struct rtl_priv *rtlpriv = rtl_priv(hw);
1389 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1390
1391 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1392 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1393
1394 if (add_msr)
1395 rtlpci->irq_mask[0] |= add_msr;
1396 if (rm_msr)
1397 rtlpci->irq_mask[0] &= (~rm_msr);
1398 rtl8723e_disable_interrupt(hw);
1399 rtl8723e_enable_interrupt(hw);
1400 }
1401
1402 static u8 _rtl8723e_get_chnl_group(u8 chnl)
1403 {
1404 u8 group;
1405
1406 if (chnl < 3)
1407 group = 0;
1408 else if (chnl < 9)
1409 group = 1;
1410 else
1411 group = 2;
1412 return group;
1413 }
1414
1415 static void _rtl8723e_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1416 bool autoload_fail,
1417 u8 *hwinfo)
1418 {
1419 struct rtl_priv *rtlpriv = rtl_priv(hw);
1420 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1421 u8 rf_path, index, tempval;
1422 u16 i;
1423
1424 for (rf_path = 0; rf_path < 1; rf_path++) {
1425 for (i = 0; i < 3; i++) {
1426 if (!autoload_fail) {
1427 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1428 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1429 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1430 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + i];
1431 } else {
1432 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1433 EEPROM_DEFAULT_TXPOWERLEVEL;
1434 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1435 EEPROM_DEFAULT_TXPOWERLEVEL;
1436 }
1437 }
1438 }
1439
1440 for (i = 0; i < 3; i++) {
1441 if (!autoload_fail)
1442 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1443 else
1444 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1445 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
1446 (tempval & 0xf);
1447 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
1448 ((tempval & 0xf0) >> 4);
1449 }
1450
1451 for (rf_path = 0; rf_path < 2; rf_path++)
1452 for (i = 0; i < 3; i++)
1453 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1454 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1455 i, rtlefuse->eeprom_chnlarea_txpwr_cck
1456 [rf_path][i]);
1457 for (rf_path = 0; rf_path < 2; rf_path++)
1458 for (i = 0; i < 3; i++)
1459 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1460 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1461 rf_path, i,
1462 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1463 [rf_path][i]);
1464 for (rf_path = 0; rf_path < 2; rf_path++)
1465 for (i = 0; i < 3; i++)
1466 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1467 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1468 rf_path, i,
1469 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1470 [rf_path][i]);
1471
1472 for (rf_path = 0; rf_path < 2; rf_path++) {
1473 for (i = 0; i < 14; i++) {
1474 index = _rtl8723e_get_chnl_group((u8)i);
1475
1476 rtlefuse->txpwrlevel_cck[rf_path][i] =
1477 rtlefuse->eeprom_chnlarea_txpwr_cck
1478 [rf_path][index];
1479 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1480 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1481 [rf_path][index];
1482
1483 if ((rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1484 [rf_path][index] -
1485 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1486 [rf_path][index]) > 0) {
1487 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1488 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1489 [rf_path][index] -
1490 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1491 [rf_path][index];
1492 } else {
1493 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1494 }
1495 }
1496
1497 for (i = 0; i < 14; i++) {
1498 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1499 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1500 rf_path, i,
1501 rtlefuse->txpwrlevel_cck[rf_path][i],
1502 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1503 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1504 }
1505 }
1506
1507 for (i = 0; i < 3; i++) {
1508 if (!autoload_fail) {
1509 rtlefuse->eeprom_pwrlimit_ht40[i] =
1510 hwinfo[EEPROM_TXPWR_GROUP + i];
1511 rtlefuse->eeprom_pwrlimit_ht20[i] =
1512 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1513 } else {
1514 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1515 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1516 }
1517 }
1518
1519 for (rf_path = 0; rf_path < 2; rf_path++) {
1520 for (i = 0; i < 14; i++) {
1521 index = _rtl8723e_get_chnl_group((u8)i);
1522
1523 if (rf_path == RF90_PATH_A) {
1524 rtlefuse->pwrgroup_ht20[rf_path][i] =
1525 (rtlefuse->eeprom_pwrlimit_ht20[index] & 0xf);
1526 rtlefuse->pwrgroup_ht40[rf_path][i] =
1527 (rtlefuse->eeprom_pwrlimit_ht40[index] & 0xf);
1528 } else if (rf_path == RF90_PATH_B) {
1529 rtlefuse->pwrgroup_ht20[rf_path][i] =
1530 ((rtlefuse->eeprom_pwrlimit_ht20[index] &
1531 0xf0) >> 4);
1532 rtlefuse->pwrgroup_ht40[rf_path][i] =
1533 ((rtlefuse->eeprom_pwrlimit_ht40[index] &
1534 0xf0) >> 4);
1535 }
1536
1537 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1538 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", rf_path, i,
1539 rtlefuse->pwrgroup_ht20[rf_path][i]);
1540 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1541 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", rf_path, i,
1542 rtlefuse->pwrgroup_ht40[rf_path][i]);
1543 }
1544 }
1545
1546 for (i = 0; i < 14; i++) {
1547 index = _rtl8723e_get_chnl_group((u8)i);
1548
1549 if (!autoload_fail)
1550 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1551 else
1552 tempval = EEPROM_DEFAULT_HT20_DIFF;
1553
1554 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1555 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1556 ((tempval >> 4) & 0xF);
1557
1558 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1559 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1560
1561 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1562 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1563
1564 index = _rtl8723e_get_chnl_group((u8)i);
1565
1566 if (!autoload_fail)
1567 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1568 else
1569 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1570
1571 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1572 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1573 ((tempval >> 4) & 0xF);
1574 }
1575
1576 rtlefuse->legacy_ht_txpowerdiff =
1577 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1578
1579 for (i = 0; i < 14; i++)
1580 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1581 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1582 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1583 for (i = 0; i < 14; i++)
1584 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1585 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1586 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1587 for (i = 0; i < 14; i++)
1588 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1589 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1590 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1591 for (i = 0; i < 14; i++)
1592 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1593 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1594 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1595
1596 if (!autoload_fail)
1597 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1598 else
1599 rtlefuse->eeprom_regulatory = 0;
1600 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1601 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1602
1603 if (!autoload_fail)
1604 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1605 else
1606 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1607
1608 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1609 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1610 rtlefuse->eeprom_tssi[RF90_PATH_A],
1611 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1612
1613 if (!autoload_fail)
1614 tempval = hwinfo[EEPROM_THERMAL_METER];
1615 else
1616 tempval = EEPROM_DEFAULT_THERMALMETER;
1617 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1618
1619 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1620 rtlefuse->apk_thermalmeterignore = true;
1621
1622 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1623 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1624 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1625 }
1626
1627 static void _rtl8723e_read_adapter_info(struct ieee80211_hw *hw,
1628 bool b_pseudo_test)
1629 {
1630 struct rtl_priv *rtlpriv = rtl_priv(hw);
1631 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1632 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1633 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1634 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
1635 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1636 COUNTRY_CODE_WORLD_WIDE_13};
1637 u8 *hwinfo;
1638
1639 if (b_pseudo_test) {
1640 /* need add */
1641 return;
1642 }
1643 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1644 if (!hwinfo)
1645 return;
1646
1647 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1648 goto exit;
1649
1650 _rtl8723e_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
1651 hwinfo);
1652
1653 rtl8723e_read_bt_coexist_info_from_hwpg(hw,
1654 rtlefuse->autoload_failflag, hwinfo);
1655
1656 if (rtlhal->oem_id != RT_CID_DEFAULT)
1657 goto exit;
1658
1659 switch (rtlefuse->eeprom_oemid) {
1660 case EEPROM_CID_DEFAULT:
1661 switch (rtlefuse->eeprom_did) {
1662 case 0x8176:
1663 switch (rtlefuse->eeprom_svid) {
1664 case 0x10EC:
1665 switch (rtlefuse->eeprom_smid) {
1666 case 0x6151 ... 0x6152:
1667 case 0x6154 ... 0x6155:
1668 case 0x6177 ... 0x6180:
1669 case 0x7151 ... 0x7152:
1670 case 0x7154 ... 0x7155:
1671 case 0x7177 ... 0x7180:
1672 case 0x8151 ... 0x8152:
1673 case 0x8154 ... 0x8155:
1674 case 0x8181 ... 0x8182:
1675 case 0x8184 ... 0x8185:
1676 case 0x9151 ... 0x9152:
1677 case 0x9154 ... 0x9155:
1678 case 0x9181 ... 0x9182:
1679 case 0x9184 ... 0x9185:
1680 rtlhal->oem_id = RT_CID_TOSHIBA;
1681 break;
1682 case 0x6191 ... 0x6193:
1683 case 0x7191 ... 0x7193:
1684 case 0x8191 ... 0x8193:
1685 case 0x9191 ... 0x9193:
1686 rtlhal->oem_id = RT_CID_819X_SAMSUNG;
1687 break;
1688 case 0x8197:
1689 case 0x9196:
1690 rtlhal->oem_id = RT_CID_819X_CLEVO;
1691 break;
1692 case 0x8203:
1693 rtlhal->oem_id = RT_CID_819X_PRONETS;
1694 break;
1695 case 0x8195:
1696 case 0x9195:
1697 case 0x7194:
1698 case 0x8200 ... 0x8202:
1699 case 0x9200:
1700 rtlhal->oem_id = RT_CID_819X_LENOVO;
1701 break;
1702 }
1703 case 0x1025:
1704 rtlhal->oem_id = RT_CID_819X_ACER;
1705 break;
1706 case 0x1028:
1707 switch (rtlefuse->eeprom_smid) {
1708 case 0x8194:
1709 case 0x8198:
1710 case 0x9197 ... 0x9198:
1711 rtlhal->oem_id = RT_CID_819X_DELL;
1712 break;
1713 }
1714 break;
1715 case 0x103C:
1716 switch (rtlefuse->eeprom_smid) {
1717 case 0x1629:
1718 rtlhal->oem_id = RT_CID_819X_HP;
1719 }
1720 break;
1721 case 0x1A32:
1722 switch (rtlefuse->eeprom_smid) {
1723 case 0x2315:
1724 rtlhal->oem_id = RT_CID_819X_QMI;
1725 break;
1726 }
1727 break;
1728 case 0x1043:
1729 switch (rtlefuse->eeprom_smid) {
1730 case 0x84B5:
1731 rtlhal->oem_id =
1732 RT_CID_819X_EDIMAX_ASUS;
1733 }
1734 break;
1735 }
1736 break;
1737 case 0x8178:
1738 switch (rtlefuse->eeprom_svid) {
1739 case 0x10ec:
1740 switch (rtlefuse->eeprom_smid) {
1741 case 0x6181 ... 0x6182:
1742 case 0x6184 ... 0x6185:
1743 case 0x7181 ... 0x7182:
1744 case 0x7184 ... 0x7185:
1745 case 0x8181 ... 0x8182:
1746 case 0x8184 ... 0x8185:
1747 case 0x9181 ... 0x9182:
1748 case 0x9184 ... 0x9185:
1749 rtlhal->oem_id = RT_CID_TOSHIBA;
1750 break;
1751 case 0x8186:
1752 rtlhal->oem_id =
1753 RT_CID_819X_PRONETS;
1754 break;
1755 }
1756 break;
1757 case 0x1025:
1758 rtlhal->oem_id = RT_CID_819X_ACER;
1759 break;
1760 case 0x1043:
1761 switch (rtlefuse->eeprom_smid) {
1762 case 0x8486:
1763 rtlhal->oem_id =
1764 RT_CID_819X_EDIMAX_ASUS;
1765 }
1766 break;
1767 }
1768 break;
1769 }
1770 break;
1771 case EEPROM_CID_TOSHIBA:
1772 rtlhal->oem_id = RT_CID_TOSHIBA;
1773 break;
1774 case EEPROM_CID_CCX:
1775 rtlhal->oem_id = RT_CID_CCX;
1776 break;
1777 case EEPROM_CID_QMI:
1778 rtlhal->oem_id = RT_CID_819X_QMI;
1779 break;
1780 case EEPROM_CID_WHQL:
1781 break;
1782 default:
1783 rtlhal->oem_id = RT_CID_DEFAULT;
1784 break;
1785 }
1786 exit:
1787 kfree(hwinfo);
1788 }
1789
1790 static void _rtl8723e_hal_customized_behavior(struct ieee80211_hw *hw)
1791 {
1792 struct rtl_priv *rtlpriv = rtl_priv(hw);
1793 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1794 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1795
1796 pcipriv->ledctl.led_opendrain = true;
1797 switch (rtlhal->oem_id) {
1798 case RT_CID_819X_HP:
1799 pcipriv->ledctl.led_opendrain = true;
1800 break;
1801 case RT_CID_819X_LENOVO:
1802 case RT_CID_DEFAULT:
1803 case RT_CID_TOSHIBA:
1804 case RT_CID_CCX:
1805 case RT_CID_819X_ACER:
1806 case RT_CID_WHQL:
1807 default:
1808 break;
1809 }
1810 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1811 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1812 }
1813
1814 void rtl8723e_read_eeprom_info(struct ieee80211_hw *hw)
1815 {
1816 struct rtl_priv *rtlpriv = rtl_priv(hw);
1817 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1818 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1819 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1820 u8 tmp_u1b;
1821 u32 value32;
1822
1823 value32 = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST]);
1824 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1825 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST], value32);
1826
1827 rtlhal->version = _rtl8723e_read_chip_version(hw);
1828
1829 if (get_rf_type(rtlphy) == RF_1T1R)
1830 rtlpriv->dm.rfpath_rxenable[0] = true;
1831 else
1832 rtlpriv->dm.rfpath_rxenable[0] =
1833 rtlpriv->dm.rfpath_rxenable[1] = true;
1834 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1835 rtlhal->version);
1836
1837 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1838 if (tmp_u1b & BIT(4)) {
1839 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1840 rtlefuse->epromtype = EEPROM_93C46;
1841 } else {
1842 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1843 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1844 }
1845 if (tmp_u1b & BIT(5)) {
1846 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1847 rtlefuse->autoload_failflag = false;
1848 _rtl8723e_read_adapter_info(hw, false);
1849 } else {
1850 rtlefuse->autoload_failflag = true;
1851 _rtl8723e_read_adapter_info(hw, false);
1852 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1853 }
1854 _rtl8723e_hal_customized_behavior(hw);
1855 }
1856
1857 static void rtl8723e_update_hal_rate_table(struct ieee80211_hw *hw,
1858 struct ieee80211_sta *sta)
1859 {
1860 struct rtl_priv *rtlpriv = rtl_priv(hw);
1861 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1862 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1863 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1864 u32 ratr_value;
1865 u8 ratr_index = 0;
1866 u8 b_nmode = mac->ht_enable;
1867 u16 shortgi_rate;
1868 u32 tmp_ratr_value;
1869 u8 curtxbw_40mhz = mac->bw_40;
1870 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1871 1 : 0;
1872 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1873 1 : 0;
1874 enum wireless_mode wirelessmode = mac->mode;
1875 u32 ratr_mask;
1876
1877 if (rtlhal->current_bandtype == BAND_ON_5G)
1878 ratr_value = sta->supp_rates[1] << 4;
1879 else
1880 ratr_value = sta->supp_rates[0];
1881 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1882 ratr_value = 0xfff;
1883 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1884 sta->ht_cap.mcs.rx_mask[0] << 12);
1885 switch (wirelessmode) {
1886 case WIRELESS_MODE_B:
1887 if (ratr_value & 0x0000000c)
1888 ratr_value &= 0x0000000d;
1889 else
1890 ratr_value &= 0x0000000f;
1891 break;
1892 case WIRELESS_MODE_G:
1893 ratr_value &= 0x00000FF5;
1894 break;
1895 case WIRELESS_MODE_N_24G:
1896 case WIRELESS_MODE_N_5G:
1897 b_nmode = 1;
1898 if (get_rf_type(rtlphy) == RF_1T2R ||
1899 get_rf_type(rtlphy) == RF_1T1R)
1900 ratr_mask = 0x000ff005;
1901 else
1902 ratr_mask = 0x0f0ff005;
1903
1904 ratr_value &= ratr_mask;
1905 break;
1906 default:
1907 if (rtlphy->rf_type == RF_1T2R)
1908 ratr_value &= 0x000ff0ff;
1909 else
1910 ratr_value &= 0x0f0ff0ff;
1911
1912 break;
1913 }
1914
1915 if ((rtlpriv->btcoexist.bt_coexistence) &&
1916 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
1917 (rtlpriv->btcoexist.bt_cur_state) &&
1918 (rtlpriv->btcoexist.bt_ant_isolation) &&
1919 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
1920 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
1921 ratr_value &= 0x0fffcfc0;
1922 else
1923 ratr_value &= 0x0FFFFFFF;
1924
1925 if (b_nmode &&
1926 ((curtxbw_40mhz && curshortgi_40mhz) ||
1927 (!curtxbw_40mhz && curshortgi_20mhz))) {
1928 ratr_value |= 0x10000000;
1929 tmp_ratr_value = (ratr_value >> 12);
1930
1931 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1932 if ((1 << shortgi_rate) & tmp_ratr_value)
1933 break;
1934 }
1935
1936 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1937 (shortgi_rate << 4) | (shortgi_rate);
1938 }
1939
1940 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1941
1942 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1943 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
1944 }
1945
1946 static void rtl8723e_update_hal_rate_mask(struct ieee80211_hw *hw,
1947 struct ieee80211_sta *sta,
1948 u8 rssi_level)
1949 {
1950 struct rtl_priv *rtlpriv = rtl_priv(hw);
1951 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1952 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1953 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1954 struct rtl_sta_info *sta_entry = NULL;
1955 u32 ratr_bitmap;
1956 u8 ratr_index;
1957 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1958 ? 1 : 0;
1959 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1960 1 : 0;
1961 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1962 1 : 0;
1963 enum wireless_mode wirelessmode = 0;
1964 bool shortgi = false;
1965 u8 rate_mask[5];
1966 u8 macid = 0;
1967 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
1968
1969 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1970 wirelessmode = sta_entry->wireless_mode;
1971 if (mac->opmode == NL80211_IFTYPE_STATION)
1972 curtxbw_40mhz = mac->bw_40;
1973 else if (mac->opmode == NL80211_IFTYPE_AP ||
1974 mac->opmode == NL80211_IFTYPE_ADHOC)
1975 macid = sta->aid + 1;
1976
1977 if (rtlhal->current_bandtype == BAND_ON_5G)
1978 ratr_bitmap = sta->supp_rates[1] << 4;
1979 else
1980 ratr_bitmap = sta->supp_rates[0];
1981 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1982 ratr_bitmap = 0xfff;
1983 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1984 sta->ht_cap.mcs.rx_mask[0] << 12);
1985 switch (wirelessmode) {
1986 case WIRELESS_MODE_B:
1987 ratr_index = RATR_INX_WIRELESS_B;
1988 if (ratr_bitmap & 0x0000000c)
1989 ratr_bitmap &= 0x0000000d;
1990 else
1991 ratr_bitmap &= 0x0000000f;
1992 break;
1993 case WIRELESS_MODE_G:
1994 ratr_index = RATR_INX_WIRELESS_GB;
1995
1996 if (rssi_level == 1)
1997 ratr_bitmap &= 0x00000f00;
1998 else if (rssi_level == 2)
1999 ratr_bitmap &= 0x00000ff0;
2000 else
2001 ratr_bitmap &= 0x00000ff5;
2002 break;
2003 case WIRELESS_MODE_A:
2004 ratr_index = RATR_INX_WIRELESS_G;
2005 ratr_bitmap &= 0x00000ff0;
2006 break;
2007 case WIRELESS_MODE_N_24G:
2008 case WIRELESS_MODE_N_5G:
2009 ratr_index = RATR_INX_WIRELESS_NGB;
2010 if (rtlphy->rf_type == RF_1T2R ||
2011 rtlphy->rf_type == RF_1T1R) {
2012 if (curtxbw_40mhz) {
2013 if (rssi_level == 1)
2014 ratr_bitmap &= 0x000f0000;
2015 else if (rssi_level == 2)
2016 ratr_bitmap &= 0x000ff000;
2017 else
2018 ratr_bitmap &= 0x000ff015;
2019 } else {
2020 if (rssi_level == 1)
2021 ratr_bitmap &= 0x000f0000;
2022 else if (rssi_level == 2)
2023 ratr_bitmap &= 0x000ff000;
2024 else
2025 ratr_bitmap &= 0x000ff005;
2026 }
2027 } else {
2028 if (curtxbw_40mhz) {
2029 if (rssi_level == 1)
2030 ratr_bitmap &= 0x0f0f0000;
2031 else if (rssi_level == 2)
2032 ratr_bitmap &= 0x0f0ff000;
2033 else
2034 ratr_bitmap &= 0x0f0ff015;
2035 } else {
2036 if (rssi_level == 1)
2037 ratr_bitmap &= 0x0f0f0000;
2038 else if (rssi_level == 2)
2039 ratr_bitmap &= 0x0f0ff000;
2040 else
2041 ratr_bitmap &= 0x0f0ff005;
2042 }
2043 }
2044
2045 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2046 (!curtxbw_40mhz && curshortgi_20mhz)) {
2047 if (macid == 0)
2048 shortgi = true;
2049 else if (macid == 1)
2050 shortgi = false;
2051 }
2052 break;
2053 default:
2054 ratr_index = RATR_INX_WIRELESS_NGB;
2055
2056 if (rtlphy->rf_type == RF_1T2R)
2057 ratr_bitmap &= 0x000ff0ff;
2058 else
2059 ratr_bitmap &= 0x0f0ff0ff;
2060 break;
2061 }
2062 sta_entry->ratr_index = ratr_index;
2063
2064 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2065 "ratr_bitmap :%x\n", ratr_bitmap);
2066 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2067 (ratr_index << 28);
2068 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2069 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2070 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2071 ratr_index, ratr_bitmap,
2072 rate_mask[0], rate_mask[1],
2073 rate_mask[2], rate_mask[3],
2074 rate_mask[4]);
2075 rtl8723e_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2076 }
2077
2078 void rtl8723e_update_hal_rate_tbl(struct ieee80211_hw *hw,
2079 struct ieee80211_sta *sta, u8 rssi_level)
2080 {
2081 struct rtl_priv *rtlpriv = rtl_priv(hw);
2082
2083 if (rtlpriv->dm.useramask)
2084 rtl8723e_update_hal_rate_mask(hw, sta, rssi_level);
2085 else
2086 rtl8723e_update_hal_rate_table(hw, sta);
2087 }
2088
2089 void rtl8723e_update_channel_access_setting(struct ieee80211_hw *hw)
2090 {
2091 struct rtl_priv *rtlpriv = rtl_priv(hw);
2092 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2093 u16 sifs_timer;
2094
2095 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2096 if (!mac->ht_enable)
2097 sifs_timer = 0x0a0a;
2098 else
2099 sifs_timer = 0x1010;
2100 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2101 }
2102
2103 bool rtl8723e_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2104 {
2105 struct rtl_priv *rtlpriv = rtl_priv(hw);
2106 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2107 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2108 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2109 u8 u1tmp;
2110 bool b_actuallyset = false;
2111
2112 if (rtlpriv->rtlhal.being_init_adapter)
2113 return false;
2114
2115 if (ppsc->swrf_processing)
2116 return false;
2117
2118 spin_lock(&rtlpriv->locks.rf_ps_lock);
2119 if (ppsc->rfchange_inprogress) {
2120 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2121 return false;
2122 } else {
2123 ppsc->rfchange_inprogress = true;
2124 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2125 }
2126
2127 cur_rfstate = ppsc->rfpwr_state;
2128
2129 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
2130 rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2)&~(BIT(1)));
2131
2132 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
2133
2134 if (rtlphy->polarity_ctl)
2135 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
2136 else
2137 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2138
2139 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2140 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2141 "GPIOChangeRF - HW Radio ON, RF ON\n");
2142
2143 e_rfpowerstate_toset = ERFON;
2144 ppsc->hwradiooff = false;
2145 b_actuallyset = true;
2146 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2147 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2148 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2149
2150 e_rfpowerstate_toset = ERFOFF;
2151 ppsc->hwradiooff = true;
2152 b_actuallyset = true;
2153 }
2154
2155 if (b_actuallyset) {
2156 spin_lock(&rtlpriv->locks.rf_ps_lock);
2157 ppsc->rfchange_inprogress = false;
2158 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2159 } else {
2160 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2161 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2162
2163 spin_lock(&rtlpriv->locks.rf_ps_lock);
2164 ppsc->rfchange_inprogress = false;
2165 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2166 }
2167
2168 *valid = 1;
2169 return !ppsc->hwradiooff;
2170
2171 }
2172
2173 void rtl8723e_set_key(struct ieee80211_hw *hw, u32 key_index,
2174 u8 *p_macaddr, bool is_group, u8 enc_algo,
2175 bool is_wepkey, bool clear_all)
2176 {
2177 struct rtl_priv *rtlpriv = rtl_priv(hw);
2178 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2179 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2180 u8 *macaddr = p_macaddr;
2181 u32 entry_id = 0;
2182 bool is_pairwise = false;
2183
2184 static u8 cam_const_addr[4][6] = {
2185 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2186 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2187 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2188 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2189 };
2190 static u8 cam_const_broad[] = {
2191 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2192 };
2193
2194 if (clear_all) {
2195 u8 idx = 0;
2196 u8 cam_offset = 0;
2197 u8 clear_number = 5;
2198
2199 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2200
2201 for (idx = 0; idx < clear_number; idx++) {
2202 rtl_cam_mark_invalid(hw, cam_offset + idx);
2203 rtl_cam_empty_entry(hw, cam_offset + idx);
2204
2205 if (idx < 5) {
2206 memset(rtlpriv->sec.key_buf[idx], 0,
2207 MAX_KEY_LEN);
2208 rtlpriv->sec.key_len[idx] = 0;
2209 }
2210 }
2211
2212 } else {
2213 switch (enc_algo) {
2214 case WEP40_ENCRYPTION:
2215 enc_algo = CAM_WEP40;
2216 break;
2217 case WEP104_ENCRYPTION:
2218 enc_algo = CAM_WEP104;
2219 break;
2220 case TKIP_ENCRYPTION:
2221 enc_algo = CAM_TKIP;
2222 break;
2223 case AESCCMP_ENCRYPTION:
2224 enc_algo = CAM_AES;
2225 break;
2226 default:
2227 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2228 "switch case not process\n");
2229 enc_algo = CAM_TKIP;
2230 break;
2231 }
2232
2233 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2234 macaddr = cam_const_addr[key_index];
2235 entry_id = key_index;
2236 } else {
2237 if (is_group) {
2238 macaddr = cam_const_broad;
2239 entry_id = key_index;
2240 } else {
2241 if (mac->opmode == NL80211_IFTYPE_AP) {
2242 entry_id =
2243 rtl_cam_get_free_entry(hw, p_macaddr);
2244 if (entry_id >= TOTAL_CAM_ENTRY) {
2245 RT_TRACE(rtlpriv, COMP_SEC,
2246 DBG_EMERG,
2247 "Can not find free hw security cam entry\n");
2248 return;
2249 }
2250 } else {
2251 entry_id = CAM_PAIRWISE_KEY_POSITION;
2252 }
2253
2254 key_index = PAIRWISE_KEYIDX;
2255 is_pairwise = true;
2256 }
2257 }
2258
2259 if (rtlpriv->sec.key_len[key_index] == 0) {
2260 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2261 "delete one entry, entry_id is %d\n",
2262 entry_id);
2263 if (mac->opmode == NL80211_IFTYPE_AP)
2264 rtl_cam_del_entry(hw, p_macaddr);
2265 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2266 } else {
2267 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2268 "add one entry\n");
2269 if (is_pairwise) {
2270 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2271 "set Pairwiase key\n");
2272
2273 rtl_cam_add_one_entry(hw, macaddr, key_index,
2274 entry_id, enc_algo,
2275 CAM_CONFIG_NO_USEDK,
2276 rtlpriv->sec.key_buf[key_index]);
2277 } else {
2278 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2279 "set group key\n");
2280
2281 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2282 rtl_cam_add_one_entry(hw,
2283 rtlefuse->dev_addr,
2284 PAIRWISE_KEYIDX,
2285 CAM_PAIRWISE_KEY_POSITION,
2286 enc_algo,
2287 CAM_CONFIG_NO_USEDK,
2288 rtlpriv->sec.key_buf
2289 [entry_id]);
2290 }
2291
2292 rtl_cam_add_one_entry(hw, macaddr, key_index,
2293 entry_id, enc_algo,
2294 CAM_CONFIG_NO_USEDK,
2295 rtlpriv->sec.key_buf[entry_id]);
2296 }
2297
2298 }
2299 }
2300 }
2301
2302 static void rtl8723e_bt_var_init(struct ieee80211_hw *hw)
2303 {
2304 struct rtl_priv *rtlpriv = rtl_priv(hw);
2305
2306 rtlpriv->btcoexist.bt_coexistence =
2307 rtlpriv->btcoexist.eeprom_bt_coexist;
2308 rtlpriv->btcoexist.bt_ant_num =
2309 rtlpriv->btcoexist.eeprom_bt_ant_num;
2310 rtlpriv->btcoexist.bt_coexist_type =
2311 rtlpriv->btcoexist.eeprom_bt_type;
2312
2313 rtlpriv->btcoexist.bt_ant_isolation =
2314 rtlpriv->btcoexist.eeprom_bt_ant_isol;
2315
2316 rtlpriv->btcoexist.bt_radio_shared_type =
2317 rtlpriv->btcoexist.eeprom_bt_radio_shared;
2318
2319 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2320 "BT Coexistance = 0x%x\n",
2321 rtlpriv->btcoexist.bt_coexistence);
2322
2323 if (rtlpriv->btcoexist.bt_coexistence) {
2324 rtlpriv->btcoexist.bt_busy_traffic = false;
2325 rtlpriv->btcoexist.bt_traffic_mode_set = false;
2326 rtlpriv->btcoexist.bt_non_traffic_mode_set = false;
2327
2328 rtlpriv->btcoexist.cstate = 0;
2329 rtlpriv->btcoexist.previous_state = 0;
2330
2331 if (rtlpriv->btcoexist.bt_ant_num == ANT_X2) {
2332 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2333 "BlueTooth BT_Ant_Num = Antx2\n");
2334 } else if (rtlpriv->btcoexist.bt_ant_num == ANT_X1) {
2335 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2336 "BlueTooth BT_Ant_Num = Antx1\n");
2337 }
2338 switch (rtlpriv->btcoexist.bt_coexist_type) {
2339 case BT_2WIRE:
2340 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2341 "BlueTooth BT_CoexistType = BT_2Wire\n");
2342 break;
2343 case BT_ISSC_3WIRE:
2344 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2345 "BlueTooth BT_CoexistType = BT_ISSC_3Wire\n");
2346 break;
2347 case BT_ACCEL:
2348 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2349 "BlueTooth BT_CoexistType = BT_ACCEL\n");
2350 break;
2351 case BT_CSR_BC4:
2352 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2353 "BlueTooth BT_CoexistType = BT_CSR_BC4\n");
2354 break;
2355 case BT_CSR_BC8:
2356 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2357 "BlueTooth BT_CoexistType = BT_CSR_BC8\n");
2358 break;
2359 case BT_RTL8756:
2360 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2361 "BlueTooth BT_CoexistType = BT_RTL8756\n");
2362 break;
2363 default:
2364 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2365 "BlueTooth BT_CoexistType = Unknown\n");
2366 break;
2367 }
2368 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2369 "BlueTooth BT_Ant_isolation = %d\n",
2370 rtlpriv->btcoexist.bt_ant_isolation);
2371 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2372 "BT_RadioSharedType = 0x%x\n",
2373 rtlpriv->btcoexist.bt_radio_shared_type);
2374 rtlpriv->btcoexist.bt_active_zero_cnt = 0;
2375 rtlpriv->btcoexist.cur_bt_disabled = false;
2376 rtlpriv->btcoexist.pre_bt_disabled = false;
2377 }
2378 }
2379
2380 void rtl8723e_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2381 bool auto_load_fail, u8 *hwinfo)
2382 {
2383 struct rtl_priv *rtlpriv = rtl_priv(hw);
2384 u8 value;
2385 u32 tmpu_32;
2386
2387 if (!auto_load_fail) {
2388 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2389 if (tmpu_32 & BIT(18))
2390 rtlpriv->btcoexist.eeprom_bt_coexist = 1;
2391 else
2392 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2393 value = hwinfo[RF_OPTION4];
2394 rtlpriv->btcoexist.eeprom_bt_type = BT_RTL8723A;
2395 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1);
2396 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2397 rtlpriv->btcoexist.eeprom_bt_radio_shared =
2398 ((value & 0x20) >> 5);
2399 } else {
2400 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2401 rtlpriv->btcoexist.eeprom_bt_type = BT_RTL8723A;
2402 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2403 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2404 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2405 }
2406
2407 rtl8723e_bt_var_init(hw);
2408 }
2409
2410 void rtl8723e_bt_reg_init(struct ieee80211_hw *hw)
2411 {
2412 struct rtl_priv *rtlpriv = rtl_priv(hw);
2413
2414 /* 0:Low, 1:High, 2:From Efuse. */
2415 rtlpriv->btcoexist.reg_bt_iso = 2;
2416 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2417 rtlpriv->btcoexist.reg_bt_sco = 3;
2418 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2419 rtlpriv->btcoexist.reg_bt_sco = 0;
2420 }
2421
2422 void rtl8723e_bt_hw_init(struct ieee80211_hw *hw)
2423 {
2424 struct rtl_priv *rtlpriv = rtl_priv(hw);
2425
2426 if (rtlpriv->cfg->ops->get_btc_status())
2427 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2428 }
2429
2430 void rtl8723e_suspend(struct ieee80211_hw *hw)
2431 {
2432 }
2433
2434 void rtl8723e_resume(struct ieee80211_hw *hw)
2435 {
2436 }
Linux kernel - Deliverables
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