drivers/net/wireless/ti/wl18xx/acx.h

   1 /*
   2  * This file is part of wl18xx
   3  *
   4  * Copyright (C) 2011 Texas Instruments. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  *
  20  */
  21
  22 #ifndef __WL18XX_ACX_H__
  23 #define __WL18XX_ACX_H__
  24
  25 #include "../wlcore/wlcore.h"
  26 #include "../wlcore/acx.h"
  27
  28 enum {
  29         ACX_NS_IPV6_FILTER               = 0x0050,
  30         ACX_PEER_HT_OPERATION_MODE_CFG   = 0x0051,
  31         ACX_CSUM_CONFIG                  = 0x0052,
  32         ACX_SIM_CONFIG                   = 0x0053,
  33         ACX_CLEAR_STATISTICS             = 0x0054,
  34         ACX_AUTO_RX_STREAMING            = 0x0055,
  35         ACX_PEER_CAP                     = 0x0056,
  36         ACX_INTERRUPT_NOTIFY             = 0x0057,
  37         ACX_RX_BA_FILTER                 = 0x0058,
  38         ACX_AP_SLEEP_CFG                 = 0x0059,
  39         ACX_DYNAMIC_TRACES_CFG           = 0x005A,
  40         ACX_TIME_SYNC_CFG                = 0x005B,
  41 };
  42
  43 /* numbers of bits the length field takes (add 1 for the actual number) */
  44 #define WL18XX_HOST_IF_LEN_SIZE_FIELD 15
  45
  46 #define WL18XX_ACX_EVENTS_VECTOR        (WL1271_ACX_INTR_WATCHDOG       | \
  47                                          WL1271_ACX_INTR_INIT_COMPLETE  | \
  48                                          WL1271_ACX_INTR_EVENT_A        | \
  49                                          WL1271_ACX_INTR_EVENT_B        | \
  50                                          WL1271_ACX_INTR_CMD_COMPLETE   | \
  51                                          WL1271_ACX_INTR_HW_AVAILABLE   | \
  52                                          WL1271_ACX_INTR_DATA           | \
  53                                          WL1271_ACX_SW_INTR_WATCHDOG)
  54
  55 #define WL18XX_INTR_MASK                (WL1271_ACX_INTR_WATCHDOG       | \
  56                                          WL1271_ACX_INTR_EVENT_A        | \
  57                                          WL1271_ACX_INTR_EVENT_B        | \
  58                                          WL1271_ACX_INTR_HW_AVAILABLE   | \
  59                                          WL1271_ACX_INTR_DATA           | \
  60                                          WL1271_ACX_SW_INTR_WATCHDOG)
  61
  62 struct wl18xx_acx_host_config_bitmap {
  63         struct acx_header header;
  64
  65         __le32 host_cfg_bitmap;
  66
  67         __le32 host_sdio_block_size;
  68
  69         /* extra mem blocks per frame in TX. */
  70         __le32 extra_mem_blocks;
  71
  72         /*
  73          * number of bits of the length field in the first TX word
  74          * (up to 15 - for using the entire 16 bits).
  75          */
  76         __le32 length_field_size;
  77
  78 } __packed;
  79
  80 enum {
  81         CHECKSUM_OFFLOAD_DISABLED = 0,
  82         CHECKSUM_OFFLOAD_ENABLED  = 1,
  83         CHECKSUM_OFFLOAD_FAKE_RX  = 2,
  84         CHECKSUM_OFFLOAD_INVALID  = 0xFF
  85 };
  86
  87 struct wl18xx_acx_checksum_state {
  88         struct acx_header header;
  89
  90          /* enum acx_checksum_state */
  91         u8 checksum_state;
  92         u8 pad[3];
  93 } __packed;
  94
  95
  96 struct wl18xx_acx_error_stats {
  97         u32 error_frame_non_ctrl;
  98         u32 error_frame_ctrl;
  99         u32 error_frame_during_protection;
 100         u32 null_frame_tx_start;
 101         u32 null_frame_cts_start;
 102         u32 bar_retry;
 103         u32 num_frame_cts_nul_flid;
 104         u32 tx_abort_failure;
 105         u32 tx_resume_failure;
 106         u32 rx_cmplt_db_overflow_cnt;
 107         u32 elp_while_rx_exch;
 108         u32 elp_while_tx_exch;
 109         u32 elp_while_tx;
 110         u32 elp_while_nvic_pending;
 111         u32 rx_excessive_frame_len;
 112         u32 burst_mismatch;
 113         u32 tbc_exch_mismatch;
 114 } __packed;
 115
 116 #define NUM_OF_RATES_INDEXES 30
 117 struct wl18xx_acx_tx_stats {
 118         u32 tx_prepared_descs;
 119         u32 tx_cmplt;
 120         u32 tx_template_prepared;
 121         u32 tx_data_prepared;
 122         u32 tx_template_programmed;
 123         u32 tx_data_programmed;
 124         u32 tx_burst_programmed;
 125         u32 tx_starts;
 126         u32 tx_stop;
 127         u32 tx_start_templates;
 128         u32 tx_start_int_templates;
 129         u32 tx_start_fw_gen;
 130         u32 tx_start_data;
 131         u32 tx_start_null_frame;
 132         u32 tx_exch;
 133         u32 tx_retry_template;
 134         u32 tx_retry_data;
 135         u32 tx_retry_per_rate[NUM_OF_RATES_INDEXES];
 136         u32 tx_exch_pending;
 137         u32 tx_exch_expiry;
 138         u32 tx_done_template;
 139         u32 tx_done_data;
 140         u32 tx_done_int_template;
 141         u32 tx_cfe1;
 142         u32 tx_cfe2;
 143         u32 frag_called;
 144         u32 frag_mpdu_alloc_failed;
 145         u32 frag_init_called;
 146         u32 frag_in_process_called;
 147         u32 frag_tkip_called;
 148         u32 frag_key_not_found;
 149         u32 frag_need_fragmentation;
 150         u32 frag_bad_mblk_num;
 151         u32 frag_failed;
 152         u32 frag_cache_hit;
 153         u32 frag_cache_miss;
 154 } __packed;
 155
 156 struct wl18xx_acx_rx_stats {
 157         u32 rx_beacon_early_term;
 158         u32 rx_out_of_mpdu_nodes;
 159         u32 rx_hdr_overflow;
 160         u32 rx_dropped_frame;
 161         u32 rx_done_stage;
 162         u32 rx_done;
 163         u32 rx_defrag;
 164         u32 rx_defrag_end;
 165         u32 rx_cmplt;
 166         u32 rx_pre_complt;
 167         u32 rx_cmplt_task;
 168         u32 rx_phy_hdr;
 169         u32 rx_timeout;
 170         u32 rx_rts_timeout;
 171         u32 rx_timeout_wa;
 172         u32 defrag_called;
 173         u32 defrag_init_called;
 174         u32 defrag_in_process_called;
 175         u32 defrag_tkip_called;
 176         u32 defrag_need_defrag;
 177         u32 defrag_decrypt_failed;
 178         u32 decrypt_key_not_found;
 179         u32 defrag_need_decrypt;
 180         u32 rx_tkip_replays;
 181         u32 rx_xfr;
 182 } __packed;
 183
 184 struct wl18xx_acx_isr_stats {
 185         u32 irqs;
 186 } __packed;
 187
 188 #define PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD 10
 189
 190 struct wl18xx_acx_pwr_stats {
 191         u32 missing_bcns_cnt;
 192         u32 rcvd_bcns_cnt;
 193         u32 connection_out_of_sync;
 194         u32 cont_miss_bcns_spread[PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD];
 195         u32 rcvd_awake_bcns_cnt;
 196         u32 sleep_time_count;
 197         u32 sleep_time_avg;
 198         u32 sleep_cycle_avg;
 199         u32 sleep_percent;
 200         u32 ap_sleep_active_conf;
 201         u32 ap_sleep_user_conf;
 202         u32 ap_sleep_counter;
 203 } __packed;
 204
 205 struct wl18xx_acx_rx_filter_stats {
 206         u32 beacon_filter;
 207         u32 arp_filter;
 208         u32 mc_filter;
 209         u32 dup_filter;
 210         u32 data_filter;
 211         u32 ibss_filter;
 212         u32 protection_filter;
 213         u32 accum_arp_pend_requests;
 214         u32 max_arp_queue_dep;
 215 } __packed;
 216
 217 struct wl18xx_acx_rx_rate_stats {
 218         u32 rx_frames_per_rates[50];
 219 } __packed;
 220
 221 #define AGGR_STATS_TX_AGG       16
 222 #define AGGR_STATS_RX_SIZE_LEN  16
 223
 224 struct wl18xx_acx_aggr_stats {
 225         u32 tx_agg_rate[AGGR_STATS_TX_AGG];
 226         u32 tx_agg_len[AGGR_STATS_TX_AGG];
 227         u32 rx_size[AGGR_STATS_RX_SIZE_LEN];
 228 } __packed;
 229
 230 #define PIPE_STATS_HW_FIFO      11
 231
 232 struct wl18xx_acx_pipeline_stats {
 233         u32 hs_tx_stat_fifo_int;
 234         u32 hs_rx_stat_fifo_int;
 235         u32 enc_tx_stat_fifo_int;
 236         u32 enc_rx_stat_fifo_int;
 237         u32 rx_complete_stat_fifo_int;
 238         u32 pre_proc_swi;
 239         u32 post_proc_swi;
 240         u32 sec_frag_swi;
 241         u32 pre_to_defrag_swi;
 242         u32 defrag_to_rx_xfer_swi;
 243         u32 dec_packet_in;
 244         u32 dec_packet_in_fifo_full;
 245         u32 dec_packet_out;
 246         u16 pipeline_fifo_full[PIPE_STATS_HW_FIFO];
 247         u16 padding;
 248 } __packed;
 249
 250 #define DIVERSITY_STATS_NUM_OF_ANT      2
 251
 252 struct wl18xx_acx_diversity_stats {
 253         u32 num_of_packets_per_ant[DIVERSITY_STATS_NUM_OF_ANT];
 254         u32 total_num_of_toggles;
 255 } __packed;
 256
 257 struct wl18xx_acx_thermal_stats {
 258         u16 irq_thr_low;
 259         u16 irq_thr_high;
 260         u16 tx_stop;
 261         u16 tx_resume;
 262         u16 false_irq;
 263         u16 adc_source_unexpected;
 264 } __packed;
 265
 266 #define WL18XX_NUM_OF_CALIBRATIONS_ERRORS 18
 267 struct wl18xx_acx_calib_failure_stats {
 268         u16 fail_count[WL18XX_NUM_OF_CALIBRATIONS_ERRORS];
 269         u32 calib_count;
 270 } __packed;
 271
 272 struct wl18xx_roaming_stats {
 273         s32 rssi_level;
 274 } __packed;
 275
 276 struct wl18xx_dfs_stats {
 277         u32 num_of_radar_detections;
 278 } __packed;
 279
 280 struct wl18xx_acx_statistics {
 281         struct acx_header header;
 282
 283         struct wl18xx_acx_error_stats           error;
 284         struct wl18xx_acx_tx_stats              tx;
 285         struct wl18xx_acx_rx_stats              rx;
 286         struct wl18xx_acx_isr_stats             isr;
 287         struct wl18xx_acx_pwr_stats             pwr;
 288         struct wl18xx_acx_rx_filter_stats       rx_filter;
 289         struct wl18xx_acx_rx_rate_stats         rx_rate;
 290         struct wl18xx_acx_aggr_stats            aggr_size;
 291         struct wl18xx_acx_pipeline_stats        pipeline;
 292         struct wl18xx_acx_diversity_stats       diversity;
 293         struct wl18xx_acx_thermal_stats         thermal;
 294         struct wl18xx_acx_calib_failure_stats   calib;
 295         struct wl18xx_roaming_stats             roaming;
 296         struct wl18xx_dfs_stats                 dfs;
 297 } __packed;
 298
 299 struct wl18xx_acx_clear_statistics {
 300         struct acx_header header;
 301 };
 302
 303 enum wlcore_bandwidth {
 304         WLCORE_BANDWIDTH_20MHZ,
 305         WLCORE_BANDWIDTH_40MHZ,
 306 };
 307
 308 struct wlcore_peer_ht_operation_mode {
 309         struct acx_header header;
 310
 311         u8 hlid;
 312         u8 bandwidth; /* enum wlcore_bandwidth */
 313         u8 padding[2];
 314 };
 315
 316 /*
 317  * ACX_PEER_CAP
 318  * this struct is very similar to wl1271_acx_ht_capabilities, with the
 319  * addition of supported rates
 320  */
 321 struct wlcore_acx_peer_cap {
 322         struct acx_header header;
 323
 324         /* bitmask of capability bits supported by the peer */
 325         __le32 ht_capabilites;
 326
 327         /* rates supported by the remote peer */
 328         __le32 supported_rates;
 329
 330         /* Indicates to which link these capabilities apply. */
 331         u8 hlid;
 332
 333         /*
 334          * This the maximum A-MPDU length supported by the AP. The FW may not
 335          * exceed this length when sending A-MPDUs
 336          */
 337         u8 ampdu_max_length;
 338
 339         /* This is the minimal spacing required when sending A-MPDUs to the AP*/
 340         u8 ampdu_min_spacing;
 341
 342         u8 padding;
 343 } __packed;
 344
 345 /*
 346  * ACX_INTERRUPT_NOTIFY
 347  * enable/disable fast-link/PSM notification from FW
 348  */
 349 struct wl18xx_acx_interrupt_notify {
 350         struct acx_header header;
 351         u32 enable;
 352 };
 353
 354 /*
 355  * ACX_RX_BA_FILTER
 356  * enable/disable RX BA filtering in FW
 357  */
 358 struct wl18xx_acx_rx_ba_filter {
 359         struct acx_header header;
 360         u32 enable;
 361 };
 362
 363 struct acx_ap_sleep_cfg {
 364         struct acx_header header;
 365         /* Duty Cycle (20-80% of staying Awake) for IDLE AP
 366          * (0: disable)
 367          */
 368         u8 idle_duty_cycle;
 369         /* Duty Cycle (20-80% of staying Awake) for Connected AP
 370          * (0: disable)
 371          */
 372         u8 connected_duty_cycle;
 373         /* Maximum stations that are allowed to be connected to AP
 374          *  (255: no limit)
 375          */
 376         u8 max_stations_thresh;
 377         /* Timeout till enabling the Sleep Mechanism after data stops
 378          * [unit: 100 msec]
 379          */
 380         u8 idle_conn_thresh;
 381 } __packed;
 382
 383 /*
 384  * ACX_DYNAMIC_TRACES_CFG
 385  * configure the FW dynamic traces
 386  */
 387 struct acx_dynamic_fw_traces_cfg {
 388         struct acx_header header;
 389         __le32 dynamic_fw_traces;
 390 } __packed;
 391
 392 /*
 393  * ACX_TIME_SYNC_CFG
 394  * configure the time sync parameters
 395  */
 396 struct acx_time_sync_cfg {
 397         struct acx_header header;
 398         u8 sync_mode;
 399         u8 zone_mac_addr[ETH_ALEN];
 400         u8 padding[1];
 401 } __packed;
 402
 403 int wl18xx_acx_host_if_cfg_bitmap(struct wl1271 *wl, u32 host_cfg_bitmap,
 404                                   u32 sdio_blk_size, u32 extra_mem_blks,
 405                                   u32 len_field_size);
 406 int wl18xx_acx_set_checksum_state(struct wl1271 *wl);
 407 int wl18xx_acx_clear_statistics(struct wl1271 *wl);
 408 int wl18xx_acx_peer_ht_operation_mode(struct wl1271 *wl, u8 hlid, bool wide);
 409 int wl18xx_acx_set_peer_cap(struct wl1271 *wl,
 410                             struct ieee80211_sta_ht_cap *ht_cap,
 411                             bool allow_ht_operation,
 412                             u32 rate_set, u8 hlid);
 413 int wl18xx_acx_interrupt_notify_config(struct wl1271 *wl, bool action);
 414 int wl18xx_acx_rx_ba_filter(struct wl1271 *wl, bool action);
 415 int wl18xx_acx_ap_sleep(struct wl1271 *wl);
 416 int wl18xx_acx_dynamic_fw_traces(struct wl1271 *wl);
 417 int wl18xx_acx_time_sync_cfg(struct wl1271 *wl);
 418
 419 #endif /* __WL18XX_ACX_H__ */