2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/cpu.h>
20 #include <linux/delay.h>
21 #include <linux/errno.h>
23 #include <linux/genhd.h>
24 #include <linux/hdreg.h>
25 #include <linux/idr.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
29 #include <linux/kdev_t.h>
30 #include <linux/kthread.h>
31 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/mutex.h>
36 #include <linux/pci.h>
37 #include <linux/poison.h>
38 #include <linux/ptrace.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/t10-pi.h>
42 #include <linux/types.h>
43 #include <linux/io-64-nonatomic-lo-hi.h>
44 #include <asm/unaligned.h>
48 #define NVME_Q_DEPTH 1024
49 #define NVME_AQ_DEPTH 256
50 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
51 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
54 * We handle AEN commands ourselves and don't even let the
55 * block layer know about them.
57 #define NVME_NR_AEN_COMMANDS 1
58 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
60 unsigned char admin_timeout
= 60;
61 module_param(admin_timeout
, byte
, 0644);
62 MODULE_PARM_DESC(admin_timeout
, "timeout in seconds for admin commands");
64 unsigned char nvme_io_timeout
= 30;
65 module_param_named(io_timeout
, nvme_io_timeout
, byte
, 0644);
66 MODULE_PARM_DESC(io_timeout
, "timeout in seconds for I/O");
68 unsigned char shutdown_timeout
= 5;
69 module_param(shutdown_timeout
, byte
, 0644);
70 MODULE_PARM_DESC(shutdown_timeout
, "timeout in seconds for controller shutdown");
72 static int use_threaded_interrupts
;
73 module_param(use_threaded_interrupts
, int, 0);
75 static bool use_cmb_sqes
= true;
76 module_param(use_cmb_sqes
, bool, 0644);
77 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
79 static LIST_HEAD(dev_list
);
80 static struct task_struct
*nvme_thread
;
81 static struct workqueue_struct
*nvme_workq
;
82 static wait_queue_head_t nvme_kthread_wait
;
87 static int nvme_reset(struct nvme_dev
*dev
);
88 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
89 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
92 * Represents an NVM Express device. Each nvme_dev is a PCI function.
95 struct list_head node
;
96 struct nvme_queue
**queues
;
97 struct blk_mq_tag_set tagset
;
98 struct blk_mq_tag_set admin_tagset
;
101 struct dma_pool
*prp_page_pool
;
102 struct dma_pool
*prp_small_pool
;
103 unsigned queue_count
;
104 unsigned online_queues
;
108 struct msix_entry
*entry
;
110 struct work_struct reset_work
;
111 struct work_struct scan_work
;
112 struct work_struct remove_work
;
113 struct mutex shutdown_lock
;
116 dma_addr_t cmb_dma_addr
;
121 #define NVME_CTRL_RESETTING 0
122 #define NVME_CTRL_REMOVING 1
124 struct nvme_ctrl ctrl
;
125 struct completion ioq_wait
;
128 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
130 return container_of(ctrl
, struct nvme_dev
, ctrl
);
134 * An NVM Express queue. Each device has at least two (one for admin
135 * commands and one for I/O commands).
138 struct device
*q_dmadev
;
139 struct nvme_dev
*dev
;
140 char irqname
[24]; /* nvme4294967295-65535\0 */
142 struct nvme_command
*sq_cmds
;
143 struct nvme_command __iomem
*sq_cmds_io
;
144 volatile struct nvme_completion
*cqes
;
145 struct blk_mq_tags
**tags
;
146 dma_addr_t sq_dma_addr
;
147 dma_addr_t cq_dma_addr
;
160 * The nvme_iod describes the data in an I/O, including the list of PRP
161 * entries. You can't see it in this data structure because C doesn't let
162 * me express that. Use nvme_init_iod to ensure there's enough space
163 * allocated to store the PRP list.
166 struct nvme_queue
*nvmeq
;
168 int npages
; /* In the PRP list. 0 means small pool in use */
169 int nents
; /* Used in scatterlist */
170 int length
; /* Of data, in bytes */
171 dma_addr_t first_dma
;
172 struct scatterlist meta_sg
; /* metadata requires single contiguous buffer */
173 struct scatterlist
*sg
;
174 struct scatterlist inline_sg
[0];
178 * Check we didin't inadvertently grow the command struct
180 static inline void _nvme_check_size(void)
182 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
183 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
184 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
185 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
186 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
187 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
188 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
189 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
190 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
191 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
192 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
193 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
197 * Max size of iod being embedded in the request payload
199 #define NVME_INT_PAGES 2
200 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
203 * Will slightly overestimate the number of pages needed. This is OK
204 * as it only leads to a small amount of wasted memory for the lifetime of
207 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
209 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
210 dev
->ctrl
.page_size
);
211 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
214 static unsigned int nvme_iod_alloc_size(struct nvme_dev
*dev
,
215 unsigned int size
, unsigned int nseg
)
217 return sizeof(__le64
*) * nvme_npages(size
, dev
) +
218 sizeof(struct scatterlist
) * nseg
;
221 static unsigned int nvme_cmd_size(struct nvme_dev
*dev
)
223 return sizeof(struct nvme_iod
) +
224 nvme_iod_alloc_size(dev
, NVME_INT_BYTES(dev
), NVME_INT_PAGES
);
227 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
228 unsigned int hctx_idx
)
230 struct nvme_dev
*dev
= data
;
231 struct nvme_queue
*nvmeq
= dev
->queues
[0];
233 WARN_ON(hctx_idx
!= 0);
234 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
235 WARN_ON(nvmeq
->tags
);
237 hctx
->driver_data
= nvmeq
;
238 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
242 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
244 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
249 static int nvme_admin_init_request(void *data
, struct request
*req
,
250 unsigned int hctx_idx
, unsigned int rq_idx
,
251 unsigned int numa_node
)
253 struct nvme_dev
*dev
= data
;
254 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
255 struct nvme_queue
*nvmeq
= dev
->queues
[0];
262 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
263 unsigned int hctx_idx
)
265 struct nvme_dev
*dev
= data
;
266 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
269 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
271 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
272 hctx
->driver_data
= nvmeq
;
276 static int nvme_init_request(void *data
, struct request
*req
,
277 unsigned int hctx_idx
, unsigned int rq_idx
,
278 unsigned int numa_node
)
280 struct nvme_dev
*dev
= data
;
281 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
282 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
289 static void nvme_queue_scan(struct nvme_dev
*dev
)
292 * Do not queue new scan work when a controller is reset during
295 if (test_bit(NVME_CTRL_REMOVING
, &dev
->flags
))
297 queue_work(nvme_workq
, &dev
->scan_work
);
300 static void nvme_complete_async_event(struct nvme_dev
*dev
,
301 struct nvme_completion
*cqe
)
303 u16 status
= le16_to_cpu(cqe
->status
) >> 1;
304 u32 result
= le32_to_cpu(cqe
->result
);
306 if (status
== NVME_SC_SUCCESS
|| status
== NVME_SC_ABORT_REQ
)
307 ++dev
->ctrl
.event_limit
;
308 if (status
!= NVME_SC_SUCCESS
)
311 switch (result
& 0xff07) {
312 case NVME_AER_NOTICE_NS_CHANGED
:
313 dev_info(dev
->dev
, "rescanning\n");
314 nvme_queue_scan(dev
);
316 dev_warn(dev
->dev
, "async event result %08x\n", result
);
321 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
322 * @nvmeq: The queue to use
323 * @cmd: The command to send
325 * Safe to use from interrupt context
327 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
328 struct nvme_command
*cmd
)
330 u16 tail
= nvmeq
->sq_tail
;
332 if (nvmeq
->sq_cmds_io
)
333 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
335 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
337 if (++tail
== nvmeq
->q_depth
)
339 writel(tail
, nvmeq
->q_db
);
340 nvmeq
->sq_tail
= tail
;
343 static __le64
**iod_list(struct request
*req
)
345 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
346 return (__le64
**)(iod
->sg
+ req
->nr_phys_segments
);
349 static int nvme_init_iod(struct request
*rq
, struct nvme_dev
*dev
)
351 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(rq
);
352 int nseg
= rq
->nr_phys_segments
;
355 if (rq
->cmd_flags
& REQ_DISCARD
)
356 size
= sizeof(struct nvme_dsm_range
);
358 size
= blk_rq_bytes(rq
);
360 if (nseg
> NVME_INT_PAGES
|| size
> NVME_INT_BYTES(dev
)) {
361 iod
->sg
= kmalloc(nvme_iod_alloc_size(dev
, size
, nseg
), GFP_ATOMIC
);
363 return BLK_MQ_RQ_QUEUE_BUSY
;
365 iod
->sg
= iod
->inline_sg
;
375 static void nvme_free_iod(struct nvme_dev
*dev
, struct request
*req
)
377 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
378 const int last_prp
= dev
->ctrl
.page_size
/ 8 - 1;
380 __le64
**list
= iod_list(req
);
381 dma_addr_t prp_dma
= iod
->first_dma
;
383 if (iod
->npages
== 0)
384 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
385 for (i
= 0; i
< iod
->npages
; i
++) {
386 __le64
*prp_list
= list
[i
];
387 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
388 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
389 prp_dma
= next_prp_dma
;
392 if (iod
->sg
!= iod
->inline_sg
)
396 #ifdef CONFIG_BLK_DEV_INTEGRITY
397 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
399 if (be32_to_cpu(pi
->ref_tag
) == v
)
400 pi
->ref_tag
= cpu_to_be32(p
);
403 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
405 if (be32_to_cpu(pi
->ref_tag
) == p
)
406 pi
->ref_tag
= cpu_to_be32(v
);
410 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
412 * The virtual start sector is the one that was originally submitted by the
413 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
414 * start sector may be different. Remap protection information to match the
415 * physical LBA on writes, and back to the original seed on reads.
417 * Type 0 and 3 do not have a ref tag, so no remapping required.
419 static void nvme_dif_remap(struct request
*req
,
420 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
422 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
423 struct bio_integrity_payload
*bip
;
424 struct t10_pi_tuple
*pi
;
426 u32 i
, nlb
, ts
, phys
, virt
;
428 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
431 bip
= bio_integrity(req
->bio
);
435 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
438 virt
= bip_get_seed(bip
);
439 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
440 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
441 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
443 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
444 pi
= (struct t10_pi_tuple
*)p
;
445 dif_swap(phys
, virt
, pi
);
450 #else /* CONFIG_BLK_DEV_INTEGRITY */
451 static void nvme_dif_remap(struct request
*req
,
452 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
455 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
458 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
463 static bool nvme_setup_prps(struct nvme_dev
*dev
, struct request
*req
,
466 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
467 struct dma_pool
*pool
;
468 int length
= total_len
;
469 struct scatterlist
*sg
= iod
->sg
;
470 int dma_len
= sg_dma_len(sg
);
471 u64 dma_addr
= sg_dma_address(sg
);
472 u32 page_size
= dev
->ctrl
.page_size
;
473 int offset
= dma_addr
& (page_size
- 1);
475 __le64
**list
= iod_list(req
);
479 length
-= (page_size
- offset
);
483 dma_len
-= (page_size
- offset
);
485 dma_addr
+= (page_size
- offset
);
488 dma_addr
= sg_dma_address(sg
);
489 dma_len
= sg_dma_len(sg
);
492 if (length
<= page_size
) {
493 iod
->first_dma
= dma_addr
;
497 nprps
= DIV_ROUND_UP(length
, page_size
);
498 if (nprps
<= (256 / 8)) {
499 pool
= dev
->prp_small_pool
;
502 pool
= dev
->prp_page_pool
;
506 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
508 iod
->first_dma
= dma_addr
;
513 iod
->first_dma
= prp_dma
;
516 if (i
== page_size
>> 3) {
517 __le64
*old_prp_list
= prp_list
;
518 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
521 list
[iod
->npages
++] = prp_list
;
522 prp_list
[0] = old_prp_list
[i
- 1];
523 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
526 prp_list
[i
++] = cpu_to_le64(dma_addr
);
527 dma_len
-= page_size
;
528 dma_addr
+= page_size
;
536 dma_addr
= sg_dma_address(sg
);
537 dma_len
= sg_dma_len(sg
);
543 static int nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
544 struct nvme_command
*cmnd
)
546 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
547 struct request_queue
*q
= req
->q
;
548 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
549 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
550 int ret
= BLK_MQ_RQ_QUEUE_ERROR
;
552 sg_init_table(iod
->sg
, req
->nr_phys_segments
);
553 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
557 ret
= BLK_MQ_RQ_QUEUE_BUSY
;
558 if (!dma_map_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
))
561 if (!nvme_setup_prps(dev
, req
, blk_rq_bytes(req
)))
564 ret
= BLK_MQ_RQ_QUEUE_ERROR
;
565 if (blk_integrity_rq(req
)) {
566 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
569 sg_init_table(&iod
->meta_sg
, 1);
570 if (blk_rq_map_integrity_sg(q
, req
->bio
, &iod
->meta_sg
) != 1)
573 if (rq_data_dir(req
))
574 nvme_dif_remap(req
, nvme_dif_prep
);
576 if (!dma_map_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
))
580 cmnd
->rw
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
581 cmnd
->rw
.prp2
= cpu_to_le64(iod
->first_dma
);
582 if (blk_integrity_rq(req
))
583 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(&iod
->meta_sg
));
584 return BLK_MQ_RQ_QUEUE_OK
;
587 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
592 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
594 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
595 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
596 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
599 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
600 if (blk_integrity_rq(req
)) {
601 if (!rq_data_dir(req
))
602 nvme_dif_remap(req
, nvme_dif_complete
);
603 dma_unmap_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
);
607 nvme_free_iod(dev
, req
);
611 * We reuse the small pool to allocate the 16-byte range here as it is not
612 * worth having a special pool for these or additional cases to handle freeing
615 static int nvme_setup_discard(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
616 struct request
*req
, struct nvme_command
*cmnd
)
618 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
619 struct nvme_dsm_range
*range
;
621 range
= dma_pool_alloc(nvmeq
->dev
->prp_small_pool
, GFP_ATOMIC
,
624 return BLK_MQ_RQ_QUEUE_BUSY
;
625 iod_list(req
)[0] = (__le64
*)range
;
628 range
->cattr
= cpu_to_le32(0);
629 range
->nlb
= cpu_to_le32(blk_rq_bytes(req
) >> ns
->lba_shift
);
630 range
->slba
= cpu_to_le64(nvme_block_nr(ns
, blk_rq_pos(req
)));
632 memset(cmnd
, 0, sizeof(*cmnd
));
633 cmnd
->dsm
.opcode
= nvme_cmd_dsm
;
634 cmnd
->dsm
.nsid
= cpu_to_le32(ns
->ns_id
);
635 cmnd
->dsm
.prp1
= cpu_to_le64(iod
->first_dma
);
637 cmnd
->dsm
.attributes
= cpu_to_le32(NVME_DSMGMT_AD
);
638 return BLK_MQ_RQ_QUEUE_OK
;
642 * NOTE: ns is NULL when called on the admin queue.
644 static int nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
645 const struct blk_mq_queue_data
*bd
)
647 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
648 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
649 struct nvme_dev
*dev
= nvmeq
->dev
;
650 struct request
*req
= bd
->rq
;
651 struct nvme_command cmnd
;
652 int ret
= BLK_MQ_RQ_QUEUE_OK
;
655 * If formated with metadata, require the block layer provide a buffer
656 * unless this namespace is formated such that the metadata can be
657 * stripped/generated by the controller with PRACT=1.
659 if (ns
&& ns
->ms
&& !blk_integrity_rq(req
)) {
660 if (!(ns
->pi_type
&& ns
->ms
== 8) &&
661 req
->cmd_type
!= REQ_TYPE_DRV_PRIV
) {
662 blk_mq_end_request(req
, -EFAULT
);
663 return BLK_MQ_RQ_QUEUE_OK
;
667 ret
= nvme_init_iod(req
, dev
);
671 if (req
->cmd_flags
& REQ_DISCARD
) {
672 ret
= nvme_setup_discard(nvmeq
, ns
, req
, &cmnd
);
674 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
)
675 memcpy(&cmnd
, req
->cmd
, sizeof(cmnd
));
676 else if (req
->cmd_flags
& REQ_FLUSH
)
677 nvme_setup_flush(ns
, &cmnd
);
679 nvme_setup_rw(ns
, req
, &cmnd
);
681 if (req
->nr_phys_segments
)
682 ret
= nvme_map_data(dev
, req
, &cmnd
);
688 cmnd
.common
.command_id
= req
->tag
;
689 blk_mq_start_request(req
);
691 spin_lock_irq(&nvmeq
->q_lock
);
692 if (unlikely(nvmeq
->cq_vector
< 0)) {
693 ret
= BLK_MQ_RQ_QUEUE_BUSY
;
694 spin_unlock_irq(&nvmeq
->q_lock
);
697 __nvme_submit_cmd(nvmeq
, &cmnd
);
698 nvme_process_cq(nvmeq
);
699 spin_unlock_irq(&nvmeq
->q_lock
);
700 return BLK_MQ_RQ_QUEUE_OK
;
702 nvme_free_iod(dev
, req
);
706 static void nvme_complete_rq(struct request
*req
)
708 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
709 struct nvme_dev
*dev
= iod
->nvmeq
->dev
;
712 nvme_unmap_data(dev
, req
);
714 if (unlikely(req
->errors
)) {
715 if (nvme_req_needs_retry(req
, req
->errors
)) {
716 nvme_requeue_req(req
);
720 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
)
723 error
= nvme_error_status(req
->errors
);
726 if (unlikely(iod
->aborted
)) {
728 "completing aborted command with status: %04x\n",
732 blk_mq_end_request(req
, error
);
735 static void __nvme_process_cq(struct nvme_queue
*nvmeq
, unsigned int *tag
)
739 head
= nvmeq
->cq_head
;
740 phase
= nvmeq
->cq_phase
;
743 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
744 u16 status
= le16_to_cpu(cqe
.status
);
747 if ((status
& 1) != phase
)
749 nvmeq
->sq_head
= le16_to_cpu(cqe
.sq_head
);
750 if (++head
== nvmeq
->q_depth
) {
755 if (tag
&& *tag
== cqe
.command_id
)
758 if (unlikely(cqe
.command_id
>= nvmeq
->q_depth
)) {
759 dev_warn(nvmeq
->q_dmadev
,
760 "invalid id %d completed on queue %d\n",
761 cqe
.command_id
, le16_to_cpu(cqe
.sq_id
));
766 * AEN requests are special as they don't time out and can
767 * survive any kind of queue freeze and often don't respond to
768 * aborts. We don't even bother to allocate a struct request
769 * for them but rather special case them here.
771 if (unlikely(nvmeq
->qid
== 0 &&
772 cqe
.command_id
>= NVME_AQ_BLKMQ_DEPTH
)) {
773 nvme_complete_async_event(nvmeq
->dev
, &cqe
);
777 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
.command_id
);
778 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
) {
779 u32 result
= le32_to_cpu(cqe
.result
);
780 req
->special
= (void *)(uintptr_t)result
;
782 blk_mq_complete_request(req
, status
>> 1);
786 /* If the controller ignores the cq head doorbell and continuously
787 * writes to the queue, it is theoretically possible to wrap around
788 * the queue twice and mistakenly return IRQ_NONE. Linux only
789 * requires that 0.1% of your interrupts are handled, so this isn't
792 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
795 if (likely(nvmeq
->cq_vector
>= 0))
796 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
797 nvmeq
->cq_head
= head
;
798 nvmeq
->cq_phase
= phase
;
803 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
805 __nvme_process_cq(nvmeq
, NULL
);
808 static irqreturn_t
nvme_irq(int irq
, void *data
)
811 struct nvme_queue
*nvmeq
= data
;
812 spin_lock(&nvmeq
->q_lock
);
813 nvme_process_cq(nvmeq
);
814 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
816 spin_unlock(&nvmeq
->q_lock
);
820 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
822 struct nvme_queue
*nvmeq
= data
;
823 struct nvme_completion cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
824 if ((le16_to_cpu(cqe
.status
) & 1) != nvmeq
->cq_phase
)
826 return IRQ_WAKE_THREAD
;
829 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
831 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
833 if ((le16_to_cpu(nvmeq
->cqes
[nvmeq
->cq_head
].status
) & 1) ==
835 spin_lock_irq(&nvmeq
->q_lock
);
836 __nvme_process_cq(nvmeq
, &tag
);
837 spin_unlock_irq(&nvmeq
->q_lock
);
846 static void nvme_submit_async_event(struct nvme_dev
*dev
)
848 struct nvme_command c
;
850 memset(&c
, 0, sizeof(c
));
851 c
.common
.opcode
= nvme_admin_async_event
;
852 c
.common
.command_id
= NVME_AQ_BLKMQ_DEPTH
+ --dev
->ctrl
.event_limit
;
854 __nvme_submit_cmd(dev
->queues
[0], &c
);
857 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
859 struct nvme_command c
;
861 memset(&c
, 0, sizeof(c
));
862 c
.delete_queue
.opcode
= opcode
;
863 c
.delete_queue
.qid
= cpu_to_le16(id
);
865 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
868 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
869 struct nvme_queue
*nvmeq
)
871 struct nvme_command c
;
872 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
875 * Note: we (ab)use the fact the the prp fields survive if no data
876 * is attached to the request.
878 memset(&c
, 0, sizeof(c
));
879 c
.create_cq
.opcode
= nvme_admin_create_cq
;
880 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
881 c
.create_cq
.cqid
= cpu_to_le16(qid
);
882 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
883 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
884 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
886 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
889 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
890 struct nvme_queue
*nvmeq
)
892 struct nvme_command c
;
893 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
896 * Note: we (ab)use the fact the the prp fields survive if no data
897 * is attached to the request.
899 memset(&c
, 0, sizeof(c
));
900 c
.create_sq
.opcode
= nvme_admin_create_sq
;
901 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
902 c
.create_sq
.sqid
= cpu_to_le16(qid
);
903 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
904 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
905 c
.create_sq
.cqid
= cpu_to_le16(qid
);
907 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
910 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
912 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
915 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
917 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
920 static void abort_endio(struct request
*req
, int error
)
922 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
923 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
924 u32 result
= (u32
)(uintptr_t)req
->special
;
925 u16 status
= req
->errors
;
927 dev_warn(nvmeq
->q_dmadev
, "Abort status:%x result:%x", status
, result
);
928 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
930 blk_mq_free_request(req
);
933 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
935 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
936 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
937 struct nvme_dev
*dev
= nvmeq
->dev
;
938 struct request
*abort_req
;
939 struct nvme_command cmd
;
942 * Shutdown immediately if controller times out while starting. The
943 * reset work will see the pci device disabled when it gets the forced
944 * cancellation error. All outstanding requests are completed on
945 * shutdown, so we return BLK_EH_HANDLED.
947 if (test_bit(NVME_CTRL_RESETTING
, &dev
->flags
)) {
949 "I/O %d QID %d timeout, disable controller\n",
950 req
->tag
, nvmeq
->qid
);
951 nvme_dev_disable(dev
, false);
952 req
->errors
= NVME_SC_CANCELLED
;
953 return BLK_EH_HANDLED
;
957 * Shutdown the controller immediately and schedule a reset if the
958 * command was already aborted once before and still hasn't been
959 * returned to the driver, or if this is the admin queue.
961 if (!nvmeq
->qid
|| iod
->aborted
) {
963 "I/O %d QID %d timeout, reset controller\n",
964 req
->tag
, nvmeq
->qid
);
965 nvme_dev_disable(dev
, false);
966 queue_work(nvme_workq
, &dev
->reset_work
);
969 * Mark the request as handled, since the inline shutdown
970 * forces all outstanding requests to complete.
972 req
->errors
= NVME_SC_CANCELLED
;
973 return BLK_EH_HANDLED
;
978 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
979 atomic_inc(&dev
->ctrl
.abort_limit
);
980 return BLK_EH_RESET_TIMER
;
983 memset(&cmd
, 0, sizeof(cmd
));
984 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
985 cmd
.abort
.cid
= req
->tag
;
986 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
988 dev_warn(nvmeq
->q_dmadev
, "I/O %d QID %d timeout, aborting\n",
989 req
->tag
, nvmeq
->qid
);
991 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
993 if (IS_ERR(abort_req
)) {
994 atomic_inc(&dev
->ctrl
.abort_limit
);
995 return BLK_EH_RESET_TIMER
;
998 abort_req
->timeout
= ADMIN_TIMEOUT
;
999 abort_req
->end_io_data
= NULL
;
1000 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
1003 * The aborted req will be completed on receiving the abort req.
1004 * We enable the timer again. If hit twice, it'll cause a device reset,
1005 * as the device then is in a faulty state.
1007 return BLK_EH_RESET_TIMER
;
1010 static void nvme_cancel_queue_ios(struct request
*req
, void *data
, bool reserved
)
1012 struct nvme_queue
*nvmeq
= data
;
1015 if (!blk_mq_request_started(req
))
1018 dev_dbg_ratelimited(nvmeq
->q_dmadev
,
1019 "Cancelling I/O %d QID %d\n", req
->tag
, nvmeq
->qid
);
1021 status
= NVME_SC_ABORT_REQ
;
1022 if (blk_queue_dying(req
->q
))
1023 status
|= NVME_SC_DNR
;
1024 blk_mq_complete_request(req
, status
);
1027 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1029 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1030 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1032 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1033 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1037 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1041 for (i
= dev
->queue_count
- 1; i
>= lowest
; i
--) {
1042 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1044 dev
->queues
[i
] = NULL
;
1045 nvme_free_queue(nvmeq
);
1050 * nvme_suspend_queue - put queue into suspended state
1051 * @nvmeq - queue to suspend
1053 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1057 spin_lock_irq(&nvmeq
->q_lock
);
1058 if (nvmeq
->cq_vector
== -1) {
1059 spin_unlock_irq(&nvmeq
->q_lock
);
1062 vector
= nvmeq
->dev
->entry
[nvmeq
->cq_vector
].vector
;
1063 nvmeq
->dev
->online_queues
--;
1064 nvmeq
->cq_vector
= -1;
1065 spin_unlock_irq(&nvmeq
->q_lock
);
1067 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1068 blk_mq_stop_hw_queues(nvmeq
->dev
->ctrl
.admin_q
);
1070 irq_set_affinity_hint(vector
, NULL
);
1071 free_irq(vector
, nvmeq
);
1076 static void nvme_clear_queue(struct nvme_queue
*nvmeq
)
1078 spin_lock_irq(&nvmeq
->q_lock
);
1079 if (nvmeq
->tags
&& *nvmeq
->tags
)
1080 blk_mq_all_tag_busy_iter(*nvmeq
->tags
, nvme_cancel_queue_ios
, nvmeq
);
1081 spin_unlock_irq(&nvmeq
->q_lock
);
1084 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
1086 struct nvme_queue
*nvmeq
= dev
->queues
[0];
1090 if (nvme_suspend_queue(nvmeq
))
1094 nvme_shutdown_ctrl(&dev
->ctrl
);
1096 nvme_disable_ctrl(&dev
->ctrl
, lo_hi_readq(
1097 dev
->bar
+ NVME_REG_CAP
));
1099 spin_lock_irq(&nvmeq
->q_lock
);
1100 nvme_process_cq(nvmeq
);
1101 spin_unlock_irq(&nvmeq
->q_lock
);
1104 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1107 int q_depth
= dev
->q_depth
;
1108 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1109 dev
->ctrl
.page_size
);
1111 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1112 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1113 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1114 q_depth
= div_u64(mem_per_q
, entry_size
);
1117 * Ensure the reduced q_depth is above some threshold where it
1118 * would be better to map queues in system memory with the
1128 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1131 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1132 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(depth
),
1133 dev
->ctrl
.page_size
);
1134 nvmeq
->sq_dma_addr
= dev
->cmb_dma_addr
+ offset
;
1135 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1137 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1138 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1139 if (!nvmeq
->sq_cmds
)
1146 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1149 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
), GFP_KERNEL
);
1153 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1154 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1158 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1161 nvmeq
->q_dmadev
= dev
->dev
;
1163 snprintf(nvmeq
->irqname
, sizeof(nvmeq
->irqname
), "nvme%dq%d",
1164 dev
->ctrl
.instance
, qid
);
1165 spin_lock_init(&nvmeq
->q_lock
);
1167 nvmeq
->cq_phase
= 1;
1168 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1169 nvmeq
->q_depth
= depth
;
1171 nvmeq
->cq_vector
= -1;
1172 dev
->queues
[qid
] = nvmeq
;
1174 /* make sure queue descriptor is set before queue count, for kthread */
1181 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1182 nvmeq
->cq_dma_addr
);
1188 static int queue_request_irq(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1191 if (use_threaded_interrupts
)
1192 return request_threaded_irq(dev
->entry
[nvmeq
->cq_vector
].vector
,
1193 nvme_irq_check
, nvme_irq
, IRQF_SHARED
,
1195 return request_irq(dev
->entry
[nvmeq
->cq_vector
].vector
, nvme_irq
,
1196 IRQF_SHARED
, name
, nvmeq
);
1199 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1201 struct nvme_dev
*dev
= nvmeq
->dev
;
1203 spin_lock_irq(&nvmeq
->q_lock
);
1206 nvmeq
->cq_phase
= 1;
1207 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1208 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1209 dev
->online_queues
++;
1210 spin_unlock_irq(&nvmeq
->q_lock
);
1213 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1215 struct nvme_dev
*dev
= nvmeq
->dev
;
1218 nvmeq
->cq_vector
= qid
- 1;
1219 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1223 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1227 result
= queue_request_irq(dev
, nvmeq
, nvmeq
->irqname
);
1231 nvme_init_queue(nvmeq
, qid
);
1235 adapter_delete_sq(dev
, qid
);
1237 adapter_delete_cq(dev
, qid
);
1241 static struct blk_mq_ops nvme_mq_admin_ops
= {
1242 .queue_rq
= nvme_queue_rq
,
1243 .complete
= nvme_complete_rq
,
1244 .map_queue
= blk_mq_map_queue
,
1245 .init_hctx
= nvme_admin_init_hctx
,
1246 .exit_hctx
= nvme_admin_exit_hctx
,
1247 .init_request
= nvme_admin_init_request
,
1248 .timeout
= nvme_timeout
,
1251 static struct blk_mq_ops nvme_mq_ops
= {
1252 .queue_rq
= nvme_queue_rq
,
1253 .complete
= nvme_complete_rq
,
1254 .map_queue
= blk_mq_map_queue
,
1255 .init_hctx
= nvme_init_hctx
,
1256 .init_request
= nvme_init_request
,
1257 .timeout
= nvme_timeout
,
1261 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1263 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1264 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1265 blk_mq_free_tag_set(&dev
->admin_tagset
);
1269 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1271 if (!dev
->ctrl
.admin_q
) {
1272 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1273 dev
->admin_tagset
.nr_hw_queues
= 1;
1276 * Subtract one to leave an empty queue entry for 'Full Queue'
1277 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1279 dev
->admin_tagset
.queue_depth
= NVME_AQ_BLKMQ_DEPTH
- 1;
1280 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1281 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1282 dev
->admin_tagset
.cmd_size
= nvme_cmd_size(dev
);
1283 dev
->admin_tagset
.driver_data
= dev
;
1285 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1288 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1289 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1290 blk_mq_free_tag_set(&dev
->admin_tagset
);
1293 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1294 nvme_dev_remove_admin(dev
);
1295 dev
->ctrl
.admin_q
= NULL
;
1299 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1304 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1308 u64 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1309 struct nvme_queue
*nvmeq
;
1311 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1) ?
1312 NVME_CAP_NSSRC(cap
) : 0;
1314 if (dev
->subsystem
&&
1315 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1316 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1318 result
= nvme_disable_ctrl(&dev
->ctrl
, cap
);
1322 nvmeq
= dev
->queues
[0];
1324 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
);
1329 aqa
= nvmeq
->q_depth
- 1;
1332 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1333 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1334 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1336 result
= nvme_enable_ctrl(&dev
->ctrl
, cap
);
1340 nvmeq
->cq_vector
= 0;
1341 result
= queue_request_irq(dev
, nvmeq
, nvmeq
->irqname
);
1343 nvmeq
->cq_vector
= -1;
1350 nvme_free_queues(dev
, 0);
1354 static int nvme_kthread(void *data
)
1356 struct nvme_dev
*dev
, *next
;
1358 while (!kthread_should_stop()) {
1359 set_current_state(TASK_INTERRUPTIBLE
);
1360 spin_lock(&dev_list_lock
);
1361 list_for_each_entry_safe(dev
, next
, &dev_list
, node
) {
1363 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1366 * Skip controllers currently under reset.
1368 if (work_pending(&dev
->reset_work
) || work_busy(&dev
->reset_work
))
1371 if ((dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
)) ||
1372 csts
& NVME_CSTS_CFS
) {
1373 if (queue_work(nvme_workq
, &dev
->reset_work
)) {
1375 "Failed status: %x, reset controller\n",
1376 readl(dev
->bar
+ NVME_REG_CSTS
));
1380 for (i
= 0; i
< dev
->queue_count
; i
++) {
1381 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1384 spin_lock_irq(&nvmeq
->q_lock
);
1385 nvme_process_cq(nvmeq
);
1387 while (i
== 0 && dev
->ctrl
.event_limit
> 0)
1388 nvme_submit_async_event(dev
);
1389 spin_unlock_irq(&nvmeq
->q_lock
);
1392 spin_unlock(&dev_list_lock
);
1393 schedule_timeout(round_jiffies_relative(HZ
));
1398 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1403 for (i
= dev
->queue_count
; i
<= dev
->max_qid
; i
++) {
1404 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
)) {
1410 for (i
= dev
->online_queues
; i
<= dev
->queue_count
- 1; i
++) {
1411 ret
= nvme_create_queue(dev
->queues
[i
], i
);
1413 nvme_free_queues(dev
, i
);
1419 * Ignore failing Create SQ/CQ commands, we can continue with less
1420 * than the desired aount of queues, and even a controller without
1421 * I/O queues an still be used to issue admin commands. This might
1422 * be useful to upgrade a buggy firmware for example.
1424 return ret
>= 0 ? 0 : ret
;
1427 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1429 u64 szu
, size
, offset
;
1431 resource_size_t bar_size
;
1432 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1434 dma_addr_t dma_addr
;
1439 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1440 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1443 cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1445 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1446 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1447 offset
= szu
* NVME_CMB_OFST(cmbloc
);
1448 bar_size
= pci_resource_len(pdev
, NVME_CMB_BIR(cmbloc
));
1450 if (offset
> bar_size
)
1454 * Controllers may support a CMB size larger than their BAR,
1455 * for example, due to being behind a bridge. Reduce the CMB to
1456 * the reported size of the BAR
1458 if (size
> bar_size
- offset
)
1459 size
= bar_size
- offset
;
1461 dma_addr
= pci_resource_start(pdev
, NVME_CMB_BIR(cmbloc
)) + offset
;
1462 cmb
= ioremap_wc(dma_addr
, size
);
1466 dev
->cmb_dma_addr
= dma_addr
;
1467 dev
->cmb_size
= size
;
1471 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1479 static size_t db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1481 return 4096 + ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1484 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1486 struct nvme_queue
*adminq
= dev
->queues
[0];
1487 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1488 int result
, i
, vecs
, nr_io_queues
, size
;
1490 nr_io_queues
= num_possible_cpus();
1491 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1496 * Degraded controllers might return an error when setting the queue
1497 * count. We still want to be able to bring them online and offer
1498 * access to the admin queue, as that might be only way to fix them up.
1501 dev_err(dev
->dev
, "Could not set queue count (%d)\n", result
);
1506 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1507 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1508 sizeof(struct nvme_command
));
1510 dev
->q_depth
= result
;
1512 nvme_release_cmb(dev
);
1515 size
= db_bar_size(dev
, nr_io_queues
);
1519 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1522 if (!--nr_io_queues
)
1524 size
= db_bar_size(dev
, nr_io_queues
);
1526 dev
->dbs
= dev
->bar
+ 4096;
1527 adminq
->q_db
= dev
->dbs
;
1530 /* Deregister the admin queue's interrupt */
1531 free_irq(dev
->entry
[0].vector
, adminq
);
1534 * If we enable msix early due to not intx, disable it again before
1535 * setting up the full range we need.
1538 pci_disable_msix(pdev
);
1540 for (i
= 0; i
< nr_io_queues
; i
++)
1541 dev
->entry
[i
].entry
= i
;
1542 vecs
= pci_enable_msix_range(pdev
, dev
->entry
, 1, nr_io_queues
);
1544 vecs
= pci_enable_msi_range(pdev
, 1, min(nr_io_queues
, 32));
1548 for (i
= 0; i
< vecs
; i
++)
1549 dev
->entry
[i
].vector
= i
+ pdev
->irq
;
1554 * Should investigate if there's a performance win from allocating
1555 * more queues than interrupt vectors; it might allow the submission
1556 * path to scale better, even if the receive path is limited by the
1557 * number of interrupts.
1559 nr_io_queues
= vecs
;
1560 dev
->max_qid
= nr_io_queues
;
1562 result
= queue_request_irq(dev
, adminq
, adminq
->irqname
);
1564 adminq
->cq_vector
= -1;
1568 /* Free previously allocated queues that are no longer usable */
1569 nvme_free_queues(dev
, nr_io_queues
+ 1);
1570 return nvme_create_io_queues(dev
);
1573 nvme_free_queues(dev
, 1);
1577 static void nvme_set_irq_hints(struct nvme_dev
*dev
)
1579 struct nvme_queue
*nvmeq
;
1582 for (i
= 0; i
< dev
->online_queues
; i
++) {
1583 nvmeq
= dev
->queues
[i
];
1585 if (!nvmeq
->tags
|| !(*nvmeq
->tags
))
1588 irq_set_affinity_hint(dev
->entry
[nvmeq
->cq_vector
].vector
,
1589 blk_mq_tags_cpumask(*nvmeq
->tags
));
1593 static void nvme_dev_scan(struct work_struct
*work
)
1595 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, scan_work
);
1597 if (!dev
->tagset
.tags
)
1599 nvme_scan_namespaces(&dev
->ctrl
);
1600 nvme_set_irq_hints(dev
);
1603 static void nvme_del_queue_end(struct request
*req
, int error
)
1605 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1607 blk_mq_free_request(req
);
1608 complete(&nvmeq
->dev
->ioq_wait
);
1611 static void nvme_del_cq_end(struct request
*req
, int error
)
1613 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1616 unsigned long flags
;
1618 spin_lock_irqsave(&nvmeq
->q_lock
, flags
);
1619 nvme_process_cq(nvmeq
);
1620 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
1623 nvme_del_queue_end(req
, error
);
1626 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
1628 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
1629 struct request
*req
;
1630 struct nvme_command cmd
;
1632 memset(&cmd
, 0, sizeof(cmd
));
1633 cmd
.delete_queue
.opcode
= opcode
;
1634 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
1636 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
);
1638 return PTR_ERR(req
);
1640 req
->timeout
= ADMIN_TIMEOUT
;
1641 req
->end_io_data
= nvmeq
;
1643 blk_execute_rq_nowait(q
, NULL
, req
, false,
1644 opcode
== nvme_admin_delete_cq
?
1645 nvme_del_cq_end
: nvme_del_queue_end
);
1649 static void nvme_disable_io_queues(struct nvme_dev
*dev
)
1652 unsigned long timeout
;
1653 u8 opcode
= nvme_admin_delete_sq
;
1655 for (pass
= 0; pass
< 2; pass
++) {
1656 int sent
= 0, i
= dev
->queue_count
- 1;
1658 reinit_completion(&dev
->ioq_wait
);
1660 timeout
= ADMIN_TIMEOUT
;
1661 for (; i
> 0; i
--) {
1662 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1665 nvme_suspend_queue(nvmeq
);
1666 if (nvme_delete_queue(nvmeq
, opcode
))
1671 timeout
= wait_for_completion_io_timeout(&dev
->ioq_wait
, timeout
);
1677 opcode
= nvme_admin_delete_cq
;
1682 * Return: error value if an error occurred setting up the queues or calling
1683 * Identify Device. 0 if these succeeded, even if adding some of the
1684 * namespaces failed. At the moment, these failures are silent. TBD which
1685 * failures should be reported.
1687 static int nvme_dev_add(struct nvme_dev
*dev
)
1689 if (!dev
->ctrl
.tagset
) {
1690 dev
->tagset
.ops
= &nvme_mq_ops
;
1691 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
1692 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
1693 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
1694 dev
->tagset
.queue_depth
=
1695 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
1696 dev
->tagset
.cmd_size
= nvme_cmd_size(dev
);
1697 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
1698 dev
->tagset
.driver_data
= dev
;
1700 if (blk_mq_alloc_tag_set(&dev
->tagset
))
1702 dev
->ctrl
.tagset
= &dev
->tagset
;
1704 nvme_queue_scan(dev
);
1708 static int nvme_pci_enable(struct nvme_dev
*dev
)
1711 int result
= -ENOMEM
;
1712 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1714 if (pci_enable_device_mem(pdev
))
1717 dev
->entry
[0].vector
= pdev
->irq
;
1718 pci_set_master(pdev
);
1720 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
1721 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
1724 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
1730 * Some devices don't advertse INTx interrupts, pre-enable a single
1731 * MSIX vec for setup. We'll adjust this later.
1734 result
= pci_enable_msix(pdev
, dev
->entry
, 1);
1739 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1741 dev
->q_depth
= min_t(int, NVME_CAP_MQES(cap
) + 1, NVME_Q_DEPTH
);
1742 dev
->db_stride
= 1 << NVME_CAP_STRIDE(cap
);
1743 dev
->dbs
= dev
->bar
+ 4096;
1746 * Temporary fix for the Apple controller found in the MacBook8,1 and
1747 * some MacBook7,1 to avoid controller resets and data loss.
1749 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
1751 dev_warn(dev
->dev
, "detected Apple NVMe controller, set "
1752 "queue depth=%u to work around controller resets\n",
1756 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2))
1757 dev
->cmb
= nvme_map_cmb(dev
);
1759 pci_enable_pcie_error_reporting(pdev
);
1760 pci_save_state(pdev
);
1764 pci_disable_device(pdev
);
1768 static void nvme_dev_unmap(struct nvme_dev
*dev
)
1772 pci_release_regions(to_pci_dev(dev
->dev
));
1775 static void nvme_pci_disable(struct nvme_dev
*dev
)
1777 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1779 if (pdev
->msi_enabled
)
1780 pci_disable_msi(pdev
);
1781 else if (pdev
->msix_enabled
)
1782 pci_disable_msix(pdev
);
1784 if (pci_is_enabled(pdev
)) {
1785 pci_disable_pcie_error_reporting(pdev
);
1786 pci_disable_device(pdev
);
1790 static int nvme_dev_list_add(struct nvme_dev
*dev
)
1792 bool start_thread
= false;
1794 spin_lock(&dev_list_lock
);
1795 if (list_empty(&dev_list
) && IS_ERR_OR_NULL(nvme_thread
)) {
1796 start_thread
= true;
1799 list_add(&dev
->node
, &dev_list
);
1800 spin_unlock(&dev_list_lock
);
1803 nvme_thread
= kthread_run(nvme_kthread
, NULL
, "nvme");
1804 wake_up_all(&nvme_kthread_wait
);
1806 wait_event_killable(nvme_kthread_wait
, nvme_thread
);
1808 if (IS_ERR_OR_NULL(nvme_thread
))
1809 return nvme_thread
? PTR_ERR(nvme_thread
) : -EINTR
;
1815 * Remove the node from the device list and check
1816 * for whether or not we need to stop the nvme_thread.
1818 static void nvme_dev_list_remove(struct nvme_dev
*dev
)
1820 struct task_struct
*tmp
= NULL
;
1822 spin_lock(&dev_list_lock
);
1823 list_del_init(&dev
->node
);
1824 if (list_empty(&dev_list
) && !IS_ERR_OR_NULL(nvme_thread
)) {
1828 spin_unlock(&dev_list_lock
);
1834 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
1839 nvme_dev_list_remove(dev
);
1841 mutex_lock(&dev
->shutdown_lock
);
1842 if (pci_is_enabled(to_pci_dev(dev
->dev
))) {
1843 nvme_stop_queues(&dev
->ctrl
);
1844 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1846 if (csts
& NVME_CSTS_CFS
|| !(csts
& NVME_CSTS_RDY
)) {
1847 for (i
= dev
->queue_count
- 1; i
>= 0; i
--) {
1848 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1849 nvme_suspend_queue(nvmeq
);
1852 nvme_disable_io_queues(dev
);
1853 nvme_disable_admin_queue(dev
, shutdown
);
1855 nvme_pci_disable(dev
);
1857 for (i
= dev
->queue_count
- 1; i
>= 0; i
--)
1858 nvme_clear_queue(dev
->queues
[i
]);
1859 mutex_unlock(&dev
->shutdown_lock
);
1862 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
1864 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
1865 PAGE_SIZE
, PAGE_SIZE
, 0);
1866 if (!dev
->prp_page_pool
)
1869 /* Optimisation for I/Os between 4k and 128k */
1870 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
1872 if (!dev
->prp_small_pool
) {
1873 dma_pool_destroy(dev
->prp_page_pool
);
1879 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
1881 dma_pool_destroy(dev
->prp_page_pool
);
1882 dma_pool_destroy(dev
->prp_small_pool
);
1885 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
1887 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1889 put_device(dev
->dev
);
1890 if (dev
->tagset
.tags
)
1891 blk_mq_free_tag_set(&dev
->tagset
);
1892 if (dev
->ctrl
.admin_q
)
1893 blk_put_queue(dev
->ctrl
.admin_q
);
1899 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
, int status
)
1901 dev_warn(dev
->dev
, "Removing after probe failure status: %d\n", status
);
1903 kref_get(&dev
->ctrl
.kref
);
1904 if (!schedule_work(&dev
->remove_work
))
1905 nvme_put_ctrl(&dev
->ctrl
);
1908 static void nvme_reset_work(struct work_struct
*work
)
1910 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, reset_work
);
1911 int result
= -ENODEV
;
1913 if (WARN_ON(test_bit(NVME_CTRL_RESETTING
, &dev
->flags
)))
1917 * If we're called to reset a live controller first shut it down before
1920 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
1921 nvme_dev_disable(dev
, false);
1923 set_bit(NVME_CTRL_RESETTING
, &dev
->flags
);
1925 result
= nvme_pci_enable(dev
);
1929 result
= nvme_configure_admin_queue(dev
);
1933 nvme_init_queue(dev
->queues
[0], 0);
1934 result
= nvme_alloc_admin_tags(dev
);
1938 result
= nvme_init_identify(&dev
->ctrl
);
1942 result
= nvme_setup_io_queues(dev
);
1946 dev
->ctrl
.event_limit
= NVME_NR_AEN_COMMANDS
;
1948 result
= nvme_dev_list_add(dev
);
1953 * Keep the controller around but remove all namespaces if we don't have
1954 * any working I/O queue.
1956 if (dev
->online_queues
< 2) {
1957 dev_warn(dev
->dev
, "IO queues not created\n");
1958 nvme_remove_namespaces(&dev
->ctrl
);
1960 nvme_start_queues(&dev
->ctrl
);
1964 clear_bit(NVME_CTRL_RESETTING
, &dev
->flags
);
1968 nvme_remove_dead_ctrl(dev
, result
);
1971 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
1973 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
1974 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1976 if (pci_get_drvdata(pdev
))
1977 pci_stop_and_remove_bus_device_locked(pdev
);
1978 nvme_put_ctrl(&dev
->ctrl
);
1981 static int nvme_reset(struct nvme_dev
*dev
)
1983 if (!dev
->ctrl
.admin_q
|| blk_queue_dying(dev
->ctrl
.admin_q
))
1986 if (!queue_work(nvme_workq
, &dev
->reset_work
))
1989 flush_work(&dev
->reset_work
);
1993 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
1995 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
1999 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2001 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2005 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2007 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
2011 static bool nvme_pci_io_incapable(struct nvme_ctrl
*ctrl
)
2013 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2015 return !dev
->bar
|| dev
->online_queues
< 2;
2018 static int nvme_pci_reset_ctrl(struct nvme_ctrl
*ctrl
)
2020 return nvme_reset(to_nvme_dev(ctrl
));
2023 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2024 .reg_read32
= nvme_pci_reg_read32
,
2025 .reg_write32
= nvme_pci_reg_write32
,
2026 .reg_read64
= nvme_pci_reg_read64
,
2027 .io_incapable
= nvme_pci_io_incapable
,
2028 .reset_ctrl
= nvme_pci_reset_ctrl
,
2029 .free_ctrl
= nvme_pci_free_ctrl
,
2032 static int nvme_dev_map(struct nvme_dev
*dev
)
2035 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2037 bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
2040 if (pci_request_selected_regions(pdev
, bars
, "nvme"))
2043 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
2049 pci_release_regions(pdev
);
2053 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2055 int node
, result
= -ENOMEM
;
2056 struct nvme_dev
*dev
;
2058 node
= dev_to_node(&pdev
->dev
);
2059 if (node
== NUMA_NO_NODE
)
2060 set_dev_node(&pdev
->dev
, 0);
2062 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2065 dev
->entry
= kzalloc_node(num_possible_cpus() * sizeof(*dev
->entry
),
2069 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2074 dev
->dev
= get_device(&pdev
->dev
);
2075 pci_set_drvdata(pdev
, dev
);
2077 result
= nvme_dev_map(dev
);
2081 INIT_LIST_HEAD(&dev
->node
);
2082 INIT_WORK(&dev
->scan_work
, nvme_dev_scan
);
2083 INIT_WORK(&dev
->reset_work
, nvme_reset_work
);
2084 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2085 mutex_init(&dev
->shutdown_lock
);
2086 init_completion(&dev
->ioq_wait
);
2088 result
= nvme_setup_prp_pools(dev
);
2092 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2097 queue_work(nvme_workq
, &dev
->reset_work
);
2101 nvme_release_prp_pools(dev
);
2103 put_device(dev
->dev
);
2104 nvme_dev_unmap(dev
);
2112 static void nvme_reset_notify(struct pci_dev
*pdev
, bool prepare
)
2114 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2117 nvme_dev_disable(dev
, false);
2119 queue_work(nvme_workq
, &dev
->reset_work
);
2122 static void nvme_shutdown(struct pci_dev
*pdev
)
2124 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2125 nvme_dev_disable(dev
, true);
2129 * The driver's remove may be called on a device in a partially initialized
2130 * state. This function must not have any dependencies on the device state in
2133 static void nvme_remove(struct pci_dev
*pdev
)
2135 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2137 set_bit(NVME_CTRL_REMOVING
, &dev
->flags
);
2138 pci_set_drvdata(pdev
, NULL
);
2139 flush_work(&dev
->scan_work
);
2140 nvme_remove_namespaces(&dev
->ctrl
);
2141 nvme_uninit_ctrl(&dev
->ctrl
);
2142 nvme_dev_disable(dev
, true);
2143 flush_work(&dev
->reset_work
);
2144 nvme_dev_remove_admin(dev
);
2145 nvme_free_queues(dev
, 0);
2146 nvme_release_cmb(dev
);
2147 nvme_release_prp_pools(dev
);
2148 nvme_dev_unmap(dev
);
2149 nvme_put_ctrl(&dev
->ctrl
);
2152 #ifdef CONFIG_PM_SLEEP
2153 static int nvme_suspend(struct device
*dev
)
2155 struct pci_dev
*pdev
= to_pci_dev(dev
);
2156 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2158 nvme_dev_disable(ndev
, true);
2162 static int nvme_resume(struct device
*dev
)
2164 struct pci_dev
*pdev
= to_pci_dev(dev
);
2165 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2167 queue_work(nvme_workq
, &ndev
->reset_work
);
2172 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2174 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
2175 pci_channel_state_t state
)
2177 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2180 * A frozen channel requires a reset. When detected, this method will
2181 * shutdown the controller to quiesce. The controller will be restarted
2182 * after the slot reset through driver's slot_reset callback.
2184 dev_warn(&pdev
->dev
, "error detected: state:%d\n", state
);
2186 case pci_channel_io_normal
:
2187 return PCI_ERS_RESULT_CAN_RECOVER
;
2188 case pci_channel_io_frozen
:
2189 nvme_dev_disable(dev
, false);
2190 return PCI_ERS_RESULT_NEED_RESET
;
2191 case pci_channel_io_perm_failure
:
2192 return PCI_ERS_RESULT_DISCONNECT
;
2194 return PCI_ERS_RESULT_NEED_RESET
;
2197 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
2199 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2201 dev_info(&pdev
->dev
, "restart after slot reset\n");
2202 pci_restore_state(pdev
);
2203 queue_work(nvme_workq
, &dev
->reset_work
);
2204 return PCI_ERS_RESULT_RECOVERED
;
2207 static void nvme_error_resume(struct pci_dev
*pdev
)
2209 pci_cleanup_aer_uncorrect_error_status(pdev
);
2212 static const struct pci_error_handlers nvme_err_handler
= {
2213 .error_detected
= nvme_error_detected
,
2214 .slot_reset
= nvme_slot_reset
,
2215 .resume
= nvme_error_resume
,
2216 .reset_notify
= nvme_reset_notify
,
2219 /* Move to pci_ids.h later */
2220 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
2222 static const struct pci_device_id nvme_id_table
[] = {
2223 { PCI_VDEVICE(INTEL
, 0x0953),
2224 .driver_data
= NVME_QUIRK_STRIPE_SIZE
, },
2225 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2226 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2227 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2228 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2231 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2233 static struct pci_driver nvme_driver
= {
2235 .id_table
= nvme_id_table
,
2236 .probe
= nvme_probe
,
2237 .remove
= nvme_remove
,
2238 .shutdown
= nvme_shutdown
,
2240 .pm
= &nvme_dev_pm_ops
,
2242 .err_handler
= &nvme_err_handler
,
2245 static int __init
nvme_init(void)
2249 init_waitqueue_head(&nvme_kthread_wait
);
2251 nvme_workq
= alloc_workqueue("nvme", WQ_UNBOUND
| WQ_MEM_RECLAIM
, 0);
2255 result
= nvme_core_init();
2259 result
= pci_register_driver(&nvme_driver
);
2267 destroy_workqueue(nvme_workq
);
2271 static void __exit
nvme_exit(void)
2273 pci_unregister_driver(&nvme_driver
);
2275 destroy_workqueue(nvme_workq
);
2276 BUG_ON(nvme_thread
&& !IS_ERR(nvme_thread
));
2280 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2281 MODULE_LICENSE("GPL");
2282 MODULE_VERSION("1.0");
2283 module_init(nvme_init
);
2284 module_exit(nvme_exit
);