2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/cpu.h>
20 #include <linux/delay.h>
21 #include <linux/errno.h>
23 #include <linux/genhd.h>
24 #include <linux/hdreg.h>
25 #include <linux/idr.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
29 #include <linux/kdev_t.h>
30 #include <linux/kthread.h>
31 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/mutex.h>
36 #include <linux/pci.h>
37 #include <linux/poison.h>
38 #include <linux/ptrace.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/t10-pi.h>
42 #include <linux/types.h>
43 #include <linux/io-64-nonatomic-lo-hi.h>
44 #include <asm/unaligned.h>
48 #define NVME_Q_DEPTH 1024
49 #define NVME_AQ_DEPTH 256
50 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
51 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
54 * We handle AEN commands ourselves and don't even let the
55 * block layer know about them.
57 #define NVME_NR_AEN_COMMANDS 1
58 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
60 unsigned char admin_timeout
= 60;
61 module_param(admin_timeout
, byte
, 0644);
62 MODULE_PARM_DESC(admin_timeout
, "timeout in seconds for admin commands");
64 unsigned char nvme_io_timeout
= 30;
65 module_param_named(io_timeout
, nvme_io_timeout
, byte
, 0644);
66 MODULE_PARM_DESC(io_timeout
, "timeout in seconds for I/O");
68 unsigned char shutdown_timeout
= 5;
69 module_param(shutdown_timeout
, byte
, 0644);
70 MODULE_PARM_DESC(shutdown_timeout
, "timeout in seconds for controller shutdown");
72 static int use_threaded_interrupts
;
73 module_param(use_threaded_interrupts
, int, 0);
75 static bool use_cmb_sqes
= true;
76 module_param(use_cmb_sqes
, bool, 0644);
77 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
79 static LIST_HEAD(dev_list
);
80 static struct task_struct
*nvme_thread
;
81 static struct workqueue_struct
*nvme_workq
;
82 static wait_queue_head_t nvme_kthread_wait
;
87 static int nvme_reset(struct nvme_dev
*dev
);
88 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
89 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
);
90 static void nvme_dev_shutdown(struct nvme_dev
*dev
);
92 struct async_cmd_info
{
93 struct kthread_work work
;
94 struct kthread_worker
*worker
;
100 * Represents an NVM Express device. Each nvme_dev is a PCI function.
103 struct list_head node
;
104 struct nvme_queue
**queues
;
105 struct blk_mq_tag_set tagset
;
106 struct blk_mq_tag_set admin_tagset
;
109 struct dma_pool
*prp_page_pool
;
110 struct dma_pool
*prp_small_pool
;
111 unsigned queue_count
;
112 unsigned online_queues
;
116 struct msix_entry
*entry
;
118 struct work_struct reset_work
;
119 struct work_struct scan_work
;
120 struct work_struct remove_work
;
121 struct mutex shutdown_lock
;
124 dma_addr_t cmb_dma_addr
;
128 #define NVME_CTRL_RESETTING 0
130 struct nvme_ctrl ctrl
;
133 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
135 return container_of(ctrl
, struct nvme_dev
, ctrl
);
139 * An NVM Express queue. Each device has at least two (one for admin
140 * commands and one for I/O commands).
143 struct device
*q_dmadev
;
144 struct nvme_dev
*dev
;
145 char irqname
[24]; /* nvme4294967295-65535\0 */
147 struct nvme_command
*sq_cmds
;
148 struct nvme_command __iomem
*sq_cmds_io
;
149 volatile struct nvme_completion
*cqes
;
150 struct blk_mq_tags
**tags
;
151 dma_addr_t sq_dma_addr
;
152 dma_addr_t cq_dma_addr
;
162 struct async_cmd_info cmdinfo
;
166 * The nvme_iod describes the data in an I/O, including the list of PRP
167 * entries. You can't see it in this data structure because C doesn't let
168 * me express that. Use nvme_init_iod to ensure there's enough space
169 * allocated to store the PRP list.
172 struct nvme_queue
*nvmeq
;
174 int npages
; /* In the PRP list. 0 means small pool in use */
175 int nents
; /* Used in scatterlist */
176 int length
; /* Of data, in bytes */
177 dma_addr_t first_dma
;
178 struct scatterlist meta_sg
; /* metadata requires single contiguous buffer */
179 struct scatterlist
*sg
;
180 struct scatterlist inline_sg
[0];
184 * Check we didin't inadvertently grow the command struct
186 static inline void _nvme_check_size(void)
188 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
189 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
190 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
191 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
192 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
193 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
194 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
195 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
196 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
197 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
198 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
203 * Max size of iod being embedded in the request payload
205 #define NVME_INT_PAGES 2
206 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
209 * Will slightly overestimate the number of pages needed. This is OK
210 * as it only leads to a small amount of wasted memory for the lifetime of
213 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
215 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
216 dev
->ctrl
.page_size
);
217 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
220 static unsigned int nvme_iod_alloc_size(struct nvme_dev
*dev
,
221 unsigned int size
, unsigned int nseg
)
223 return sizeof(__le64
*) * nvme_npages(size
, dev
) +
224 sizeof(struct scatterlist
) * nseg
;
227 static unsigned int nvme_cmd_size(struct nvme_dev
*dev
)
229 return sizeof(struct nvme_iod
) +
230 nvme_iod_alloc_size(dev
, NVME_INT_BYTES(dev
), NVME_INT_PAGES
);
233 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
234 unsigned int hctx_idx
)
236 struct nvme_dev
*dev
= data
;
237 struct nvme_queue
*nvmeq
= dev
->queues
[0];
239 WARN_ON(hctx_idx
!= 0);
240 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
241 WARN_ON(nvmeq
->tags
);
243 hctx
->driver_data
= nvmeq
;
244 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
248 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
250 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
255 static int nvme_admin_init_request(void *data
, struct request
*req
,
256 unsigned int hctx_idx
, unsigned int rq_idx
,
257 unsigned int numa_node
)
259 struct nvme_dev
*dev
= data
;
260 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
261 struct nvme_queue
*nvmeq
= dev
->queues
[0];
268 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
269 unsigned int hctx_idx
)
271 struct nvme_dev
*dev
= data
;
272 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
275 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
277 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
278 hctx
->driver_data
= nvmeq
;
282 static int nvme_init_request(void *data
, struct request
*req
,
283 unsigned int hctx_idx
, unsigned int rq_idx
,
284 unsigned int numa_node
)
286 struct nvme_dev
*dev
= data
;
287 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
288 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
295 static void nvme_complete_async_event(struct nvme_dev
*dev
,
296 struct nvme_completion
*cqe
)
298 u16 status
= le16_to_cpu(cqe
->status
) >> 1;
299 u32 result
= le32_to_cpu(cqe
->result
);
301 if (status
== NVME_SC_SUCCESS
|| status
== NVME_SC_ABORT_REQ
)
302 ++dev
->ctrl
.event_limit
;
303 if (status
!= NVME_SC_SUCCESS
)
306 switch (result
& 0xff07) {
307 case NVME_AER_NOTICE_NS_CHANGED
:
308 dev_info(dev
->dev
, "rescanning\n");
309 queue_work(nvme_workq
, &dev
->scan_work
);
311 dev_warn(dev
->dev
, "async event result %08x\n", result
);
316 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
317 * @nvmeq: The queue to use
318 * @cmd: The command to send
320 * Safe to use from interrupt context
322 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
323 struct nvme_command
*cmd
)
325 u16 tail
= nvmeq
->sq_tail
;
327 if (nvmeq
->sq_cmds_io
)
328 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
330 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
332 if (++tail
== nvmeq
->q_depth
)
334 writel(tail
, nvmeq
->q_db
);
335 nvmeq
->sq_tail
= tail
;
338 static __le64
**iod_list(struct request
*req
)
340 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
341 return (__le64
**)(iod
->sg
+ req
->nr_phys_segments
);
344 static int nvme_init_iod(struct request
*rq
, struct nvme_dev
*dev
)
346 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(rq
);
347 int nseg
= rq
->nr_phys_segments
;
350 if (rq
->cmd_flags
& REQ_DISCARD
)
351 size
= sizeof(struct nvme_dsm_range
);
353 size
= blk_rq_bytes(rq
);
355 if (nseg
> NVME_INT_PAGES
|| size
> NVME_INT_BYTES(dev
)) {
356 iod
->sg
= kmalloc(nvme_iod_alloc_size(dev
, size
, nseg
), GFP_ATOMIC
);
358 return BLK_MQ_RQ_QUEUE_BUSY
;
360 iod
->sg
= iod
->inline_sg
;
370 static void nvme_free_iod(struct nvme_dev
*dev
, struct request
*req
)
372 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
373 const int last_prp
= dev
->ctrl
.page_size
/ 8 - 1;
375 __le64
**list
= iod_list(req
);
376 dma_addr_t prp_dma
= iod
->first_dma
;
378 if (iod
->npages
== 0)
379 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
380 for (i
= 0; i
< iod
->npages
; i
++) {
381 __le64
*prp_list
= list
[i
];
382 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
383 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
384 prp_dma
= next_prp_dma
;
387 if (iod
->sg
!= iod
->inline_sg
)
391 #ifdef CONFIG_BLK_DEV_INTEGRITY
392 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
394 if (be32_to_cpu(pi
->ref_tag
) == v
)
395 pi
->ref_tag
= cpu_to_be32(p
);
398 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
400 if (be32_to_cpu(pi
->ref_tag
) == p
)
401 pi
->ref_tag
= cpu_to_be32(v
);
405 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
407 * The virtual start sector is the one that was originally submitted by the
408 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
409 * start sector may be different. Remap protection information to match the
410 * physical LBA on writes, and back to the original seed on reads.
412 * Type 0 and 3 do not have a ref tag, so no remapping required.
414 static void nvme_dif_remap(struct request
*req
,
415 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
417 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
418 struct bio_integrity_payload
*bip
;
419 struct t10_pi_tuple
*pi
;
421 u32 i
, nlb
, ts
, phys
, virt
;
423 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
426 bip
= bio_integrity(req
->bio
);
430 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
433 virt
= bip_get_seed(bip
);
434 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
435 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
436 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
438 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
439 pi
= (struct t10_pi_tuple
*)p
;
440 dif_swap(phys
, virt
, pi
);
445 #else /* CONFIG_BLK_DEV_INTEGRITY */
446 static void nvme_dif_remap(struct request
*req
,
447 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
450 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
453 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
458 static bool nvme_setup_prps(struct nvme_dev
*dev
, struct request
*req
,
461 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
462 struct dma_pool
*pool
;
463 int length
= total_len
;
464 struct scatterlist
*sg
= iod
->sg
;
465 int dma_len
= sg_dma_len(sg
);
466 u64 dma_addr
= sg_dma_address(sg
);
467 u32 page_size
= dev
->ctrl
.page_size
;
468 int offset
= dma_addr
& (page_size
- 1);
470 __le64
**list
= iod_list(req
);
474 length
-= (page_size
- offset
);
478 dma_len
-= (page_size
- offset
);
480 dma_addr
+= (page_size
- offset
);
483 dma_addr
= sg_dma_address(sg
);
484 dma_len
= sg_dma_len(sg
);
487 if (length
<= page_size
) {
488 iod
->first_dma
= dma_addr
;
492 nprps
= DIV_ROUND_UP(length
, page_size
);
493 if (nprps
<= (256 / 8)) {
494 pool
= dev
->prp_small_pool
;
497 pool
= dev
->prp_page_pool
;
501 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
503 iod
->first_dma
= dma_addr
;
508 iod
->first_dma
= prp_dma
;
511 if (i
== page_size
>> 3) {
512 __le64
*old_prp_list
= prp_list
;
513 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
516 list
[iod
->npages
++] = prp_list
;
517 prp_list
[0] = old_prp_list
[i
- 1];
518 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
521 prp_list
[i
++] = cpu_to_le64(dma_addr
);
522 dma_len
-= page_size
;
523 dma_addr
+= page_size
;
531 dma_addr
= sg_dma_address(sg
);
532 dma_len
= sg_dma_len(sg
);
538 static int nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
539 struct nvme_command
*cmnd
)
541 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
542 struct request_queue
*q
= req
->q
;
543 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
544 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
545 int ret
= BLK_MQ_RQ_QUEUE_ERROR
;
547 sg_init_table(iod
->sg
, req
->nr_phys_segments
);
548 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
552 ret
= BLK_MQ_RQ_QUEUE_BUSY
;
553 if (!dma_map_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
))
556 if (!nvme_setup_prps(dev
, req
, blk_rq_bytes(req
)))
559 ret
= BLK_MQ_RQ_QUEUE_ERROR
;
560 if (blk_integrity_rq(req
)) {
561 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
564 sg_init_table(&iod
->meta_sg
, 1);
565 if (blk_rq_map_integrity_sg(q
, req
->bio
, &iod
->meta_sg
) != 1)
568 if (rq_data_dir(req
))
569 nvme_dif_remap(req
, nvme_dif_prep
);
571 if (!dma_map_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
))
575 cmnd
->rw
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
576 cmnd
->rw
.prp2
= cpu_to_le64(iod
->first_dma
);
577 if (blk_integrity_rq(req
))
578 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(&iod
->meta_sg
));
579 return BLK_MQ_RQ_QUEUE_OK
;
582 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
587 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
589 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
590 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
591 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
594 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
595 if (blk_integrity_rq(req
)) {
596 if (!rq_data_dir(req
))
597 nvme_dif_remap(req
, nvme_dif_complete
);
598 dma_unmap_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
);
602 nvme_free_iod(dev
, req
);
606 * We reuse the small pool to allocate the 16-byte range here as it is not
607 * worth having a special pool for these or additional cases to handle freeing
610 static int nvme_setup_discard(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
611 struct request
*req
, struct nvme_command
*cmnd
)
613 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
614 struct nvme_dsm_range
*range
;
616 range
= dma_pool_alloc(nvmeq
->dev
->prp_small_pool
, GFP_ATOMIC
,
619 return BLK_MQ_RQ_QUEUE_BUSY
;
620 iod_list(req
)[0] = (__le64
*)range
;
623 range
->cattr
= cpu_to_le32(0);
624 range
->nlb
= cpu_to_le32(blk_rq_bytes(req
) >> ns
->lba_shift
);
625 range
->slba
= cpu_to_le64(nvme_block_nr(ns
, blk_rq_pos(req
)));
627 memset(cmnd
, 0, sizeof(*cmnd
));
628 cmnd
->dsm
.opcode
= nvme_cmd_dsm
;
629 cmnd
->dsm
.nsid
= cpu_to_le32(ns
->ns_id
);
630 cmnd
->dsm
.prp1
= cpu_to_le64(iod
->first_dma
);
632 cmnd
->dsm
.attributes
= cpu_to_le32(NVME_DSMGMT_AD
);
633 return BLK_MQ_RQ_QUEUE_OK
;
637 * NOTE: ns is NULL when called on the admin queue.
639 static int nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
640 const struct blk_mq_queue_data
*bd
)
642 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
643 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
644 struct nvme_dev
*dev
= nvmeq
->dev
;
645 struct request
*req
= bd
->rq
;
646 struct nvme_command cmnd
;
647 int ret
= BLK_MQ_RQ_QUEUE_OK
;
650 * If formated with metadata, require the block layer provide a buffer
651 * unless this namespace is formated such that the metadata can be
652 * stripped/generated by the controller with PRACT=1.
654 if (ns
&& ns
->ms
&& !blk_integrity_rq(req
)) {
655 if (!(ns
->pi_type
&& ns
->ms
== 8) &&
656 req
->cmd_type
!= REQ_TYPE_DRV_PRIV
) {
657 blk_mq_end_request(req
, -EFAULT
);
658 return BLK_MQ_RQ_QUEUE_OK
;
662 ret
= nvme_init_iod(req
, dev
);
666 if (req
->cmd_flags
& REQ_DISCARD
) {
667 ret
= nvme_setup_discard(nvmeq
, ns
, req
, &cmnd
);
669 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
)
670 memcpy(&cmnd
, req
->cmd
, sizeof(cmnd
));
671 else if (req
->cmd_flags
& REQ_FLUSH
)
672 nvme_setup_flush(ns
, &cmnd
);
674 nvme_setup_rw(ns
, req
, &cmnd
);
676 if (req
->nr_phys_segments
)
677 ret
= nvme_map_data(dev
, req
, &cmnd
);
683 cmnd
.common
.command_id
= req
->tag
;
684 blk_mq_start_request(req
);
686 spin_lock_irq(&nvmeq
->q_lock
);
687 __nvme_submit_cmd(nvmeq
, &cmnd
);
688 nvme_process_cq(nvmeq
);
689 spin_unlock_irq(&nvmeq
->q_lock
);
690 return BLK_MQ_RQ_QUEUE_OK
;
692 nvme_free_iod(dev
, req
);
696 static void nvme_complete_rq(struct request
*req
)
698 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
699 struct nvme_dev
*dev
= iod
->nvmeq
->dev
;
702 nvme_unmap_data(dev
, req
);
704 if (unlikely(req
->errors
)) {
705 if (nvme_req_needs_retry(req
, req
->errors
)) {
706 nvme_requeue_req(req
);
710 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
)
713 error
= nvme_error_status(req
->errors
);
716 if (unlikely(iod
->aborted
)) {
718 "completing aborted command with status: %04x\n",
722 blk_mq_end_request(req
, error
);
725 static void __nvme_process_cq(struct nvme_queue
*nvmeq
, unsigned int *tag
)
729 head
= nvmeq
->cq_head
;
730 phase
= nvmeq
->cq_phase
;
733 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
734 u16 status
= le16_to_cpu(cqe
.status
);
737 if ((status
& 1) != phase
)
739 nvmeq
->sq_head
= le16_to_cpu(cqe
.sq_head
);
740 if (++head
== nvmeq
->q_depth
) {
745 if (tag
&& *tag
== cqe
.command_id
)
748 if (unlikely(cqe
.command_id
>= nvmeq
->q_depth
)) {
749 dev_warn(nvmeq
->q_dmadev
,
750 "invalid id %d completed on queue %d\n",
751 cqe
.command_id
, le16_to_cpu(cqe
.sq_id
));
756 * AEN requests are special as they don't time out and can
757 * survive any kind of queue freeze and often don't respond to
758 * aborts. We don't even bother to allocate a struct request
759 * for them but rather special case them here.
761 if (unlikely(nvmeq
->qid
== 0 &&
762 cqe
.command_id
>= NVME_AQ_BLKMQ_DEPTH
)) {
763 nvme_complete_async_event(nvmeq
->dev
, &cqe
);
767 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
.command_id
);
768 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
) {
769 u32 result
= le32_to_cpu(cqe
.result
);
770 req
->special
= (void *)(uintptr_t)result
;
772 blk_mq_complete_request(req
, status
>> 1);
776 /* If the controller ignores the cq head doorbell and continuously
777 * writes to the queue, it is theoretically possible to wrap around
778 * the queue twice and mistakenly return IRQ_NONE. Linux only
779 * requires that 0.1% of your interrupts are handled, so this isn't
782 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
785 if (likely(nvmeq
->cq_vector
>= 0))
786 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
787 nvmeq
->cq_head
= head
;
788 nvmeq
->cq_phase
= phase
;
793 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
795 __nvme_process_cq(nvmeq
, NULL
);
798 static irqreturn_t
nvme_irq(int irq
, void *data
)
801 struct nvme_queue
*nvmeq
= data
;
802 spin_lock(&nvmeq
->q_lock
);
803 nvme_process_cq(nvmeq
);
804 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
806 spin_unlock(&nvmeq
->q_lock
);
810 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
812 struct nvme_queue
*nvmeq
= data
;
813 struct nvme_completion cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
814 if ((le16_to_cpu(cqe
.status
) & 1) != nvmeq
->cq_phase
)
816 return IRQ_WAKE_THREAD
;
819 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
821 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
823 if ((le16_to_cpu(nvmeq
->cqes
[nvmeq
->cq_head
].status
) & 1) ==
825 spin_lock_irq(&nvmeq
->q_lock
);
826 __nvme_process_cq(nvmeq
, &tag
);
827 spin_unlock_irq(&nvmeq
->q_lock
);
836 static void nvme_submit_async_event(struct nvme_dev
*dev
)
838 struct nvme_command c
;
840 memset(&c
, 0, sizeof(c
));
841 c
.common
.opcode
= nvme_admin_async_event
;
842 c
.common
.command_id
= NVME_AQ_BLKMQ_DEPTH
+ --dev
->ctrl
.event_limit
;
844 __nvme_submit_cmd(dev
->queues
[0], &c
);
847 static void async_cmd_info_endio(struct request
*req
, int error
)
849 struct async_cmd_info
*cmdinfo
= req
->end_io_data
;
851 cmdinfo
->status
= req
->errors
;
852 queue_kthread_work(cmdinfo
->worker
, &cmdinfo
->work
);
853 blk_mq_free_request(req
);
856 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
858 struct nvme_command c
;
860 memset(&c
, 0, sizeof(c
));
861 c
.delete_queue
.opcode
= opcode
;
862 c
.delete_queue
.qid
= cpu_to_le16(id
);
864 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
867 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
868 struct nvme_queue
*nvmeq
)
870 struct nvme_command c
;
871 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
874 * Note: we (ab)use the fact the the prp fields survive if no data
875 * is attached to the request.
877 memset(&c
, 0, sizeof(c
));
878 c
.create_cq
.opcode
= nvme_admin_create_cq
;
879 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
880 c
.create_cq
.cqid
= cpu_to_le16(qid
);
881 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
882 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
883 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
885 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
888 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
889 struct nvme_queue
*nvmeq
)
891 struct nvme_command c
;
892 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
895 * Note: we (ab)use the fact the the prp fields survive if no data
896 * is attached to the request.
898 memset(&c
, 0, sizeof(c
));
899 c
.create_sq
.opcode
= nvme_admin_create_sq
;
900 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
901 c
.create_sq
.sqid
= cpu_to_le16(qid
);
902 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
903 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
904 c
.create_sq
.cqid
= cpu_to_le16(qid
);
906 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
909 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
911 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
914 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
916 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
919 static void abort_endio(struct request
*req
, int error
)
921 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
922 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
923 u32 result
= (u32
)(uintptr_t)req
->special
;
924 u16 status
= req
->errors
;
926 dev_warn(nvmeq
->q_dmadev
, "Abort status:%x result:%x", status
, result
);
927 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
929 blk_mq_free_request(req
);
932 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
934 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
935 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
936 struct nvme_dev
*dev
= nvmeq
->dev
;
937 struct request
*abort_req
;
938 struct nvme_command cmd
;
941 * Shutdown immediately if controller times out while starting. The
942 * reset work will see the pci device disabled when it gets the forced
943 * cancellation error. All outstanding requests are completed on
944 * shutdown, so we return BLK_EH_HANDLED.
946 if (test_bit(NVME_CTRL_RESETTING
, &dev
->flags
)) {
948 "I/O %d QID %d timeout, disable controller\n",
949 req
->tag
, nvmeq
->qid
);
950 nvme_dev_shutdown(dev
);
951 req
->errors
= NVME_SC_CANCELLED
;
952 return BLK_EH_HANDLED
;
956 * Shutdown the controller immediately and schedule a reset if the
957 * command was already aborted once before and still hasn't been
958 * returned to the driver, or if this is the admin queue.
960 if (!nvmeq
->qid
|| iod
->aborted
) {
962 "I/O %d QID %d timeout, reset controller\n",
963 req
->tag
, nvmeq
->qid
);
964 nvme_dev_shutdown(dev
);
965 queue_work(nvme_workq
, &dev
->reset_work
);
968 * Mark the request as handled, since the inline shutdown
969 * forces all outstanding requests to complete.
971 req
->errors
= NVME_SC_CANCELLED
;
972 return BLK_EH_HANDLED
;
977 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
978 atomic_inc(&dev
->ctrl
.abort_limit
);
979 return BLK_EH_RESET_TIMER
;
982 memset(&cmd
, 0, sizeof(cmd
));
983 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
984 cmd
.abort
.cid
= req
->tag
;
985 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
987 dev_warn(nvmeq
->q_dmadev
, "I/O %d QID %d timeout, aborting\n",
988 req
->tag
, nvmeq
->qid
);
990 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
992 if (IS_ERR(abort_req
)) {
993 atomic_inc(&dev
->ctrl
.abort_limit
);
994 return BLK_EH_RESET_TIMER
;
997 abort_req
->timeout
= ADMIN_TIMEOUT
;
998 abort_req
->end_io_data
= NULL
;
999 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
1002 * The aborted req will be completed on receiving the abort req.
1003 * We enable the timer again. If hit twice, it'll cause a device reset,
1004 * as the device then is in a faulty state.
1006 return BLK_EH_RESET_TIMER
;
1009 static void nvme_cancel_queue_ios(struct request
*req
, void *data
, bool reserved
)
1011 struct nvme_queue
*nvmeq
= data
;
1014 if (!blk_mq_request_started(req
))
1017 dev_warn(nvmeq
->q_dmadev
,
1018 "Cancelling I/O %d QID %d\n", req
->tag
, nvmeq
->qid
);
1020 status
= NVME_SC_CANCELLED
;
1021 if (blk_queue_dying(req
->q
))
1022 status
|= NVME_SC_DNR
;
1023 blk_mq_complete_request(req
, status
);
1026 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1028 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1029 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1031 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1032 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1036 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1040 for (i
= dev
->queue_count
- 1; i
>= lowest
; i
--) {
1041 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1043 dev
->queues
[i
] = NULL
;
1044 nvme_free_queue(nvmeq
);
1049 * nvme_suspend_queue - put queue into suspended state
1050 * @nvmeq - queue to suspend
1052 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1056 spin_lock_irq(&nvmeq
->q_lock
);
1057 if (nvmeq
->cq_vector
== -1) {
1058 spin_unlock_irq(&nvmeq
->q_lock
);
1061 vector
= nvmeq
->dev
->entry
[nvmeq
->cq_vector
].vector
;
1062 nvmeq
->dev
->online_queues
--;
1063 nvmeq
->cq_vector
= -1;
1064 spin_unlock_irq(&nvmeq
->q_lock
);
1066 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1067 blk_mq_freeze_queue_start(nvmeq
->dev
->ctrl
.admin_q
);
1069 irq_set_affinity_hint(vector
, NULL
);
1070 free_irq(vector
, nvmeq
);
1075 static void nvme_clear_queue(struct nvme_queue
*nvmeq
)
1077 spin_lock_irq(&nvmeq
->q_lock
);
1078 if (nvmeq
->tags
&& *nvmeq
->tags
)
1079 blk_mq_all_tag_busy_iter(*nvmeq
->tags
, nvme_cancel_queue_ios
, nvmeq
);
1080 spin_unlock_irq(&nvmeq
->q_lock
);
1083 static void nvme_disable_queue(struct nvme_dev
*dev
, int qid
)
1085 struct nvme_queue
*nvmeq
= dev
->queues
[qid
];
1089 if (nvme_suspend_queue(nvmeq
))
1092 /* Don't tell the adapter to delete the admin queue.
1093 * Don't tell a removed adapter to delete IO queues. */
1094 if (qid
&& readl(dev
->bar
+ NVME_REG_CSTS
) != -1) {
1095 adapter_delete_sq(dev
, qid
);
1096 adapter_delete_cq(dev
, qid
);
1099 spin_lock_irq(&nvmeq
->q_lock
);
1100 nvme_process_cq(nvmeq
);
1101 spin_unlock_irq(&nvmeq
->q_lock
);
1104 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1107 int q_depth
= dev
->q_depth
;
1108 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1109 dev
->ctrl
.page_size
);
1111 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1112 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1113 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1114 q_depth
= div_u64(mem_per_q
, entry_size
);
1117 * Ensure the reduced q_depth is above some threshold where it
1118 * would be better to map queues in system memory with the
1128 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1131 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1132 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(depth
),
1133 dev
->ctrl
.page_size
);
1134 nvmeq
->sq_dma_addr
= dev
->cmb_dma_addr
+ offset
;
1135 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1137 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1138 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1139 if (!nvmeq
->sq_cmds
)
1146 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1149 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
), GFP_KERNEL
);
1153 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1154 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1158 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1161 nvmeq
->q_dmadev
= dev
->dev
;
1163 snprintf(nvmeq
->irqname
, sizeof(nvmeq
->irqname
), "nvme%dq%d",
1164 dev
->ctrl
.instance
, qid
);
1165 spin_lock_init(&nvmeq
->q_lock
);
1167 nvmeq
->cq_phase
= 1;
1168 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1169 nvmeq
->q_depth
= depth
;
1171 nvmeq
->cq_vector
= -1;
1172 dev
->queues
[qid
] = nvmeq
;
1174 /* make sure queue descriptor is set before queue count, for kthread */
1181 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1182 nvmeq
->cq_dma_addr
);
1188 static int queue_request_irq(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1191 if (use_threaded_interrupts
)
1192 return request_threaded_irq(dev
->entry
[nvmeq
->cq_vector
].vector
,
1193 nvme_irq_check
, nvme_irq
, IRQF_SHARED
,
1195 return request_irq(dev
->entry
[nvmeq
->cq_vector
].vector
, nvme_irq
,
1196 IRQF_SHARED
, name
, nvmeq
);
1199 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1201 struct nvme_dev
*dev
= nvmeq
->dev
;
1203 spin_lock_irq(&nvmeq
->q_lock
);
1206 nvmeq
->cq_phase
= 1;
1207 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1208 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1209 dev
->online_queues
++;
1210 spin_unlock_irq(&nvmeq
->q_lock
);
1213 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1215 struct nvme_dev
*dev
= nvmeq
->dev
;
1218 nvmeq
->cq_vector
= qid
- 1;
1219 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1223 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1227 result
= queue_request_irq(dev
, nvmeq
, nvmeq
->irqname
);
1231 nvme_init_queue(nvmeq
, qid
);
1235 adapter_delete_sq(dev
, qid
);
1237 adapter_delete_cq(dev
, qid
);
1241 static struct blk_mq_ops nvme_mq_admin_ops
= {
1242 .queue_rq
= nvme_queue_rq
,
1243 .complete
= nvme_complete_rq
,
1244 .map_queue
= blk_mq_map_queue
,
1245 .init_hctx
= nvme_admin_init_hctx
,
1246 .exit_hctx
= nvme_admin_exit_hctx
,
1247 .init_request
= nvme_admin_init_request
,
1248 .timeout
= nvme_timeout
,
1251 static struct blk_mq_ops nvme_mq_ops
= {
1252 .queue_rq
= nvme_queue_rq
,
1253 .complete
= nvme_complete_rq
,
1254 .map_queue
= blk_mq_map_queue
,
1255 .init_hctx
= nvme_init_hctx
,
1256 .init_request
= nvme_init_request
,
1257 .timeout
= nvme_timeout
,
1261 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1263 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1264 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1265 blk_mq_free_tag_set(&dev
->admin_tagset
);
1269 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1271 if (!dev
->ctrl
.admin_q
) {
1272 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1273 dev
->admin_tagset
.nr_hw_queues
= 1;
1274 dev
->admin_tagset
.queue_depth
= NVME_AQ_BLKMQ_DEPTH
;
1275 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1276 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1277 dev
->admin_tagset
.cmd_size
= nvme_cmd_size(dev
);
1278 dev
->admin_tagset
.driver_data
= dev
;
1280 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1283 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1284 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1285 blk_mq_free_tag_set(&dev
->admin_tagset
);
1288 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1289 nvme_dev_remove_admin(dev
);
1290 dev
->ctrl
.admin_q
= NULL
;
1294 blk_mq_unfreeze_queue(dev
->ctrl
.admin_q
);
1299 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1303 u64 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1304 struct nvme_queue
*nvmeq
;
1306 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1) ?
1307 NVME_CAP_NSSRC(cap
) : 0;
1309 if (dev
->subsystem
&&
1310 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1311 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1313 result
= nvme_disable_ctrl(&dev
->ctrl
, cap
);
1317 nvmeq
= dev
->queues
[0];
1319 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
);
1324 aqa
= nvmeq
->q_depth
- 1;
1327 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1328 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1329 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1331 result
= nvme_enable_ctrl(&dev
->ctrl
, cap
);
1335 nvmeq
->cq_vector
= 0;
1336 result
= queue_request_irq(dev
, nvmeq
, nvmeq
->irqname
);
1338 nvmeq
->cq_vector
= -1;
1345 nvme_free_queues(dev
, 0);
1349 static int nvme_kthread(void *data
)
1351 struct nvme_dev
*dev
, *next
;
1353 while (!kthread_should_stop()) {
1354 set_current_state(TASK_INTERRUPTIBLE
);
1355 spin_lock(&dev_list_lock
);
1356 list_for_each_entry_safe(dev
, next
, &dev_list
, node
) {
1358 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1361 * Skip controllers currently under reset.
1363 if (work_pending(&dev
->reset_work
) || work_busy(&dev
->reset_work
))
1366 if ((dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
)) ||
1367 csts
& NVME_CSTS_CFS
) {
1368 if (queue_work(nvme_workq
, &dev
->reset_work
)) {
1370 "Failed status: %x, reset controller\n",
1371 readl(dev
->bar
+ NVME_REG_CSTS
));
1375 for (i
= 0; i
< dev
->queue_count
; i
++) {
1376 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1379 spin_lock_irq(&nvmeq
->q_lock
);
1380 nvme_process_cq(nvmeq
);
1382 while (i
== 0 && dev
->ctrl
.event_limit
> 0)
1383 nvme_submit_async_event(dev
);
1384 spin_unlock_irq(&nvmeq
->q_lock
);
1387 spin_unlock(&dev_list_lock
);
1388 schedule_timeout(round_jiffies_relative(HZ
));
1393 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1398 for (i
= dev
->queue_count
; i
<= dev
->max_qid
; i
++) {
1399 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
)) {
1405 for (i
= dev
->online_queues
; i
<= dev
->queue_count
- 1; i
++) {
1406 ret
= nvme_create_queue(dev
->queues
[i
], i
);
1408 nvme_free_queues(dev
, i
);
1414 * Ignore failing Create SQ/CQ commands, we can continue with less
1415 * than the desired aount of queues, and even a controller without
1416 * I/O queues an still be used to issue admin commands. This might
1417 * be useful to upgrade a buggy firmware for example.
1419 return ret
>= 0 ? 0 : ret
;
1422 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1424 u64 szu
, size
, offset
;
1426 resource_size_t bar_size
;
1427 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1429 dma_addr_t dma_addr
;
1434 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1435 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1438 cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1440 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1441 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1442 offset
= szu
* NVME_CMB_OFST(cmbloc
);
1443 bar_size
= pci_resource_len(pdev
, NVME_CMB_BIR(cmbloc
));
1445 if (offset
> bar_size
)
1449 * Controllers may support a CMB size larger than their BAR,
1450 * for example, due to being behind a bridge. Reduce the CMB to
1451 * the reported size of the BAR
1453 if (size
> bar_size
- offset
)
1454 size
= bar_size
- offset
;
1456 dma_addr
= pci_resource_start(pdev
, NVME_CMB_BIR(cmbloc
)) + offset
;
1457 cmb
= ioremap_wc(dma_addr
, size
);
1461 dev
->cmb_dma_addr
= dma_addr
;
1462 dev
->cmb_size
= size
;
1466 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1474 static size_t db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1476 return 4096 + ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1479 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1481 struct nvme_queue
*adminq
= dev
->queues
[0];
1482 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1483 int result
, i
, vecs
, nr_io_queues
, size
;
1485 nr_io_queues
= num_possible_cpus();
1486 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1491 * Degraded controllers might return an error when setting the queue
1492 * count. We still want to be able to bring them online and offer
1493 * access to the admin queue, as that might be only way to fix them up.
1496 dev_err(dev
->dev
, "Could not set queue count (%d)\n", result
);
1501 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1502 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1503 sizeof(struct nvme_command
));
1505 dev
->q_depth
= result
;
1507 nvme_release_cmb(dev
);
1510 size
= db_bar_size(dev
, nr_io_queues
);
1514 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1517 if (!--nr_io_queues
)
1519 size
= db_bar_size(dev
, nr_io_queues
);
1521 dev
->dbs
= dev
->bar
+ 4096;
1522 adminq
->q_db
= dev
->dbs
;
1525 /* Deregister the admin queue's interrupt */
1526 free_irq(dev
->entry
[0].vector
, adminq
);
1529 * If we enable msix early due to not intx, disable it again before
1530 * setting up the full range we need.
1533 pci_disable_msix(pdev
);
1535 for (i
= 0; i
< nr_io_queues
; i
++)
1536 dev
->entry
[i
].entry
= i
;
1537 vecs
= pci_enable_msix_range(pdev
, dev
->entry
, 1, nr_io_queues
);
1539 vecs
= pci_enable_msi_range(pdev
, 1, min(nr_io_queues
, 32));
1543 for (i
= 0; i
< vecs
; i
++)
1544 dev
->entry
[i
].vector
= i
+ pdev
->irq
;
1549 * Should investigate if there's a performance win from allocating
1550 * more queues than interrupt vectors; it might allow the submission
1551 * path to scale better, even if the receive path is limited by the
1552 * number of interrupts.
1554 nr_io_queues
= vecs
;
1555 dev
->max_qid
= nr_io_queues
;
1557 result
= queue_request_irq(dev
, adminq
, adminq
->irqname
);
1559 adminq
->cq_vector
= -1;
1563 /* Free previously allocated queues that are no longer usable */
1564 nvme_free_queues(dev
, nr_io_queues
+ 1);
1565 return nvme_create_io_queues(dev
);
1568 nvme_free_queues(dev
, 1);
1572 static void nvme_set_irq_hints(struct nvme_dev
*dev
)
1574 struct nvme_queue
*nvmeq
;
1577 for (i
= 0; i
< dev
->online_queues
; i
++) {
1578 nvmeq
= dev
->queues
[i
];
1580 if (!nvmeq
->tags
|| !(*nvmeq
->tags
))
1583 irq_set_affinity_hint(dev
->entry
[nvmeq
->cq_vector
].vector
,
1584 blk_mq_tags_cpumask(*nvmeq
->tags
));
1588 static void nvme_dev_scan(struct work_struct
*work
)
1590 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, scan_work
);
1592 if (!dev
->tagset
.tags
)
1594 nvme_scan_namespaces(&dev
->ctrl
);
1595 nvme_set_irq_hints(dev
);
1599 * Return: error value if an error occurred setting up the queues or calling
1600 * Identify Device. 0 if these succeeded, even if adding some of the
1601 * namespaces failed. At the moment, these failures are silent. TBD which
1602 * failures should be reported.
1604 static int nvme_dev_add(struct nvme_dev
*dev
)
1606 if (!dev
->ctrl
.tagset
) {
1607 dev
->tagset
.ops
= &nvme_mq_ops
;
1608 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
1609 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
1610 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
1611 dev
->tagset
.queue_depth
=
1612 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
1613 dev
->tagset
.cmd_size
= nvme_cmd_size(dev
);
1614 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
1615 dev
->tagset
.driver_data
= dev
;
1617 if (blk_mq_alloc_tag_set(&dev
->tagset
))
1619 dev
->ctrl
.tagset
= &dev
->tagset
;
1621 queue_work(nvme_workq
, &dev
->scan_work
);
1625 static int nvme_dev_map(struct nvme_dev
*dev
)
1628 int bars
, result
= -ENOMEM
;
1629 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1631 if (pci_enable_device_mem(pdev
))
1634 dev
->entry
[0].vector
= pdev
->irq
;
1635 pci_set_master(pdev
);
1636 bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
1640 if (pci_request_selected_regions(pdev
, bars
, "nvme"))
1643 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
1644 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
1647 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
1651 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
1657 * Some devices don't advertse INTx interrupts, pre-enable a single
1658 * MSIX vec for setup. We'll adjust this later.
1661 result
= pci_enable_msix(pdev
, dev
->entry
, 1);
1666 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1668 dev
->q_depth
= min_t(int, NVME_CAP_MQES(cap
) + 1, NVME_Q_DEPTH
);
1669 dev
->db_stride
= 1 << NVME_CAP_STRIDE(cap
);
1670 dev
->dbs
= dev
->bar
+ 4096;
1671 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2))
1672 dev
->cmb
= nvme_map_cmb(dev
);
1674 pci_enable_pcie_error_reporting(pdev
);
1675 pci_save_state(pdev
);
1682 pci_release_regions(pdev
);
1684 pci_disable_device(pdev
);
1688 static void nvme_dev_unmap(struct nvme_dev
*dev
)
1690 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1692 if (pdev
->msi_enabled
)
1693 pci_disable_msi(pdev
);
1694 else if (pdev
->msix_enabled
)
1695 pci_disable_msix(pdev
);
1700 pci_release_regions(pdev
);
1703 if (pci_is_enabled(pdev
)) {
1704 pci_disable_pcie_error_reporting(pdev
);
1705 pci_disable_device(pdev
);
1709 struct nvme_delq_ctx
{
1710 struct task_struct
*waiter
;
1711 struct kthread_worker
*worker
;
1715 static void nvme_wait_dq(struct nvme_delq_ctx
*dq
, struct nvme_dev
*dev
)
1717 dq
->waiter
= current
;
1721 set_current_state(TASK_KILLABLE
);
1722 if (!atomic_read(&dq
->refcount
))
1724 if (!schedule_timeout(ADMIN_TIMEOUT
) ||
1725 fatal_signal_pending(current
)) {
1727 * Disable the controller first since we can't trust it
1728 * at this point, but leave the admin queue enabled
1729 * until all queue deletion requests are flushed.
1730 * FIXME: This may take a while if there are more h/w
1731 * queues than admin tags.
1733 set_current_state(TASK_RUNNING
);
1734 nvme_disable_ctrl(&dev
->ctrl
,
1735 lo_hi_readq(dev
->bar
+ NVME_REG_CAP
));
1736 nvme_clear_queue(dev
->queues
[0]);
1737 flush_kthread_worker(dq
->worker
);
1738 nvme_disable_queue(dev
, 0);
1742 set_current_state(TASK_RUNNING
);
1745 static void nvme_put_dq(struct nvme_delq_ctx
*dq
)
1747 atomic_dec(&dq
->refcount
);
1749 wake_up_process(dq
->waiter
);
1752 static struct nvme_delq_ctx
*nvme_get_dq(struct nvme_delq_ctx
*dq
)
1754 atomic_inc(&dq
->refcount
);
1758 static void nvme_del_queue_end(struct nvme_queue
*nvmeq
)
1760 struct nvme_delq_ctx
*dq
= nvmeq
->cmdinfo
.ctx
;
1763 spin_lock_irq(&nvmeq
->q_lock
);
1764 nvme_process_cq(nvmeq
);
1765 spin_unlock_irq(&nvmeq
->q_lock
);
1768 static int adapter_async_del_queue(struct nvme_queue
*nvmeq
, u8 opcode
,
1769 kthread_work_func_t fn
)
1771 struct request
*req
;
1772 struct nvme_command c
;
1774 memset(&c
, 0, sizeof(c
));
1775 c
.delete_queue
.opcode
= opcode
;
1776 c
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
1778 init_kthread_work(&nvmeq
->cmdinfo
.work
, fn
);
1780 req
= nvme_alloc_request(nvmeq
->dev
->ctrl
.admin_q
, &c
, 0);
1782 return PTR_ERR(req
);
1784 req
->timeout
= ADMIN_TIMEOUT
;
1785 req
->end_io_data
= &nvmeq
->cmdinfo
;
1786 blk_execute_rq_nowait(req
->q
, NULL
, req
, 0, async_cmd_info_endio
);
1790 static void nvme_del_cq_work_handler(struct kthread_work
*work
)
1792 struct nvme_queue
*nvmeq
= container_of(work
, struct nvme_queue
,
1794 nvme_del_queue_end(nvmeq
);
1797 static int nvme_delete_cq(struct nvme_queue
*nvmeq
)
1799 return adapter_async_del_queue(nvmeq
, nvme_admin_delete_cq
,
1800 nvme_del_cq_work_handler
);
1803 static void nvme_del_sq_work_handler(struct kthread_work
*work
)
1805 struct nvme_queue
*nvmeq
= container_of(work
, struct nvme_queue
,
1807 int status
= nvmeq
->cmdinfo
.status
;
1810 status
= nvme_delete_cq(nvmeq
);
1812 nvme_del_queue_end(nvmeq
);
1815 static int nvme_delete_sq(struct nvme_queue
*nvmeq
)
1817 return adapter_async_del_queue(nvmeq
, nvme_admin_delete_sq
,
1818 nvme_del_sq_work_handler
);
1821 static void nvme_del_queue_start(struct kthread_work
*work
)
1823 struct nvme_queue
*nvmeq
= container_of(work
, struct nvme_queue
,
1825 if (nvme_delete_sq(nvmeq
))
1826 nvme_del_queue_end(nvmeq
);
1829 static void nvme_disable_io_queues(struct nvme_dev
*dev
)
1832 DEFINE_KTHREAD_WORKER_ONSTACK(worker
);
1833 struct nvme_delq_ctx dq
;
1834 struct task_struct
*kworker_task
= kthread_run(kthread_worker_fn
,
1835 &worker
, "nvme%d", dev
->ctrl
.instance
);
1837 if (IS_ERR(kworker_task
)) {
1839 "Failed to create queue del task\n");
1840 for (i
= dev
->queue_count
- 1; i
> 0; i
--)
1841 nvme_disable_queue(dev
, i
);
1846 atomic_set(&dq
.refcount
, 0);
1847 dq
.worker
= &worker
;
1848 for (i
= dev
->queue_count
- 1; i
> 0; i
--) {
1849 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1851 if (nvme_suspend_queue(nvmeq
))
1853 nvmeq
->cmdinfo
.ctx
= nvme_get_dq(&dq
);
1854 nvmeq
->cmdinfo
.worker
= dq
.worker
;
1855 init_kthread_work(&nvmeq
->cmdinfo
.work
, nvme_del_queue_start
);
1856 queue_kthread_work(dq
.worker
, &nvmeq
->cmdinfo
.work
);
1858 nvme_wait_dq(&dq
, dev
);
1859 kthread_stop(kworker_task
);
1862 static int nvme_dev_list_add(struct nvme_dev
*dev
)
1864 bool start_thread
= false;
1866 spin_lock(&dev_list_lock
);
1867 if (list_empty(&dev_list
) && IS_ERR_OR_NULL(nvme_thread
)) {
1868 start_thread
= true;
1871 list_add(&dev
->node
, &dev_list
);
1872 spin_unlock(&dev_list_lock
);
1875 nvme_thread
= kthread_run(nvme_kthread
, NULL
, "nvme");
1876 wake_up_all(&nvme_kthread_wait
);
1878 wait_event_killable(nvme_kthread_wait
, nvme_thread
);
1880 if (IS_ERR_OR_NULL(nvme_thread
))
1881 return nvme_thread
? PTR_ERR(nvme_thread
) : -EINTR
;
1887 * Remove the node from the device list and check
1888 * for whether or not we need to stop the nvme_thread.
1890 static void nvme_dev_list_remove(struct nvme_dev
*dev
)
1892 struct task_struct
*tmp
= NULL
;
1894 spin_lock(&dev_list_lock
);
1895 list_del_init(&dev
->node
);
1896 if (list_empty(&dev_list
) && !IS_ERR_OR_NULL(nvme_thread
)) {
1900 spin_unlock(&dev_list_lock
);
1906 static void nvme_freeze_queues(struct nvme_dev
*dev
)
1910 list_for_each_entry(ns
, &dev
->ctrl
.namespaces
, list
) {
1911 blk_mq_freeze_queue_start(ns
->queue
);
1913 spin_lock_irq(ns
->queue
->queue_lock
);
1914 queue_flag_set(QUEUE_FLAG_STOPPED
, ns
->queue
);
1915 spin_unlock_irq(ns
->queue
->queue_lock
);
1917 blk_mq_cancel_requeue_work(ns
->queue
);
1918 blk_mq_stop_hw_queues(ns
->queue
);
1922 static void nvme_unfreeze_queues(struct nvme_dev
*dev
)
1926 list_for_each_entry(ns
, &dev
->ctrl
.namespaces
, list
) {
1927 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED
, ns
->queue
);
1928 blk_mq_unfreeze_queue(ns
->queue
);
1929 blk_mq_start_stopped_hw_queues(ns
->queue
, true);
1930 blk_mq_kick_requeue_list(ns
->queue
);
1934 static void nvme_dev_shutdown(struct nvme_dev
*dev
)
1939 nvme_dev_list_remove(dev
);
1941 mutex_lock(&dev
->shutdown_lock
);
1943 nvme_freeze_queues(dev
);
1944 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1946 if (csts
& NVME_CSTS_CFS
|| !(csts
& NVME_CSTS_RDY
)) {
1947 for (i
= dev
->queue_count
- 1; i
>= 0; i
--) {
1948 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1949 nvme_suspend_queue(nvmeq
);
1952 nvme_disable_io_queues(dev
);
1953 nvme_shutdown_ctrl(&dev
->ctrl
);
1954 nvme_disable_queue(dev
, 0);
1956 nvme_dev_unmap(dev
);
1958 for (i
= dev
->queue_count
- 1; i
>= 0; i
--)
1959 nvme_clear_queue(dev
->queues
[i
]);
1960 mutex_unlock(&dev
->shutdown_lock
);
1963 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
1965 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
1966 PAGE_SIZE
, PAGE_SIZE
, 0);
1967 if (!dev
->prp_page_pool
)
1970 /* Optimisation for I/Os between 4k and 128k */
1971 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
1973 if (!dev
->prp_small_pool
) {
1974 dma_pool_destroy(dev
->prp_page_pool
);
1980 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
1982 dma_pool_destroy(dev
->prp_page_pool
);
1983 dma_pool_destroy(dev
->prp_small_pool
);
1986 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
1988 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1990 put_device(dev
->dev
);
1991 if (dev
->tagset
.tags
)
1992 blk_mq_free_tag_set(&dev
->tagset
);
1993 if (dev
->ctrl
.admin_q
)
1994 blk_put_queue(dev
->ctrl
.admin_q
);
2000 static void nvme_reset_work(struct work_struct
*work
)
2002 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, reset_work
);
2005 if (WARN_ON(test_bit(NVME_CTRL_RESETTING
, &dev
->flags
)))
2009 * If we're called to reset a live controller first shut it down before
2013 nvme_dev_shutdown(dev
);
2015 set_bit(NVME_CTRL_RESETTING
, &dev
->flags
);
2017 result
= nvme_dev_map(dev
);
2021 result
= nvme_configure_admin_queue(dev
);
2025 nvme_init_queue(dev
->queues
[0], 0);
2026 result
= nvme_alloc_admin_tags(dev
);
2030 result
= nvme_init_identify(&dev
->ctrl
);
2034 result
= nvme_setup_io_queues(dev
);
2038 dev
->ctrl
.event_limit
= NVME_NR_AEN_COMMANDS
;
2040 result
= nvme_dev_list_add(dev
);
2045 * Keep the controller around but remove all namespaces if we don't have
2046 * any working I/O queue.
2048 if (dev
->online_queues
< 2) {
2049 dev_warn(dev
->dev
, "IO queues not created\n");
2050 nvme_remove_namespaces(&dev
->ctrl
);
2052 nvme_unfreeze_queues(dev
);
2056 clear_bit(NVME_CTRL_RESETTING
, &dev
->flags
);
2060 nvme_dev_list_remove(dev
);
2062 nvme_dev_remove_admin(dev
);
2063 blk_put_queue(dev
->ctrl
.admin_q
);
2064 dev
->ctrl
.admin_q
= NULL
;
2065 dev
->queues
[0]->tags
= NULL
;
2067 nvme_disable_queue(dev
, 0);
2069 nvme_dev_unmap(dev
);
2071 nvme_remove_dead_ctrl(dev
);
2074 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
2076 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
2077 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2079 if (pci_get_drvdata(pdev
))
2080 pci_stop_and_remove_bus_device_locked(pdev
);
2081 nvme_put_ctrl(&dev
->ctrl
);
2084 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
)
2086 dev_warn(dev
->dev
, "Removing after probe failure\n");
2087 kref_get(&dev
->ctrl
.kref
);
2088 if (!schedule_work(&dev
->remove_work
))
2089 nvme_put_ctrl(&dev
->ctrl
);
2092 static int nvme_reset(struct nvme_dev
*dev
)
2094 if (!dev
->ctrl
.admin_q
|| blk_queue_dying(dev
->ctrl
.admin_q
))
2097 if (!queue_work(nvme_workq
, &dev
->reset_work
))
2100 flush_work(&dev
->reset_work
);
2104 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
2106 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
2110 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2112 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2116 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2118 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
2122 static bool nvme_pci_io_incapable(struct nvme_ctrl
*ctrl
)
2124 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2126 return !dev
->bar
|| dev
->online_queues
< 2;
2129 static int nvme_pci_reset_ctrl(struct nvme_ctrl
*ctrl
)
2131 return nvme_reset(to_nvme_dev(ctrl
));
2134 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2135 .reg_read32
= nvme_pci_reg_read32
,
2136 .reg_write32
= nvme_pci_reg_write32
,
2137 .reg_read64
= nvme_pci_reg_read64
,
2138 .io_incapable
= nvme_pci_io_incapable
,
2139 .reset_ctrl
= nvme_pci_reset_ctrl
,
2140 .free_ctrl
= nvme_pci_free_ctrl
,
2143 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2145 int node
, result
= -ENOMEM
;
2146 struct nvme_dev
*dev
;
2148 node
= dev_to_node(&pdev
->dev
);
2149 if (node
== NUMA_NO_NODE
)
2150 set_dev_node(&pdev
->dev
, 0);
2152 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2155 dev
->entry
= kzalloc_node(num_possible_cpus() * sizeof(*dev
->entry
),
2159 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2164 dev
->dev
= get_device(&pdev
->dev
);
2165 pci_set_drvdata(pdev
, dev
);
2167 INIT_LIST_HEAD(&dev
->node
);
2168 INIT_WORK(&dev
->scan_work
, nvme_dev_scan
);
2169 INIT_WORK(&dev
->reset_work
, nvme_reset_work
);
2170 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2171 mutex_init(&dev
->shutdown_lock
);
2173 result
= nvme_setup_prp_pools(dev
);
2177 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2182 queue_work(nvme_workq
, &dev
->reset_work
);
2186 nvme_release_prp_pools(dev
);
2188 put_device(dev
->dev
);
2196 static void nvme_reset_notify(struct pci_dev
*pdev
, bool prepare
)
2198 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2201 nvme_dev_shutdown(dev
);
2203 queue_work(nvme_workq
, &dev
->reset_work
);
2206 static void nvme_shutdown(struct pci_dev
*pdev
)
2208 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2209 nvme_dev_shutdown(dev
);
2212 static void nvme_remove(struct pci_dev
*pdev
)
2214 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2216 spin_lock(&dev_list_lock
);
2217 list_del_init(&dev
->node
);
2218 spin_unlock(&dev_list_lock
);
2220 pci_set_drvdata(pdev
, NULL
);
2221 flush_work(&dev
->reset_work
);
2222 flush_work(&dev
->scan_work
);
2223 nvme_remove_namespaces(&dev
->ctrl
);
2224 nvme_uninit_ctrl(&dev
->ctrl
);
2225 nvme_dev_shutdown(dev
);
2226 nvme_dev_remove_admin(dev
);
2227 nvme_free_queues(dev
, 0);
2228 nvme_release_cmb(dev
);
2229 nvme_release_prp_pools(dev
);
2230 nvme_put_ctrl(&dev
->ctrl
);
2233 #ifdef CONFIG_PM_SLEEP
2234 static int nvme_suspend(struct device
*dev
)
2236 struct pci_dev
*pdev
= to_pci_dev(dev
);
2237 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2239 nvme_dev_shutdown(ndev
);
2243 static int nvme_resume(struct device
*dev
)
2245 struct pci_dev
*pdev
= to_pci_dev(dev
);
2246 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2248 queue_work(nvme_workq
, &ndev
->reset_work
);
2253 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2255 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
2256 pci_channel_state_t state
)
2258 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2261 * A frozen channel requires a reset. When detected, this method will
2262 * shutdown the controller to quiesce. The controller will be restarted
2263 * after the slot reset through driver's slot_reset callback.
2265 dev_warn(&pdev
->dev
, "error detected: state:%d\n", state
);
2267 case pci_channel_io_normal
:
2268 return PCI_ERS_RESULT_CAN_RECOVER
;
2269 case pci_channel_io_frozen
:
2270 nvme_dev_shutdown(dev
);
2271 return PCI_ERS_RESULT_NEED_RESET
;
2272 case pci_channel_io_perm_failure
:
2273 return PCI_ERS_RESULT_DISCONNECT
;
2275 return PCI_ERS_RESULT_NEED_RESET
;
2278 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
2280 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2282 dev_info(&pdev
->dev
, "restart after slot reset\n");
2283 pci_restore_state(pdev
);
2284 queue_work(nvme_workq
, &dev
->reset_work
);
2285 return PCI_ERS_RESULT_RECOVERED
;
2288 static void nvme_error_resume(struct pci_dev
*pdev
)
2290 pci_cleanup_aer_uncorrect_error_status(pdev
);
2293 static const struct pci_error_handlers nvme_err_handler
= {
2294 .error_detected
= nvme_error_detected
,
2295 .slot_reset
= nvme_slot_reset
,
2296 .resume
= nvme_error_resume
,
2297 .reset_notify
= nvme_reset_notify
,
2300 /* Move to pci_ids.h later */
2301 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
2303 static const struct pci_device_id nvme_id_table
[] = {
2304 { PCI_VDEVICE(INTEL
, 0x0953),
2305 .driver_data
= NVME_QUIRK_STRIPE_SIZE
, },
2306 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2307 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2308 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2309 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2312 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2314 static struct pci_driver nvme_driver
= {
2316 .id_table
= nvme_id_table
,
2317 .probe
= nvme_probe
,
2318 .remove
= nvme_remove
,
2319 .shutdown
= nvme_shutdown
,
2321 .pm
= &nvme_dev_pm_ops
,
2323 .err_handler
= &nvme_err_handler
,
2326 static int __init
nvme_init(void)
2330 init_waitqueue_head(&nvme_kthread_wait
);
2332 nvme_workq
= alloc_workqueue("nvme", WQ_UNBOUND
| WQ_MEM_RECLAIM
, 0);
2336 result
= nvme_core_init();
2340 result
= pci_register_driver(&nvme_driver
);
2348 destroy_workqueue(nvme_workq
);
2352 static void __exit
nvme_exit(void)
2354 pci_unregister_driver(&nvme_driver
);
2356 destroy_workqueue(nvme_workq
);
2357 BUG_ON(nvme_thread
&& !IS_ERR(nvme_thread
));
2361 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2362 MODULE_LICENSE("GPL");
2363 MODULE_VERSION("1.0");
2364 module_init(nvme_init
);
2365 module_exit(nvme_exit
);