drivers/pci/probe.c

   1 /*
   2  * probe.c - PCI detection and setup code
   3  */
   4
   5 #include <linux/kernel.h>
   6 #include <linux/delay.h>
   7 #include <linux/init.h>
   8 #include <linux/pci.h>
   9 #include <linux/slab.h>
  10 #include <linux/module.h>
  11 #include <linux/cpumask.h>
  12
  13 #define CARDBUS_LATENCY_TIMER   176     /* secondary latency timer */
  14 #define CARDBUS_RESERVE_BUSNR   3
  15 #define PCI_CFG_SPACE_SIZE      256
  16 #define PCI_CFG_SPACE_EXP_SIZE  4096
  17
  18 /* Ugh.  Need to stop exporting this to modules. */
  19 LIST_HEAD(pci_root_buses);
  20 EXPORT_SYMBOL(pci_root_buses);
  21
  22 LIST_HEAD(pci_devices);
  23
  24 #ifdef HAVE_PCI_LEGACY
  25 /**
  26  * pci_create_legacy_files - create legacy I/O port and memory files
  27  * @b: bus to create files under
  28  *
  29  * Some platforms allow access to legacy I/O port and ISA memory space on
  30  * a per-bus basis.  This routine creates the files and ties them into
  31  * their associated read, write and mmap files from pci-sysfs.c
  32  */
  33 static void pci_create_legacy_files(struct pci_bus *b)
  34 {
  35         b->legacy_io = kmalloc(sizeof(struct bin_attribute) * 2,
  36                                GFP_ATOMIC);
  37         if (b->legacy_io) {
  38                 memset(b->legacy_io, 0, sizeof(struct bin_attribute) * 2);
  39                 b->legacy_io->attr.name = "legacy_io";
  40                 b->legacy_io->size = 0xffff;
  41                 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
  42                 b->legacy_io->attr.owner = THIS_MODULE;
  43                 b->legacy_io->read = pci_read_legacy_io;
  44                 b->legacy_io->write = pci_write_legacy_io;
  45                 class_device_create_bin_file(&b->class_dev, b->legacy_io);
  46
  47                 /* Allocated above after the legacy_io struct */
  48                 b->legacy_mem = b->legacy_io + 1;
  49                 b->legacy_mem->attr.name = "legacy_mem";
  50                 b->legacy_mem->size = 1024*1024;
  51                 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
  52                 b->legacy_mem->attr.owner = THIS_MODULE;
  53                 b->legacy_mem->mmap = pci_mmap_legacy_mem;
  54                 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
  55         }
  56 }
  57
  58 void pci_remove_legacy_files(struct pci_bus *b)
  59 {
  60         if (b->legacy_io) {
  61                 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
  62                 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
  63                 kfree(b->legacy_io); /* both are allocated here */
  64         }
  65 }
  66 #else /* !HAVE_PCI_LEGACY */
  67 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
  68 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
  69 #endif /* HAVE_PCI_LEGACY */
  70
  71 /*
  72  * PCI Bus Class Devices
  73  */
  74 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev, char *buf)
  75 {
  76         cpumask_t cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
  77         int ret;
  78
  79         ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
  80         if (ret < PAGE_SIZE)
  81                 buf[ret++] = '\n';
  82         return ret;
  83 }
  84 CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
  85
  86 /*
  87  * PCI Bus Class
  88  */
  89 static void release_pcibus_dev(struct class_device *class_dev)
  90 {
  91         struct pci_bus *pci_bus = to_pci_bus(class_dev);
  92
  93         if (pci_bus->bridge)
  94                 put_device(pci_bus->bridge);
  95         kfree(pci_bus);
  96 }
  97
  98 static struct class pcibus_class = {
  99         .name           = "pci_bus",
 100         .release        = &release_pcibus_dev,
 101 };
 102
 103 static int __init pcibus_class_init(void)
 104 {
 105         return class_register(&pcibus_class);
 106 }
 107 postcore_initcall(pcibus_class_init);
 108
 109 /*
 110  * Translate the low bits of the PCI base
 111  * to the resource type
 112  */
 113 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
 114 {
 115         if (flags & PCI_BASE_ADDRESS_SPACE_IO)
 116                 return IORESOURCE_IO;
 117
 118         if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
 119                 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
 120
 121         return IORESOURCE_MEM;
 122 }
 123
 124 /*
 125  * Find the extent of a PCI decode..
 126  */
 127 static u32 pci_size(u32 base, u32 maxbase, unsigned long mask)
 128 {
 129         u32 size = mask & maxbase;      /* Find the significant bits */
 130         if (!size)
 131                 return 0;
 132
 133         /* Get the lowest of them to find the decode size, and
 134            from that the extent.  */
 135         size = (size & ~(size-1)) - 1;
 136
 137         /* base == maxbase can be valid only if the BAR has
 138            already been programmed with all 1s.  */
 139         if (base == maxbase && ((base | size) & mask) != mask)
 140                 return 0;
 141
 142         return size;
 143 }
 144
 145 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
 146 {
 147         unsigned int pos, reg, next;
 148         u32 l, sz;
 149         struct resource *res;
 150
 151         for(pos=0; pos<howmany; pos = next) {
 152                 next = pos+1;
 153                 res = &dev->resource[pos];
 154                 res->name = pci_name(dev);
 155                 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
 156                 pci_read_config_dword(dev, reg, &l);
 157                 pci_write_config_dword(dev, reg, ~0);
 158                 pci_read_config_dword(dev, reg, &sz);
 159                 pci_write_config_dword(dev, reg, l);
 160                 if (!sz || sz == 0xffffffff)
 161                         continue;
 162                 if (l == 0xffffffff)
 163                         l = 0;
 164                 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
 165                         sz = pci_size(l, sz, PCI_BASE_ADDRESS_MEM_MASK);
 166                         if (!sz)
 167                                 continue;
 168                         res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
 169                         res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
 170                 } else {
 171                         sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
 172                         if (!sz)
 173                                 continue;
 174                         res->start = l & PCI_BASE_ADDRESS_IO_MASK;
 175                         res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
 176                 }
 177                 res->end = res->start + (unsigned long) sz;
 178                 res->flags |= pci_calc_resource_flags(l);
 179                 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
 180                     == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
 181                         pci_read_config_dword(dev, reg+4, &l);
 182                         next++;
 183 #if BITS_PER_LONG == 64
 184                         res->start |= ((unsigned long) l) << 32;
 185                         res->end = res->start + sz;
 186                         pci_write_config_dword(dev, reg+4, ~0);
 187                         pci_read_config_dword(dev, reg+4, &sz);
 188                         pci_write_config_dword(dev, reg+4, l);
 189                         sz = pci_size(l, sz, 0xffffffff);
 190                         if (sz) {
 191                                 /* This BAR needs > 4GB?  Wow. */
 192                                 res->end |= (unsigned long)sz<<32;
 193                         }
 194 #else
 195                         if (l) {
 196                                 printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", pci_name(dev));
 197                                 res->start = 0;
 198                                 res->flags = 0;
 199                                 continue;
 200                         }
 201 #endif
 202                 }
 203         }
 204         if (rom) {
 205                 dev->rom_base_reg = rom;
 206                 res = &dev->resource[PCI_ROM_RESOURCE];
 207                 res->name = pci_name(dev);
 208                 pci_read_config_dword(dev, rom, &l);
 209                 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
 210                 pci_read_config_dword(dev, rom, &sz);
 211                 pci_write_config_dword(dev, rom, l);
 212                 if (l == 0xffffffff)
 213                         l = 0;
 214                 if (sz && sz != 0xffffffff) {
 215                         sz = pci_size(l, sz, PCI_ROM_ADDRESS_MASK);
 216                         if (sz) {
 217                                 res->flags = (l & IORESOURCE_ROM_ENABLE) |
 218                                   IORESOURCE_MEM | IORESOURCE_PREFETCH |
 219                                   IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
 220                                 res->start = l & PCI_ROM_ADDRESS_MASK;
 221                                 res->end = res->start + (unsigned long) sz;
 222                         }
 223                 }
 224         }
 225 }
 226
 227 void __devinit pci_read_bridge_bases(struct pci_bus *child)
 228 {
 229         struct pci_dev *dev = child->self;
 230         u8 io_base_lo, io_limit_lo;
 231         u16 mem_base_lo, mem_limit_lo;
 232         unsigned long base, limit;
 233         struct resource *res;
 234         int i;
 235
 236         if (!dev)               /* It's a host bus, nothing to read */
 237                 return;
 238
 239         if (dev->transparent) {
 240                 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
 241                 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++)
 242                         child->resource[i] = child->parent->resource[i];
 243                 return;
 244         }
 245
 246         for(i=0; i<3; i++)
 247                 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
 248
 249         res = child->resource[0];
 250         pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
 251         pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
 252         base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
 253         limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
 254
 255         if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
 256                 u16 io_base_hi, io_limit_hi;
 257                 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
 258                 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
 259                 base |= (io_base_hi << 16);
 260                 limit |= (io_limit_hi << 16);
 261         }
 262
 263         if (base <= limit) {
 264                 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
 265                 res->start = base;
 266                 res->end = limit + 0xfff;
 267         }
 268
 269         res = child->resource[1];
 270         pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
 271         pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
 272         base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
 273         limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
 274         if (base <= limit) {
 275                 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
 276                 res->start = base;
 277                 res->end = limit + 0xfffff;
 278         }
 279
 280         res = child->resource[2];
 281         pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
 282         pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
 283         base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
 284         limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
 285
 286         if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
 287                 u32 mem_base_hi, mem_limit_hi;
 288                 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
 289                 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
 290
 291                 /*
 292                  * Some bridges set the base > limit by default, and some
 293                  * (broken) BIOSes do not initialize them.  If we find
 294                  * this, just assume they are not being used.
 295                  */
 296                 if (mem_base_hi <= mem_limit_hi) {
 297 #if BITS_PER_LONG == 64
 298                         base |= ((long) mem_base_hi) << 32;
 299                         limit |= ((long) mem_limit_hi) << 32;
 300 #else
 301                         if (mem_base_hi || mem_limit_hi) {
 302                                 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
 303                                 return;
 304                         }
 305 #endif
 306                 }
 307         }
 308         if (base <= limit) {
 309                 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
 310                 res->start = base;
 311                 res->end = limit + 0xfffff;
 312         }
 313 }
 314
 315 static struct pci_bus * __devinit pci_alloc_bus(void)
 316 {
 317         struct pci_bus *b;
 318
 319         b = kmalloc(sizeof(*b), GFP_KERNEL);
 320         if (b) {
 321                 memset(b, 0, sizeof(*b));
 322                 INIT_LIST_HEAD(&b->node);
 323                 INIT_LIST_HEAD(&b->children);
 324                 INIT_LIST_HEAD(&b->devices);
 325         }
 326         return b;
 327 }
 328
 329 static struct pci_bus * __devinit
 330 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
 331 {
 332         struct pci_bus *child;
 333         int i;
 334
 335         /*
 336          * Allocate a new bus, and inherit stuff from the parent..
 337          */
 338         child = pci_alloc_bus();
 339         if (!child)
 340                 return NULL;
 341
 342         child->self = bridge;
 343         child->parent = parent;
 344         child->ops = parent->ops;
 345         child->sysdata = parent->sysdata;
 346         child->bridge = get_device(&bridge->dev);
 347
 348         child->class_dev.class = &pcibus_class;
 349         sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
 350         class_device_register(&child->class_dev);
 351         class_device_create_file(&child->class_dev, &class_device_attr_cpuaffinity);
 352
 353         /*
 354          * Set up the primary, secondary and subordinate
 355          * bus numbers.
 356          */
 357         child->number = child->secondary = busnr;
 358         child->primary = parent->secondary;
 359         child->subordinate = 0xff;
 360
 361         /* Set up default resource pointers and names.. */
 362         for (i = 0; i < 4; i++) {
 363                 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
 364                 child->resource[i]->name = child->name;
 365         }
 366         bridge->subordinate = child;
 367
 368         return child;
 369 }
 370
 371 struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
 372 {
 373         struct pci_bus *child;
 374
 375         child = pci_alloc_child_bus(parent, dev, busnr);
 376         if (child)
 377                 list_add_tail(&child->node, &parent->children);
 378         return child;
 379 }
 380
 381 static void pci_enable_crs(struct pci_dev *dev)
 382 {
 383         u16 cap, rpctl;
 384         int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP);
 385         if (!rpcap)
 386                 return;
 387
 388         pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap);
 389         if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT)
 390                 return;
 391
 392         pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl);
 393         rpctl |= PCI_EXP_RTCTL_CRSSVE;
 394         pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl);
 395 }
 396
 397 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
 398
 399 /*
 400  * If it's a bridge, configure it and scan the bus behind it.
 401  * For CardBus bridges, we don't scan behind as the devices will
 402  * be handled by the bridge driver itself.
 403  *
 404  * We need to process bridges in two passes -- first we scan those
 405  * already configured by the BIOS and after we are done with all of
 406  * them, we proceed to assigning numbers to the remaining buses in
 407  * order to avoid overlaps between old and new bus numbers.
 408  */
 409 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
 410 {
 411         struct pci_bus *child;
 412         int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
 413         u32 buses;
 414         u16 bctl;
 415
 416         pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
 417
 418         pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
 419                  pci_name(dev), buses & 0xffffff, pass);
 420
 421         /* Disable MasterAbortMode during probing to avoid reporting
 422            of bus errors (in some architectures) */
 423         pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
 424         pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
 425                               bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
 426
 427         pci_enable_crs(dev);
 428
 429         if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
 430                 unsigned int cmax, busnr;
 431                 /*
 432                  * Bus already configured by firmware, process it in the first
 433                  * pass and just note the configuration.
 434                  */
 435                 if (pass)
 436                         return max;
 437                 busnr = (buses >> 8) & 0xFF;
 438
 439                 /*
 440                  * If we already got to this bus through a different bridge,
 441                  * ignore it.  This can happen with the i450NX chipset.
 442                  */
 443                 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
 444                         printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
 445                                         pci_domain_nr(bus), busnr);
 446                         return max;
 447                 }
 448
 449                 child = pci_alloc_child_bus(bus, dev, busnr);
 450                 if (!child)
 451                         return max;
 452                 child->primary = buses & 0xFF;
 453                 child->subordinate = (buses >> 16) & 0xFF;
 454                 child->bridge_ctl = bctl;
 455
 456                 cmax = pci_scan_child_bus(child);
 457                 if (cmax > max)
 458                         max = cmax;
 459                 if (child->subordinate > max)
 460                         max = child->subordinate;
 461         } else {
 462                 /*
 463                  * We need to assign a number to this bus which we always
 464                  * do in the second pass.
 465                  */
 466                 if (!pass)
 467                         return max;
 468
 469                 /* Clear errors */
 470                 pci_write_config_word(dev, PCI_STATUS, 0xffff);
 471
 472                 child = pci_alloc_child_bus(bus, dev, ++max);
 473                 buses = (buses & 0xff000000)
 474                       | ((unsigned int)(child->primary)     <<  0)
 475                       | ((unsigned int)(child->secondary)   <<  8)
 476                       | ((unsigned int)(child->subordinate) << 16);
 477
 478                 /*
 479                  * yenta.c forces a secondary latency timer of 176.
 480                  * Copy that behaviour here.
 481                  */
 482                 if (is_cardbus) {
 483                         buses &= ~0xff000000;
 484                         buses |= CARDBUS_LATENCY_TIMER << 24;
 485                 }
 486
 487                 /*
 488                  * We need to blast all three values with a single write.
 489                  */
 490                 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
 491
 492                 if (!is_cardbus) {
 493                         child->bridge_ctl = PCI_BRIDGE_CTL_NO_ISA;
 494
 495                         /* Now we can scan all subordinate buses... */
 496                         max = pci_scan_child_bus(child);
 497                 } else {
 498                         /*
 499                          * For CardBus bridges, we leave 4 bus numbers
 500                          * as cards with a PCI-to-PCI bridge can be
 501                          * inserted later.
 502                          */
 503                         max += CARDBUS_RESERVE_BUSNR;
 504                 }
 505                 /*
 506                  * Set the subordinate bus number to its real value.
 507                  */
 508                 child->subordinate = max;
 509                 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
 510         }
 511
 512         pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
 513
 514         sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
 515
 516         return max;
 517 }
 518
 519 /*
 520  * Read interrupt line and base address registers.
 521  * The architecture-dependent code can tweak these, of course.
 522  */
 523 static void pci_read_irq(struct pci_dev *dev)
 524 {
 525         unsigned char irq;
 526
 527         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
 528         if (irq)
 529                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 530         dev->irq = irq;
 531 }
 532
 533 /**
 534  * pci_setup_device - fill in class and map information of a device
 535  * @dev: the device structure to fill
 536  *
 537  * Initialize the device structure with information about the device's
 538  * vendor,class,memory and IO-space addresses,IRQ lines etc.
 539  * Called at initialisation of the PCI subsystem and by CardBus services.
 540  * Returns 0 on success and -1 if unknown type of device (not normal, bridge
 541  * or CardBus).
 542  */
 543 static int pci_setup_device(struct pci_dev * dev)
 544 {
 545         u32 class;
 546
 547         sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
 548                 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
 549
 550         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
 551         class >>= 8;                                /* upper 3 bytes */
 552         dev->class = class;
 553         class >>= 8;
 554
 555         pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
 556                  dev->vendor, dev->device, class, dev->hdr_type);
 557
 558         /* "Unknown power state" */
 559         dev->current_state = 4;
 560
 561         /* Early fixups, before probing the BARs */
 562         pci_fixup_device(pci_fixup_early, dev);
 563         class = dev->class >> 8;
 564
 565         switch (dev->hdr_type) {                    /* header type */
 566         case PCI_HEADER_TYPE_NORMAL:                /* standard header */
 567                 if (class == PCI_CLASS_BRIDGE_PCI)
 568                         goto bad;
 569                 pci_read_irq(dev);
 570                 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
 571                 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
 572                 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
 573                 break;
 574
 575         case PCI_HEADER_TYPE_BRIDGE:                /* bridge header */
 576                 if (class != PCI_CLASS_BRIDGE_PCI)
 577                         goto bad;
 578                 /* The PCI-to-PCI bridge spec requires that subtractive
 579                    decoding (i.e. transparent) bridge must have programming
 580                    interface code of 0x01. */
 581                 dev->transparent = ((dev->class & 0xff) == 1);
 582                 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
 583                 break;
 584
 585         case PCI_HEADER_TYPE_CARDBUS:               /* CardBus bridge header */
 586                 if (class != PCI_CLASS_BRIDGE_CARDBUS)
 587                         goto bad;
 588                 pci_read_irq(dev);
 589                 pci_read_bases(dev, 1, 0);
 590                 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
 591                 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
 592                 break;
 593
 594         default:                                    /* unknown header */
 595                 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
 596                         pci_name(dev), dev->hdr_type);
 597                 return -1;
 598
 599         bad:
 600                 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
 601                        pci_name(dev), class, dev->hdr_type);
 602                 dev->class = PCI_CLASS_NOT_DEFINED;
 603         }
 604
 605         /* We found a fine healthy device, go go go... */
 606         return 0;
 607 }
 608
 609 /**
 610  * pci_release_dev - free a pci device structure when all users of it are finished.
 611  * @dev: device that's been disconnected
 612  *
 613  * Will be called only by the device core when all users of this pci device are
 614  * done.
 615  */
 616 static void pci_release_dev(struct device *dev)
 617 {
 618         struct pci_dev *pci_dev;
 619
 620         pci_dev = to_pci_dev(dev);
 621         kfree(pci_dev);
 622 }
 623
 624 /**
 625  * pci_cfg_space_size - get the configuration space size of the PCI device.
 626  *
 627  * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
 628  * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
 629  * access it.  Maybe we don't have a way to generate extended config space
 630  * accesses, or the device is behind a reverse Express bridge.  So we try
 631  * reading the dword at 0x100 which must either be 0 or a valid extended
 632  * capability header.
 633  */
 634 static int pci_cfg_space_size(struct pci_dev *dev)
 635 {
 636         int pos;
 637         u32 status;
 638
 639         pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
 640         if (!pos) {
 641                 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
 642                 if (!pos)
 643                         goto fail;
 644
 645                 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
 646                 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
 647                         goto fail;
 648         }
 649
 650         if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
 651                 goto fail;
 652         if (status == 0xffffffff)
 653                 goto fail;
 654
 655         return PCI_CFG_SPACE_EXP_SIZE;
 656
 657  fail:
 658         return PCI_CFG_SPACE_SIZE;
 659 }
 660
 661 static void pci_release_bus_bridge_dev(struct device *dev)
 662 {
 663         kfree(dev);
 664 }
 665
 666 /*
 667  * Read the config data for a PCI device, sanity-check it
 668  * and fill in the dev structure...
 669  */
 670 static struct pci_dev * __devinit
 671 pci_scan_device(struct pci_bus *bus, int devfn)
 672 {
 673         struct pci_dev *dev;
 674         u32 l;
 675         u8 hdr_type;
 676         int delay = 1;
 677
 678         if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
 679                 return NULL;
 680
 681         /* some broken boards return 0 or ~0 if a slot is empty: */
 682         if (l == 0xffffffff || l == 0x00000000 ||
 683             l == 0x0000ffff || l == 0xffff0000)
 684                 return NULL;
 685
 686         /* Configuration request Retry Status */
 687         while (l == 0xffff0001) {
 688                 msleep(delay);
 689                 delay *= 2;
 690                 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
 691                         return NULL;
 692                 /* Card hasn't responded in 60 seconds?  Must be stuck. */
 693                 if (delay > 60 * 1000) {
 694                         printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
 695                                         "responding\n", pci_domain_nr(bus),
 696                                         bus->number, PCI_SLOT(devfn),
 697                                         PCI_FUNC(devfn));
 698                         return NULL;
 699                 }
 700         }
 701
 702         if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
 703                 return NULL;
 704
 705         dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
 706         if (!dev)
 707                 return NULL;
 708
 709         memset(dev, 0, sizeof(struct pci_dev));
 710         dev->bus = bus;
 711         dev->sysdata = bus->sysdata;
 712         dev->dev.parent = bus->bridge;
 713         dev->dev.bus = &pci_bus_type;
 714         dev->devfn = devfn;
 715         dev->hdr_type = hdr_type & 0x7f;
 716         dev->multifunction = !!(hdr_type & 0x80);
 717         dev->vendor = l & 0xffff;
 718         dev->device = (l >> 16) & 0xffff;
 719         dev->cfg_size = pci_cfg_space_size(dev);
 720
 721         /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
 722            set this higher, assuming the system even supports it.  */
 723         dev->dma_mask = 0xffffffff;
 724         if (pci_setup_device(dev) < 0) {
 725                 kfree(dev);
 726                 return NULL;
 727         }
 728         device_initialize(&dev->dev);
 729         dev->dev.release = pci_release_dev;
 730         pci_dev_get(dev);
 731
 732         pci_name_device(dev);
 733
 734         dev->dev.dma_mask = &dev->dma_mask;
 735         dev->dev.coherent_dma_mask = 0xffffffffull;
 736
 737         return dev;
 738 }
 739
 740 struct pci_dev * __devinit
 741 pci_scan_single_device(struct pci_bus *bus, int devfn)
 742 {
 743         struct pci_dev *dev;
 744
 745         dev = pci_scan_device(bus, devfn);
 746         pci_scan_msi_device(dev);
 747
 748         if (!dev)
 749                 return NULL;
 750
 751         /* Fix up broken headers */
 752         pci_fixup_device(pci_fixup_header, dev);
 753
 754         /*
 755          * Add the device to our list of discovered devices
 756          * and the bus list for fixup functions, etc.
 757          */
 758         INIT_LIST_HEAD(&dev->global_list);
 759         list_add_tail(&dev->bus_list, &bus->devices);
 760
 761         return dev;
 762 }
 763
 764 /**
 765  * pci_scan_slot - scan a PCI slot on a bus for devices.
 766  * @bus: PCI bus to scan
 767  * @devfn: slot number to scan (must have zero function.)
 768  *
 769  * Scan a PCI slot on the specified PCI bus for devices, adding
 770  * discovered devices to the @bus->devices list.  New devices
 771  * will have an empty dev->global_list head.
 772  */
 773 int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
 774 {
 775         int func, nr = 0;
 776         int scan_all_fns;
 777
 778         scan_all_fns = pcibios_scan_all_fns(bus, devfn);
 779
 780         for (func = 0; func < 8; func++, devfn++) {
 781                 struct pci_dev *dev;
 782
 783                 dev = pci_scan_single_device(bus, devfn);
 784                 if (dev) {
 785                         nr++;
 786
 787                         /*
 788                          * If this is a single function device,
 789                          * don't scan past the first function.
 790                          */
 791                         if (!dev->multifunction) {
 792                                 if (func > 0) {
 793                                         dev->multifunction = 1;
 794                                 } else {
 795                                         break;
 796                                 }
 797                         }
 798                 } else {
 799                         if (func == 0 && !scan_all_fns)
 800                                 break;
 801                 }
 802         }
 803         return nr;
 804 }
 805
 806 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
 807 {
 808         unsigned int devfn, pass, max = bus->secondary;
 809         struct pci_dev *dev;
 810
 811         pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
 812
 813         /* Go find them, Rover! */
 814         for (devfn = 0; devfn < 0x100; devfn += 8)
 815                 pci_scan_slot(bus, devfn);
 816
 817         /*
 818          * After performing arch-dependent fixup of the bus, look behind
 819          * all PCI-to-PCI bridges on this bus.
 820          */
 821         pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
 822         pcibios_fixup_bus(bus);
 823         for (pass=0; pass < 2; pass++)
 824                 list_for_each_entry(dev, &bus->devices, bus_list) {
 825                         if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
 826                             dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
 827                                 max = pci_scan_bridge(bus, dev, max, pass);
 828                 }
 829
 830         /*
 831          * We've scanned the bus and so we know all about what's on
 832          * the other side of any bridges that may be on this bus plus
 833          * any devices.
 834          *
 835          * Return how far we've got finding sub-buses.
 836          */
 837         pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
 838                 pci_domain_nr(bus), bus->number, max);
 839         return max;
 840 }
 841
 842 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
 843 {
 844         unsigned int max;
 845
 846         max = pci_scan_child_bus(bus);
 847
 848         /*
 849          * Make the discovered devices available.
 850          */
 851         pci_bus_add_devices(bus);
 852
 853         return max;
 854 }
 855
 856 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata)
 857 {
 858         int error;
 859         struct pci_bus *b;
 860         struct device *dev;
 861
 862         b = pci_alloc_bus();
 863         if (!b)
 864                 return NULL;
 865
 866         dev = kmalloc(sizeof(*dev), GFP_KERNEL);
 867         if (!dev){
 868                 kfree(b);
 869                 return NULL;
 870         }
 871
 872         b->sysdata = sysdata;
 873         b->ops = ops;
 874
 875         if (pci_find_bus(pci_domain_nr(b), bus)) {
 876                 /* If we already got to this bus through a different bridge, ignore it */
 877                 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
 878                 goto err_out;
 879         }
 880         list_add_tail(&b->node, &pci_root_buses);
 881
 882         memset(dev, 0, sizeof(*dev));
 883         dev->parent = parent;
 884         dev->release = pci_release_bus_bridge_dev;
 885         sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
 886         error = device_register(dev);
 887         if (error)
 888                 goto dev_reg_err;
 889         b->bridge = get_device(dev);
 890
 891         b->class_dev.class = &pcibus_class;
 892         sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
 893         error = class_device_register(&b->class_dev);
 894         if (error)
 895                 goto class_dev_reg_err;
 896         error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
 897         if (error)
 898                 goto class_dev_create_file_err;
 899
 900         /* Create legacy_io and legacy_mem files for this bus */
 901         pci_create_legacy_files(b);
 902
 903         error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
 904         if (error)
 905                 goto sys_create_link_err;
 906
 907         b->number = b->secondary = bus;
 908         b->resource[0] = &ioport_resource;
 909         b->resource[1] = &iomem_resource;
 910
 911         b->subordinate = pci_scan_child_bus(b);
 912
 913         pci_bus_add_devices(b);
 914
 915         return b;
 916
 917 sys_create_link_err:
 918         class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
 919 class_dev_create_file_err:
 920         class_device_unregister(&b->class_dev);
 921 class_dev_reg_err:
 922         device_unregister(dev);
 923 dev_reg_err:
 924         list_del(&b->node);
 925 err_out:
 926         kfree(dev);
 927         kfree(b);
 928         return NULL;
 929 }
 930 EXPORT_SYMBOL(pci_scan_bus_parented);
 931
 932 #ifdef CONFIG_HOTPLUG
 933 EXPORT_SYMBOL(pci_add_new_bus);
 934 EXPORT_SYMBOL(pci_do_scan_bus);
 935 EXPORT_SYMBOL(pci_scan_slot);
 936 EXPORT_SYMBOL(pci_scan_bridge);
 937 EXPORT_SYMBOL(pci_scan_single_device);
 938 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
 939 #endif