2 * R8A7795 processor support - PFC hardware block.
4 * Copyright (C) 2015 Renesas Electronics Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
11 #include <linux/kernel.h>
16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
17 SH_PFC_PIN_CFG_PULL_UP | \
18 SH_PFC_PIN_CFG_PULL_DOWN)
20 #define CPU_ALL_PORT(fn, sfx) \
21 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
25 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
30 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
34 * F_() : just information
35 * FM() : macro for FN_xxx / xxx_MARK
39 #define GPSR0_15 F_(D15, IP7_11_8)
40 #define GPSR0_14 F_(D14, IP7_7_4)
41 #define GPSR0_13 F_(D13, IP7_3_0)
42 #define GPSR0_12 F_(D12, IP6_31_28)
43 #define GPSR0_11 F_(D11, IP6_27_24)
44 #define GPSR0_10 F_(D10, IP6_23_20)
45 #define GPSR0_9 F_(D9, IP6_19_16)
46 #define GPSR0_8 F_(D8, IP6_15_12)
47 #define GPSR0_7 F_(D7, IP6_11_8)
48 #define GPSR0_6 F_(D6, IP6_7_4)
49 #define GPSR0_5 F_(D5, IP6_3_0)
50 #define GPSR0_4 F_(D4, IP5_31_28)
51 #define GPSR0_3 F_(D3, IP5_27_24)
52 #define GPSR0_2 F_(D2, IP5_23_20)
53 #define GPSR0_1 F_(D1, IP5_19_16)
54 #define GPSR0_0 F_(D0, IP5_15_12)
57 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
58 #define GPSR1_26 F_(WE1_N, IP5_7_4)
59 #define GPSR1_25 F_(WE0_N, IP5_3_0)
60 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
61 #define GPSR1_23 F_(RD_N, IP4_27_24)
62 #define GPSR1_22 F_(BS_N, IP4_23_20)
63 #define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
64 #define GPSR1_20 F_(CS0_N, IP4_15_12)
65 #define GPSR1_19 F_(A19, IP4_11_8)
66 #define GPSR1_18 F_(A18, IP4_7_4)
67 #define GPSR1_17 F_(A17, IP4_3_0)
68 #define GPSR1_16 F_(A16, IP3_31_28)
69 #define GPSR1_15 F_(A15, IP3_27_24)
70 #define GPSR1_14 F_(A14, IP3_23_20)
71 #define GPSR1_13 F_(A13, IP3_19_16)
72 #define GPSR1_12 F_(A12, IP3_15_12)
73 #define GPSR1_11 F_(A11, IP3_11_8)
74 #define GPSR1_10 F_(A10, IP3_7_4)
75 #define GPSR1_9 F_(A9, IP3_3_0)
76 #define GPSR1_8 F_(A8, IP2_31_28)
77 #define GPSR1_7 F_(A7, IP2_27_24)
78 #define GPSR1_6 F_(A6, IP2_23_20)
79 #define GPSR1_5 F_(A5, IP2_19_16)
80 #define GPSR1_4 F_(A4, IP2_15_12)
81 #define GPSR1_3 F_(A3, IP2_11_8)
82 #define GPSR1_2 F_(A2, IP2_7_4)
83 #define GPSR1_1 F_(A1, IP2_3_0)
84 #define GPSR1_0 F_(A0, IP1_31_28)
87 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
88 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
89 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
90 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
91 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
92 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
93 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
94 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
95 #define GPSR2_6 F_(PWM0, IP1_19_16)
96 #define GPSR2_5 F_(IRQ5, IP1_15_12)
97 #define GPSR2_4 F_(IRQ4, IP1_11_8)
98 #define GPSR2_3 F_(IRQ3, IP1_7_4)
99 #define GPSR2_2 F_(IRQ2, IP1_3_0)
100 #define GPSR2_1 F_(IRQ1, IP0_31_28)
101 #define GPSR2_0 F_(IRQ0, IP0_27_24)
104 #define GPSR3_15 F_(SD1_WP, IP10_23_20)
105 #define GPSR3_14 F_(SD1_CD, IP10_19_16)
106 #define GPSR3_13 F_(SD0_WP, IP10_15_12)
107 #define GPSR3_12 F_(SD0_CD, IP10_11_8)
108 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
109 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
110 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
111 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
112 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
113 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
114 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
115 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
116 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
117 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
118 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
119 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
122 #define GPSR4_17 FM(SD3_DS)
123 #define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
124 #define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
125 #define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
126 #define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
127 #define GPSR4_12 FM(SD3_DAT3)
128 #define GPSR4_11 FM(SD3_DAT2)
129 #define GPSR4_10 FM(SD3_DAT1)
130 #define GPSR4_9 FM(SD3_DAT0)
131 #define GPSR4_8 FM(SD3_CMD)
132 #define GPSR4_7 FM(SD3_CLK)
133 #define GPSR4_6 F_(SD2_DS, IP9_23_20)
134 #define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
135 #define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
136 #define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
137 #define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
138 #define GPSR4_1 FM(SD2_CMD)
139 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
142 #define GPSR5_25 F_(MLB_DAT, IP13_19_16)
143 #define GPSR5_24 F_(MLB_SIG, IP13_15_12)
144 #define GPSR5_23 F_(MLB_CLK, IP13_11_8)
145 #define GPSR5_22 FM(MSIOF0_RXD)
146 #define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4)
147 #define GPSR5_20 FM(MSIOF0_TXD)
148 #define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0)
149 #define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28)
150 #define GPSR5_17 FM(MSIOF0_SCK)
151 #define GPSR5_16 F_(HRTS0_N, IP12_27_24)
152 #define GPSR5_15 F_(HCTS0_N, IP12_23_20)
153 #define GPSR5_14 F_(HTX0, IP12_19_16)
154 #define GPSR5_13 F_(HRX0, IP12_15_12)
155 #define GPSR5_12 F_(HSCK0, IP12_11_8)
156 #define GPSR5_11 F_(RX2_A, IP12_7_4)
157 #define GPSR5_10 F_(TX2_A, IP12_3_0)
158 #define GPSR5_9 F_(SCK2, IP11_31_28)
159 #define GPSR5_8 F_(RTS1_N_TANS, IP11_27_24)
160 #define GPSR5_7 F_(CTS1_N, IP11_23_20)
161 #define GPSR5_6 F_(TX1_A, IP11_19_16)
162 #define GPSR5_5 F_(RX1_A, IP11_15_12)
163 #define GPSR5_4 F_(RTS0_N_TANS, IP11_11_8)
164 #define GPSR5_3 F_(CTS0_N, IP11_7_4)
165 #define GPSR5_2 F_(TX0, IP11_3_0)
166 #define GPSR5_1 F_(RX0, IP10_31_28)
167 #define GPSR5_0 F_(SCK0, IP10_27_24)
170 #define GPSR6_31 F_(USB31_OVC, IP17_7_4)
171 #define GPSR6_30 F_(USB31_PWEN, IP17_3_0)
172 #define GPSR6_29 F_(USB30_OVC, IP16_31_28)
173 #define GPSR6_28 F_(USB30_PWEN, IP16_27_24)
174 #define GPSR6_27 F_(USB1_OVC, IP16_23_20)
175 #define GPSR6_26 F_(USB1_PWEN, IP16_19_16)
176 #define GPSR6_25 F_(USB0_OVC, IP16_15_12)
177 #define GPSR6_24 F_(USB0_PWEN, IP16_11_8)
178 #define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4)
179 #define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0)
180 #define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28)
181 #define GPSR6_20 F_(SSI_SDATA8, IP15_27_24)
182 #define GPSR6_19 F_(SSI_SDATA7, IP15_23_20)
183 #define GPSR6_18 F_(SSI_WS78, IP15_19_16)
184 #define GPSR6_17 F_(SSI_SCK78, IP15_15_12)
185 #define GPSR6_16 F_(SSI_SDATA6, IP15_11_8)
186 #define GPSR6_15 F_(SSI_WS6, IP15_7_4)
187 #define GPSR6_14 F_(SSI_SCK6, IP15_3_0)
188 #define GPSR6_13 FM(SSI_SDATA5)
189 #define GPSR6_12 FM(SSI_WS5)
190 #define GPSR6_11 FM(SSI_SCK5)
191 #define GPSR6_10 F_(SSI_SDATA4, IP14_31_28)
192 #define GPSR6_9 F_(SSI_WS4, IP14_27_24)
193 #define GPSR6_8 F_(SSI_SCK4, IP14_23_20)
194 #define GPSR6_7 F_(SSI_SDATA3, IP14_19_16)
195 #define GPSR6_6 F_(SSI_WS34, IP14_15_12)
196 #define GPSR6_5 F_(SSI_SCK34, IP14_11_8)
197 #define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4)
198 #define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0)
199 #define GPSR6_2 F_(SSI_SDATA0, IP13_31_28)
200 #define GPSR6_1 F_(SSI_WS01239, IP13_27_24)
201 #define GPSR6_0 F_(SSI_SCK01239, IP13_23_20)
204 #define GPSR7_3 FM(HDMI1_CEC)
205 #define GPSR7_2 FM(HDMI0_CEC)
206 #define GPSR7_1 FM(AVS2)
207 #define GPSR7_0 FM(AVS1)
210 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
211 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
232 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP11_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP11_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
320 #define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP14_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP14_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define PINMUX_GPSR \
364 GPSR1_25 GPSR5_25 GPSR6_25 \
365 GPSR1_24 GPSR5_24 GPSR6_24 \
366 GPSR1_23 GPSR5_23 GPSR6_23 \
367 GPSR1_22 GPSR5_22 GPSR6_22 \
368 GPSR1_21 GPSR5_21 GPSR6_21 \
369 GPSR1_20 GPSR5_20 GPSR6_20 \
370 GPSR1_19 GPSR5_19 GPSR6_19 \
371 GPSR1_18 GPSR5_18 GPSR6_18 \
372 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
373 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
374 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
375 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
376 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
377 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
378 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
379 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
380 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
381 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
382 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
383 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
384 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
385 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
386 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
387 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
388 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
389 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
391 #define PINMUX_IPSR \
393 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
394 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
395 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
396 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
397 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
398 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
399 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
400 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
402 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
403 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
404 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
405 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
406 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
407 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
408 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
409 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
411 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
412 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
413 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
414 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
415 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
416 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
417 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
418 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
420 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
421 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
422 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
423 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
424 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
425 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
426 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
427 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
429 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \
430 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \
431 FM(IP16_11_8) IP16_11_8 \
432 FM(IP16_15_12) IP16_15_12 \
433 FM(IP16_19_16) IP16_19_16 \
434 FM(IP16_23_20) IP16_23_20 \
435 FM(IP16_27_24) IP16_27_24 \
436 FM(IP16_31_28) IP16_31_28
438 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
439 #define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3)
440 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
441 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
442 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
443 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
444 #define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0)
445 #define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
446 #define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
447 #define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
448 #define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
449 #define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
450 #define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
451 #define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1)
452 #define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1)
453 #define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
454 #define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
455 #define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
456 #define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
457 #define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
458 #define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
459 #define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3)
461 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
462 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
463 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
464 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
465 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
466 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
467 #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
468 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
469 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
470 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
471 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
472 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
473 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
474 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
475 #define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
476 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
477 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
478 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
479 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
480 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
481 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
482 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
483 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
485 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
486 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
487 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
488 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
489 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
491 #define PINMUX_MOD_SELS\
493 MOD_SEL1_31_30 MOD_SEL2_31 \
494 MOD_SEL0_30_29 MOD_SEL2_30 \
495 MOD_SEL1_29_28_27 MOD_SEL2_29 \
498 MOD_SEL0_26_25_24 MOD_SEL1_26 \
501 MOD_SEL0_23 MOD_SEL1_23_22_21 \
505 MOD_SEL0_19 MOD_SEL1_19 \
506 MOD_SEL0_18 MOD_SEL1_18_17 \
508 MOD_SEL0_16_15 MOD_SEL1_16 \
511 MOD_SEL0_13 MOD_SEL1_13 \
512 MOD_SEL0_12 MOD_SEL1_12 \
513 MOD_SEL0_11 MOD_SEL1_11 \
514 MOD_SEL0_10 MOD_SEL1_10 \
515 MOD_SEL0_9 MOD_SEL1_9 \
519 MOD_SEL0_5_4 MOD_SEL1_5 \
521 MOD_SEL0_3 MOD_SEL1_3 \
522 MOD_SEL0_2_1 MOD_SEL1_2 \
524 MOD_SEL1_0 MOD_SEL2_0
535 #define FM(x) FN_##x,
536 PINMUX_FUNCTION_BEGIN
,
546 #define FM(x) x##_MARK,
556 static const u16 pinmux_data
[] = {
557 PINMUX_DATA_GP_ALL(),
561 PINMUX_SINGLE(HDMI0_CEC
),
562 PINMUX_SINGLE(HDMI1_CEC
),
563 PINMUX_SINGLE(I2C_SEL_0_1
),
564 PINMUX_SINGLE(I2C_SEL_3_1
),
565 PINMUX_SINGLE(I2C_SEL_5_1
),
566 PINMUX_SINGLE(MSIOF0_RXD
),
567 PINMUX_SINGLE(MSIOF0_SCK
),
568 PINMUX_SINGLE(MSIOF0_TXD
),
569 PINMUX_SINGLE(SD2_CMD
),
570 PINMUX_SINGLE(SD3_CLK
),
571 PINMUX_SINGLE(SD3_CMD
),
572 PINMUX_SINGLE(SD3_DAT0
),
573 PINMUX_SINGLE(SD3_DAT1
),
574 PINMUX_SINGLE(SD3_DAT2
),
575 PINMUX_SINGLE(SD3_DAT3
),
576 PINMUX_SINGLE(SD3_DS
),
577 PINMUX_SINGLE(SSI_SCK5
),
578 PINMUX_SINGLE(SSI_SDATA5
),
579 PINMUX_SINGLE(SSI_WS5
),
582 PINMUX_IPSR_GPSR(IP0_3_0
, AVB_MDC
),
583 PINMUX_IPSR_MSEL(IP0_3_0
, MSIOF2_SS2_C
, SEL_MSIOF2_2
),
585 PINMUX_IPSR_GPSR(IP0_7_4
, AVB_MAGIC
),
586 PINMUX_IPSR_MSEL(IP0_7_4
, MSIOF2_SS1_C
, SEL_MSIOF2_2
),
587 PINMUX_IPSR_MSEL(IP0_7_4
, SCK4_A
, SEL_SCIF4_0
),
589 PINMUX_IPSR_GPSR(IP0_11_8
, AVB_PHY_INT
),
590 PINMUX_IPSR_MSEL(IP0_11_8
, MSIOF2_SYNC_C
, SEL_MSIOF2_2
),
591 PINMUX_IPSR_MSEL(IP0_11_8
, RX4_A
, SEL_SCIF4_0
),
593 PINMUX_IPSR_GPSR(IP0_15_12
, AVB_LINK
),
594 PINMUX_IPSR_MSEL(IP0_15_12
, MSIOF2_SCK_C
, SEL_MSIOF2_2
),
595 PINMUX_IPSR_MSEL(IP0_15_12
, TX4_A
, SEL_SCIF4_0
),
597 PINMUX_IPSR_MSEL(IP0_19_16
, AVB_AVTP_MATCH_A
, SEL_ETHERAVB_0
),
598 PINMUX_IPSR_MSEL(IP0_19_16
, MSIOF2_RXD_C
, SEL_MSIOF2_2
),
599 PINMUX_IPSR_MSEL(IP0_19_16
, CTS4_N_A
, SEL_SCIF4_0
),
601 PINMUX_IPSR_MSEL(IP0_23_20
, AVB_AVTP_CAPTURE_A
, SEL_ETHERAVB_0
),
602 PINMUX_IPSR_MSEL(IP0_23_20
, MSIOF2_TXD_C
, SEL_MSIOF2_2
),
603 PINMUX_IPSR_MSEL(IP0_23_20
, RTS4_N_TANS_A
, SEL_SCIF4_0
),
605 PINMUX_IPSR_GPSR(IP0_27_24
, IRQ0
),
606 PINMUX_IPSR_GPSR(IP0_27_24
, QPOLB
),
607 PINMUX_IPSR_GPSR(IP0_27_24
, DU_CDE
),
608 PINMUX_IPSR_MSEL(IP0_27_24
, VI4_DATA0_B
, SEL_VIN4_1
),
609 PINMUX_IPSR_MSEL(IP0_27_24
, CAN0_TX_B
, SEL_RCAN0_1
),
610 PINMUX_IPSR_MSEL(IP0_27_24
, CANFD0_TX_B
, SEL_CANFD0_1
),
612 PINMUX_IPSR_GPSR(IP0_31_28
, IRQ1
),
613 PINMUX_IPSR_GPSR(IP0_31_28
, QPOLA
),
614 PINMUX_IPSR_GPSR(IP0_31_28
, DU_DISP
),
615 PINMUX_IPSR_MSEL(IP0_31_28
, VI4_DATA1_B
, SEL_VIN4_1
),
616 PINMUX_IPSR_MSEL(IP0_31_28
, CAN0_RX_B
, SEL_RCAN0_1
),
617 PINMUX_IPSR_MSEL(IP0_31_28
, CANFD0_RX_B
, SEL_CANFD0_1
),
620 PINMUX_IPSR_GPSR(IP1_3_0
, IRQ2
),
621 PINMUX_IPSR_GPSR(IP1_3_0
, QCPV_QDE
),
622 PINMUX_IPSR_GPSR(IP1_3_0
, DU_EXODDF_DU_ODDF_DISP_CDE
),
623 PINMUX_IPSR_MSEL(IP1_3_0
, VI4_DATA2_B
, SEL_VIN4_1
),
624 PINMUX_IPSR_MSEL(IP1_3_0
, PWM3_B
, SEL_PWM3_1
),
626 PINMUX_IPSR_GPSR(IP1_7_4
, IRQ3
),
627 PINMUX_IPSR_GPSR(IP1_7_4
, QSTVB_QVE
),
628 PINMUX_IPSR_GPSR(IP1_7_4
, A25
),
629 PINMUX_IPSR_GPSR(IP1_7_4
, DU_DOTCLKOUT1
),
630 PINMUX_IPSR_MSEL(IP1_7_4
, VI4_DATA3_B
, SEL_VIN4_1
),
631 PINMUX_IPSR_MSEL(IP1_7_4
, PWM4_B
, SEL_PWM4_1
),
633 PINMUX_IPSR_GPSR(IP1_11_8
, IRQ4
),
634 PINMUX_IPSR_GPSR(IP1_11_8
, QSTH_QHS
),
635 PINMUX_IPSR_GPSR(IP1_11_8
, A24
),
636 PINMUX_IPSR_GPSR(IP1_11_8
, DU_EXHSYNC_DU_HSYNC
),
637 PINMUX_IPSR_MSEL(IP1_11_8
, VI4_DATA4_B
, SEL_VIN4_1
),
638 PINMUX_IPSR_MSEL(IP1_11_8
, PWM5_B
, SEL_PWM5_1
),
640 PINMUX_IPSR_GPSR(IP1_15_12
, IRQ5
),
641 PINMUX_IPSR_GPSR(IP1_15_12
, QSTB_QHE
),
642 PINMUX_IPSR_GPSR(IP1_15_12
, A23
),
643 PINMUX_IPSR_GPSR(IP1_15_12
, DU_EXVSYNC_DU_VSYNC
),
644 PINMUX_IPSR_MSEL(IP1_15_12
, VI4_DATA5_B
, SEL_VIN4_1
),
645 PINMUX_IPSR_MSEL(IP1_15_12
, PWM6_B
, SEL_PWM6_1
),
647 PINMUX_IPSR_GPSR(IP1_19_16
, PWM0
),
648 PINMUX_IPSR_GPSR(IP1_19_16
, AVB_AVTP_PPS
),
649 PINMUX_IPSR_GPSR(IP1_19_16
, A22
),
650 PINMUX_IPSR_MSEL(IP1_19_16
, VI4_DATA6_B
, SEL_VIN4_1
),
651 PINMUX_IPSR_MSEL(IP1_19_16
, IECLK_B
, SEL_IEBUS_1
),
653 PINMUX_IPSR_MSEL(IP1_23_20
, PWM1_A
, SEL_PWM1_0
),
654 PINMUX_IPSR_GPSR(IP1_23_20
, A21
),
655 PINMUX_IPSR_MSEL(IP1_23_20
, HRX3_D
, SEL_HSCIF3_3
),
656 PINMUX_IPSR_MSEL(IP1_23_20
, VI4_DATA7_B
, SEL_VIN4_1
),
657 PINMUX_IPSR_MSEL(IP1_23_20
, IERX_B
, SEL_IEBUS_1
),
659 PINMUX_IPSR_MSEL(IP1_27_24
, PWM2_A
, SEL_PWM2_0
),
660 PINMUX_IPSR_GPSR(IP1_27_24
, A20
),
661 PINMUX_IPSR_MSEL(IP1_27_24
, HTX3_D
, SEL_HSCIF3_3
),
662 PINMUX_IPSR_MSEL(IP1_27_24
, IETX_B
, SEL_IEBUS_1
),
664 PINMUX_IPSR_GPSR(IP1_31_28
, A0
),
665 PINMUX_IPSR_GPSR(IP1_31_28
, LCDOUT16
),
666 PINMUX_IPSR_MSEL(IP1_31_28
, MSIOF3_SYNC_B
, SEL_MSIOF3_1
),
667 PINMUX_IPSR_GPSR(IP1_31_28
, VI4_DATA8
),
668 PINMUX_IPSR_GPSR(IP1_31_28
, DU_DB0
),
669 PINMUX_IPSR_MSEL(IP1_31_28
, PWM3_A
, SEL_PWM3_0
),
672 PINMUX_IPSR_GPSR(IP2_3_0
, A1
),
673 PINMUX_IPSR_GPSR(IP2_3_0
, LCDOUT17
),
674 PINMUX_IPSR_MSEL(IP2_3_0
, MSIOF3_TXD_B
, SEL_MSIOF3_1
),
675 PINMUX_IPSR_GPSR(IP2_3_0
, VI4_DATA9
),
676 PINMUX_IPSR_GPSR(IP2_3_0
, DU_DB1
),
677 PINMUX_IPSR_MSEL(IP2_3_0
, PWM4_A
, SEL_PWM4_0
),
679 PINMUX_IPSR_GPSR(IP2_7_4
, A2
),
680 PINMUX_IPSR_GPSR(IP2_7_4
, LCDOUT18
),
681 PINMUX_IPSR_MSEL(IP2_7_4
, MSIOF3_SCK_B
, SEL_MSIOF3_1
),
682 PINMUX_IPSR_GPSR(IP2_7_4
, VI4_DATA10
),
683 PINMUX_IPSR_GPSR(IP2_7_4
, DU_DB2
),
684 PINMUX_IPSR_MSEL(IP2_7_4
, PWM5_A
, SEL_PWM5_0
),
686 PINMUX_IPSR_GPSR(IP2_11_8
, A3
),
687 PINMUX_IPSR_GPSR(IP2_11_8
, LCDOUT19
),
688 PINMUX_IPSR_MSEL(IP2_11_8
, MSIOF3_RXD_B
, SEL_MSIOF3_1
),
689 PINMUX_IPSR_GPSR(IP2_11_8
, VI4_DATA11
),
690 PINMUX_IPSR_GPSR(IP2_11_8
, DU_DB3
),
691 PINMUX_IPSR_MSEL(IP2_11_8
, PWM6_A
, SEL_PWM6_0
),
693 PINMUX_IPSR_GPSR(IP2_15_12
, A4
),
694 PINMUX_IPSR_GPSR(IP2_15_12
, LCDOUT20
),
695 PINMUX_IPSR_MSEL(IP2_15_12
, MSIOF3_SS1_B
, SEL_MSIOF3_1
),
696 PINMUX_IPSR_GPSR(IP2_15_12
, VI4_DATA12
),
697 PINMUX_IPSR_GPSR(IP2_15_12
, VI5_DATA12
),
698 PINMUX_IPSR_GPSR(IP2_15_12
, DU_DB4
),
700 PINMUX_IPSR_GPSR(IP2_19_16
, A5
),
701 PINMUX_IPSR_GPSR(IP2_19_16
, LCDOUT21
),
702 PINMUX_IPSR_MSEL(IP2_19_16
, MSIOF3_SS2_B
, SEL_MSIOF3_1
),
703 PINMUX_IPSR_MSEL(IP2_19_16
, SCK4_B
, SEL_SCIF4_1
),
704 PINMUX_IPSR_GPSR(IP2_19_16
, VI4_DATA13
),
705 PINMUX_IPSR_GPSR(IP2_19_16
, VI5_DATA13
),
706 PINMUX_IPSR_GPSR(IP2_19_16
, DU_DB5
),
708 PINMUX_IPSR_GPSR(IP2_23_20
, A6
),
709 PINMUX_IPSR_GPSR(IP2_23_20
, LCDOUT22
),
710 PINMUX_IPSR_MSEL(IP2_23_20
, MSIOF2_SS1_A
, SEL_MSIOF2_0
),
711 PINMUX_IPSR_MSEL(IP2_23_20
, RX4_B
, SEL_SCIF4_1
),
712 PINMUX_IPSR_GPSR(IP2_23_20
, VI4_DATA14
),
713 PINMUX_IPSR_GPSR(IP2_23_20
, VI5_DATA14
),
714 PINMUX_IPSR_GPSR(IP2_23_20
, DU_DB6
),
716 PINMUX_IPSR_GPSR(IP2_27_24
, A7
),
717 PINMUX_IPSR_GPSR(IP2_27_24
, LCDOUT23
),
718 PINMUX_IPSR_MSEL(IP2_27_24
, MSIOF2_SS2_A
, SEL_MSIOF2_0
),
719 PINMUX_IPSR_MSEL(IP2_27_24
, TX4_B
, SEL_SCIF4_1
),
720 PINMUX_IPSR_GPSR(IP2_27_24
, VI4_DATA15
),
721 PINMUX_IPSR_GPSR(IP2_27_24
, VI5_DATA15
),
722 PINMUX_IPSR_GPSR(IP2_27_24
, DU_DB7
),
724 PINMUX_IPSR_GPSR(IP2_31_28
, A8
),
725 PINMUX_IPSR_MSEL(IP2_31_28
, RX3_B
, SEL_SCIF3_1
),
726 PINMUX_IPSR_MSEL(IP2_31_28
, MSIOF2_SYNC_A
, SEL_MSIOF2_0
),
727 PINMUX_IPSR_MSEL(IP2_31_28
, HRX4_B
, SEL_HSCIF4_1
),
728 PINMUX_IPSR_MSEL(IP2_31_28
, SDA6_A
, SEL_I2C6_0
),
729 PINMUX_IPSR_MSEL(IP2_31_28
, AVB_AVTP_MATCH_B
, SEL_ETHERAVB_1
),
730 PINMUX_IPSR_MSEL(IP2_31_28
, PWM1_B
, SEL_PWM1_1
),
733 PINMUX_IPSR_GPSR(IP3_3_0
, A9
),
734 PINMUX_IPSR_MSEL(IP3_3_0
, MSIOF2_SCK_A
, SEL_MSIOF2_0
),
735 PINMUX_IPSR_MSEL(IP3_3_0
, CTS4_N_B
, SEL_SCIF4_1
),
736 PINMUX_IPSR_GPSR(IP3_3_0
, VI5_VSYNC_N
),
738 PINMUX_IPSR_GPSR(IP3_7_4
, A10
),
739 PINMUX_IPSR_MSEL(IP3_7_4
, MSIOF2_RXD_A
, SEL_MSIOF2_0
),
740 PINMUX_IPSR_MSEL(IP3_7_4
, RTS4_N_TANS_B
, SEL_SCIF4_1
),
741 PINMUX_IPSR_GPSR(IP3_7_4
, VI5_HSYNC_N
),
743 PINMUX_IPSR_GPSR(IP3_11_8
, A11
),
744 PINMUX_IPSR_MSEL(IP3_11_8
, TX3_B
, SEL_SCIF3_1
),
745 PINMUX_IPSR_MSEL(IP3_11_8
, MSIOF2_TXD_A
, SEL_MSIOF2_0
),
746 PINMUX_IPSR_MSEL(IP3_11_8
, HTX4_B
, SEL_HSCIF4_1
),
747 PINMUX_IPSR_GPSR(IP3_11_8
, HSCK4
),
748 PINMUX_IPSR_GPSR(IP3_11_8
, VI5_FIELD
),
749 PINMUX_IPSR_MSEL(IP3_11_8
, SCL6_A
, SEL_I2C6_0
),
750 PINMUX_IPSR_MSEL(IP3_11_8
, AVB_AVTP_CAPTURE_B
, SEL_ETHERAVB_1
),
751 PINMUX_IPSR_MSEL(IP3_11_8
, PWM2_B
, SEL_PWM2_1
),
753 PINMUX_IPSR_GPSR(IP3_15_12
, A12
),
754 PINMUX_IPSR_GPSR(IP3_15_12
, LCDOUT12
),
755 PINMUX_IPSR_MSEL(IP3_15_12
, MSIOF3_SCK_C
, SEL_MSIOF3_2
),
756 PINMUX_IPSR_MSEL(IP3_15_12
, HRX4_A
, SEL_HSCIF4_0
),
757 PINMUX_IPSR_GPSR(IP3_15_12
, VI5_DATA8
),
758 PINMUX_IPSR_GPSR(IP3_15_12
, DU_DG4
),
760 PINMUX_IPSR_GPSR(IP3_19_16
, A13
),
761 PINMUX_IPSR_GPSR(IP3_19_16
, LCDOUT13
),
762 PINMUX_IPSR_MSEL(IP3_19_16
, MSIOF3_SYNC_C
, SEL_MSIOF3_2
),
763 PINMUX_IPSR_MSEL(IP3_19_16
, HTX4_A
, SEL_HSCIF4_0
),
764 PINMUX_IPSR_GPSR(IP3_19_16
, VI5_DATA9
),
765 PINMUX_IPSR_GPSR(IP3_19_16
, DU_DG5
),
767 PINMUX_IPSR_GPSR(IP3_23_20
, A14
),
768 PINMUX_IPSR_GPSR(IP3_23_20
, LCDOUT14
),
769 PINMUX_IPSR_MSEL(IP3_23_20
, MSIOF3_RXD_C
, SEL_MSIOF3_2
),
770 PINMUX_IPSR_GPSR(IP3_23_20
, HCTS4_N
),
771 PINMUX_IPSR_GPSR(IP3_23_20
, VI5_DATA10
),
772 PINMUX_IPSR_GPSR(IP3_23_20
, DU_DG6
),
774 PINMUX_IPSR_GPSR(IP3_27_24
, A15
),
775 PINMUX_IPSR_GPSR(IP3_27_24
, LCDOUT15
),
776 PINMUX_IPSR_MSEL(IP3_27_24
, MSIOF3_TXD_C
, SEL_MSIOF3_2
),
777 PINMUX_IPSR_GPSR(IP3_27_24
, HRTS4_N
),
778 PINMUX_IPSR_GPSR(IP3_27_24
, VI5_DATA11
),
779 PINMUX_IPSR_GPSR(IP3_27_24
, DU_DG7
),
781 PINMUX_IPSR_GPSR(IP3_31_28
, A16
),
782 PINMUX_IPSR_GPSR(IP3_31_28
, LCDOUT8
),
783 PINMUX_IPSR_GPSR(IP3_31_28
, VI4_FIELD
),
784 PINMUX_IPSR_GPSR(IP3_31_28
, DU_DG0
),
787 PINMUX_IPSR_GPSR(IP4_3_0
, A17
),
788 PINMUX_IPSR_GPSR(IP4_3_0
, LCDOUT9
),
789 PINMUX_IPSR_GPSR(IP4_3_0
, VI4_VSYNC_N
),
790 PINMUX_IPSR_GPSR(IP4_3_0
, DU_DG1
),
792 PINMUX_IPSR_GPSR(IP4_7_4
, A18
),
793 PINMUX_IPSR_GPSR(IP4_7_4
, LCDOUT10
),
794 PINMUX_IPSR_GPSR(IP4_7_4
, VI4_HSYNC_N
),
795 PINMUX_IPSR_GPSR(IP4_7_4
, DU_DG2
),
797 PINMUX_IPSR_GPSR(IP4_11_8
, A19
),
798 PINMUX_IPSR_GPSR(IP4_11_8
, LCDOUT11
),
799 PINMUX_IPSR_GPSR(IP4_11_8
, VI4_CLKENB
),
800 PINMUX_IPSR_GPSR(IP4_11_8
, DU_DG3
),
802 PINMUX_IPSR_GPSR(IP4_15_12
, CS0_N
),
803 PINMUX_IPSR_GPSR(IP4_15_12
, VI5_CLKENB
),
805 PINMUX_IPSR_GPSR(IP4_19_16
, CS1_N_A26
),
806 PINMUX_IPSR_GPSR(IP4_19_16
, VI5_CLK
),
807 PINMUX_IPSR_MSEL(IP4_19_16
, EX_WAIT0_B
, SEL_LBSC_1
),
809 PINMUX_IPSR_GPSR(IP4_23_20
, BS_N
),
810 PINMUX_IPSR_GPSR(IP4_23_20
, QSTVA_QVS
),
811 PINMUX_IPSR_MSEL(IP4_23_20
, MSIOF3_SCK_D
, SEL_MSIOF3_3
),
812 PINMUX_IPSR_GPSR(IP4_23_20
, SCK3
),
813 PINMUX_IPSR_GPSR(IP4_23_20
, HSCK3
),
814 PINMUX_IPSR_GPSR(IP4_23_20
, CAN1_TX
),
815 PINMUX_IPSR_GPSR(IP4_23_20
, CANFD1_TX
),
816 PINMUX_IPSR_MSEL(IP4_23_20
, IETX_A
, SEL_IEBUS_0
),
818 PINMUX_IPSR_GPSR(IP4_27_24
, RD_N
),
819 PINMUX_IPSR_MSEL(IP4_27_24
, MSIOF3_SYNC_D
, SEL_MSIOF3_3
),
820 PINMUX_IPSR_MSEL(IP4_27_24
, RX3_A
, SEL_SCIF3_0
),
821 PINMUX_IPSR_MSEL(IP4_27_24
, HRX3_A
, SEL_HSCIF3_0
),
822 PINMUX_IPSR_MSEL(IP4_27_24
, CAN0_TX_A
, SEL_RCAN0_0
),
823 PINMUX_IPSR_MSEL(IP4_27_24
, CANFD0_TX_A
, SEL_CANFD0_0
),
825 PINMUX_IPSR_GPSR(IP4_31_28
, RD_WR_N
),
826 PINMUX_IPSR_MSEL(IP4_31_28
, MSIOF3_RXD_D
, SEL_MSIOF3_3
),
827 PINMUX_IPSR_MSEL(IP4_31_28
, TX3_A
, SEL_SCIF3_0
),
828 PINMUX_IPSR_MSEL(IP4_31_28
, HTX3_A
, SEL_HSCIF3_0
),
829 PINMUX_IPSR_MSEL(IP4_31_28
, CAN0_RX_A
, SEL_RCAN0_0
),
830 PINMUX_IPSR_MSEL(IP4_31_28
, CANFD0_RX_A
, SEL_CANFD0_0
),
833 PINMUX_IPSR_GPSR(IP5_3_0
, WE0_N
),
834 PINMUX_IPSR_MSEL(IP5_3_0
, MSIOF3_TXD_D
, SEL_MSIOF3_3
),
835 PINMUX_IPSR_GPSR(IP5_3_0
, CTS3_N
),
836 PINMUX_IPSR_GPSR(IP5_3_0
, HCTS3_N
),
837 PINMUX_IPSR_MSEL(IP5_3_0
, SCL6_B
, SEL_I2C6_1
),
838 PINMUX_IPSR_GPSR(IP5_3_0
, CAN_CLK
),
839 PINMUX_IPSR_MSEL(IP5_3_0
, IECLK_A
, SEL_IEBUS_0
),
841 PINMUX_IPSR_GPSR(IP5_7_4
, WE1_N
),
842 PINMUX_IPSR_MSEL(IP5_7_4
, MSIOF3_SS1_D
, SEL_MSIOF3_3
),
843 PINMUX_IPSR_GPSR(IP5_7_4
, RTS3_N_TANS
),
844 PINMUX_IPSR_GPSR(IP5_7_4
, HRTS3_N
),
845 PINMUX_IPSR_MSEL(IP5_7_4
, SDA6_B
, SEL_I2C6_1
),
846 PINMUX_IPSR_GPSR(IP5_7_4
, CAN1_RX
),
847 PINMUX_IPSR_GPSR(IP5_7_4
, CANFD1_RX
),
848 PINMUX_IPSR_MSEL(IP5_7_4
, IERX_A
, SEL_IEBUS_0
),
850 PINMUX_IPSR_MSEL(IP5_11_8
, EX_WAIT0_A
, SEL_LBSC_0
),
851 PINMUX_IPSR_GPSR(IP5_11_8
, QCLK
),
852 PINMUX_IPSR_GPSR(IP5_11_8
, VI4_CLK
),
853 PINMUX_IPSR_GPSR(IP5_11_8
, DU_DOTCLKOUT0
),
855 PINMUX_IPSR_GPSR(IP5_15_12
, D0
),
856 PINMUX_IPSR_MSEL(IP5_15_12
, MSIOF2_SS1_B
, SEL_MSIOF2_1
),
857 PINMUX_IPSR_MSEL(IP5_15_12
, MSIOF3_SCK_A
, SEL_MSIOF3_0
),
858 PINMUX_IPSR_GPSR(IP5_15_12
, VI4_DATA16
),
859 PINMUX_IPSR_GPSR(IP5_15_12
, VI5_DATA0
),
861 PINMUX_IPSR_GPSR(IP5_19_16
, D1
),
862 PINMUX_IPSR_MSEL(IP5_19_16
, MSIOF2_SS2_B
, SEL_MSIOF2_1
),
863 PINMUX_IPSR_MSEL(IP5_19_16
, MSIOF3_SYNC_A
, SEL_MSIOF3_0
),
864 PINMUX_IPSR_GPSR(IP5_19_16
, VI4_DATA17
),
865 PINMUX_IPSR_GPSR(IP5_19_16
, VI5_DATA1
),
867 PINMUX_IPSR_GPSR(IP5_23_20
, D2
),
868 PINMUX_IPSR_MSEL(IP5_23_20
, MSIOF3_RXD_A
, SEL_MSIOF3_0
),
869 PINMUX_IPSR_GPSR(IP5_23_20
, VI4_DATA18
),
870 PINMUX_IPSR_GPSR(IP5_23_20
, VI5_DATA2
),
872 PINMUX_IPSR_GPSR(IP5_27_24
, D3
),
873 PINMUX_IPSR_MSEL(IP5_27_24
, MSIOF3_TXD_A
, SEL_MSIOF3_0
),
874 PINMUX_IPSR_GPSR(IP5_27_24
, VI4_DATA19
),
875 PINMUX_IPSR_GPSR(IP5_27_24
, VI5_DATA3
),
877 PINMUX_IPSR_GPSR(IP5_31_28
, D4
),
878 PINMUX_IPSR_MSEL(IP5_31_28
, MSIOF2_SCK_B
, SEL_MSIOF2_1
),
879 PINMUX_IPSR_GPSR(IP5_31_28
, VI4_DATA20
),
880 PINMUX_IPSR_GPSR(IP5_31_28
, VI5_DATA4
),
883 PINMUX_IPSR_GPSR(IP6_3_0
, D5
),
884 PINMUX_IPSR_MSEL(IP6_3_0
, MSIOF2_SYNC_B
, SEL_MSIOF2_1
),
885 PINMUX_IPSR_GPSR(IP6_3_0
, VI4_DATA21
),
886 PINMUX_IPSR_GPSR(IP6_3_0
, VI5_DATA5
),
888 PINMUX_IPSR_GPSR(IP6_7_4
, D6
),
889 PINMUX_IPSR_MSEL(IP6_7_4
, MSIOF2_RXD_B
, SEL_MSIOF2_1
),
890 PINMUX_IPSR_GPSR(IP6_7_4
, VI4_DATA22
),
891 PINMUX_IPSR_GPSR(IP6_7_4
, VI5_DATA6
),
893 PINMUX_IPSR_GPSR(IP6_11_8
, D7
),
894 PINMUX_IPSR_MSEL(IP6_11_8
, MSIOF2_TXD_B
, SEL_MSIOF2_1
),
895 PINMUX_IPSR_GPSR(IP6_11_8
, VI4_DATA23
),
896 PINMUX_IPSR_GPSR(IP6_11_8
, VI5_DATA7
),
898 PINMUX_IPSR_GPSR(IP6_15_12
, D8
),
899 PINMUX_IPSR_GPSR(IP6_15_12
, LCDOUT0
),
900 PINMUX_IPSR_MSEL(IP6_15_12
, MSIOF2_SCK_D
, SEL_MSIOF2_3
),
901 PINMUX_IPSR_MSEL(IP6_15_12
, SCK4_C
, SEL_SCIF4_2
),
902 PINMUX_IPSR_MSEL(IP6_15_12
, VI4_DATA0_A
, SEL_VIN4_0
),
903 PINMUX_IPSR_GPSR(IP6_15_12
, DU_DR0
),
905 PINMUX_IPSR_GPSR(IP6_19_16
, D9
),
906 PINMUX_IPSR_GPSR(IP6_19_16
, LCDOUT1
),
907 PINMUX_IPSR_MSEL(IP6_19_16
, MSIOF2_SYNC_D
, SEL_MSIOF2_3
),
908 PINMUX_IPSR_MSEL(IP6_19_16
, VI4_DATA1_A
, SEL_VIN4_0
),
909 PINMUX_IPSR_GPSR(IP6_19_16
, DU_DR1
),
911 PINMUX_IPSR_GPSR(IP6_23_20
, D10
),
912 PINMUX_IPSR_GPSR(IP6_23_20
, LCDOUT2
),
913 PINMUX_IPSR_MSEL(IP6_23_20
, MSIOF2_RXD_D
, SEL_MSIOF2_3
),
914 PINMUX_IPSR_MSEL(IP6_23_20
, HRX3_B
, SEL_HSCIF3_1
),
915 PINMUX_IPSR_MSEL(IP6_23_20
, VI4_DATA2_A
, SEL_VIN4_0
),
916 PINMUX_IPSR_MSEL(IP6_23_20
, CTS4_N_C
, SEL_SCIF4_2
),
917 PINMUX_IPSR_GPSR(IP6_23_20
, DU_DR2
),
919 PINMUX_IPSR_GPSR(IP6_27_24
, D11
),
920 PINMUX_IPSR_GPSR(IP6_27_24
, LCDOUT3
),
921 PINMUX_IPSR_MSEL(IP6_27_24
, MSIOF2_TXD_D
, SEL_MSIOF2_3
),
922 PINMUX_IPSR_MSEL(IP6_27_24
, HTX3_B
, SEL_HSCIF3_1
),
923 PINMUX_IPSR_MSEL(IP6_27_24
, VI4_DATA3_A
, SEL_VIN4_0
),
924 PINMUX_IPSR_MSEL(IP6_27_24
, RTS4_N_TANS_C
, SEL_SCIF4_2
),
925 PINMUX_IPSR_GPSR(IP6_27_24
, DU_DR3
),
927 PINMUX_IPSR_GPSR(IP6_31_28
, D12
),
928 PINMUX_IPSR_GPSR(IP6_31_28
, LCDOUT4
),
929 PINMUX_IPSR_MSEL(IP6_31_28
, MSIOF2_SS1_D
, SEL_MSIOF2_3
),
930 PINMUX_IPSR_MSEL(IP6_31_28
, RX4_C
, SEL_SCIF4_2
),
931 PINMUX_IPSR_MSEL(IP6_31_28
, VI4_DATA4_A
, SEL_VIN4_0
),
932 PINMUX_IPSR_GPSR(IP6_31_28
, DU_DR4
),
935 PINMUX_IPSR_GPSR(IP7_3_0
, D13
),
936 PINMUX_IPSR_GPSR(IP7_3_0
, LCDOUT5
),
937 PINMUX_IPSR_MSEL(IP7_3_0
, MSIOF2_SS2_D
, SEL_MSIOF2_3
),
938 PINMUX_IPSR_MSEL(IP7_3_0
, TX4_C
, SEL_SCIF4_2
),
939 PINMUX_IPSR_MSEL(IP7_3_0
, VI4_DATA5_A
, SEL_VIN4_0
),
940 PINMUX_IPSR_GPSR(IP7_3_0
, DU_DR5
),
942 PINMUX_IPSR_GPSR(IP7_7_4
, D14
),
943 PINMUX_IPSR_GPSR(IP7_7_4
, LCDOUT6
),
944 PINMUX_IPSR_MSEL(IP7_7_4
, MSIOF3_SS1_A
, SEL_MSIOF3_0
),
945 PINMUX_IPSR_MSEL(IP7_7_4
, HRX3_C
, SEL_HSCIF3_2
),
946 PINMUX_IPSR_MSEL(IP7_7_4
, VI4_DATA6_A
, SEL_VIN4_0
),
947 PINMUX_IPSR_GPSR(IP7_7_4
, DU_DR6
),
948 PINMUX_IPSR_MSEL(IP7_7_4
, SCL6_C
, SEL_I2C6_2
),
950 PINMUX_IPSR_GPSR(IP7_11_8
, D15
),
951 PINMUX_IPSR_GPSR(IP7_11_8
, LCDOUT7
),
952 PINMUX_IPSR_MSEL(IP7_11_8
, MSIOF3_SS2_A
, SEL_MSIOF3_0
),
953 PINMUX_IPSR_MSEL(IP7_11_8
, HTX3_C
, SEL_HSCIF3_2
),
954 PINMUX_IPSR_MSEL(IP7_11_8
, VI4_DATA7_A
, SEL_VIN4_0
),
955 PINMUX_IPSR_GPSR(IP7_11_8
, DU_DR7
),
956 PINMUX_IPSR_MSEL(IP7_11_8
, SDA6_C
, SEL_I2C6_2
),
958 PINMUX_IPSR_GPSR(IP7_15_12
, FSCLKST
),
960 PINMUX_IPSR_GPSR(IP7_19_16
, SD0_CLK
),
961 PINMUX_IPSR_MSEL(IP7_19_16
, MSIOF1_SCK_E
, SEL_MSIOF1_4
),
962 PINMUX_IPSR_MSEL(IP7_19_16
, STP_OPWM_0_B
, SEL_SSP1_0_1
),
964 PINMUX_IPSR_GPSR(IP7_23_20
, SD0_CMD
),
965 PINMUX_IPSR_MSEL(IP7_23_20
, MSIOF1_SYNC_E
, SEL_MSIOF1_4
),
966 PINMUX_IPSR_MSEL(IP7_23_20
, STP_IVCXO27_0_B
, SEL_SSP1_0_1
),
968 PINMUX_IPSR_GPSR(IP7_27_24
, SD0_DAT0
),
969 PINMUX_IPSR_MSEL(IP7_27_24
, MSIOF1_RXD_E
, SEL_MSIOF1_4
),
970 PINMUX_IPSR_MSEL(IP7_27_24
, TS_SCK0_B
, SEL_TSIF0_1
),
971 PINMUX_IPSR_MSEL(IP7_27_24
, STP_ISCLK_0_B
, SEL_SSP1_0_1
),
973 PINMUX_IPSR_GPSR(IP7_31_28
, SD0_DAT1
),
974 PINMUX_IPSR_MSEL(IP7_31_28
, MSIOF1_TXD_E
, SEL_MSIOF1_4
),
975 PINMUX_IPSR_MSEL(IP7_31_28
, TS_SPSYNC0_B
, SEL_TSIF0_1
),
976 PINMUX_IPSR_MSEL(IP7_31_28
, STP_ISSYNC_0_B
, SEL_SSP1_0_1
),
979 PINMUX_IPSR_GPSR(IP8_3_0
, SD0_DAT2
),
980 PINMUX_IPSR_MSEL(IP8_3_0
, MSIOF1_SS1_E
, SEL_MSIOF1_4
),
981 PINMUX_IPSR_MSEL(IP8_3_0
, TS_SDAT0_B
, SEL_TSIF0_1
),
982 PINMUX_IPSR_MSEL(IP8_3_0
, STP_ISD_0_B
, SEL_SSP1_0_1
),
984 PINMUX_IPSR_GPSR(IP8_7_4
, SD0_DAT3
),
985 PINMUX_IPSR_MSEL(IP8_7_4
, MSIOF1_SS2_E
, SEL_MSIOF1_4
),
986 PINMUX_IPSR_MSEL(IP8_7_4
, TS_SDEN0_B
, SEL_TSIF0_1
),
987 PINMUX_IPSR_MSEL(IP8_7_4
, STP_ISEN_0_B
, SEL_SSP1_0_1
),
989 PINMUX_IPSR_GPSR(IP8_11_8
, SD1_CLK
),
990 PINMUX_IPSR_MSEL(IP8_11_8
, MSIOF1_SCK_G
, SEL_MSIOF1_6
),
991 PINMUX_IPSR_MSEL(IP8_11_8
, SIM0_CLK_A
, SEL_SIMCARD_0
),
993 PINMUX_IPSR_GPSR(IP8_15_12
, SD1_CMD
),
994 PINMUX_IPSR_MSEL(IP8_15_12
, MSIOF1_SYNC_G
, SEL_MSIOF1_6
),
995 PINMUX_IPSR_MSEL(IP8_15_12
, SIM0_D_A
, SEL_SIMCARD_0
),
996 PINMUX_IPSR_MSEL(IP8_15_12
, STP_IVCXO27_1_B
, SEL_SSP1_1_1
),
998 PINMUX_IPSR_GPSR(IP8_19_16
, SD1_DAT0
),
999 PINMUX_IPSR_GPSR(IP8_19_16
, SD2_DAT4
),
1000 PINMUX_IPSR_MSEL(IP8_19_16
, MSIOF1_RXD_G
, SEL_MSIOF1_6
),
1001 PINMUX_IPSR_MSEL(IP8_19_16
, TS_SCK1_B
, SEL_TSIF1_1
),
1002 PINMUX_IPSR_MSEL(IP8_19_16
, STP_ISCLK_1_B
, SEL_SSP1_1_1
),
1004 PINMUX_IPSR_GPSR(IP8_23_20
, SD1_DAT1
),
1005 PINMUX_IPSR_GPSR(IP8_23_20
, SD2_DAT5
),
1006 PINMUX_IPSR_MSEL(IP8_23_20
, MSIOF1_TXD_G
, SEL_MSIOF1_6
),
1007 PINMUX_IPSR_MSEL(IP8_23_20
, TS_SPSYNC1_B
, SEL_TSIF1_1
),
1008 PINMUX_IPSR_MSEL(IP8_23_20
, STP_ISSYNC_1_B
, SEL_SSP1_1_1
),
1010 PINMUX_IPSR_GPSR(IP8_27_24
, SD1_DAT2
),
1011 PINMUX_IPSR_GPSR(IP8_27_24
, SD2_DAT6
),
1012 PINMUX_IPSR_MSEL(IP8_27_24
, MSIOF1_SS1_G
, SEL_MSIOF1_6
),
1013 PINMUX_IPSR_MSEL(IP8_27_24
, TS_SDAT1_B
, SEL_TSIF1_1
),
1014 PINMUX_IPSR_MSEL(IP8_27_24
, STP_ISD_1_B
, SEL_SSP1_1_1
),
1016 PINMUX_IPSR_GPSR(IP8_31_28
, SD1_DAT3
),
1017 PINMUX_IPSR_GPSR(IP8_31_28
, SD2_DAT7
),
1018 PINMUX_IPSR_MSEL(IP8_31_28
, MSIOF1_SS2_G
, SEL_MSIOF1_6
),
1019 PINMUX_IPSR_MSEL(IP8_31_28
, TS_SDEN1_B
, SEL_TSIF1_1
),
1020 PINMUX_IPSR_MSEL(IP8_31_28
, STP_ISEN_1_B
, SEL_SSP1_1_1
),
1023 PINMUX_IPSR_GPSR(IP9_3_0
, SD2_CLK
),
1025 PINMUX_IPSR_GPSR(IP9_7_4
, SD2_DAT0
),
1027 PINMUX_IPSR_GPSR(IP9_11_8
, SD2_DAT1
),
1029 PINMUX_IPSR_GPSR(IP9_15_12
, SD2_DAT2
),
1031 PINMUX_IPSR_GPSR(IP9_19_16
, SD2_DAT3
),
1033 PINMUX_IPSR_GPSR(IP9_23_20
, SD2_DS
),
1034 PINMUX_IPSR_MSEL(IP9_23_20
, SATA_DEVSLP_B
, SEL_SATA_1
),
1036 PINMUX_IPSR_GPSR(IP9_27_24
, SD3_DAT4
),
1037 PINMUX_IPSR_MSEL(IP9_27_24
, SD2_CD_A
, SEL_SDHI2_0
),
1039 PINMUX_IPSR_GPSR(IP9_31_28
, SD3_DAT5
),
1040 PINMUX_IPSR_MSEL(IP9_31_28
, SD2_WP_A
, SEL_SDHI2_0
),
1043 PINMUX_IPSR_GPSR(IP10_3_0
, SD3_DAT6
),
1044 PINMUX_IPSR_GPSR(IP10_3_0
, SD3_CD
),
1046 PINMUX_IPSR_GPSR(IP10_7_4
, SD3_DAT7
),
1047 PINMUX_IPSR_GPSR(IP10_7_4
, SD3_WP
),
1049 PINMUX_IPSR_GPSR(IP10_11_8
, SD0_CD
),
1050 PINMUX_IPSR_MSEL(IP10_11_8
, SCL2_B
, SEL_I2C2_1
),
1051 PINMUX_IPSR_MSEL(IP10_11_8
, SIM0_RST_A
, SEL_SIMCARD_0
),
1053 PINMUX_IPSR_GPSR(IP10_15_12
, SD0_WP
),
1054 PINMUX_IPSR_MSEL(IP10_15_12
, SDA2_B
, SEL_I2C2_1
),
1056 PINMUX_IPSR_GPSR(IP10_19_16
, SD1_CD
),
1057 PINMUX_IPSR_MSEL(IP10_19_16
, SIM0_CLK_B
, SEL_SIMCARD_1
),
1059 PINMUX_IPSR_GPSR(IP10_23_20
, SD1_WP
),
1060 PINMUX_IPSR_MSEL(IP10_23_20
, SIM0_D_B
, SEL_SIMCARD_1
),
1062 PINMUX_IPSR_GPSR(IP10_27_24
, SCK0
),
1063 PINMUX_IPSR_MSEL(IP10_27_24
, HSCK1_B
, SEL_HSCIF1_1
),
1064 PINMUX_IPSR_MSEL(IP10_27_24
, MSIOF1_SS2_B
, SEL_MSIOF1_1
),
1065 PINMUX_IPSR_MSEL(IP10_27_24
, AUDIO_CLKC_B
, SEL_ADG_1
),
1066 PINMUX_IPSR_MSEL(IP10_27_24
, SDA2_A
, SEL_I2C2_0
),
1067 PINMUX_IPSR_MSEL(IP10_27_24
, SIM0_RST_B
, SEL_SIMCARD_1
),
1068 PINMUX_IPSR_MSEL(IP10_27_24
, STP_OPWM_0_C
, SEL_SSP1_0_2
),
1069 PINMUX_IPSR_MSEL(IP10_27_24
, RIF0_CLK_B
, SEL_DRIF0_1
),
1070 PINMUX_IPSR_GPSR(IP10_27_24
, ADICHS2
),
1072 PINMUX_IPSR_GPSR(IP10_31_28
, RX0
),
1073 PINMUX_IPSR_MSEL(IP10_31_28
, HRX1_B
, SEL_HSCIF1_1
),
1074 PINMUX_IPSR_MSEL(IP10_31_28
, TS_SCK0_C
, SEL_TSIF0_2
),
1075 PINMUX_IPSR_MSEL(IP10_31_28
, STP_ISCLK_0_C
, SEL_SSP1_0_2
),
1076 PINMUX_IPSR_MSEL(IP10_31_28
, RIF0_D0_B
, SEL_DRIF0_1
),
1079 PINMUX_IPSR_GPSR(IP11_3_0
, TX0
),
1080 PINMUX_IPSR_MSEL(IP11_3_0
, HTX1_B
, SEL_HSCIF1_1
),
1081 PINMUX_IPSR_MSEL(IP11_3_0
, TS_SPSYNC0_C
, SEL_TSIF0_2
),
1082 PINMUX_IPSR_MSEL(IP11_3_0
, STP_ISSYNC_0_C
, SEL_SSP1_0_2
),
1083 PINMUX_IPSR_MSEL(IP11_3_0
, RIF0_D1_B
, SEL_DRIF0_1
),
1085 PINMUX_IPSR_GPSR(IP11_7_4
, CTS0_N
),
1086 PINMUX_IPSR_MSEL(IP11_7_4
, HCTS1_N_B
, SEL_HSCIF1_1
),
1087 PINMUX_IPSR_MSEL(IP11_7_4
, MSIOF1_SYNC_B
, SEL_MSIOF1_1
),
1088 PINMUX_IPSR_MSEL(IP11_7_4
, TS_SPSYNC1_C
, SEL_TSIF1_2
),
1089 PINMUX_IPSR_MSEL(IP11_7_4
, STP_ISSYNC_1_C
, SEL_SSP1_1_2
),
1090 PINMUX_IPSR_MSEL(IP11_7_4
, RIF1_SYNC_B
, SEL_DRIF1_1
),
1091 PINMUX_IPSR_MSEL(IP11_7_4
, AUDIO_CLKOUT_C
, SEL_ADG_2
),
1092 PINMUX_IPSR_GPSR(IP11_7_4
, ADICS_SAMP
),
1094 PINMUX_IPSR_GPSR(IP11_11_8
, RTS0_N_TANS
),
1095 PINMUX_IPSR_MSEL(IP11_11_8
, HRTS1_N_B
, SEL_HSCIF1_1
),
1096 PINMUX_IPSR_MSEL(IP11_11_8
, MSIOF1_SS1_B
, SEL_MSIOF1_1
),
1097 PINMUX_IPSR_MSEL(IP11_11_8
, AUDIO_CLKA_B
, SEL_ADG_1
),
1098 PINMUX_IPSR_MSEL(IP11_11_8
, SCL2_A
, SEL_I2C2_0
),
1099 PINMUX_IPSR_MSEL(IP11_11_8
, STP_IVCXO27_1_C
, SEL_SSP1_1_2
),
1100 PINMUX_IPSR_MSEL(IP11_11_8
, RIF0_SYNC_B
, SEL_DRIF0_1
),
1101 PINMUX_IPSR_GPSR(IP11_11_8
, ADICHS1
),
1103 PINMUX_IPSR_MSEL(IP11_15_12
, RX1_A
, SEL_SCIF1_0
),
1104 PINMUX_IPSR_MSEL(IP11_15_12
, HRX1_A
, SEL_HSCIF1_0
),
1105 PINMUX_IPSR_MSEL(IP11_15_12
, TS_SDAT0_C
, SEL_TSIF0_2
),
1106 PINMUX_IPSR_MSEL(IP11_15_12
, STP_ISD_0_C
, SEL_SSP1_0_2
),
1107 PINMUX_IPSR_MSEL(IP11_15_12
, RIF1_CLK_C
, SEL_DRIF1_2
),
1109 PINMUX_IPSR_MSEL(IP11_19_16
, TX1_A
, SEL_SCIF1_0
),
1110 PINMUX_IPSR_MSEL(IP11_19_16
, HTX1_A
, SEL_HSCIF1_0
),
1111 PINMUX_IPSR_MSEL(IP11_19_16
, TS_SDEN0_C
, SEL_TSIF0_2
),
1112 PINMUX_IPSR_MSEL(IP11_19_16
, STP_ISEN_0_C
, SEL_SSP1_0_2
),
1113 PINMUX_IPSR_MSEL(IP11_19_16
, RIF1_D0_C
, SEL_DRIF1_2
),
1115 PINMUX_IPSR_GPSR(IP11_23_20
, CTS1_N
),
1116 PINMUX_IPSR_MSEL(IP11_23_20
, HCTS1_N_A
, SEL_HSCIF1_0
),
1117 PINMUX_IPSR_MSEL(IP11_23_20
, MSIOF1_RXD_B
, SEL_MSIOF1_1
),
1118 PINMUX_IPSR_MSEL(IP11_23_20
, TS_SDEN1_C
, SEL_TSIF1_2
),
1119 PINMUX_IPSR_MSEL(IP11_23_20
, STP_ISEN_1_C
, SEL_SSP1_1_2
),
1120 PINMUX_IPSR_MSEL(IP11_23_20
, RIF1_D0_B
, SEL_DRIF1_1
),
1121 PINMUX_IPSR_GPSR(IP11_23_20
, ADIDATA
),
1123 PINMUX_IPSR_GPSR(IP11_27_24
, RTS1_N_TANS
),
1124 PINMUX_IPSR_MSEL(IP11_27_24
, HRTS1_N_A
, SEL_HSCIF1_0
),
1125 PINMUX_IPSR_MSEL(IP11_27_24
, MSIOF1_TXD_B
, SEL_MSIOF1_1
),
1126 PINMUX_IPSR_MSEL(IP11_27_24
, TS_SDAT1_C
, SEL_TSIF1_2
),
1127 PINMUX_IPSR_MSEL(IP11_27_24
, STP_ISD_1_C
, SEL_SSP1_1_2
),
1128 PINMUX_IPSR_MSEL(IP11_27_24
, RIF1_D1_B
, SEL_DRIF1_1
),
1129 PINMUX_IPSR_GPSR(IP11_27_24
, ADICHS0
),
1131 PINMUX_IPSR_GPSR(IP11_31_28
, SCK2
),
1132 PINMUX_IPSR_MSEL(IP11_31_28
, SCIF_CLK_B
, SEL_SCIF1_1
),
1133 PINMUX_IPSR_MSEL(IP11_31_28
, MSIOF1_SCK_B
, SEL_MSIOF1_1
),
1134 PINMUX_IPSR_MSEL(IP11_31_28
, TS_SCK1_C
, SEL_TSIF1_2
),
1135 PINMUX_IPSR_MSEL(IP11_31_28
, STP_ISCLK_1_C
, SEL_SSP1_1_2
),
1136 PINMUX_IPSR_MSEL(IP11_31_28
, RIF1_CLK_B
, SEL_DRIF1_1
),
1137 PINMUX_IPSR_GPSR(IP11_31_28
, ADICLK
),
1140 PINMUX_IPSR_MSEL(IP12_3_0
, TX2_A
, SEL_SCIF2_0
),
1141 PINMUX_IPSR_MSEL(IP12_3_0
, SD2_CD_B
, SEL_SDHI2_1
),
1142 PINMUX_IPSR_MSEL(IP12_3_0
, SCL1_A
, SEL_I2C1_0
),
1143 PINMUX_IPSR_MSEL(IP12_3_0
, FMCLK_A
, SEL_FM_0
),
1144 PINMUX_IPSR_MSEL(IP12_3_0
, RIF1_D1_C
, SEL_DRIF1_2
),
1145 PINMUX_IPSR_MSEL(IP12_3_0
, FSO_CFE_0_B
, SEL_FSO_1
),
1147 PINMUX_IPSR_MSEL(IP12_7_4
, RX2_A
, SEL_SCIF2_0
),
1148 PINMUX_IPSR_MSEL(IP12_7_4
, SD2_WP_B
, SEL_SDHI2_1
),
1149 PINMUX_IPSR_MSEL(IP12_7_4
, SDA1_A
, SEL_I2C1_0
),
1150 PINMUX_IPSR_MSEL(IP12_7_4
, FMIN_A
, SEL_FM_0
),
1151 PINMUX_IPSR_MSEL(IP12_7_4
, RIF1_SYNC_C
, SEL_DRIF1_2
),
1152 PINMUX_IPSR_MSEL(IP12_7_4
, FSO_CFE_1_B
, SEL_FSO_1
),
1154 PINMUX_IPSR_GPSR(IP12_11_8
, HSCK0
),
1155 PINMUX_IPSR_MSEL(IP12_11_8
, MSIOF1_SCK_D
, SEL_MSIOF1_3
),
1156 PINMUX_IPSR_MSEL(IP12_11_8
, AUDIO_CLKB_A
, SEL_ADG_0
),
1157 PINMUX_IPSR_MSEL(IP12_11_8
, SSI_SDATA1_B
, SEL_SSI_1
),
1158 PINMUX_IPSR_MSEL(IP12_11_8
, TS_SCK0_D
, SEL_TSIF0_3
),
1159 PINMUX_IPSR_MSEL(IP12_11_8
, STP_ISCLK_0_D
, SEL_SSP1_0_3
),
1160 PINMUX_IPSR_MSEL(IP12_11_8
, RIF0_CLK_C
, SEL_DRIF0_2
),
1162 PINMUX_IPSR_GPSR(IP12_15_12
, HRX0
),
1163 PINMUX_IPSR_MSEL(IP12_15_12
, MSIOF1_RXD_D
, SEL_MSIOF1_3
),
1164 PINMUX_IPSR_MSEL(IP12_15_12
, SSI_SDATA2_B
, SEL_SSI_1
),
1165 PINMUX_IPSR_MSEL(IP12_15_12
, TS_SDEN0_D
, SEL_TSIF0_3
),
1166 PINMUX_IPSR_MSEL(IP12_15_12
, STP_ISEN_0_D
, SEL_SSP1_0_3
),
1167 PINMUX_IPSR_MSEL(IP12_15_12
, RIF0_D0_C
, SEL_DRIF0_2
),
1169 PINMUX_IPSR_GPSR(IP12_19_16
, HTX0
),
1170 PINMUX_IPSR_MSEL(IP12_19_16
, MSIOF1_TXD_D
, SEL_MSIOF1_3
),
1171 PINMUX_IPSR_MSEL(IP12_19_16
, SSI_SDATA9_B
, SEL_SSI_1
),
1172 PINMUX_IPSR_MSEL(IP12_19_16
, TS_SDAT0_D
, SEL_TSIF0_3
),
1173 PINMUX_IPSR_MSEL(IP12_19_16
, STP_ISD_0_D
, SEL_SSP1_0_3
),
1174 PINMUX_IPSR_MSEL(IP12_19_16
, RIF0_D1_C
, SEL_DRIF0_2
),
1176 PINMUX_IPSR_GPSR(IP12_23_20
, HCTS0_N
),
1177 PINMUX_IPSR_MSEL(IP12_23_20
, RX2_B
, SEL_SCIF2_1
),
1178 PINMUX_IPSR_MSEL(IP12_23_20
, MSIOF1_SYNC_D
, SEL_MSIOF1_3
),
1179 PINMUX_IPSR_MSEL(IP12_23_20
, SSI_SCK9_A
, SEL_SSI_0
),
1180 PINMUX_IPSR_MSEL(IP12_23_20
, TS_SPSYNC0_D
, SEL_TSIF0_3
),
1181 PINMUX_IPSR_MSEL(IP12_23_20
, STP_ISSYNC_0_D
, SEL_SSP1_0_3
),
1182 PINMUX_IPSR_MSEL(IP12_23_20
, RIF0_SYNC_C
, SEL_DRIF0_2
),
1183 PINMUX_IPSR_MSEL(IP12_23_20
, AUDIO_CLKOUT1_A
, SEL_ADG_0
),
1185 PINMUX_IPSR_GPSR(IP12_27_24
, HRTS0_N
),
1186 PINMUX_IPSR_MSEL(IP12_27_24
, TX2_B
, SEL_SCIF2_1
),
1187 PINMUX_IPSR_MSEL(IP12_27_24
, MSIOF1_SS1_D
, SEL_MSIOF1_3
),
1188 PINMUX_IPSR_MSEL(IP12_27_24
, SSI_WS9_A
, SEL_SSI_0
),
1189 PINMUX_IPSR_MSEL(IP12_27_24
, STP_IVCXO27_0_D
, SEL_SSP1_0_3
),
1190 PINMUX_IPSR_MSEL(IP12_27_24
, BPFCLK_A
, SEL_FM_0
),
1191 PINMUX_IPSR_MSEL(IP12_27_24
, AUDIO_CLKOUT2_A
, SEL_ADG_0
),
1193 PINMUX_IPSR_GPSR(IP12_31_28
, MSIOF0_SYNC
),
1194 PINMUX_IPSR_MSEL(IP12_31_28
, AUDIO_CLKOUT_A
, SEL_ADG_0
),
1197 PINMUX_IPSR_GPSR(IP13_3_0
, MSIOF0_SS1
),
1198 PINMUX_IPSR_GPSR(IP13_3_0
, RX5
),
1199 PINMUX_IPSR_MSEL(IP13_3_0
, AUDIO_CLKA_C
, SEL_ADG_2
),
1200 PINMUX_IPSR_MSEL(IP13_3_0
, SSI_SCK2_A
, SEL_SSI_0
),
1201 PINMUX_IPSR_MSEL(IP13_3_0
, STP_IVCXO27_0_C
, SEL_SSP1_0_2
),
1202 PINMUX_IPSR_MSEL(IP13_3_0
, AUDIO_CLKOUT3_A
, SEL_ADG_0
),
1203 PINMUX_IPSR_MSEL(IP13_3_0
, TCLK1_B
, SEL_TIMER_TMU_1
),
1205 PINMUX_IPSR_GPSR(IP13_7_4
, MSIOF0_SS2
),
1206 PINMUX_IPSR_GPSR(IP13_7_4
, TX5
),
1207 PINMUX_IPSR_MSEL(IP13_7_4
, MSIOF1_SS2_D
, SEL_MSIOF1_3
),
1208 PINMUX_IPSR_MSEL(IP13_7_4
, AUDIO_CLKC_A
, SEL_ADG_0
),
1209 PINMUX_IPSR_MSEL(IP13_7_4
, SSI_WS2_A
, SEL_SSI_0
),
1210 PINMUX_IPSR_MSEL(IP13_7_4
, STP_OPWM_0_D
, SEL_SSP1_0_3
),
1211 PINMUX_IPSR_MSEL(IP13_7_4
, AUDIO_CLKOUT_D
, SEL_ADG_3
),
1212 PINMUX_IPSR_MSEL(IP13_7_4
, SPEEDIN_B
, SEL_SPEED_PULSE_1
),
1214 PINMUX_IPSR_GPSR(IP13_11_8
, MLB_CLK
),
1215 PINMUX_IPSR_MSEL(IP13_11_8
, MSIOF1_SCK_F
, SEL_MSIOF1_5
),
1216 PINMUX_IPSR_MSEL(IP13_11_8
, SCL1_B
, SEL_I2C1_1
),
1218 PINMUX_IPSR_GPSR(IP13_15_12
, MLB_SIG
),
1219 PINMUX_IPSR_MSEL(IP13_15_12
, RX1_B
, SEL_SCIF1_1
),
1220 PINMUX_IPSR_MSEL(IP13_15_12
, MSIOF1_SYNC_F
, SEL_MSIOF1_5
),
1221 PINMUX_IPSR_MSEL(IP13_15_12
, SDA1_B
, SEL_I2C1_1
),
1223 PINMUX_IPSR_GPSR(IP13_19_16
, MLB_DAT
),
1224 PINMUX_IPSR_MSEL(IP13_19_16
, TX1_B
, SEL_SCIF1_1
),
1225 PINMUX_IPSR_MSEL(IP13_19_16
, MSIOF1_RXD_F
, SEL_MSIOF1_5
),
1227 PINMUX_IPSR_GPSR(IP13_23_20
, SSI_SCK01239
),
1228 PINMUX_IPSR_MSEL(IP13_23_20
, MSIOF1_TXD_F
, SEL_MSIOF1_5
),
1230 PINMUX_IPSR_GPSR(IP13_27_24
, SSI_WS01239
),
1231 PINMUX_IPSR_MSEL(IP13_27_24
, MSIOF1_SS1_F
, SEL_MSIOF1_5
),
1233 PINMUX_IPSR_GPSR(IP13_31_28
, SSI_SDATA0
),
1234 PINMUX_IPSR_MSEL(IP13_31_28
, MSIOF1_SS2_F
, SEL_MSIOF1_5
),
1237 PINMUX_IPSR_MSEL(IP14_3_0
, SSI_SDATA1_A
, SEL_SSI_0
),
1239 PINMUX_IPSR_MSEL(IP14_7_4
, SSI_SDATA2_A
, SEL_SSI_0
),
1240 PINMUX_IPSR_MSEL(IP14_7_4
, SSI_SCK1_B
, SEL_SSI_1
),
1242 PINMUX_IPSR_GPSR(IP14_11_8
, SSI_SCK34
),
1243 PINMUX_IPSR_MSEL(IP14_11_8
, MSIOF1_SS1_A
, SEL_MSIOF1_0
),
1244 PINMUX_IPSR_MSEL(IP14_11_8
, STP_OPWM_0_A
, SEL_SSP1_0_0
),
1246 PINMUX_IPSR_GPSR(IP14_15_12
, SSI_WS34
),
1247 PINMUX_IPSR_MSEL(IP14_15_12
, HCTS2_N_A
, SEL_HSCIF2_0
),
1248 PINMUX_IPSR_MSEL(IP14_15_12
, MSIOF1_SS2_A
, SEL_MSIOF1_0
),
1249 PINMUX_IPSR_MSEL(IP14_15_12
, STP_IVCXO27_0_A
, SEL_SSP1_0_0
),
1251 PINMUX_IPSR_GPSR(IP14_19_16
, SSI_SDATA3
),
1252 PINMUX_IPSR_MSEL(IP14_19_16
, HRTS2_N_A
, SEL_HSCIF2_0
),
1253 PINMUX_IPSR_MSEL(IP14_19_16
, MSIOF1_TXD_A
, SEL_MSIOF1_0
),
1254 PINMUX_IPSR_MSEL(IP14_19_16
, TS_SCK0_A
, SEL_TSIF0_0
),
1255 PINMUX_IPSR_MSEL(IP14_19_16
, STP_ISCLK_0_A
, SEL_SSP1_0_0
),
1256 PINMUX_IPSR_MSEL(IP14_19_16
, RIF0_D1_A
, SEL_DRIF0_0
),
1257 PINMUX_IPSR_MSEL(IP14_19_16
, RIF2_D0_A
, SEL_DRIF2_0
),
1259 PINMUX_IPSR_GPSR(IP14_23_20
, SSI_SCK4
),
1260 PINMUX_IPSR_MSEL(IP14_23_20
, HRX2_A
, SEL_HSCIF2_0
),
1261 PINMUX_IPSR_MSEL(IP14_23_20
, MSIOF1_SCK_A
, SEL_MSIOF1_0
),
1262 PINMUX_IPSR_MSEL(IP14_23_20
, TS_SDAT0_A
, SEL_TSIF0_0
),
1263 PINMUX_IPSR_MSEL(IP14_23_20
, STP_ISD_0_A
, SEL_SSP1_0_0
),
1264 PINMUX_IPSR_MSEL(IP14_23_20
, RIF0_CLK_A
, SEL_DRIF0_0
),
1265 PINMUX_IPSR_MSEL(IP14_23_20
, RIF2_CLK_A
, SEL_DRIF2_0
),
1267 PINMUX_IPSR_GPSR(IP14_27_24
, SSI_WS4
),
1268 PINMUX_IPSR_MSEL(IP14_27_24
, HTX2_A
, SEL_HSCIF2_0
),
1269 PINMUX_IPSR_MSEL(IP14_27_24
, MSIOF1_SYNC_A
, SEL_MSIOF1_0
),
1270 PINMUX_IPSR_MSEL(IP14_27_24
, TS_SDEN0_A
, SEL_TSIF0_0
),
1271 PINMUX_IPSR_MSEL(IP14_27_24
, STP_ISEN_0_A
, SEL_SSP1_0_0
),
1272 PINMUX_IPSR_MSEL(IP14_27_24
, RIF0_SYNC_A
, SEL_DRIF0_0
),
1273 PINMUX_IPSR_MSEL(IP14_27_24
, RIF2_SYNC_A
, SEL_DRIF2_0
),
1275 PINMUX_IPSR_GPSR(IP14_31_28
, SSI_SDATA4
),
1276 PINMUX_IPSR_MSEL(IP14_31_28
, HSCK2_A
, SEL_HSCIF2_0
),
1277 PINMUX_IPSR_MSEL(IP14_31_28
, MSIOF1_RXD_A
, SEL_MSIOF1_0
),
1278 PINMUX_IPSR_MSEL(IP14_31_28
, TS_SPSYNC0_A
, SEL_TSIF0_0
),
1279 PINMUX_IPSR_MSEL(IP14_31_28
, STP_ISSYNC_0_A
, SEL_SSP1_0_0
),
1280 PINMUX_IPSR_MSEL(IP14_31_28
, RIF0_D0_A
, SEL_DRIF0_0
),
1281 PINMUX_IPSR_MSEL(IP14_31_28
, RIF2_D1_A
, SEL_DRIF2_0
),
1284 PINMUX_IPSR_GPSR(IP15_3_0
, SSI_SCK6
),
1285 PINMUX_IPSR_GPSR(IP15_3_0
, USB2_PWEN
),
1286 PINMUX_IPSR_MSEL(IP15_3_0
, SIM0_RST_D
, SEL_SIMCARD_3
),
1288 PINMUX_IPSR_GPSR(IP15_7_4
, SSI_WS6
),
1289 PINMUX_IPSR_GPSR(IP15_7_4
, USB2_OVC
),
1290 PINMUX_IPSR_MSEL(IP15_7_4
, SIM0_D_D
, SEL_SIMCARD_3
),
1292 PINMUX_IPSR_GPSR(IP15_11_8
, SSI_SDATA6
),
1293 PINMUX_IPSR_MSEL(IP15_11_8
, SIM0_CLK_D
, SEL_SIMCARD_3
),
1294 PINMUX_IPSR_MSEL(IP15_11_8
, SATA_DEVSLP_A
, SEL_SATA_0
),
1296 PINMUX_IPSR_GPSR(IP15_15_12
, SSI_SCK78
),
1297 PINMUX_IPSR_MSEL(IP15_15_12
, HRX2_B
, SEL_HSCIF2_1
),
1298 PINMUX_IPSR_MSEL(IP15_15_12
, MSIOF1_SCK_C
, SEL_MSIOF1_2
),
1299 PINMUX_IPSR_MSEL(IP15_15_12
, TS_SCK1_A
, SEL_TSIF1_0
),
1300 PINMUX_IPSR_MSEL(IP15_15_12
, STP_ISCLK_1_A
, SEL_SSP1_1_0
),
1301 PINMUX_IPSR_MSEL(IP15_15_12
, RIF1_CLK_A
, SEL_DRIF1_0
),
1302 PINMUX_IPSR_MSEL(IP15_15_12
, RIF3_CLK_A
, SEL_DRIF3_0
),
1304 PINMUX_IPSR_GPSR(IP15_19_16
, SSI_WS78
),
1305 PINMUX_IPSR_MSEL(IP15_19_16
, HTX2_B
, SEL_HSCIF2_1
),
1306 PINMUX_IPSR_MSEL(IP15_19_16
, MSIOF1_SYNC_C
, SEL_MSIOF1_2
),
1307 PINMUX_IPSR_MSEL(IP15_19_16
, TS_SDAT1_A
, SEL_TSIF1_0
),
1308 PINMUX_IPSR_MSEL(IP15_19_16
, STP_ISD_1_A
, SEL_SSP1_1_0
),
1309 PINMUX_IPSR_MSEL(IP15_19_16
, RIF1_SYNC_A
, SEL_DRIF1_0
),
1310 PINMUX_IPSR_MSEL(IP15_19_16
, RIF3_SYNC_A
, SEL_DRIF3_0
),
1312 PINMUX_IPSR_GPSR(IP15_23_20
, SSI_SDATA7
),
1313 PINMUX_IPSR_MSEL(IP15_23_20
, HCTS2_N_B
, SEL_HSCIF2_1
),
1314 PINMUX_IPSR_MSEL(IP15_23_20
, MSIOF1_RXD_C
, SEL_MSIOF1_2
),
1315 PINMUX_IPSR_MSEL(IP15_23_20
, TS_SDEN1_A
, SEL_TSIF1_0
),
1316 PINMUX_IPSR_MSEL(IP15_23_20
, STP_ISEN_1_A
, SEL_SSP1_1_0
),
1317 PINMUX_IPSR_MSEL(IP15_23_20
, RIF1_D0_A
, SEL_DRIF1_0
),
1318 PINMUX_IPSR_MSEL(IP15_23_20
, RIF3_D0_A
, SEL_DRIF3_0
),
1319 PINMUX_IPSR_MSEL(IP15_23_20
, TCLK2_A
, SEL_TIMER_TMU_0
),
1321 PINMUX_IPSR_GPSR(IP15_27_24
, SSI_SDATA8
),
1322 PINMUX_IPSR_MSEL(IP15_27_24
, HRTS2_N_B
, SEL_HSCIF2_1
),
1323 PINMUX_IPSR_MSEL(IP15_27_24
, MSIOF1_TXD_C
, SEL_MSIOF1_2
),
1324 PINMUX_IPSR_MSEL(IP15_27_24
, TS_SPSYNC1_A
, SEL_TSIF1_0
),
1325 PINMUX_IPSR_MSEL(IP15_27_24
, STP_ISSYNC_1_A
, SEL_SSP1_1_0
),
1326 PINMUX_IPSR_MSEL(IP15_27_24
, RIF1_D1_A
, SEL_DRIF1_0
),
1327 PINMUX_IPSR_MSEL(IP15_27_24
, RIF3_D1_A
, SEL_DRIF3_0
),
1329 PINMUX_IPSR_MSEL(IP15_31_28
, SSI_SDATA9_A
, SEL_SSI_0
),
1330 PINMUX_IPSR_MSEL(IP15_31_28
, HSCK2_B
, SEL_HSCIF2_1
),
1331 PINMUX_IPSR_MSEL(IP15_31_28
, MSIOF1_SS1_C
, SEL_MSIOF1_2
),
1332 PINMUX_IPSR_MSEL(IP15_31_28
, HSCK1_A
, SEL_HSCIF1_0
),
1333 PINMUX_IPSR_MSEL(IP15_31_28
, SSI_WS1_B
, SEL_SSI_1
),
1334 PINMUX_IPSR_GPSR(IP15_31_28
, SCK1
),
1335 PINMUX_IPSR_MSEL(IP15_31_28
, STP_IVCXO27_1_A
, SEL_SSP1_1_0
),
1336 PINMUX_IPSR_GPSR(IP15_31_28
, SCK5
),
1339 PINMUX_IPSR_MSEL(IP16_3_0
, AUDIO_CLKA_A
, SEL_ADG_0
),
1340 PINMUX_IPSR_GPSR(IP16_3_0
, CC5_OSCOUT
),
1342 PINMUX_IPSR_MSEL(IP16_7_4
, AUDIO_CLKB_B
, SEL_ADG_1
),
1343 PINMUX_IPSR_MSEL(IP16_7_4
, SCIF_CLK_A
, SEL_SCIF1_0
),
1344 PINMUX_IPSR_MSEL(IP16_7_4
, STP_IVCXO27_1_D
, SEL_SSP1_1_3
),
1345 PINMUX_IPSR_MSEL(IP16_7_4
, REMOCON_A
, SEL_REMOCON_0
),
1346 PINMUX_IPSR_MSEL(IP16_7_4
, TCLK1_A
, SEL_TIMER_TMU_0
),
1348 PINMUX_IPSR_GPSR(IP16_11_8
, USB0_PWEN
),
1349 PINMUX_IPSR_MSEL(IP16_11_8
, SIM0_RST_C
, SEL_SIMCARD_2
),
1350 PINMUX_IPSR_MSEL(IP16_11_8
, TS_SCK1_D
, SEL_TSIF1_3
),
1351 PINMUX_IPSR_MSEL(IP16_11_8
, STP_ISCLK_1_D
, SEL_SSP1_1_3
),
1352 PINMUX_IPSR_MSEL(IP16_11_8
, BPFCLK_B
, SEL_FM_1
),
1353 PINMUX_IPSR_MSEL(IP16_11_8
, RIF3_CLK_B
, SEL_DRIF3_1
),
1355 PINMUX_IPSR_GPSR(IP16_15_12
, USB0_OVC
),
1356 PINMUX_IPSR_MSEL(IP16_11_8
, SIM0_D_C
, SEL_SIMCARD_2
),
1357 PINMUX_IPSR_MSEL(IP16_11_8
, TS_SDAT1_D
, SEL_TSIF1_3
),
1358 PINMUX_IPSR_MSEL(IP16_11_8
, STP_ISD_1_D
, SEL_SSP1_1_3
),
1359 PINMUX_IPSR_MSEL(IP16_11_8
, RIF3_SYNC_B
, SEL_DRIF3_1
),
1361 PINMUX_IPSR_GPSR(IP16_19_16
, USB1_PWEN
),
1362 PINMUX_IPSR_MSEL(IP16_19_16
, SIM0_CLK_C
, SEL_SIMCARD_2
),
1363 PINMUX_IPSR_MSEL(IP16_19_16
, SSI_SCK1_A
, SEL_SSI_0
),
1364 PINMUX_IPSR_MSEL(IP16_19_16
, TS_SCK0_E
, SEL_TSIF0_4
),
1365 PINMUX_IPSR_MSEL(IP16_19_16
, STP_ISCLK_0_E
, SEL_SSP1_0_4
),
1366 PINMUX_IPSR_MSEL(IP16_19_16
, FMCLK_B
, SEL_FM_1
),
1367 PINMUX_IPSR_MSEL(IP16_19_16
, RIF2_CLK_B
, SEL_DRIF2_1
),
1368 PINMUX_IPSR_MSEL(IP16_19_16
, SPEEDIN_A
, SEL_SPEED_PULSE_0
),
1370 PINMUX_IPSR_GPSR(IP16_23_20
, USB1_OVC
),
1371 PINMUX_IPSR_MSEL(IP16_23_20
, MSIOF1_SS2_C
, SEL_MSIOF1_2
),
1372 PINMUX_IPSR_MSEL(IP16_23_20
, SSI_WS1_A
, SEL_SSI_0
),
1373 PINMUX_IPSR_MSEL(IP16_23_20
, TS_SDAT0_E
, SEL_TSIF0_4
),
1374 PINMUX_IPSR_MSEL(IP16_23_20
, STP_ISD_0_E
, SEL_SSP1_0_4
),
1375 PINMUX_IPSR_MSEL(IP16_23_20
, FMIN_B
, SEL_FM_1
),
1376 PINMUX_IPSR_MSEL(IP16_23_20
, RIF2_SYNC_B
, SEL_DRIF2_1
),
1377 PINMUX_IPSR_MSEL(IP16_23_20
, REMOCON_B
, SEL_REMOCON_1
),
1379 PINMUX_IPSR_GPSR(IP16_27_24
, USB30_PWEN
),
1380 PINMUX_IPSR_MSEL(IP16_27_24
, AUDIO_CLKOUT_B
, SEL_ADG_1
),
1381 PINMUX_IPSR_MSEL(IP16_27_24
, SSI_SCK2_B
, SEL_SSI_1
),
1382 PINMUX_IPSR_MSEL(IP16_27_24
, TS_SDEN1_D
, SEL_TSIF1_3
),
1383 PINMUX_IPSR_MSEL(IP16_27_24
, STP_ISEN_1_D
, SEL_SSP1_1_2
),
1384 PINMUX_IPSR_MSEL(IP16_27_24
, STP_OPWM_0_E
, SEL_SSP1_0_4
),
1385 PINMUX_IPSR_MSEL(IP16_27_24
, RIF3_D0_B
, SEL_DRIF3_1
),
1386 PINMUX_IPSR_MSEL(IP16_27_24
, TCLK2_B
, SEL_TIMER_TMU_1
),
1387 PINMUX_IPSR_GPSR(IP16_27_24
, TPU0TO0
),
1389 PINMUX_IPSR_GPSR(IP16_31_28
, USB30_OVC
),
1390 PINMUX_IPSR_MSEL(IP16_31_28
, AUDIO_CLKOUT1_B
, SEL_ADG_1
),
1391 PINMUX_IPSR_MSEL(IP16_31_28
, SSI_WS2_B
, SEL_SSI_1
),
1392 PINMUX_IPSR_MSEL(IP16_31_28
, TS_SPSYNC1_D
, SEL_TSIF1_3
),
1393 PINMUX_IPSR_MSEL(IP16_31_28
, STP_ISSYNC_1_D
, SEL_SSP1_1_3
),
1394 PINMUX_IPSR_MSEL(IP16_31_28
, STP_IVCXO27_0_E
, SEL_SSP1_0_4
),
1395 PINMUX_IPSR_MSEL(IP16_31_28
, RIF3_D1_B
, SEL_DRIF3_1
),
1396 PINMUX_IPSR_MSEL(IP16_31_28
, FSO_TOE_B
, SEL_FSO_1
),
1397 PINMUX_IPSR_GPSR(IP16_31_28
, TPU0TO1
),
1400 PINMUX_IPSR_GPSR(IP17_3_0
, USB31_PWEN
),
1401 PINMUX_IPSR_MSEL(IP17_3_0
, AUDIO_CLKOUT2_B
, SEL_ADG_1
),
1402 PINMUX_IPSR_MSEL(IP17_3_0
, SSI_SCK9_B
, SEL_SSI_1
),
1403 PINMUX_IPSR_MSEL(IP17_3_0
, TS_SDEN0_E
, SEL_TSIF0_4
),
1404 PINMUX_IPSR_MSEL(IP17_3_0
, STP_ISEN_0_E
, SEL_SSP1_0_4
),
1405 PINMUX_IPSR_MSEL(IP17_3_0
, RIF2_D0_B
, SEL_DRIF2_1
),
1406 PINMUX_IPSR_GPSR(IP17_3_0
, TPU0TO2
),
1408 PINMUX_IPSR_GPSR(IP17_7_4
, USB31_OVC
),
1409 PINMUX_IPSR_MSEL(IP17_7_4
, AUDIO_CLKOUT3_B
, SEL_ADG_1
),
1410 PINMUX_IPSR_MSEL(IP17_7_4
, SSI_WS9_B
, SEL_SSI_1
),
1411 PINMUX_IPSR_MSEL(IP17_7_4
, TS_SPSYNC0_E
, SEL_TSIF0_4
),
1412 PINMUX_IPSR_MSEL(IP17_7_4
, STP_ISSYNC_0_E
, SEL_SSP1_0_4
),
1413 PINMUX_IPSR_MSEL(IP17_7_4
, RIF2_D1_B
, SEL_DRIF2_1
),
1414 PINMUX_IPSR_GPSR(IP17_7_4
, TPU0TO3
),
1417 static const struct sh_pfc_pin pinmux_pins
[] = {
1418 PINMUX_GPIO_GP_ALL(),
1421 /* - AUDIO CLOCK ------------------------------------------------------------ */
1422 static const unsigned int audio_clk_a_a_pins
[] = {
1426 static const unsigned int audio_clk_a_a_mux
[] = {
1429 static const unsigned int audio_clk_a_b_pins
[] = {
1433 static const unsigned int audio_clk_a_b_mux
[] = {
1436 static const unsigned int audio_clk_a_c_pins
[] = {
1440 static const unsigned int audio_clk_a_c_mux
[] = {
1443 static const unsigned int audio_clk_b_a_pins
[] = {
1447 static const unsigned int audio_clk_b_a_mux
[] = {
1450 static const unsigned int audio_clk_b_b_pins
[] = {
1454 static const unsigned int audio_clk_b_b_mux
[] = {
1457 static const unsigned int audio_clk_c_a_pins
[] = {
1461 static const unsigned int audio_clk_c_a_mux
[] = {
1464 static const unsigned int audio_clk_c_b_pins
[] = {
1468 static const unsigned int audio_clk_c_b_mux
[] = {
1471 static const unsigned int audio_clkout_a_pins
[] = {
1475 static const unsigned int audio_clkout_a_mux
[] = {
1476 AUDIO_CLKOUT_A_MARK
,
1478 static const unsigned int audio_clkout_b_pins
[] = {
1482 static const unsigned int audio_clkout_b_mux
[] = {
1483 AUDIO_CLKOUT_B_MARK
,
1485 static const unsigned int audio_clkout_c_pins
[] = {
1489 static const unsigned int audio_clkout_c_mux
[] = {
1490 AUDIO_CLKOUT_C_MARK
,
1492 static const unsigned int audio_clkout_d_pins
[] = {
1496 static const unsigned int audio_clkout_d_mux
[] = {
1497 AUDIO_CLKOUT_D_MARK
,
1499 static const unsigned int audio_clkout1_a_pins
[] = {
1503 static const unsigned int audio_clkout1_a_mux
[] = {
1504 AUDIO_CLKOUT1_A_MARK
,
1506 static const unsigned int audio_clkout1_b_pins
[] = {
1510 static const unsigned int audio_clkout1_b_mux
[] = {
1511 AUDIO_CLKOUT1_B_MARK
,
1513 static const unsigned int audio_clkout2_a_pins
[] = {
1517 static const unsigned int audio_clkout2_a_mux
[] = {
1518 AUDIO_CLKOUT2_A_MARK
,
1520 static const unsigned int audio_clkout2_b_pins
[] = {
1524 static const unsigned int audio_clkout2_b_mux
[] = {
1525 AUDIO_CLKOUT2_B_MARK
,
1528 static const unsigned int audio_clkout3_a_pins
[] = {
1532 static const unsigned int audio_clkout3_a_mux
[] = {
1533 AUDIO_CLKOUT3_A_MARK
,
1535 static const unsigned int audio_clkout3_b_pins
[] = {
1539 static const unsigned int audio_clkout3_b_mux
[] = {
1540 AUDIO_CLKOUT3_B_MARK
,
1543 /* - EtherAVB --------------------------------------------------------------- */
1544 static const unsigned int avb_link_pins
[] = {
1548 static const unsigned int avb_link_mux
[] = {
1551 static const unsigned int avb_magic_pins
[] = {
1555 static const unsigned int avb_magic_mux
[] = {
1558 static const unsigned int avb_phy_int_pins
[] = {
1562 static const unsigned int avb_phy_int_mux
[] = {
1565 static const unsigned int avb_mdc_pins
[] = {
1569 static const unsigned int avb_mdc_mux
[] = {
1572 static const unsigned int avb_avtp_pps_pins
[] = {
1576 static const unsigned int avb_avtp_pps_mux
[] = {
1579 static const unsigned int avb_avtp_match_a_pins
[] = {
1580 /* AVB_AVTP_MATCH_A */
1583 static const unsigned int avb_avtp_match_a_mux
[] = {
1584 AVB_AVTP_MATCH_A_MARK
,
1586 static const unsigned int avb_avtp_capture_a_pins
[] = {
1587 /* AVB_AVTP_CAPTURE_A */
1590 static const unsigned int avb_avtp_capture_a_mux
[] = {
1591 AVB_AVTP_CAPTURE_A_MARK
,
1593 static const unsigned int avb_avtp_match_b_pins
[] = {
1594 /* AVB_AVTP_MATCH_B */
1597 static const unsigned int avb_avtp_match_b_mux
[] = {
1598 AVB_AVTP_MATCH_B_MARK
,
1600 static const unsigned int avb_avtp_capture_b_pins
[] = {
1601 /* AVB_AVTP_CAPTURE_B */
1604 static const unsigned int avb_avtp_capture_b_mux
[] = {
1605 AVB_AVTP_CAPTURE_B_MARK
,
1608 /* - CAN ------------------------------------------------------------------ */
1609 static const unsigned int can0_data_a_pins
[] = {
1611 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1613 static const unsigned int can0_data_a_mux
[] = {
1614 CAN0_TX_A_MARK
, CAN0_RX_A_MARK
,
1616 static const unsigned int can0_data_b_pins
[] = {
1618 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1620 static const unsigned int can0_data_b_mux
[] = {
1621 CAN0_TX_B_MARK
, CAN0_RX_B_MARK
,
1623 static const unsigned int can1_data_pins
[] = {
1625 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1627 static const unsigned int can1_data_mux
[] = {
1628 CAN1_TX_MARK
, CAN1_RX_MARK
,
1631 /* - CAN Clock -------------------------------------------------------------- */
1632 static const unsigned int can_clk_pins
[] = {
1636 static const unsigned int can_clk_mux
[] = {
1640 /* - CAN FD --------------------------------------------------------------- */
1641 static const unsigned int canfd0_data_a_pins
[] = {
1643 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1645 static const unsigned int canfd0_data_a_mux
[] = {
1646 CANFD0_TX_A_MARK
, CANFD0_RX_A_MARK
,
1648 static const unsigned int canfd0_data_b_pins
[] = {
1650 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1652 static const unsigned int canfd0_data_b_mux
[] = {
1653 CANFD0_TX_B_MARK
, CANFD0_RX_B_MARK
,
1655 static const unsigned int canfd1_data_pins
[] = {
1657 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1659 static const unsigned int canfd1_data_mux
[] = {
1660 CANFD1_TX_MARK
, CANFD1_RX_MARK
,
1663 /* - DRIF0 --------------------------------------------------------------- */
1664 static const unsigned int drif0_ctrl_a_pins
[] = {
1666 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1668 static const unsigned int drif0_ctrl_a_mux
[] = {
1669 RIF0_CLK_A_MARK
, RIF0_SYNC_A_MARK
,
1671 static const unsigned int drif0_data0_a_pins
[] = {
1675 static const unsigned int drif0_data0_a_mux
[] = {
1678 static const unsigned int drif0_data1_a_pins
[] = {
1682 static const unsigned int drif0_data1_a_mux
[] = {
1685 static const unsigned int drif0_ctrl_b_pins
[] = {
1687 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1689 static const unsigned int drif0_ctrl_b_mux
[] = {
1690 RIF0_CLK_B_MARK
, RIF0_SYNC_B_MARK
,
1692 static const unsigned int drif0_data0_b_pins
[] = {
1696 static const unsigned int drif0_data0_b_mux
[] = {
1699 static const unsigned int drif0_data1_b_pins
[] = {
1703 static const unsigned int drif0_data1_b_mux
[] = {
1706 static const unsigned int drif0_ctrl_c_pins
[] = {
1708 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1710 static const unsigned int drif0_ctrl_c_mux
[] = {
1711 RIF0_CLK_C_MARK
, RIF0_SYNC_C_MARK
,
1713 static const unsigned int drif0_data0_c_pins
[] = {
1717 static const unsigned int drif0_data0_c_mux
[] = {
1720 static const unsigned int drif0_data1_c_pins
[] = {
1724 static const unsigned int drif0_data1_c_mux
[] = {
1727 /* - DRIF1 --------------------------------------------------------------- */
1728 static const unsigned int drif1_ctrl_a_pins
[] = {
1730 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1732 static const unsigned int drif1_ctrl_a_mux
[] = {
1733 RIF1_CLK_A_MARK
, RIF1_SYNC_A_MARK
,
1735 static const unsigned int drif1_data0_a_pins
[] = {
1739 static const unsigned int drif1_data0_a_mux
[] = {
1742 static const unsigned int drif1_data1_a_pins
[] = {
1746 static const unsigned int drif1_data1_a_mux
[] = {
1749 static const unsigned int drif1_ctrl_b_pins
[] = {
1751 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1753 static const unsigned int drif1_ctrl_b_mux
[] = {
1754 RIF1_CLK_B_MARK
, RIF1_SYNC_B_MARK
,
1756 static const unsigned int drif1_data0_b_pins
[] = {
1760 static const unsigned int drif1_data0_b_mux
[] = {
1763 static const unsigned int drif1_data1_b_pins
[] = {
1767 static const unsigned int drif1_data1_b_mux
[] = {
1770 static const unsigned int drif1_ctrl_c_pins
[] = {
1772 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1774 static const unsigned int drif1_ctrl_c_mux
[] = {
1775 RIF1_CLK_C_MARK
, RIF1_SYNC_C_MARK
,
1777 static const unsigned int drif1_data0_c_pins
[] = {
1781 static const unsigned int drif1_data0_c_mux
[] = {
1784 static const unsigned int drif1_data1_c_pins
[] = {
1788 static const unsigned int drif1_data1_c_mux
[] = {
1791 /* - DRIF2 --------------------------------------------------------------- */
1792 static const unsigned int drif2_ctrl_a_pins
[] = {
1794 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1796 static const unsigned int drif2_ctrl_a_mux
[] = {
1797 RIF2_CLK_A_MARK
, RIF2_SYNC_A_MARK
,
1799 static const unsigned int drif2_data0_a_pins
[] = {
1803 static const unsigned int drif2_data0_a_mux
[] = {
1806 static const unsigned int drif2_data1_a_pins
[] = {
1810 static const unsigned int drif2_data1_a_mux
[] = {
1813 static const unsigned int drif2_ctrl_b_pins
[] = {
1815 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1817 static const unsigned int drif2_ctrl_b_mux
[] = {
1818 RIF2_CLK_B_MARK
, RIF2_SYNC_B_MARK
,
1820 static const unsigned int drif2_data0_b_pins
[] = {
1824 static const unsigned int drif2_data0_b_mux
[] = {
1827 static const unsigned int drif2_data1_b_pins
[] = {
1831 static const unsigned int drif2_data1_b_mux
[] = {
1834 /* - DRIF3 --------------------------------------------------------------- */
1835 static const unsigned int drif3_ctrl_a_pins
[] = {
1837 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1839 static const unsigned int drif3_ctrl_a_mux
[] = {
1840 RIF3_CLK_A_MARK
, RIF3_SYNC_A_MARK
,
1842 static const unsigned int drif3_data0_a_pins
[] = {
1846 static const unsigned int drif3_data0_a_mux
[] = {
1849 static const unsigned int drif3_data1_a_pins
[] = {
1853 static const unsigned int drif3_data1_a_mux
[] = {
1856 static const unsigned int drif3_ctrl_b_pins
[] = {
1858 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1860 static const unsigned int drif3_ctrl_b_mux
[] = {
1861 RIF3_CLK_B_MARK
, RIF3_SYNC_B_MARK
,
1863 static const unsigned int drif3_data0_b_pins
[] = {
1867 static const unsigned int drif3_data0_b_mux
[] = {
1870 static const unsigned int drif3_data1_b_pins
[] = {
1874 static const unsigned int drif3_data1_b_mux
[] = {
1878 /* - DU --------------------------------------------------------------------- */
1879 static const unsigned int du_rgb666_pins
[] = {
1880 /* R[7:2], G[7:2], B[7:2] */
1881 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1882 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1883 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1884 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1885 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1886 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1888 static const unsigned int du_rgb666_mux
[] = {
1889 DU_DR7_MARK
, DU_DR6_MARK
, DU_DR5_MARK
, DU_DR4_MARK
,
1890 DU_DR3_MARK
, DU_DR2_MARK
,
1891 DU_DG7_MARK
, DU_DG6_MARK
, DU_DG5_MARK
, DU_DG4_MARK
,
1892 DU_DG3_MARK
, DU_DG2_MARK
,
1893 DU_DB7_MARK
, DU_DB6_MARK
, DU_DB5_MARK
, DU_DB4_MARK
,
1894 DU_DB3_MARK
, DU_DB2_MARK
,
1896 static const unsigned int du_rgb888_pins
[] = {
1897 /* R[7:0], G[7:0], B[7:0] */
1898 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1899 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1900 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1901 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1902 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1903 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1904 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1905 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1906 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1908 static const unsigned int du_rgb888_mux
[] = {
1909 DU_DR7_MARK
, DU_DR6_MARK
, DU_DR5_MARK
, DU_DR4_MARK
,
1910 DU_DR3_MARK
, DU_DR2_MARK
, DU_DR1_MARK
, DU_DR0_MARK
,
1911 DU_DG7_MARK
, DU_DG6_MARK
, DU_DG5_MARK
, DU_DG4_MARK
,
1912 DU_DG3_MARK
, DU_DG2_MARK
, DU_DG1_MARK
, DU_DG0_MARK
,
1913 DU_DB7_MARK
, DU_DB6_MARK
, DU_DB5_MARK
, DU_DB4_MARK
,
1914 DU_DB3_MARK
, DU_DB2_MARK
, DU_DB1_MARK
, DU_DB0_MARK
,
1916 static const unsigned int du_clk_out_0_pins
[] = {
1920 static const unsigned int du_clk_out_0_mux
[] = {
1923 static const unsigned int du_clk_out_1_pins
[] = {
1927 static const unsigned int du_clk_out_1_mux
[] = {
1930 static const unsigned int du_sync_pins
[] = {
1931 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1932 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1934 static const unsigned int du_sync_mux
[] = {
1935 DU_EXVSYNC_DU_VSYNC_MARK
, DU_EXHSYNC_DU_HSYNC_MARK
1937 static const unsigned int du_oddf_pins
[] = {
1938 /* EXDISP/EXODDF/EXCDE */
1941 static const unsigned int du_oddf_mux
[] = {
1942 DU_EXODDF_DU_ODDF_DISP_CDE_MARK
,
1944 static const unsigned int du_cde_pins
[] = {
1948 static const unsigned int du_cde_mux
[] = {
1951 static const unsigned int du_disp_pins
[] = {
1955 static const unsigned int du_disp_mux
[] = {
1958 /* - HSCIF0 ----------------------------------------------------------------- */
1959 static const unsigned int hscif0_data_pins
[] = {
1961 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1963 static const unsigned int hscif0_data_mux
[] = {
1964 HRX0_MARK
, HTX0_MARK
,
1966 static const unsigned int hscif0_clk_pins
[] = {
1970 static const unsigned int hscif0_clk_mux
[] = {
1973 static const unsigned int hscif0_ctrl_pins
[] = {
1975 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
1977 static const unsigned int hscif0_ctrl_mux
[] = {
1978 HRTS0_N_MARK
, HCTS0_N_MARK
,
1980 /* - HSCIF1 ----------------------------------------------------------------- */
1981 static const unsigned int hscif1_data_a_pins
[] = {
1983 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1985 static const unsigned int hscif1_data_a_mux
[] = {
1986 HRX1_A_MARK
, HTX1_A_MARK
,
1988 static const unsigned int hscif1_clk_a_pins
[] = {
1992 static const unsigned int hscif1_clk_a_mux
[] = {
1995 static const unsigned int hscif1_ctrl_a_pins
[] = {
1997 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
1999 static const unsigned int hscif1_ctrl_a_mux
[] = {
2000 HRTS1_N_A_MARK
, HCTS1_N_A_MARK
,
2003 static const unsigned int hscif1_data_b_pins
[] = {
2005 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2007 static const unsigned int hscif1_data_b_mux
[] = {
2008 HRX1_B_MARK
, HTX1_B_MARK
,
2010 static const unsigned int hscif1_clk_b_pins
[] = {
2014 static const unsigned int hscif1_clk_b_mux
[] = {
2017 static const unsigned int hscif1_ctrl_b_pins
[] = {
2019 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2021 static const unsigned int hscif1_ctrl_b_mux
[] = {
2022 HRTS1_N_B_MARK
, HCTS1_N_B_MARK
,
2024 /* - HSCIF2 ----------------------------------------------------------------- */
2025 static const unsigned int hscif2_data_a_pins
[] = {
2027 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2029 static const unsigned int hscif2_data_a_mux
[] = {
2030 HRX2_A_MARK
, HTX2_A_MARK
,
2032 static const unsigned int hscif2_clk_a_pins
[] = {
2036 static const unsigned int hscif2_clk_a_mux
[] = {
2039 static const unsigned int hscif2_ctrl_a_pins
[] = {
2041 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2043 static const unsigned int hscif2_ctrl_a_mux
[] = {
2044 HRTS2_N_A_MARK
, HCTS2_N_A_MARK
,
2047 static const unsigned int hscif2_data_b_pins
[] = {
2049 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2051 static const unsigned int hscif2_data_b_mux
[] = {
2052 HRX2_B_MARK
, HTX2_B_MARK
,
2054 static const unsigned int hscif2_clk_b_pins
[] = {
2058 static const unsigned int hscif2_clk_b_mux
[] = {
2061 static const unsigned int hscif2_ctrl_b_pins
[] = {
2063 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2065 static const unsigned int hscif2_ctrl_b_mux
[] = {
2066 HRTS2_N_B_MARK
, HCTS2_N_B_MARK
,
2068 /* - HSCIF3 ----------------------------------------------------------------- */
2069 static const unsigned int hscif3_data_a_pins
[] = {
2071 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2073 static const unsigned int hscif3_data_a_mux
[] = {
2074 HRX3_A_MARK
, HTX3_A_MARK
,
2076 static const unsigned int hscif3_clk_pins
[] = {
2080 static const unsigned int hscif3_clk_mux
[] = {
2083 static const unsigned int hscif3_ctrl_pins
[] = {
2085 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2087 static const unsigned int hscif3_ctrl_mux
[] = {
2088 HRTS3_N_MARK
, HCTS3_N_MARK
,
2091 static const unsigned int hscif3_data_b_pins
[] = {
2093 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2095 static const unsigned int hscif3_data_b_mux
[] = {
2096 HRX3_B_MARK
, HTX3_B_MARK
,
2098 static const unsigned int hscif3_data_c_pins
[] = {
2100 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2102 static const unsigned int hscif3_data_c_mux
[] = {
2103 HRX3_C_MARK
, HTX3_C_MARK
,
2105 static const unsigned int hscif3_data_d_pins
[] = {
2107 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2109 static const unsigned int hscif3_data_d_mux
[] = {
2110 HRX3_D_MARK
, HTX3_D_MARK
,
2112 /* - HSCIF4 ----------------------------------------------------------------- */
2113 static const unsigned int hscif4_data_a_pins
[] = {
2115 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2117 static const unsigned int hscif4_data_a_mux
[] = {
2118 HRX4_A_MARK
, HTX4_A_MARK
,
2120 static const unsigned int hscif4_clk_pins
[] = {
2124 static const unsigned int hscif4_clk_mux
[] = {
2127 static const unsigned int hscif4_ctrl_pins
[] = {
2129 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2131 static const unsigned int hscif4_ctrl_mux
[] = {
2132 HRTS4_N_MARK
, HCTS3_N_MARK
,
2135 static const unsigned int hscif4_data_b_pins
[] = {
2137 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2139 static const unsigned int hscif4_data_b_mux
[] = {
2140 HRX4_B_MARK
, HTX4_B_MARK
,
2143 /* - I2C -------------------------------------------------------------------- */
2144 static const unsigned int i2c1_a_pins
[] = {
2146 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2148 static const unsigned int i2c1_a_mux
[] = {
2149 SDA1_A_MARK
, SCL1_A_MARK
,
2151 static const unsigned int i2c1_b_pins
[] = {
2153 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2155 static const unsigned int i2c1_b_mux
[] = {
2156 SDA1_B_MARK
, SCL1_B_MARK
,
2158 static const unsigned int i2c2_a_pins
[] = {
2160 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2162 static const unsigned int i2c2_a_mux
[] = {
2163 SDA2_A_MARK
, SCL2_A_MARK
,
2165 static const unsigned int i2c2_b_pins
[] = {
2167 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2169 static const unsigned int i2c2_b_mux
[] = {
2170 SDA2_B_MARK
, SCL2_B_MARK
,
2172 static const unsigned int i2c6_a_pins
[] = {
2174 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2176 static const unsigned int i2c6_a_mux
[] = {
2177 SDA6_A_MARK
, SCL6_A_MARK
,
2179 static const unsigned int i2c6_b_pins
[] = {
2181 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2183 static const unsigned int i2c6_b_mux
[] = {
2184 SDA6_B_MARK
, SCL6_B_MARK
,
2186 static const unsigned int i2c6_c_pins
[] = {
2188 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2190 static const unsigned int i2c6_c_mux
[] = {
2191 SDA6_C_MARK
, SCL6_C_MARK
,
2194 /* - INTC-EX ---------------------------------------------------------------- */
2195 static const unsigned int intc_ex_irq0_pins
[] = {
2199 static const unsigned int intc_ex_irq0_mux
[] = {
2202 static const unsigned int intc_ex_irq1_pins
[] = {
2206 static const unsigned int intc_ex_irq1_mux
[] = {
2209 static const unsigned int intc_ex_irq2_pins
[] = {
2213 static const unsigned int intc_ex_irq2_mux
[] = {
2216 static const unsigned int intc_ex_irq3_pins
[] = {
2220 static const unsigned int intc_ex_irq3_mux
[] = {
2223 static const unsigned int intc_ex_irq4_pins
[] = {
2227 static const unsigned int intc_ex_irq4_mux
[] = {
2230 static const unsigned int intc_ex_irq5_pins
[] = {
2234 static const unsigned int intc_ex_irq5_mux
[] = {
2238 /* - MSIOF0 ----------------------------------------------------------------- */
2239 static const unsigned int msiof0_clk_pins
[] = {
2243 static const unsigned int msiof0_clk_mux
[] = {
2246 static const unsigned int msiof0_sync_pins
[] = {
2250 static const unsigned int msiof0_sync_mux
[] = {
2253 static const unsigned int msiof0_ss1_pins
[] = {
2257 static const unsigned int msiof0_ss1_mux
[] = {
2260 static const unsigned int msiof0_ss2_pins
[] = {
2264 static const unsigned int msiof0_ss2_mux
[] = {
2267 static const unsigned int msiof0_txd_pins
[] = {
2271 static const unsigned int msiof0_txd_mux
[] = {
2274 static const unsigned int msiof0_rxd_pins
[] = {
2278 static const unsigned int msiof0_rxd_mux
[] = {
2281 /* - MSIOF1 ----------------------------------------------------------------- */
2282 static const unsigned int msiof1_clk_a_pins
[] = {
2286 static const unsigned int msiof1_clk_a_mux
[] = {
2289 static const unsigned int msiof1_sync_a_pins
[] = {
2293 static const unsigned int msiof1_sync_a_mux
[] = {
2296 static const unsigned int msiof1_ss1_a_pins
[] = {
2300 static const unsigned int msiof1_ss1_a_mux
[] = {
2303 static const unsigned int msiof1_ss2_a_pins
[] = {
2307 static const unsigned int msiof1_ss2_a_mux
[] = {
2310 static const unsigned int msiof1_txd_a_pins
[] = {
2314 static const unsigned int msiof1_txd_a_mux
[] = {
2317 static const unsigned int msiof1_rxd_a_pins
[] = {
2321 static const unsigned int msiof1_rxd_a_mux
[] = {
2324 static const unsigned int msiof1_clk_b_pins
[] = {
2328 static const unsigned int msiof1_clk_b_mux
[] = {
2331 static const unsigned int msiof1_sync_b_pins
[] = {
2335 static const unsigned int msiof1_sync_b_mux
[] = {
2338 static const unsigned int msiof1_ss1_b_pins
[] = {
2342 static const unsigned int msiof1_ss1_b_mux
[] = {
2345 static const unsigned int msiof1_ss2_b_pins
[] = {
2349 static const unsigned int msiof1_ss2_b_mux
[] = {
2352 static const unsigned int msiof1_txd_b_pins
[] = {
2356 static const unsigned int msiof1_txd_b_mux
[] = {
2359 static const unsigned int msiof1_rxd_b_pins
[] = {
2363 static const unsigned int msiof1_rxd_b_mux
[] = {
2366 static const unsigned int msiof1_clk_c_pins
[] = {
2370 static const unsigned int msiof1_clk_c_mux
[] = {
2373 static const unsigned int msiof1_sync_c_pins
[] = {
2377 static const unsigned int msiof1_sync_c_mux
[] = {
2380 static const unsigned int msiof1_ss1_c_pins
[] = {
2384 static const unsigned int msiof1_ss1_c_mux
[] = {
2387 static const unsigned int msiof1_ss2_c_pins
[] = {
2391 static const unsigned int msiof1_ss2_c_mux
[] = {
2394 static const unsigned int msiof1_txd_c_pins
[] = {
2398 static const unsigned int msiof1_txd_c_mux
[] = {
2401 static const unsigned int msiof1_rxd_c_pins
[] = {
2405 static const unsigned int msiof1_rxd_c_mux
[] = {
2408 static const unsigned int msiof1_clk_d_pins
[] = {
2412 static const unsigned int msiof1_clk_d_mux
[] = {
2415 static const unsigned int msiof1_sync_d_pins
[] = {
2419 static const unsigned int msiof1_sync_d_mux
[] = {
2422 static const unsigned int msiof1_ss1_d_pins
[] = {
2426 static const unsigned int msiof1_ss1_d_mux
[] = {
2429 static const unsigned int msiof1_ss2_d_pins
[] = {
2433 static const unsigned int msiof1_ss2_d_mux
[] = {
2436 static const unsigned int msiof1_txd_d_pins
[] = {
2440 static const unsigned int msiof1_txd_d_mux
[] = {
2443 static const unsigned int msiof1_rxd_d_pins
[] = {
2447 static const unsigned int msiof1_rxd_d_mux
[] = {
2450 static const unsigned int msiof1_clk_e_pins
[] = {
2454 static const unsigned int msiof1_clk_e_mux
[] = {
2457 static const unsigned int msiof1_sync_e_pins
[] = {
2461 static const unsigned int msiof1_sync_e_mux
[] = {
2464 static const unsigned int msiof1_ss1_e_pins
[] = {
2468 static const unsigned int msiof1_ss1_e_mux
[] = {
2471 static const unsigned int msiof1_ss2_e_pins
[] = {
2475 static const unsigned int msiof1_ss2_e_mux
[] = {
2478 static const unsigned int msiof1_txd_e_pins
[] = {
2482 static const unsigned int msiof1_txd_e_mux
[] = {
2485 static const unsigned int msiof1_rxd_e_pins
[] = {
2489 static const unsigned int msiof1_rxd_e_mux
[] = {
2492 static const unsigned int msiof1_clk_f_pins
[] = {
2496 static const unsigned int msiof1_clk_f_mux
[] = {
2499 static const unsigned int msiof1_sync_f_pins
[] = {
2503 static const unsigned int msiof1_sync_f_mux
[] = {
2506 static const unsigned int msiof1_ss1_f_pins
[] = {
2510 static const unsigned int msiof1_ss1_f_mux
[] = {
2513 static const unsigned int msiof1_ss2_f_pins
[] = {
2517 static const unsigned int msiof1_ss2_f_mux
[] = {
2520 static const unsigned int msiof1_txd_f_pins
[] = {
2524 static const unsigned int msiof1_txd_f_mux
[] = {
2527 static const unsigned int msiof1_rxd_f_pins
[] = {
2531 static const unsigned int msiof1_rxd_f_mux
[] = {
2534 static const unsigned int msiof1_clk_g_pins
[] = {
2538 static const unsigned int msiof1_clk_g_mux
[] = {
2541 static const unsigned int msiof1_sync_g_pins
[] = {
2545 static const unsigned int msiof1_sync_g_mux
[] = {
2548 static const unsigned int msiof1_ss1_g_pins
[] = {
2552 static const unsigned int msiof1_ss1_g_mux
[] = {
2555 static const unsigned int msiof1_ss2_g_pins
[] = {
2559 static const unsigned int msiof1_ss2_g_mux
[] = {
2562 static const unsigned int msiof1_txd_g_pins
[] = {
2566 static const unsigned int msiof1_txd_g_mux
[] = {
2569 static const unsigned int msiof1_rxd_g_pins
[] = {
2573 static const unsigned int msiof1_rxd_g_mux
[] = {
2576 /* - MSIOF2 ----------------------------------------------------------------- */
2577 static const unsigned int msiof2_clk_a_pins
[] = {
2581 static const unsigned int msiof2_clk_a_mux
[] = {
2584 static const unsigned int msiof2_sync_a_pins
[] = {
2588 static const unsigned int msiof2_sync_a_mux
[] = {
2591 static const unsigned int msiof2_ss1_a_pins
[] = {
2595 static const unsigned int msiof2_ss1_a_mux
[] = {
2598 static const unsigned int msiof2_ss2_a_pins
[] = {
2602 static const unsigned int msiof2_ss2_a_mux
[] = {
2605 static const unsigned int msiof2_txd_a_pins
[] = {
2609 static const unsigned int msiof2_txd_a_mux
[] = {
2612 static const unsigned int msiof2_rxd_a_pins
[] = {
2616 static const unsigned int msiof2_rxd_a_mux
[] = {
2619 static const unsigned int msiof2_clk_b_pins
[] = {
2623 static const unsigned int msiof2_clk_b_mux
[] = {
2626 static const unsigned int msiof2_sync_b_pins
[] = {
2630 static const unsigned int msiof2_sync_b_mux
[] = {
2633 static const unsigned int msiof2_ss1_b_pins
[] = {
2637 static const unsigned int msiof2_ss1_b_mux
[] = {
2640 static const unsigned int msiof2_ss2_b_pins
[] = {
2644 static const unsigned int msiof2_ss2_b_mux
[] = {
2647 static const unsigned int msiof2_txd_b_pins
[] = {
2651 static const unsigned int msiof2_txd_b_mux
[] = {
2654 static const unsigned int msiof2_rxd_b_pins
[] = {
2658 static const unsigned int msiof2_rxd_b_mux
[] = {
2661 static const unsigned int msiof2_clk_c_pins
[] = {
2665 static const unsigned int msiof2_clk_c_mux
[] = {
2668 static const unsigned int msiof2_sync_c_pins
[] = {
2672 static const unsigned int msiof2_sync_c_mux
[] = {
2675 static const unsigned int msiof2_ss1_c_pins
[] = {
2679 static const unsigned int msiof2_ss1_c_mux
[] = {
2682 static const unsigned int msiof2_ss2_c_pins
[] = {
2686 static const unsigned int msiof2_ss2_c_mux
[] = {
2689 static const unsigned int msiof2_txd_c_pins
[] = {
2693 static const unsigned int msiof2_txd_c_mux
[] = {
2696 static const unsigned int msiof2_rxd_c_pins
[] = {
2700 static const unsigned int msiof2_rxd_c_mux
[] = {
2703 static const unsigned int msiof2_clk_d_pins
[] = {
2707 static const unsigned int msiof2_clk_d_mux
[] = {
2710 static const unsigned int msiof2_sync_d_pins
[] = {
2714 static const unsigned int msiof2_sync_d_mux
[] = {
2717 static const unsigned int msiof2_ss1_d_pins
[] = {
2721 static const unsigned int msiof2_ss1_d_mux
[] = {
2724 static const unsigned int msiof2_ss2_d_pins
[] = {
2728 static const unsigned int msiof2_ss2_d_mux
[] = {
2731 static const unsigned int msiof2_txd_d_pins
[] = {
2735 static const unsigned int msiof2_txd_d_mux
[] = {
2738 static const unsigned int msiof2_rxd_d_pins
[] = {
2742 static const unsigned int msiof2_rxd_d_mux
[] = {
2745 /* - MSIOF3 ----------------------------------------------------------------- */
2746 static const unsigned int msiof3_clk_a_pins
[] = {
2750 static const unsigned int msiof3_clk_a_mux
[] = {
2753 static const unsigned int msiof3_sync_a_pins
[] = {
2757 static const unsigned int msiof3_sync_a_mux
[] = {
2760 static const unsigned int msiof3_ss1_a_pins
[] = {
2764 static const unsigned int msiof3_ss1_a_mux
[] = {
2767 static const unsigned int msiof3_ss2_a_pins
[] = {
2771 static const unsigned int msiof3_ss2_a_mux
[] = {
2774 static const unsigned int msiof3_txd_a_pins
[] = {
2778 static const unsigned int msiof3_txd_a_mux
[] = {
2781 static const unsigned int msiof3_rxd_a_pins
[] = {
2785 static const unsigned int msiof3_rxd_a_mux
[] = {
2788 static const unsigned int msiof3_clk_b_pins
[] = {
2792 static const unsigned int msiof3_clk_b_mux
[] = {
2795 static const unsigned int msiof3_sync_b_pins
[] = {
2799 static const unsigned int msiof3_sync_b_mux
[] = {
2802 static const unsigned int msiof3_ss1_b_pins
[] = {
2806 static const unsigned int msiof3_ss1_b_mux
[] = {
2809 static const unsigned int msiof3_ss2_b_pins
[] = {
2813 static const unsigned int msiof3_ss2_b_mux
[] = {
2816 static const unsigned int msiof3_txd_b_pins
[] = {
2820 static const unsigned int msiof3_txd_b_mux
[] = {
2823 static const unsigned int msiof3_rxd_b_pins
[] = {
2827 static const unsigned int msiof3_rxd_b_mux
[] = {
2830 static const unsigned int msiof3_clk_c_pins
[] = {
2834 static const unsigned int msiof3_clk_c_mux
[] = {
2837 static const unsigned int msiof3_sync_c_pins
[] = {
2841 static const unsigned int msiof3_sync_c_mux
[] = {
2844 static const unsigned int msiof3_txd_c_pins
[] = {
2848 static const unsigned int msiof3_txd_c_mux
[] = {
2851 static const unsigned int msiof3_rxd_c_pins
[] = {
2855 static const unsigned int msiof3_rxd_c_mux
[] = {
2858 static const unsigned int msiof3_clk_d_pins
[] = {
2862 static const unsigned int msiof3_clk_d_mux
[] = {
2865 static const unsigned int msiof3_sync_d_pins
[] = {
2869 static const unsigned int msiof3_sync_d_mux
[] = {
2872 static const unsigned int msiof3_ss1_d_pins
[] = {
2876 static const unsigned int msiof3_ss1_d_mux
[] = {
2879 static const unsigned int msiof3_txd_d_pins
[] = {
2883 static const unsigned int msiof3_txd_d_mux
[] = {
2886 static const unsigned int msiof3_rxd_d_pins
[] = {
2890 static const unsigned int msiof3_rxd_d_mux
[] = {
2894 /* - PWM0 --------------------------------------------------------------------*/
2895 static const unsigned int pwm0_pins
[] = {
2899 static const unsigned int pwm0_mux
[] = {
2902 /* - PWM1 --------------------------------------------------------------------*/
2903 static const unsigned int pwm1_a_pins
[] = {
2907 static const unsigned int pwm1_a_mux
[] = {
2910 static const unsigned int pwm1_b_pins
[] = {
2914 static const unsigned int pwm1_b_mux
[] = {
2917 /* - PWM2 --------------------------------------------------------------------*/
2918 static const unsigned int pwm2_a_pins
[] = {
2922 static const unsigned int pwm2_a_mux
[] = {
2925 static const unsigned int pwm2_b_pins
[] = {
2929 static const unsigned int pwm2_b_mux
[] = {
2932 /* - PWM3 --------------------------------------------------------------------*/
2933 static const unsigned int pwm3_a_pins
[] = {
2937 static const unsigned int pwm3_a_mux
[] = {
2940 static const unsigned int pwm3_b_pins
[] = {
2944 static const unsigned int pwm3_b_mux
[] = {
2947 /* - PWM4 --------------------------------------------------------------------*/
2948 static const unsigned int pwm4_a_pins
[] = {
2952 static const unsigned int pwm4_a_mux
[] = {
2955 static const unsigned int pwm4_b_pins
[] = {
2959 static const unsigned int pwm4_b_mux
[] = {
2962 /* - PWM5 --------------------------------------------------------------------*/
2963 static const unsigned int pwm5_a_pins
[] = {
2967 static const unsigned int pwm5_a_mux
[] = {
2970 static const unsigned int pwm5_b_pins
[] = {
2974 static const unsigned int pwm5_b_mux
[] = {
2977 /* - PWM6 --------------------------------------------------------------------*/
2978 static const unsigned int pwm6_a_pins
[] = {
2982 static const unsigned int pwm6_a_mux
[] = {
2985 static const unsigned int pwm6_b_pins
[] = {
2989 static const unsigned int pwm6_b_mux
[] = {
2993 /* - SATA --------------------------------------------------------------------*/
2994 static const unsigned int sata0_devslp_a_pins
[] = {
2998 static const unsigned int sata0_devslp_a_mux
[] = {
3001 static const unsigned int sata0_devslp_b_pins
[] = {
3005 static const unsigned int sata0_devslp_b_mux
[] = {
3009 /* - SCIF0 ------------------------------------------------------------------ */
3010 static const unsigned int scif0_data_pins
[] = {
3012 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3014 static const unsigned int scif0_data_mux
[] = {
3017 static const unsigned int scif0_clk_pins
[] = {
3021 static const unsigned int scif0_clk_mux
[] = {
3024 static const unsigned int scif0_ctrl_pins
[] = {
3026 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3028 static const unsigned int scif0_ctrl_mux
[] = {
3029 RTS0_N_TANS_MARK
, CTS0_N_MARK
,
3031 /* - SCIF1 ------------------------------------------------------------------ */
3032 static const unsigned int scif1_data_a_pins
[] = {
3034 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3036 static const unsigned int scif1_data_a_mux
[] = {
3037 RX1_A_MARK
, TX1_A_MARK
,
3039 static const unsigned int scif1_clk_pins
[] = {
3043 static const unsigned int scif1_clk_mux
[] = {
3046 static const unsigned int scif1_ctrl_pins
[] = {
3048 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3050 static const unsigned int scif1_ctrl_mux
[] = {
3051 RTS1_N_TANS_MARK
, CTS1_N_MARK
,
3054 static const unsigned int scif1_data_b_pins
[] = {
3056 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3058 static const unsigned int scif1_data_b_mux
[] = {
3059 RX1_B_MARK
, TX1_B_MARK
,
3061 /* - SCIF2 ------------------------------------------------------------------ */
3062 static const unsigned int scif2_data_a_pins
[] = {
3064 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3066 static const unsigned int scif2_data_a_mux
[] = {
3067 RX2_A_MARK
, TX2_A_MARK
,
3069 static const unsigned int scif2_clk_pins
[] = {
3073 static const unsigned int scif2_clk_mux
[] = {
3076 static const unsigned int scif2_data_b_pins
[] = {
3078 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3080 static const unsigned int scif2_data_b_mux
[] = {
3081 RX2_B_MARK
, TX2_B_MARK
,
3083 /* - SCIF3 ------------------------------------------------------------------ */
3084 static const unsigned int scif3_data_a_pins
[] = {
3086 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3088 static const unsigned int scif3_data_a_mux
[] = {
3089 RX3_A_MARK
, TX3_A_MARK
,
3091 static const unsigned int scif3_clk_pins
[] = {
3095 static const unsigned int scif3_clk_mux
[] = {
3098 static const unsigned int scif3_ctrl_pins
[] = {
3100 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3102 static const unsigned int scif3_ctrl_mux
[] = {
3103 RTS3_N_TANS_MARK
, CTS3_N_MARK
,
3105 static const unsigned int scif3_data_b_pins
[] = {
3107 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3109 static const unsigned int scif3_data_b_mux
[] = {
3110 RX3_B_MARK
, TX3_B_MARK
,
3112 /* - SCIF4 ------------------------------------------------------------------ */
3113 static const unsigned int scif4_data_a_pins
[] = {
3115 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3117 static const unsigned int scif4_data_a_mux
[] = {
3118 RX4_A_MARK
, TX4_A_MARK
,
3120 static const unsigned int scif4_clk_a_pins
[] = {
3124 static const unsigned int scif4_clk_a_mux
[] = {
3127 static const unsigned int scif4_ctrl_a_pins
[] = {
3129 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3131 static const unsigned int scif4_ctrl_a_mux
[] = {
3132 RTS4_N_TANS_A_MARK
, CTS4_N_A_MARK
,
3134 static const unsigned int scif4_data_b_pins
[] = {
3136 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3138 static const unsigned int scif4_data_b_mux
[] = {
3139 RX4_B_MARK
, TX4_B_MARK
,
3141 static const unsigned int scif4_clk_b_pins
[] = {
3145 static const unsigned int scif4_clk_b_mux
[] = {
3148 static const unsigned int scif4_ctrl_b_pins
[] = {
3150 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3152 static const unsigned int scif4_ctrl_b_mux
[] = {
3153 RTS4_N_TANS_B_MARK
, CTS4_N_B_MARK
,
3155 static const unsigned int scif4_data_c_pins
[] = {
3157 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3159 static const unsigned int scif4_data_c_mux
[] = {
3160 RX4_C_MARK
, TX4_C_MARK
,
3162 static const unsigned int scif4_clk_c_pins
[] = {
3166 static const unsigned int scif4_clk_c_mux
[] = {
3169 static const unsigned int scif4_ctrl_c_pins
[] = {
3171 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3173 static const unsigned int scif4_ctrl_c_mux
[] = {
3174 RTS4_N_TANS_C_MARK
, CTS4_N_C_MARK
,
3176 /* - SCIF5 ------------------------------------------------------------------ */
3177 static const unsigned int scif5_data_pins
[] = {
3179 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3181 static const unsigned int scif5_data_mux
[] = {
3184 static const unsigned int scif5_clk_pins
[] = {
3188 static const unsigned int scif5_clk_mux
[] = {
3191 /* - SDHI0 ------------------------------------------------------------------ */
3192 static const unsigned int sdhi0_data1_pins
[] = {
3196 static const unsigned int sdhi0_data1_mux
[] = {
3199 static const unsigned int sdhi0_data4_pins
[] = {
3201 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3202 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3204 static const unsigned int sdhi0_data4_mux
[] = {
3205 SD0_DAT0_MARK
, SD0_DAT1_MARK
,
3206 SD0_DAT2_MARK
, SD0_DAT3_MARK
,
3208 static const unsigned int sdhi0_ctrl_pins
[] = {
3210 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3212 static const unsigned int sdhi0_ctrl_mux
[] = {
3213 SD0_CLK_MARK
, SD0_CMD_MARK
,
3215 static const unsigned int sdhi0_cd_pins
[] = {
3219 static const unsigned int sdhi0_cd_mux
[] = {
3222 static const unsigned int sdhi0_wp_pins
[] = {
3226 static const unsigned int sdhi0_wp_mux
[] = {
3229 /* - SDHI1 ------------------------------------------------------------------ */
3230 static const unsigned int sdhi1_data1_pins
[] = {
3234 static const unsigned int sdhi1_data1_mux
[] = {
3237 static const unsigned int sdhi1_data4_pins
[] = {
3239 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3240 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3242 static const unsigned int sdhi1_data4_mux
[] = {
3243 SD1_DAT0_MARK
, SD1_DAT1_MARK
,
3244 SD1_DAT2_MARK
, SD1_DAT3_MARK
,
3246 static const unsigned int sdhi1_ctrl_pins
[] = {
3248 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3250 static const unsigned int sdhi1_ctrl_mux
[] = {
3251 SD1_CLK_MARK
, SD1_CMD_MARK
,
3253 static const unsigned int sdhi1_cd_pins
[] = {
3257 static const unsigned int sdhi1_cd_mux
[] = {
3260 static const unsigned int sdhi1_wp_pins
[] = {
3264 static const unsigned int sdhi1_wp_mux
[] = {
3267 /* - SDHI2 ------------------------------------------------------------------ */
3268 static const unsigned int sdhi2_data1_pins
[] = {
3272 static const unsigned int sdhi2_data1_mux
[] = {
3275 static const unsigned int sdhi2_data4_pins
[] = {
3277 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3278 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3280 static const unsigned int sdhi2_data4_mux
[] = {
3281 SD2_DAT0_MARK
, SD2_DAT1_MARK
,
3282 SD2_DAT2_MARK
, SD2_DAT3_MARK
,
3284 static const unsigned int sdhi2_data8_pins
[] = {
3286 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3287 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3288 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3289 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3291 static const unsigned int sdhi2_data8_mux
[] = {
3292 SD2_DAT0_MARK
, SD2_DAT1_MARK
,
3293 SD2_DAT2_MARK
, SD2_DAT3_MARK
,
3294 SD2_DAT4_MARK
, SD2_DAT5_MARK
,
3295 SD2_DAT6_MARK
, SD2_DAT7_MARK
,
3297 static const unsigned int sdhi2_ctrl_pins
[] = {
3299 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3301 static const unsigned int sdhi2_ctrl_mux
[] = {
3302 SD2_CLK_MARK
, SD2_CMD_MARK
,
3304 static const unsigned int sdhi2_cd_a_pins
[] = {
3308 static const unsigned int sdhi2_cd_a_mux
[] = {
3311 static const unsigned int sdhi2_cd_b_pins
[] = {
3315 static const unsigned int sdhi2_cd_b_mux
[] = {
3318 static const unsigned int sdhi2_wp_a_pins
[] = {
3322 static const unsigned int sdhi2_wp_a_mux
[] = {
3325 static const unsigned int sdhi2_wp_b_pins
[] = {
3329 static const unsigned int sdhi2_wp_b_mux
[] = {
3332 static const unsigned int sdhi2_ds_pins
[] = {
3336 static const unsigned int sdhi2_ds_mux
[] = {
3339 /* - SDHI3 ------------------------------------------------------------------ */
3340 static const unsigned int sdhi3_data1_pins
[] = {
3344 static const unsigned int sdhi3_data1_mux
[] = {
3347 static const unsigned int sdhi3_data4_pins
[] = {
3349 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3350 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3352 static const unsigned int sdhi3_data4_mux
[] = {
3353 SD3_DAT0_MARK
, SD3_DAT1_MARK
,
3354 SD3_DAT2_MARK
, SD3_DAT3_MARK
,
3356 static const unsigned int sdhi3_data8_pins
[] = {
3358 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3359 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3360 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3361 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3363 static const unsigned int sdhi3_data8_mux
[] = {
3364 SD3_DAT0_MARK
, SD3_DAT1_MARK
,
3365 SD3_DAT2_MARK
, SD3_DAT3_MARK
,
3366 SD3_DAT4_MARK
, SD3_DAT5_MARK
,
3367 SD3_DAT6_MARK
, SD3_DAT7_MARK
,
3369 static const unsigned int sdhi3_ctrl_pins
[] = {
3371 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3373 static const unsigned int sdhi3_ctrl_mux
[] = {
3374 SD3_CLK_MARK
, SD3_CMD_MARK
,
3376 static const unsigned int sdhi3_cd_pins
[] = {
3380 static const unsigned int sdhi3_cd_mux
[] = {
3383 static const unsigned int sdhi3_wp_pins
[] = {
3387 static const unsigned int sdhi3_wp_mux
[] = {
3390 static const unsigned int sdhi3_ds_pins
[] = {
3394 static const unsigned int sdhi3_ds_mux
[] = {
3398 /* - SCIF Clock ------------------------------------------------------------- */
3399 static const unsigned int scif_clk_a_pins
[] = {
3403 static const unsigned int scif_clk_a_mux
[] = {
3406 static const unsigned int scif_clk_b_pins
[] = {
3410 static const unsigned int scif_clk_b_mux
[] = {
3414 /* - SSI -------------------------------------------------------------------- */
3415 static const unsigned int ssi0_data_pins
[] = {
3419 static const unsigned int ssi0_data_mux
[] = {
3422 static const unsigned int ssi01239_ctrl_pins
[] = {
3424 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3426 static const unsigned int ssi01239_ctrl_mux
[] = {
3427 SSI_SCK01239_MARK
, SSI_WS01239_MARK
,
3429 static const unsigned int ssi1_data_a_pins
[] = {
3433 static const unsigned int ssi1_data_a_mux
[] = {
3436 static const unsigned int ssi1_data_b_pins
[] = {
3440 static const unsigned int ssi1_data_b_mux
[] = {
3443 static const unsigned int ssi1_ctrl_a_pins
[] = {
3445 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3447 static const unsigned int ssi1_ctrl_a_mux
[] = {
3448 SSI_SCK1_A_MARK
, SSI_WS1_A_MARK
,
3450 static const unsigned int ssi1_ctrl_b_pins
[] = {
3452 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3454 static const unsigned int ssi1_ctrl_b_mux
[] = {
3455 SSI_SCK1_B_MARK
, SSI_WS1_B_MARK
,
3457 static const unsigned int ssi2_data_a_pins
[] = {
3461 static const unsigned int ssi2_data_a_mux
[] = {
3464 static const unsigned int ssi2_data_b_pins
[] = {
3468 static const unsigned int ssi2_data_b_mux
[] = {
3471 static const unsigned int ssi2_ctrl_a_pins
[] = {
3473 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3475 static const unsigned int ssi2_ctrl_a_mux
[] = {
3476 SSI_SCK2_A_MARK
, SSI_WS2_A_MARK
,
3478 static const unsigned int ssi2_ctrl_b_pins
[] = {
3480 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3482 static const unsigned int ssi2_ctrl_b_mux
[] = {
3483 SSI_SCK2_B_MARK
, SSI_WS2_B_MARK
,
3485 static const unsigned int ssi3_data_pins
[] = {
3489 static const unsigned int ssi3_data_mux
[] = {
3492 static const unsigned int ssi34_ctrl_pins
[] = {
3494 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3496 static const unsigned int ssi34_ctrl_mux
[] = {
3497 SSI_SCK34_MARK
, SSI_WS34_MARK
,
3499 static const unsigned int ssi4_data_pins
[] = {
3503 static const unsigned int ssi4_data_mux
[] = {
3506 static const unsigned int ssi4_ctrl_pins
[] = {
3508 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3510 static const unsigned int ssi4_ctrl_mux
[] = {
3511 SSI_SCK4_MARK
, SSI_WS4_MARK
,
3513 static const unsigned int ssi5_data_pins
[] = {
3517 static const unsigned int ssi5_data_mux
[] = {
3520 static const unsigned int ssi5_ctrl_pins
[] = {
3522 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3524 static const unsigned int ssi5_ctrl_mux
[] = {
3525 SSI_SCK5_MARK
, SSI_WS5_MARK
,
3527 static const unsigned int ssi6_data_pins
[] = {
3531 static const unsigned int ssi6_data_mux
[] = {
3534 static const unsigned int ssi6_ctrl_pins
[] = {
3536 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3538 static const unsigned int ssi6_ctrl_mux
[] = {
3539 SSI_SCK6_MARK
, SSI_WS6_MARK
,
3541 static const unsigned int ssi7_data_pins
[] = {
3545 static const unsigned int ssi7_data_mux
[] = {
3548 static const unsigned int ssi78_ctrl_pins
[] = {
3550 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3552 static const unsigned int ssi78_ctrl_mux
[] = {
3553 SSI_SCK78_MARK
, SSI_WS78_MARK
,
3555 static const unsigned int ssi8_data_pins
[] = {
3559 static const unsigned int ssi8_data_mux
[] = {
3562 static const unsigned int ssi9_data_a_pins
[] = {
3566 static const unsigned int ssi9_data_a_mux
[] = {
3569 static const unsigned int ssi9_data_b_pins
[] = {
3573 static const unsigned int ssi9_data_b_mux
[] = {
3576 static const unsigned int ssi9_ctrl_a_pins
[] = {
3578 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3580 static const unsigned int ssi9_ctrl_a_mux
[] = {
3581 SSI_SCK9_A_MARK
, SSI_WS9_A_MARK
,
3583 static const unsigned int ssi9_ctrl_b_pins
[] = {
3585 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3587 static const unsigned int ssi9_ctrl_b_mux
[] = {
3588 SSI_SCK9_B_MARK
, SSI_WS9_B_MARK
,
3591 /* - USB0 ------------------------------------------------------------------- */
3592 static const unsigned int usb0_pins
[] = {
3594 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3596 static const unsigned int usb0_mux
[] = {
3597 USB0_PWEN_MARK
, USB0_OVC_MARK
,
3599 /* - USB1 ------------------------------------------------------------------- */
3600 static const unsigned int usb1_pins
[] = {
3602 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3604 static const unsigned int usb1_mux
[] = {
3605 USB1_PWEN_MARK
, USB1_OVC_MARK
,
3607 /* - USB2 ------------------------------------------------------------------- */
3608 static const unsigned int usb2_pins
[] = {
3610 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3612 static const unsigned int usb2_mux
[] = {
3613 USB2_PWEN_MARK
, USB2_OVC_MARK
,
3616 static const struct sh_pfc_pin_group pinmux_groups
[] = {
3617 SH_PFC_PIN_GROUP(audio_clk_a_a
),
3618 SH_PFC_PIN_GROUP(audio_clk_a_b
),
3619 SH_PFC_PIN_GROUP(audio_clk_a_c
),
3620 SH_PFC_PIN_GROUP(audio_clk_b_a
),
3621 SH_PFC_PIN_GROUP(audio_clk_b_b
),
3622 SH_PFC_PIN_GROUP(audio_clk_c_a
),
3623 SH_PFC_PIN_GROUP(audio_clk_c_b
),
3624 SH_PFC_PIN_GROUP(audio_clkout_a
),
3625 SH_PFC_PIN_GROUP(audio_clkout_b
),
3626 SH_PFC_PIN_GROUP(audio_clkout_c
),
3627 SH_PFC_PIN_GROUP(audio_clkout_d
),
3628 SH_PFC_PIN_GROUP(audio_clkout1_a
),
3629 SH_PFC_PIN_GROUP(audio_clkout1_b
),
3630 SH_PFC_PIN_GROUP(audio_clkout2_a
),
3631 SH_PFC_PIN_GROUP(audio_clkout2_b
),
3632 SH_PFC_PIN_GROUP(audio_clkout3_a
),
3633 SH_PFC_PIN_GROUP(audio_clkout3_b
),
3634 SH_PFC_PIN_GROUP(avb_link
),
3635 SH_PFC_PIN_GROUP(avb_magic
),
3636 SH_PFC_PIN_GROUP(avb_phy_int
),
3637 SH_PFC_PIN_GROUP(avb_mdc
),
3638 SH_PFC_PIN_GROUP(avb_avtp_pps
),
3639 SH_PFC_PIN_GROUP(avb_avtp_match_a
),
3640 SH_PFC_PIN_GROUP(avb_avtp_capture_a
),
3641 SH_PFC_PIN_GROUP(avb_avtp_match_b
),
3642 SH_PFC_PIN_GROUP(avb_avtp_capture_b
),
3643 SH_PFC_PIN_GROUP(can0_data_a
),
3644 SH_PFC_PIN_GROUP(can0_data_b
),
3645 SH_PFC_PIN_GROUP(can1_data
),
3646 SH_PFC_PIN_GROUP(can_clk
),
3647 SH_PFC_PIN_GROUP(canfd0_data_a
),
3648 SH_PFC_PIN_GROUP(canfd0_data_b
),
3649 SH_PFC_PIN_GROUP(canfd1_data
),
3650 SH_PFC_PIN_GROUP(drif0_ctrl_a
),
3651 SH_PFC_PIN_GROUP(drif0_data0_a
),
3652 SH_PFC_PIN_GROUP(drif0_data1_a
),
3653 SH_PFC_PIN_GROUP(drif0_ctrl_b
),
3654 SH_PFC_PIN_GROUP(drif0_data0_b
),
3655 SH_PFC_PIN_GROUP(drif0_data1_b
),
3656 SH_PFC_PIN_GROUP(drif0_ctrl_c
),
3657 SH_PFC_PIN_GROUP(drif0_data0_c
),
3658 SH_PFC_PIN_GROUP(drif0_data1_c
),
3659 SH_PFC_PIN_GROUP(drif1_ctrl_a
),
3660 SH_PFC_PIN_GROUP(drif1_data0_a
),
3661 SH_PFC_PIN_GROUP(drif1_data1_a
),
3662 SH_PFC_PIN_GROUP(drif1_ctrl_b
),
3663 SH_PFC_PIN_GROUP(drif1_data0_b
),
3664 SH_PFC_PIN_GROUP(drif1_data1_b
),
3665 SH_PFC_PIN_GROUP(drif1_ctrl_c
),
3666 SH_PFC_PIN_GROUP(drif1_data0_c
),
3667 SH_PFC_PIN_GROUP(drif1_data1_c
),
3668 SH_PFC_PIN_GROUP(drif2_ctrl_a
),
3669 SH_PFC_PIN_GROUP(drif2_data0_a
),
3670 SH_PFC_PIN_GROUP(drif2_data1_a
),
3671 SH_PFC_PIN_GROUP(drif2_ctrl_b
),
3672 SH_PFC_PIN_GROUP(drif2_data0_b
),
3673 SH_PFC_PIN_GROUP(drif2_data1_b
),
3674 SH_PFC_PIN_GROUP(drif3_ctrl_a
),
3675 SH_PFC_PIN_GROUP(drif3_data0_a
),
3676 SH_PFC_PIN_GROUP(drif3_data1_a
),
3677 SH_PFC_PIN_GROUP(drif3_ctrl_b
),
3678 SH_PFC_PIN_GROUP(drif3_data0_b
),
3679 SH_PFC_PIN_GROUP(drif3_data1_b
),
3680 SH_PFC_PIN_GROUP(du_rgb666
),
3681 SH_PFC_PIN_GROUP(du_rgb888
),
3682 SH_PFC_PIN_GROUP(du_clk_out_0
),
3683 SH_PFC_PIN_GROUP(du_clk_out_1
),
3684 SH_PFC_PIN_GROUP(du_sync
),
3685 SH_PFC_PIN_GROUP(du_oddf
),
3686 SH_PFC_PIN_GROUP(du_cde
),
3687 SH_PFC_PIN_GROUP(du_disp
),
3688 SH_PFC_PIN_GROUP(hscif0_data
),
3689 SH_PFC_PIN_GROUP(hscif0_clk
),
3690 SH_PFC_PIN_GROUP(hscif0_ctrl
),
3691 SH_PFC_PIN_GROUP(hscif1_data_a
),
3692 SH_PFC_PIN_GROUP(hscif1_clk_a
),
3693 SH_PFC_PIN_GROUP(hscif1_ctrl_a
),
3694 SH_PFC_PIN_GROUP(hscif1_data_b
),
3695 SH_PFC_PIN_GROUP(hscif1_clk_b
),
3696 SH_PFC_PIN_GROUP(hscif1_ctrl_b
),
3697 SH_PFC_PIN_GROUP(hscif2_data_a
),
3698 SH_PFC_PIN_GROUP(hscif2_clk_a
),
3699 SH_PFC_PIN_GROUP(hscif2_ctrl_a
),
3700 SH_PFC_PIN_GROUP(hscif2_data_b
),
3701 SH_PFC_PIN_GROUP(hscif2_clk_b
),
3702 SH_PFC_PIN_GROUP(hscif2_ctrl_b
),
3703 SH_PFC_PIN_GROUP(hscif3_data_a
),
3704 SH_PFC_PIN_GROUP(hscif3_clk
),
3705 SH_PFC_PIN_GROUP(hscif3_ctrl
),
3706 SH_PFC_PIN_GROUP(hscif3_data_b
),
3707 SH_PFC_PIN_GROUP(hscif3_data_c
),
3708 SH_PFC_PIN_GROUP(hscif3_data_d
),
3709 SH_PFC_PIN_GROUP(hscif4_data_a
),
3710 SH_PFC_PIN_GROUP(hscif4_clk
),
3711 SH_PFC_PIN_GROUP(hscif4_ctrl
),
3712 SH_PFC_PIN_GROUP(hscif4_data_b
),
3713 SH_PFC_PIN_GROUP(i2c1_a
),
3714 SH_PFC_PIN_GROUP(i2c1_b
),
3715 SH_PFC_PIN_GROUP(i2c2_a
),
3716 SH_PFC_PIN_GROUP(i2c2_b
),
3717 SH_PFC_PIN_GROUP(i2c6_a
),
3718 SH_PFC_PIN_GROUP(i2c6_b
),
3719 SH_PFC_PIN_GROUP(i2c6_c
),
3720 SH_PFC_PIN_GROUP(intc_ex_irq0
),
3721 SH_PFC_PIN_GROUP(intc_ex_irq1
),
3722 SH_PFC_PIN_GROUP(intc_ex_irq2
),
3723 SH_PFC_PIN_GROUP(intc_ex_irq3
),
3724 SH_PFC_PIN_GROUP(intc_ex_irq4
),
3725 SH_PFC_PIN_GROUP(intc_ex_irq5
),
3726 SH_PFC_PIN_GROUP(msiof0_clk
),
3727 SH_PFC_PIN_GROUP(msiof0_sync
),
3728 SH_PFC_PIN_GROUP(msiof0_ss1
),
3729 SH_PFC_PIN_GROUP(msiof0_ss2
),
3730 SH_PFC_PIN_GROUP(msiof0_txd
),
3731 SH_PFC_PIN_GROUP(msiof0_rxd
),
3732 SH_PFC_PIN_GROUP(msiof1_clk_a
),
3733 SH_PFC_PIN_GROUP(msiof1_sync_a
),
3734 SH_PFC_PIN_GROUP(msiof1_ss1_a
),
3735 SH_PFC_PIN_GROUP(msiof1_ss2_a
),
3736 SH_PFC_PIN_GROUP(msiof1_txd_a
),
3737 SH_PFC_PIN_GROUP(msiof1_rxd_a
),
3738 SH_PFC_PIN_GROUP(msiof1_clk_b
),
3739 SH_PFC_PIN_GROUP(msiof1_sync_b
),
3740 SH_PFC_PIN_GROUP(msiof1_ss1_b
),
3741 SH_PFC_PIN_GROUP(msiof1_ss2_b
),
3742 SH_PFC_PIN_GROUP(msiof1_txd_b
),
3743 SH_PFC_PIN_GROUP(msiof1_rxd_b
),
3744 SH_PFC_PIN_GROUP(msiof1_clk_c
),
3745 SH_PFC_PIN_GROUP(msiof1_sync_c
),
3746 SH_PFC_PIN_GROUP(msiof1_ss1_c
),
3747 SH_PFC_PIN_GROUP(msiof1_ss2_c
),
3748 SH_PFC_PIN_GROUP(msiof1_txd_c
),
3749 SH_PFC_PIN_GROUP(msiof1_rxd_c
),
3750 SH_PFC_PIN_GROUP(msiof1_clk_d
),
3751 SH_PFC_PIN_GROUP(msiof1_sync_d
),
3752 SH_PFC_PIN_GROUP(msiof1_ss1_d
),
3753 SH_PFC_PIN_GROUP(msiof1_ss2_d
),
3754 SH_PFC_PIN_GROUP(msiof1_txd_d
),
3755 SH_PFC_PIN_GROUP(msiof1_rxd_d
),
3756 SH_PFC_PIN_GROUP(msiof1_clk_e
),
3757 SH_PFC_PIN_GROUP(msiof1_sync_e
),
3758 SH_PFC_PIN_GROUP(msiof1_ss1_e
),
3759 SH_PFC_PIN_GROUP(msiof1_ss2_e
),
3760 SH_PFC_PIN_GROUP(msiof1_txd_e
),
3761 SH_PFC_PIN_GROUP(msiof1_rxd_e
),
3762 SH_PFC_PIN_GROUP(msiof1_clk_f
),
3763 SH_PFC_PIN_GROUP(msiof1_sync_f
),
3764 SH_PFC_PIN_GROUP(msiof1_ss1_f
),
3765 SH_PFC_PIN_GROUP(msiof1_ss2_f
),
3766 SH_PFC_PIN_GROUP(msiof1_txd_f
),
3767 SH_PFC_PIN_GROUP(msiof1_rxd_f
),
3768 SH_PFC_PIN_GROUP(msiof1_clk_g
),
3769 SH_PFC_PIN_GROUP(msiof1_sync_g
),
3770 SH_PFC_PIN_GROUP(msiof1_ss1_g
),
3771 SH_PFC_PIN_GROUP(msiof1_ss2_g
),
3772 SH_PFC_PIN_GROUP(msiof1_txd_g
),
3773 SH_PFC_PIN_GROUP(msiof1_rxd_g
),
3774 SH_PFC_PIN_GROUP(msiof2_clk_a
),
3775 SH_PFC_PIN_GROUP(msiof2_sync_a
),
3776 SH_PFC_PIN_GROUP(msiof2_ss1_a
),
3777 SH_PFC_PIN_GROUP(msiof2_ss2_a
),
3778 SH_PFC_PIN_GROUP(msiof2_txd_a
),
3779 SH_PFC_PIN_GROUP(msiof2_rxd_a
),
3780 SH_PFC_PIN_GROUP(msiof2_clk_b
),
3781 SH_PFC_PIN_GROUP(msiof2_sync_b
),
3782 SH_PFC_PIN_GROUP(msiof2_ss1_b
),
3783 SH_PFC_PIN_GROUP(msiof2_ss2_b
),
3784 SH_PFC_PIN_GROUP(msiof2_txd_b
),
3785 SH_PFC_PIN_GROUP(msiof2_rxd_b
),
3786 SH_PFC_PIN_GROUP(msiof2_clk_c
),
3787 SH_PFC_PIN_GROUP(msiof2_sync_c
),
3788 SH_PFC_PIN_GROUP(msiof2_ss1_c
),
3789 SH_PFC_PIN_GROUP(msiof2_ss2_c
),
3790 SH_PFC_PIN_GROUP(msiof2_txd_c
),
3791 SH_PFC_PIN_GROUP(msiof2_rxd_c
),
3792 SH_PFC_PIN_GROUP(msiof2_clk_d
),
3793 SH_PFC_PIN_GROUP(msiof2_sync_d
),
3794 SH_PFC_PIN_GROUP(msiof2_ss1_d
),
3795 SH_PFC_PIN_GROUP(msiof2_ss2_d
),
3796 SH_PFC_PIN_GROUP(msiof2_txd_d
),
3797 SH_PFC_PIN_GROUP(msiof2_rxd_d
),
3798 SH_PFC_PIN_GROUP(msiof3_clk_a
),
3799 SH_PFC_PIN_GROUP(msiof3_sync_a
),
3800 SH_PFC_PIN_GROUP(msiof3_ss1_a
),
3801 SH_PFC_PIN_GROUP(msiof3_ss2_a
),
3802 SH_PFC_PIN_GROUP(msiof3_txd_a
),
3803 SH_PFC_PIN_GROUP(msiof3_rxd_a
),
3804 SH_PFC_PIN_GROUP(msiof3_clk_b
),
3805 SH_PFC_PIN_GROUP(msiof3_sync_b
),
3806 SH_PFC_PIN_GROUP(msiof3_ss1_b
),
3807 SH_PFC_PIN_GROUP(msiof3_ss2_b
),
3808 SH_PFC_PIN_GROUP(msiof3_txd_b
),
3809 SH_PFC_PIN_GROUP(msiof3_rxd_b
),
3810 SH_PFC_PIN_GROUP(msiof3_clk_c
),
3811 SH_PFC_PIN_GROUP(msiof3_sync_c
),
3812 SH_PFC_PIN_GROUP(msiof3_txd_c
),
3813 SH_PFC_PIN_GROUP(msiof3_rxd_c
),
3814 SH_PFC_PIN_GROUP(msiof3_clk_d
),
3815 SH_PFC_PIN_GROUP(msiof3_sync_d
),
3816 SH_PFC_PIN_GROUP(msiof3_ss1_d
),
3817 SH_PFC_PIN_GROUP(msiof3_txd_d
),
3818 SH_PFC_PIN_GROUP(msiof3_rxd_d
),
3819 SH_PFC_PIN_GROUP(pwm0
),
3820 SH_PFC_PIN_GROUP(pwm1_a
),
3821 SH_PFC_PIN_GROUP(pwm1_b
),
3822 SH_PFC_PIN_GROUP(pwm2_a
),
3823 SH_PFC_PIN_GROUP(pwm2_b
),
3824 SH_PFC_PIN_GROUP(pwm3_a
),
3825 SH_PFC_PIN_GROUP(pwm3_b
),
3826 SH_PFC_PIN_GROUP(pwm4_a
),
3827 SH_PFC_PIN_GROUP(pwm4_b
),
3828 SH_PFC_PIN_GROUP(pwm5_a
),
3829 SH_PFC_PIN_GROUP(pwm5_b
),
3830 SH_PFC_PIN_GROUP(pwm6_a
),
3831 SH_PFC_PIN_GROUP(pwm6_b
),
3832 SH_PFC_PIN_GROUP(sata0_devslp_a
),
3833 SH_PFC_PIN_GROUP(sata0_devslp_b
),
3834 SH_PFC_PIN_GROUP(scif0_data
),
3835 SH_PFC_PIN_GROUP(scif0_clk
),
3836 SH_PFC_PIN_GROUP(scif0_ctrl
),
3837 SH_PFC_PIN_GROUP(scif1_data_a
),
3838 SH_PFC_PIN_GROUP(scif1_clk
),
3839 SH_PFC_PIN_GROUP(scif1_ctrl
),
3840 SH_PFC_PIN_GROUP(scif1_data_b
),
3841 SH_PFC_PIN_GROUP(scif2_data_a
),
3842 SH_PFC_PIN_GROUP(scif2_clk
),
3843 SH_PFC_PIN_GROUP(scif2_data_b
),
3844 SH_PFC_PIN_GROUP(scif3_data_a
),
3845 SH_PFC_PIN_GROUP(scif3_clk
),
3846 SH_PFC_PIN_GROUP(scif3_ctrl
),
3847 SH_PFC_PIN_GROUP(scif3_data_b
),
3848 SH_PFC_PIN_GROUP(scif4_data_a
),
3849 SH_PFC_PIN_GROUP(scif4_clk_a
),
3850 SH_PFC_PIN_GROUP(scif4_ctrl_a
),
3851 SH_PFC_PIN_GROUP(scif4_data_b
),
3852 SH_PFC_PIN_GROUP(scif4_clk_b
),
3853 SH_PFC_PIN_GROUP(scif4_ctrl_b
),
3854 SH_PFC_PIN_GROUP(scif4_data_c
),
3855 SH_PFC_PIN_GROUP(scif4_clk_c
),
3856 SH_PFC_PIN_GROUP(scif4_ctrl_c
),
3857 SH_PFC_PIN_GROUP(scif5_data
),
3858 SH_PFC_PIN_GROUP(scif5_clk
),
3859 SH_PFC_PIN_GROUP(scif_clk_a
),
3860 SH_PFC_PIN_GROUP(scif_clk_b
),
3861 SH_PFC_PIN_GROUP(sdhi0_data1
),
3862 SH_PFC_PIN_GROUP(sdhi0_data4
),
3863 SH_PFC_PIN_GROUP(sdhi0_ctrl
),
3864 SH_PFC_PIN_GROUP(sdhi0_cd
),
3865 SH_PFC_PIN_GROUP(sdhi0_wp
),
3866 SH_PFC_PIN_GROUP(sdhi1_data1
),
3867 SH_PFC_PIN_GROUP(sdhi1_data4
),
3868 SH_PFC_PIN_GROUP(sdhi1_ctrl
),
3869 SH_PFC_PIN_GROUP(sdhi1_cd
),
3870 SH_PFC_PIN_GROUP(sdhi1_wp
),
3871 SH_PFC_PIN_GROUP(sdhi2_data1
),
3872 SH_PFC_PIN_GROUP(sdhi2_data4
),
3873 SH_PFC_PIN_GROUP(sdhi2_data8
),
3874 SH_PFC_PIN_GROUP(sdhi2_ctrl
),
3875 SH_PFC_PIN_GROUP(sdhi2_cd_a
),
3876 SH_PFC_PIN_GROUP(sdhi2_wp_a
),
3877 SH_PFC_PIN_GROUP(sdhi2_cd_b
),
3878 SH_PFC_PIN_GROUP(sdhi2_wp_b
),
3879 SH_PFC_PIN_GROUP(sdhi2_ds
),
3880 SH_PFC_PIN_GROUP(sdhi3_data1
),
3881 SH_PFC_PIN_GROUP(sdhi3_data4
),
3882 SH_PFC_PIN_GROUP(sdhi3_data8
),
3883 SH_PFC_PIN_GROUP(sdhi3_ctrl
),
3884 SH_PFC_PIN_GROUP(sdhi3_cd
),
3885 SH_PFC_PIN_GROUP(sdhi3_wp
),
3886 SH_PFC_PIN_GROUP(sdhi3_ds
),
3887 SH_PFC_PIN_GROUP(ssi0_data
),
3888 SH_PFC_PIN_GROUP(ssi01239_ctrl
),
3889 SH_PFC_PIN_GROUP(ssi1_data_a
),
3890 SH_PFC_PIN_GROUP(ssi1_data_b
),
3891 SH_PFC_PIN_GROUP(ssi1_ctrl_a
),
3892 SH_PFC_PIN_GROUP(ssi1_ctrl_b
),
3893 SH_PFC_PIN_GROUP(ssi2_data_a
),
3894 SH_PFC_PIN_GROUP(ssi2_data_b
),
3895 SH_PFC_PIN_GROUP(ssi2_ctrl_a
),
3896 SH_PFC_PIN_GROUP(ssi2_ctrl_b
),
3897 SH_PFC_PIN_GROUP(ssi3_data
),
3898 SH_PFC_PIN_GROUP(ssi34_ctrl
),
3899 SH_PFC_PIN_GROUP(ssi4_data
),
3900 SH_PFC_PIN_GROUP(ssi4_ctrl
),
3901 SH_PFC_PIN_GROUP(ssi5_data
),
3902 SH_PFC_PIN_GROUP(ssi5_ctrl
),
3903 SH_PFC_PIN_GROUP(ssi6_data
),
3904 SH_PFC_PIN_GROUP(ssi6_ctrl
),
3905 SH_PFC_PIN_GROUP(ssi7_data
),
3906 SH_PFC_PIN_GROUP(ssi78_ctrl
),
3907 SH_PFC_PIN_GROUP(ssi8_data
),
3908 SH_PFC_PIN_GROUP(ssi9_data_a
),
3909 SH_PFC_PIN_GROUP(ssi9_data_b
),
3910 SH_PFC_PIN_GROUP(ssi9_ctrl_a
),
3911 SH_PFC_PIN_GROUP(ssi9_ctrl_b
),
3912 SH_PFC_PIN_GROUP(usb0
),
3913 SH_PFC_PIN_GROUP(usb1
),
3914 SH_PFC_PIN_GROUP(usb2
),
3917 static const char * const audio_clk_groups
[] = {
3937 static const char * const avb_groups
[] = {
3944 "avb_avtp_capture_a",
3946 "avb_avtp_capture_b",
3949 static const char * const can0_groups
[] = {
3954 static const char * const can1_groups
[] = {
3958 static const char * const can_clk_groups
[] = {
3962 static const char * const canfd0_groups
[] = {
3967 static const char * const canfd1_groups
[] = {
3971 static const char * const drif0_groups
[] = {
3983 static const char * const drif1_groups
[] = {
3995 static const char * const drif2_groups
[] = {
4004 static const char * const drif3_groups
[] = {
4013 static const char * const du_groups
[] = {
4024 static const char * const hscif0_groups
[] = {
4030 static const char * const hscif1_groups
[] = {
4039 static const char * const hscif2_groups
[] = {
4048 static const char * const hscif3_groups
[] = {
4057 static const char * const hscif4_groups
[] = {
4064 static const char * const i2c1_groups
[] = {
4069 static const char * const i2c2_groups
[] = {
4074 static const char * const i2c6_groups
[] = {
4080 static const char * const intc_ex_groups
[] = {
4089 static const char * const msiof0_groups
[] = {
4098 static const char * const msiof1_groups
[] = {
4143 static const char * const msiof2_groups
[] = {
4170 static const char * const msiof3_groups
[] = {
4194 static const char * const pwm0_groups
[] = {
4198 static const char * const pwm1_groups
[] = {
4203 static const char * const pwm2_groups
[] = {
4208 static const char * const pwm3_groups
[] = {
4213 static const char * const pwm4_groups
[] = {
4218 static const char * const pwm5_groups
[] = {
4223 static const char * const pwm6_groups
[] = {
4228 static const char * const sata0_groups
[] = {
4233 static const char * const scif0_groups
[] = {
4239 static const char * const scif1_groups
[] = {
4246 static const char * const scif2_groups
[] = {
4252 static const char * const scif3_groups
[] = {
4259 static const char * const scif4_groups
[] = {
4271 static const char * const scif5_groups
[] = {
4276 static const char * const scif_clk_groups
[] = {
4281 static const char * const sdhi0_groups
[] = {
4289 static const char * const sdhi1_groups
[] = {
4297 static const char * const sdhi2_groups
[] = {
4309 static const char * const sdhi3_groups
[] = {
4319 static const char * const ssi_groups
[] = {
4347 static const char * const usb0_groups
[] = {
4351 static const char * const usb1_groups
[] = {
4355 static const char * const usb2_groups
[] = {
4359 static const struct sh_pfc_function pinmux_functions
[] = {
4360 SH_PFC_FUNCTION(audio_clk
),
4361 SH_PFC_FUNCTION(avb
),
4362 SH_PFC_FUNCTION(can0
),
4363 SH_PFC_FUNCTION(can1
),
4364 SH_PFC_FUNCTION(can_clk
),
4365 SH_PFC_FUNCTION(canfd0
),
4366 SH_PFC_FUNCTION(canfd1
),
4367 SH_PFC_FUNCTION(drif0
),
4368 SH_PFC_FUNCTION(drif1
),
4369 SH_PFC_FUNCTION(drif2
),
4370 SH_PFC_FUNCTION(drif3
),
4371 SH_PFC_FUNCTION(du
),
4372 SH_PFC_FUNCTION(hscif0
),
4373 SH_PFC_FUNCTION(hscif1
),
4374 SH_PFC_FUNCTION(hscif2
),
4375 SH_PFC_FUNCTION(hscif3
),
4376 SH_PFC_FUNCTION(hscif4
),
4377 SH_PFC_FUNCTION(i2c1
),
4378 SH_PFC_FUNCTION(i2c2
),
4379 SH_PFC_FUNCTION(i2c6
),
4380 SH_PFC_FUNCTION(intc_ex
),
4381 SH_PFC_FUNCTION(msiof0
),
4382 SH_PFC_FUNCTION(msiof1
),
4383 SH_PFC_FUNCTION(msiof2
),
4384 SH_PFC_FUNCTION(msiof3
),
4385 SH_PFC_FUNCTION(pwm0
),
4386 SH_PFC_FUNCTION(pwm1
),
4387 SH_PFC_FUNCTION(pwm2
),
4388 SH_PFC_FUNCTION(pwm3
),
4389 SH_PFC_FUNCTION(pwm4
),
4390 SH_PFC_FUNCTION(pwm5
),
4391 SH_PFC_FUNCTION(pwm6
),
4392 SH_PFC_FUNCTION(sata0
),
4393 SH_PFC_FUNCTION(scif0
),
4394 SH_PFC_FUNCTION(scif1
),
4395 SH_PFC_FUNCTION(scif2
),
4396 SH_PFC_FUNCTION(scif3
),
4397 SH_PFC_FUNCTION(scif4
),
4398 SH_PFC_FUNCTION(scif5
),
4399 SH_PFC_FUNCTION(scif_clk
),
4400 SH_PFC_FUNCTION(sdhi0
),
4401 SH_PFC_FUNCTION(sdhi1
),
4402 SH_PFC_FUNCTION(sdhi2
),
4403 SH_PFC_FUNCTION(sdhi3
),
4404 SH_PFC_FUNCTION(ssi
),
4405 SH_PFC_FUNCTION(usb0
),
4406 SH_PFC_FUNCTION(usb1
),
4407 SH_PFC_FUNCTION(usb2
),
4410 static const struct pinmux_cfg_reg pinmux_config_regs
[] = {
4411 #define F_(x, y) FN_##y
4412 #define FM(x) FN_##x
4413 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4430 GP_0_15_FN
, GPSR0_15
,
4431 GP_0_14_FN
, GPSR0_14
,
4432 GP_0_13_FN
, GPSR0_13
,
4433 GP_0_12_FN
, GPSR0_12
,
4434 GP_0_11_FN
, GPSR0_11
,
4435 GP_0_10_FN
, GPSR0_10
,
4445 GP_0_0_FN
, GPSR0_0
, }
4447 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4452 GP_1_27_FN
, GPSR1_27
,
4453 GP_1_26_FN
, GPSR1_26
,
4454 GP_1_25_FN
, GPSR1_25
,
4455 GP_1_24_FN
, GPSR1_24
,
4456 GP_1_23_FN
, GPSR1_23
,
4457 GP_1_22_FN
, GPSR1_22
,
4458 GP_1_21_FN
, GPSR1_21
,
4459 GP_1_20_FN
, GPSR1_20
,
4460 GP_1_19_FN
, GPSR1_19
,
4461 GP_1_18_FN
, GPSR1_18
,
4462 GP_1_17_FN
, GPSR1_17
,
4463 GP_1_16_FN
, GPSR1_16
,
4464 GP_1_15_FN
, GPSR1_15
,
4465 GP_1_14_FN
, GPSR1_14
,
4466 GP_1_13_FN
, GPSR1_13
,
4467 GP_1_12_FN
, GPSR1_12
,
4468 GP_1_11_FN
, GPSR1_11
,
4469 GP_1_10_FN
, GPSR1_10
,
4479 GP_1_0_FN
, GPSR1_0
, }
4481 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4499 GP_2_14_FN
, GPSR2_14
,
4500 GP_2_13_FN
, GPSR2_13
,
4501 GP_2_12_FN
, GPSR2_12
,
4502 GP_2_11_FN
, GPSR2_11
,
4503 GP_2_10_FN
, GPSR2_10
,
4513 GP_2_0_FN
, GPSR2_0
, }
4515 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4532 GP_3_15_FN
, GPSR3_15
,
4533 GP_3_14_FN
, GPSR3_14
,
4534 GP_3_13_FN
, GPSR3_13
,
4535 GP_3_12_FN
, GPSR3_12
,
4536 GP_3_11_FN
, GPSR3_11
,
4537 GP_3_10_FN
, GPSR3_10
,
4547 GP_3_0_FN
, GPSR3_0
, }
4549 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4564 GP_4_17_FN
, GPSR4_17
,
4565 GP_4_16_FN
, GPSR4_16
,
4566 GP_4_15_FN
, GPSR4_15
,
4567 GP_4_14_FN
, GPSR4_14
,
4568 GP_4_13_FN
, GPSR4_13
,
4569 GP_4_12_FN
, GPSR4_12
,
4570 GP_4_11_FN
, GPSR4_11
,
4571 GP_4_10_FN
, GPSR4_10
,
4581 GP_4_0_FN
, GPSR4_0
, }
4583 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4590 GP_5_25_FN
, GPSR5_25
,
4591 GP_5_24_FN
, GPSR5_24
,
4592 GP_5_23_FN
, GPSR5_23
,
4593 GP_5_22_FN
, GPSR5_22
,
4594 GP_5_21_FN
, GPSR5_21
,
4595 GP_5_20_FN
, GPSR5_20
,
4596 GP_5_19_FN
, GPSR5_19
,
4597 GP_5_18_FN
, GPSR5_18
,
4598 GP_5_17_FN
, GPSR5_17
,
4599 GP_5_16_FN
, GPSR5_16
,
4600 GP_5_15_FN
, GPSR5_15
,
4601 GP_5_14_FN
, GPSR5_14
,
4602 GP_5_13_FN
, GPSR5_13
,
4603 GP_5_12_FN
, GPSR5_12
,
4604 GP_5_11_FN
, GPSR5_11
,
4605 GP_5_10_FN
, GPSR5_10
,
4615 GP_5_0_FN
, GPSR5_0
, }
4617 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4618 GP_6_31_FN
, GPSR6_31
,
4619 GP_6_30_FN
, GPSR6_30
,
4620 GP_6_29_FN
, GPSR6_29
,
4621 GP_6_28_FN
, GPSR6_28
,
4622 GP_6_27_FN
, GPSR6_27
,
4623 GP_6_26_FN
, GPSR6_26
,
4624 GP_6_25_FN
, GPSR6_25
,
4625 GP_6_24_FN
, GPSR6_24
,
4626 GP_6_23_FN
, GPSR6_23
,
4627 GP_6_22_FN
, GPSR6_22
,
4628 GP_6_21_FN
, GPSR6_21
,
4629 GP_6_20_FN
, GPSR6_20
,
4630 GP_6_19_FN
, GPSR6_19
,
4631 GP_6_18_FN
, GPSR6_18
,
4632 GP_6_17_FN
, GPSR6_17
,
4633 GP_6_16_FN
, GPSR6_16
,
4634 GP_6_15_FN
, GPSR6_15
,
4635 GP_6_14_FN
, GPSR6_14
,
4636 GP_6_13_FN
, GPSR6_13
,
4637 GP_6_12_FN
, GPSR6_12
,
4638 GP_6_11_FN
, GPSR6_11
,
4639 GP_6_10_FN
, GPSR6_10
,
4649 GP_6_0_FN
, GPSR6_0
, }
4651 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4683 GP_7_0_FN
, GPSR7_0
, }
4689 #define FM(x) FN_##x,
4690 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4700 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4710 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4720 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4730 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4740 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4750 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4760 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4770 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4780 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4790 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
4800 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
4810 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
4820 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
4830 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
4840 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
4850 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
4860 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
4861 /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4862 /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4863 /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4864 /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4865 /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4866 /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4874 #define FM(x) FN_##x,
4875 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4876 1, 2, 2, 3, 1, 1, 2, 1, 1, 1,
4877 2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) {
4878 0, 0, /* RESERVED 31 */
4900 0, 0, /* RESERVED 0 */ }
4902 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4903 2, 3, 1, 2, 3, 1, 1, 2, 1,
4904 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
4920 0, 0, 0, 0, /* RESERVED 8, 7 */
4929 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
4930 1, 1, 1, 1, 4, 4, 4,
4937 /* RESERVED 27, 26, 25, 24 */
4938 0, 0, 0, 0, 0, 0, 0, 0,
4939 0, 0, 0, 0, 0, 0, 0, 0,
4940 /* RESERVED 23, 22, 21, 20 */
4941 0, 0, 0, 0, 0, 0, 0, 0,
4942 0, 0, 0, 0, 0, 0, 0, 0,
4943 /* RESERVED 19, 18, 17, 16 */
4944 0, 0, 0, 0, 0, 0, 0, 0,
4945 0, 0, 0, 0, 0, 0, 0, 0,
4946 /* RESERVED 15, 14, 13, 12 */
4947 0, 0, 0, 0, 0, 0, 0, 0,
4948 0, 0, 0, 0, 0, 0, 0, 0,
4949 /* RESERVED 11, 10, 9, 8 */
4950 0, 0, 0, 0, 0, 0, 0, 0,
4951 0, 0, 0, 0, 0, 0, 0, 0,
4952 /* RESERVED 7, 6, 5, 4 */
4953 0, 0, 0, 0, 0, 0, 0, 0,
4954 0, 0, 0, 0, 0, 0, 0, 0,
4964 static const struct pinmux_drive_reg pinmux_drive_regs
[] = {
4965 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
4966 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
4967 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
4968 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
4970 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
4971 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
4972 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
4973 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
4974 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
4975 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
4976 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
4977 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
4978 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
4980 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
4981 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
4982 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
4983 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
4984 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
4985 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
4986 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
4987 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
4988 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
4990 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
4991 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
4992 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
4993 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
4994 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
4995 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
4996 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
4997 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
4998 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5000 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5001 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5002 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5003 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5004 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5005 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5006 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5007 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5008 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5010 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5011 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5012 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5013 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5014 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5015 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5016 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5017 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5019 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5020 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5021 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5022 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5023 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5024 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5025 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5026 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5028 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5029 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5030 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5031 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5032 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5033 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5034 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5035 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5036 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5038 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5039 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5040 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5041 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5042 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5043 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
5044 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
5046 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5047 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5048 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5049 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5050 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5051 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5052 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5054 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5055 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5056 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5057 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5058 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5059 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5060 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5061 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5062 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5064 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5065 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5066 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5067 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5068 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5069 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5070 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5071 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5072 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5074 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5075 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5076 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5077 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5078 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5079 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5080 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5081 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5082 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5084 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5085 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5086 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5087 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5088 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5089 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5090 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5091 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5092 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5094 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5095 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
5096 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5097 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5098 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5099 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
5100 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5101 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5102 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5104 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5105 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5106 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5107 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5108 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5109 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5110 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5111 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5112 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5114 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5115 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5116 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5117 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5118 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5119 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5120 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5121 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5123 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5124 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5125 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5126 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5127 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5128 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK34 */
5129 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS34 */
5130 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5131 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5133 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5134 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5135 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5136 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5137 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5138 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5139 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5140 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5141 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5143 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5144 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5145 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5146 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5147 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5148 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5149 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5150 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5151 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5153 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5154 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5155 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5156 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5157 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5158 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5159 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB31_PWEN */
5160 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB31_OVC */
5165 static int r8a7795_pin_to_pocctrl(struct sh_pfc
*pfc
, unsigned int pin
, u32
*pocctrl
)
5169 *pocctrl
= 0xe6060380;
5171 if (pin
>= RCAR_GP_PIN(3, 0) && pin
<= RCAR_GP_PIN(3, 11))
5174 if (pin
>= RCAR_GP_PIN(4, 0) && pin
<= RCAR_GP_PIN(4, 17))
5175 bit
= (pin
& 0x1f) + 12;
5180 #define PUEN 0xe6060400
5181 #define PUD 0xe6060440
5191 static const struct {
5195 [RCAR_GP_PIN(2, 11)] = { PU0
, 31 }, /* AVB_PHY_INT */
5196 [RCAR_GP_PIN(2, 10)] = { PU0
, 30 }, /* AVB_MAGIC */
5197 [RCAR_GP_PIN(2, 9)] = { PU0
, 29 }, /* AVB_MDC */
5199 [RCAR_GP_PIN(1, 19)] = { PU1
, 31 }, /* A19 */
5200 [RCAR_GP_PIN(1, 18)] = { PU1
, 30 }, /* A18 */
5201 [RCAR_GP_PIN(1, 17)] = { PU1
, 29 }, /* A17 */
5202 [RCAR_GP_PIN(1, 16)] = { PU1
, 28 }, /* A16 */
5203 [RCAR_GP_PIN(1, 15)] = { PU1
, 27 }, /* A15 */
5204 [RCAR_GP_PIN(1, 14)] = { PU1
, 26 }, /* A14 */
5205 [RCAR_GP_PIN(1, 13)] = { PU1
, 25 }, /* A13 */
5206 [RCAR_GP_PIN(1, 12)] = { PU1
, 24 }, /* A12 */
5207 [RCAR_GP_PIN(1, 11)] = { PU1
, 23 }, /* A11 */
5208 [RCAR_GP_PIN(1, 10)] = { PU1
, 22 }, /* A10 */
5209 [RCAR_GP_PIN(1, 9)] = { PU1
, 21 }, /* A9 */
5210 [RCAR_GP_PIN(1, 8)] = { PU1
, 20 }, /* A8 */
5211 [RCAR_GP_PIN(1, 7)] = { PU1
, 19 }, /* A7 */
5212 [RCAR_GP_PIN(1, 6)] = { PU1
, 18 }, /* A6 */
5213 [RCAR_GP_PIN(1, 5)] = { PU1
, 17 }, /* A5 */
5214 [RCAR_GP_PIN(1, 4)] = { PU1
, 16 }, /* A4 */
5215 [RCAR_GP_PIN(1, 3)] = { PU1
, 15 }, /* A3 */
5216 [RCAR_GP_PIN(1, 2)] = { PU1
, 14 }, /* A2 */
5217 [RCAR_GP_PIN(1, 1)] = { PU1
, 13 }, /* A1 */
5218 [RCAR_GP_PIN(1, 0)] = { PU1
, 12 }, /* A0 */
5219 [RCAR_GP_PIN(2, 8)] = { PU1
, 11 }, /* PWM2_A */
5220 [RCAR_GP_PIN(2, 7)] = { PU1
, 10 }, /* PWM1_A */
5221 [RCAR_GP_PIN(2, 6)] = { PU1
, 9 }, /* PWM0 */
5222 [RCAR_GP_PIN(2, 5)] = { PU1
, 8 }, /* IRQ5 */
5223 [RCAR_GP_PIN(2, 4)] = { PU1
, 7 }, /* IRQ4 */
5224 [RCAR_GP_PIN(2, 3)] = { PU1
, 6 }, /* IRQ3 */
5225 [RCAR_GP_PIN(2, 2)] = { PU1
, 5 }, /* IRQ2 */
5226 [RCAR_GP_PIN(2, 1)] = { PU1
, 4 }, /* IRQ1 */
5227 [RCAR_GP_PIN(2, 0)] = { PU1
, 3 }, /* IRQ0 */
5228 [RCAR_GP_PIN(2, 14)] = { PU1
, 2 }, /* AVB_AVTP_CAPTURE_A */
5229 [RCAR_GP_PIN(2, 13)] = { PU1
, 1 }, /* AVB_AVTP_MATCH_A */
5230 [RCAR_GP_PIN(2, 12)] = { PU1
, 0 }, /* AVB_LINK */
5232 [RCAR_GP_PIN(7, 3)] = { PU2
, 29 }, /* HDMI1_CEC */
5233 [RCAR_GP_PIN(7, 2)] = { PU2
, 28 }, /* HDMI0_CEC */
5234 [RCAR_GP_PIN(7, 1)] = { PU2
, 27 }, /* AVS2 */
5235 [RCAR_GP_PIN(7, 0)] = { PU2
, 26 }, /* AVS1 */
5236 [RCAR_GP_PIN(0, 15)] = { PU2
, 25 }, /* D15 */
5237 [RCAR_GP_PIN(0, 14)] = { PU2
, 24 }, /* D14 */
5238 [RCAR_GP_PIN(0, 13)] = { PU2
, 23 }, /* D13 */
5239 [RCAR_GP_PIN(0, 12)] = { PU2
, 22 }, /* D12 */
5240 [RCAR_GP_PIN(0, 11)] = { PU2
, 21 }, /* D11 */
5241 [RCAR_GP_PIN(0, 10)] = { PU2
, 20 }, /* D10 */
5242 [RCAR_GP_PIN(0, 9)] = { PU2
, 19 }, /* D9 */
5243 [RCAR_GP_PIN(0, 8)] = { PU2
, 18 }, /* D8 */
5244 [RCAR_GP_PIN(0, 7)] = { PU2
, 17 }, /* D7 */
5245 [RCAR_GP_PIN(0, 6)] = { PU2
, 16 }, /* D6 */
5246 [RCAR_GP_PIN(0, 5)] = { PU2
, 15 }, /* D5 */
5247 [RCAR_GP_PIN(0, 4)] = { PU2
, 14 }, /* D4 */
5248 [RCAR_GP_PIN(0, 3)] = { PU2
, 13 }, /* D3 */
5249 [RCAR_GP_PIN(0, 2)] = { PU2
, 12 }, /* D2 */
5250 [RCAR_GP_PIN(0, 1)] = { PU2
, 11 }, /* D1 */
5251 [RCAR_GP_PIN(0, 0)] = { PU2
, 10 }, /* D0 */
5252 [RCAR_GP_PIN(1, 27)] = { PU2
, 8 }, /* EX_WAIT0_A */
5253 [RCAR_GP_PIN(1, 26)] = { PU2
, 7 }, /* WE1_N */
5254 [RCAR_GP_PIN(1, 25)] = { PU2
, 6 }, /* WE0_N */
5255 [RCAR_GP_PIN(1, 24)] = { PU2
, 5 }, /* RD_WR_N */
5256 [RCAR_GP_PIN(1, 23)] = { PU2
, 4 }, /* RD_N */
5257 [RCAR_GP_PIN(1, 22)] = { PU2
, 3 }, /* BS_N */
5258 [RCAR_GP_PIN(1, 21)] = { PU2
, 2 }, /* CS1_N_A26 */
5259 [RCAR_GP_PIN(1, 20)] = { PU2
, 1 }, /* CS0_N */
5261 [RCAR_GP_PIN(4, 9)] = { PU3
, 31 }, /* SD3_DAT0 */
5262 [RCAR_GP_PIN(4, 8)] = { PU3
, 30 }, /* SD3_CMD */
5263 [RCAR_GP_PIN(4, 7)] = { PU3
, 29 }, /* SD3_CLK */
5264 [RCAR_GP_PIN(4, 6)] = { PU3
, 28 }, /* SD2_DS */
5265 [RCAR_GP_PIN(4, 5)] = { PU3
, 27 }, /* SD2_DAT3 */
5266 [RCAR_GP_PIN(4, 4)] = { PU3
, 26 }, /* SD2_DAT2 */
5267 [RCAR_GP_PIN(4, 3)] = { PU3
, 25 }, /* SD2_DAT1 */
5268 [RCAR_GP_PIN(4, 2)] = { PU3
, 24 }, /* SD2_DAT0 */
5269 [RCAR_GP_PIN(4, 1)] = { PU3
, 23 }, /* SD2_CMD */
5270 [RCAR_GP_PIN(4, 0)] = { PU3
, 22 }, /* SD2_CLK */
5271 [RCAR_GP_PIN(3, 11)] = { PU3
, 21 }, /* SD1_DAT3 */
5272 [RCAR_GP_PIN(3, 10)] = { PU3
, 20 }, /* SD1_DAT2 */
5273 [RCAR_GP_PIN(3, 9)] = { PU3
, 19 }, /* SD1_DAT1 */
5274 [RCAR_GP_PIN(3, 8)] = { PU3
, 18 }, /* SD1_DAT0 */
5275 [RCAR_GP_PIN(3, 7)] = { PU3
, 17 }, /* SD1_CMD */
5276 [RCAR_GP_PIN(3, 6)] = { PU3
, 16 }, /* SD1_CLK */
5277 [RCAR_GP_PIN(3, 5)] = { PU3
, 15 }, /* SD0_DAT3 */
5278 [RCAR_GP_PIN(3, 4)] = { PU3
, 14 }, /* SD0_DAT2 */
5279 [RCAR_GP_PIN(3, 3)] = { PU3
, 13 }, /* SD0_DAT1 */
5280 [RCAR_GP_PIN(3, 2)] = { PU3
, 12 }, /* SD0_DAT0 */
5281 [RCAR_GP_PIN(3, 1)] = { PU3
, 11 }, /* SD0_CMD */
5282 [RCAR_GP_PIN(3, 0)] = { PU3
, 10 }, /* SD0_CLK */
5284 [RCAR_GP_PIN(5, 19)] = { PU4
, 31 }, /* MSIOF0_SS1 */
5285 [RCAR_GP_PIN(5, 18)] = { PU4
, 30 }, /* MSIOF0_SYNC */
5286 [RCAR_GP_PIN(5, 17)] = { PU4
, 29 }, /* MSIOF0_SCK */
5287 [RCAR_GP_PIN(5, 16)] = { PU4
, 28 }, /* HRTS0_N */
5288 [RCAR_GP_PIN(5, 15)] = { PU4
, 27 }, /* HCTS0_N */
5289 [RCAR_GP_PIN(5, 14)] = { PU4
, 26 }, /* HTX0 */
5290 [RCAR_GP_PIN(5, 13)] = { PU4
, 25 }, /* HRX0 */
5291 [RCAR_GP_PIN(5, 12)] = { PU4
, 24 }, /* HSCK0 */
5292 [RCAR_GP_PIN(5, 11)] = { PU4
, 23 }, /* RX2_A */
5293 [RCAR_GP_PIN(5, 10)] = { PU4
, 22 }, /* TX2_A */
5294 [RCAR_GP_PIN(5, 9)] = { PU4
, 21 }, /* SCK2 */
5295 [RCAR_GP_PIN(5, 8)] = { PU4
, 20 }, /* RTS1_N_TANS */
5296 [RCAR_GP_PIN(5, 7)] = { PU4
, 19 }, /* CTS1_N */
5297 [RCAR_GP_PIN(5, 6)] = { PU4
, 18 }, /* TX1_A */
5298 [RCAR_GP_PIN(5, 5)] = { PU4
, 17 }, /* RX1_A */
5299 [RCAR_GP_PIN(5, 4)] = { PU4
, 16 }, /* RTS0_N_TANS */
5300 [RCAR_GP_PIN(5, 3)] = { PU4
, 15 }, /* CTS0_N */
5301 [RCAR_GP_PIN(5, 2)] = { PU4
, 14 }, /* TX0 */
5302 [RCAR_GP_PIN(5, 1)] = { PU4
, 13 }, /* RX0 */
5303 [RCAR_GP_PIN(5, 0)] = { PU4
, 12 }, /* SCK0 */
5304 [RCAR_GP_PIN(3, 15)] = { PU4
, 11 }, /* SD1_WP */
5305 [RCAR_GP_PIN(3, 14)] = { PU4
, 10 }, /* SD1_CD */
5306 [RCAR_GP_PIN(3, 13)] = { PU4
, 9 }, /* SD0_WP */
5307 [RCAR_GP_PIN(3, 12)] = { PU4
, 8 }, /* SD0_CD */
5308 [RCAR_GP_PIN(4, 17)] = { PU4
, 7 }, /* SD3_DS */
5309 [RCAR_GP_PIN(4, 16)] = { PU4
, 6 }, /* SD3_DAT7 */
5310 [RCAR_GP_PIN(4, 15)] = { PU4
, 5 }, /* SD3_DAT6 */
5311 [RCAR_GP_PIN(4, 14)] = { PU4
, 4 }, /* SD3_DAT5 */
5312 [RCAR_GP_PIN(4, 13)] = { PU4
, 3 }, /* SD3_DAT4 */
5313 [RCAR_GP_PIN(4, 12)] = { PU4
, 2 }, /* SD3_DAT3 */
5314 [RCAR_GP_PIN(4, 11)] = { PU4
, 1 }, /* SD3_DAT2 */
5315 [RCAR_GP_PIN(4, 10)] = { PU4
, 0 }, /* SD3_DAT1 */
5317 [RCAR_GP_PIN(6, 24)] = { PU5
, 31 }, /* USB0_PWEN */
5318 [RCAR_GP_PIN(6, 23)] = { PU5
, 30 }, /* AUDIO_CLKB_B */
5319 [RCAR_GP_PIN(6, 22)] = { PU5
, 29 }, /* AUDIO_CLKA_A */
5320 [RCAR_GP_PIN(6, 21)] = { PU5
, 28 }, /* SSI_SDATA9_A */
5321 [RCAR_GP_PIN(6, 20)] = { PU5
, 27 }, /* SSI_SDATA8 */
5322 [RCAR_GP_PIN(6, 19)] = { PU5
, 26 }, /* SSI_SDATA7 */
5323 [RCAR_GP_PIN(6, 18)] = { PU5
, 25 }, /* SSI_WS78 */
5324 [RCAR_GP_PIN(6, 17)] = { PU5
, 24 }, /* SSI_SCK78 */
5325 [RCAR_GP_PIN(6, 16)] = { PU5
, 23 }, /* SSI_SDATA6 */
5326 [RCAR_GP_PIN(6, 15)] = { PU5
, 22 }, /* SSI_WS6 */
5327 [RCAR_GP_PIN(6, 14)] = { PU5
, 21 }, /* SSI_SCK6 */
5328 [RCAR_GP_PIN(6, 13)] = { PU5
, 20 }, /* SSI_SDATA5 */
5329 [RCAR_GP_PIN(6, 12)] = { PU5
, 19 }, /* SSI_WS5 */
5330 [RCAR_GP_PIN(6, 11)] = { PU5
, 18 }, /* SSI_SCK5 */
5331 [RCAR_GP_PIN(6, 10)] = { PU5
, 17 }, /* SSI_SDATA4 */
5332 [RCAR_GP_PIN(6, 9)] = { PU5
, 16 }, /* SSI_WS4 */
5333 [RCAR_GP_PIN(6, 8)] = { PU5
, 15 }, /* SSI_SCK4 */
5334 [RCAR_GP_PIN(6, 7)] = { PU5
, 14 }, /* SSI_SDATA3 */
5335 [RCAR_GP_PIN(6, 6)] = { PU5
, 13 }, /* SSI_WS34 */
5336 [RCAR_GP_PIN(6, 5)] = { PU5
, 12 }, /* SSI_SCK34 */
5337 [RCAR_GP_PIN(6, 4)] = { PU5
, 11 }, /* SSI_SDATA2_A */
5338 [RCAR_GP_PIN(6, 3)] = { PU5
, 10 }, /* SSI_SDATA1_A */
5339 [RCAR_GP_PIN(6, 2)] = { PU5
, 9 }, /* SSI_SDATA0 */
5340 [RCAR_GP_PIN(6, 1)] = { PU5
, 8 }, /* SSI_WS01239 */
5341 [RCAR_GP_PIN(6, 0)] = { PU5
, 7 }, /* SSI_SCK01239 */
5342 [RCAR_GP_PIN(5, 25)] = { PU5
, 5 }, /* MLB_DAT */
5343 [RCAR_GP_PIN(5, 24)] = { PU5
, 4 }, /* MLB_SIG */
5344 [RCAR_GP_PIN(5, 23)] = { PU5
, 3 }, /* MLB_CLK */
5345 [RCAR_GP_PIN(5, 22)] = { PU5
, 2 }, /* MSIOF0_RXD */
5346 [RCAR_GP_PIN(5, 21)] = { PU5
, 1 }, /* MSIOF0_SS2 */
5347 [RCAR_GP_PIN(5, 20)] = { PU5
, 0 }, /* MSIOF0_TXD */
5349 [RCAR_GP_PIN(6, 31)] = { PU6
, 6 }, /* USB31_OVC */
5350 [RCAR_GP_PIN(6, 30)] = { PU6
, 5 }, /* USB31_PWEN */
5351 [RCAR_GP_PIN(6, 29)] = { PU6
, 4 }, /* USB30_OVC */
5352 [RCAR_GP_PIN(6, 28)] = { PU6
, 3 }, /* USB30_PWEN */
5353 [RCAR_GP_PIN(6, 27)] = { PU6
, 2 }, /* USB1_OVC */
5354 [RCAR_GP_PIN(6, 26)] = { PU6
, 1 }, /* USB1_PWEN */
5355 [RCAR_GP_PIN(6, 25)] = { PU6
, 0 }, /* USB0_OVC */
5358 static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc
*pfc
,
5364 if (WARN_ON_ONCE(!pullups
[pin
].reg
))
5365 return PIN_CONFIG_BIAS_DISABLE
;
5367 reg
= pullups
[pin
].reg
;
5368 bit
= BIT(pullups
[pin
].bit
);
5370 if (sh_pfc_read_reg(pfc
, PUEN
+ reg
, 32) & bit
) {
5371 if (sh_pfc_read_reg(pfc
, PUD
+ reg
, 32) & bit
)
5372 return PIN_CONFIG_BIAS_PULL_UP
;
5374 return PIN_CONFIG_BIAS_PULL_DOWN
;
5376 return PIN_CONFIG_BIAS_DISABLE
;
5379 static void r8a7795_pinmux_set_bias(struct sh_pfc
*pfc
, unsigned int pin
,
5386 if (WARN_ON_ONCE(!pullups
[pin
].reg
))
5389 reg
= pullups
[pin
].reg
;
5390 bit
= BIT(pullups
[pin
].bit
);
5392 enable
= sh_pfc_read_reg(pfc
, PUEN
+ reg
, 32) & ~bit
;
5393 if (bias
!= PIN_CONFIG_BIAS_DISABLE
)
5396 updown
= sh_pfc_read_reg(pfc
, PUD
+ reg
, 32) & ~bit
;
5397 if (bias
== PIN_CONFIG_BIAS_PULL_UP
)
5400 sh_pfc_write_reg(pfc
, PUD
+ reg
, 32, updown
);
5401 sh_pfc_write_reg(pfc
, PUEN
+ reg
, 32, enable
);
5404 static const struct sh_pfc_soc_operations r8a7795_pinmux_ops
= {
5405 .pin_to_pocctrl
= r8a7795_pin_to_pocctrl
,
5406 .get_bias
= r8a7795_pinmux_get_bias
,
5407 .set_bias
= r8a7795_pinmux_set_bias
,
5410 const struct sh_pfc_soc_info r8a7795_pinmux_info
= {
5411 .name
= "r8a77950_pfc",
5412 .ops
= &r8a7795_pinmux_ops
,
5413 .unlock_reg
= 0xe6060000, /* PMMR */
5415 .function
= { PINMUX_FUNCTION_BEGIN
, PINMUX_FUNCTION_END
},
5417 .pins
= pinmux_pins
,
5418 .nr_pins
= ARRAY_SIZE(pinmux_pins
),
5419 .groups
= pinmux_groups
,
5420 .nr_groups
= ARRAY_SIZE(pinmux_groups
),
5421 .functions
= pinmux_functions
,
5422 .nr_functions
= ARRAY_SIZE(pinmux_functions
),
5424 .cfg_regs
= pinmux_config_regs
,
5425 .drive_regs
= pinmux_drive_regs
,
5427 .pinmux_data
= pinmux_data
,
5428 .pinmux_data_size
= ARRAY_SIZE(pinmux_data
),