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lightnvm: NVM should depend on HAS_DMA
[deliverable/linux.git] / drivers / pinctrl / sh-pfc / pfc-r8a7795.c
1 /*
2 * R-Car Gen3 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11 #include <linux/kernel.h>
12
13 #include "core.h"
14 #include "sh_pfc.h"
15
16 #define CPU_ALL_PORT(fn, sfx) \
17 PORT_GP_CFG_16(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
18 PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
19 PORT_GP_CFG_15(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
20 PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE), \
21 PORT_GP_CFG_1(3, 12, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
22 PORT_GP_CFG_1(3, 13, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
23 PORT_GP_CFG_1(3, 14, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
24 PORT_GP_CFG_1(3, 15, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
25 PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_26(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
27 PORT_GP_CFG_32(6, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
28 PORT_GP_CFG_4(7, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
29 /*
30 * F_() : just information
31 * FM() : macro for FN_xxx / xxx_MARK
32 */
33
34 /* GPSR0 */
35 #define GPSR0_15 F_(D15, IP7_11_8)
36 #define GPSR0_14 F_(D14, IP7_7_4)
37 #define GPSR0_13 F_(D13, IP7_3_0)
38 #define GPSR0_12 F_(D12, IP6_31_28)
39 #define GPSR0_11 F_(D11, IP6_27_24)
40 #define GPSR0_10 F_(D10, IP6_23_20)
41 #define GPSR0_9 F_(D9, IP6_19_16)
42 #define GPSR0_8 F_(D8, IP6_15_12)
43 #define GPSR0_7 F_(D7, IP6_11_8)
44 #define GPSR0_6 F_(D6, IP6_7_4)
45 #define GPSR0_5 F_(D5, IP6_3_0)
46 #define GPSR0_4 F_(D4, IP5_31_28)
47 #define GPSR0_3 F_(D3, IP5_27_24)
48 #define GPSR0_2 F_(D2, IP5_23_20)
49 #define GPSR0_1 F_(D1, IP5_19_16)
50 #define GPSR0_0 F_(D0, IP5_15_12)
51
52 /* GPSR1 */
53 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
54 #define GPSR1_26 F_(WE1_N, IP5_7_4)
55 #define GPSR1_25 F_(WE0_N, IP5_3_0)
56 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
57 #define GPSR1_23 F_(RD_N, IP4_27_24)
58 #define GPSR1_22 F_(BS_N, IP4_23_20)
59 #define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
60 #define GPSR1_20 F_(CS0_N, IP4_15_12)
61 #define GPSR1_19 F_(A19, IP4_11_8)
62 #define GPSR1_18 F_(A18, IP4_7_4)
63 #define GPSR1_17 F_(A17, IP4_3_0)
64 #define GPSR1_16 F_(A16, IP3_31_28)
65 #define GPSR1_15 F_(A15, IP3_27_24)
66 #define GPSR1_14 F_(A14, IP3_23_20)
67 #define GPSR1_13 F_(A13, IP3_19_16)
68 #define GPSR1_12 F_(A12, IP3_15_12)
69 #define GPSR1_11 F_(A11, IP3_11_8)
70 #define GPSR1_10 F_(A10, IP3_7_4)
71 #define GPSR1_9 F_(A9, IP3_3_0)
72 #define GPSR1_8 F_(A8, IP2_31_28)
73 #define GPSR1_7 F_(A7, IP2_27_24)
74 #define GPSR1_6 F_(A6, IP2_23_20)
75 #define GPSR1_5 F_(A5, IP2_19_16)
76 #define GPSR1_4 F_(A4, IP2_15_12)
77 #define GPSR1_3 F_(A3, IP2_11_8)
78 #define GPSR1_2 F_(A2, IP2_7_4)
79 #define GPSR1_1 F_(A1, IP2_3_0)
80 #define GPSR1_0 F_(A0, IP1_31_28)
81
82 /* GPSR2 */
83 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
84 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
85 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
86 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
87 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
88 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
89 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
90 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
91 #define GPSR2_6 F_(PWM0, IP1_19_16)
92 #define GPSR2_5 F_(IRQ5, IP1_15_12)
93 #define GPSR2_4 F_(IRQ4, IP1_11_8)
94 #define GPSR2_3 F_(IRQ3, IP1_7_4)
95 #define GPSR2_2 F_(IRQ2, IP1_3_0)
96 #define GPSR2_1 F_(IRQ1, IP0_31_28)
97 #define GPSR2_0 F_(IRQ0, IP0_27_24)
98
99 /* GPSR3 */
100 #define GPSR3_15 F_(SD1_WP, IP10_23_20)
101 #define GPSR3_14 F_(SD1_CD, IP10_19_16)
102 #define GPSR3_13 F_(SD0_WP, IP10_15_12)
103 #define GPSR3_12 F_(SD0_CD, IP10_11_8)
104 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
105 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
106 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
107 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
108 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
109 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
110 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
111 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
112 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
113 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
114 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
115 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
116
117 /* GPSR4 */
118 #define GPSR4_17 FM(SD3_DS)
119 #define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
120 #define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
121 #define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
122 #define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
123 #define GPSR4_12 FM(SD3_DAT3)
124 #define GPSR4_11 FM(SD3_DAT2)
125 #define GPSR4_10 FM(SD3_DAT1)
126 #define GPSR4_9 FM(SD3_DAT0)
127 #define GPSR4_8 FM(SD3_CMD)
128 #define GPSR4_7 FM(SD3_CLK)
129 #define GPSR4_6 F_(SD2_DS, IP9_23_20)
130 #define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
131 #define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
132 #define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
133 #define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
134 #define GPSR4_1 FM(SD2_CMD)
135 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
136
137 /* GPSR5 */
138 #define GPSR5_25 F_(MLB_DAT, IP13_19_16)
139 #define GPSR5_24 F_(MLB_SIG, IP13_15_12)
140 #define GPSR5_23 F_(MLB_CLK, IP13_11_8)
141 #define GPSR5_22 FM(MSIOF0_RXD)
142 #define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4)
143 #define GPSR5_20 FM(MSIOF0_TXD)
144 #define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0)
145 #define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28)
146 #define GPSR5_17 FM(MSIOF0_SCK)
147 #define GPSR5_16 F_(HRTS0_N, IP12_27_24)
148 #define GPSR5_15 F_(HCTS0_N, IP12_23_20)
149 #define GPSR5_14 F_(HTX0, IP12_19_16)
150 #define GPSR5_13 F_(HRX0, IP12_15_12)
151 #define GPSR5_12 F_(HSCK0, IP12_11_8)
152 #define GPSR5_11 F_(RX2_A, IP12_7_4)
153 #define GPSR5_10 F_(TX2_A, IP12_3_0)
154 #define GPSR5_9 F_(SCK2, IP11_31_28)
155 #define GPSR5_8 F_(RTS1_N_TANS, IP11_27_24)
156 #define GPSR5_7 F_(CTS1_N, IP11_23_20)
157 #define GPSR5_6 F_(TX1_A, IP11_19_16)
158 #define GPSR5_5 F_(RX1_A, IP11_15_12)
159 #define GPSR5_4 F_(RTS0_N_TANS, IP11_11_8)
160 #define GPSR5_3 F_(CTS0_N, IP11_7_4)
161 #define GPSR5_2 F_(TX0, IP11_3_0)
162 #define GPSR5_1 F_(RX0, IP10_31_28)
163 #define GPSR5_0 F_(SCK0, IP10_27_24)
164
165 /* GPSR6 */
166 #define GPSR6_31 F_(USB31_OVC, IP17_7_4)
167 #define GPSR6_30 F_(USB31_PWEN, IP17_3_0)
168 #define GPSR6_29 F_(USB30_OVC, IP16_31_28)
169 #define GPSR6_28 F_(USB30_PWEN, IP16_27_24)
170 #define GPSR6_27 F_(USB1_OVC, IP16_23_20)
171 #define GPSR6_26 F_(USB1_PWEN, IP16_19_16)
172 #define GPSR6_25 F_(USB0_OVC, IP16_15_12)
173 #define GPSR6_24 F_(USB0_PWEN, IP16_11_8)
174 #define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4)
175 #define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0)
176 #define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28)
177 #define GPSR6_20 F_(SSI_SDATA8, IP15_27_24)
178 #define GPSR6_19 F_(SSI_SDATA7, IP15_23_20)
179 #define GPSR6_18 F_(SSI_WS78, IP15_19_16)
180 #define GPSR6_17 F_(SSI_SCK78, IP15_15_12)
181 #define GPSR6_16 F_(SSI_SDATA6, IP15_11_8)
182 #define GPSR6_15 F_(SSI_WS6, IP15_7_4)
183 #define GPSR6_14 F_(SSI_SCK6, IP15_3_0)
184 #define GPSR6_13 FM(SSI_SDATA5)
185 #define GPSR6_12 FM(SSI_WS5)
186 #define GPSR6_11 FM(SSI_SCK5)
187 #define GPSR6_10 F_(SSI_SDATA4, IP14_31_28)
188 #define GPSR6_9 F_(SSI_WS4, IP14_27_24)
189 #define GPSR6_8 F_(SSI_SCK4, IP14_23_20)
190 #define GPSR6_7 F_(SSI_SDATA3, IP14_19_16)
191 #define GPSR6_6 F_(SSI_WS34, IP14_15_12)
192 #define GPSR6_5 F_(SSI_SCK34, IP14_11_8)
193 #define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4)
194 #define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0)
195 #define GPSR6_2 F_(SSI_SDATA0, IP13_31_28)
196 #define GPSR6_1 F_(SSI_WS01239, IP13_27_24)
197 #define GPSR6_0 F_(SSI_SCK01239, IP13_23_20)
198
199 /* GPSR7 */
200 #define GPSR7_3 FM(HDMI1_CEC)
201 #define GPSR7_2 FM(HDMI0_CEC)
202 #define GPSR7_1 FM(AVS2)
203 #define GPSR7_0 FM(AVS1)
204
205
206 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
207 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226
227 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
228 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270
271 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
272 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP11_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP11_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314
315 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
316 #define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP14_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP14_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351
352 #define PINMUX_GPSR \
353 \
354 GPSR6_31 \
355 GPSR6_30 \
356 GPSR6_29 \
357 GPSR6_28 \
358 GPSR1_27 GPSR6_27 \
359 GPSR1_26 GPSR6_26 \
360 GPSR1_25 GPSR5_25 GPSR6_25 \
361 GPSR1_24 GPSR5_24 GPSR6_24 \
362 GPSR1_23 GPSR5_23 GPSR6_23 \
363 GPSR1_22 GPSR5_22 GPSR6_22 \
364 GPSR1_21 GPSR5_21 GPSR6_21 \
365 GPSR1_20 GPSR5_20 GPSR6_20 \
366 GPSR1_19 GPSR5_19 GPSR6_19 \
367 GPSR1_18 GPSR5_18 GPSR6_18 \
368 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
369 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
370 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
371 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
372 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
373 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
374 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
375 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
376 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
377 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
378 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
379 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
380 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
381 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
382 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
383 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
384 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
385 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
386
387 #define PINMUX_IPSR \
388 \
389 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
390 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
391 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
392 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
393 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
394 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
395 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
396 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
397 \
398 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
399 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
400 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
401 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
402 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
403 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
404 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
405 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
406 \
407 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
408 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
409 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
410 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
411 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
412 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
413 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
414 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
415 \
416 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
417 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
418 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
419 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
420 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
421 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
422 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
423 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
424 \
425 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \
426 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \
427 FM(IP16_11_8) IP16_11_8 \
428 FM(IP16_15_12) IP16_15_12 \
429 FM(IP16_19_16) IP16_19_16 \
430 FM(IP16_23_20) IP16_23_20 \
431 FM(IP16_27_24) IP16_27_24 \
432 FM(IP16_31_28) IP16_31_28
433
434 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
435 #define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3)
436 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
437 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
438 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
439 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
440 #define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0)
441 #define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
442 #define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
443 #define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
444 #define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
445 #define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
446 #define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
447 #define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1)
448 #define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1)
449 #define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
450 #define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
451 #define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
452 #define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
453 #define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
454 #define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
455 #define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3)
456
457 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
458 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
459 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
460 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
461 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
462 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
463 #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
464 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
465 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
466 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
467 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
468 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
469 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
470 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
471 #define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
472 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
473 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
474 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
475 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
476 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
477 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
478 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
479 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
480
481 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
482 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
483 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
484 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
485 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
486
487 #define PINMUX_MOD_SELS\
488 \
489 MOD_SEL1_31_30 MOD_SEL2_31 \
490 MOD_SEL0_30_29 MOD_SEL2_30 \
491 MOD_SEL1_29_28_27 MOD_SEL2_29 \
492 MOD_SEL0_28_27 \
493 \
494 MOD_SEL0_26_25_24 MOD_SEL1_26 \
495 MOD_SEL1_25_24 \
496 \
497 MOD_SEL0_23 MOD_SEL1_23_22_21 \
498 MOD_SEL0_22 \
499 MOD_SEL0_21_20 \
500 MOD_SEL1_20 \
501 MOD_SEL0_19 MOD_SEL1_19 \
502 MOD_SEL0_18 MOD_SEL1_18_17 \
503 MOD_SEL0_17 \
504 MOD_SEL0_16_15 MOD_SEL1_16 \
505 MOD_SEL1_15_14 \
506 MOD_SEL0_14 \
507 MOD_SEL0_13 MOD_SEL1_13 \
508 MOD_SEL0_12 MOD_SEL1_12 \
509 MOD_SEL0_11 MOD_SEL1_11 \
510 MOD_SEL0_10 MOD_SEL1_10 \
511 MOD_SEL0_9 MOD_SEL1_9 \
512 MOD_SEL0_8 \
513 MOD_SEL0_7_6 \
514 MOD_SEL1_6 \
515 MOD_SEL0_5_4 MOD_SEL1_5 \
516 MOD_SEL1_4 \
517 MOD_SEL0_3 MOD_SEL1_3 \
518 MOD_SEL0_2_1 MOD_SEL1_2 \
519 MOD_SEL1_1 \
520 MOD_SEL1_0 MOD_SEL2_0
521
522
523 enum {
524 PINMUX_RESERVED = 0,
525
526 PINMUX_DATA_BEGIN,
527 GP_ALL(DATA),
528 PINMUX_DATA_END,
529
530 #define F_(x, y)
531 #define FM(x) FN_##x,
532 PINMUX_FUNCTION_BEGIN,
533 GP_ALL(FN),
534 PINMUX_GPSR
535 PINMUX_IPSR
536 PINMUX_MOD_SELS
537 PINMUX_FUNCTION_END,
538 #undef F_
539 #undef FM
540
541 #define F_(x, y)
542 #define FM(x) x##_MARK,
543 PINMUX_MARK_BEGIN,
544 PINMUX_GPSR
545 PINMUX_IPSR
546 PINMUX_MOD_SELS
547 PINMUX_MARK_END,
548 #undef F_
549 #undef FM
550 };
551
552 static const u16 pinmux_data[] = {
553 PINMUX_DATA_GP_ALL(),
554
555 PINMUX_SINGLE(AVS1),
556 PINMUX_SINGLE(AVS2),
557 PINMUX_SINGLE(HDMI0_CEC),
558 PINMUX_SINGLE(HDMI1_CEC),
559 PINMUX_SINGLE(I2C_SEL_0_1),
560 PINMUX_SINGLE(I2C_SEL_3_1),
561 PINMUX_SINGLE(I2C_SEL_5_1),
562 PINMUX_SINGLE(MSIOF0_RXD),
563 PINMUX_SINGLE(MSIOF0_SCK),
564 PINMUX_SINGLE(MSIOF0_TXD),
565 PINMUX_SINGLE(SD2_CMD),
566 PINMUX_SINGLE(SD3_CLK),
567 PINMUX_SINGLE(SD3_CMD),
568 PINMUX_SINGLE(SD3_DAT0),
569 PINMUX_SINGLE(SD3_DAT1),
570 PINMUX_SINGLE(SD3_DAT2),
571 PINMUX_SINGLE(SD3_DAT3),
572 PINMUX_SINGLE(SD3_DS),
573 PINMUX_SINGLE(SSI_SCK5),
574 PINMUX_SINGLE(SSI_SDATA5),
575 PINMUX_SINGLE(SSI_WS5),
576
577 /* IPSR0 */
578 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
579 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
580
581 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
582 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
583 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
584
585 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
586 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
587 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
588
589 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
590 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
591 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
592
593 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
594 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
595 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
596
597 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
598 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
599 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
600
601 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
602 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
603 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
604 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
605 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
606 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
607
608 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
609 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
610 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
611 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
612 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
613 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
614
615 /* IPSR1 */
616 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
617 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
618 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
619 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
620 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
621
622 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
623 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
624 PINMUX_IPSR_GPSR(IP1_7_4, A25),
625 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
626 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
627 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
628
629 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
630 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
631 PINMUX_IPSR_GPSR(IP1_11_8, A24),
632 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
633 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
634 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
635
636 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
637 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
638 PINMUX_IPSR_GPSR(IP1_15_12, A23),
639 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
640 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
641 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
642
643 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
644 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
645 PINMUX_IPSR_GPSR(IP1_19_16, A22),
646 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
647 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
648
649 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
650 PINMUX_IPSR_GPSR(IP1_23_20, A21),
651 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
652 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
653 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
654
655 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
656 PINMUX_IPSR_GPSR(IP1_27_24, A20),
657 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
658 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
659
660 PINMUX_IPSR_GPSR(IP1_31_28, A0),
661 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
662 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
663 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
664 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
665 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
666
667 /* IPSR2 */
668 PINMUX_IPSR_GPSR(IP2_3_0, A1),
669 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
670 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
671 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
672 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
673 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
674
675 PINMUX_IPSR_GPSR(IP2_7_4, A2),
676 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
677 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
678 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
679 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
680 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
681
682 PINMUX_IPSR_GPSR(IP2_11_8, A3),
683 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
684 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
685 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
686 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
687 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
688
689 PINMUX_IPSR_GPSR(IP2_15_12, A4),
690 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
691 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
692 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
693 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
694 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
695
696 PINMUX_IPSR_GPSR(IP2_19_16, A5),
697 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
698 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
699 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
700 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
701 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
702 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
703
704 PINMUX_IPSR_GPSR(IP2_23_20, A6),
705 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
706 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
707 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
708 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
709 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
710 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
711
712 PINMUX_IPSR_GPSR(IP2_27_24, A7),
713 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
714 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
715 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
716 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
717 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
718 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
719
720 PINMUX_IPSR_GPSR(IP2_31_28, A8),
721 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
722 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
723 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
724 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
725 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
726 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
727
728 /* IPSR3 */
729 PINMUX_IPSR_GPSR(IP3_3_0, A9),
730 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
731 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
732 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
733
734 PINMUX_IPSR_GPSR(IP3_7_4, A10),
735 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
736 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
737 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
738
739 PINMUX_IPSR_GPSR(IP3_11_8, A11),
740 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
741 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
742 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
743 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
744 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
745 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
746 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
747 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
748
749 PINMUX_IPSR_GPSR(IP3_15_12, A12),
750 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
751 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
752 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
753 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
754 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
755
756 PINMUX_IPSR_GPSR(IP3_19_16, A13),
757 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
758 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
759 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
760 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
761 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
762
763 PINMUX_IPSR_GPSR(IP3_23_20, A14),
764 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
765 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
766 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
767 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
768 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
769
770 PINMUX_IPSR_GPSR(IP3_27_24, A15),
771 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
772 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
773 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
774 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
775 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
776
777 PINMUX_IPSR_GPSR(IP3_31_28, A16),
778 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
779 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
780 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
781
782 /* IPSR4 */
783 PINMUX_IPSR_GPSR(IP4_3_0, A17),
784 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
785 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
786 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
787
788 PINMUX_IPSR_GPSR(IP4_7_4, A18),
789 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
790 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
791 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
792
793 PINMUX_IPSR_GPSR(IP4_11_8, A19),
794 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
795 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
796 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
797
798 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
799 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
800
801 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
802 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
803 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
804
805 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
806 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
807 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
808 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
809 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
810 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
811 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
812 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
813
814 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
815 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
816 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
817 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
818 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
819 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
820
821 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
822 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
823 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
824 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
825 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
826 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
827
828 /* IPSR5 */
829 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
830 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
831 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
832 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
833 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
834 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
835 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
836
837 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
838 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
839 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
840 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
841 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
842 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
843 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
844 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
845
846 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
847 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
848 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
849 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
850
851 PINMUX_IPSR_GPSR(IP5_15_12, D0),
852 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
853 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
854 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
855 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
856
857 PINMUX_IPSR_GPSR(IP5_19_16, D1),
858 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
859 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
860 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
861 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
862
863 PINMUX_IPSR_GPSR(IP5_23_20, D2),
864 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
865 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
866 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
867
868 PINMUX_IPSR_GPSR(IP5_27_24, D3),
869 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
870 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
871 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
872
873 PINMUX_IPSR_GPSR(IP5_31_28, D4),
874 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
875 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
876 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
877
878 /* IPSR6 */
879 PINMUX_IPSR_GPSR(IP6_3_0, D5),
880 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
881 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
882 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
883
884 PINMUX_IPSR_GPSR(IP6_7_4, D6),
885 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
886 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
887 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
888
889 PINMUX_IPSR_GPSR(IP6_11_8, D7),
890 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
891 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
892 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
893
894 PINMUX_IPSR_GPSR(IP6_15_12, D8),
895 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
896 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
897 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
898 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
899 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
900
901 PINMUX_IPSR_GPSR(IP6_19_16, D9),
902 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
903 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
904 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
905 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
906
907 PINMUX_IPSR_GPSR(IP6_23_20, D10),
908 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
909 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
910 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
911 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
912 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
913 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
914
915 PINMUX_IPSR_GPSR(IP6_27_24, D11),
916 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
917 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
918 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
919 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
920 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
921 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
922
923 PINMUX_IPSR_GPSR(IP6_31_28, D12),
924 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
925 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
926 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
927 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
928 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
929
930 /* IPSR7 */
931 PINMUX_IPSR_GPSR(IP7_3_0, D13),
932 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
933 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
934 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
935 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
936 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
937
938 PINMUX_IPSR_GPSR(IP7_7_4, D14),
939 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
940 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
941 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
942 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
943 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
944 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
945
946 PINMUX_IPSR_GPSR(IP7_11_8, D15),
947 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
948 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
949 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
950 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
951 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
952 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
953
954 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
955
956 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
957 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
958 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
959
960 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
961 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
962 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
963
964 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
965 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
966 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
967 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
968
969 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
970 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
971 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
972 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
973
974 /* IPSR8 */
975 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
976 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
977 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
978 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
979
980 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
981 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
982 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
983 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
984
985 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
986 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
987 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
988
989 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
990 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
991 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
992 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
993
994 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
995 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
996 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
997 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
998 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
999
1000 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1001 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1002 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1003 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1004 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1005
1006 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1007 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1008 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1009 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1010 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1011
1012 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1013 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1014 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1015 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1016 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1017
1018 /* IPSR9 */
1019 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1020
1021 PINMUX_IPSR_GPSR(IP9_7_4, SD2_DAT0),
1022
1023 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT1),
1024
1025 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT2),
1026
1027 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT3),
1028
1029 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DS),
1030 PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1),
1031
1032 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT4),
1033 PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0),
1034
1035 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT5),
1036 PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0),
1037
1038 /* IPSR10 */
1039 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT6),
1040 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CD),
1041
1042 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT7),
1043 PINMUX_IPSR_GPSR(IP10_7_4, SD3_WP),
1044
1045 PINMUX_IPSR_GPSR(IP10_11_8, SD0_CD),
1046 PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1),
1047 PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1048
1049 PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP),
1050 PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1),
1051
1052 PINMUX_IPSR_GPSR(IP10_19_16, SD1_CD),
1053 PINMUX_IPSR_MSEL(IP10_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1054
1055 PINMUX_IPSR_GPSR(IP10_23_20, SD1_WP),
1056 PINMUX_IPSR_MSEL(IP10_23_20, SIM0_D_B, SEL_SIMCARD_1),
1057
1058 PINMUX_IPSR_GPSR(IP10_27_24, SCK0),
1059 PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
1060 PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1061 PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1),
1062 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
1063 PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1064 PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1065 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1066 PINMUX_IPSR_GPSR(IP10_27_24, ADICHS2),
1067
1068 PINMUX_IPSR_GPSR(IP10_31_28, RX0),
1069 PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1),
1070 PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2),
1071 PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1072 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1073
1074 /* IPSR11 */
1075 PINMUX_IPSR_GPSR(IP11_3_0, TX0),
1076 PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1),
1077 PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1078 PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1079 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1080
1081 PINMUX_IPSR_GPSR(IP11_7_4, CTS0_N),
1082 PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1083 PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1084 PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1085 PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1086 PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1087 PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2),
1088 PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP),
1089
1090 PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N_TANS),
1091 PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1092 PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1093 PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
1094 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0),
1095 PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1096 PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1097 PINMUX_IPSR_GPSR(IP11_11_8, ADICHS1),
1098
1099 PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0),
1100 PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0),
1101 PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1102 PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1103 PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1104
1105 PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0),
1106 PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0),
1107 PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1108 PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1109 PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2),
1110
1111 PINMUX_IPSR_GPSR(IP11_23_20, CTS1_N),
1112 PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1113 PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1114 PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1115 PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1116 PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1),
1117 PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA),
1118
1119 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
1120 PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1121 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1122 PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1123 PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1124 PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1),
1125 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS0),
1126
1127 PINMUX_IPSR_GPSR(IP11_31_28, SCK2),
1128 PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1129 PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1130 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2),
1131 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1132 PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1133 PINMUX_IPSR_GPSR(IP11_31_28, ADICLK),
1134
1135 /* IPSR12 */
1136 PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0),
1137 PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1),
1138 PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0),
1139 PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0),
1140 PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2),
1141 PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1),
1142
1143 PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0),
1144 PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1),
1145 PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0),
1146 PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0),
1147 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1148 PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1),
1149
1150 PINMUX_IPSR_GPSR(IP12_11_8, HSCK0),
1151 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1152 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0),
1153 PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1),
1154 PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3),
1155 PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1156 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1157
1158 PINMUX_IPSR_GPSR(IP12_15_12, HRX0),
1159 PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1160 PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1),
1161 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1162 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1163 PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2),
1164
1165 PINMUX_IPSR_GPSR(IP12_19_16, HTX0),
1166 PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1167 PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1),
1168 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1169 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1170 PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2),
1171
1172 PINMUX_IPSR_GPSR(IP12_23_20, HCTS0_N),
1173 PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1),
1174 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1175 PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0),
1176 PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1177 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1178 PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1179 PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0),
1180
1181 PINMUX_IPSR_GPSR(IP12_27_24, HRTS0_N),
1182 PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1),
1183 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1184 PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0),
1185 PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1186 PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0),
1187 PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0),
1188
1189 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
1190 PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0),
1191
1192 /* IPSR13 */
1193 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
1194 PINMUX_IPSR_GPSR(IP13_3_0, RX5),
1195 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2),
1196 PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0),
1197 PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1198 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0),
1199 PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1200
1201 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
1202 PINMUX_IPSR_GPSR(IP13_7_4, TX5),
1203 PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1204 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0),
1205 PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0),
1206 PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1207 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3),
1208 PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1209
1210 PINMUX_IPSR_GPSR(IP13_11_8, MLB_CLK),
1211 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1212 PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1),
1213
1214 PINMUX_IPSR_GPSR(IP13_15_12, MLB_SIG),
1215 PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1),
1216 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1217 PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1),
1218
1219 PINMUX_IPSR_GPSR(IP13_19_16, MLB_DAT),
1220 PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1),
1221 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1222
1223 PINMUX_IPSR_GPSR(IP13_23_20, SSI_SCK01239),
1224 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1225
1226 PINMUX_IPSR_GPSR(IP13_27_24, SSI_WS01239),
1227 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1228
1229 PINMUX_IPSR_GPSR(IP13_31_28, SSI_SDATA0),
1230 PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1231
1232 /* IPSR14 */
1233 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0),
1234
1235 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0),
1236 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1),
1237
1238 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK34),
1239 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1240 PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1241
1242 PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS34),
1243 PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1244 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1245 PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1246
1247 PINMUX_IPSR_GPSR(IP14_19_16, SSI_SDATA3),
1248 PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1249 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1250 PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0),
1251 PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1252 PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0),
1253 PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0),
1254
1255 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK4),
1256 PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0),
1257 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1258 PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1259 PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1260 PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1261 PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1262
1263 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS4),
1264 PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0),
1265 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1266 PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1267 PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1268 PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1269 PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1270
1271 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA4),
1272 PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0),
1273 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1274 PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1275 PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1276 PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0),
1277 PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0),
1278
1279 /* IPSR15 */
1280 PINMUX_IPSR_GPSR(IP15_3_0, SSI_SCK6),
1281 PINMUX_IPSR_GPSR(IP15_3_0, USB2_PWEN),
1282 PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1283
1284 PINMUX_IPSR_GPSR(IP15_7_4, SSI_WS6),
1285 PINMUX_IPSR_GPSR(IP15_7_4, USB2_OVC),
1286 PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3),
1287
1288 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SDATA6),
1289 PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1290 PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0),
1291
1292 PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK78),
1293 PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1),
1294 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1295 PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0),
1296 PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1297 PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1298 PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1299
1300 PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS78),
1301 PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1),
1302 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1303 PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1304 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1305 PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1306 PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1307
1308 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA7),
1309 PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1310 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1311 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1312 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1313 PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0),
1314 PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0),
1315 PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0),
1316
1317 PINMUX_IPSR_GPSR(IP15_27_24, SSI_SDATA8),
1318 PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1319 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1320 PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1321 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1322 PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0),
1323 PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0),
1324
1325 PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0),
1326 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1),
1327 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1328 PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0),
1329 PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1),
1330 PINMUX_IPSR_GPSR(IP15_31_28, SCK1),
1331 PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1332 PINMUX_IPSR_GPSR(IP15_31_28, SCK5),
1333
1334 /* IPSR16 */
1335 PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
1336 PINMUX_IPSR_GPSR(IP16_3_0, CC5_OSCOUT),
1337
1338 PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
1339 PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1340 PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1341 PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0),
1342 PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1343
1344 PINMUX_IPSR_GPSR(IP16_11_8, USB0_PWEN),
1345 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1346 PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3),
1347 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1348 PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1),
1349 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1350
1351 PINMUX_IPSR_GPSR(IP16_15_12, USB0_OVC),
1352 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2),
1353 PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3),
1354 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3),
1355 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1),
1356
1357 PINMUX_IPSR_GPSR(IP16_19_16, USB1_PWEN),
1358 PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1359 PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0),
1360 PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4),
1361 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1362 PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1),
1363 PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1364 PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1365
1366 PINMUX_IPSR_GPSR(IP16_23_20, USB1_OVC),
1367 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1368 PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0),
1369 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1370 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1371 PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1),
1372 PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1373 PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1),
1374
1375 PINMUX_IPSR_GPSR(IP16_27_24, USB30_PWEN),
1376 PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
1377 PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
1378 PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1379 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_2),
1380 PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1381 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
1382 PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
1383 PINMUX_IPSR_GPSR(IP16_27_24, TPU0TO0),
1384
1385 PINMUX_IPSR_GPSR(IP16_31_28, USB30_OVC),
1386 PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1),
1387 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1),
1388 PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1389 PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1390 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1391 PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1),
1392 PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1),
1393 PINMUX_IPSR_GPSR(IP16_31_28, TPU0TO1),
1394
1395 /* IPSR17 */
1396 PINMUX_IPSR_GPSR(IP17_3_0, USB31_PWEN),
1397 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1),
1398 PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1),
1399 PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1400 PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1401 PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1),
1402 PINMUX_IPSR_GPSR(IP17_3_0, TPU0TO2),
1403
1404 PINMUX_IPSR_GPSR(IP17_7_4, USB31_OVC),
1405 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1),
1406 PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1),
1407 PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1408 PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1409 PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
1410 PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3),
1411 };
1412
1413 static const struct sh_pfc_pin pinmux_pins[] = {
1414 PINMUX_GPIO_GP_ALL(),
1415 };
1416
1417 /* - AUDIO CLOCK ------------------------------------------------------------ */
1418 static const unsigned int audio_clk_a_a_pins[] = {
1419 /* CLK A */
1420 RCAR_GP_PIN(6, 22),
1421 };
1422 static const unsigned int audio_clk_a_a_mux[] = {
1423 AUDIO_CLKA_A_MARK,
1424 };
1425 static const unsigned int audio_clk_a_b_pins[] = {
1426 /* CLK A */
1427 RCAR_GP_PIN(5, 4),
1428 };
1429 static const unsigned int audio_clk_a_b_mux[] = {
1430 AUDIO_CLKA_B_MARK,
1431 };
1432 static const unsigned int audio_clk_a_c_pins[] = {
1433 /* CLK A */
1434 RCAR_GP_PIN(5, 19),
1435 };
1436 static const unsigned int audio_clk_a_c_mux[] = {
1437 AUDIO_CLKA_C_MARK,
1438 };
1439 static const unsigned int audio_clk_b_a_pins[] = {
1440 /* CLK B */
1441 RCAR_GP_PIN(5, 12),
1442 };
1443 static const unsigned int audio_clk_b_a_mux[] = {
1444 AUDIO_CLKB_A_MARK,
1445 };
1446 static const unsigned int audio_clk_b_b_pins[] = {
1447 /* CLK B */
1448 RCAR_GP_PIN(6, 23),
1449 };
1450 static const unsigned int audio_clk_b_b_mux[] = {
1451 AUDIO_CLKB_B_MARK,
1452 };
1453 static const unsigned int audio_clk_c_a_pins[] = {
1454 /* CLK C */
1455 RCAR_GP_PIN(5, 21),
1456 };
1457 static const unsigned int audio_clk_c_a_mux[] = {
1458 AUDIO_CLKC_A_MARK,
1459 };
1460 static const unsigned int audio_clk_c_b_pins[] = {
1461 /* CLK C */
1462 RCAR_GP_PIN(5, 0),
1463 };
1464 static const unsigned int audio_clk_c_b_mux[] = {
1465 AUDIO_CLKC_B_MARK,
1466 };
1467 static const unsigned int audio_clkout_a_pins[] = {
1468 /* CLKOUT */
1469 RCAR_GP_PIN(5, 18),
1470 };
1471 static const unsigned int audio_clkout_a_mux[] = {
1472 AUDIO_CLKOUT_A_MARK,
1473 };
1474 static const unsigned int audio_clkout_b_pins[] = {
1475 /* CLKOUT */
1476 RCAR_GP_PIN(6, 28),
1477 };
1478 static const unsigned int audio_clkout_b_mux[] = {
1479 AUDIO_CLKOUT_B_MARK,
1480 };
1481 static const unsigned int audio_clkout_c_pins[] = {
1482 /* CLKOUT */
1483 RCAR_GP_PIN(5, 3),
1484 };
1485 static const unsigned int audio_clkout_c_mux[] = {
1486 AUDIO_CLKOUT_C_MARK,
1487 };
1488 static const unsigned int audio_clkout_d_pins[] = {
1489 /* CLKOUT */
1490 RCAR_GP_PIN(5, 21),
1491 };
1492 static const unsigned int audio_clkout_d_mux[] = {
1493 AUDIO_CLKOUT_D_MARK,
1494 };
1495 static const unsigned int audio_clkout1_a_pins[] = {
1496 /* CLKOUT1 */
1497 RCAR_GP_PIN(5, 15),
1498 };
1499 static const unsigned int audio_clkout1_a_mux[] = {
1500 AUDIO_CLKOUT1_A_MARK,
1501 };
1502 static const unsigned int audio_clkout1_b_pins[] = {
1503 /* CLKOUT1 */
1504 RCAR_GP_PIN(6, 29),
1505 };
1506 static const unsigned int audio_clkout1_b_mux[] = {
1507 AUDIO_CLKOUT1_B_MARK,
1508 };
1509 static const unsigned int audio_clkout2_a_pins[] = {
1510 /* CLKOUT2 */
1511 RCAR_GP_PIN(5, 16),
1512 };
1513 static const unsigned int audio_clkout2_a_mux[] = {
1514 AUDIO_CLKOUT2_A_MARK,
1515 };
1516 static const unsigned int audio_clkout2_b_pins[] = {
1517 /* CLKOUT2 */
1518 RCAR_GP_PIN(6, 30),
1519 };
1520 static const unsigned int audio_clkout2_b_mux[] = {
1521 AUDIO_CLKOUT2_B_MARK,
1522 };
1523
1524 static const unsigned int audio_clkout3_a_pins[] = {
1525 /* CLKOUT3 */
1526 RCAR_GP_PIN(5, 19),
1527 };
1528 static const unsigned int audio_clkout3_a_mux[] = {
1529 AUDIO_CLKOUT3_A_MARK,
1530 };
1531 static const unsigned int audio_clkout3_b_pins[] = {
1532 /* CLKOUT3 */
1533 RCAR_GP_PIN(6, 31),
1534 };
1535 static const unsigned int audio_clkout3_b_mux[] = {
1536 AUDIO_CLKOUT3_B_MARK,
1537 };
1538
1539 /* - EtherAVB --------------------------------------------------------------- */
1540 static const unsigned int avb_link_pins[] = {
1541 /* AVB_LINK */
1542 RCAR_GP_PIN(2, 12),
1543 };
1544 static const unsigned int avb_link_mux[] = {
1545 AVB_LINK_MARK,
1546 };
1547 static const unsigned int avb_magic_pins[] = {
1548 /* AVB_MAGIC_ */
1549 RCAR_GP_PIN(2, 10),
1550 };
1551 static const unsigned int avb_magic_mux[] = {
1552 AVB_MAGIC_MARK,
1553 };
1554 static const unsigned int avb_phy_int_pins[] = {
1555 /* AVB_PHY_INT */
1556 RCAR_GP_PIN(2, 11),
1557 };
1558 static const unsigned int avb_phy_int_mux[] = {
1559 AVB_PHY_INT_MARK,
1560 };
1561 static const unsigned int avb_mdc_pins[] = {
1562 /* AVB_MDC */
1563 RCAR_GP_PIN(2, 9),
1564 };
1565 static const unsigned int avb_mdc_mux[] = {
1566 AVB_MDC_MARK,
1567 };
1568 static const unsigned int avb_avtp_pps_pins[] = {
1569 /* AVB_AVTP_PPS */
1570 RCAR_GP_PIN(2, 6),
1571 };
1572 static const unsigned int avb_avtp_pps_mux[] = {
1573 AVB_AVTP_PPS_MARK,
1574 };
1575 static const unsigned int avb_avtp_match_a_pins[] = {
1576 /* AVB_AVTP_MATCH_A */
1577 RCAR_GP_PIN(2, 13),
1578 };
1579 static const unsigned int avb_avtp_match_a_mux[] = {
1580 AVB_AVTP_MATCH_A_MARK,
1581 };
1582 static const unsigned int avb_avtp_capture_a_pins[] = {
1583 /* AVB_AVTP_CAPTURE_A */
1584 RCAR_GP_PIN(2, 14),
1585 };
1586 static const unsigned int avb_avtp_capture_a_mux[] = {
1587 AVB_AVTP_CAPTURE_A_MARK,
1588 };
1589 static const unsigned int avb_avtp_match_b_pins[] = {
1590 /* AVB_AVTP_MATCH_B */
1591 RCAR_GP_PIN(1, 8),
1592 };
1593 static const unsigned int avb_avtp_match_b_mux[] = {
1594 AVB_AVTP_MATCH_B_MARK,
1595 };
1596 static const unsigned int avb_avtp_capture_b_pins[] = {
1597 /* AVB_AVTP_CAPTURE_B */
1598 RCAR_GP_PIN(1, 11),
1599 };
1600 static const unsigned int avb_avtp_capture_b_mux[] = {
1601 AVB_AVTP_CAPTURE_B_MARK,
1602 };
1603
1604 /* - CAN ------------------------------------------------------------------ */
1605 static const unsigned int can0_data_a_pins[] = {
1606 /* TX, RX */
1607 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1608 };
1609 static const unsigned int can0_data_a_mux[] = {
1610 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1611 };
1612 static const unsigned int can0_data_b_pins[] = {
1613 /* TX, RX */
1614 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1615 };
1616 static const unsigned int can0_data_b_mux[] = {
1617 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1618 };
1619 static const unsigned int can1_data_pins[] = {
1620 /* TX, RX */
1621 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1622 };
1623 static const unsigned int can1_data_mux[] = {
1624 CAN1_TX_MARK, CAN1_RX_MARK,
1625 };
1626
1627 /* - CAN Clock -------------------------------------------------------------- */
1628 static const unsigned int can_clk_pins[] = {
1629 /* CLK */
1630 RCAR_GP_PIN(1, 25),
1631 };
1632 static const unsigned int can_clk_mux[] = {
1633 CAN_CLK_MARK,
1634 };
1635
1636 /* - CAN FD --------------------------------------------------------------- */
1637 static const unsigned int canfd0_data_a_pins[] = {
1638 /* TX, RX */
1639 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1640 };
1641 static const unsigned int canfd0_data_a_mux[] = {
1642 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1643 };
1644 static const unsigned int canfd0_data_b_pins[] = {
1645 /* TX, RX */
1646 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1647 };
1648 static const unsigned int canfd0_data_b_mux[] = {
1649 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1650 };
1651 static const unsigned int canfd1_data_pins[] = {
1652 /* TX, RX */
1653 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1654 };
1655 static const unsigned int canfd1_data_mux[] = {
1656 CANFD1_TX_MARK, CANFD1_RX_MARK,
1657 };
1658
1659 /* - DRIF0 --------------------------------------------------------------- */
1660 static const unsigned int drif0_ctrl_a_pins[] = {
1661 /* CLK, SYNC */
1662 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1663 };
1664 static const unsigned int drif0_ctrl_a_mux[] = {
1665 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1666 };
1667 static const unsigned int drif0_data0_a_pins[] = {
1668 /* D0 */
1669 RCAR_GP_PIN(6, 10),
1670 };
1671 static const unsigned int drif0_data0_a_mux[] = {
1672 RIF0_D0_A_MARK,
1673 };
1674 static const unsigned int drif0_data1_a_pins[] = {
1675 /* D1 */
1676 RCAR_GP_PIN(6, 7),
1677 };
1678 static const unsigned int drif0_data1_a_mux[] = {
1679 RIF0_D1_A_MARK,
1680 };
1681 static const unsigned int drif0_ctrl_b_pins[] = {
1682 /* CLK, SYNC */
1683 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1684 };
1685 static const unsigned int drif0_ctrl_b_mux[] = {
1686 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1687 };
1688 static const unsigned int drif0_data0_b_pins[] = {
1689 /* D0 */
1690 RCAR_GP_PIN(5, 1),
1691 };
1692 static const unsigned int drif0_data0_b_mux[] = {
1693 RIF0_D0_B_MARK,
1694 };
1695 static const unsigned int drif0_data1_b_pins[] = {
1696 /* D1 */
1697 RCAR_GP_PIN(5, 2),
1698 };
1699 static const unsigned int drif0_data1_b_mux[] = {
1700 RIF0_D1_B_MARK,
1701 };
1702 static const unsigned int drif0_ctrl_c_pins[] = {
1703 /* CLK, SYNC */
1704 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1705 };
1706 static const unsigned int drif0_ctrl_c_mux[] = {
1707 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1708 };
1709 static const unsigned int drif0_data0_c_pins[] = {
1710 /* D0 */
1711 RCAR_GP_PIN(5, 13),
1712 };
1713 static const unsigned int drif0_data0_c_mux[] = {
1714 RIF0_D0_C_MARK,
1715 };
1716 static const unsigned int drif0_data1_c_pins[] = {
1717 /* D1 */
1718 RCAR_GP_PIN(5, 14),
1719 };
1720 static const unsigned int drif0_data1_c_mux[] = {
1721 RIF0_D1_C_MARK,
1722 };
1723 /* - DRIF1 --------------------------------------------------------------- */
1724 static const unsigned int drif1_ctrl_a_pins[] = {
1725 /* CLK, SYNC */
1726 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1727 };
1728 static const unsigned int drif1_ctrl_a_mux[] = {
1729 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1730 };
1731 static const unsigned int drif1_data0_a_pins[] = {
1732 /* D0 */
1733 RCAR_GP_PIN(6, 19),
1734 };
1735 static const unsigned int drif1_data0_a_mux[] = {
1736 RIF1_D0_A_MARK,
1737 };
1738 static const unsigned int drif1_data1_a_pins[] = {
1739 /* D1 */
1740 RCAR_GP_PIN(6, 20),
1741 };
1742 static const unsigned int drif1_data1_a_mux[] = {
1743 RIF1_D1_A_MARK,
1744 };
1745 static const unsigned int drif1_ctrl_b_pins[] = {
1746 /* CLK, SYNC */
1747 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1748 };
1749 static const unsigned int drif1_ctrl_b_mux[] = {
1750 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1751 };
1752 static const unsigned int drif1_data0_b_pins[] = {
1753 /* D0 */
1754 RCAR_GP_PIN(5, 7),
1755 };
1756 static const unsigned int drif1_data0_b_mux[] = {
1757 RIF1_D0_B_MARK,
1758 };
1759 static const unsigned int drif1_data1_b_pins[] = {
1760 /* D1 */
1761 RCAR_GP_PIN(5, 8),
1762 };
1763 static const unsigned int drif1_data1_b_mux[] = {
1764 RIF1_D1_B_MARK,
1765 };
1766 static const unsigned int drif1_ctrl_c_pins[] = {
1767 /* CLK, SYNC */
1768 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1769 };
1770 static const unsigned int drif1_ctrl_c_mux[] = {
1771 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1772 };
1773 static const unsigned int drif1_data0_c_pins[] = {
1774 /* D0 */
1775 RCAR_GP_PIN(5, 6),
1776 };
1777 static const unsigned int drif1_data0_c_mux[] = {
1778 RIF1_D0_C_MARK,
1779 };
1780 static const unsigned int drif1_data1_c_pins[] = {
1781 /* D1 */
1782 RCAR_GP_PIN(5, 10),
1783 };
1784 static const unsigned int drif1_data1_c_mux[] = {
1785 RIF1_D1_C_MARK,
1786 };
1787 /* - DRIF2 --------------------------------------------------------------- */
1788 static const unsigned int drif2_ctrl_a_pins[] = {
1789 /* CLK, SYNC */
1790 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1791 };
1792 static const unsigned int drif2_ctrl_a_mux[] = {
1793 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1794 };
1795 static const unsigned int drif2_data0_a_pins[] = {
1796 /* D0 */
1797 RCAR_GP_PIN(6, 7),
1798 };
1799 static const unsigned int drif2_data0_a_mux[] = {
1800 RIF2_D0_A_MARK,
1801 };
1802 static const unsigned int drif2_data1_a_pins[] = {
1803 /* D1 */
1804 RCAR_GP_PIN(6, 10),
1805 };
1806 static const unsigned int drif2_data1_a_mux[] = {
1807 RIF2_D1_A_MARK,
1808 };
1809 static const unsigned int drif2_ctrl_b_pins[] = {
1810 /* CLK, SYNC */
1811 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1812 };
1813 static const unsigned int drif2_ctrl_b_mux[] = {
1814 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1815 };
1816 static const unsigned int drif2_data0_b_pins[] = {
1817 /* D0 */
1818 RCAR_GP_PIN(6, 30),
1819 };
1820 static const unsigned int drif2_data0_b_mux[] = {
1821 RIF2_D0_B_MARK,
1822 };
1823 static const unsigned int drif2_data1_b_pins[] = {
1824 /* D1 */
1825 RCAR_GP_PIN(6, 31),
1826 };
1827 static const unsigned int drif2_data1_b_mux[] = {
1828 RIF2_D1_B_MARK,
1829 };
1830 /* - DRIF3 --------------------------------------------------------------- */
1831 static const unsigned int drif3_ctrl_a_pins[] = {
1832 /* CLK, SYNC */
1833 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1834 };
1835 static const unsigned int drif3_ctrl_a_mux[] = {
1836 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1837 };
1838 static const unsigned int drif3_data0_a_pins[] = {
1839 /* D0 */
1840 RCAR_GP_PIN(6, 19),
1841 };
1842 static const unsigned int drif3_data0_a_mux[] = {
1843 RIF3_D0_A_MARK,
1844 };
1845 static const unsigned int drif3_data1_a_pins[] = {
1846 /* D1 */
1847 RCAR_GP_PIN(6, 20),
1848 };
1849 static const unsigned int drif3_data1_a_mux[] = {
1850 RIF3_D1_A_MARK,
1851 };
1852 static const unsigned int drif3_ctrl_b_pins[] = {
1853 /* CLK, SYNC */
1854 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1855 };
1856 static const unsigned int drif3_ctrl_b_mux[] = {
1857 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1858 };
1859 static const unsigned int drif3_data0_b_pins[] = {
1860 /* D0 */
1861 RCAR_GP_PIN(6, 28),
1862 };
1863 static const unsigned int drif3_data0_b_mux[] = {
1864 RIF3_D0_B_MARK,
1865 };
1866 static const unsigned int drif3_data1_b_pins[] = {
1867 /* D1 */
1868 RCAR_GP_PIN(6, 29),
1869 };
1870 static const unsigned int drif3_data1_b_mux[] = {
1871 RIF3_D1_B_MARK,
1872 };
1873
1874 /* - HSCIF0 ----------------------------------------------------------------- */
1875 static const unsigned int hscif0_data_pins[] = {
1876 /* RX, TX */
1877 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1878 };
1879 static const unsigned int hscif0_data_mux[] = {
1880 HRX0_MARK, HTX0_MARK,
1881 };
1882 static const unsigned int hscif0_clk_pins[] = {
1883 /* SCK */
1884 RCAR_GP_PIN(5, 12),
1885 };
1886 static const unsigned int hscif0_clk_mux[] = {
1887 HSCK0_MARK,
1888 };
1889 static const unsigned int hscif0_ctrl_pins[] = {
1890 /* RTS, CTS */
1891 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
1892 };
1893 static const unsigned int hscif0_ctrl_mux[] = {
1894 HRTS0_N_MARK, HCTS0_N_MARK,
1895 };
1896 /* - HSCIF1 ----------------------------------------------------------------- */
1897 static const unsigned int hscif1_data_a_pins[] = {
1898 /* RX, TX */
1899 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1900 };
1901 static const unsigned int hscif1_data_a_mux[] = {
1902 HRX1_A_MARK, HTX1_A_MARK,
1903 };
1904 static const unsigned int hscif1_clk_a_pins[] = {
1905 /* SCK */
1906 RCAR_GP_PIN(6, 21),
1907 };
1908 static const unsigned int hscif1_clk_a_mux[] = {
1909 HSCK1_A_MARK,
1910 };
1911 static const unsigned int hscif1_ctrl_a_pins[] = {
1912 /* RTS, CTS */
1913 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
1914 };
1915 static const unsigned int hscif1_ctrl_a_mux[] = {
1916 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
1917 };
1918
1919 static const unsigned int hscif1_data_b_pins[] = {
1920 /* RX, TX */
1921 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1922 };
1923 static const unsigned int hscif1_data_b_mux[] = {
1924 HRX1_B_MARK, HTX1_B_MARK,
1925 };
1926 static const unsigned int hscif1_clk_b_pins[] = {
1927 /* SCK */
1928 RCAR_GP_PIN(5, 0),
1929 };
1930 static const unsigned int hscif1_clk_b_mux[] = {
1931 HSCK1_B_MARK,
1932 };
1933 static const unsigned int hscif1_ctrl_b_pins[] = {
1934 /* RTS, CTS */
1935 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
1936 };
1937 static const unsigned int hscif1_ctrl_b_mux[] = {
1938 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1939 };
1940 /* - HSCIF2 ----------------------------------------------------------------- */
1941 static const unsigned int hscif2_data_a_pins[] = {
1942 /* RX, TX */
1943 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1944 };
1945 static const unsigned int hscif2_data_a_mux[] = {
1946 HRX2_A_MARK, HTX2_A_MARK,
1947 };
1948 static const unsigned int hscif2_clk_a_pins[] = {
1949 /* SCK */
1950 RCAR_GP_PIN(6, 10),
1951 };
1952 static const unsigned int hscif2_clk_a_mux[] = {
1953 HSCK2_A_MARK,
1954 };
1955 static const unsigned int hscif2_ctrl_a_pins[] = {
1956 /* RTS, CTS */
1957 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1958 };
1959 static const unsigned int hscif2_ctrl_a_mux[] = {
1960 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
1961 };
1962
1963 static const unsigned int hscif2_data_b_pins[] = {
1964 /* RX, TX */
1965 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1966 };
1967 static const unsigned int hscif2_data_b_mux[] = {
1968 HRX2_B_MARK, HTX2_B_MARK,
1969 };
1970 static const unsigned int hscif2_clk_b_pins[] = {
1971 /* SCK */
1972 RCAR_GP_PIN(6, 21),
1973 };
1974 static const unsigned int hscif2_clk_b_mux[] = {
1975 HSCK1_B_MARK,
1976 };
1977 static const unsigned int hscif2_ctrl_b_pins[] = {
1978 /* RTS, CTS */
1979 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
1980 };
1981 static const unsigned int hscif2_ctrl_b_mux[] = {
1982 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
1983 };
1984 /* - HSCIF3 ----------------------------------------------------------------- */
1985 static const unsigned int hscif3_data_a_pins[] = {
1986 /* RX, TX */
1987 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1988 };
1989 static const unsigned int hscif3_data_a_mux[] = {
1990 HRX3_A_MARK, HTX3_A_MARK,
1991 };
1992 static const unsigned int hscif3_clk_pins[] = {
1993 /* SCK */
1994 RCAR_GP_PIN(1, 22),
1995 };
1996 static const unsigned int hscif3_clk_mux[] = {
1997 HSCK3_MARK,
1998 };
1999 static const unsigned int hscif3_ctrl_pins[] = {
2000 /* RTS, CTS */
2001 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2002 };
2003 static const unsigned int hscif3_ctrl_mux[] = {
2004 HRTS3_N_MARK, HCTS3_N_MARK,
2005 };
2006
2007 static const unsigned int hscif3_data_b_pins[] = {
2008 /* RX, TX */
2009 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2010 };
2011 static const unsigned int hscif3_data_b_mux[] = {
2012 HRX3_B_MARK, HTX3_B_MARK,
2013 };
2014 static const unsigned int hscif3_data_c_pins[] = {
2015 /* RX, TX */
2016 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2017 };
2018 static const unsigned int hscif3_data_c_mux[] = {
2019 HRX3_C_MARK, HTX3_C_MARK,
2020 };
2021 static const unsigned int hscif3_data_d_pins[] = {
2022 /* RX, TX */
2023 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2024 };
2025 static const unsigned int hscif3_data_d_mux[] = {
2026 HRX3_D_MARK, HTX3_D_MARK,
2027 };
2028 /* - HSCIF4 ----------------------------------------------------------------- */
2029 static const unsigned int hscif4_data_a_pins[] = {
2030 /* RX, TX */
2031 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2032 };
2033 static const unsigned int hscif4_data_a_mux[] = {
2034 HRX4_A_MARK, HTX4_A_MARK,
2035 };
2036 static const unsigned int hscif4_clk_pins[] = {
2037 /* SCK */
2038 RCAR_GP_PIN(1, 11),
2039 };
2040 static const unsigned int hscif4_clk_mux[] = {
2041 HSCK4_MARK,
2042 };
2043 static const unsigned int hscif4_ctrl_pins[] = {
2044 /* RTS, CTS */
2045 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2046 };
2047 static const unsigned int hscif4_ctrl_mux[] = {
2048 HRTS4_N_MARK, HCTS3_N_MARK,
2049 };
2050
2051 static const unsigned int hscif4_data_b_pins[] = {
2052 /* RX, TX */
2053 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2054 };
2055 static const unsigned int hscif4_data_b_mux[] = {
2056 HRX4_B_MARK, HTX4_B_MARK,
2057 };
2058
2059 /* - I2C -------------------------------------------------------------------- */
2060 static const unsigned int i2c1_a_pins[] = {
2061 /* SDA, SCL */
2062 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2063 };
2064 static const unsigned int i2c1_a_mux[] = {
2065 SDA1_A_MARK, SCL1_A_MARK,
2066 };
2067 static const unsigned int i2c1_b_pins[] = {
2068 /* SDA, SCL */
2069 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2070 };
2071 static const unsigned int i2c1_b_mux[] = {
2072 SDA1_B_MARK, SCL1_B_MARK,
2073 };
2074 static const unsigned int i2c2_a_pins[] = {
2075 /* SDA, SCL */
2076 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2077 };
2078 static const unsigned int i2c2_a_mux[] = {
2079 SDA2_A_MARK, SCL2_A_MARK,
2080 };
2081 static const unsigned int i2c2_b_pins[] = {
2082 /* SDA, SCL */
2083 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2084 };
2085 static const unsigned int i2c2_b_mux[] = {
2086 SDA2_B_MARK, SCL2_B_MARK,
2087 };
2088 static const unsigned int i2c6_a_pins[] = {
2089 /* SDA, SCL */
2090 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2091 };
2092 static const unsigned int i2c6_a_mux[] = {
2093 SDA6_A_MARK, SCL6_A_MARK,
2094 };
2095 static const unsigned int i2c6_b_pins[] = {
2096 /* SDA, SCL */
2097 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2098 };
2099 static const unsigned int i2c6_b_mux[] = {
2100 SDA6_B_MARK, SCL6_B_MARK,
2101 };
2102 static const unsigned int i2c6_c_pins[] = {
2103 /* SDA, SCL */
2104 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2105 };
2106 static const unsigned int i2c6_c_mux[] = {
2107 SDA6_C_MARK, SCL6_C_MARK,
2108 };
2109
2110 /* - INTC-EX ---------------------------------------------------------------- */
2111 static const unsigned int intc_ex_irq0_pins[] = {
2112 /* IRQ0 */
2113 RCAR_GP_PIN(2, 0),
2114 };
2115 static const unsigned int intc_ex_irq0_mux[] = {
2116 IRQ0_MARK,
2117 };
2118 static const unsigned int intc_ex_irq1_pins[] = {
2119 /* IRQ1 */
2120 RCAR_GP_PIN(2, 1),
2121 };
2122 static const unsigned int intc_ex_irq1_mux[] = {
2123 IRQ1_MARK,
2124 };
2125 static const unsigned int intc_ex_irq2_pins[] = {
2126 /* IRQ2 */
2127 RCAR_GP_PIN(2, 2),
2128 };
2129 static const unsigned int intc_ex_irq2_mux[] = {
2130 IRQ2_MARK,
2131 };
2132 static const unsigned int intc_ex_irq3_pins[] = {
2133 /* IRQ3 */
2134 RCAR_GP_PIN(2, 3),
2135 };
2136 static const unsigned int intc_ex_irq3_mux[] = {
2137 IRQ3_MARK,
2138 };
2139 static const unsigned int intc_ex_irq4_pins[] = {
2140 /* IRQ4 */
2141 RCAR_GP_PIN(2, 4),
2142 };
2143 static const unsigned int intc_ex_irq4_mux[] = {
2144 IRQ4_MARK,
2145 };
2146 static const unsigned int intc_ex_irq5_pins[] = {
2147 /* IRQ5 */
2148 RCAR_GP_PIN(2, 5),
2149 };
2150 static const unsigned int intc_ex_irq5_mux[] = {
2151 IRQ5_MARK,
2152 };
2153
2154 /* - MSIOF0 ----------------------------------------------------------------- */
2155 static const unsigned int msiof0_clk_pins[] = {
2156 /* SCK */
2157 RCAR_GP_PIN(5, 17),
2158 };
2159 static const unsigned int msiof0_clk_mux[] = {
2160 MSIOF0_SCK_MARK,
2161 };
2162 static const unsigned int msiof0_sync_pins[] = {
2163 /* SYNC */
2164 RCAR_GP_PIN(5, 18),
2165 };
2166 static const unsigned int msiof0_sync_mux[] = {
2167 MSIOF0_SYNC_MARK,
2168 };
2169 static const unsigned int msiof0_ss1_pins[] = {
2170 /* SS1 */
2171 RCAR_GP_PIN(5, 19),
2172 };
2173 static const unsigned int msiof0_ss1_mux[] = {
2174 MSIOF0_SS1_MARK,
2175 };
2176 static const unsigned int msiof0_ss2_pins[] = {
2177 /* SS2 */
2178 RCAR_GP_PIN(5, 21),
2179 };
2180 static const unsigned int msiof0_ss2_mux[] = {
2181 MSIOF0_SS2_MARK,
2182 };
2183 static const unsigned int msiof0_txd_pins[] = {
2184 /* TXD */
2185 RCAR_GP_PIN(5, 20),
2186 };
2187 static const unsigned int msiof0_txd_mux[] = {
2188 MSIOF0_TXD_MARK,
2189 };
2190 static const unsigned int msiof0_rxd_pins[] = {
2191 /* RXD */
2192 RCAR_GP_PIN(5, 22),
2193 };
2194 static const unsigned int msiof0_rxd_mux[] = {
2195 MSIOF0_RXD_MARK,
2196 };
2197 /* - MSIOF1 ----------------------------------------------------------------- */
2198 static const unsigned int msiof1_clk_a_pins[] = {
2199 /* SCK */
2200 RCAR_GP_PIN(6, 8),
2201 };
2202 static const unsigned int msiof1_clk_a_mux[] = {
2203 MSIOF1_SCK_A_MARK,
2204 };
2205 static const unsigned int msiof1_sync_a_pins[] = {
2206 /* SYNC */
2207 RCAR_GP_PIN(6, 9),
2208 };
2209 static const unsigned int msiof1_sync_a_mux[] = {
2210 MSIOF1_SYNC_A_MARK,
2211 };
2212 static const unsigned int msiof1_ss1_a_pins[] = {
2213 /* SS1 */
2214 RCAR_GP_PIN(6, 5),
2215 };
2216 static const unsigned int msiof1_ss1_a_mux[] = {
2217 MSIOF1_SS1_A_MARK,
2218 };
2219 static const unsigned int msiof1_ss2_a_pins[] = {
2220 /* SS2 */
2221 RCAR_GP_PIN(6, 6),
2222 };
2223 static const unsigned int msiof1_ss2_a_mux[] = {
2224 MSIOF1_SS2_A_MARK,
2225 };
2226 static const unsigned int msiof1_txd_a_pins[] = {
2227 /* TXD */
2228 RCAR_GP_PIN(6, 7),
2229 };
2230 static const unsigned int msiof1_txd_a_mux[] = {
2231 MSIOF1_TXD_A_MARK,
2232 };
2233 static const unsigned int msiof1_rxd_a_pins[] = {
2234 /* RXD */
2235 RCAR_GP_PIN(6, 10),
2236 };
2237 static const unsigned int msiof1_rxd_a_mux[] = {
2238 MSIOF1_RXD_A_MARK,
2239 };
2240 static const unsigned int msiof1_clk_b_pins[] = {
2241 /* SCK */
2242 RCAR_GP_PIN(5, 9),
2243 };
2244 static const unsigned int msiof1_clk_b_mux[] = {
2245 MSIOF1_SCK_B_MARK,
2246 };
2247 static const unsigned int msiof1_sync_b_pins[] = {
2248 /* SYNC */
2249 RCAR_GP_PIN(5, 3),
2250 };
2251 static const unsigned int msiof1_sync_b_mux[] = {
2252 MSIOF1_SYNC_B_MARK,
2253 };
2254 static const unsigned int msiof1_ss1_b_pins[] = {
2255 /* SS1 */
2256 RCAR_GP_PIN(5, 4),
2257 };
2258 static const unsigned int msiof1_ss1_b_mux[] = {
2259 MSIOF1_SS1_B_MARK,
2260 };
2261 static const unsigned int msiof1_ss2_b_pins[] = {
2262 /* SS2 */
2263 RCAR_GP_PIN(5, 0),
2264 };
2265 static const unsigned int msiof1_ss2_b_mux[] = {
2266 MSIOF1_SS2_B_MARK,
2267 };
2268 static const unsigned int msiof1_txd_b_pins[] = {
2269 /* TXD */
2270 RCAR_GP_PIN(5, 8),
2271 };
2272 static const unsigned int msiof1_txd_b_mux[] = {
2273 MSIOF1_TXD_B_MARK,
2274 };
2275 static const unsigned int msiof1_rxd_b_pins[] = {
2276 /* RXD */
2277 RCAR_GP_PIN(5, 7),
2278 };
2279 static const unsigned int msiof1_rxd_b_mux[] = {
2280 MSIOF1_RXD_B_MARK,
2281 };
2282 static const unsigned int msiof1_clk_c_pins[] = {
2283 /* SCK */
2284 RCAR_GP_PIN(6, 17),
2285 };
2286 static const unsigned int msiof1_clk_c_mux[] = {
2287 MSIOF1_SCK_C_MARK,
2288 };
2289 static const unsigned int msiof1_sync_c_pins[] = {
2290 /* SYNC */
2291 RCAR_GP_PIN(6, 18),
2292 };
2293 static const unsigned int msiof1_sync_c_mux[] = {
2294 MSIOF1_SYNC_C_MARK,
2295 };
2296 static const unsigned int msiof1_ss1_c_pins[] = {
2297 /* SS1 */
2298 RCAR_GP_PIN(6, 21),
2299 };
2300 static const unsigned int msiof1_ss1_c_mux[] = {
2301 MSIOF1_SS1_C_MARK,
2302 };
2303 static const unsigned int msiof1_ss2_c_pins[] = {
2304 /* SS2 */
2305 RCAR_GP_PIN(6, 27),
2306 };
2307 static const unsigned int msiof1_ss2_c_mux[] = {
2308 MSIOF1_SS2_C_MARK,
2309 };
2310 static const unsigned int msiof1_txd_c_pins[] = {
2311 /* TXD */
2312 RCAR_GP_PIN(6, 20),
2313 };
2314 static const unsigned int msiof1_txd_c_mux[] = {
2315 MSIOF1_TXD_C_MARK,
2316 };
2317 static const unsigned int msiof1_rxd_c_pins[] = {
2318 /* RXD */
2319 RCAR_GP_PIN(6, 19),
2320 };
2321 static const unsigned int msiof1_rxd_c_mux[] = {
2322 MSIOF1_RXD_C_MARK,
2323 };
2324 static const unsigned int msiof1_clk_d_pins[] = {
2325 /* SCK */
2326 RCAR_GP_PIN(5, 12),
2327 };
2328 static const unsigned int msiof1_clk_d_mux[] = {
2329 MSIOF1_SCK_D_MARK,
2330 };
2331 static const unsigned int msiof1_sync_d_pins[] = {
2332 /* SYNC */
2333 RCAR_GP_PIN(5, 15),
2334 };
2335 static const unsigned int msiof1_sync_d_mux[] = {
2336 MSIOF1_SYNC_D_MARK,
2337 };
2338 static const unsigned int msiof1_ss1_d_pins[] = {
2339 /* SS1 */
2340 RCAR_GP_PIN(5, 16),
2341 };
2342 static const unsigned int msiof1_ss1_d_mux[] = {
2343 MSIOF1_SS1_D_MARK,
2344 };
2345 static const unsigned int msiof1_ss2_d_pins[] = {
2346 /* SS2 */
2347 RCAR_GP_PIN(5, 21),
2348 };
2349 static const unsigned int msiof1_ss2_d_mux[] = {
2350 MSIOF1_SS2_D_MARK,
2351 };
2352 static const unsigned int msiof1_txd_d_pins[] = {
2353 /* TXD */
2354 RCAR_GP_PIN(5, 14),
2355 };
2356 static const unsigned int msiof1_txd_d_mux[] = {
2357 MSIOF1_TXD_D_MARK,
2358 };
2359 static const unsigned int msiof1_rxd_d_pins[] = {
2360 /* RXD */
2361 RCAR_GP_PIN(5, 13),
2362 };
2363 static const unsigned int msiof1_rxd_d_mux[] = {
2364 MSIOF1_RXD_D_MARK,
2365 };
2366 static const unsigned int msiof1_clk_e_pins[] = {
2367 /* SCK */
2368 RCAR_GP_PIN(3, 0),
2369 };
2370 static const unsigned int msiof1_clk_e_mux[] = {
2371 MSIOF1_SCK_E_MARK,
2372 };
2373 static const unsigned int msiof1_sync_e_pins[] = {
2374 /* SYNC */
2375 RCAR_GP_PIN(3, 1),
2376 };
2377 static const unsigned int msiof1_sync_e_mux[] = {
2378 MSIOF1_SYNC_E_MARK,
2379 };
2380 static const unsigned int msiof1_ss1_e_pins[] = {
2381 /* SS1 */
2382 RCAR_GP_PIN(3, 4),
2383 };
2384 static const unsigned int msiof1_ss1_e_mux[] = {
2385 MSIOF1_SS1_E_MARK,
2386 };
2387 static const unsigned int msiof1_ss2_e_pins[] = {
2388 /* SS2 */
2389 RCAR_GP_PIN(3, 5),
2390 };
2391 static const unsigned int msiof1_ss2_e_mux[] = {
2392 MSIOF1_SS2_E_MARK,
2393 };
2394 static const unsigned int msiof1_txd_e_pins[] = {
2395 /* TXD */
2396 RCAR_GP_PIN(3, 3),
2397 };
2398 static const unsigned int msiof1_txd_e_mux[] = {
2399 MSIOF1_TXD_E_MARK,
2400 };
2401 static const unsigned int msiof1_rxd_e_pins[] = {
2402 /* RXD */
2403 RCAR_GP_PIN(3, 2),
2404 };
2405 static const unsigned int msiof1_rxd_e_mux[] = {
2406 MSIOF1_RXD_E_MARK,
2407 };
2408 static const unsigned int msiof1_clk_f_pins[] = {
2409 /* SCK */
2410 RCAR_GP_PIN(5, 23),
2411 };
2412 static const unsigned int msiof1_clk_f_mux[] = {
2413 MSIOF1_SCK_F_MARK,
2414 };
2415 static const unsigned int msiof1_sync_f_pins[] = {
2416 /* SYNC */
2417 RCAR_GP_PIN(5, 24),
2418 };
2419 static const unsigned int msiof1_sync_f_mux[] = {
2420 MSIOF1_SYNC_F_MARK,
2421 };
2422 static const unsigned int msiof1_ss1_f_pins[] = {
2423 /* SS1 */
2424 RCAR_GP_PIN(6, 1),
2425 };
2426 static const unsigned int msiof1_ss1_f_mux[] = {
2427 MSIOF1_SS1_F_MARK,
2428 };
2429 static const unsigned int msiof1_ss2_f_pins[] = {
2430 /* SS2 */
2431 RCAR_GP_PIN(6, 2),
2432 };
2433 static const unsigned int msiof1_ss2_f_mux[] = {
2434 MSIOF1_SS2_F_MARK,
2435 };
2436 static const unsigned int msiof1_txd_f_pins[] = {
2437 /* TXD */
2438 RCAR_GP_PIN(6, 0),
2439 };
2440 static const unsigned int msiof1_txd_f_mux[] = {
2441 MSIOF1_TXD_F_MARK,
2442 };
2443 static const unsigned int msiof1_rxd_f_pins[] = {
2444 /* RXD */
2445 RCAR_GP_PIN(5, 25),
2446 };
2447 static const unsigned int msiof1_rxd_f_mux[] = {
2448 MSIOF1_RXD_F_MARK,
2449 };
2450 static const unsigned int msiof1_clk_g_pins[] = {
2451 /* SCK */
2452 RCAR_GP_PIN(3, 6),
2453 };
2454 static const unsigned int msiof1_clk_g_mux[] = {
2455 MSIOF1_SCK_G_MARK,
2456 };
2457 static const unsigned int msiof1_sync_g_pins[] = {
2458 /* SYNC */
2459 RCAR_GP_PIN(3, 7),
2460 };
2461 static const unsigned int msiof1_sync_g_mux[] = {
2462 MSIOF1_SYNC_G_MARK,
2463 };
2464 static const unsigned int msiof1_ss1_g_pins[] = {
2465 /* SS1 */
2466 RCAR_GP_PIN(3, 10),
2467 };
2468 static const unsigned int msiof1_ss1_g_mux[] = {
2469 MSIOF1_SS1_G_MARK,
2470 };
2471 static const unsigned int msiof1_ss2_g_pins[] = {
2472 /* SS2 */
2473 RCAR_GP_PIN(3, 11),
2474 };
2475 static const unsigned int msiof1_ss2_g_mux[] = {
2476 MSIOF1_SS2_G_MARK,
2477 };
2478 static const unsigned int msiof1_txd_g_pins[] = {
2479 /* TXD */
2480 RCAR_GP_PIN(3, 9),
2481 };
2482 static const unsigned int msiof1_txd_g_mux[] = {
2483 MSIOF1_TXD_G_MARK,
2484 };
2485 static const unsigned int msiof1_rxd_g_pins[] = {
2486 /* RXD */
2487 RCAR_GP_PIN(3, 8),
2488 };
2489 static const unsigned int msiof1_rxd_g_mux[] = {
2490 MSIOF1_RXD_G_MARK,
2491 };
2492 /* - MSIOF2 ----------------------------------------------------------------- */
2493 static const unsigned int msiof2_clk_a_pins[] = {
2494 /* SCK */
2495 RCAR_GP_PIN(1, 9),
2496 };
2497 static const unsigned int msiof2_clk_a_mux[] = {
2498 MSIOF2_SCK_A_MARK,
2499 };
2500 static const unsigned int msiof2_sync_a_pins[] = {
2501 /* SYNC */
2502 RCAR_GP_PIN(1, 8),
2503 };
2504 static const unsigned int msiof2_sync_a_mux[] = {
2505 MSIOF2_SYNC_A_MARK,
2506 };
2507 static const unsigned int msiof2_ss1_a_pins[] = {
2508 /* SS1 */
2509 RCAR_GP_PIN(1, 6),
2510 };
2511 static const unsigned int msiof2_ss1_a_mux[] = {
2512 MSIOF2_SS1_A_MARK,
2513 };
2514 static const unsigned int msiof2_ss2_a_pins[] = {
2515 /* SS2 */
2516 RCAR_GP_PIN(1, 7),
2517 };
2518 static const unsigned int msiof2_ss2_a_mux[] = {
2519 MSIOF2_SS2_A_MARK,
2520 };
2521 static const unsigned int msiof2_txd_a_pins[] = {
2522 /* TXD */
2523 RCAR_GP_PIN(1, 11),
2524 };
2525 static const unsigned int msiof2_txd_a_mux[] = {
2526 MSIOF2_TXD_A_MARK,
2527 };
2528 static const unsigned int msiof2_rxd_a_pins[] = {
2529 /* RXD */
2530 RCAR_GP_PIN(1, 10),
2531 };
2532 static const unsigned int msiof2_rxd_a_mux[] = {
2533 MSIOF2_RXD_A_MARK,
2534 };
2535 static const unsigned int msiof2_clk_b_pins[] = {
2536 /* SCK */
2537 RCAR_GP_PIN(0, 4),
2538 };
2539 static const unsigned int msiof2_clk_b_mux[] = {
2540 MSIOF2_SCK_B_MARK,
2541 };
2542 static const unsigned int msiof2_sync_b_pins[] = {
2543 /* SYNC */
2544 RCAR_GP_PIN(0, 5),
2545 };
2546 static const unsigned int msiof2_sync_b_mux[] = {
2547 MSIOF2_SYNC_B_MARK,
2548 };
2549 static const unsigned int msiof2_ss1_b_pins[] = {
2550 /* SS1 */
2551 RCAR_GP_PIN(0, 0),
2552 };
2553 static const unsigned int msiof2_ss1_b_mux[] = {
2554 MSIOF2_SS1_B_MARK,
2555 };
2556 static const unsigned int msiof2_ss2_b_pins[] = {
2557 /* SS2 */
2558 RCAR_GP_PIN(0, 1),
2559 };
2560 static const unsigned int msiof2_ss2_b_mux[] = {
2561 MSIOF2_SS2_B_MARK,
2562 };
2563 static const unsigned int msiof2_txd_b_pins[] = {
2564 /* TXD */
2565 RCAR_GP_PIN(0, 7),
2566 };
2567 static const unsigned int msiof2_txd_b_mux[] = {
2568 MSIOF2_TXD_B_MARK,
2569 };
2570 static const unsigned int msiof2_rxd_b_pins[] = {
2571 /* RXD */
2572 RCAR_GP_PIN(0, 6),
2573 };
2574 static const unsigned int msiof2_rxd_b_mux[] = {
2575 MSIOF2_RXD_B_MARK,
2576 };
2577 static const unsigned int msiof2_clk_c_pins[] = {
2578 /* SCK */
2579 RCAR_GP_PIN(2, 12),
2580 };
2581 static const unsigned int msiof2_clk_c_mux[] = {
2582 MSIOF2_SCK_C_MARK,
2583 };
2584 static const unsigned int msiof2_sync_c_pins[] = {
2585 /* SYNC */
2586 RCAR_GP_PIN(2, 11),
2587 };
2588 static const unsigned int msiof2_sync_c_mux[] = {
2589 MSIOF2_SYNC_C_MARK,
2590 };
2591 static const unsigned int msiof2_ss1_c_pins[] = {
2592 /* SS1 */
2593 RCAR_GP_PIN(2, 10),
2594 };
2595 static const unsigned int msiof2_ss1_c_mux[] = {
2596 MSIOF2_SS1_C_MARK,
2597 };
2598 static const unsigned int msiof2_ss2_c_pins[] = {
2599 /* SS2 */
2600 RCAR_GP_PIN(2, 9),
2601 };
2602 static const unsigned int msiof2_ss2_c_mux[] = {
2603 MSIOF2_SS2_C_MARK,
2604 };
2605 static const unsigned int msiof2_txd_c_pins[] = {
2606 /* TXD */
2607 RCAR_GP_PIN(2, 14),
2608 };
2609 static const unsigned int msiof2_txd_c_mux[] = {
2610 MSIOF2_TXD_C_MARK,
2611 };
2612 static const unsigned int msiof2_rxd_c_pins[] = {
2613 /* RXD */
2614 RCAR_GP_PIN(2, 13),
2615 };
2616 static const unsigned int msiof2_rxd_c_mux[] = {
2617 MSIOF2_RXD_C_MARK,
2618 };
2619 static const unsigned int msiof2_clk_d_pins[] = {
2620 /* SCK */
2621 RCAR_GP_PIN(0, 8),
2622 };
2623 static const unsigned int msiof2_clk_d_mux[] = {
2624 MSIOF2_SCK_D_MARK,
2625 };
2626 static const unsigned int msiof2_sync_d_pins[] = {
2627 /* SYNC */
2628 RCAR_GP_PIN(0, 9),
2629 };
2630 static const unsigned int msiof2_sync_d_mux[] = {
2631 MSIOF2_SYNC_D_MARK,
2632 };
2633 static const unsigned int msiof2_ss1_d_pins[] = {
2634 /* SS1 */
2635 RCAR_GP_PIN(0, 12),
2636 };
2637 static const unsigned int msiof2_ss1_d_mux[] = {
2638 MSIOF2_SS1_D_MARK,
2639 };
2640 static const unsigned int msiof2_ss2_d_pins[] = {
2641 /* SS2 */
2642 RCAR_GP_PIN(0, 13),
2643 };
2644 static const unsigned int msiof2_ss2_d_mux[] = {
2645 MSIOF2_SS2_D_MARK,
2646 };
2647 static const unsigned int msiof2_txd_d_pins[] = {
2648 /* TXD */
2649 RCAR_GP_PIN(0, 11),
2650 };
2651 static const unsigned int msiof2_txd_d_mux[] = {
2652 MSIOF2_TXD_D_MARK,
2653 };
2654 static const unsigned int msiof2_rxd_d_pins[] = {
2655 /* RXD */
2656 RCAR_GP_PIN(0, 10),
2657 };
2658 static const unsigned int msiof2_rxd_d_mux[] = {
2659 MSIOF2_RXD_D_MARK,
2660 };
2661 /* - MSIOF3 ----------------------------------------------------------------- */
2662 static const unsigned int msiof3_clk_a_pins[] = {
2663 /* SCK */
2664 RCAR_GP_PIN(0, 0),
2665 };
2666 static const unsigned int msiof3_clk_a_mux[] = {
2667 MSIOF3_SCK_A_MARK,
2668 };
2669 static const unsigned int msiof3_sync_a_pins[] = {
2670 /* SYNC */
2671 RCAR_GP_PIN(0, 1),
2672 };
2673 static const unsigned int msiof3_sync_a_mux[] = {
2674 MSIOF3_SYNC_A_MARK,
2675 };
2676 static const unsigned int msiof3_ss1_a_pins[] = {
2677 /* SS1 */
2678 RCAR_GP_PIN(0, 14),
2679 };
2680 static const unsigned int msiof3_ss1_a_mux[] = {
2681 MSIOF3_SS1_A_MARK,
2682 };
2683 static const unsigned int msiof3_ss2_a_pins[] = {
2684 /* SS2 */
2685 RCAR_GP_PIN(0, 15),
2686 };
2687 static const unsigned int msiof3_ss2_a_mux[] = {
2688 MSIOF3_SS2_A_MARK,
2689 };
2690 static const unsigned int msiof3_txd_a_pins[] = {
2691 /* TXD */
2692 RCAR_GP_PIN(0, 3),
2693 };
2694 static const unsigned int msiof3_txd_a_mux[] = {
2695 MSIOF3_TXD_A_MARK,
2696 };
2697 static const unsigned int msiof3_rxd_a_pins[] = {
2698 /* RXD */
2699 RCAR_GP_PIN(0, 2),
2700 };
2701 static const unsigned int msiof3_rxd_a_mux[] = {
2702 MSIOF3_RXD_A_MARK,
2703 };
2704 static const unsigned int msiof3_clk_b_pins[] = {
2705 /* SCK */
2706 RCAR_GP_PIN(1, 2),
2707 };
2708 static const unsigned int msiof3_clk_b_mux[] = {
2709 MSIOF3_SCK_B_MARK,
2710 };
2711 static const unsigned int msiof3_sync_b_pins[] = {
2712 /* SYNC */
2713 RCAR_GP_PIN(1, 0),
2714 };
2715 static const unsigned int msiof3_sync_b_mux[] = {
2716 MSIOF3_SYNC_B_MARK,
2717 };
2718 static const unsigned int msiof3_ss1_b_pins[] = {
2719 /* SS1 */
2720 RCAR_GP_PIN(1, 4),
2721 };
2722 static const unsigned int msiof3_ss1_b_mux[] = {
2723 MSIOF3_SS1_B_MARK,
2724 };
2725 static const unsigned int msiof3_ss2_b_pins[] = {
2726 /* SS2 */
2727 RCAR_GP_PIN(1, 5),
2728 };
2729 static const unsigned int msiof3_ss2_b_mux[] = {
2730 MSIOF3_SS2_B_MARK,
2731 };
2732 static const unsigned int msiof3_txd_b_pins[] = {
2733 /* TXD */
2734 RCAR_GP_PIN(1, 1),
2735 };
2736 static const unsigned int msiof3_txd_b_mux[] = {
2737 MSIOF3_TXD_B_MARK,
2738 };
2739 static const unsigned int msiof3_rxd_b_pins[] = {
2740 /* RXD */
2741 RCAR_GP_PIN(1, 3),
2742 };
2743 static const unsigned int msiof3_rxd_b_mux[] = {
2744 MSIOF3_RXD_B_MARK,
2745 };
2746 static const unsigned int msiof3_clk_c_pins[] = {
2747 /* SCK */
2748 RCAR_GP_PIN(1, 12),
2749 };
2750 static const unsigned int msiof3_clk_c_mux[] = {
2751 MSIOF3_SCK_C_MARK,
2752 };
2753 static const unsigned int msiof3_sync_c_pins[] = {
2754 /* SYNC */
2755 RCAR_GP_PIN(1, 13),
2756 };
2757 static const unsigned int msiof3_sync_c_mux[] = {
2758 MSIOF3_SYNC_C_MARK,
2759 };
2760 static const unsigned int msiof3_txd_c_pins[] = {
2761 /* TXD */
2762 RCAR_GP_PIN(1, 15),
2763 };
2764 static const unsigned int msiof3_txd_c_mux[] = {
2765 MSIOF3_TXD_C_MARK,
2766 };
2767 static const unsigned int msiof3_rxd_c_pins[] = {
2768 /* RXD */
2769 RCAR_GP_PIN(1, 14),
2770 };
2771 static const unsigned int msiof3_rxd_c_mux[] = {
2772 MSIOF3_RXD_C_MARK,
2773 };
2774 static const unsigned int msiof3_clk_d_pins[] = {
2775 /* SCK */
2776 RCAR_GP_PIN(1, 22),
2777 };
2778 static const unsigned int msiof3_clk_d_mux[] = {
2779 MSIOF3_SCK_D_MARK,
2780 };
2781 static const unsigned int msiof3_sync_d_pins[] = {
2782 /* SYNC */
2783 RCAR_GP_PIN(1, 23),
2784 };
2785 static const unsigned int msiof3_sync_d_mux[] = {
2786 MSIOF3_SYNC_D_MARK,
2787 };
2788 static const unsigned int msiof3_ss1_d_pins[] = {
2789 /* SS1 */
2790 RCAR_GP_PIN(1, 26),
2791 };
2792 static const unsigned int msiof3_ss1_d_mux[] = {
2793 MSIOF3_SS1_D_MARK,
2794 };
2795 static const unsigned int msiof3_txd_d_pins[] = {
2796 /* TXD */
2797 RCAR_GP_PIN(1, 25),
2798 };
2799 static const unsigned int msiof3_txd_d_mux[] = {
2800 MSIOF3_TXD_D_MARK,
2801 };
2802 static const unsigned int msiof3_rxd_d_pins[] = {
2803 /* RXD */
2804 RCAR_GP_PIN(1, 24),
2805 };
2806 static const unsigned int msiof3_rxd_d_mux[] = {
2807 MSIOF3_RXD_D_MARK,
2808 };
2809
2810 /* - PWM0 --------------------------------------------------------------------*/
2811 static const unsigned int pwm0_pins[] = {
2812 /* PWM */
2813 RCAR_GP_PIN(2, 6),
2814 };
2815 static const unsigned int pwm0_mux[] = {
2816 PWM0_MARK,
2817 };
2818 /* - PWM1 --------------------------------------------------------------------*/
2819 static const unsigned int pwm1_a_pins[] = {
2820 /* PWM */
2821 RCAR_GP_PIN(2, 7),
2822 };
2823 static const unsigned int pwm1_a_mux[] = {
2824 PWM1_A_MARK,
2825 };
2826 static const unsigned int pwm1_b_pins[] = {
2827 /* PWM */
2828 RCAR_GP_PIN(1, 8),
2829 };
2830 static const unsigned int pwm1_b_mux[] = {
2831 PWM1_B_MARK,
2832 };
2833 /* - PWM2 --------------------------------------------------------------------*/
2834 static const unsigned int pwm2_a_pins[] = {
2835 /* PWM */
2836 RCAR_GP_PIN(2, 8),
2837 };
2838 static const unsigned int pwm2_a_mux[] = {
2839 PWM2_A_MARK,
2840 };
2841 static const unsigned int pwm2_b_pins[] = {
2842 /* PWM */
2843 RCAR_GP_PIN(1, 11),
2844 };
2845 static const unsigned int pwm2_b_mux[] = {
2846 PWM2_B_MARK,
2847 };
2848 /* - PWM3 --------------------------------------------------------------------*/
2849 static const unsigned int pwm3_a_pins[] = {
2850 /* PWM */
2851 RCAR_GP_PIN(1, 0),
2852 };
2853 static const unsigned int pwm3_a_mux[] = {
2854 PWM3_A_MARK,
2855 };
2856 static const unsigned int pwm3_b_pins[] = {
2857 /* PWM */
2858 RCAR_GP_PIN(2, 2),
2859 };
2860 static const unsigned int pwm3_b_mux[] = {
2861 PWM3_B_MARK,
2862 };
2863 /* - PWM4 --------------------------------------------------------------------*/
2864 static const unsigned int pwm4_a_pins[] = {
2865 /* PWM */
2866 RCAR_GP_PIN(1, 1),
2867 };
2868 static const unsigned int pwm4_a_mux[] = {
2869 PWM4_A_MARK,
2870 };
2871 static const unsigned int pwm4_b_pins[] = {
2872 /* PWM */
2873 RCAR_GP_PIN(2, 3),
2874 };
2875 static const unsigned int pwm4_b_mux[] = {
2876 PWM4_B_MARK,
2877 };
2878 /* - PWM5 --------------------------------------------------------------------*/
2879 static const unsigned int pwm5_a_pins[] = {
2880 /* PWM */
2881 RCAR_GP_PIN(1, 2),
2882 };
2883 static const unsigned int pwm5_a_mux[] = {
2884 PWM5_A_MARK,
2885 };
2886 static const unsigned int pwm5_b_pins[] = {
2887 /* PWM */
2888 RCAR_GP_PIN(2, 4),
2889 };
2890 static const unsigned int pwm5_b_mux[] = {
2891 PWM5_B_MARK,
2892 };
2893 /* - PWM6 --------------------------------------------------------------------*/
2894 static const unsigned int pwm6_a_pins[] = {
2895 /* PWM */
2896 RCAR_GP_PIN(1, 3),
2897 };
2898 static const unsigned int pwm6_a_mux[] = {
2899 PWM6_A_MARK,
2900 };
2901 static const unsigned int pwm6_b_pins[] = {
2902 /* PWM */
2903 RCAR_GP_PIN(2, 5),
2904 };
2905 static const unsigned int pwm6_b_mux[] = {
2906 PWM6_B_MARK,
2907 };
2908
2909 /* - SATA --------------------------------------------------------------------*/
2910 static const unsigned int sata0_devslp_a_pins[] = {
2911 /* DEVSLP */
2912 RCAR_GP_PIN(6, 16),
2913 };
2914 static const unsigned int sata0_devslp_a_mux[] = {
2915 SATA_DEVSLP_A_MARK,
2916 };
2917 static const unsigned int sata0_devslp_b_pins[] = {
2918 /* DEVSLP */
2919 RCAR_GP_PIN(4, 6),
2920 };
2921 static const unsigned int sata0_devslp_b_mux[] = {
2922 SATA_DEVSLP_B_MARK,
2923 };
2924
2925 /* - SCIF0 ------------------------------------------------------------------ */
2926 static const unsigned int scif0_data_pins[] = {
2927 /* RX, TX */
2928 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2929 };
2930 static const unsigned int scif0_data_mux[] = {
2931 RX0_MARK, TX0_MARK,
2932 };
2933 static const unsigned int scif0_clk_pins[] = {
2934 /* SCK */
2935 RCAR_GP_PIN(5, 0),
2936 };
2937 static const unsigned int scif0_clk_mux[] = {
2938 SCK0_MARK,
2939 };
2940 static const unsigned int scif0_ctrl_pins[] = {
2941 /* RTS, CTS */
2942 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2943 };
2944 static const unsigned int scif0_ctrl_mux[] = {
2945 RTS0_N_TANS_MARK, CTS0_N_MARK,
2946 };
2947 /* - SCIF1 ------------------------------------------------------------------ */
2948 static const unsigned int scif1_data_a_pins[] = {
2949 /* RX, TX */
2950 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2951 };
2952 static const unsigned int scif1_data_a_mux[] = {
2953 RX1_A_MARK, TX1_A_MARK,
2954 };
2955 static const unsigned int scif1_clk_pins[] = {
2956 /* SCK */
2957 RCAR_GP_PIN(6, 21),
2958 };
2959 static const unsigned int scif1_clk_mux[] = {
2960 SCK1_MARK,
2961 };
2962 static const unsigned int scif1_ctrl_pins[] = {
2963 /* RTS, CTS */
2964 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2965 };
2966 static const unsigned int scif1_ctrl_mux[] = {
2967 RTS1_N_TANS_MARK, CTS1_N_MARK,
2968 };
2969
2970 static const unsigned int scif1_data_b_pins[] = {
2971 /* RX, TX */
2972 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2973 };
2974 static const unsigned int scif1_data_b_mux[] = {
2975 RX1_B_MARK, TX1_B_MARK,
2976 };
2977 /* - SCIF2 ------------------------------------------------------------------ */
2978 static const unsigned int scif2_data_a_pins[] = {
2979 /* RX, TX */
2980 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2981 };
2982 static const unsigned int scif2_data_a_mux[] = {
2983 RX2_A_MARK, TX2_A_MARK,
2984 };
2985 static const unsigned int scif2_clk_pins[] = {
2986 /* SCK */
2987 RCAR_GP_PIN(5, 9),
2988 };
2989 static const unsigned int scif2_clk_mux[] = {
2990 SCK2_MARK,
2991 };
2992 static const unsigned int scif2_data_b_pins[] = {
2993 /* RX, TX */
2994 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2995 };
2996 static const unsigned int scif2_data_b_mux[] = {
2997 RX2_B_MARK, TX2_B_MARK,
2998 };
2999 /* - SCIF3 ------------------------------------------------------------------ */
3000 static const unsigned int scif3_data_a_pins[] = {
3001 /* RX, TX */
3002 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3003 };
3004 static const unsigned int scif3_data_a_mux[] = {
3005 RX3_A_MARK, TX3_A_MARK,
3006 };
3007 static const unsigned int scif3_clk_pins[] = {
3008 /* SCK */
3009 RCAR_GP_PIN(1, 22),
3010 };
3011 static const unsigned int scif3_clk_mux[] = {
3012 SCK3_MARK,
3013 };
3014 static const unsigned int scif3_ctrl_pins[] = {
3015 /* RTS, CTS */
3016 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3017 };
3018 static const unsigned int scif3_ctrl_mux[] = {
3019 RTS3_N_TANS_MARK, CTS3_N_MARK,
3020 };
3021 static const unsigned int scif3_data_b_pins[] = {
3022 /* RX, TX */
3023 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3024 };
3025 static const unsigned int scif3_data_b_mux[] = {
3026 RX3_B_MARK, TX3_B_MARK,
3027 };
3028 /* - SCIF4 ------------------------------------------------------------------ */
3029 static const unsigned int scif4_data_a_pins[] = {
3030 /* RX, TX */
3031 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3032 };
3033 static const unsigned int scif4_data_a_mux[] = {
3034 RX4_A_MARK, TX4_A_MARK,
3035 };
3036 static const unsigned int scif4_clk_a_pins[] = {
3037 /* SCK */
3038 RCAR_GP_PIN(2, 10),
3039 };
3040 static const unsigned int scif4_clk_a_mux[] = {
3041 SCK4_A_MARK,
3042 };
3043 static const unsigned int scif4_ctrl_a_pins[] = {
3044 /* RTS, CTS */
3045 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3046 };
3047 static const unsigned int scif4_ctrl_a_mux[] = {
3048 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
3049 };
3050 static const unsigned int scif4_data_b_pins[] = {
3051 /* RX, TX */
3052 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3053 };
3054 static const unsigned int scif4_data_b_mux[] = {
3055 RX4_B_MARK, TX4_B_MARK,
3056 };
3057 static const unsigned int scif4_clk_b_pins[] = {
3058 /* SCK */
3059 RCAR_GP_PIN(1, 5),
3060 };
3061 static const unsigned int scif4_clk_b_mux[] = {
3062 SCK4_B_MARK,
3063 };
3064 static const unsigned int scif4_ctrl_b_pins[] = {
3065 /* RTS, CTS */
3066 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3067 };
3068 static const unsigned int scif4_ctrl_b_mux[] = {
3069 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
3070 };
3071 static const unsigned int scif4_data_c_pins[] = {
3072 /* RX, TX */
3073 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3074 };
3075 static const unsigned int scif4_data_c_mux[] = {
3076 RX4_C_MARK, TX4_C_MARK,
3077 };
3078 static const unsigned int scif4_clk_c_pins[] = {
3079 /* SCK */
3080 RCAR_GP_PIN(0, 8),
3081 };
3082 static const unsigned int scif4_clk_c_mux[] = {
3083 SCK4_C_MARK,
3084 };
3085 static const unsigned int scif4_ctrl_c_pins[] = {
3086 /* RTS, CTS */
3087 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3088 };
3089 static const unsigned int scif4_ctrl_c_mux[] = {
3090 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
3091 };
3092 /* - SCIF5 ------------------------------------------------------------------ */
3093 static const unsigned int scif5_data_pins[] = {
3094 /* RX, TX */
3095 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3096 };
3097 static const unsigned int scif5_data_mux[] = {
3098 RX5_MARK, TX5_MARK,
3099 };
3100 static const unsigned int scif5_clk_pins[] = {
3101 /* SCK */
3102 RCAR_GP_PIN(6, 21),
3103 };
3104 static const unsigned int scif5_clk_mux[] = {
3105 SCK5_MARK,
3106 };
3107 /* - SDHI0 ------------------------------------------------------------------ */
3108 static const unsigned int sdhi0_data1_pins[] = {
3109 /* D0 */
3110 RCAR_GP_PIN(3, 2),
3111 };
3112 static const unsigned int sdhi0_data1_mux[] = {
3113 SD0_DAT0_MARK,
3114 };
3115 static const unsigned int sdhi0_data4_pins[] = {
3116 /* D[0:3] */
3117 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3118 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3119 };
3120 static const unsigned int sdhi0_data4_mux[] = {
3121 SD0_DAT0_MARK, SD0_DAT1_MARK,
3122 SD0_DAT2_MARK, SD0_DAT3_MARK,
3123 };
3124 static const unsigned int sdhi0_ctrl_pins[] = {
3125 /* CLK, CMD */
3126 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3127 };
3128 static const unsigned int sdhi0_ctrl_mux[] = {
3129 SD0_CLK_MARK, SD0_CMD_MARK,
3130 };
3131 static const unsigned int sdhi0_cd_pins[] = {
3132 /* CD */
3133 RCAR_GP_PIN(3, 12),
3134 };
3135 static const unsigned int sdhi0_cd_mux[] = {
3136 SD0_CD_MARK,
3137 };
3138 static const unsigned int sdhi0_wp_pins[] = {
3139 /* WP */
3140 RCAR_GP_PIN(3, 13),
3141 };
3142 static const unsigned int sdhi0_wp_mux[] = {
3143 SD0_WP_MARK,
3144 };
3145 /* - SDHI1 ------------------------------------------------------------------ */
3146 static const unsigned int sdhi1_data1_pins[] = {
3147 /* D0 */
3148 RCAR_GP_PIN(3, 8),
3149 };
3150 static const unsigned int sdhi1_data1_mux[] = {
3151 SD1_DAT0_MARK,
3152 };
3153 static const unsigned int sdhi1_data4_pins[] = {
3154 /* D[0:3] */
3155 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3156 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3157 };
3158 static const unsigned int sdhi1_data4_mux[] = {
3159 SD1_DAT0_MARK, SD1_DAT1_MARK,
3160 SD1_DAT2_MARK, SD1_DAT3_MARK,
3161 };
3162 static const unsigned int sdhi1_ctrl_pins[] = {
3163 /* CLK, CMD */
3164 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3165 };
3166 static const unsigned int sdhi1_ctrl_mux[] = {
3167 SD1_CLK_MARK, SD1_CMD_MARK,
3168 };
3169 static const unsigned int sdhi1_cd_pins[] = {
3170 /* CD */
3171 RCAR_GP_PIN(3, 14),
3172 };
3173 static const unsigned int sdhi1_cd_mux[] = {
3174 SD1_CD_MARK,
3175 };
3176 static const unsigned int sdhi1_wp_pins[] = {
3177 /* WP */
3178 RCAR_GP_PIN(3, 15),
3179 };
3180 static const unsigned int sdhi1_wp_mux[] = {
3181 SD1_WP_MARK,
3182 };
3183 /* - SDHI2 ------------------------------------------------------------------ */
3184 static const unsigned int sdhi2_data1_pins[] = {
3185 /* D0 */
3186 RCAR_GP_PIN(4, 2),
3187 };
3188 static const unsigned int sdhi2_data1_mux[] = {
3189 SD2_DAT0_MARK,
3190 };
3191 static const unsigned int sdhi2_data4_pins[] = {
3192 /* D[0:3] */
3193 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3194 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3195 };
3196 static const unsigned int sdhi2_data4_mux[] = {
3197 SD2_DAT0_MARK, SD2_DAT1_MARK,
3198 SD2_DAT2_MARK, SD2_DAT3_MARK,
3199 };
3200 static const unsigned int sdhi2_data8_pins[] = {
3201 /* D[0:7] */
3202 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3203 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3204 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3205 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3206 };
3207 static const unsigned int sdhi2_data8_mux[] = {
3208 SD2_DAT0_MARK, SD2_DAT1_MARK,
3209 SD2_DAT2_MARK, SD2_DAT3_MARK,
3210 SD2_DAT4_MARK, SD2_DAT5_MARK,
3211 SD2_DAT6_MARK, SD2_DAT7_MARK,
3212 };
3213 static const unsigned int sdhi2_ctrl_pins[] = {
3214 /* CLK, CMD */
3215 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3216 };
3217 static const unsigned int sdhi2_ctrl_mux[] = {
3218 SD2_CLK_MARK, SD2_CMD_MARK,
3219 };
3220 static const unsigned int sdhi2_cd_a_pins[] = {
3221 /* CD */
3222 RCAR_GP_PIN(4, 13),
3223 };
3224 static const unsigned int sdhi2_cd_a_mux[] = {
3225 SD2_CD_A_MARK,
3226 };
3227 static const unsigned int sdhi2_cd_b_pins[] = {
3228 /* CD */
3229 RCAR_GP_PIN(5, 10),
3230 };
3231 static const unsigned int sdhi2_cd_b_mux[] = {
3232 SD2_CD_B_MARK,
3233 };
3234 static const unsigned int sdhi2_wp_a_pins[] = {
3235 /* WP */
3236 RCAR_GP_PIN(4, 14),
3237 };
3238 static const unsigned int sdhi2_wp_a_mux[] = {
3239 SD2_WP_A_MARK,
3240 };
3241 static const unsigned int sdhi2_wp_b_pins[] = {
3242 /* WP */
3243 RCAR_GP_PIN(5, 11),
3244 };
3245 static const unsigned int sdhi2_wp_b_mux[] = {
3246 SD2_WP_B_MARK,
3247 };
3248 static const unsigned int sdhi2_ds_pins[] = {
3249 /* DS */
3250 RCAR_GP_PIN(4, 6),
3251 };
3252 static const unsigned int sdhi2_ds_mux[] = {
3253 SD2_DS_MARK,
3254 };
3255 /* - SDHI3 ------------------------------------------------------------------ */
3256 static const unsigned int sdhi3_data1_pins[] = {
3257 /* D0 */
3258 RCAR_GP_PIN(4, 9),
3259 };
3260 static const unsigned int sdhi3_data1_mux[] = {
3261 SD3_DAT0_MARK,
3262 };
3263 static const unsigned int sdhi3_data4_pins[] = {
3264 /* D[0:3] */
3265 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3266 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3267 };
3268 static const unsigned int sdhi3_data4_mux[] = {
3269 SD3_DAT0_MARK, SD3_DAT1_MARK,
3270 SD3_DAT2_MARK, SD3_DAT3_MARK,
3271 };
3272 static const unsigned int sdhi3_data8_pins[] = {
3273 /* D[0:7] */
3274 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3275 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3276 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3277 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3278 };
3279 static const unsigned int sdhi3_data8_mux[] = {
3280 SD3_DAT0_MARK, SD3_DAT1_MARK,
3281 SD3_DAT2_MARK, SD3_DAT3_MARK,
3282 SD3_DAT4_MARK, SD3_DAT5_MARK,
3283 SD3_DAT6_MARK, SD3_DAT7_MARK,
3284 };
3285 static const unsigned int sdhi3_ctrl_pins[] = {
3286 /* CLK, CMD */
3287 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3288 };
3289 static const unsigned int sdhi3_ctrl_mux[] = {
3290 SD3_CLK_MARK, SD3_CMD_MARK,
3291 };
3292 static const unsigned int sdhi3_cd_pins[] = {
3293 /* CD */
3294 RCAR_GP_PIN(4, 15),
3295 };
3296 static const unsigned int sdhi3_cd_mux[] = {
3297 SD3_CD_MARK,
3298 };
3299 static const unsigned int sdhi3_wp_pins[] = {
3300 /* WP */
3301 RCAR_GP_PIN(4, 16),
3302 };
3303 static const unsigned int sdhi3_wp_mux[] = {
3304 SD3_WP_MARK,
3305 };
3306 static const unsigned int sdhi3_ds_pins[] = {
3307 /* DS */
3308 RCAR_GP_PIN(4, 17),
3309 };
3310 static const unsigned int sdhi3_ds_mux[] = {
3311 SD3_DS_MARK,
3312 };
3313
3314 /* - SCIF Clock ------------------------------------------------------------- */
3315 static const unsigned int scif_clk_a_pins[] = {
3316 /* SCIF_CLK */
3317 RCAR_GP_PIN(6, 23),
3318 };
3319 static const unsigned int scif_clk_a_mux[] = {
3320 SCIF_CLK_A_MARK,
3321 };
3322 static const unsigned int scif_clk_b_pins[] = {
3323 /* SCIF_CLK */
3324 RCAR_GP_PIN(5, 9),
3325 };
3326 static const unsigned int scif_clk_b_mux[] = {
3327 SCIF_CLK_B_MARK,
3328 };
3329
3330 /* - SSI -------------------------------------------------------------------- */
3331 static const unsigned int ssi0_data_pins[] = {
3332 /* SDATA */
3333 RCAR_GP_PIN(6, 2),
3334 };
3335 static const unsigned int ssi0_data_mux[] = {
3336 SSI_SDATA0_MARK,
3337 };
3338 static const unsigned int ssi01239_ctrl_pins[] = {
3339 /* SCK, WS */
3340 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3341 };
3342 static const unsigned int ssi01239_ctrl_mux[] = {
3343 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3344 };
3345 static const unsigned int ssi1_data_a_pins[] = {
3346 /* SDATA */
3347 RCAR_GP_PIN(6, 3),
3348 };
3349 static const unsigned int ssi1_data_a_mux[] = {
3350 SSI_SDATA1_A_MARK,
3351 };
3352 static const unsigned int ssi1_data_b_pins[] = {
3353 /* SDATA */
3354 RCAR_GP_PIN(5, 12),
3355 };
3356 static const unsigned int ssi1_data_b_mux[] = {
3357 SSI_SDATA1_B_MARK,
3358 };
3359 static const unsigned int ssi1_ctrl_a_pins[] = {
3360 /* SCK, WS */
3361 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3362 };
3363 static const unsigned int ssi1_ctrl_a_mux[] = {
3364 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3365 };
3366 static const unsigned int ssi1_ctrl_b_pins[] = {
3367 /* SCK, WS */
3368 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3369 };
3370 static const unsigned int ssi1_ctrl_b_mux[] = {
3371 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3372 };
3373 static const unsigned int ssi2_data_a_pins[] = {
3374 /* SDATA */
3375 RCAR_GP_PIN(6, 4),
3376 };
3377 static const unsigned int ssi2_data_a_mux[] = {
3378 SSI_SDATA2_A_MARK,
3379 };
3380 static const unsigned int ssi2_data_b_pins[] = {
3381 /* SDATA */
3382 RCAR_GP_PIN(5, 13),
3383 };
3384 static const unsigned int ssi2_data_b_mux[] = {
3385 SSI_SDATA2_B_MARK,
3386 };
3387 static const unsigned int ssi2_ctrl_a_pins[] = {
3388 /* SCK, WS */
3389 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3390 };
3391 static const unsigned int ssi2_ctrl_a_mux[] = {
3392 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3393 };
3394 static const unsigned int ssi2_ctrl_b_pins[] = {
3395 /* SCK, WS */
3396 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3397 };
3398 static const unsigned int ssi2_ctrl_b_mux[] = {
3399 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3400 };
3401 static const unsigned int ssi3_data_pins[] = {
3402 /* SDATA */
3403 RCAR_GP_PIN(6, 7),
3404 };
3405 static const unsigned int ssi3_data_mux[] = {
3406 SSI_SDATA3_MARK,
3407 };
3408 static const unsigned int ssi34_ctrl_pins[] = {
3409 /* SCK, WS */
3410 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3411 };
3412 static const unsigned int ssi34_ctrl_mux[] = {
3413 SSI_SCK34_MARK, SSI_WS34_MARK,
3414 };
3415 static const unsigned int ssi4_data_pins[] = {
3416 /* SDATA */
3417 RCAR_GP_PIN(6, 10),
3418 };
3419 static const unsigned int ssi4_data_mux[] = {
3420 SSI_SDATA4_MARK,
3421 };
3422 static const unsigned int ssi4_ctrl_pins[] = {
3423 /* SCK, WS */
3424 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3425 };
3426 static const unsigned int ssi4_ctrl_mux[] = {
3427 SSI_SCK4_MARK, SSI_WS4_MARK,
3428 };
3429 static const unsigned int ssi5_data_pins[] = {
3430 /* SDATA */
3431 RCAR_GP_PIN(6, 13),
3432 };
3433 static const unsigned int ssi5_data_mux[] = {
3434 SSI_SDATA5_MARK,
3435 };
3436 static const unsigned int ssi5_ctrl_pins[] = {
3437 /* SCK, WS */
3438 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3439 };
3440 static const unsigned int ssi5_ctrl_mux[] = {
3441 SSI_SCK5_MARK, SSI_WS5_MARK,
3442 };
3443 static const unsigned int ssi6_data_pins[] = {
3444 /* SDATA */
3445 RCAR_GP_PIN(6, 16),
3446 };
3447 static const unsigned int ssi6_data_mux[] = {
3448 SSI_SDATA6_MARK,
3449 };
3450 static const unsigned int ssi6_ctrl_pins[] = {
3451 /* SCK, WS */
3452 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3453 };
3454 static const unsigned int ssi6_ctrl_mux[] = {
3455 SSI_SCK6_MARK, SSI_WS6_MARK,
3456 };
3457 static const unsigned int ssi7_data_pins[] = {
3458 /* SDATA */
3459 RCAR_GP_PIN(6, 19),
3460 };
3461 static const unsigned int ssi7_data_mux[] = {
3462 SSI_SDATA7_MARK,
3463 };
3464 static const unsigned int ssi78_ctrl_pins[] = {
3465 /* SCK, WS */
3466 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3467 };
3468 static const unsigned int ssi78_ctrl_mux[] = {
3469 SSI_SCK78_MARK, SSI_WS78_MARK,
3470 };
3471 static const unsigned int ssi8_data_pins[] = {
3472 /* SDATA */
3473 RCAR_GP_PIN(6, 20),
3474 };
3475 static const unsigned int ssi8_data_mux[] = {
3476 SSI_SDATA8_MARK,
3477 };
3478 static const unsigned int ssi9_data_a_pins[] = {
3479 /* SDATA */
3480 RCAR_GP_PIN(6, 21),
3481 };
3482 static const unsigned int ssi9_data_a_mux[] = {
3483 SSI_SDATA9_A_MARK,
3484 };
3485 static const unsigned int ssi9_data_b_pins[] = {
3486 /* SDATA */
3487 RCAR_GP_PIN(5, 14),
3488 };
3489 static const unsigned int ssi9_data_b_mux[] = {
3490 SSI_SDATA9_B_MARK,
3491 };
3492 static const unsigned int ssi9_ctrl_a_pins[] = {
3493 /* SCK, WS */
3494 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3495 };
3496 static const unsigned int ssi9_ctrl_a_mux[] = {
3497 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3498 };
3499 static const unsigned int ssi9_ctrl_b_pins[] = {
3500 /* SCK, WS */
3501 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3502 };
3503 static const unsigned int ssi9_ctrl_b_mux[] = {
3504 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3505 };
3506
3507 /* - USB0 ------------------------------------------------------------------- */
3508 static const unsigned int usb0_pins[] = {
3509 /* PWEN, OVC */
3510 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3511 };
3512 static const unsigned int usb0_mux[] = {
3513 USB0_PWEN_MARK, USB0_OVC_MARK,
3514 };
3515 /* - USB1 ------------------------------------------------------------------- */
3516 static const unsigned int usb1_pins[] = {
3517 /* PWEN, OVC */
3518 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3519 };
3520 static const unsigned int usb1_mux[] = {
3521 USB1_PWEN_MARK, USB1_OVC_MARK,
3522 };
3523 /* - USB2 ------------------------------------------------------------------- */
3524 static const unsigned int usb2_pins[] = {
3525 /* PWEN, OVC */
3526 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3527 };
3528 static const unsigned int usb2_mux[] = {
3529 USB2_PWEN_MARK, USB2_OVC_MARK,
3530 };
3531
3532 static const struct sh_pfc_pin_group pinmux_groups[] = {
3533 SH_PFC_PIN_GROUP(audio_clk_a_a),
3534 SH_PFC_PIN_GROUP(audio_clk_a_b),
3535 SH_PFC_PIN_GROUP(audio_clk_a_c),
3536 SH_PFC_PIN_GROUP(audio_clk_b_a),
3537 SH_PFC_PIN_GROUP(audio_clk_b_b),
3538 SH_PFC_PIN_GROUP(audio_clk_c_a),
3539 SH_PFC_PIN_GROUP(audio_clk_c_b),
3540 SH_PFC_PIN_GROUP(audio_clkout_a),
3541 SH_PFC_PIN_GROUP(audio_clkout_b),
3542 SH_PFC_PIN_GROUP(audio_clkout_c),
3543 SH_PFC_PIN_GROUP(audio_clkout_d),
3544 SH_PFC_PIN_GROUP(audio_clkout1_a),
3545 SH_PFC_PIN_GROUP(audio_clkout1_b),
3546 SH_PFC_PIN_GROUP(audio_clkout2_a),
3547 SH_PFC_PIN_GROUP(audio_clkout2_b),
3548 SH_PFC_PIN_GROUP(audio_clkout3_a),
3549 SH_PFC_PIN_GROUP(audio_clkout3_b),
3550 SH_PFC_PIN_GROUP(avb_link),
3551 SH_PFC_PIN_GROUP(avb_magic),
3552 SH_PFC_PIN_GROUP(avb_phy_int),
3553 SH_PFC_PIN_GROUP(avb_mdc),
3554 SH_PFC_PIN_GROUP(avb_avtp_pps),
3555 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3556 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3557 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3558 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3559 SH_PFC_PIN_GROUP(can0_data_a),
3560 SH_PFC_PIN_GROUP(can0_data_b),
3561 SH_PFC_PIN_GROUP(can1_data),
3562 SH_PFC_PIN_GROUP(can_clk),
3563 SH_PFC_PIN_GROUP(canfd0_data_a),
3564 SH_PFC_PIN_GROUP(canfd0_data_b),
3565 SH_PFC_PIN_GROUP(canfd1_data),
3566 SH_PFC_PIN_GROUP(drif0_ctrl_a),
3567 SH_PFC_PIN_GROUP(drif0_data0_a),
3568 SH_PFC_PIN_GROUP(drif0_data1_a),
3569 SH_PFC_PIN_GROUP(drif0_ctrl_b),
3570 SH_PFC_PIN_GROUP(drif0_data0_b),
3571 SH_PFC_PIN_GROUP(drif0_data1_b),
3572 SH_PFC_PIN_GROUP(drif0_ctrl_c),
3573 SH_PFC_PIN_GROUP(drif0_data0_c),
3574 SH_PFC_PIN_GROUP(drif0_data1_c),
3575 SH_PFC_PIN_GROUP(drif1_ctrl_a),
3576 SH_PFC_PIN_GROUP(drif1_data0_a),
3577 SH_PFC_PIN_GROUP(drif1_data1_a),
3578 SH_PFC_PIN_GROUP(drif1_ctrl_b),
3579 SH_PFC_PIN_GROUP(drif1_data0_b),
3580 SH_PFC_PIN_GROUP(drif1_data1_b),
3581 SH_PFC_PIN_GROUP(drif1_ctrl_c),
3582 SH_PFC_PIN_GROUP(drif1_data0_c),
3583 SH_PFC_PIN_GROUP(drif1_data1_c),
3584 SH_PFC_PIN_GROUP(drif2_ctrl_a),
3585 SH_PFC_PIN_GROUP(drif2_data0_a),
3586 SH_PFC_PIN_GROUP(drif2_data1_a),
3587 SH_PFC_PIN_GROUP(drif2_ctrl_b),
3588 SH_PFC_PIN_GROUP(drif2_data0_b),
3589 SH_PFC_PIN_GROUP(drif2_data1_b),
3590 SH_PFC_PIN_GROUP(drif3_ctrl_a),
3591 SH_PFC_PIN_GROUP(drif3_data0_a),
3592 SH_PFC_PIN_GROUP(drif3_data1_a),
3593 SH_PFC_PIN_GROUP(drif3_ctrl_b),
3594 SH_PFC_PIN_GROUP(drif3_data0_b),
3595 SH_PFC_PIN_GROUP(drif3_data1_b),
3596 SH_PFC_PIN_GROUP(hscif0_data),
3597 SH_PFC_PIN_GROUP(hscif0_clk),
3598 SH_PFC_PIN_GROUP(hscif0_ctrl),
3599 SH_PFC_PIN_GROUP(hscif1_data_a),
3600 SH_PFC_PIN_GROUP(hscif1_clk_a),
3601 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3602 SH_PFC_PIN_GROUP(hscif1_data_b),
3603 SH_PFC_PIN_GROUP(hscif1_clk_b),
3604 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3605 SH_PFC_PIN_GROUP(hscif2_data_a),
3606 SH_PFC_PIN_GROUP(hscif2_clk_a),
3607 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3608 SH_PFC_PIN_GROUP(hscif2_data_b),
3609 SH_PFC_PIN_GROUP(hscif2_clk_b),
3610 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3611 SH_PFC_PIN_GROUP(hscif3_data_a),
3612 SH_PFC_PIN_GROUP(hscif3_clk),
3613 SH_PFC_PIN_GROUP(hscif3_ctrl),
3614 SH_PFC_PIN_GROUP(hscif3_data_b),
3615 SH_PFC_PIN_GROUP(hscif3_data_c),
3616 SH_PFC_PIN_GROUP(hscif3_data_d),
3617 SH_PFC_PIN_GROUP(hscif4_data_a),
3618 SH_PFC_PIN_GROUP(hscif4_clk),
3619 SH_PFC_PIN_GROUP(hscif4_ctrl),
3620 SH_PFC_PIN_GROUP(hscif4_data_b),
3621 SH_PFC_PIN_GROUP(i2c1_a),
3622 SH_PFC_PIN_GROUP(i2c1_b),
3623 SH_PFC_PIN_GROUP(i2c2_a),
3624 SH_PFC_PIN_GROUP(i2c2_b),
3625 SH_PFC_PIN_GROUP(i2c6_a),
3626 SH_PFC_PIN_GROUP(i2c6_b),
3627 SH_PFC_PIN_GROUP(i2c6_c),
3628 SH_PFC_PIN_GROUP(intc_ex_irq0),
3629 SH_PFC_PIN_GROUP(intc_ex_irq1),
3630 SH_PFC_PIN_GROUP(intc_ex_irq2),
3631 SH_PFC_PIN_GROUP(intc_ex_irq3),
3632 SH_PFC_PIN_GROUP(intc_ex_irq4),
3633 SH_PFC_PIN_GROUP(intc_ex_irq5),
3634 SH_PFC_PIN_GROUP(msiof0_clk),
3635 SH_PFC_PIN_GROUP(msiof0_sync),
3636 SH_PFC_PIN_GROUP(msiof0_ss1),
3637 SH_PFC_PIN_GROUP(msiof0_ss2),
3638 SH_PFC_PIN_GROUP(msiof0_txd),
3639 SH_PFC_PIN_GROUP(msiof0_rxd),
3640 SH_PFC_PIN_GROUP(msiof1_clk_a),
3641 SH_PFC_PIN_GROUP(msiof1_sync_a),
3642 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3643 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3644 SH_PFC_PIN_GROUP(msiof1_txd_a),
3645 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3646 SH_PFC_PIN_GROUP(msiof1_clk_b),
3647 SH_PFC_PIN_GROUP(msiof1_sync_b),
3648 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3649 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3650 SH_PFC_PIN_GROUP(msiof1_txd_b),
3651 SH_PFC_PIN_GROUP(msiof1_rxd_b),
3652 SH_PFC_PIN_GROUP(msiof1_clk_c),
3653 SH_PFC_PIN_GROUP(msiof1_sync_c),
3654 SH_PFC_PIN_GROUP(msiof1_ss1_c),
3655 SH_PFC_PIN_GROUP(msiof1_ss2_c),
3656 SH_PFC_PIN_GROUP(msiof1_txd_c),
3657 SH_PFC_PIN_GROUP(msiof1_rxd_c),
3658 SH_PFC_PIN_GROUP(msiof1_clk_d),
3659 SH_PFC_PIN_GROUP(msiof1_sync_d),
3660 SH_PFC_PIN_GROUP(msiof1_ss1_d),
3661 SH_PFC_PIN_GROUP(msiof1_ss2_d),
3662 SH_PFC_PIN_GROUP(msiof1_txd_d),
3663 SH_PFC_PIN_GROUP(msiof1_rxd_d),
3664 SH_PFC_PIN_GROUP(msiof1_clk_e),
3665 SH_PFC_PIN_GROUP(msiof1_sync_e),
3666 SH_PFC_PIN_GROUP(msiof1_ss1_e),
3667 SH_PFC_PIN_GROUP(msiof1_ss2_e),
3668 SH_PFC_PIN_GROUP(msiof1_txd_e),
3669 SH_PFC_PIN_GROUP(msiof1_rxd_e),
3670 SH_PFC_PIN_GROUP(msiof1_clk_f),
3671 SH_PFC_PIN_GROUP(msiof1_sync_f),
3672 SH_PFC_PIN_GROUP(msiof1_ss1_f),
3673 SH_PFC_PIN_GROUP(msiof1_ss2_f),
3674 SH_PFC_PIN_GROUP(msiof1_txd_f),
3675 SH_PFC_PIN_GROUP(msiof1_rxd_f),
3676 SH_PFC_PIN_GROUP(msiof1_clk_g),
3677 SH_PFC_PIN_GROUP(msiof1_sync_g),
3678 SH_PFC_PIN_GROUP(msiof1_ss1_g),
3679 SH_PFC_PIN_GROUP(msiof1_ss2_g),
3680 SH_PFC_PIN_GROUP(msiof1_txd_g),
3681 SH_PFC_PIN_GROUP(msiof1_rxd_g),
3682 SH_PFC_PIN_GROUP(msiof2_clk_a),
3683 SH_PFC_PIN_GROUP(msiof2_sync_a),
3684 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3685 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3686 SH_PFC_PIN_GROUP(msiof2_txd_a),
3687 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3688 SH_PFC_PIN_GROUP(msiof2_clk_b),
3689 SH_PFC_PIN_GROUP(msiof2_sync_b),
3690 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3691 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3692 SH_PFC_PIN_GROUP(msiof2_txd_b),
3693 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3694 SH_PFC_PIN_GROUP(msiof2_clk_c),
3695 SH_PFC_PIN_GROUP(msiof2_sync_c),
3696 SH_PFC_PIN_GROUP(msiof2_ss1_c),
3697 SH_PFC_PIN_GROUP(msiof2_ss2_c),
3698 SH_PFC_PIN_GROUP(msiof2_txd_c),
3699 SH_PFC_PIN_GROUP(msiof2_rxd_c),
3700 SH_PFC_PIN_GROUP(msiof2_clk_d),
3701 SH_PFC_PIN_GROUP(msiof2_sync_d),
3702 SH_PFC_PIN_GROUP(msiof2_ss1_d),
3703 SH_PFC_PIN_GROUP(msiof2_ss2_d),
3704 SH_PFC_PIN_GROUP(msiof2_txd_d),
3705 SH_PFC_PIN_GROUP(msiof2_rxd_d),
3706 SH_PFC_PIN_GROUP(msiof3_clk_a),
3707 SH_PFC_PIN_GROUP(msiof3_sync_a),
3708 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3709 SH_PFC_PIN_GROUP(msiof3_ss2_a),
3710 SH_PFC_PIN_GROUP(msiof3_txd_a),
3711 SH_PFC_PIN_GROUP(msiof3_rxd_a),
3712 SH_PFC_PIN_GROUP(msiof3_clk_b),
3713 SH_PFC_PIN_GROUP(msiof3_sync_b),
3714 SH_PFC_PIN_GROUP(msiof3_ss1_b),
3715 SH_PFC_PIN_GROUP(msiof3_ss2_b),
3716 SH_PFC_PIN_GROUP(msiof3_txd_b),
3717 SH_PFC_PIN_GROUP(msiof3_rxd_b),
3718 SH_PFC_PIN_GROUP(msiof3_clk_c),
3719 SH_PFC_PIN_GROUP(msiof3_sync_c),
3720 SH_PFC_PIN_GROUP(msiof3_txd_c),
3721 SH_PFC_PIN_GROUP(msiof3_rxd_c),
3722 SH_PFC_PIN_GROUP(msiof3_clk_d),
3723 SH_PFC_PIN_GROUP(msiof3_sync_d),
3724 SH_PFC_PIN_GROUP(msiof3_ss1_d),
3725 SH_PFC_PIN_GROUP(msiof3_txd_d),
3726 SH_PFC_PIN_GROUP(msiof3_rxd_d),
3727 SH_PFC_PIN_GROUP(pwm0),
3728 SH_PFC_PIN_GROUP(pwm1_a),
3729 SH_PFC_PIN_GROUP(pwm1_b),
3730 SH_PFC_PIN_GROUP(pwm2_a),
3731 SH_PFC_PIN_GROUP(pwm2_b),
3732 SH_PFC_PIN_GROUP(pwm3_a),
3733 SH_PFC_PIN_GROUP(pwm3_b),
3734 SH_PFC_PIN_GROUP(pwm4_a),
3735 SH_PFC_PIN_GROUP(pwm4_b),
3736 SH_PFC_PIN_GROUP(pwm5_a),
3737 SH_PFC_PIN_GROUP(pwm5_b),
3738 SH_PFC_PIN_GROUP(pwm6_a),
3739 SH_PFC_PIN_GROUP(pwm6_b),
3740 SH_PFC_PIN_GROUP(sata0_devslp_a),
3741 SH_PFC_PIN_GROUP(sata0_devslp_b),
3742 SH_PFC_PIN_GROUP(scif0_data),
3743 SH_PFC_PIN_GROUP(scif0_clk),
3744 SH_PFC_PIN_GROUP(scif0_ctrl),
3745 SH_PFC_PIN_GROUP(scif1_data_a),
3746 SH_PFC_PIN_GROUP(scif1_clk),
3747 SH_PFC_PIN_GROUP(scif1_ctrl),
3748 SH_PFC_PIN_GROUP(scif1_data_b),
3749 SH_PFC_PIN_GROUP(scif2_data_a),
3750 SH_PFC_PIN_GROUP(scif2_clk),
3751 SH_PFC_PIN_GROUP(scif2_data_b),
3752 SH_PFC_PIN_GROUP(scif3_data_a),
3753 SH_PFC_PIN_GROUP(scif3_clk),
3754 SH_PFC_PIN_GROUP(scif3_ctrl),
3755 SH_PFC_PIN_GROUP(scif3_data_b),
3756 SH_PFC_PIN_GROUP(scif4_data_a),
3757 SH_PFC_PIN_GROUP(scif4_clk_a),
3758 SH_PFC_PIN_GROUP(scif4_ctrl_a),
3759 SH_PFC_PIN_GROUP(scif4_data_b),
3760 SH_PFC_PIN_GROUP(scif4_clk_b),
3761 SH_PFC_PIN_GROUP(scif4_ctrl_b),
3762 SH_PFC_PIN_GROUP(scif4_data_c),
3763 SH_PFC_PIN_GROUP(scif4_clk_c),
3764 SH_PFC_PIN_GROUP(scif4_ctrl_c),
3765 SH_PFC_PIN_GROUP(scif5_data),
3766 SH_PFC_PIN_GROUP(scif5_clk),
3767 SH_PFC_PIN_GROUP(scif_clk_a),
3768 SH_PFC_PIN_GROUP(scif_clk_b),
3769 SH_PFC_PIN_GROUP(sdhi0_data1),
3770 SH_PFC_PIN_GROUP(sdhi0_data4),
3771 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3772 SH_PFC_PIN_GROUP(sdhi0_cd),
3773 SH_PFC_PIN_GROUP(sdhi0_wp),
3774 SH_PFC_PIN_GROUP(sdhi1_data1),
3775 SH_PFC_PIN_GROUP(sdhi1_data4),
3776 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3777 SH_PFC_PIN_GROUP(sdhi1_cd),
3778 SH_PFC_PIN_GROUP(sdhi1_wp),
3779 SH_PFC_PIN_GROUP(sdhi2_data1),
3780 SH_PFC_PIN_GROUP(sdhi2_data4),
3781 SH_PFC_PIN_GROUP(sdhi2_data8),
3782 SH_PFC_PIN_GROUP(sdhi2_ctrl),
3783 SH_PFC_PIN_GROUP(sdhi2_cd_a),
3784 SH_PFC_PIN_GROUP(sdhi2_wp_a),
3785 SH_PFC_PIN_GROUP(sdhi2_cd_b),
3786 SH_PFC_PIN_GROUP(sdhi2_wp_b),
3787 SH_PFC_PIN_GROUP(sdhi2_ds),
3788 SH_PFC_PIN_GROUP(sdhi3_data1),
3789 SH_PFC_PIN_GROUP(sdhi3_data4),
3790 SH_PFC_PIN_GROUP(sdhi3_data8),
3791 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3792 SH_PFC_PIN_GROUP(sdhi3_cd),
3793 SH_PFC_PIN_GROUP(sdhi3_wp),
3794 SH_PFC_PIN_GROUP(sdhi3_ds),
3795 SH_PFC_PIN_GROUP(ssi0_data),
3796 SH_PFC_PIN_GROUP(ssi01239_ctrl),
3797 SH_PFC_PIN_GROUP(ssi1_data_a),
3798 SH_PFC_PIN_GROUP(ssi1_data_b),
3799 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
3800 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
3801 SH_PFC_PIN_GROUP(ssi2_data_a),
3802 SH_PFC_PIN_GROUP(ssi2_data_b),
3803 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
3804 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
3805 SH_PFC_PIN_GROUP(ssi3_data),
3806 SH_PFC_PIN_GROUP(ssi34_ctrl),
3807 SH_PFC_PIN_GROUP(ssi4_data),
3808 SH_PFC_PIN_GROUP(ssi4_ctrl),
3809 SH_PFC_PIN_GROUP(ssi5_data),
3810 SH_PFC_PIN_GROUP(ssi5_ctrl),
3811 SH_PFC_PIN_GROUP(ssi6_data),
3812 SH_PFC_PIN_GROUP(ssi6_ctrl),
3813 SH_PFC_PIN_GROUP(ssi7_data),
3814 SH_PFC_PIN_GROUP(ssi78_ctrl),
3815 SH_PFC_PIN_GROUP(ssi8_data),
3816 SH_PFC_PIN_GROUP(ssi9_data_a),
3817 SH_PFC_PIN_GROUP(ssi9_data_b),
3818 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
3819 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
3820 SH_PFC_PIN_GROUP(usb0),
3821 SH_PFC_PIN_GROUP(usb1),
3822 SH_PFC_PIN_GROUP(usb2),
3823 };
3824
3825 static const char * const audio_clk_groups[] = {
3826 "audio_clk_a_a",
3827 "audio_clk_a_b",
3828 "audio_clk_a_c",
3829 "audio_clk_b_a",
3830 "audio_clk_b_b",
3831 "audio_clk_c_a",
3832 "audio_clk_c_b",
3833 "audio_clkout_a",
3834 "audio_clkout_b",
3835 "audio_clkout_c",
3836 "audio_clkout_d",
3837 "audio_clkout1_a",
3838 "audio_clkout1_b",
3839 "audio_clkout2_a",
3840 "audio_clkout2_b",
3841 "audio_clkout3_a",
3842 "audio_clkout3_b",
3843 };
3844
3845 static const char * const avb_groups[] = {
3846 "avb_link",
3847 "avb_magic",
3848 "avb_phy_int",
3849 "avb_mdc",
3850 "avb_avtp_pps",
3851 "avb_avtp_match_a",
3852 "avb_avtp_capture_a",
3853 "avb_avtp_match_b",
3854 "avb_avtp_capture_b",
3855 };
3856
3857 static const char * const can0_groups[] = {
3858 "can0_data_a",
3859 "can0_data_b",
3860 };
3861
3862 static const char * const can1_groups[] = {
3863 "can1_data",
3864 };
3865
3866 static const char * const can_clk_groups[] = {
3867 "can_clk",
3868 };
3869
3870 static const char * const canfd0_groups[] = {
3871 "canfd0_data_a",
3872 "canfd0_data_b",
3873 };
3874
3875 static const char * const canfd1_groups[] = {
3876 "canfd1_data",
3877 };
3878
3879 static const char * const drif0_groups[] = {
3880 "drif0_ctrl_a",
3881 "drif0_data0_a",
3882 "drif0_data1_a",
3883 "drif0_ctrl_b",
3884 "drif0_data0_b",
3885 "drif0_data1_b",
3886 "drif0_ctrl_c",
3887 "drif0_data0_c",
3888 "drif0_data1_c",
3889 };
3890
3891 static const char * const drif1_groups[] = {
3892 "drif1_ctrl_a",
3893 "drif1_data0_a",
3894 "drif1_data1_a",
3895 "drif1_ctrl_b",
3896 "drif1_data0_b",
3897 "drif1_data1_b",
3898 "drif1_ctrl_c",
3899 "drif1_data0_c",
3900 "drif1_data1_c",
3901 };
3902
3903 static const char * const drif2_groups[] = {
3904 "drif2_ctrl_a",
3905 "drif2_data0_a",
3906 "drif2_data1_a",
3907 "drif2_ctrl_b",
3908 "drif2_data0_b",
3909 "drif2_data1_b",
3910 };
3911
3912 static const char * const drif3_groups[] = {
3913 "drif3_ctrl_a",
3914 "drif3_data0_a",
3915 "drif3_data1_a",
3916 "drif3_ctrl_b",
3917 "drif3_data0_b",
3918 "drif3_data1_b",
3919 };
3920
3921 static const char * const hscif0_groups[] = {
3922 "hscif0_data",
3923 "hscif0_clk",
3924 "hscif0_ctrl",
3925 };
3926
3927 static const char * const hscif1_groups[] = {
3928 "hscif1_data_a",
3929 "hscif1_clk_a",
3930 "hscif1_ctrl_a",
3931 "hscif1_data_b",
3932 "hscif1_clk_b",
3933 "hscif1_ctrl_b",
3934 };
3935
3936 static const char * const hscif2_groups[] = {
3937 "hscif2_data_a",
3938 "hscif2_clk_a",
3939 "hscif2_ctrl_a",
3940 "hscif2_data_b",
3941 "hscif2_clk_b",
3942 "hscif2_ctrl_b",
3943 };
3944
3945 static const char * const hscif3_groups[] = {
3946 "hscif3_data_a",
3947 "hscif3_clk",
3948 "hscif3_ctrl",
3949 "hscif3_data_b",
3950 "hscif3_data_c",
3951 "hscif3_data_d",
3952 };
3953
3954 static const char * const hscif4_groups[] = {
3955 "hscif4_data_a",
3956 "hscif4_clk",
3957 "hscif4_ctrl",
3958 "hscif4_data_b",
3959 };
3960
3961 static const char * const i2c1_groups[] = {
3962 "i2c1_a",
3963 "i2c1_b",
3964 };
3965
3966 static const char * const i2c2_groups[] = {
3967 "i2c2_a",
3968 "i2c2_b",
3969 };
3970
3971 static const char * const i2c6_groups[] = {
3972 "i2c6_a",
3973 "i2c6_b",
3974 "i2c6_c",
3975 };
3976
3977 static const char * const intc_ex_groups[] = {
3978 "intc_ex_irq0",
3979 "intc_ex_irq1",
3980 "intc_ex_irq2",
3981 "intc_ex_irq3",
3982 "intc_ex_irq4",
3983 "intc_ex_irq5",
3984 };
3985
3986 static const char * const msiof0_groups[] = {
3987 "msiof0_clk",
3988 "msiof0_sync",
3989 "msiof0_ss1",
3990 "msiof0_ss2",
3991 "msiof0_txd",
3992 "msiof0_rxd",
3993 };
3994
3995 static const char * const msiof1_groups[] = {
3996 "msiof1_clk_a",
3997 "msiof1_sync_a",
3998 "msiof1_ss1_a",
3999 "msiof1_ss2_a",
4000 "msiof1_txd_a",
4001 "msiof1_rxd_a",
4002 "msiof1_clk_b",
4003 "msiof1_sync_b",
4004 "msiof1_ss1_b",
4005 "msiof1_ss2_b",
4006 "msiof1_txd_b",
4007 "msiof1_rxd_b",
4008 "msiof1_clk_c",
4009 "msiof1_sync_c",
4010 "msiof1_ss1_c",
4011 "msiof1_ss2_c",
4012 "msiof1_txd_c",
4013 "msiof1_rxd_c",
4014 "msiof1_clk_d",
4015 "msiof1_sync_d",
4016 "msiof1_ss1_d",
4017 "msiof1_ss2_d",
4018 "msiof1_txd_d",
4019 "msiof1_rxd_d",
4020 "msiof1_clk_e",
4021 "msiof1_sync_e",
4022 "msiof1_ss1_e",
4023 "msiof1_ss2_e",
4024 "msiof1_txd_e",
4025 "msiof1_rxd_e",
4026 "msiof1_clk_f",
4027 "msiof1_sync_f",
4028 "msiof1_ss1_f",
4029 "msiof1_ss2_f",
4030 "msiof1_txd_f",
4031 "msiof1_rxd_f",
4032 "msiof1_clk_g",
4033 "msiof1_sync_g",
4034 "msiof1_ss1_g",
4035 "msiof1_ss2_g",
4036 "msiof1_txd_g",
4037 "msiof1_rxd_g",
4038 };
4039
4040 static const char * const msiof2_groups[] = {
4041 "msiof2_clk_a",
4042 "msiof2_sync_a",
4043 "msiof2_ss1_a",
4044 "msiof2_ss2_a",
4045 "msiof2_txd_a",
4046 "msiof2_rxd_a",
4047 "msiof2_clk_b",
4048 "msiof2_sync_b",
4049 "msiof2_ss1_b",
4050 "msiof2_ss2_b",
4051 "msiof2_txd_b",
4052 "msiof2_rxd_b",
4053 "msiof2_clk_c",
4054 "msiof2_sync_c",
4055 "msiof2_ss1_c",
4056 "msiof2_ss2_c",
4057 "msiof2_txd_c",
4058 "msiof2_rxd_c",
4059 "msiof2_clk_d",
4060 "msiof2_sync_d",
4061 "msiof2_ss1_d",
4062 "msiof2_ss2_d",
4063 "msiof2_txd_d",
4064 "msiof2_rxd_d",
4065 };
4066
4067 static const char * const msiof3_groups[] = {
4068 "msiof3_clk_a",
4069 "msiof3_sync_a",
4070 "msiof3_ss1_a",
4071 "msiof3_ss2_a",
4072 "msiof3_txd_a",
4073 "msiof3_rxd_a",
4074 "msiof3_clk_b",
4075 "msiof3_sync_b",
4076 "msiof3_ss1_b",
4077 "msiof3_ss2_b",
4078 "msiof3_txd_b",
4079 "msiof3_rxd_b",
4080 "msiof3_clk_c",
4081 "msiof3_sync_c",
4082 "msiof3_txd_c",
4083 "msiof3_rxd_c",
4084 "msiof3_clk_d",
4085 "msiof3_sync_d",
4086 "msiof3_ss1_d",
4087 "msiof3_txd_d",
4088 "msiof3_rxd_d",
4089 };
4090
4091 static const char * const pwm0_groups[] = {
4092 "pwm0",
4093 };
4094
4095 static const char * const pwm1_groups[] = {
4096 "pwm1_a",
4097 "pwm1_b",
4098 };
4099
4100 static const char * const pwm2_groups[] = {
4101 "pwm2_a",
4102 "pwm2_b",
4103 };
4104
4105 static const char * const pwm3_groups[] = {
4106 "pwm3_a",
4107 "pwm3_b",
4108 };
4109
4110 static const char * const pwm4_groups[] = {
4111 "pwm4_a",
4112 "pwm4_b",
4113 };
4114
4115 static const char * const pwm5_groups[] = {
4116 "pwm5_a",
4117 "pwm5_b",
4118 };
4119
4120 static const char * const pwm6_groups[] = {
4121 "pwm6_a",
4122 "pwm6_b",
4123 };
4124
4125 static const char * const sata0_groups[] = {
4126 "sata0_devslp_a",
4127 "sata0_devslp_b",
4128 };
4129
4130 static const char * const scif0_groups[] = {
4131 "scif0_data",
4132 "scif0_clk",
4133 "scif0_ctrl",
4134 };
4135
4136 static const char * const scif1_groups[] = {
4137 "scif1_data_a",
4138 "scif1_clk",
4139 "scif1_ctrl",
4140 "scif1_data_b",
4141 };
4142
4143 static const char * const scif2_groups[] = {
4144 "scif2_data_a",
4145 "scif2_clk",
4146 "scif2_data_b",
4147 };
4148
4149 static const char * const scif3_groups[] = {
4150 "scif3_data_a",
4151 "scif3_clk",
4152 "scif3_ctrl",
4153 "scif3_data_b",
4154 };
4155
4156 static const char * const scif4_groups[] = {
4157 "scif4_data_a",
4158 "scif4_clk_a",
4159 "scif4_ctrl_a",
4160 "scif4_data_b",
4161 "scif4_clk_b",
4162 "scif4_ctrl_b",
4163 "scif4_data_c",
4164 "scif4_clk_c",
4165 "scif4_ctrl_c",
4166 };
4167
4168 static const char * const scif5_groups[] = {
4169 "scif5_data",
4170 "scif5_clk",
4171 };
4172
4173 static const char * const scif_clk_groups[] = {
4174 "scif_clk_a",
4175 "scif_clk_b",
4176 };
4177
4178 static const char * const sdhi0_groups[] = {
4179 "sdhi0_data1",
4180 "sdhi0_data4",
4181 "sdhi0_ctrl",
4182 "sdhi0_cd",
4183 "sdhi0_wp",
4184 };
4185
4186 static const char * const sdhi1_groups[] = {
4187 "sdhi1_data1",
4188 "sdhi1_data4",
4189 "sdhi1_ctrl",
4190 "sdhi1_cd",
4191 "sdhi1_wp",
4192 };
4193
4194 static const char * const sdhi2_groups[] = {
4195 "sdhi2_data1",
4196 "sdhi2_data4",
4197 "sdhi2_data8",
4198 "sdhi2_ctrl",
4199 "sdhi2_cd_a",
4200 "sdhi2_wp_a",
4201 "sdhi2_cd_b",
4202 "sdhi2_wp_b",
4203 "sdhi2_ds",
4204 };
4205
4206 static const char * const sdhi3_groups[] = {
4207 "sdhi3_data1",
4208 "sdhi3_data4",
4209 "sdhi3_data8",
4210 "sdhi3_ctrl",
4211 "sdhi3_cd",
4212 "sdhi3_wp",
4213 "sdhi3_ds",
4214 };
4215
4216 static const char * const ssi_groups[] = {
4217 "ssi0_data",
4218 "ssi01239_ctrl",
4219 "ssi1_data_a",
4220 "ssi1_data_b",
4221 "ssi1_ctrl_a",
4222 "ssi1_ctrl_b",
4223 "ssi2_data_a",
4224 "ssi2_data_b",
4225 "ssi2_ctrl_a",
4226 "ssi2_ctrl_b",
4227 "ssi3_data",
4228 "ssi34_ctrl",
4229 "ssi4_data",
4230 "ssi4_ctrl",
4231 "ssi5_data",
4232 "ssi5_ctrl",
4233 "ssi6_data",
4234 "ssi6_ctrl",
4235 "ssi7_data",
4236 "ssi78_ctrl",
4237 "ssi8_data",
4238 "ssi9_data_a",
4239 "ssi9_data_b",
4240 "ssi9_ctrl_a",
4241 "ssi9_ctrl_b",
4242 };
4243
4244 static const char * const usb0_groups[] = {
4245 "usb0",
4246 };
4247
4248 static const char * const usb1_groups[] = {
4249 "usb1",
4250 };
4251
4252 static const char * const usb2_groups[] = {
4253 "usb2",
4254 };
4255
4256 static const struct sh_pfc_function pinmux_functions[] = {
4257 SH_PFC_FUNCTION(audio_clk),
4258 SH_PFC_FUNCTION(avb),
4259 SH_PFC_FUNCTION(can0),
4260 SH_PFC_FUNCTION(can1),
4261 SH_PFC_FUNCTION(can_clk),
4262 SH_PFC_FUNCTION(canfd0),
4263 SH_PFC_FUNCTION(canfd1),
4264 SH_PFC_FUNCTION(drif0),
4265 SH_PFC_FUNCTION(drif1),
4266 SH_PFC_FUNCTION(drif2),
4267 SH_PFC_FUNCTION(drif3),
4268 SH_PFC_FUNCTION(hscif0),
4269 SH_PFC_FUNCTION(hscif1),
4270 SH_PFC_FUNCTION(hscif2),
4271 SH_PFC_FUNCTION(hscif3),
4272 SH_PFC_FUNCTION(hscif4),
4273 SH_PFC_FUNCTION(i2c1),
4274 SH_PFC_FUNCTION(i2c2),
4275 SH_PFC_FUNCTION(i2c6),
4276 SH_PFC_FUNCTION(intc_ex),
4277 SH_PFC_FUNCTION(msiof0),
4278 SH_PFC_FUNCTION(msiof1),
4279 SH_PFC_FUNCTION(msiof2),
4280 SH_PFC_FUNCTION(msiof3),
4281 SH_PFC_FUNCTION(pwm0),
4282 SH_PFC_FUNCTION(pwm1),
4283 SH_PFC_FUNCTION(pwm2),
4284 SH_PFC_FUNCTION(pwm3),
4285 SH_PFC_FUNCTION(pwm4),
4286 SH_PFC_FUNCTION(pwm5),
4287 SH_PFC_FUNCTION(pwm6),
4288 SH_PFC_FUNCTION(sata0),
4289 SH_PFC_FUNCTION(scif0),
4290 SH_PFC_FUNCTION(scif1),
4291 SH_PFC_FUNCTION(scif2),
4292 SH_PFC_FUNCTION(scif3),
4293 SH_PFC_FUNCTION(scif4),
4294 SH_PFC_FUNCTION(scif5),
4295 SH_PFC_FUNCTION(scif_clk),
4296 SH_PFC_FUNCTION(sdhi0),
4297 SH_PFC_FUNCTION(sdhi1),
4298 SH_PFC_FUNCTION(sdhi2),
4299 SH_PFC_FUNCTION(sdhi3),
4300 SH_PFC_FUNCTION(ssi),
4301 SH_PFC_FUNCTION(usb0),
4302 SH_PFC_FUNCTION(usb1),
4303 SH_PFC_FUNCTION(usb2),
4304 };
4305
4306 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4307 #define F_(x, y) FN_##y
4308 #define FM(x) FN_##x
4309 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4310 0, 0,
4311 0, 0,
4312 0, 0,
4313 0, 0,
4314 0, 0,
4315 0, 0,
4316 0, 0,
4317 0, 0,
4318 0, 0,
4319 0, 0,
4320 0, 0,
4321 0, 0,
4322 0, 0,
4323 0, 0,
4324 0, 0,
4325 0, 0,
4326 GP_0_15_FN, GPSR0_15,
4327 GP_0_14_FN, GPSR0_14,
4328 GP_0_13_FN, GPSR0_13,
4329 GP_0_12_FN, GPSR0_12,
4330 GP_0_11_FN, GPSR0_11,
4331 GP_0_10_FN, GPSR0_10,
4332 GP_0_9_FN, GPSR0_9,
4333 GP_0_8_FN, GPSR0_8,
4334 GP_0_7_FN, GPSR0_7,
4335 GP_0_6_FN, GPSR0_6,
4336 GP_0_5_FN, GPSR0_5,
4337 GP_0_4_FN, GPSR0_4,
4338 GP_0_3_FN, GPSR0_3,
4339 GP_0_2_FN, GPSR0_2,
4340 GP_0_1_FN, GPSR0_1,
4341 GP_0_0_FN, GPSR0_0, }
4342 },
4343 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4344 0, 0,
4345 0, 0,
4346 0, 0,
4347 0, 0,
4348 GP_1_27_FN, GPSR1_27,
4349 GP_1_26_FN, GPSR1_26,
4350 GP_1_25_FN, GPSR1_25,
4351 GP_1_24_FN, GPSR1_24,
4352 GP_1_23_FN, GPSR1_23,
4353 GP_1_22_FN, GPSR1_22,
4354 GP_1_21_FN, GPSR1_21,
4355 GP_1_20_FN, GPSR1_20,
4356 GP_1_19_FN, GPSR1_19,
4357 GP_1_18_FN, GPSR1_18,
4358 GP_1_17_FN, GPSR1_17,
4359 GP_1_16_FN, GPSR1_16,
4360 GP_1_15_FN, GPSR1_15,
4361 GP_1_14_FN, GPSR1_14,
4362 GP_1_13_FN, GPSR1_13,
4363 GP_1_12_FN, GPSR1_12,
4364 GP_1_11_FN, GPSR1_11,
4365 GP_1_10_FN, GPSR1_10,
4366 GP_1_9_FN, GPSR1_9,
4367 GP_1_8_FN, GPSR1_8,
4368 GP_1_7_FN, GPSR1_7,
4369 GP_1_6_FN, GPSR1_6,
4370 GP_1_5_FN, GPSR1_5,
4371 GP_1_4_FN, GPSR1_4,
4372 GP_1_3_FN, GPSR1_3,
4373 GP_1_2_FN, GPSR1_2,
4374 GP_1_1_FN, GPSR1_1,
4375 GP_1_0_FN, GPSR1_0, }
4376 },
4377 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4378 0, 0,
4379 0, 0,
4380 0, 0,
4381 0, 0,
4382 0, 0,
4383 0, 0,
4384 0, 0,
4385 0, 0,
4386 0, 0,
4387 0, 0,
4388 0, 0,
4389 0, 0,
4390 0, 0,
4391 0, 0,
4392 0, 0,
4393 0, 0,
4394 0, 0,
4395 GP_2_14_FN, GPSR2_14,
4396 GP_2_13_FN, GPSR2_13,
4397 GP_2_12_FN, GPSR2_12,
4398 GP_2_11_FN, GPSR2_11,
4399 GP_2_10_FN, GPSR2_10,
4400 GP_2_9_FN, GPSR2_9,
4401 GP_2_8_FN, GPSR2_8,
4402 GP_2_7_FN, GPSR2_7,
4403 GP_2_6_FN, GPSR2_6,
4404 GP_2_5_FN, GPSR2_5,
4405 GP_2_4_FN, GPSR2_4,
4406 GP_2_3_FN, GPSR2_3,
4407 GP_2_2_FN, GPSR2_2,
4408 GP_2_1_FN, GPSR2_1,
4409 GP_2_0_FN, GPSR2_0, }
4410 },
4411 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4412 0, 0,
4413 0, 0,
4414 0, 0,
4415 0, 0,
4416 0, 0,
4417 0, 0,
4418 0, 0,
4419 0, 0,
4420 0, 0,
4421 0, 0,
4422 0, 0,
4423 0, 0,
4424 0, 0,
4425 0, 0,
4426 0, 0,
4427 0, 0,
4428 GP_3_15_FN, GPSR3_15,
4429 GP_3_14_FN, GPSR3_14,
4430 GP_3_13_FN, GPSR3_13,
4431 GP_3_12_FN, GPSR3_12,
4432 GP_3_11_FN, GPSR3_11,
4433 GP_3_10_FN, GPSR3_10,
4434 GP_3_9_FN, GPSR3_9,
4435 GP_3_8_FN, GPSR3_8,
4436 GP_3_7_FN, GPSR3_7,
4437 GP_3_6_FN, GPSR3_6,
4438 GP_3_5_FN, GPSR3_5,
4439 GP_3_4_FN, GPSR3_4,
4440 GP_3_3_FN, GPSR3_3,
4441 GP_3_2_FN, GPSR3_2,
4442 GP_3_1_FN, GPSR3_1,
4443 GP_3_0_FN, GPSR3_0, }
4444 },
4445 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4446 0, 0,
4447 0, 0,
4448 0, 0,
4449 0, 0,
4450 0, 0,
4451 0, 0,
4452 0, 0,
4453 0, 0,
4454 0, 0,
4455 0, 0,
4456 0, 0,
4457 0, 0,
4458 0, 0,
4459 0, 0,
4460 GP_4_17_FN, GPSR4_17,
4461 GP_4_16_FN, GPSR4_16,
4462 GP_4_15_FN, GPSR4_15,
4463 GP_4_14_FN, GPSR4_14,
4464 GP_4_13_FN, GPSR4_13,
4465 GP_4_12_FN, GPSR4_12,
4466 GP_4_11_FN, GPSR4_11,
4467 GP_4_10_FN, GPSR4_10,
4468 GP_4_9_FN, GPSR4_9,
4469 GP_4_8_FN, GPSR4_8,
4470 GP_4_7_FN, GPSR4_7,
4471 GP_4_6_FN, GPSR4_6,
4472 GP_4_5_FN, GPSR4_5,
4473 GP_4_4_FN, GPSR4_4,
4474 GP_4_3_FN, GPSR4_3,
4475 GP_4_2_FN, GPSR4_2,
4476 GP_4_1_FN, GPSR4_1,
4477 GP_4_0_FN, GPSR4_0, }
4478 },
4479 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4480 0, 0,
4481 0, 0,
4482 0, 0,
4483 0, 0,
4484 0, 0,
4485 0, 0,
4486 GP_5_25_FN, GPSR5_25,
4487 GP_5_24_FN, GPSR5_24,
4488 GP_5_23_FN, GPSR5_23,
4489 GP_5_22_FN, GPSR5_22,
4490 GP_5_21_FN, GPSR5_21,
4491 GP_5_20_FN, GPSR5_20,
4492 GP_5_19_FN, GPSR5_19,
4493 GP_5_18_FN, GPSR5_18,
4494 GP_5_17_FN, GPSR5_17,
4495 GP_5_16_FN, GPSR5_16,
4496 GP_5_15_FN, GPSR5_15,
4497 GP_5_14_FN, GPSR5_14,
4498 GP_5_13_FN, GPSR5_13,
4499 GP_5_12_FN, GPSR5_12,
4500 GP_5_11_FN, GPSR5_11,
4501 GP_5_10_FN, GPSR5_10,
4502 GP_5_9_FN, GPSR5_9,
4503 GP_5_8_FN, GPSR5_8,
4504 GP_5_7_FN, GPSR5_7,
4505 GP_5_6_FN, GPSR5_6,
4506 GP_5_5_FN, GPSR5_5,
4507 GP_5_4_FN, GPSR5_4,
4508 GP_5_3_FN, GPSR5_3,
4509 GP_5_2_FN, GPSR5_2,
4510 GP_5_1_FN, GPSR5_1,
4511 GP_5_0_FN, GPSR5_0, }
4512 },
4513 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4514 GP_6_31_FN, GPSR6_31,
4515 GP_6_30_FN, GPSR6_30,
4516 GP_6_29_FN, GPSR6_29,
4517 GP_6_28_FN, GPSR6_28,
4518 GP_6_27_FN, GPSR6_27,
4519 GP_6_26_FN, GPSR6_26,
4520 GP_6_25_FN, GPSR6_25,
4521 GP_6_24_FN, GPSR6_24,
4522 GP_6_23_FN, GPSR6_23,
4523 GP_6_22_FN, GPSR6_22,
4524 GP_6_21_FN, GPSR6_21,
4525 GP_6_20_FN, GPSR6_20,
4526 GP_6_19_FN, GPSR6_19,
4527 GP_6_18_FN, GPSR6_18,
4528 GP_6_17_FN, GPSR6_17,
4529 GP_6_16_FN, GPSR6_16,
4530 GP_6_15_FN, GPSR6_15,
4531 GP_6_14_FN, GPSR6_14,
4532 GP_6_13_FN, GPSR6_13,
4533 GP_6_12_FN, GPSR6_12,
4534 GP_6_11_FN, GPSR6_11,
4535 GP_6_10_FN, GPSR6_10,
4536 GP_6_9_FN, GPSR6_9,
4537 GP_6_8_FN, GPSR6_8,
4538 GP_6_7_FN, GPSR6_7,
4539 GP_6_6_FN, GPSR6_6,
4540 GP_6_5_FN, GPSR6_5,
4541 GP_6_4_FN, GPSR6_4,
4542 GP_6_3_FN, GPSR6_3,
4543 GP_6_2_FN, GPSR6_2,
4544 GP_6_1_FN, GPSR6_1,
4545 GP_6_0_FN, GPSR6_0, }
4546 },
4547 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4548 0, 0,
4549 0, 0,
4550 0, 0,
4551 0, 0,
4552 0, 0,
4553 0, 0,
4554 0, 0,
4555 0, 0,
4556 0, 0,
4557 0, 0,
4558 0, 0,
4559 0, 0,
4560 0, 0,
4561 0, 0,
4562 0, 0,
4563 0, 0,
4564 0, 0,
4565 0, 0,
4566 0, 0,
4567 0, 0,
4568 0, 0,
4569 0, 0,
4570 0, 0,
4571 0, 0,
4572 0, 0,
4573 0, 0,
4574 0, 0,
4575 0, 0,
4576 GP_7_3_FN, GPSR7_3,
4577 GP_7_2_FN, GPSR7_2,
4578 GP_7_1_FN, GPSR7_1,
4579 GP_7_0_FN, GPSR7_0, }
4580 },
4581 #undef F_
4582 #undef FM
4583
4584 #define F_(x, y) x,
4585 #define FM(x) FN_##x,
4586 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4587 IP0_31_28
4588 IP0_27_24
4589 IP0_23_20
4590 IP0_19_16
4591 IP0_15_12
4592 IP0_11_8
4593 IP0_7_4
4594 IP0_3_0 }
4595 },
4596 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4597 IP1_31_28
4598 IP1_27_24
4599 IP1_23_20
4600 IP1_19_16
4601 IP1_15_12
4602 IP1_11_8
4603 IP1_7_4
4604 IP1_3_0 }
4605 },
4606 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4607 IP2_31_28
4608 IP2_27_24
4609 IP2_23_20
4610 IP2_19_16
4611 IP2_15_12
4612 IP2_11_8
4613 IP2_7_4
4614 IP2_3_0 }
4615 },
4616 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4617 IP3_31_28
4618 IP3_27_24
4619 IP3_23_20
4620 IP3_19_16
4621 IP3_15_12
4622 IP3_11_8
4623 IP3_7_4
4624 IP3_3_0 }
4625 },
4626 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4627 IP4_31_28
4628 IP4_27_24
4629 IP4_23_20
4630 IP4_19_16
4631 IP4_15_12
4632 IP4_11_8
4633 IP4_7_4
4634 IP4_3_0 }
4635 },
4636 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4637 IP5_31_28
4638 IP5_27_24
4639 IP5_23_20
4640 IP5_19_16
4641 IP5_15_12
4642 IP5_11_8
4643 IP5_7_4
4644 IP5_3_0 }
4645 },
4646 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4647 IP6_31_28
4648 IP6_27_24
4649 IP6_23_20
4650 IP6_19_16
4651 IP6_15_12
4652 IP6_11_8
4653 IP6_7_4
4654 IP6_3_0 }
4655 },
4656 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4657 IP7_31_28
4658 IP7_27_24
4659 IP7_23_20
4660 IP7_19_16
4661 IP7_15_12
4662 IP7_11_8
4663 IP7_7_4
4664 IP7_3_0 }
4665 },
4666 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4667 IP8_31_28
4668 IP8_27_24
4669 IP8_23_20
4670 IP8_19_16
4671 IP8_15_12
4672 IP8_11_8
4673 IP8_7_4
4674 IP8_3_0 }
4675 },
4676 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4677 IP9_31_28
4678 IP9_27_24
4679 IP9_23_20
4680 IP9_19_16
4681 IP9_15_12
4682 IP9_11_8
4683 IP9_7_4
4684 IP9_3_0 }
4685 },
4686 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
4687 IP10_31_28
4688 IP10_27_24
4689 IP10_23_20
4690 IP10_19_16
4691 IP10_15_12
4692 IP10_11_8
4693 IP10_7_4
4694 IP10_3_0 }
4695 },
4696 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
4697 IP11_31_28
4698 IP11_27_24
4699 IP11_23_20
4700 IP11_19_16
4701 IP11_15_12
4702 IP11_11_8
4703 IP11_7_4
4704 IP11_3_0 }
4705 },
4706 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
4707 IP12_31_28
4708 IP12_27_24
4709 IP12_23_20
4710 IP12_19_16
4711 IP12_15_12
4712 IP12_11_8
4713 IP12_7_4
4714 IP12_3_0 }
4715 },
4716 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
4717 IP13_31_28
4718 IP13_27_24
4719 IP13_23_20
4720 IP13_19_16
4721 IP13_15_12
4722 IP13_11_8
4723 IP13_7_4
4724 IP13_3_0 }
4725 },
4726 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
4727 IP14_31_28
4728 IP14_27_24
4729 IP14_23_20
4730 IP14_19_16
4731 IP14_15_12
4732 IP14_11_8
4733 IP14_7_4
4734 IP14_3_0 }
4735 },
4736 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
4737 IP15_31_28
4738 IP15_27_24
4739 IP15_23_20
4740 IP15_19_16
4741 IP15_15_12
4742 IP15_11_8
4743 IP15_7_4
4744 IP15_3_0 }
4745 },
4746 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
4747 IP16_31_28
4748 IP16_27_24
4749 IP16_23_20
4750 IP16_19_16
4751 IP16_15_12
4752 IP16_11_8
4753 IP16_7_4
4754 IP16_3_0 }
4755 },
4756 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
4757 /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4758 /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4759 /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4760 /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4761 /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4762 /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4763 IP17_7_4
4764 IP17_3_0 }
4765 },
4766 #undef F_
4767 #undef FM
4768
4769 #define F_(x, y) x,
4770 #define FM(x) FN_##x,
4771 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4772 1, 2, 2, 3, 1, 1, 2, 1, 1, 1,
4773 2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) {
4774 0, 0, /* RESERVED 31 */
4775 MOD_SEL0_30_29
4776 MOD_SEL0_28_27
4777 MOD_SEL0_26_25_24
4778 MOD_SEL0_23
4779 MOD_SEL0_22
4780 MOD_SEL0_21_20
4781 MOD_SEL0_19
4782 MOD_SEL0_18
4783 MOD_SEL0_17
4784 MOD_SEL0_16_15
4785 MOD_SEL0_14
4786 MOD_SEL0_13
4787 MOD_SEL0_12
4788 MOD_SEL0_11
4789 MOD_SEL0_10
4790 MOD_SEL0_9
4791 MOD_SEL0_8
4792 MOD_SEL0_7_6
4793 MOD_SEL0_5_4
4794 MOD_SEL0_3
4795 MOD_SEL0_2_1
4796 0, 0, /* RESERVED 0 */ }
4797 },
4798 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4799 2, 3, 1, 2, 3, 1, 1, 2, 1,
4800 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
4801 MOD_SEL1_31_30
4802 MOD_SEL1_29_28_27
4803 MOD_SEL1_26
4804 MOD_SEL1_25_24
4805 MOD_SEL1_23_22_21
4806 MOD_SEL1_20
4807 MOD_SEL1_19
4808 MOD_SEL1_18_17
4809 MOD_SEL1_16
4810 MOD_SEL1_15_14
4811 MOD_SEL1_13
4812 MOD_SEL1_12
4813 MOD_SEL1_11
4814 MOD_SEL1_10
4815 MOD_SEL1_9
4816 0, 0, 0, 0, /* RESERVED 8, 7 */
4817 MOD_SEL1_6
4818 MOD_SEL1_5
4819 MOD_SEL1_4
4820 MOD_SEL1_3
4821 MOD_SEL1_2
4822 MOD_SEL1_1
4823 MOD_SEL1_0 }
4824 },
4825 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
4826 1, 1, 1, 1, 4, 4, 4,
4827 4, 4, 4, 1, 2, 1) {
4828 MOD_SEL2_31
4829 MOD_SEL2_30
4830 MOD_SEL2_29
4831 /* RESERVED 28 */
4832 0, 0,
4833 /* RESERVED 27, 26, 25, 24 */
4834 0, 0, 0, 0, 0, 0, 0, 0,
4835 0, 0, 0, 0, 0, 0, 0, 0,
4836 /* RESERVED 23, 22, 21, 20 */
4837 0, 0, 0, 0, 0, 0, 0, 0,
4838 0, 0, 0, 0, 0, 0, 0, 0,
4839 /* RESERVED 19, 18, 17, 16 */
4840 0, 0, 0, 0, 0, 0, 0, 0,
4841 0, 0, 0, 0, 0, 0, 0, 0,
4842 /* RESERVED 15, 14, 13, 12 */
4843 0, 0, 0, 0, 0, 0, 0, 0,
4844 0, 0, 0, 0, 0, 0, 0, 0,
4845 /* RESERVED 11, 10, 9, 8 */
4846 0, 0, 0, 0, 0, 0, 0, 0,
4847 0, 0, 0, 0, 0, 0, 0, 0,
4848 /* RESERVED 7, 6, 5, 4 */
4849 0, 0, 0, 0, 0, 0, 0, 0,
4850 0, 0, 0, 0, 0, 0, 0, 0,
4851 /* RESERVED 3 */
4852 0, 0,
4853 /* RESERVED 2, 1 */
4854 0, 0, 0, 0,
4855 MOD_SEL2_0 }
4856 },
4857 { },
4858 };
4859
4860 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
4861 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
4862 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
4863 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
4864 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
4865 } },
4866 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
4867 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
4868 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
4869 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
4870 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
4871 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
4872 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
4873 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
4874 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
4875 } },
4876 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
4877 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
4878 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
4879 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
4880 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
4881 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
4882 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
4883 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
4884 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
4885 } },
4886 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
4887 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
4888 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
4889 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
4890 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
4891 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
4892 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
4893 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
4894 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
4895 } },
4896 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
4897 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
4898 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
4899 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
4900 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
4901 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
4902 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
4903 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
4904 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
4905 } },
4906 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
4907 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
4908 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
4909 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
4910 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
4911 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
4912 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
4913 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
4914 } },
4915 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
4916 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
4917 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
4918 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
4919 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
4920 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
4921 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
4922 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
4923 } },
4924 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
4925 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
4926 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
4927 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
4928 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
4929 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
4930 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
4931 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
4932 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
4933 } },
4934 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
4935 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
4936 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
4937 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
4938 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
4939 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
4940 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
4941 } },
4942 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
4943 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
4944 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
4945 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
4946 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
4947 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
4948 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
4949 } },
4950 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
4951 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
4952 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
4953 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
4954 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
4955 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
4956 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
4957 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
4958 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
4959 } },
4960 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
4961 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
4962 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
4963 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
4964 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
4965 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
4966 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
4967 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
4968 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
4969 } },
4970 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
4971 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
4972 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
4973 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
4974 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
4975 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
4976 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
4977 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
4978 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
4979 } },
4980 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
4981 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
4982 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
4983 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
4984 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
4985 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
4986 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
4987 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
4988 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
4989 } },
4990 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
4991 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
4992 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
4993 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
4994 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
4995 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
4996 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
4997 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
4998 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
4999 } },
5000 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5001 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5002 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5003 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5004 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5005 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5006 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5007 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5008 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5009 } },
5010 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5011 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5012 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5013 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5014 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5015 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5016 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5017 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5018 } },
5019 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5020 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5021 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5022 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5023 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5024 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK34 */
5025 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS34 */
5026 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5027 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5028 } },
5029 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5030 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5031 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5032 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5033 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5034 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5035 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5036 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5037 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5038 } },
5039 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5040 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5041 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5042 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5043 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5044 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5045 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5046 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5047 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5048 } },
5049 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5050 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5051 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5052 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5053 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5054 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5055 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB31_PWEN */
5056 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB31_OVC */
5057 } },
5058 { },
5059 };
5060
5061 static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5062 {
5063 int bit = -EINVAL;
5064
5065 *pocctrl = 0xe6060380;
5066
5067 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5068 bit = pin & 0x1f;
5069
5070 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5071 bit = (pin & 0x1f) + 12;
5072
5073 return bit;
5074 }
5075
5076 static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
5077 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
5078 };
5079
5080 const struct sh_pfc_soc_info r8a7795_pinmux_info = {
5081 .name = "r8a77950_pfc",
5082 .ops = &r8a7795_pinmux_ops,
5083 .unlock_reg = 0xe6060000, /* PMMR */
5084
5085 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5086
5087 .pins = pinmux_pins,
5088 .nr_pins = ARRAY_SIZE(pinmux_pins),
5089 .groups = pinmux_groups,
5090 .nr_groups = ARRAY_SIZE(pinmux_groups),
5091 .functions = pinmux_functions,
5092 .nr_functions = ARRAY_SIZE(pinmux_functions),
5093
5094 .cfg_regs = pinmux_config_regs,
5095 .drive_regs = pinmux_drive_regs,
5096
5097 .pinmux_data = pinmux_data,
5098 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5099 };
Linux kernel - Deliverables
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