drivers/pinctrl/sh-pfc/sh_pfc.h

   1 /*
   2  * SuperH Pin Function Controller Support
   3  *
   4  * Copyright (c) 2008 Magnus Damm
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #ifndef __SH_PFC_H
  12 #define __SH_PFC_H
  13
  14 #include <linux/bug.h>
  15 #include <linux/pinctrl/pinconf-generic.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/stringify.h>
  18
  19 enum {
  20         PINMUX_TYPE_NONE,
  21         PINMUX_TYPE_FUNCTION,
  22         PINMUX_TYPE_GPIO,
  23         PINMUX_TYPE_OUTPUT,
  24         PINMUX_TYPE_INPUT,
  25 };
  26
  27 #define SH_PFC_PIN_CFG_INPUT            (1 << 0)
  28 #define SH_PFC_PIN_CFG_OUTPUT           (1 << 1)
  29 #define SH_PFC_PIN_CFG_PULL_UP          (1 << 2)
  30 #define SH_PFC_PIN_CFG_PULL_DOWN        (1 << 3)
  31 #define SH_PFC_PIN_CFG_IO_VOLTAGE       (1 << 4)
  32 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH   (1 << 5)
  33 #define SH_PFC_PIN_CFG_NO_GPIO          (1 << 31)
  34
  35 struct sh_pfc_pin {
  36         u16 pin;
  37         u16 enum_id;
  38         const char *name;
  39         unsigned int configs;
  40 };
  41
  42 #define SH_PFC_PIN_GROUP(n)                             \
  43         {                                               \
  44                 .name = #n,                             \
  45                 .pins = n##_pins,                       \
  46                 .mux = n##_mux,                         \
  47                 .nr_pins = ARRAY_SIZE(n##_pins),        \
  48         }
  49
  50 struct sh_pfc_pin_group {
  51         const char *name;
  52         const unsigned int *pins;
  53         const unsigned int *mux;
  54         unsigned int nr_pins;
  55 };
  56
  57 /*
  58  * Using union vin_data saves memory occupied by the VIN data pins.
  59  * VIN_DATA_PIN_GROUP() is  a macro  used  to describe the VIN pin groups
  60  * in this case.
  61  */
  62 #define VIN_DATA_PIN_GROUP(n, s)                                \
  63         {                                                       \
  64                 .name = #n#s,                                   \
  65                 .pins = n##_pins.data##s,                       \
  66                 .mux = n##_mux.data##s,                         \
  67                 .nr_pins = ARRAY_SIZE(n##_pins.data##s),        \
  68         }
  69
  70 union vin_data {
  71         unsigned int data24[24];
  72         unsigned int data20[20];
  73         unsigned int data16[16];
  74         unsigned int data12[12];
  75         unsigned int data10[10];
  76         unsigned int data8[8];
  77         unsigned int data4[4];
  78 };
  79
  80 #define SH_PFC_FUNCTION(n)                              \
  81         {                                               \
  82                 .name = #n,                             \
  83                 .groups = n##_groups,                   \
  84                 .nr_groups = ARRAY_SIZE(n##_groups),    \
  85         }
  86
  87 struct sh_pfc_function {
  88         const char *name;
  89         const char * const *groups;
  90         unsigned int nr_groups;
  91 };
  92
  93 struct pinmux_func {
  94         u16 enum_id;
  95         const char *name;
  96 };
  97
  98 struct pinmux_cfg_reg {
  99         u32 reg;
 100         u8 reg_width, field_width;
 101         const u16 *enum_ids;
 102         const u8 *var_field_width;
 103 };
 104
 105 /*
 106  * Describe a config register consisting of several fields of the same width
 107  *   - name: Register name (unused, for documentation purposes only)
 108  *   - r: Physical register address
 109  *   - r_width: Width of the register (in bits)
 110  *   - f_width: Width of the fixed-width register fields (in bits)
 111  * This macro must be followed by initialization data: For each register field
 112  * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
 113  * one for each possible combination of the register field bit values.
 114  */
 115 #define PINMUX_CFG_REG(name, r, r_width, f_width) \
 116         .reg = r, .reg_width = r_width, .field_width = f_width,         \
 117         .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
 118
 119 /*
 120  * Describe a config register consisting of several fields of different widths
 121  *   - name: Register name (unused, for documentation purposes only)
 122  *   - r: Physical register address
 123  *   - r_width: Width of the register (in bits)
 124  *   - var_fw0, var_fwn...: List of widths of the register fields (in bits),
 125  *                          From left to right (i.e. MSB to LSB)
 126  * This macro must be followed by initialization data: For each register field
 127  * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
 128  * one for each possible combination of the register field bit values.
 129  */
 130 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
 131         .reg = r, .reg_width = r_width, \
 132         .var_field_width = (const u8 [r_width]) \
 133                 { var_fw0, var_fwn, 0 }, \
 134         .enum_ids = (const u16 [])
 135
 136 struct pinmux_drive_reg_field {
 137         u16 pin;
 138         u8 offset;
 139         u8 size;
 140 };
 141
 142 struct pinmux_drive_reg {
 143         u32 reg;
 144         const struct pinmux_drive_reg_field fields[8];
 145 };
 146
 147 #define PINMUX_DRIVE_REG(name, r) \
 148         .reg = r, \
 149         .fields =
 150
 151 struct pinmux_data_reg {
 152         u32 reg;
 153         u8 reg_width;
 154         const u16 *enum_ids;
 155 };
 156
 157 /*
 158  * Describe a data register
 159  *   - name: Register name (unused, for documentation purposes only)
 160  *   - r: Physical register address
 161  *   - r_width: Width of the register (in bits)
 162  * This macro must be followed by initialization data: For each register bit
 163  * (from left to right, i.e. MSB to LSB), one enum ID must be specified.
 164  */
 165 #define PINMUX_DATA_REG(name, r, r_width) \
 166         .reg = r, .reg_width = r_width, \
 167         .enum_ids = (const u16 [r_width]) \
 168
 169 struct pinmux_irq {
 170         const short *gpios;
 171 };
 172
 173 /*
 174  * Describe the mapping from GPIOs to a single IRQ
 175  *   - ids...: List of GPIOs that are mapped to the same IRQ
 176  */
 177 #define PINMUX_IRQ(ids...)                         \
 178         { .gpios = (const short []) { ids, -1 } }
 179
 180 struct pinmux_range {
 181         u16 begin;
 182         u16 end;
 183         u16 force;
 184 };
 185
 186 struct sh_pfc_window {
 187         phys_addr_t phys;
 188         void __iomem *virt;
 189         unsigned long size;
 190 };
 191
 192 struct sh_pfc_pin_range;
 193
 194 struct sh_pfc {
 195         struct device *dev;
 196         const struct sh_pfc_soc_info *info;
 197         spinlock_t lock;
 198
 199         unsigned int num_windows;
 200         struct sh_pfc_window *windows;
 201         unsigned int num_irqs;
 202         unsigned int *irqs;
 203
 204         struct sh_pfc_pin_range *ranges;
 205         unsigned int nr_ranges;
 206
 207         unsigned int nr_gpio_pins;
 208
 209         struct sh_pfc_chip *gpio;
 210 };
 211
 212 struct sh_pfc_soc_operations {
 213         int (*init)(struct sh_pfc *pfc);
 214         unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
 215         void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
 216                          unsigned int bias);
 217         int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
 218 };
 219
 220 struct sh_pfc_soc_info {
 221         const char *name;
 222         const struct sh_pfc_soc_operations *ops;
 223
 224         struct pinmux_range input;
 225         struct pinmux_range output;
 226         struct pinmux_range function;
 227
 228         const struct sh_pfc_pin *pins;
 229         unsigned int nr_pins;
 230         const struct sh_pfc_pin_group *groups;
 231         unsigned int nr_groups;
 232         const struct sh_pfc_function *functions;
 233         unsigned int nr_functions;
 234
 235 #ifdef CONFIG_SUPERH
 236         const struct pinmux_func *func_gpios;
 237         unsigned int nr_func_gpios;
 238 #endif
 239
 240         const struct pinmux_cfg_reg *cfg_regs;
 241         const struct pinmux_drive_reg *drive_regs;
 242         const struct pinmux_data_reg *data_regs;
 243
 244         const u16 *pinmux_data;
 245         unsigned int pinmux_data_size;
 246
 247         const struct pinmux_irq *gpio_irq;
 248         unsigned int gpio_irq_size;
 249
 250         u32 unlock_reg;
 251 };
 252
 253 extern const struct sh_pfc_soc_info emev2_pinmux_info;
 254 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
 255 extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
 256 extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
 257 extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
 258 extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
 259 extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
 260 extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
 261 extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
 262 extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
 263 extern const struct sh_pfc_soc_info sh7203_pinmux_info;
 264 extern const struct sh_pfc_soc_info sh7264_pinmux_info;
 265 extern const struct sh_pfc_soc_info sh7269_pinmux_info;
 266 extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
 267 extern const struct sh_pfc_soc_info sh7720_pinmux_info;
 268 extern const struct sh_pfc_soc_info sh7722_pinmux_info;
 269 extern const struct sh_pfc_soc_info sh7723_pinmux_info;
 270 extern const struct sh_pfc_soc_info sh7724_pinmux_info;
 271 extern const struct sh_pfc_soc_info sh7734_pinmux_info;
 272 extern const struct sh_pfc_soc_info sh7757_pinmux_info;
 273 extern const struct sh_pfc_soc_info sh7785_pinmux_info;
 274 extern const struct sh_pfc_soc_info sh7786_pinmux_info;
 275 extern const struct sh_pfc_soc_info shx3_pinmux_info;
 276
 277 /* -----------------------------------------------------------------------------
 278  * Helper macros to create pin and port lists
 279  */
 280
 281 /*
 282  * sh_pfc_soc_info pinmux_data array macros
 283  */
 284
 285 /*
 286  * Describe generic pinmux data
 287  *   - data_or_mark: *_DATA or *_MARK enum ID
 288  *   - ids...: List of enum IDs to associate with data_or_mark
 289  */
 290 #define PINMUX_DATA(data_or_mark, ids...)       data_or_mark, ids, 0
 291
 292 /*
 293  * Describe a pinmux configuration without GPIO function that needs
 294  * configuration in a Peripheral Function Select Register (IPSR)
 295  *   - ipsr: IPSR field (unused, for documentation purposes only)
 296  *   - fn: Function name, referring to a field in the IPSR
 297  */
 298 #define PINMUX_IPSR_NOGP(ipsr, fn)                                      \
 299         PINMUX_DATA(fn##_MARK, FN_##fn)
 300
 301 /*
 302  * Describe a pinmux configuration with GPIO function that needs configuration
 303  * in both a Peripheral Function Select Register (IPSR) and in a
 304  * GPIO/Peripheral Function Select Register (GPSR)
 305  *   - ipsr: IPSR field
 306  *   - fn: Function name, also referring to the IPSR field
 307  */
 308 #define PINMUX_IPSR_GPSR(ipsr, fn)                                      \
 309         PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
 310
 311 /*
 312  * Describe a pinmux configuration without GPIO function that needs
 313  * configuration in a Peripheral Function Select Register (IPSR), and where the
 314  * pinmux function has a representation in a Module Select Register (MOD_SEL).
 315  *   - ipsr: IPSR field (unused, for documentation purposes only)
 316  *   - fn: Function name, also referring to the IPSR field
 317  *   - msel: Module selector
 318  */
 319 #define PINMUX_IPSR_NOGM(ipsr, fn, msel)                                \
 320         PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
 321
 322 /*
 323  * Describe a pinmux configuration with GPIO function where the pinmux function
 324  * has no representation in a Peripheral Function Select Register (IPSR), but
 325  * instead solely depends on a group selection.
 326  *   - gpsr: GPSR field
 327  *   - fn: Function name, also referring to the GPSR field
 328  *   - gsel: Group selector
 329  */
 330 #define PINMUX_IPSR_NOFN(gpsr, fn, gsel)                                \
 331         PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
 332
 333 /*
 334  * Describe a pinmux configuration with GPIO function that needs configuration
 335  * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
 336  * Function Select Register (GPSR), and where the pinmux function has a
 337  * representation in a Module Select Register (MOD_SEL).
 338  *   - ipsr: IPSR field
 339  *   - fn: Function name, also referring to the IPSR field
 340  *   - msel: Module selector
 341  */
 342 #define PINMUX_IPSR_MSEL(ipsr, fn, msel)                                \
 343         PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
 344
 345 /*
 346  * Describe a pinmux configuration for a single-function pin with GPIO
 347  * capability.
 348  *   - fn: Function name
 349  */
 350 #define PINMUX_SINGLE(fn)                                               \
 351         PINMUX_DATA(fn##_MARK, FN_##fn)
 352
 353 /*
 354  * GP port style (32 ports banks)
 355  */
 356
 357 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
 358 #define PORT_GP_1(bank, pin, fn, sfx)   PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
 359
 360 #define PORT_GP_CFG_4(bank, fn, sfx, cfg)                                               \
 361         PORT_GP_CFG_1(bank, 0,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 1,  fn, sfx, cfg),   \
 362         PORT_GP_CFG_1(bank, 2,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 3,  fn, sfx, cfg)
 363 #define PORT_GP_4(bank, fn, sfx)        PORT_GP_CFG_4(bank, fn, sfx, 0)
 364
 365 #define PORT_GP_CFG_8(bank, fn, sfx, cfg)                                               \
 366         PORT_GP_CFG_4(bank, fn, sfx, cfg),                                              \
 367         PORT_GP_CFG_1(bank, 4,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 5,  fn, sfx, cfg),   \
 368         PORT_GP_CFG_1(bank, 6,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 7,  fn, sfx, cfg)
 369 #define PORT_GP_8(bank, fn, sfx)        PORT_GP_CFG_8(bank, fn, sfx, 0)
 370
 371 #define PORT_GP_CFG_9(bank, fn, sfx, cfg)                                               \
 372         PORT_GP_CFG_8(bank, fn, sfx, cfg),                                              \
 373         PORT_GP_CFG_1(bank, 8,  fn, sfx, cfg)
 374 #define PORT_GP_9(bank, fn, sfx)        PORT_GP_CFG_9(bank, fn, sfx, 0)
 375
 376 #define PORT_GP_CFG_12(bank, fn, sfx, cfg)                                              \
 377         PORT_GP_CFG_8(bank, fn, sfx, cfg),                                              \
 378         PORT_GP_CFG_1(bank, 8,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 9,  fn, sfx, cfg),   \
 379         PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
 380 #define PORT_GP_12(bank, fn, sfx)       PORT_GP_CFG_12(bank, fn, sfx, 0)
 381
 382 #define PORT_GP_CFG_14(bank, fn, sfx, cfg)                                              \
 383         PORT_GP_CFG_12(bank, fn, sfx, cfg),                                             \
 384         PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
 385 #define PORT_GP_14(bank, fn, sfx)       PORT_GP_CFG_14(bank, fn, sfx, 0)
 386
 387 #define PORT_GP_CFG_15(bank, fn, sfx, cfg)                                              \
 388         PORT_GP_CFG_14(bank, fn, sfx, cfg),                                             \
 389         PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
 390 #define PORT_GP_15(bank, fn, sfx)       PORT_GP_CFG_15(bank, fn, sfx, 0)
 391
 392 #define PORT_GP_CFG_16(bank, fn, sfx, cfg)                                              \
 393         PORT_GP_CFG_14(bank, fn, sfx, cfg),                                             \
 394         PORT_GP_CFG_1(bank, 14, fn, sfx, cfg), PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
 395 #define PORT_GP_16(bank, fn, sfx)       PORT_GP_CFG_16(bank, fn, sfx, 0)
 396
 397 #define PORT_GP_CFG_18(bank, fn, sfx, cfg)                                              \
 398         PORT_GP_CFG_16(bank, fn, sfx, cfg),                                             \
 399         PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
 400 #define PORT_GP_18(bank, fn, sfx)       PORT_GP_CFG_18(bank, fn, sfx, 0)
 401
 402 #define PORT_GP_CFG_26(bank, fn, sfx, cfg)                                              \
 403         PORT_GP_CFG_18(bank, fn, sfx, cfg),                                             \
 404         PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg),   \
 405         PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg),   \
 406         PORT_GP_CFG_1(bank, 22, fn, sfx, cfg), PORT_GP_CFG_1(bank, 23, fn, sfx, cfg),   \
 407         PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
 408 #define PORT_GP_26(bank, fn, sfx)       PORT_GP_CFG_26(bank, fn, sfx, 0)
 409
 410 #define PORT_GP_CFG_28(bank, fn, sfx, cfg)                                              \
 411         PORT_GP_CFG_26(bank, fn, sfx, cfg),                                             \
 412         PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
 413 #define PORT_GP_28(bank, fn, sfx)       PORT_GP_CFG_28(bank, fn, sfx, 0)
 414
 415 #define PORT_GP_CFG_30(bank, fn, sfx, cfg)                                              \
 416         PORT_GP_CFG_28(bank, fn, sfx, cfg),                                             \
 417         PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
 418 #define PORT_GP_30(bank, fn, sfx)       PORT_GP_CFG_30(bank, fn, sfx, 0)
 419
 420 #define PORT_GP_CFG_32(bank, fn, sfx, cfg)                                              \
 421         PORT_GP_CFG_30(bank, fn, sfx, cfg),                                             \
 422         PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
 423 #define PORT_GP_32(bank, fn, sfx)       PORT_GP_CFG_32(bank, fn, sfx, 0)
 424
 425 #define PORT_GP_32_REV(bank, fn, sfx)                                   \
 426         PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),     \
 427         PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),     \
 428         PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),     \
 429         PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),     \
 430         PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),     \
 431         PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),     \
 432         PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),     \
 433         PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),     \
 434         PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),     \
 435         PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),     \
 436         PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),     \
 437         PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),     \
 438         PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),     \
 439         PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),     \
 440         PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),     \
 441         PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)
 442
 443 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
 444 #define _GP_ALL(bank, pin, name, sfx, cfg)      name##_##sfx
 445 #define GP_ALL(str)                     CPU_ALL_PORT(_GP_ALL, str)
 446
 447 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
 448 #define _GP_GPIO(bank, _pin, _name, sfx, cfg)                           \
 449         {                                                               \
 450                 .pin = (bank * 32) + _pin,                              \
 451                 .name = __stringify(_name),                             \
 452                 .enum_id = _name##_DATA,                                \
 453                 .configs = cfg,                                         \
 454         }
 455 #define PINMUX_GPIO_GP_ALL()            CPU_ALL_PORT(_GP_GPIO, unused)
 456
 457 /* PINMUX_DATA_GP_ALL -  Expand to a list of name_DATA, name_FN marks */
 458 #define _GP_DATA(bank, pin, name, sfx, cfg)     PINMUX_DATA(name##_DATA, name##_FN)
 459 #define PINMUX_DATA_GP_ALL()            CPU_ALL_PORT(_GP_DATA, unused)
 460
 461 /*
 462  * PORT style (linear pin space)
 463  */
 464
 465 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
 466
 467 #define PORT_10(pn, fn, pfx, sfx)                                         \
 468         PORT_1(pn,   fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx),     \
 469         PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx),     \
 470         PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx),     \
 471         PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx),     \
 472         PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
 473
 474 #define PORT_90(pn, fn, pfx, sfx)                                         \
 475         PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
 476         PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
 477         PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
 478         PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
 479         PORT_10(pn+90, fn, pfx##9, sfx)
 480
 481 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
 482 #define _PORT_ALL(pn, pfx, sfx)         pfx##_##sfx
 483 #define PORT_ALL(str)                   CPU_ALL_PORT(_PORT_ALL, PORT, str)
 484
 485 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
 486 #define PINMUX_GPIO(_pin)                                               \
 487         [GPIO_##_pin] = {                                               \
 488                 .pin = (u16)-1,                                         \
 489                 .name = __stringify(GPIO_##_pin),                       \
 490                 .enum_id = _pin##_DATA,                                 \
 491         }
 492
 493 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
 494 #define SH_PFC_PIN_CFG(_pin, cfgs)                                      \
 495         {                                                               \
 496                 .pin = _pin,                                            \
 497                 .name = __stringify(PORT##_pin),                        \
 498                 .enum_id = PORT##_pin##_DATA,                           \
 499                 .configs = cfgs,                                        \
 500         }
 501
 502 /* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
 503 #define SH_PFC_PIN_NAMED(row, col, _name)                               \
 504         {                                                               \
 505                 .pin = PIN_NUMBER(row, col),                            \
 506                 .name = __stringify(PIN_##_name),                       \
 507                 .configs = SH_PFC_PIN_CFG_NO_GPIO,                      \
 508         }
 509
 510 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
 511  *                   PORT_name_OUT, PORT_name_IN marks
 512  */
 513 #define _PORT_DATA(pn, pfx, sfx)                                        \
 514         PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0,                  \
 515                     PORT##pfx##_OUT, PORT##pfx##_IN)
 516 #define PINMUX_DATA_ALL()               CPU_ALL_PORT(_PORT_DATA, , unused)
 517
 518 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
 519 #define PINMUX_GPIO_FN(gpio, base, data_or_mark)                        \
 520         [gpio - (base)] = {                                             \
 521                 .name = __stringify(gpio),                              \
 522                 .enum_id = data_or_mark,                                \
 523         }
 524 #define GPIO_FN(str)                                                    \
 525         PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
 526
 527 /*
 528  * PORTnCR helper macro for SH-Mobile/R-Mobile
 529  */
 530 #define PORTCR(nr, reg)                                                 \
 531         {                                                               \
 532                 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
 533                         /* PULMD[1:0], handled by .set_bias() */        \
 534                         0, 0, 0, 0,                                     \
 535                         /* IE and OE */                                 \
 536                         0, PORT##nr##_OUT, PORT##nr##_IN, 0,            \
 537                         /* SEC, not supported */                        \
 538                         0, 0,                                           \
 539                         /* PTMD[2:0] */                                 \
 540                         PORT##nr##_FN0, PORT##nr##_FN1,                 \
 541                         PORT##nr##_FN2, PORT##nr##_FN3,                 \
 542                         PORT##nr##_FN4, PORT##nr##_FN5,                 \
 543                         PORT##nr##_FN6, PORT##nr##_FN7                  \
 544                 }                                                       \
 545         }
 546
 547 /*
 548  * GPIO number helper macro for R-Car
 549  */
 550 #define RCAR_GP_PIN(bank, pin)          (((bank) * 32) + (pin))
 551
 552 #endif /* __SH_PFC_H */