drivers/pwm/pwm-omap-dmtimer.c

   1 /*
   2  * Copyright (c) 2015 Neil Armstrong <narmstrong@baylibre.com>
   3  * Copyright (c) 2014 Joachim Eastwood <manabian@gmail.com>
   4  * Copyright (c) 2012 NeilBrown <neilb@suse.de>
   5  * Heavily based on earlier code which is:
   6  * Copyright (c) 2010 Grant Erickson <marathon96@gmail.com>
   7  *
   8  * Also based on pwm-samsung.c
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * version 2 as published by the Free Software Foundation.
  13  *
  14  * Description:
  15  *   This file is the core OMAP support for the generic, Linux
  16  *   PWM driver / controller, using the OMAP's dual-mode timers.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/err.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/mutex.h>
  24 #include <linux/of.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/platform_data/pwm_omap_dmtimer.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/pwm.h>
  30 #include <linux/slab.h>
  31 #include <linux/time.h>
  32
  33 #define DM_TIMER_LOAD_MIN 0xfffffffe
  34 #define DM_TIMER_MAX      0xffffffff
  35
  36 struct pwm_omap_dmtimer_chip {
  37         struct pwm_chip chip;
  38         struct mutex mutex;
  39         pwm_omap_dmtimer *dm_timer;
  40         struct pwm_omap_dmtimer_pdata *pdata;
  41         struct platform_device *dm_timer_pdev;
  42 };
  43
  44 static inline struct pwm_omap_dmtimer_chip *
  45 to_pwm_omap_dmtimer_chip(struct pwm_chip *chip)
  46 {
  47         return container_of(chip, struct pwm_omap_dmtimer_chip, chip);
  48 }
  49
  50 static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns)
  51 {
  52         return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC);
  53 }
  54
  55 static void pwm_omap_dmtimer_start(struct pwm_omap_dmtimer_chip *omap)
  56 {
  57         /*
  58          * According to OMAP 4 TRM section 22.2.4.10 the counter should be
  59          * started at 0xFFFFFFFE when overflow and match is used to ensure
  60          * that the PWM line is toggled on the first event.
  61          *
  62          * Note that omap_dm_timer_enable/disable is for register access and
  63          * not the timer counter itself.
  64          */
  65         omap->pdata->enable(omap->dm_timer);
  66         omap->pdata->write_counter(omap->dm_timer, DM_TIMER_LOAD_MIN);
  67         omap->pdata->disable(omap->dm_timer);
  68
  69         omap->pdata->start(omap->dm_timer);
  70 }
  71
  72 static int pwm_omap_dmtimer_enable(struct pwm_chip *chip,
  73                                    struct pwm_device *pwm)
  74 {
  75         struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
  76
  77         mutex_lock(&omap->mutex);
  78         pwm_omap_dmtimer_start(omap);
  79         mutex_unlock(&omap->mutex);
  80
  81         return 0;
  82 }
  83
  84 static void pwm_omap_dmtimer_disable(struct pwm_chip *chip,
  85                                      struct pwm_device *pwm)
  86 {
  87         struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
  88
  89         mutex_lock(&omap->mutex);
  90         omap->pdata->stop(omap->dm_timer);
  91         mutex_unlock(&omap->mutex);
  92 }
  93
  94 static int pwm_omap_dmtimer_config(struct pwm_chip *chip,
  95                                    struct pwm_device *pwm,
  96                                    int duty_ns, int period_ns)
  97 {
  98         struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
  99         u32 period_cycles, duty_cycles;
 100         u32 load_value, match_value;
 101         struct clk *fclk;
 102         unsigned long clk_rate;
 103         bool timer_active;
 104
 105         dev_dbg(chip->dev, "duty cycle: %d, period %d\n", duty_ns, period_ns);
 106
 107         mutex_lock(&omap->mutex);
 108         if (duty_ns == pwm_get_duty_cycle(pwm) &&
 109             period_ns == pwm_get_period(pwm)) {
 110                 /* No change - don't cause any transients. */
 111                 mutex_unlock(&omap->mutex);
 112                 return 0;
 113         }
 114
 115         fclk = omap->pdata->get_fclk(omap->dm_timer);
 116         if (!fclk) {
 117                 dev_err(chip->dev, "invalid pmtimer fclk\n");
 118                 goto err_einval;
 119         }
 120
 121         clk_rate = clk_get_rate(fclk);
 122         if (!clk_rate) {
 123                 dev_err(chip->dev, "invalid pmtimer fclk rate\n");
 124                 goto err_einval;
 125         }
 126
 127         dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate);
 128
 129         /*
 130          * Calculate the appropriate load and match values based on the
 131          * specified period and duty cycle. The load value determines the
 132          * period time and the match value determines the duty time.
 133          *
 134          * The period lasts for (DM_TIMER_MAX-load_value+1) clock cycles.
 135          * Similarly, the active time lasts (match_value-load_value+1) cycles.
 136          * The non-active time is the remainder: (DM_TIMER_MAX-match_value)
 137          * clock cycles.
 138          *
 139          * NOTE: It is required that: load_value <= match_value < DM_TIMER_MAX
 140          *
 141          * References:
 142          *   OMAP4430/60/70 TRM sections 22.2.4.10 and 22.2.4.11
 143          *   AM335x Sitara TRM sections 20.1.3.5 and 20.1.3.6
 144          */
 145         period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
 146         duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);
 147
 148         if (period_cycles < 2) {
 149                 dev_info(chip->dev,
 150                          "period %d ns too short for clock rate %lu Hz\n",
 151                          period_ns, clk_rate);
 152                 goto err_einval;
 153         }
 154
 155         if (duty_cycles < 1) {
 156                 dev_dbg(chip->dev,
 157                         "duty cycle %d ns is too short for clock rate %lu Hz\n",
 158                         duty_ns, clk_rate);
 159                 dev_dbg(chip->dev, "using minimum of 1 clock cycle\n");
 160                 duty_cycles = 1;
 161         } else if (duty_cycles >= period_cycles) {
 162                 dev_dbg(chip->dev,
 163                         "duty cycle %d ns is too long for period %d ns at clock rate %lu Hz\n",
 164                         duty_ns, period_ns, clk_rate);
 165                 dev_dbg(chip->dev, "using maximum of 1 clock cycle less than period\n");
 166                 duty_cycles = period_cycles - 1;
 167         }
 168
 169         load_value = (DM_TIMER_MAX - period_cycles) + 1;
 170         match_value = load_value + duty_cycles - 1;
 171
 172         /*
 173          * We MUST stop the associated dual-mode timer before attempting to
 174          * write its registers, but calls to omap_dm_timer_start/stop must
 175          * be balanced so check if timer is active before calling timer_stop.
 176          */
 177         timer_active = pm_runtime_active(&omap->dm_timer_pdev->dev);
 178         if (timer_active)
 179                 omap->pdata->stop(omap->dm_timer);
 180
 181         omap->pdata->set_load(omap->dm_timer, true, load_value);
 182         omap->pdata->set_match(omap->dm_timer, true, match_value);
 183
 184         dev_dbg(chip->dev, "load value: %#08x (%d), match value: %#08x (%d)\n",
 185                 load_value, load_value, match_value, match_value);
 186
 187         omap->pdata->set_pwm(omap->dm_timer,
 188                               pwm->polarity == PWM_POLARITY_INVERSED,
 189                               true,
 190                               PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
 191
 192         /* If config was called while timer was running it must be reenabled. */
 193         if (timer_active)
 194                 pwm_omap_dmtimer_start(omap);
 195
 196         mutex_unlock(&omap->mutex);
 197
 198         return 0;
 199
 200 err_einval:
 201         mutex_unlock(&omap->mutex);
 202
 203         return -EINVAL;
 204 }
 205
 206 static int pwm_omap_dmtimer_set_polarity(struct pwm_chip *chip,
 207                                          struct pwm_device *pwm,
 208                                          enum pwm_polarity polarity)
 209 {
 210         struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
 211
 212         /*
 213          * PWM core will not call set_polarity while PWM is enabled so it's
 214          * safe to reconfigure the timer here without stopping it first.
 215          */
 216         mutex_lock(&omap->mutex);
 217         omap->pdata->set_pwm(omap->dm_timer,
 218                               polarity == PWM_POLARITY_INVERSED,
 219                               true,
 220                               PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
 221         mutex_unlock(&omap->mutex);
 222
 223         return 0;
 224 }
 225
 226 static const struct pwm_ops pwm_omap_dmtimer_ops = {
 227         .enable = pwm_omap_dmtimer_enable,
 228         .disable = pwm_omap_dmtimer_disable,
 229         .config = pwm_omap_dmtimer_config,
 230         .set_polarity = pwm_omap_dmtimer_set_polarity,
 231         .owner = THIS_MODULE,
 232 };
 233
 234 static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
 235 {
 236         struct device_node *np = pdev->dev.of_node;
 237         struct device_node *timer;
 238         struct pwm_omap_dmtimer_chip *omap;
 239         struct pwm_omap_dmtimer_pdata *pdata;
 240         pwm_omap_dmtimer *dm_timer;
 241         u32 prescaler;
 242         int status;
 243
 244         pdata = dev_get_platdata(&pdev->dev);
 245         if (!pdata) {
 246                 dev_err(&pdev->dev, "Missing dmtimer platform data\n");
 247                 return -EINVAL;
 248         }
 249
 250         if (!pdata->request_by_node ||
 251             !pdata->free ||
 252             !pdata->enable ||
 253             !pdata->disable ||
 254             !pdata->get_fclk ||
 255             !pdata->start ||
 256             !pdata->stop ||
 257             !pdata->set_load ||
 258             !pdata->set_match ||
 259             !pdata->set_pwm ||
 260             !pdata->set_prescaler ||
 261             !pdata->write_counter) {
 262                 dev_err(&pdev->dev, "Incomplete dmtimer pdata structure\n");
 263                 return -EINVAL;
 264         }
 265
 266         timer = of_parse_phandle(np, "ti,timers", 0);
 267         if (!timer)
 268                 return -ENODEV;
 269
 270         if (!of_get_property(timer, "ti,timer-pwm", NULL)) {
 271                 dev_err(&pdev->dev, "Missing ti,timer-pwm capability\n");
 272                 return -ENODEV;
 273         }
 274
 275         dm_timer = pdata->request_by_node(timer);
 276         if (!dm_timer)
 277                 return -EPROBE_DEFER;
 278
 279         omap = devm_kzalloc(&pdev->dev, sizeof(*omap), GFP_KERNEL);
 280         if (!omap) {
 281                 pdata->free(dm_timer);
 282                 return -ENOMEM;
 283         }
 284
 285         omap->pdata = pdata;
 286         omap->dm_timer = dm_timer;
 287
 288         omap->dm_timer_pdev = of_find_device_by_node(timer);
 289         if (!omap->dm_timer_pdev) {
 290                 dev_err(&pdev->dev, "Unable to find timer pdev\n");
 291                 omap->pdata->free(dm_timer);
 292                 return -EINVAL;
 293         }
 294
 295         /*
 296          * Ensure that the timer is stopped before we allow PWM core to call
 297          * pwm_enable.
 298          */
 299         if (pm_runtime_active(&omap->dm_timer_pdev->dev))
 300                 omap->pdata->stop(omap->dm_timer);
 301
 302         /* setup dmtimer prescaler */
 303         if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler",
 304                                 &prescaler))
 305                 omap->pdata->set_prescaler(omap->dm_timer, prescaler);
 306
 307         omap->chip.dev = &pdev->dev;
 308         omap->chip.ops = &pwm_omap_dmtimer_ops;
 309         omap->chip.base = -1;
 310         omap->chip.npwm = 1;
 311         omap->chip.of_xlate = of_pwm_xlate_with_flags;
 312         omap->chip.of_pwm_n_cells = 3;
 313
 314         mutex_init(&omap->mutex);
 315
 316         status = pwmchip_add(&omap->chip);
 317         if (status < 0) {
 318                 dev_err(&pdev->dev, "failed to register PWM\n");
 319                 omap->pdata->free(omap->dm_timer);
 320                 return status;
 321         }
 322
 323         platform_set_drvdata(pdev, omap);
 324
 325         return 0;
 326 }
 327
 328 static int pwm_omap_dmtimer_remove(struct platform_device *pdev)
 329 {
 330         struct pwm_omap_dmtimer_chip *omap = platform_get_drvdata(pdev);
 331
 332         if (pm_runtime_active(&omap->dm_timer_pdev->dev))
 333                 omap->pdata->stop(omap->dm_timer);
 334
 335         omap->pdata->free(omap->dm_timer);
 336
 337         mutex_destroy(&omap->mutex);
 338
 339         return pwmchip_remove(&omap->chip);
 340 }
 341
 342 static const struct of_device_id pwm_omap_dmtimer_of_match[] = {
 343         {.compatible = "ti,omap-dmtimer-pwm"},
 344         {}
 345 };
 346 MODULE_DEVICE_TABLE(of, pwm_omap_dmtimer_of_match);
 347
 348 static struct platform_driver pwm_omap_dmtimer_driver = {
 349         .driver = {
 350                 .name = "omap-dmtimer-pwm",
 351                 .of_match_table = of_match_ptr(pwm_omap_dmtimer_of_match),
 352         },
 353         .probe = pwm_omap_dmtimer_probe,
 354         .remove = pwm_omap_dmtimer_remove,
 355 };
 356 module_platform_driver(pwm_omap_dmtimer_driver);
 357
 358 MODULE_AUTHOR("Grant Erickson <marathon96@gmail.com>");
 359 MODULE_AUTHOR("NeilBrown <neilb@suse.de>");
 360 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
 361 MODULE_LICENSE("GPL v2");
 362 MODULE_DESCRIPTION("OMAP PWM Driver using Dual-mode Timers");