drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

   1 /*
   2  * Copyright (c) 2016 Linaro Ltd.
   3  * Copyright (c) 2016 Hisilicon Limited.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  */
  11
  12 #include "hisi_sas.h"
  13 #define DRV_NAME "hisi_sas_v2_hw"
  14
  15 /* global registers need init*/
  16 #define DLVRY_QUEUE_ENABLE              0x0
  17 #define IOST_BASE_ADDR_LO               0x8
  18 #define IOST_BASE_ADDR_HI               0xc
  19 #define ITCT_BASE_ADDR_LO               0x10
  20 #define ITCT_BASE_ADDR_HI               0x14
  21 #define IO_BROKEN_MSG_ADDR_LO           0x18
  22 #define IO_BROKEN_MSG_ADDR_HI           0x1c
  23 #define PHY_CONTEXT                     0x20
  24 #define PHY_STATE                       0x24
  25 #define PHY_PORT_NUM_MA                 0x28
  26 #define PORT_STATE                      0x2c
  27 #define PORT_STATE_PHY8_PORT_NUM_OFF    16
  28 #define PORT_STATE_PHY8_PORT_NUM_MSK    (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
  29 #define PORT_STATE_PHY8_CONN_RATE_OFF   20
  30 #define PORT_STATE_PHY8_CONN_RATE_MSK   (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
  31 #define PHY_CONN_RATE                   0x30
  32 #define HGC_TRANS_TASK_CNT_LIMIT        0x38
  33 #define AXI_AHB_CLK_CFG                 0x3c
  34 #define ITCT_CLR                        0x44
  35 #define ITCT_CLR_EN_OFF                 16
  36 #define ITCT_CLR_EN_MSK                 (0x1 << ITCT_CLR_EN_OFF)
  37 #define ITCT_DEV_OFF                    0
  38 #define ITCT_DEV_MSK                    (0x7ff << ITCT_DEV_OFF)
  39 #define AXI_USER1                       0x48
  40 #define AXI_USER2                       0x4c
  41 #define IO_SATA_BROKEN_MSG_ADDR_LO      0x58
  42 #define IO_SATA_BROKEN_MSG_ADDR_HI      0x5c
  43 #define SATA_INITI_D2H_STORE_ADDR_LO    0x60
  44 #define SATA_INITI_D2H_STORE_ADDR_HI    0x64
  45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
  46 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x88
  47 #define HGC_GET_ITV_TIME                0x90
  48 #define DEVICE_MSG_WORK_MODE            0x94
  49 #define OPENA_WT_CONTI_TIME             0x9c
  50 #define I_T_NEXUS_LOSS_TIME             0xa0
  51 #define MAX_CON_TIME_LIMIT_TIME         0xa4
  52 #define BUS_INACTIVE_LIMIT_TIME         0xa8
  53 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
  54 #define CFG_AGING_TIME                  0xbc
  55 #define HGC_DFX_CFG2                    0xc0
  56 #define HGC_IOMB_PROC1_STATUS   0x104
  57 #define CFG_1US_TIMER_TRSH              0xcc
  58 #define HGC_INVLD_DQE_INFO              0x148
  59 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF   9
  60 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK   (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
  61 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF   18
  62 #define INT_COAL_EN                     0x19c
  63 #define OQ_INT_COAL_TIME                0x1a0
  64 #define OQ_INT_COAL_CNT                 0x1a4
  65 #define ENT_INT_COAL_TIME               0x1a8
  66 #define ENT_INT_COAL_CNT                0x1ac
  67 #define OQ_INT_SRC                      0x1b0
  68 #define OQ_INT_SRC_MSK                  0x1b4
  69 #define ENT_INT_SRC1                    0x1b8
  70 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF    0
  71 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
  72 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF    8
  73 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
  74 #define ENT_INT_SRC2                    0x1bc
  75 #define ENT_INT_SRC3                    0x1c0
  76 #define ENT_INT_SRC3_ITC_INT_OFF        15
  77 #define ENT_INT_SRC3_ITC_INT_MSK        (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
  78 #define ENT_INT_SRC_MSK1                0x1c4
  79 #define ENT_INT_SRC_MSK2                0x1c8
  80 #define ENT_INT_SRC_MSK3                0x1cc
  81 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF  31
  82 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK  (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
  83 #define SAS_ECC_INTR_MSK                0x1ec
  84 #define HGC_ERR_STAT_EN                 0x238
  85 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
  86 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
  87 #define DLVRY_Q_0_DEPTH                 0x268
  88 #define DLVRY_Q_0_WR_PTR                0x26c
  89 #define DLVRY_Q_0_RD_PTR                0x270
  90 #define HYPER_STREAM_ID_EN_CFG          0xc80
  91 #define OQ0_INT_SRC_MSK                 0xc90
  92 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
  93 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
  94 #define COMPL_Q_0_DEPTH                 0x4e8
  95 #define COMPL_Q_0_WR_PTR                0x4ec
  96 #define COMPL_Q_0_RD_PTR                0x4f0
  97
  98 /* phy registers need init */
  99 #define PORT_BASE                       (0x2000)
 100
 101 #define PHY_CFG                         (PORT_BASE + 0x0)
 102 #define HARD_PHY_LINKRATE               (PORT_BASE + 0x4)
 103 #define PHY_CFG_ENA_OFF                 0
 104 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
 105 #define PHY_CFG_DC_OPT_OFF              2
 106 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
 107 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0x8)
 108 #define PROG_PHY_LINK_RATE_MAX_OFF      0
 109 #define PROG_PHY_LINK_RATE_MAX_MSK      (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
 110 #define PHY_CTRL                        (PORT_BASE + 0x14)
 111 #define PHY_CTRL_RESET_OFF              0
 112 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
 113 #define SAS_PHY_CTRL                    (PORT_BASE + 0x20)
 114 #define SL_CFG                          (PORT_BASE + 0x84)
 115 #define PHY_PCN                         (PORT_BASE + 0x44)
 116 #define SL_TOUT_CFG                     (PORT_BASE + 0x8c)
 117 #define SL_CONTROL                      (PORT_BASE + 0x94)
 118 #define SL_CONTROL_NOTIFY_EN_OFF        0
 119 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
 120 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
 121 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
 122 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
 123 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
 124 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
 125 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
 126 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
 127 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
 128 #define RX_IDAF_DWORD1                  (PORT_BASE + 0xc8)
 129 #define RX_IDAF_DWORD2                  (PORT_BASE + 0xcc)
 130 #define RX_IDAF_DWORD3                  (PORT_BASE + 0xd0)
 131 #define RX_IDAF_DWORD4                  (PORT_BASE + 0xd4)
 132 #define RX_IDAF_DWORD5                  (PORT_BASE + 0xd8)
 133 #define RX_IDAF_DWORD6                  (PORT_BASE + 0xdc)
 134 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
 135 #define DONE_RECEIVED_TIME              (PORT_BASE + 0x11c)
 136 #define CHL_INT0                        (PORT_BASE + 0x1b4)
 137 #define CHL_INT0_HOTPLUG_TOUT_OFF       0
 138 #define CHL_INT0_HOTPLUG_TOUT_MSK       (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
 139 #define CHL_INT0_SL_RX_BCST_ACK_OFF     1
 140 #define CHL_INT0_SL_RX_BCST_ACK_MSK     (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
 141 #define CHL_INT0_SL_PHY_ENABLE_OFF      2
 142 #define CHL_INT0_SL_PHY_ENABLE_MSK      (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
 143 #define CHL_INT0_NOT_RDY_OFF            4
 144 #define CHL_INT0_NOT_RDY_MSK            (0x1 << CHL_INT0_NOT_RDY_OFF)
 145 #define CHL_INT0_PHY_RDY_OFF            5
 146 #define CHL_INT0_PHY_RDY_MSK            (0x1 << CHL_INT0_PHY_RDY_OFF)
 147 #define CHL_INT1                        (PORT_BASE + 0x1b8)
 148 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF    15
 149 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
 150 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF    17
 151 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
 152 #define CHL_INT2                        (PORT_BASE + 0x1bc)
 153 #define CHL_INT0_MSK                    (PORT_BASE + 0x1c0)
 154 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c4)
 155 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c8)
 156 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
 157 #define PHY_CTRL_RDY_MSK                (PORT_BASE + 0x2b0)
 158 #define PHYCTRL_NOT_RDY_MSK             (PORT_BASE + 0x2b4)
 159 #define PHYCTRL_DWS_RESET_MSK           (PORT_BASE + 0x2b8)
 160 #define PHYCTRL_PHY_ENA_MSK             (PORT_BASE + 0x2bc)
 161 #define SL_RX_BCAST_CHK_MSK             (PORT_BASE + 0x2c0)
 162 #define PHYCTRL_OOB_RESTART_MSK         (PORT_BASE + 0x2c4)
 163 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
 164 #define DMA_TX_STATUS_BUSY_OFF          0
 165 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
 166 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
 167 #define DMA_RX_STATUS_BUSY_OFF          0
 168 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
 169
 170 #define AXI_CFG                         (0x5100)
 171 #define AM_CFG_MAX_TRANS                (0x5010)
 172 #define AM_CFG_SINGLE_PORT_MAX_TRANS    (0x5014)
 173
 174 /* HW dma structures */
 175 /* Delivery queue header */
 176 /* dw0 */
 177 #define CMD_HDR_RESP_REPORT_OFF         5
 178 #define CMD_HDR_RESP_REPORT_MSK         (0x1 << CMD_HDR_RESP_REPORT_OFF)
 179 #define CMD_HDR_TLR_CTRL_OFF            6
 180 #define CMD_HDR_TLR_CTRL_MSK            (0x3 << CMD_HDR_TLR_CTRL_OFF)
 181 #define CMD_HDR_PORT_OFF                18
 182 #define CMD_HDR_PORT_MSK                (0xf << CMD_HDR_PORT_OFF)
 183 #define CMD_HDR_PRIORITY_OFF            27
 184 #define CMD_HDR_PRIORITY_MSK            (0x1 << CMD_HDR_PRIORITY_OFF)
 185 #define CMD_HDR_CMD_OFF                 29
 186 #define CMD_HDR_CMD_MSK                 (0x7 << CMD_HDR_CMD_OFF)
 187 /* dw1 */
 188 #define CMD_HDR_DIR_OFF                 5
 189 #define CMD_HDR_DIR_MSK                 (0x3 << CMD_HDR_DIR_OFF)
 190 #define CMD_HDR_RESET_OFF               7
 191 #define CMD_HDR_RESET_MSK               (0x1 << CMD_HDR_RESET_OFF)
 192 #define CMD_HDR_VDTL_OFF                10
 193 #define CMD_HDR_VDTL_MSK                (0x1 << CMD_HDR_VDTL_OFF)
 194 #define CMD_HDR_FRAME_TYPE_OFF          11
 195 #define CMD_HDR_FRAME_TYPE_MSK          (0x1f << CMD_HDR_FRAME_TYPE_OFF)
 196 #define CMD_HDR_DEV_ID_OFF              16
 197 #define CMD_HDR_DEV_ID_MSK              (0xffff << CMD_HDR_DEV_ID_OFF)
 198 /* dw2 */
 199 #define CMD_HDR_CFL_OFF                 0
 200 #define CMD_HDR_CFL_MSK                 (0x1ff << CMD_HDR_CFL_OFF)
 201 #define CMD_HDR_NCQ_TAG_OFF             10
 202 #define CMD_HDR_NCQ_TAG_MSK             (0x1f << CMD_HDR_NCQ_TAG_OFF)
 203 #define CMD_HDR_MRFL_OFF                15
 204 #define CMD_HDR_MRFL_MSK                (0x1ff << CMD_HDR_MRFL_OFF)
 205 #define CMD_HDR_SG_MOD_OFF              24
 206 #define CMD_HDR_SG_MOD_MSK              (0x3 << CMD_HDR_SG_MOD_OFF)
 207 #define CMD_HDR_FIRST_BURST_OFF         26
 208 #define CMD_HDR_FIRST_BURST_MSK         (0x1 << CMD_HDR_SG_MOD_OFF)
 209 /* dw3 */
 210 #define CMD_HDR_IPTT_OFF                0
 211 #define CMD_HDR_IPTT_MSK                (0xffff << CMD_HDR_IPTT_OFF)
 212 /* dw6 */
 213 #define CMD_HDR_DIF_SGL_LEN_OFF         0
 214 #define CMD_HDR_DIF_SGL_LEN_MSK         (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
 215 #define CMD_HDR_DATA_SGL_LEN_OFF        16
 216 #define CMD_HDR_DATA_SGL_LEN_MSK        (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
 217
 218 /* Completion header */
 219 /* dw0 */
 220 #define CMPLT_HDR_RSPNS_XFRD_OFF        10
 221 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
 222 #define CMPLT_HDR_ERX_OFF               12
 223 #define CMPLT_HDR_ERX_MSK               (0x1 << CMPLT_HDR_ERX_OFF)
 224 /* dw1 */
 225 #define CMPLT_HDR_IPTT_OFF              0
 226 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
 227 #define CMPLT_HDR_DEV_ID_OFF            16
 228 #define CMPLT_HDR_DEV_ID_MSK            (0xffff << CMPLT_HDR_DEV_ID_OFF)
 229
 230 /* ITCT header */
 231 /* qw0 */
 232 #define ITCT_HDR_DEV_TYPE_OFF           0
 233 #define ITCT_HDR_DEV_TYPE_MSK           (0x3 << ITCT_HDR_DEV_TYPE_OFF)
 234 #define ITCT_HDR_VALID_OFF              2
 235 #define ITCT_HDR_VALID_MSK              (0x1 << ITCT_HDR_VALID_OFF)
 236 #define ITCT_HDR_MCR_OFF                5
 237 #define ITCT_HDR_MCR_MSK                (0xf << ITCT_HDR_MCR_OFF)
 238 #define ITCT_HDR_VLN_OFF                9
 239 #define ITCT_HDR_VLN_MSK                (0xf << ITCT_HDR_VLN_OFF)
 240 #define ITCT_HDR_PORT_ID_OFF            28
 241 #define ITCT_HDR_PORT_ID_MSK            (0xf << ITCT_HDR_PORT_ID_OFF)
 242 /* qw2 */
 243 #define ITCT_HDR_INLT_OFF               0
 244 #define ITCT_HDR_INLT_MSK               (0xffffULL << ITCT_HDR_INLT_OFF)
 245 #define ITCT_HDR_BITLT_OFF              16
 246 #define ITCT_HDR_BITLT_MSK              (0xffffULL << ITCT_HDR_BITLT_OFF)
 247 #define ITCT_HDR_MCTLT_OFF              32
 248 #define ITCT_HDR_MCTLT_MSK              (0xffffULL << ITCT_HDR_MCTLT_OFF)
 249 #define ITCT_HDR_RTOLT_OFF              48
 250 #define ITCT_HDR_RTOLT_MSK              (0xffffULL << ITCT_HDR_RTOLT_OFF)
 251
 252 struct hisi_sas_complete_v2_hdr {
 253         __le32 dw0;
 254         __le32 dw1;
 255         __le32 act;
 256         __le32 dw3;
 257 };
 258
 259 struct hisi_sas_err_record_v2 {
 260         /* dw0 */
 261         __le32 trans_tx_fail_type;
 262
 263         /* dw1 */
 264         __le32 trans_rx_fail_type;
 265
 266         /* dw2 */
 267         __le16 dma_tx_err_type;
 268         __le16 sipc_rx_err_type;
 269
 270         /* dw3 */
 271         __le32 dma_rx_err_type;
 272 };
 273
 274 enum {
 275         HISI_SAS_PHY_PHY_UPDOWN,
 276         HISI_SAS_PHY_CHNL_INT,
 277         HISI_SAS_PHY_INT_NR
 278 };
 279
 280 enum {
 281         TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
 282         TRANS_RX_FAIL_BASE = 0x100, /* dw1 */
 283         DMA_TX_ERR_BASE = 0x200, /* dw2 bit 15-0 */
 284         SIPC_RX_ERR_BASE = 0x300, /* dw2 bit 31-16*/
 285         DMA_RX_ERR_BASE = 0x400, /* dw3 */
 286
 287         /* trans tx*/
 288         TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
 289         TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
 290         TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
 291         TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
 292         TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
 293         RESERVED0, /* 0x5 */
 294         TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
 295         TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
 296         TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
 297         TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
 298         TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
 299         TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
 300         TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
 301         TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
 302         TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
 303         TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
 304         TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
 305         TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
 306         TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
 307         TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
 308         TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
 309         TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
 310         TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
 311         TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
 312         TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
 313         TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
 314         TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
 315         TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
 316         /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
 317         TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
 318         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
 319         TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
 320         TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
 321         /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
 322         TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
 323
 324         /* trans rx */
 325         TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x100 */
 326         TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x101 for sata/stp */
 327         TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x102 for ssp/smp */
 328         /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x102 <] for sata/stp */
 329         TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x103 for sata/stp */
 330         TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x104 for sata/stp */
 331         TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x105 for smp */
 332         /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x105 <] for sata/stp */
 333         TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x106 for sata/stp*/
 334         TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x107 */
 335         TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x108 */
 336         TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x109 */
 337         TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x10a */
 338         RESERVED1, /* 0x10b */
 339         TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x10c */
 340         TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x10d */
 341         TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x10e */
 342         TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x10f */
 343         TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x110 for ssp/smp */
 344         TRANS_RX_ERR_WITH_BAD_HASH, /* 0x111 for ssp */
 345         /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x111 <] for sata/stp */
 346         TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x112 for ssp*/
 347         /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x112 <] for sata/stp */
 348         TRANS_RX_SSP_FRM_LEN_ERR, /* 0x113 for ssp */
 349         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x113 <] for sata */
 350         RESERVED2, /* 0x114 */
 351         RESERVED3, /* 0x115 */
 352         RESERVED4, /* 0x116 */
 353         RESERVED5, /* 0x117 */
 354         TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x118 */
 355         TRANS_RX_SMP_FRM_LEN_ERR, /* 0x119 */
 356         TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x11a */
 357         RESERVED6, /* 0x11b */
 358         RESERVED7, /* 0x11c */
 359         RESERVED8, /* 0x11d */
 360         RESERVED9, /* 0x11e */
 361         TRANS_RX_R_ERR, /* 0x11f */
 362
 363         /* dma tx */
 364         DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x200 */
 365         DMA_TX_DIF_APP_ERR, /* 0x201 */
 366         DMA_TX_DIF_RPP_ERR, /* 0x202 */
 367         DMA_TX_DATA_SGL_OVERFLOW, /* 0x203 */
 368         DMA_TX_DIF_SGL_OVERFLOW, /* 0x204 */
 369         DMA_TX_UNEXP_XFER_ERR, /* 0x205 */
 370         DMA_TX_UNEXP_RETRANS_ERR, /* 0x206 */
 371         DMA_TX_XFER_LEN_OVERFLOW, /* 0x207 */
 372         DMA_TX_XFER_OFFSET_ERR, /* 0x208 */
 373         DMA_TX_RAM_ECC_ERR, /* 0x209 */
 374         DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x20a */
 375
 376         /* sipc rx */
 377         SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x300 */
 378         SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x301 */
 379         SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x302 */
 380         SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x303 */
 381         SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x304 */
 382         SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x305 */
 383         SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x306 */
 384         SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x307 */
 385         SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x308 */
 386         SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x309 */
 387         SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x30a */
 388
 389         /* dma rx */
 390         DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x400 */
 391         DMA_RX_DIF_APP_ERR, /* 0x401 */
 392         DMA_RX_DIF_RPP_ERR, /* 0x402 */
 393         DMA_RX_DATA_SGL_OVERFLOW, /* 0x403 */
 394         DMA_RX_DIF_SGL_OVERFLOW, /* 0x404 */
 395         DMA_RX_DATA_LEN_OVERFLOW, /* 0x405 */
 396         DMA_RX_DATA_LEN_UNDERFLOW, /* 0x406 */
 397         DMA_RX_DATA_OFFSET_ERR, /* 0x407 */
 398         RESERVED10, /* 0x408 */
 399         DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x409 */
 400         DMA_RX_RESP_BUF_OVERFLOW, /* 0x40a */
 401         DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x40b */
 402         DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x40c */
 403         DMA_RX_UNEXP_RDFRAME_ERR, /* 0x40d */
 404         DMA_RX_PIO_DATA_LEN_ERR, /* 0x40e */
 405         DMA_RX_RDSETUP_STATUS_ERR, /* 0x40f */
 406         DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x410 */
 407         DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x411 */
 408         DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x412 */
 409         DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x413 */
 410         DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x414 */
 411         DMA_RX_RDSETUP_OFFSET_ERR, /* 0x415 */
 412         DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x416 */
 413         DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x417 */
 414         DMA_RX_RAM_ECC_ERR, /* 0x418 */
 415         DMA_RX_UNKNOWN_FRM_ERR, /* 0x419 */
 416 };
 417
 418 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
 419
 420 #define DIR_NO_DATA 0
 421 #define DIR_TO_INI 1
 422 #define DIR_TO_DEVICE 2
 423 #define DIR_RESERVED 3
 424
 425 #define SATA_PROTOCOL_NONDATA           0x1
 426 #define SATA_PROTOCOL_PIO               0x2
 427 #define SATA_PROTOCOL_DMA               0x4
 428 #define SATA_PROTOCOL_FPDMA             0x8
 429 #define SATA_PROTOCOL_ATAPI             0x10
 430
 431 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 432 {
 433         void __iomem *regs = hisi_hba->regs + off;
 434
 435         return readl(regs);
 436 }
 437
 438 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
 439 {
 440         void __iomem *regs = hisi_hba->regs + off;
 441
 442         return readl_relaxed(regs);
 443 }
 444
 445 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
 446 {
 447         void __iomem *regs = hisi_hba->regs + off;
 448
 449         writel(val, regs);
 450 }
 451
 452 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
 453                                  u32 off, u32 val)
 454 {
 455         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 456
 457         writel(val, regs);
 458 }
 459
 460 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
 461                                       int phy_no, u32 off)
 462 {
 463         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 464
 465         return readl(regs);
 466 }
 467
 468 /* This function needs to be protected from pre-emption. */
 469 static int
 470 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
 471                        struct domain_device *device)
 472 {
 473         unsigned int index = 0;
 474         void *bitmap = hisi_hba->slot_index_tags;
 475         int sata_dev = dev_is_sata(device);
 476
 477         while (1) {
 478                 index = find_next_zero_bit(bitmap, hisi_hba->slot_index_count,
 479                                            index);
 480                 if (index >= hisi_hba->slot_index_count)
 481                         return -SAS_QUEUE_FULL;
 482                 /*
 483                  * SAS IPTT bit0 should be 1
 484                  */
 485                 if (sata_dev || (index & 1))
 486                         break;
 487                 index++;
 488         }
 489
 490         set_bit(index, bitmap);
 491         *slot_idx = index;
 492         return 0;
 493 }
 494
 495 static struct
 496 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
 497 {
 498         struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
 499         struct hisi_sas_device *sas_dev = NULL;
 500         int i, sata_dev = dev_is_sata(device);
 501
 502         spin_lock(&hisi_hba->lock);
 503         for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
 504                 /*
 505                  * SATA device id bit0 should be 0
 506                  */
 507                 if (sata_dev && (i & 1))
 508                         continue;
 509                 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
 510                         hisi_hba->devices[i].device_id = i;
 511                         sas_dev = &hisi_hba->devices[i];
 512                         sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
 513                         sas_dev->dev_type = device->dev_type;
 514                         sas_dev->hisi_hba = hisi_hba;
 515                         sas_dev->sas_device = device;
 516                         break;
 517                 }
 518         }
 519         spin_unlock(&hisi_hba->lock);
 520
 521         return sas_dev;
 522 }
 523
 524 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 525 {
 526         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 527
 528         cfg &= ~PHY_CFG_DC_OPT_MSK;
 529         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
 530         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 531 }
 532
 533 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 534 {
 535         struct sas_identify_frame identify_frame;
 536         u32 *identify_buffer;
 537
 538         memset(&identify_frame, 0, sizeof(identify_frame));
 539         identify_frame.dev_type = SAS_END_DEVICE;
 540         identify_frame.frame_type = 0;
 541         identify_frame._un1 = 1;
 542         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
 543         identify_frame.target_bits = SAS_PROTOCOL_NONE;
 544         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 545         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 546         identify_frame.phy_id = phy_no;
 547         identify_buffer = (u32 *)(&identify_frame);
 548
 549         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
 550                         __swab32(identify_buffer[0]));
 551         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
 552                         identify_buffer[2]);
 553         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
 554                         identify_buffer[1]);
 555         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
 556                         identify_buffer[4]);
 557         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
 558                         identify_buffer[3]);
 559         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
 560                         __swab32(identify_buffer[5]));
 561 }
 562
 563 static void init_id_frame_v2_hw(struct hisi_hba *hisi_hba)
 564 {
 565         int i;
 566
 567         for (i = 0; i < hisi_hba->n_phy; i++)
 568                 config_id_frame_v2_hw(hisi_hba, i);
 569 }
 570
 571 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
 572                              struct hisi_sas_device *sas_dev)
 573 {
 574         struct domain_device *device = sas_dev->sas_device;
 575         struct device *dev = &hisi_hba->pdev->dev;
 576         u64 qw0, device_id = sas_dev->device_id;
 577         struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
 578         struct domain_device *parent_dev = device->parent;
 579         struct hisi_sas_port *port = device->port->lldd_port;
 580
 581         memset(itct, 0, sizeof(*itct));
 582
 583         /* qw0 */
 584         qw0 = 0;
 585         switch (sas_dev->dev_type) {
 586         case SAS_END_DEVICE:
 587         case SAS_EDGE_EXPANDER_DEVICE:
 588         case SAS_FANOUT_EXPANDER_DEVICE:
 589                 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
 590                 break;
 591         case SAS_SATA_DEV:
 592                 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
 593                         qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
 594                 else
 595                         qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
 596                 break;
 597         default:
 598                 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
 599                          sas_dev->dev_type);
 600         }
 601
 602         qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
 603                 (device->linkrate << ITCT_HDR_MCR_OFF) |
 604                 (1 << ITCT_HDR_VLN_OFF) |
 605                 (port->id << ITCT_HDR_PORT_ID_OFF));
 606         itct->qw0 = cpu_to_le64(qw0);
 607
 608         /* qw1 */
 609         memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
 610         itct->sas_addr = __swab64(itct->sas_addr);
 611
 612         /* qw2 */
 613         if (!dev_is_sata(device))
 614                 itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_INLT_OFF) |
 615                                         (0x1ULL << ITCT_HDR_BITLT_OFF) |
 616                                         (0x32ULL << ITCT_HDR_MCTLT_OFF) |
 617                                         (0x1ULL << ITCT_HDR_RTOLT_OFF));
 618 }
 619
 620 static void free_device_v2_hw(struct hisi_hba *hisi_hba,
 621                               struct hisi_sas_device *sas_dev)
 622 {
 623         u64 qw0, dev_id = sas_dev->device_id;
 624         struct device *dev = &hisi_hba->pdev->dev;
 625         struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
 626         u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
 627         int i;
 628
 629         /* clear the itct interrupt state */
 630         if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
 631                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
 632                                  ENT_INT_SRC3_ITC_INT_MSK);
 633
 634         /* clear the itct int*/
 635         for (i = 0; i < 2; i++) {
 636                 /* clear the itct table*/
 637                 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
 638                 reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
 639                 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
 640
 641                 udelay(10);
 642                 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
 643                 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) {
 644                         dev_dbg(dev, "got clear ITCT done interrupt\n");
 645
 646                         /* invalid the itct state*/
 647                         qw0 = cpu_to_le64(itct->qw0);
 648                         qw0 &= ~(1 << ITCT_HDR_VALID_OFF);
 649                         hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
 650                                          ENT_INT_SRC3_ITC_INT_MSK);
 651                         hisi_hba->devices[dev_id].dev_type = SAS_PHY_UNUSED;
 652                         hisi_hba->devices[dev_id].dev_status = HISI_SAS_DEV_NORMAL;
 653
 654                         /* clear the itct */
 655                         hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
 656                         dev_dbg(dev, "clear ITCT ok\n");
 657                         break;
 658                 }
 659         }
 660 }
 661
 662 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
 663 {
 664         int i, reset_val;
 665         u32 val;
 666         unsigned long end_time;
 667         struct device *dev = &hisi_hba->pdev->dev;
 668
 669         /* The mask needs to be set depending on the number of phys */
 670         if (hisi_hba->n_phy == 9)
 671                 reset_val = 0x1fffff;
 672         else
 673                 reset_val = 0x7ffff;
 674
 675         /* Disable all of the DQ */
 676         for (i = 0; i < HISI_SAS_MAX_QUEUES; i++)
 677                 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
 678
 679         /* Disable all of the PHYs */
 680         for (i = 0; i < hisi_hba->n_phy; i++) {
 681                 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
 682
 683                 phy_cfg &= ~PHY_CTRL_RESET_MSK;
 684                 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
 685         }
 686         udelay(50);
 687
 688         /* Ensure DMA tx & rx idle */
 689         for (i = 0; i < hisi_hba->n_phy; i++) {
 690                 u32 dma_tx_status, dma_rx_status;
 691
 692                 end_time = jiffies + msecs_to_jiffies(1000);
 693
 694                 while (1) {
 695                         dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
 696                                                             DMA_TX_STATUS);
 697                         dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
 698                                                             DMA_RX_STATUS);
 699
 700                         if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
 701                                 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
 702                                 break;
 703
 704                         msleep(20);
 705                         if (time_after(jiffies, end_time))
 706                                 return -EIO;
 707                 }
 708         }
 709
 710         /* Ensure axi bus idle */
 711         end_time = jiffies + msecs_to_jiffies(1000);
 712         while (1) {
 713                 u32 axi_status =
 714                         hisi_sas_read32(hisi_hba, AXI_CFG);
 715
 716                 if (axi_status == 0)
 717                         break;
 718
 719                 msleep(20);
 720                 if (time_after(jiffies, end_time))
 721                         return -EIO;
 722         }
 723
 724         if (ACPI_HANDLE(dev)) {
 725                 acpi_status s;
 726
 727                 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
 728                 if (ACPI_FAILURE(s)) {
 729                         dev_err(dev, "Reset failed\n");
 730                         return -EIO;
 731                 }
 732         } else if (hisi_hba->ctrl) {
 733                 /* reset and disable clock*/
 734                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
 735                                 reset_val);
 736                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
 737                                 reset_val);
 738                 msleep(1);
 739                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
 740                 if (reset_val != (val & reset_val)) {
 741                         dev_err(dev, "SAS reset fail.\n");
 742                         return -EIO;
 743                 }
 744
 745                 /* De-reset and enable clock*/
 746                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
 747                                 reset_val);
 748                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
 749                                 reset_val);
 750                 msleep(1);
 751                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
 752                                 &val);
 753                 if (val & reset_val) {
 754                         dev_err(dev, "SAS de-reset fail.\n");
 755                         return -EIO;
 756                 }
 757         } else
 758                 dev_warn(dev, "no reset method\n");
 759
 760         return 0;
 761 }
 762
 763 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
 764 {
 765         struct device *dev = &hisi_hba->pdev->dev;
 766         int i;
 767
 768         /* Global registers init */
 769
 770         /* Deal with am-max-transmissions quirk */
 771         if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
 772                 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
 773                 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
 774                                  0x2020);
 775         } /* Else, use defaults -> do nothing */
 776
 777         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
 778                          (u32)((1ULL << hisi_hba->queue_count) - 1));
 779         hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
 780         hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
 781         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
 782         hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
 783         hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
 784         hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
 785         hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
 786         hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
 787         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
 788         hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
 789         hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
 790         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
 791         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
 792         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
 793         hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
 794         hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
 795         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
 796         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
 797         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
 798         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
 799         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
 800         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
 801         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe);
 802         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfffff3c0);
 803         for (i = 0; i < hisi_hba->queue_count; i++)
 804                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
 805
 806         hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
 807         hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
 808
 809         for (i = 0; i < hisi_hba->n_phy; i++) {
 810                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
 811                 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
 812                 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
 813                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x10);
 814                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
 815                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
 816                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
 817                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
 818                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
 819                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
 820                 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x23f801fc);
 821                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
 822                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
 823                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
 824                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
 825                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
 826                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
 827                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
 828                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
 829         }
 830
 831         for (i = 0; i < hisi_hba->queue_count; i++) {
 832                 /* Delivery queue */
 833                 hisi_sas_write32(hisi_hba,
 834                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
 835                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
 836
 837                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
 838                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
 839
 840                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
 841                                  HISI_SAS_QUEUE_SLOTS);
 842
 843                 /* Completion queue */
 844                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
 845                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
 846
 847                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
 848                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
 849
 850                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
 851                                  HISI_SAS_QUEUE_SLOTS);
 852         }
 853
 854         /* itct */
 855         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
 856                          lower_32_bits(hisi_hba->itct_dma));
 857
 858         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
 859                          upper_32_bits(hisi_hba->itct_dma));
 860
 861         /* iost */
 862         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
 863                          lower_32_bits(hisi_hba->iost_dma));
 864
 865         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
 866                          upper_32_bits(hisi_hba->iost_dma));
 867
 868         /* breakpoint */
 869         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
 870                          lower_32_bits(hisi_hba->breakpoint_dma));
 871
 872         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
 873                          upper_32_bits(hisi_hba->breakpoint_dma));
 874
 875         /* SATA broken msg */
 876         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
 877                          lower_32_bits(hisi_hba->sata_breakpoint_dma));
 878
 879         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
 880                          upper_32_bits(hisi_hba->sata_breakpoint_dma));
 881
 882         /* SATA initial fis */
 883         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
 884                          lower_32_bits(hisi_hba->initial_fis_dma));
 885
 886         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
 887                          upper_32_bits(hisi_hba->initial_fis_dma));
 888 }
 889
 890 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
 891 {
 892         struct device *dev = &hisi_hba->pdev->dev;
 893         int rc;
 894
 895         rc = reset_hw_v2_hw(hisi_hba);
 896         if (rc) {
 897                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
 898                 return rc;
 899         }
 900
 901         msleep(100);
 902         init_reg_v2_hw(hisi_hba);
 903
 904         init_id_frame_v2_hw(hisi_hba);
 905
 906         return 0;
 907 }
 908
 909 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 910 {
 911         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 912
 913         cfg |= PHY_CFG_ENA_MSK;
 914         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 915 }
 916
 917 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 918 {
 919         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 920
 921         cfg &= ~PHY_CFG_ENA_MSK;
 922         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 923 }
 924
 925 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 926 {
 927         config_id_frame_v2_hw(hisi_hba, phy_no);
 928         config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
 929         enable_phy_v2_hw(hisi_hba, phy_no);
 930 }
 931
 932 static void stop_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 933 {
 934         disable_phy_v2_hw(hisi_hba, phy_no);
 935 }
 936
 937 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 938 {
 939         stop_phy_v2_hw(hisi_hba, phy_no);
 940         msleep(100);
 941         start_phy_v2_hw(hisi_hba, phy_no);
 942 }
 943
 944 static void start_phys_v2_hw(unsigned long data)
 945 {
 946         struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
 947         int i;
 948
 949         for (i = 0; i < hisi_hba->n_phy; i++)
 950                 start_phy_v2_hw(hisi_hba, i);
 951 }
 952
 953 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
 954 {
 955         int i;
 956         struct timer_list *timer = &hisi_hba->timer;
 957
 958         for (i = 0; i < hisi_hba->n_phy; i++) {
 959                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a);
 960                 hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK);
 961         }
 962
 963         setup_timer(timer, start_phys_v2_hw, (unsigned long)hisi_hba);
 964         mod_timer(timer, jiffies + HZ);
 965 }
 966
 967 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 968 {
 969         u32 sl_control;
 970
 971         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 972         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
 973         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 974         msleep(1);
 975         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 976         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
 977         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 978 }
 979
 980 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
 981 {
 982         int i, bitmap = 0;
 983         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
 984         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
 985
 986         for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
 987                 if (phy_state & 1 << i)
 988                         if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
 989                                 bitmap |= 1 << i;
 990
 991         if (hisi_hba->n_phy == 9) {
 992                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
 993
 994                 if (phy_state & 1 << 8)
 995                         if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
 996                              PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
 997                                 bitmap |= 1 << 9;
 998         }
 999
1000         return bitmap;
1001 }
1002
1003 /**
1004  * This function allocates across all queues to load balance.
1005  * Slots are allocated from queues in a round-robin fashion.
1006  *
1007  * The callpath to this function and upto writing the write
1008  * queue pointer should be safe from interruption.
1009  */
1010 static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, int *q, int *s)
1011 {
1012         struct device *dev = &hisi_hba->pdev->dev;
1013         u32 r, w;
1014         int queue = hisi_hba->queue;
1015
1016         while (1) {
1017                 w = hisi_sas_read32_relaxed(hisi_hba,
1018                                             DLVRY_Q_0_WR_PTR + (queue * 0x14));
1019                 r = hisi_sas_read32_relaxed(hisi_hba,
1020                                             DLVRY_Q_0_RD_PTR + (queue * 0x14));
1021                 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1022                         queue = (queue + 1) % hisi_hba->queue_count;
1023                         if (queue == hisi_hba->queue) {
1024                                 dev_warn(dev, "could not find free slot\n");
1025                                 return -EAGAIN;
1026                         }
1027                         continue;
1028                 }
1029                 break;
1030         }
1031         hisi_hba->queue = (queue + 1) % hisi_hba->queue_count;
1032         *q = queue;
1033         *s = w;
1034         return 0;
1035 }
1036
1037 static void start_delivery_v2_hw(struct hisi_hba *hisi_hba)
1038 {
1039         int dlvry_queue = hisi_hba->slot_prep->dlvry_queue;
1040         int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot;
1041
1042         hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
1043                          ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS);
1044 }
1045
1046 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1047                               struct hisi_sas_slot *slot,
1048                               struct hisi_sas_cmd_hdr *hdr,
1049                               struct scatterlist *scatter,
1050                               int n_elem)
1051 {
1052         struct device *dev = &hisi_hba->pdev->dev;
1053         struct scatterlist *sg;
1054         int i;
1055
1056         if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
1057                 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
1058                         n_elem);
1059                 return -EINVAL;
1060         }
1061
1062         slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
1063                                         &slot->sge_page_dma);
1064         if (!slot->sge_page)
1065                 return -ENOMEM;
1066
1067         for_each_sg(scatter, sg, n_elem, i) {
1068                 struct hisi_sas_sge *entry = &slot->sge_page->sge[i];
1069
1070                 entry->addr = cpu_to_le64(sg_dma_address(sg));
1071                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1072                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1073                 entry->data_off = 0;
1074         }
1075
1076         hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma);
1077
1078         hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1079
1080         return 0;
1081 }
1082
1083 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1084                           struct hisi_sas_slot *slot)
1085 {
1086         struct sas_task *task = slot->task;
1087         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1088         struct domain_device *device = task->dev;
1089         struct device *dev = &hisi_hba->pdev->dev;
1090         struct hisi_sas_port *port = slot->port;
1091         struct scatterlist *sg_req, *sg_resp;
1092         struct hisi_sas_device *sas_dev = device->lldd_dev;
1093         dma_addr_t req_dma_addr;
1094         unsigned int req_len, resp_len;
1095         int elem, rc;
1096
1097         /*
1098         * DMA-map SMP request, response buffers
1099         */
1100         /* req */
1101         sg_req = &task->smp_task.smp_req;
1102         elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
1103         if (!elem)
1104                 return -ENOMEM;
1105         req_len = sg_dma_len(sg_req);
1106         req_dma_addr = sg_dma_address(sg_req);
1107
1108         /* resp */
1109         sg_resp = &task->smp_task.smp_resp;
1110         elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
1111         if (!elem) {
1112                 rc = -ENOMEM;
1113                 goto err_out_req;
1114         }
1115         resp_len = sg_dma_len(sg_resp);
1116         if ((req_len & 0x3) || (resp_len & 0x3)) {
1117                 rc = -EINVAL;
1118                 goto err_out_resp;
1119         }
1120
1121         /* create header */
1122         /* dw0 */
1123         hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1124                                (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1125                                (2 << CMD_HDR_CMD_OFF)); /* smp */
1126
1127         /* map itct entry */
1128         hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1129                                (1 << CMD_HDR_FRAME_TYPE_OFF) |
1130                                (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1131
1132         /* dw2 */
1133         hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1134                                (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1135                                CMD_HDR_MRFL_OFF));
1136
1137         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1138
1139         hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1140         hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1141
1142         return 0;
1143
1144 err_out_resp:
1145         dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
1146                      DMA_FROM_DEVICE);
1147 err_out_req:
1148         dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
1149                      DMA_TO_DEVICE);
1150         return rc;
1151 }
1152
1153 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1154                           struct hisi_sas_slot *slot, int is_tmf,
1155                           struct hisi_sas_tmf_task *tmf)
1156 {
1157         struct sas_task *task = slot->task;
1158         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1159         struct domain_device *device = task->dev;
1160         struct hisi_sas_device *sas_dev = device->lldd_dev;
1161         struct hisi_sas_port *port = slot->port;
1162         struct sas_ssp_task *ssp_task = &task->ssp_task;
1163         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1164         int has_data = 0, rc, priority = is_tmf;
1165         u8 *buf_cmd;
1166         u32 dw1 = 0, dw2 = 0;
1167
1168         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1169                                (2 << CMD_HDR_TLR_CTRL_OFF) |
1170                                (port->id << CMD_HDR_PORT_OFF) |
1171                                (priority << CMD_HDR_PRIORITY_OFF) |
1172                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
1173
1174         dw1 = 1 << CMD_HDR_VDTL_OFF;
1175         if (is_tmf) {
1176                 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1177                 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1178         } else {
1179                 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1180                 switch (scsi_cmnd->sc_data_direction) {
1181                 case DMA_TO_DEVICE:
1182                         has_data = 1;
1183                         dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1184                         break;
1185                 case DMA_FROM_DEVICE:
1186                         has_data = 1;
1187                         dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1188                         break;
1189                 default:
1190                         dw1 &= ~CMD_HDR_DIR_MSK;
1191                 }
1192         }
1193
1194         /* map itct entry */
1195         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1196         hdr->dw1 = cpu_to_le32(dw1);
1197
1198         dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1199               + 3) / 4) << CMD_HDR_CFL_OFF) |
1200               ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1201               (2 << CMD_HDR_SG_MOD_OFF);
1202         hdr->dw2 = cpu_to_le32(dw2);
1203
1204         hdr->transfer_tags = cpu_to_le32(slot->idx);
1205
1206         if (has_data) {
1207                 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1208                                         slot->n_elem);
1209                 if (rc)
1210                         return rc;
1211         }
1212
1213         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1214         hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
1215         hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1216
1217         buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr);
1218
1219         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1220         if (!is_tmf) {
1221                 buf_cmd[9] = task->ssp_task.task_attr |
1222                                 (task->ssp_task.task_prio << 3);
1223                 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1224                                 task->ssp_task.cmd->cmd_len);
1225         } else {
1226                 buf_cmd[10] = tmf->tmf;
1227                 switch (tmf->tmf) {
1228                 case TMF_ABORT_TASK:
1229                 case TMF_QUERY_TASK:
1230                         buf_cmd[12] =
1231                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1232                         buf_cmd[13] =
1233                                 tmf->tag_of_task_to_be_managed & 0xff;
1234                         break;
1235                 default:
1236                         break;
1237                 }
1238         }
1239
1240         return 0;
1241 }
1242
1243 static void sata_done_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1244                             struct hisi_sas_slot *slot)
1245 {
1246         struct task_status_struct *ts = &task->task_status;
1247         struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf;
1248         struct dev_to_host_fis *d2h = slot->status_buffer +
1249                                       sizeof(struct hisi_sas_err_record);
1250
1251         resp->frame_len = sizeof(struct dev_to_host_fis);
1252         memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis));
1253
1254         ts->buf_valid_size = sizeof(*resp);
1255 }
1256
1257 /* by default, task resp is complete */
1258 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
1259                            struct sas_task *task,
1260                            struct hisi_sas_slot *slot)
1261 {
1262         struct task_status_struct *ts = &task->task_status;
1263         struct hisi_sas_err_record_v2 *err_record = slot->status_buffer;
1264         u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
1265         u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
1266         u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
1267         u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
1268         u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
1269         int error = -1;
1270
1271         if (dma_rx_err_type) {
1272                 error = ffs(dma_rx_err_type)
1273                         - 1 + DMA_RX_ERR_BASE;
1274         } else if (sipc_rx_err_type) {
1275                 error = ffs(sipc_rx_err_type)
1276                         - 1 + SIPC_RX_ERR_BASE;
1277         }  else if (dma_tx_err_type) {
1278                 error = ffs(dma_tx_err_type)
1279                         - 1 + DMA_TX_ERR_BASE;
1280         } else if (trans_rx_fail_type) {
1281                 error = ffs(trans_rx_fail_type)
1282                         - 1 + TRANS_RX_FAIL_BASE;
1283         } else if (trans_tx_fail_type) {
1284                 error = ffs(trans_tx_fail_type)
1285                         - 1 + TRANS_TX_FAIL_BASE;
1286         }
1287
1288         switch (task->task_proto) {
1289         case SAS_PROTOCOL_SSP:
1290         {
1291                 switch (error) {
1292                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
1293                 {
1294                         ts->stat = SAS_OPEN_REJECT;
1295                         ts->open_rej_reason = SAS_OREJ_NO_DEST;
1296                         break;
1297                 }
1298                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
1299                 {
1300                         ts->stat = SAS_OPEN_REJECT;
1301                         ts->open_rej_reason = SAS_OREJ_PATH_BLOCKED;
1302                         break;
1303                 }
1304                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
1305                 {
1306                         ts->stat = SAS_OPEN_REJECT;
1307                         ts->open_rej_reason = SAS_OREJ_EPROTO;
1308                         break;
1309                 }
1310                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
1311                 {
1312                         ts->stat = SAS_OPEN_REJECT;
1313                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1314                         break;
1315                 }
1316                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
1317                 {
1318                         ts->stat = SAS_OPEN_REJECT;
1319                         ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1320                         break;
1321                 }
1322                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
1323                 {
1324                         ts->stat = SAS_OPEN_REJECT;
1325                         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1326                         break;
1327                 }
1328                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
1329                 {
1330                         ts->stat = SAS_OPEN_REJECT;
1331                         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1332                         break;
1333                 }
1334                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
1335                 {
1336                         ts->stat = SAS_OPEN_REJECT;
1337                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1338                         break;
1339                 }
1340                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
1341                 {
1342                         /* not sure */
1343                         ts->stat = SAS_DEV_NO_RESPONSE;
1344                         break;
1345                 }
1346                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
1347                 {
1348                         ts->stat = SAS_PHY_DOWN;
1349                         break;
1350                 }
1351                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
1352                 {
1353                         ts->stat = SAS_OPEN_TO;
1354                         break;
1355                 }
1356                 case DMA_RX_DATA_LEN_OVERFLOW:
1357                 {
1358                         ts->stat = SAS_DATA_OVERRUN;
1359                         ts->residual = 0;
1360                         break;
1361                 }
1362                 case DMA_RX_DATA_LEN_UNDERFLOW:
1363                 case SIPC_RX_DATA_UNDERFLOW_ERR:
1364                 {
1365                         ts->residual = trans_tx_fail_type;
1366                         ts->stat = SAS_DATA_UNDERRUN;
1367                         break;
1368                 }
1369                 case TRANS_TX_ERR_FRAME_TXED:
1370                 {
1371                         /* This will request a retry */
1372                         ts->stat = SAS_QUEUE_FULL;
1373                         slot->abort = 1;
1374                         break;
1375                 }
1376                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
1377                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
1378                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
1379                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
1380                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
1381                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
1382                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
1383                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
1384                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
1385                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
1386                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1387                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
1388                 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
1389                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
1390                 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
1391                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
1392                 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
1393                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
1394                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
1395                 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
1396                 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
1397                 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
1398                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
1399                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1400                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
1401                 case TRANS_RX_ERR_WITH_DATA_LEN0:
1402                 case TRANS_RX_ERR_WITH_BAD_HASH:
1403                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
1404                 case TRANS_RX_SSP_FRM_LEN_ERR:
1405                 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
1406                 case DMA_TX_UNEXP_XFER_ERR:
1407                 case DMA_TX_UNEXP_RETRANS_ERR:
1408                 case DMA_TX_XFER_LEN_OVERFLOW:
1409                 case DMA_TX_XFER_OFFSET_ERR:
1410                 case DMA_RX_DATA_OFFSET_ERR:
1411                 case DMA_RX_UNEXP_NORM_RESP_ERR:
1412                 case DMA_RX_UNEXP_RDFRAME_ERR:
1413                 case DMA_RX_UNKNOWN_FRM_ERR:
1414                 {
1415                         ts->stat = SAS_OPEN_REJECT;
1416                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1417                         break;
1418                 }
1419                 default:
1420                         break;
1421                 }
1422         }
1423                 break;
1424         case SAS_PROTOCOL_SMP:
1425                 ts->stat = SAM_STAT_CHECK_CONDITION;
1426                 break;
1427
1428         case SAS_PROTOCOL_SATA:
1429         case SAS_PROTOCOL_STP:
1430         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1431         {
1432                 switch (error) {
1433                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
1434                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
1435                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
1436                 {
1437                         ts->resp = SAS_TASK_UNDELIVERED;
1438                         ts->stat = SAS_DEV_NO_RESPONSE;
1439                         break;
1440                 }
1441                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
1442                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
1443                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
1444                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
1445                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
1446                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
1447                 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
1448                 {
1449                         ts->stat = SAS_OPEN_REJECT;
1450                         break;
1451                 }
1452                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
1453                 {
1454                         ts->stat = SAS_OPEN_TO;
1455                         break;
1456                 }
1457                 case DMA_RX_DATA_LEN_OVERFLOW:
1458                 {
1459                         ts->stat = SAS_DATA_OVERRUN;
1460                         break;
1461                 }
1462                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
1463                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
1464                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
1465                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
1466                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
1467                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
1468                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
1469                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
1470                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
1471                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
1472                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1473                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
1474                 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
1475                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
1476                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
1477                 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
1478                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
1479                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
1480                 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
1481                 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
1482                 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
1483                 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
1484                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
1485                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
1486                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
1487                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
1488                 case TRANS_RX_ERR_WITH_DATA_LEN0:
1489                 case TRANS_RX_ERR_WITH_BAD_HASH:
1490                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
1491                 case TRANS_RX_SSP_FRM_LEN_ERR:
1492                 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
1493                 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
1494                 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
1495                 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
1496                 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
1497                 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
1498                 case SIPC_RX_SATA_UNEXP_FIS_ERR:
1499                 case DMA_RX_SATA_FRAME_TYPE_ERR:
1500                 case DMA_RX_UNEXP_RDFRAME_ERR:
1501                 case DMA_RX_PIO_DATA_LEN_ERR:
1502                 case DMA_RX_RDSETUP_STATUS_ERR:
1503                 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
1504                 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
1505                 case DMA_RX_RDSETUP_LEN_ODD_ERR:
1506                 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
1507                 case DMA_RX_RDSETUP_LEN_OVER_ERR:
1508                 case DMA_RX_RDSETUP_OFFSET_ERR:
1509                 case DMA_RX_RDSETUP_ACTIVE_ERR:
1510                 case DMA_RX_RDSETUP_ESTATUS_ERR:
1511                 case DMA_RX_UNKNOWN_FRM_ERR:
1512                 {
1513                         ts->stat = SAS_OPEN_REJECT;
1514                         break;
1515                 }
1516                 default:
1517                 {
1518                         ts->stat = SAS_PROTO_RESPONSE;
1519                         break;
1520                 }
1521                 }
1522                 sata_done_v2_hw(hisi_hba, task, slot);
1523         }
1524                 break;
1525         default:
1526                 break;
1527         }
1528 }
1529
1530 static int
1531 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot,
1532                     int abort)
1533 {
1534         struct sas_task *task = slot->task;
1535         struct hisi_sas_device *sas_dev;
1536         struct device *dev = &hisi_hba->pdev->dev;
1537         struct task_status_struct *ts;
1538         struct domain_device *device;
1539         enum exec_status sts;
1540         struct hisi_sas_complete_v2_hdr *complete_queue =
1541                         hisi_hba->complete_hdr[slot->cmplt_queue];
1542         struct hisi_sas_complete_v2_hdr *complete_hdr =
1543                         &complete_queue[slot->cmplt_queue_slot];
1544
1545         if (unlikely(!task || !task->lldd_task || !task->dev))
1546                 return -EINVAL;
1547
1548         ts = &task->task_status;
1549         device = task->dev;
1550         sas_dev = device->lldd_dev;
1551
1552         task->task_state_flags &=
1553                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1554         task->task_state_flags |= SAS_TASK_STATE_DONE;
1555
1556         memset(ts, 0, sizeof(*ts));
1557         ts->resp = SAS_TASK_COMPLETE;
1558
1559         if (unlikely(!sas_dev || abort)) {
1560                 if (!sas_dev)
1561                         dev_dbg(dev, "slot complete: port has not device\n");
1562                 ts->stat = SAS_PHY_DOWN;
1563                 goto out;
1564         }
1565
1566         if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
1567                 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
1568
1569                 slot_err_v2_hw(hisi_hba, task, slot);
1570                 if (unlikely(slot->abort)) {
1571                         queue_work(hisi_hba->wq, &slot->abort_slot);
1572                         /* immediately return and do not complete */
1573                         return ts->stat;
1574                 }
1575                 goto out;
1576         }
1577
1578         switch (task->task_proto) {
1579         case SAS_PROTOCOL_SSP:
1580         {
1581                 struct ssp_response_iu *iu = slot->status_buffer +
1582                         sizeof(struct hisi_sas_err_record);
1583
1584                 sas_ssp_task_response(dev, task, iu);
1585                 break;
1586         }
1587         case SAS_PROTOCOL_SMP:
1588         {
1589                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1590                 void *to;
1591
1592                 ts->stat = SAM_STAT_GOOD;
1593                 to = kmap_atomic(sg_page(sg_resp));
1594
1595                 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1596                              DMA_FROM_DEVICE);
1597                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1598                              DMA_TO_DEVICE);
1599                 memcpy(to + sg_resp->offset,
1600                        slot->status_buffer +
1601                        sizeof(struct hisi_sas_err_record),
1602                        sg_dma_len(sg_resp));
1603                 kunmap_atomic(to);
1604                 break;
1605         }
1606         case SAS_PROTOCOL_SATA:
1607         case SAS_PROTOCOL_STP:
1608         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1609         {
1610                 ts->stat = SAM_STAT_GOOD;
1611                 sata_done_v2_hw(hisi_hba, task, slot);
1612                 break;
1613         }
1614         default:
1615                 ts->stat = SAM_STAT_CHECK_CONDITION;
1616                 break;
1617         }
1618
1619         if (!slot->port->port_attached) {
1620                 dev_err(dev, "slot complete: port %d has removed\n",
1621                         slot->port->sas_port.id);
1622                 ts->stat = SAS_PHY_DOWN;
1623         }
1624
1625 out:
1626         if (sas_dev && sas_dev->running_req)
1627                 sas_dev->running_req--;
1628
1629         hisi_sas_slot_task_free(hisi_hba, task, slot);
1630         sts = ts->stat;
1631
1632         if (task->task_done)
1633                 task->task_done(task);
1634
1635         return sts;
1636 }
1637
1638 static u8 get_ata_protocol(u8 cmd, int direction)
1639 {
1640         switch (cmd) {
1641         case ATA_CMD_FPDMA_WRITE:
1642         case ATA_CMD_FPDMA_READ:
1643         case ATA_CMD_FPDMA_RECV:
1644         case ATA_CMD_FPDMA_SEND:
1645         case ATA_CMD_NCQ_NON_DATA:
1646         return SATA_PROTOCOL_FPDMA;
1647
1648         case ATA_CMD_ID_ATA:
1649         case ATA_CMD_PMP_READ:
1650         case ATA_CMD_READ_LOG_EXT:
1651         case ATA_CMD_PIO_READ:
1652         case ATA_CMD_PIO_READ_EXT:
1653         case ATA_CMD_PMP_WRITE:
1654         case ATA_CMD_WRITE_LOG_EXT:
1655         case ATA_CMD_PIO_WRITE:
1656         case ATA_CMD_PIO_WRITE_EXT:
1657         return SATA_PROTOCOL_PIO;
1658
1659         case ATA_CMD_READ:
1660         case ATA_CMD_READ_EXT:
1661         case ATA_CMD_READ_LOG_DMA_EXT:
1662         case ATA_CMD_WRITE:
1663         case ATA_CMD_WRITE_EXT:
1664         case ATA_CMD_WRITE_QUEUED:
1665         case ATA_CMD_WRITE_LOG_DMA_EXT:
1666         return SATA_PROTOCOL_DMA;
1667
1668         case ATA_CMD_DOWNLOAD_MICRO:
1669         case ATA_CMD_DEV_RESET:
1670         case ATA_CMD_CHK_POWER:
1671         case ATA_CMD_FLUSH:
1672         case ATA_CMD_FLUSH_EXT:
1673         case ATA_CMD_VERIFY:
1674         case ATA_CMD_VERIFY_EXT:
1675         case ATA_CMD_SET_FEATURES:
1676         case ATA_CMD_STANDBY:
1677         case ATA_CMD_STANDBYNOW1:
1678         return SATA_PROTOCOL_NONDATA;
1679         default:
1680                 if (direction == DMA_NONE)
1681                         return SATA_PROTOCOL_NONDATA;
1682                 return SATA_PROTOCOL_PIO;
1683         }
1684 }
1685
1686 static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag)
1687 {
1688         struct ata_queued_cmd *qc = task->uldd_task;
1689
1690         if (qc) {
1691                 if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
1692                         qc->tf.command == ATA_CMD_FPDMA_READ) {
1693                         *tag = qc->tag;
1694                         return 1;
1695                 }
1696         }
1697         return 0;
1698 }
1699
1700 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba,
1701                           struct hisi_sas_slot *slot)
1702 {
1703         struct sas_task *task = slot->task;
1704         struct domain_device *device = task->dev;
1705         struct domain_device *parent_dev = device->parent;
1706         struct hisi_sas_device *sas_dev = device->lldd_dev;
1707         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1708         struct hisi_sas_port *port = device->port->lldd_port;
1709         u8 *buf_cmd;
1710         int has_data = 0, rc = 0, hdr_tag = 0;
1711         u32 dw1 = 0, dw2 = 0;
1712
1713         /* create header */
1714         /* dw0 */
1715         hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1716         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1717                 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1718         else
1719                 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1720
1721         /* dw1 */
1722         switch (task->data_dir) {
1723         case DMA_TO_DEVICE:
1724                 has_data = 1;
1725                 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1726                 break;
1727         case DMA_FROM_DEVICE:
1728                 has_data = 1;
1729                 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1730                 break;
1731         default:
1732                 dw1 &= ~CMD_HDR_DIR_MSK;
1733         }
1734
1735         if (0 == task->ata_task.fis.command)
1736                 dw1 |= 1 << CMD_HDR_RESET_OFF;
1737
1738         dw1 |= (get_ata_protocol(task->ata_task.fis.command, task->data_dir))
1739                 << CMD_HDR_FRAME_TYPE_OFF;
1740         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1741         hdr->dw1 = cpu_to_le32(dw1);
1742
1743         /* dw2 */
1744         if (task->ata_task.use_ncq && get_ncq_tag_v2_hw(task, &hdr_tag)) {
1745                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1746                 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1747         }
1748
1749         dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1750                         2 << CMD_HDR_SG_MOD_OFF;
1751         hdr->dw2 = cpu_to_le32(dw2);
1752
1753         /* dw3 */
1754         hdr->transfer_tags = cpu_to_le32(slot->idx);
1755
1756         if (has_data) {
1757                 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1758                                         slot->n_elem);
1759                 if (rc)
1760                         return rc;
1761         }
1762
1763
1764         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1765         hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
1766         hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1767
1768         buf_cmd = slot->command_table;
1769
1770         if (likely(!task->ata_task.device_control_reg_update))
1771                 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1772         /* fill in command FIS */
1773         memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1774
1775         return 0;
1776 }
1777
1778 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1779 {
1780         int i, res = 0;
1781         u32 context, port_id, link_rate, hard_phy_linkrate;
1782         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1783         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1784         struct device *dev = &hisi_hba->pdev->dev;
1785         u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1786         struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
1787
1788         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1789
1790         /* Check for SATA dev */
1791         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1792         if (context & (1 << phy_no))
1793                 goto end;
1794
1795         if (phy_no == 8) {
1796                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1797
1798                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1799                           PORT_STATE_PHY8_PORT_NUM_OFF;
1800                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
1801                             PORT_STATE_PHY8_CONN_RATE_OFF;
1802         } else {
1803                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1804                 port_id = (port_id >> (4 * phy_no)) & 0xf;
1805                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1806                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1807         }
1808
1809         if (port_id == 0xf) {
1810                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1811                 res = IRQ_NONE;
1812                 goto end;
1813         }
1814
1815         for (i = 0; i < 6; i++) {
1816                 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1817                                                RX_IDAF_DWORD0 + (i * 4));
1818                 frame_rcvd[i] = __swab32(idaf);
1819         }
1820
1821         /* Get the linkrates */
1822         link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1823         link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1824         sas_phy->linkrate = link_rate;
1825         hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1826                                                 HARD_PHY_LINKRATE);
1827         phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1828         phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1829
1830         sas_phy->oob_mode = SAS_OOB_MODE;
1831         memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
1832         dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1833         phy->port_id = port_id;
1834         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1835         phy->phy_type |= PORT_TYPE_SAS;
1836         phy->phy_attached = 1;
1837         phy->identify.device_type = id->dev_type;
1838         phy->frame_rcvd_size =  sizeof(struct sas_identify_frame);
1839         if (phy->identify.device_type == SAS_END_DEVICE)
1840                 phy->identify.target_port_protocols =
1841                         SAS_PROTOCOL_SSP;
1842         else if (phy->identify.device_type != SAS_PHY_UNUSED)
1843                 phy->identify.target_port_protocols =
1844                         SAS_PROTOCOL_SMP;
1845         queue_work(hisi_hba->wq, &phy->phyup_ws);
1846
1847 end:
1848         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1849                              CHL_INT0_SL_PHY_ENABLE_MSK);
1850         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1851
1852         return res;
1853 }
1854
1855 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1856 {
1857         int res = 0;
1858         u32 phy_cfg, phy_state;
1859
1860         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1861
1862         phy_cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1863
1864         phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1865
1866         hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1867
1868         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1869         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1870
1871         return res;
1872 }
1873
1874 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
1875 {
1876         struct hisi_hba *hisi_hba = p;
1877         u32 irq_msk;
1878         int phy_no = 0;
1879         irqreturn_t res = IRQ_HANDLED;
1880
1881         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
1882                    >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
1883         while (irq_msk) {
1884                 if (irq_msk  & 1) {
1885                         u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1886                                                             CHL_INT0);
1887
1888                         if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1889                                 /* phy up */
1890                                 if (phy_up_v2_hw(phy_no, hisi_hba)) {
1891                                         res = IRQ_NONE;
1892                                         goto end;
1893                                 }
1894
1895                         if (irq_value & CHL_INT0_NOT_RDY_MSK)
1896                                 /* phy down */
1897                                 if (phy_down_v2_hw(phy_no, hisi_hba)) {
1898                                         res = IRQ_NONE;
1899                                         goto end;
1900                                 }
1901                 }
1902                 irq_msk >>= 1;
1903                 phy_no++;
1904         }
1905
1906 end:
1907         return res;
1908 }
1909
1910 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1911 {
1912         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1913         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1914         struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1915
1916         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1917         sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1918         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1919                              CHL_INT0_SL_RX_BCST_ACK_MSK);
1920         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1921 }
1922
1923 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
1924 {
1925         struct hisi_hba *hisi_hba = p;
1926         struct device *dev = &hisi_hba->pdev->dev;
1927         u32 ent_msk, ent_tmp, irq_msk;
1928         int phy_no = 0;
1929
1930         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1931         ent_tmp = ent_msk;
1932         ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1933         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1934
1935         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
1936                         HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
1937
1938         while (irq_msk) {
1939                 if (irq_msk & (1 << phy_no)) {
1940                         u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1941                                                              CHL_INT0);
1942                         u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1943                                                              CHL_INT1);
1944                         u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1945                                                              CHL_INT2);
1946
1947                         if (irq_value1) {
1948                                 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
1949                                                   CHL_INT1_DMAC_TX_ECC_ERR_MSK))
1950                                         panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
1951                                                 dev_name(dev), irq_value1);
1952
1953                                 hisi_sas_phy_write32(hisi_hba, phy_no,
1954                                                      CHL_INT1, irq_value1);
1955                         }
1956
1957                         if (irq_value2)
1958                                 hisi_sas_phy_write32(hisi_hba, phy_no,
1959                                                      CHL_INT2, irq_value2);
1960
1961
1962                         if (irq_value0) {
1963                                 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
1964                                         phy_bcast_v2_hw(phy_no, hisi_hba);
1965
1966                                 hisi_sas_phy_write32(hisi_hba, phy_no,
1967                                                 CHL_INT0, irq_value0
1968                                                 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
1969                                                 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1970                                                 & (~CHL_INT0_NOT_RDY_MSK));
1971                         }
1972                 }
1973                 irq_msk &= ~(1 << phy_no);
1974                 phy_no++;
1975         }
1976
1977         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
1978
1979         return IRQ_HANDLED;
1980 }
1981
1982 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
1983 {
1984         struct hisi_sas_cq *cq = p;
1985         struct hisi_hba *hisi_hba = cq->hisi_hba;
1986         struct hisi_sas_slot *slot;
1987         struct hisi_sas_itct *itct;
1988         struct hisi_sas_complete_v2_hdr *complete_queue;
1989         u32 irq_value, rd_point, wr_point, dev_id;
1990         int queue = cq->id;
1991
1992         complete_queue = hisi_hba->complete_hdr[queue];
1993         irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC);
1994
1995         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1996
1997         rd_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_RD_PTR +
1998                                    (0x14 * queue));
1999         wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
2000                                    (0x14 * queue));
2001
2002         while (rd_point != wr_point) {
2003                 struct hisi_sas_complete_v2_hdr *complete_hdr;
2004                 int iptt;
2005
2006                 complete_hdr = &complete_queue[rd_point];
2007
2008                 /* Check for NCQ completion */
2009                 if (complete_hdr->act) {
2010                         u32 act_tmp = complete_hdr->act;
2011                         int ncq_tag_count = ffs(act_tmp);
2012
2013                         dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
2014                                  CMPLT_HDR_DEV_ID_OFF;
2015                         itct = &hisi_hba->itct[dev_id];
2016
2017                         /* The NCQ tags are held in the itct header */
2018                         while (ncq_tag_count) {
2019                                 __le64 *ncq_tag = &itct->qw4_15[0];
2020
2021                                 ncq_tag_count -= 1;
2022                                 iptt = (ncq_tag[ncq_tag_count / 5]
2023                                         >> (ncq_tag_count % 5) * 12) & 0xfff;
2024
2025                                 slot = &hisi_hba->slot_info[iptt];
2026                                 slot->cmplt_queue_slot = rd_point;
2027                                 slot->cmplt_queue = queue;
2028                                 slot_complete_v2_hw(hisi_hba, slot, 0);
2029
2030                                 act_tmp &= ~(1 << ncq_tag_count);
2031                                 ncq_tag_count = ffs(act_tmp);
2032                         }
2033                 } else {
2034                         iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
2035                         slot = &hisi_hba->slot_info[iptt];
2036                         slot->cmplt_queue_slot = rd_point;
2037                         slot->cmplt_queue = queue;
2038                         slot_complete_v2_hw(hisi_hba, slot, 0);
2039                 }
2040
2041                 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
2042                         rd_point = 0;
2043         }
2044
2045         /* update rd_point */
2046         hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
2047         return IRQ_HANDLED;
2048 }
2049
2050 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
2051 {
2052         struct hisi_sas_phy *phy = p;
2053         struct hisi_hba *hisi_hba = phy->hisi_hba;
2054         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2055         struct device *dev = &hisi_hba->pdev->dev;
2056         struct  hisi_sas_initial_fis *initial_fis;
2057         struct dev_to_host_fis *fis;
2058         u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
2059         irqreturn_t res = IRQ_HANDLED;
2060         u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
2061         int phy_no, offset;
2062
2063         phy_no = sas_phy->id;
2064         initial_fis = &hisi_hba->initial_fis[phy_no];
2065         fis = &initial_fis->fis;
2066
2067         offset = 4 * (phy_no / 4);
2068         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
2069         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
2070                          ent_msk | 1 << ((phy_no % 4) * 8));
2071
2072         ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
2073         ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
2074                              (phy_no % 4)));
2075         ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
2076         if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
2077                 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
2078                 res = IRQ_NONE;
2079                 goto end;
2080         }
2081
2082         if (unlikely(phy_no == 8)) {
2083                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2084
2085                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2086                           PORT_STATE_PHY8_PORT_NUM_OFF;
2087                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2088                             PORT_STATE_PHY8_CONN_RATE_OFF;
2089         } else {
2090                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2091                 port_id = (port_id >> (4 * phy_no)) & 0xf;
2092                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2093                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2094         }
2095
2096         if (port_id == 0xf) {
2097                 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
2098                 res = IRQ_NONE;
2099                 goto end;
2100         }
2101
2102         sas_phy->linkrate = link_rate;
2103         hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
2104                                                 HARD_PHY_LINKRATE);
2105         phy->maximum_linkrate = hard_phy_linkrate & 0xf;
2106         phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
2107
2108         sas_phy->oob_mode = SATA_OOB_MODE;
2109         /* Make up some unique SAS address */
2110         attached_sas_addr[0] = 0x50;
2111         attached_sas_addr[7] = phy_no;
2112         memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
2113         memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
2114         dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2115         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2116         phy->port_id = port_id;
2117         phy->phy_type |= PORT_TYPE_SATA;
2118         phy->phy_attached = 1;
2119         phy->identify.device_type = SAS_SATA_DEV;
2120         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2121         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2122         queue_work(hisi_hba->wq, &phy->phyup_ws);
2123
2124 end:
2125         hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
2126         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
2127
2128         return res;
2129 }
2130
2131 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
2132         int_phy_updown_v2_hw,
2133         int_chnl_int_v2_hw,
2134 };
2135
2136 /**
2137  * There is a limitation in the hip06 chipset that we need
2138  * to map in all mbigen interrupts, even if they are not used.
2139  */
2140 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
2141 {
2142         struct platform_device *pdev = hisi_hba->pdev;
2143         struct device *dev = &pdev->dev;
2144         int i, irq, rc, irq_map[128];
2145
2146
2147         for (i = 0; i < 128; i++)
2148                 irq_map[i] = platform_get_irq(pdev, i);
2149
2150         for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
2151                 int idx = i;
2152
2153                 irq = irq_map[idx + 1]; /* Phy up/down is irq1 */
2154                 if (!irq) {
2155                         dev_err(dev, "irq init: fail map phy interrupt %d\n",
2156                                 idx);
2157                         return -ENOENT;
2158                 }
2159
2160                 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
2161                                       DRV_NAME " phy", hisi_hba);
2162                 if (rc) {
2163                         dev_err(dev, "irq init: could not request "
2164                                 "phy interrupt %d, rc=%d\n",
2165                                 irq, rc);
2166                         return -ENOENT;
2167                 }
2168         }
2169
2170         for (i = 0; i < hisi_hba->n_phy; i++) {
2171                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
2172                 int idx = i + 72; /* First SATA interrupt is irq72 */
2173
2174                 irq = irq_map[idx];
2175                 if (!irq) {
2176                         dev_err(dev, "irq init: fail map phy interrupt %d\n",
2177                                 idx);
2178                         return -ENOENT;
2179                 }
2180
2181                 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
2182                                       DRV_NAME " sata", phy);
2183                 if (rc) {
2184                         dev_err(dev, "irq init: could not request "
2185                                 "sata interrupt %d, rc=%d\n",
2186                                 irq, rc);
2187                         return -ENOENT;
2188                 }
2189         }
2190
2191         for (i = 0; i < hisi_hba->queue_count; i++) {
2192                 int idx = i + 96; /* First cq interrupt is irq96 */
2193
2194                 irq = irq_map[idx];
2195                 if (!irq) {
2196                         dev_err(dev,
2197                                 "irq init: could not map cq interrupt %d\n",
2198                                 idx);
2199                         return -ENOENT;
2200                 }
2201                 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
2202                                       DRV_NAME " cq", &hisi_hba->cq[i]);
2203                 if (rc) {
2204                         dev_err(dev,
2205                                 "irq init: could not request cq interrupt %d, rc=%d\n",
2206                                 irq, rc);
2207                         return -ENOENT;
2208                 }
2209         }
2210
2211         return 0;
2212 }
2213
2214 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
2215 {
2216         int rc;
2217
2218         rc = hw_init_v2_hw(hisi_hba);
2219         if (rc)
2220                 return rc;
2221
2222         rc = interrupt_init_v2_hw(hisi_hba);
2223         if (rc)
2224                 return rc;
2225
2226         phys_init_v2_hw(hisi_hba);
2227
2228         return 0;
2229 }
2230
2231 static const struct hisi_sas_hw hisi_sas_v2_hw = {
2232         .hw_init = hisi_sas_v2_init,
2233         .setup_itct = setup_itct_v2_hw,
2234         .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
2235         .alloc_dev = alloc_dev_quirk_v2_hw,
2236         .sl_notify = sl_notify_v2_hw,
2237         .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
2238         .free_device = free_device_v2_hw,
2239         .prep_smp = prep_smp_v2_hw,
2240         .prep_ssp = prep_ssp_v2_hw,
2241         .prep_stp = prep_ata_v2_hw,
2242         .get_free_slot = get_free_slot_v2_hw,
2243         .start_delivery = start_delivery_v2_hw,
2244         .slot_complete = slot_complete_v2_hw,
2245         .phy_enable = enable_phy_v2_hw,
2246         .phy_disable = disable_phy_v2_hw,
2247         .phy_hard_reset = phy_hard_reset_v2_hw,
2248         .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
2249         .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
2250 };
2251
2252 static int hisi_sas_v2_probe(struct platform_device *pdev)
2253 {
2254         return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
2255 }
2256
2257 static int hisi_sas_v2_remove(struct platform_device *pdev)
2258 {
2259         return hisi_sas_remove(pdev);
2260 }
2261
2262 static const struct of_device_id sas_v2_of_match[] = {
2263         { .compatible = "hisilicon,hip06-sas-v2",},
2264         {},
2265 };
2266 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
2267
2268 static const struct acpi_device_id sas_v2_acpi_match[] = {
2269         { "HISI0162", 0 },
2270         { }
2271 };
2272
2273 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
2274
2275 static struct platform_driver hisi_sas_v2_driver = {
2276         .probe = hisi_sas_v2_probe,
2277         .remove = hisi_sas_v2_remove,
2278         .driver = {
2279                 .name = DRV_NAME,
2280                 .of_match_table = sas_v2_of_match,
2281                 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
2282         },
2283 };
2284
2285 module_platform_driver(hisi_sas_v2_driver);
2286
2287 MODULE_LICENSE("GPL");
2288 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2289 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
2290 MODULE_ALIAS("platform:" DRV_NAME);