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fb: adv7393: off by one in probe function
[deliverable/linux.git] / drivers / spi / spi-sh-msiof.c
1 /*
2 * SuperH MSIOF SPI Master Interface
3 *
4 * Copyright (c) 2009 Magnus Damm
5 * Copyright (C) 2014 Glider bvba
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13 #include <linux/bitmap.h>
14 #include <linux/clk.h>
15 #include <linux/completion.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/dmaengine.h>
19 #include <linux/err.h>
20 #include <linux/gpio.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/sh_dma.h>
30
31 #include <linux/spi/sh_msiof.h>
32 #include <linux/spi/spi.h>
33
34 #include <asm/unaligned.h>
35
36
37 struct sh_msiof_chipdata {
38 u16 tx_fifo_size;
39 u16 rx_fifo_size;
40 u16 master_flags;
41 };
42
43 struct sh_msiof_spi_priv {
44 struct spi_master *master;
45 void __iomem *mapbase;
46 struct clk *clk;
47 struct platform_device *pdev;
48 struct sh_msiof_spi_info *info;
49 struct completion done;
50 unsigned int tx_fifo_size;
51 unsigned int rx_fifo_size;
52 void *tx_dma_page;
53 void *rx_dma_page;
54 dma_addr_t tx_dma_addr;
55 dma_addr_t rx_dma_addr;
56 };
57
58 #define TMDR1 0x00 /* Transmit Mode Register 1 */
59 #define TMDR2 0x04 /* Transmit Mode Register 2 */
60 #define TMDR3 0x08 /* Transmit Mode Register 3 */
61 #define RMDR1 0x10 /* Receive Mode Register 1 */
62 #define RMDR2 0x14 /* Receive Mode Register 2 */
63 #define RMDR3 0x18 /* Receive Mode Register 3 */
64 #define TSCR 0x20 /* Transmit Clock Select Register */
65 #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
66 #define CTR 0x28 /* Control Register */
67 #define FCTR 0x30 /* FIFO Control Register */
68 #define STR 0x40 /* Status Register */
69 #define IER 0x44 /* Interrupt Enable Register */
70 #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
71 #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
72 #define TFDR 0x50 /* Transmit FIFO Data Register */
73 #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
74 #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
75 #define RFDR 0x60 /* Receive FIFO Data Register */
76
77 /* TMDR1 and RMDR1 */
78 #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
79 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
80 #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
81 #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
82 #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
83 #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
84 #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
85 #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
86 #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
87 #define MDR1_FLD_SHIFT 2
88 #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
89 /* TMDR1 */
90 #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
91
92 /* TMDR2 and RMDR2 */
93 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
94 #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
95 #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
96
97 /* TSCR and RSCR */
98 #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
99 #define SCR_BRPS(i) (((i) - 1) << 8)
100 #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
101 #define SCR_BRDV_DIV_2 0x0000
102 #define SCR_BRDV_DIV_4 0x0001
103 #define SCR_BRDV_DIV_8 0x0002
104 #define SCR_BRDV_DIV_16 0x0003
105 #define SCR_BRDV_DIV_32 0x0004
106 #define SCR_BRDV_DIV_1 0x0007
107
108 /* CTR */
109 #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
110 #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
111 #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
112 #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
113 #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
114 #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
115 #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
116 #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
117 #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
118 #define CTR_TXDIZ_LOW 0x00000000 /* 0 */
119 #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
120 #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
121 #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
122 #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
123 #define CTR_TXE 0x00000200 /* Transmit Enable */
124 #define CTR_RXE 0x00000100 /* Receive Enable */
125
126 /* FCTR */
127 #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */
128 #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */
129 #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */
130 #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */
131 #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */
132 #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */
133 #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */
134 #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */
135 #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */
136 #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */
137 #define FCTR_TFUA_SHIFT 20
138 #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT)
139 #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */
140 #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */
141 #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */
142 #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */
143 #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */
144 #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */
145 #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */
146 #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */
147 #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */
148 #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */
149 #define FCTR_RFUA_SHIFT 4
150 #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT)
151
152 /* STR */
153 #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */
154 #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */
155 #define STR_TEOF 0x00800000 /* Frame Transmission End */
156 #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */
157 #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */
158 #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */
159 #define STR_RFFUL 0x00002000 /* Receive FIFO Full */
160 #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */
161 #define STR_REOF 0x00000080 /* Frame Reception End */
162 #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */
163 #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */
164 #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */
165
166 /* IER */
167 #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */
168 #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */
169 #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */
170 #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */
171 #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */
172 #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */
173 #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */
174 #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */
175 #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */
176 #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */
177 #define IER_REOFE 0x00000080 /* Frame Reception End Enable */
178 #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */
179 #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */
180 #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */
181
182
183 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
184 {
185 switch (reg_offs) {
186 case TSCR:
187 case RSCR:
188 return ioread16(p->mapbase + reg_offs);
189 default:
190 return ioread32(p->mapbase + reg_offs);
191 }
192 }
193
194 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
195 u32 value)
196 {
197 switch (reg_offs) {
198 case TSCR:
199 case RSCR:
200 iowrite16(value, p->mapbase + reg_offs);
201 break;
202 default:
203 iowrite32(value, p->mapbase + reg_offs);
204 break;
205 }
206 }
207
208 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
209 u32 clr, u32 set)
210 {
211 u32 mask = clr | set;
212 u32 data;
213 int k;
214
215 data = sh_msiof_read(p, CTR);
216 data &= ~clr;
217 data |= set;
218 sh_msiof_write(p, CTR, data);
219
220 for (k = 100; k > 0; k--) {
221 if ((sh_msiof_read(p, CTR) & mask) == set)
222 break;
223
224 udelay(10);
225 }
226
227 return k > 0 ? 0 : -ETIMEDOUT;
228 }
229
230 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
231 {
232 struct sh_msiof_spi_priv *p = data;
233
234 /* just disable the interrupt and wake up */
235 sh_msiof_write(p, IER, 0);
236 complete(&p->done);
237
238 return IRQ_HANDLED;
239 }
240
241 static struct {
242 unsigned short div;
243 unsigned short brdv;
244 } const sh_msiof_spi_div_table[] = {
245 { 1, SCR_BRDV_DIV_1 },
246 { 2, SCR_BRDV_DIV_2 },
247 { 4, SCR_BRDV_DIV_4 },
248 { 8, SCR_BRDV_DIV_8 },
249 { 16, SCR_BRDV_DIV_16 },
250 { 32, SCR_BRDV_DIV_32 },
251 };
252
253 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
254 unsigned long parent_rate, u32 spi_hz)
255 {
256 unsigned long div = 1024;
257 u32 brps, scr;
258 size_t k;
259
260 if (!WARN_ON(!spi_hz || !parent_rate))
261 div = DIV_ROUND_UP(parent_rate, spi_hz);
262
263 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) {
264 brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div);
265 if (brps <= 32) /* max of brdv is 32 */
266 break;
267 }
268
269 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1);
270
271 scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps);
272 sh_msiof_write(p, TSCR, scr);
273 if (!(p->master->flags & SPI_MASTER_MUST_TX))
274 sh_msiof_write(p, RSCR, scr);
275 }
276
277 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
278 {
279 /*
280 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
281 * b'000 : 0
282 * b'001 : 100
283 * b'010 : 200
284 * b'011 (SYNCDL only) : 300
285 * b'101 : 50
286 * b'110 : 150
287 */
288 if (dtdl_or_syncdl % 100)
289 return dtdl_or_syncdl / 100 + 5;
290 else
291 return dtdl_or_syncdl / 100;
292 }
293
294 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
295 {
296 u32 val;
297
298 if (!p->info)
299 return 0;
300
301 /* check if DTDL and SYNCDL is allowed value */
302 if (p->info->dtdl > 200 || p->info->syncdl > 300) {
303 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
304 return 0;
305 }
306
307 /* check if the sum of DTDL and SYNCDL becomes an integer value */
308 if ((p->info->dtdl + p->info->syncdl) % 100) {
309 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
310 return 0;
311 }
312
313 val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
314 val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
315
316 return val;
317 }
318
319 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
320 u32 cpol, u32 cpha,
321 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
322 {
323 u32 tmp;
324 int edge;
325
326 /*
327 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
328 * 0 0 10 10 1 1
329 * 0 1 10 10 0 0
330 * 1 0 11 11 0 0
331 * 1 1 11 11 1 1
332 */
333 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
334 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
335 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
336 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
337 sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
338 if (p->master->flags & SPI_MASTER_MUST_TX) {
339 /* These bits are reserved if RX needs TX */
340 tmp &= ~0x0000ffff;
341 }
342 sh_msiof_write(p, RMDR1, tmp);
343
344 tmp = 0;
345 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
346 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
347
348 edge = cpol ^ !cpha;
349
350 tmp |= edge << CTR_TEDG_SHIFT;
351 tmp |= edge << CTR_REDG_SHIFT;
352 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
353 sh_msiof_write(p, CTR, tmp);
354 }
355
356 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
357 const void *tx_buf, void *rx_buf,
358 u32 bits, u32 words)
359 {
360 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
361
362 if (tx_buf || (p->master->flags & SPI_MASTER_MUST_TX))
363 sh_msiof_write(p, TMDR2, dr2);
364 else
365 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
366
367 if (rx_buf)
368 sh_msiof_write(p, RMDR2, dr2);
369 }
370
371 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
372 {
373 sh_msiof_write(p, STR, sh_msiof_read(p, STR));
374 }
375
376 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
377 const void *tx_buf, int words, int fs)
378 {
379 const u8 *buf_8 = tx_buf;
380 int k;
381
382 for (k = 0; k < words; k++)
383 sh_msiof_write(p, TFDR, buf_8[k] << fs);
384 }
385
386 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
387 const void *tx_buf, int words, int fs)
388 {
389 const u16 *buf_16 = tx_buf;
390 int k;
391
392 for (k = 0; k < words; k++)
393 sh_msiof_write(p, TFDR, buf_16[k] << fs);
394 }
395
396 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
397 const void *tx_buf, int words, int fs)
398 {
399 const u16 *buf_16 = tx_buf;
400 int k;
401
402 for (k = 0; k < words; k++)
403 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
404 }
405
406 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
407 const void *tx_buf, int words, int fs)
408 {
409 const u32 *buf_32 = tx_buf;
410 int k;
411
412 for (k = 0; k < words; k++)
413 sh_msiof_write(p, TFDR, buf_32[k] << fs);
414 }
415
416 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
417 const void *tx_buf, int words, int fs)
418 {
419 const u32 *buf_32 = tx_buf;
420 int k;
421
422 for (k = 0; k < words; k++)
423 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
424 }
425
426 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
427 const void *tx_buf, int words, int fs)
428 {
429 const u32 *buf_32 = tx_buf;
430 int k;
431
432 for (k = 0; k < words; k++)
433 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
434 }
435
436 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
437 const void *tx_buf, int words, int fs)
438 {
439 const u32 *buf_32 = tx_buf;
440 int k;
441
442 for (k = 0; k < words; k++)
443 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
444 }
445
446 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
447 void *rx_buf, int words, int fs)
448 {
449 u8 *buf_8 = rx_buf;
450 int k;
451
452 for (k = 0; k < words; k++)
453 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
454 }
455
456 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
457 void *rx_buf, int words, int fs)
458 {
459 u16 *buf_16 = rx_buf;
460 int k;
461
462 for (k = 0; k < words; k++)
463 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
464 }
465
466 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
467 void *rx_buf, int words, int fs)
468 {
469 u16 *buf_16 = rx_buf;
470 int k;
471
472 for (k = 0; k < words; k++)
473 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
474 }
475
476 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
477 void *rx_buf, int words, int fs)
478 {
479 u32 *buf_32 = rx_buf;
480 int k;
481
482 for (k = 0; k < words; k++)
483 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
484 }
485
486 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
487 void *rx_buf, int words, int fs)
488 {
489 u32 *buf_32 = rx_buf;
490 int k;
491
492 for (k = 0; k < words; k++)
493 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
494 }
495
496 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
497 void *rx_buf, int words, int fs)
498 {
499 u32 *buf_32 = rx_buf;
500 int k;
501
502 for (k = 0; k < words; k++)
503 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
504 }
505
506 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
507 void *rx_buf, int words, int fs)
508 {
509 u32 *buf_32 = rx_buf;
510 int k;
511
512 for (k = 0; k < words; k++)
513 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
514 }
515
516 static int sh_msiof_spi_setup(struct spi_device *spi)
517 {
518 struct device_node *np = spi->master->dev.of_node;
519 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
520
521 pm_runtime_get_sync(&p->pdev->dev);
522
523 if (!np) {
524 /*
525 * Use spi->controller_data for CS (same strategy as spi_gpio),
526 * if any. otherwise let HW control CS
527 */
528 spi->cs_gpio = (uintptr_t)spi->controller_data;
529 }
530
531 /* Configure pins before deasserting CS */
532 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
533 !!(spi->mode & SPI_CPHA),
534 !!(spi->mode & SPI_3WIRE),
535 !!(spi->mode & SPI_LSB_FIRST),
536 !!(spi->mode & SPI_CS_HIGH));
537
538 if (spi->cs_gpio >= 0)
539 gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
540
541
542 pm_runtime_put(&p->pdev->dev);
543
544 return 0;
545 }
546
547 static int sh_msiof_prepare_message(struct spi_master *master,
548 struct spi_message *msg)
549 {
550 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
551 const struct spi_device *spi = msg->spi;
552
553 /* Configure pins before asserting CS */
554 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
555 !!(spi->mode & SPI_CPHA),
556 !!(spi->mode & SPI_3WIRE),
557 !!(spi->mode & SPI_LSB_FIRST),
558 !!(spi->mode & SPI_CS_HIGH));
559 return 0;
560 }
561
562 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
563 {
564 int ret;
565
566 /* setup clock and rx/tx signals */
567 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
568 if (rx_buf && !ret)
569 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
570 if (!ret)
571 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
572
573 /* start by setting frame bit */
574 if (!ret)
575 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
576
577 return ret;
578 }
579
580 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
581 {
582 int ret;
583
584 /* shut down frame, rx/tx and clock signals */
585 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
586 if (!ret)
587 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
588 if (rx_buf && !ret)
589 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
590 if (!ret)
591 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
592
593 return ret;
594 }
595
596 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
597 void (*tx_fifo)(struct sh_msiof_spi_priv *,
598 const void *, int, int),
599 void (*rx_fifo)(struct sh_msiof_spi_priv *,
600 void *, int, int),
601 const void *tx_buf, void *rx_buf,
602 int words, int bits)
603 {
604 int fifo_shift;
605 int ret;
606
607 /* limit maximum word transfer to rx/tx fifo size */
608 if (tx_buf)
609 words = min_t(int, words, p->tx_fifo_size);
610 if (rx_buf)
611 words = min_t(int, words, p->rx_fifo_size);
612
613 /* the fifo contents need shifting */
614 fifo_shift = 32 - bits;
615
616 /* default FIFO watermarks for PIO */
617 sh_msiof_write(p, FCTR, 0);
618
619 /* setup msiof transfer mode registers */
620 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
621 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
622
623 /* write tx fifo */
624 if (tx_buf)
625 tx_fifo(p, tx_buf, words, fifo_shift);
626
627 reinit_completion(&p->done);
628
629 ret = sh_msiof_spi_start(p, rx_buf);
630 if (ret) {
631 dev_err(&p->pdev->dev, "failed to start hardware\n");
632 goto stop_ier;
633 }
634
635 /* wait for tx fifo to be emptied / rx fifo to be filled */
636 if (!wait_for_completion_timeout(&p->done, HZ)) {
637 dev_err(&p->pdev->dev, "PIO timeout\n");
638 ret = -ETIMEDOUT;
639 goto stop_reset;
640 }
641
642 /* read rx fifo */
643 if (rx_buf)
644 rx_fifo(p, rx_buf, words, fifo_shift);
645
646 /* clear status bits */
647 sh_msiof_reset_str(p);
648
649 ret = sh_msiof_spi_stop(p, rx_buf);
650 if (ret) {
651 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
652 return ret;
653 }
654
655 return words;
656
657 stop_reset:
658 sh_msiof_reset_str(p);
659 sh_msiof_spi_stop(p, rx_buf);
660 stop_ier:
661 sh_msiof_write(p, IER, 0);
662 return ret;
663 }
664
665 static void sh_msiof_dma_complete(void *arg)
666 {
667 struct sh_msiof_spi_priv *p = arg;
668
669 sh_msiof_write(p, IER, 0);
670 complete(&p->done);
671 }
672
673 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
674 void *rx, unsigned int len)
675 {
676 u32 ier_bits = 0;
677 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
678 dma_cookie_t cookie;
679 int ret;
680
681 /* First prepare and submit the DMA request(s), as this may fail */
682 if (rx) {
683 ier_bits |= IER_RDREQE | IER_RDMAE;
684 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
685 p->rx_dma_addr, len, DMA_FROM_DEVICE,
686 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
687 if (!desc_rx)
688 return -EAGAIN;
689
690 desc_rx->callback = sh_msiof_dma_complete;
691 desc_rx->callback_param = p;
692 cookie = dmaengine_submit(desc_rx);
693 if (dma_submit_error(cookie))
694 return cookie;
695 }
696
697 if (tx) {
698 ier_bits |= IER_TDREQE | IER_TDMAE;
699 dma_sync_single_for_device(p->master->dma_tx->device->dev,
700 p->tx_dma_addr, len, DMA_TO_DEVICE);
701 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
702 p->tx_dma_addr, len, DMA_TO_DEVICE,
703 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
704 if (!desc_tx) {
705 ret = -EAGAIN;
706 goto no_dma_tx;
707 }
708
709 if (rx) {
710 /* No callback */
711 desc_tx->callback = NULL;
712 } else {
713 desc_tx->callback = sh_msiof_dma_complete;
714 desc_tx->callback_param = p;
715 }
716 cookie = dmaengine_submit(desc_tx);
717 if (dma_submit_error(cookie)) {
718 ret = cookie;
719 goto no_dma_tx;
720 }
721 }
722
723 /* 1 stage FIFO watermarks for DMA */
724 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
725
726 /* setup msiof transfer mode registers (32-bit words) */
727 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
728
729 sh_msiof_write(p, IER, ier_bits);
730
731 reinit_completion(&p->done);
732
733 /* Now start DMA */
734 if (rx)
735 dma_async_issue_pending(p->master->dma_rx);
736 if (tx)
737 dma_async_issue_pending(p->master->dma_tx);
738
739 ret = sh_msiof_spi_start(p, rx);
740 if (ret) {
741 dev_err(&p->pdev->dev, "failed to start hardware\n");
742 goto stop_dma;
743 }
744
745 /* wait for tx fifo to be emptied / rx fifo to be filled */
746 if (!wait_for_completion_timeout(&p->done, HZ)) {
747 dev_err(&p->pdev->dev, "DMA timeout\n");
748 ret = -ETIMEDOUT;
749 goto stop_reset;
750 }
751
752 /* clear status bits */
753 sh_msiof_reset_str(p);
754
755 ret = sh_msiof_spi_stop(p, rx);
756 if (ret) {
757 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
758 return ret;
759 }
760
761 if (rx)
762 dma_sync_single_for_cpu(p->master->dma_rx->device->dev,
763 p->rx_dma_addr, len,
764 DMA_FROM_DEVICE);
765
766 return 0;
767
768 stop_reset:
769 sh_msiof_reset_str(p);
770 sh_msiof_spi_stop(p, rx);
771 stop_dma:
772 if (tx)
773 dmaengine_terminate_all(p->master->dma_tx);
774 no_dma_tx:
775 if (rx)
776 dmaengine_terminate_all(p->master->dma_rx);
777 sh_msiof_write(p, IER, 0);
778 return ret;
779 }
780
781 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
782 {
783 /* src or dst can be unaligned, but not both */
784 if ((unsigned long)src & 3) {
785 while (words--) {
786 *dst++ = swab32(get_unaligned(src));
787 src++;
788 }
789 } else if ((unsigned long)dst & 3) {
790 while (words--) {
791 put_unaligned(swab32(*src++), dst);
792 dst++;
793 }
794 } else {
795 while (words--)
796 *dst++ = swab32(*src++);
797 }
798 }
799
800 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
801 {
802 /* src or dst can be unaligned, but not both */
803 if ((unsigned long)src & 3) {
804 while (words--) {
805 *dst++ = swahw32(get_unaligned(src));
806 src++;
807 }
808 } else if ((unsigned long)dst & 3) {
809 while (words--) {
810 put_unaligned(swahw32(*src++), dst);
811 dst++;
812 }
813 } else {
814 while (words--)
815 *dst++ = swahw32(*src++);
816 }
817 }
818
819 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
820 {
821 memcpy(dst, src, words * 4);
822 }
823
824 static int sh_msiof_transfer_one(struct spi_master *master,
825 struct spi_device *spi,
826 struct spi_transfer *t)
827 {
828 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
829 void (*copy32)(u32 *, const u32 *, unsigned int);
830 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
831 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
832 const void *tx_buf = t->tx_buf;
833 void *rx_buf = t->rx_buf;
834 unsigned int len = t->len;
835 unsigned int bits = t->bits_per_word;
836 unsigned int bytes_per_word;
837 unsigned int words;
838 int n;
839 bool swab;
840 int ret;
841
842 /* setup clocks (clock already enabled in chipselect()) */
843 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
844
845 while (master->dma_tx && len > 15) {
846 /*
847 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
848 * words, with byte resp. word swapping.
849 */
850 unsigned int l = 0;
851
852 if (tx_buf)
853 l = min(len, p->tx_fifo_size * 4);
854 if (rx_buf)
855 l = min(len, p->rx_fifo_size * 4);
856
857 if (bits <= 8) {
858 if (l & 3)
859 break;
860 copy32 = copy_bswap32;
861 } else if (bits <= 16) {
862 if (l & 1)
863 break;
864 copy32 = copy_wswap32;
865 } else {
866 copy32 = copy_plain32;
867 }
868
869 if (tx_buf)
870 copy32(p->tx_dma_page, tx_buf, l / 4);
871
872 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
873 if (ret == -EAGAIN) {
874 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
875 dev_driver_string(&p->pdev->dev),
876 dev_name(&p->pdev->dev));
877 break;
878 }
879 if (ret)
880 return ret;
881
882 if (rx_buf) {
883 copy32(rx_buf, p->rx_dma_page, l / 4);
884 rx_buf += l;
885 }
886 if (tx_buf)
887 tx_buf += l;
888
889 len -= l;
890 if (!len)
891 return 0;
892 }
893
894 if (bits <= 8 && len > 15 && !(len & 3)) {
895 bits = 32;
896 swab = true;
897 } else {
898 swab = false;
899 }
900
901 /* setup bytes per word and fifo read/write functions */
902 if (bits <= 8) {
903 bytes_per_word = 1;
904 tx_fifo = sh_msiof_spi_write_fifo_8;
905 rx_fifo = sh_msiof_spi_read_fifo_8;
906 } else if (bits <= 16) {
907 bytes_per_word = 2;
908 if ((unsigned long)tx_buf & 0x01)
909 tx_fifo = sh_msiof_spi_write_fifo_16u;
910 else
911 tx_fifo = sh_msiof_spi_write_fifo_16;
912
913 if ((unsigned long)rx_buf & 0x01)
914 rx_fifo = sh_msiof_spi_read_fifo_16u;
915 else
916 rx_fifo = sh_msiof_spi_read_fifo_16;
917 } else if (swab) {
918 bytes_per_word = 4;
919 if ((unsigned long)tx_buf & 0x03)
920 tx_fifo = sh_msiof_spi_write_fifo_s32u;
921 else
922 tx_fifo = sh_msiof_spi_write_fifo_s32;
923
924 if ((unsigned long)rx_buf & 0x03)
925 rx_fifo = sh_msiof_spi_read_fifo_s32u;
926 else
927 rx_fifo = sh_msiof_spi_read_fifo_s32;
928 } else {
929 bytes_per_word = 4;
930 if ((unsigned long)tx_buf & 0x03)
931 tx_fifo = sh_msiof_spi_write_fifo_32u;
932 else
933 tx_fifo = sh_msiof_spi_write_fifo_32;
934
935 if ((unsigned long)rx_buf & 0x03)
936 rx_fifo = sh_msiof_spi_read_fifo_32u;
937 else
938 rx_fifo = sh_msiof_spi_read_fifo_32;
939 }
940
941 /* transfer in fifo sized chunks */
942 words = len / bytes_per_word;
943
944 while (words > 0) {
945 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
946 words, bits);
947 if (n < 0)
948 return n;
949
950 if (tx_buf)
951 tx_buf += n * bytes_per_word;
952 if (rx_buf)
953 rx_buf += n * bytes_per_word;
954 words -= n;
955 }
956
957 return 0;
958 }
959
960 static const struct sh_msiof_chipdata sh_data = {
961 .tx_fifo_size = 64,
962 .rx_fifo_size = 64,
963 .master_flags = 0,
964 };
965
966 static const struct sh_msiof_chipdata r8a779x_data = {
967 .tx_fifo_size = 64,
968 .rx_fifo_size = 64,
969 .master_flags = SPI_MASTER_MUST_TX,
970 };
971
972 static const struct of_device_id sh_msiof_match[] = {
973 { .compatible = "renesas,sh-msiof", .data = &sh_data },
974 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
975 { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data },
976 { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data },
977 { .compatible = "renesas,msiof-r8a7792", .data = &r8a779x_data },
978 { .compatible = "renesas,msiof-r8a7793", .data = &r8a779x_data },
979 { .compatible = "renesas,msiof-r8a7794", .data = &r8a779x_data },
980 {},
981 };
982 MODULE_DEVICE_TABLE(of, sh_msiof_match);
983
984 #ifdef CONFIG_OF
985 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
986 {
987 struct sh_msiof_spi_info *info;
988 struct device_node *np = dev->of_node;
989 u32 num_cs = 1;
990
991 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
992 if (!info)
993 return NULL;
994
995 /* Parse the MSIOF properties */
996 of_property_read_u32(np, "num-cs", &num_cs);
997 of_property_read_u32(np, "renesas,tx-fifo-size",
998 &info->tx_fifo_override);
999 of_property_read_u32(np, "renesas,rx-fifo-size",
1000 &info->rx_fifo_override);
1001 of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1002 of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
1003
1004 info->num_chipselect = num_cs;
1005
1006 return info;
1007 }
1008 #else
1009 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1010 {
1011 return NULL;
1012 }
1013 #endif
1014
1015 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
1016 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
1017 {
1018 dma_cap_mask_t mask;
1019 struct dma_chan *chan;
1020 struct dma_slave_config cfg;
1021 int ret;
1022
1023 dma_cap_zero(mask);
1024 dma_cap_set(DMA_SLAVE, mask);
1025
1026 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1027 (void *)(unsigned long)id, dev,
1028 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1029 if (!chan) {
1030 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1031 return NULL;
1032 }
1033
1034 memset(&cfg, 0, sizeof(cfg));
1035 cfg.direction = dir;
1036 if (dir == DMA_MEM_TO_DEV) {
1037 cfg.dst_addr = port_addr;
1038 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1039 } else {
1040 cfg.src_addr = port_addr;
1041 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1042 }
1043
1044 ret = dmaengine_slave_config(chan, &cfg);
1045 if (ret) {
1046 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1047 dma_release_channel(chan);
1048 return NULL;
1049 }
1050
1051 return chan;
1052 }
1053
1054 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1055 {
1056 struct platform_device *pdev = p->pdev;
1057 struct device *dev = &pdev->dev;
1058 const struct sh_msiof_spi_info *info = dev_get_platdata(dev);
1059 unsigned int dma_tx_id, dma_rx_id;
1060 const struct resource *res;
1061 struct spi_master *master;
1062 struct device *tx_dev, *rx_dev;
1063
1064 if (dev->of_node) {
1065 /* In the OF case we will get the slave IDs from the DT */
1066 dma_tx_id = 0;
1067 dma_rx_id = 0;
1068 } else if (info && info->dma_tx_id && info->dma_rx_id) {
1069 dma_tx_id = info->dma_tx_id;
1070 dma_rx_id = info->dma_rx_id;
1071 } else {
1072 /* The driver assumes no error */
1073 return 0;
1074 }
1075
1076 /* The DMA engine uses the second register set, if present */
1077 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1078 if (!res)
1079 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1080
1081 master = p->master;
1082 master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1083 dma_tx_id,
1084 res->start + TFDR);
1085 if (!master->dma_tx)
1086 return -ENODEV;
1087
1088 master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1089 dma_rx_id,
1090 res->start + RFDR);
1091 if (!master->dma_rx)
1092 goto free_tx_chan;
1093
1094 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1095 if (!p->tx_dma_page)
1096 goto free_rx_chan;
1097
1098 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1099 if (!p->rx_dma_page)
1100 goto free_tx_page;
1101
1102 tx_dev = master->dma_tx->device->dev;
1103 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1104 DMA_TO_DEVICE);
1105 if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1106 goto free_rx_page;
1107
1108 rx_dev = master->dma_rx->device->dev;
1109 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1110 DMA_FROM_DEVICE);
1111 if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1112 goto unmap_tx_page;
1113
1114 dev_info(dev, "DMA available");
1115 return 0;
1116
1117 unmap_tx_page:
1118 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1119 free_rx_page:
1120 free_page((unsigned long)p->rx_dma_page);
1121 free_tx_page:
1122 free_page((unsigned long)p->tx_dma_page);
1123 free_rx_chan:
1124 dma_release_channel(master->dma_rx);
1125 free_tx_chan:
1126 dma_release_channel(master->dma_tx);
1127 master->dma_tx = NULL;
1128 return -ENODEV;
1129 }
1130
1131 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1132 {
1133 struct spi_master *master = p->master;
1134 struct device *dev;
1135
1136 if (!master->dma_tx)
1137 return;
1138
1139 dev = &p->pdev->dev;
1140 dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr,
1141 PAGE_SIZE, DMA_FROM_DEVICE);
1142 dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr,
1143 PAGE_SIZE, DMA_TO_DEVICE);
1144 free_page((unsigned long)p->rx_dma_page);
1145 free_page((unsigned long)p->tx_dma_page);
1146 dma_release_channel(master->dma_rx);
1147 dma_release_channel(master->dma_tx);
1148 }
1149
1150 static int sh_msiof_spi_probe(struct platform_device *pdev)
1151 {
1152 struct resource *r;
1153 struct spi_master *master;
1154 const struct sh_msiof_chipdata *chipdata;
1155 const struct of_device_id *of_id;
1156 struct sh_msiof_spi_priv *p;
1157 int i;
1158 int ret;
1159
1160 master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv));
1161 if (master == NULL) {
1162 dev_err(&pdev->dev, "failed to allocate spi master\n");
1163 return -ENOMEM;
1164 }
1165
1166 p = spi_master_get_devdata(master);
1167
1168 platform_set_drvdata(pdev, p);
1169 p->master = master;
1170
1171 of_id = of_match_device(sh_msiof_match, &pdev->dev);
1172 if (of_id) {
1173 chipdata = of_id->data;
1174 p->info = sh_msiof_spi_parse_dt(&pdev->dev);
1175 } else {
1176 chipdata = (const void *)pdev->id_entry->driver_data;
1177 p->info = dev_get_platdata(&pdev->dev);
1178 }
1179
1180 if (!p->info) {
1181 dev_err(&pdev->dev, "failed to obtain device info\n");
1182 ret = -ENXIO;
1183 goto err1;
1184 }
1185
1186 init_completion(&p->done);
1187
1188 p->clk = devm_clk_get(&pdev->dev, NULL);
1189 if (IS_ERR(p->clk)) {
1190 dev_err(&pdev->dev, "cannot get clock\n");
1191 ret = PTR_ERR(p->clk);
1192 goto err1;
1193 }
1194
1195 i = platform_get_irq(pdev, 0);
1196 if (i < 0) {
1197 dev_err(&pdev->dev, "cannot get platform IRQ\n");
1198 ret = -ENOENT;
1199 goto err1;
1200 }
1201
1202 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1203 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
1204 if (IS_ERR(p->mapbase)) {
1205 ret = PTR_ERR(p->mapbase);
1206 goto err1;
1207 }
1208
1209 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1210 dev_name(&pdev->dev), p);
1211 if (ret) {
1212 dev_err(&pdev->dev, "unable to request irq\n");
1213 goto err1;
1214 }
1215
1216 p->pdev = pdev;
1217 pm_runtime_enable(&pdev->dev);
1218
1219 /* Platform data may override FIFO sizes */
1220 p->tx_fifo_size = chipdata->tx_fifo_size;
1221 p->rx_fifo_size = chipdata->rx_fifo_size;
1222 if (p->info->tx_fifo_override)
1223 p->tx_fifo_size = p->info->tx_fifo_override;
1224 if (p->info->rx_fifo_override)
1225 p->rx_fifo_size = p->info->rx_fifo_override;
1226
1227 /* init master code */
1228 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1229 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1230 master->flags = chipdata->master_flags;
1231 master->bus_num = pdev->id;
1232 master->dev.of_node = pdev->dev.of_node;
1233 master->num_chipselect = p->info->num_chipselect;
1234 master->setup = sh_msiof_spi_setup;
1235 master->prepare_message = sh_msiof_prepare_message;
1236 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
1237 master->auto_runtime_pm = true;
1238 master->transfer_one = sh_msiof_transfer_one;
1239
1240 ret = sh_msiof_request_dma(p);
1241 if (ret < 0)
1242 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1243
1244 ret = devm_spi_register_master(&pdev->dev, master);
1245 if (ret < 0) {
1246 dev_err(&pdev->dev, "spi_register_master error.\n");
1247 goto err2;
1248 }
1249
1250 return 0;
1251
1252 err2:
1253 sh_msiof_release_dma(p);
1254 pm_runtime_disable(&pdev->dev);
1255 err1:
1256 spi_master_put(master);
1257 return ret;
1258 }
1259
1260 static int sh_msiof_spi_remove(struct platform_device *pdev)
1261 {
1262 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1263
1264 sh_msiof_release_dma(p);
1265 pm_runtime_disable(&pdev->dev);
1266 return 0;
1267 }
1268
1269 static const struct platform_device_id spi_driver_ids[] = {
1270 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
1271 {},
1272 };
1273 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1274
1275 static struct platform_driver sh_msiof_spi_drv = {
1276 .probe = sh_msiof_spi_probe,
1277 .remove = sh_msiof_spi_remove,
1278 .id_table = spi_driver_ids,
1279 .driver = {
1280 .name = "spi_sh_msiof",
1281 .of_match_table = of_match_ptr(sh_msiof_match),
1282 },
1283 };
1284 module_platform_driver(sh_msiof_spi_drv);
1285
1286 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
1287 MODULE_AUTHOR("Magnus Damm");
1288 MODULE_LICENSE("GPL v2");
1289 MODULE_ALIAS("platform:spi_sh_msiof");
Linux kernel - Deliverables
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