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Staging: comedi: ni_mio_common: Fix endian sparse warning
[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_mio_common.c
1 /*
2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18 */
19
20 /*
21 This file is meant to be included by another file, e.g.,
22 ni_atmio.c or ni_pcimio.c.
23
24 Interrupt support originally added by Truxton Fulton
25 <trux@truxton.com>
26
27 References (from ftp://ftp.natinst.com/support/manuals):
28
29 340747b.pdf AT-MIO E series Register Level Programmer Manual
30 341079b.pdf PCI E Series RLPM
31 340934b.pdf DAQ-STC reference manual
32 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
33 release_ni611x.pdf
34 release_ni67xx.pdf
35 Other possibly relevant info:
36
37 320517c.pdf User manual (obsolete)
38 320517f.pdf User manual (new)
39 320889a.pdf delete
40 320906c.pdf maximum signal ratings
41 321066a.pdf about 16x
42 321791a.pdf discontinuation of at-mio-16e-10 rev. c
43 321808a.pdf about at-mio-16e-10 rev P
44 321837a.pdf discontinuation of at-mio-16de-10 rev d
45 321838a.pdf about at-mio-16de-10 rev N
46
47 ISSUES:
48
49 - the interrupt routine needs to be cleaned up
50
51 2006-02-07: S-Series PCI-6143: Support has been added but is not
52 fully tested as yet. Terry Barnaby, BEAM Ltd.
53 */
54
55 #include <linux/interrupt.h>
56 #include <linux/sched.h>
57 #include <linux/delay.h>
58 #include "8255.h"
59 #include "mite.h"
60
61 /* A timeout count */
62 #define NI_TIMEOUT 1000
63
64 /* Note: this table must match the ai_gain_* definitions */
65 static const short ni_gainlkup[][16] = {
66 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
67 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
68 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
69 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
70 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
71 [ai_gain_4] = {0, 1, 4, 7},
72 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
73 0x003, 0x004, 0x005, 0x006},
74 [ai_gain_622x] = {0, 1, 4, 5},
75 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
76 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
77 };
78
79 static const struct comedi_lrange range_ni_E_ai = {
80 16, {
81 BIP_RANGE(10),
82 BIP_RANGE(5),
83 BIP_RANGE(2.5),
84 BIP_RANGE(1),
85 BIP_RANGE(0.5),
86 BIP_RANGE(0.25),
87 BIP_RANGE(0.1),
88 BIP_RANGE(0.05),
89 UNI_RANGE(20),
90 UNI_RANGE(10),
91 UNI_RANGE(5),
92 UNI_RANGE(2),
93 UNI_RANGE(1),
94 UNI_RANGE(0.5),
95 UNI_RANGE(0.2),
96 UNI_RANGE(0.1)
97 }
98 };
99
100 static const struct comedi_lrange range_ni_E_ai_limited = {
101 8, {
102 BIP_RANGE(10),
103 BIP_RANGE(5),
104 BIP_RANGE(1),
105 BIP_RANGE(0.1),
106 UNI_RANGE(10),
107 UNI_RANGE(5),
108 UNI_RANGE(1),
109 UNI_RANGE(0.1)
110 }
111 };
112
113 static const struct comedi_lrange range_ni_E_ai_limited14 = {
114 14, {
115 BIP_RANGE(10),
116 BIP_RANGE(5),
117 BIP_RANGE(2),
118 BIP_RANGE(1),
119 BIP_RANGE(0.5),
120 BIP_RANGE(0.2),
121 BIP_RANGE(0.1),
122 UNI_RANGE(10),
123 UNI_RANGE(5),
124 UNI_RANGE(2),
125 UNI_RANGE(1),
126 UNI_RANGE(0.5),
127 UNI_RANGE(0.2),
128 UNI_RANGE(0.1)
129 }
130 };
131
132 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
133 4, {
134 BIP_RANGE(10),
135 BIP_RANGE(5),
136 BIP_RANGE(0.5),
137 BIP_RANGE(0.05)
138 }
139 };
140
141 static const struct comedi_lrange range_ni_E_ai_611x = {
142 8, {
143 BIP_RANGE(50),
144 BIP_RANGE(20),
145 BIP_RANGE(10),
146 BIP_RANGE(5),
147 BIP_RANGE(2),
148 BIP_RANGE(1),
149 BIP_RANGE(0.5),
150 BIP_RANGE(0.2)
151 }
152 };
153
154 static const struct comedi_lrange range_ni_M_ai_622x = {
155 4, {
156 BIP_RANGE(10),
157 BIP_RANGE(5),
158 BIP_RANGE(1),
159 BIP_RANGE(0.2)
160 }
161 };
162
163 static const struct comedi_lrange range_ni_M_ai_628x = {
164 7, {
165 BIP_RANGE(10),
166 BIP_RANGE(5),
167 BIP_RANGE(2),
168 BIP_RANGE(1),
169 BIP_RANGE(0.5),
170 BIP_RANGE(0.2),
171 BIP_RANGE(0.1)
172 }
173 };
174
175 static const struct comedi_lrange range_ni_E_ao_ext = {
176 4, {
177 BIP_RANGE(10),
178 UNI_RANGE(10),
179 RANGE_ext(-1, 1),
180 RANGE_ext(0, 1)
181 }
182 };
183
184 static const struct comedi_lrange *const ni_range_lkup[] = {
185 [ai_gain_16] = &range_ni_E_ai,
186 [ai_gain_8] = &range_ni_E_ai_limited,
187 [ai_gain_14] = &range_ni_E_ai_limited14,
188 [ai_gain_4] = &range_ni_E_ai_bipolar4,
189 [ai_gain_611x] = &range_ni_E_ai_611x,
190 [ai_gain_622x] = &range_ni_M_ai_622x,
191 [ai_gain_628x] = &range_ni_M_ai_628x,
192 [ai_gain_6143] = &range_bipolar5
193 };
194
195 enum aimodes {
196 AIMODE_NONE = 0,
197 AIMODE_HALF_FULL = 1,
198 AIMODE_SCAN = 2,
199 AIMODE_SAMPLE = 3,
200 };
201
202 enum ni_common_subdevices {
203 NI_AI_SUBDEV,
204 NI_AO_SUBDEV,
205 NI_DIO_SUBDEV,
206 NI_8255_DIO_SUBDEV,
207 NI_UNUSED_SUBDEV,
208 NI_CALIBRATION_SUBDEV,
209 NI_EEPROM_SUBDEV,
210 NI_PFI_DIO_SUBDEV,
211 NI_CS5529_CALIBRATION_SUBDEV,
212 NI_SERIAL_SUBDEV,
213 NI_RTSI_SUBDEV,
214 NI_GPCT0_SUBDEV,
215 NI_GPCT1_SUBDEV,
216 NI_FREQ_OUT_SUBDEV,
217 NI_NUM_SUBDEVICES
218 };
219 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
220 {
221 switch (counter_index) {
222 case 0:
223 return NI_GPCT0_SUBDEV;
224 case 1:
225 return NI_GPCT1_SUBDEV;
226 default:
227 break;
228 }
229 BUG();
230 return NI_GPCT0_SUBDEV;
231 }
232
233 enum timebase_nanoseconds {
234 TIMEBASE_1_NS = 50,
235 TIMEBASE_2_NS = 10000
236 };
237
238 #define SERIAL_DISABLED 0
239 #define SERIAL_600NS 600
240 #define SERIAL_1_2US 1200
241 #define SERIAL_10US 10000
242
243 static const int num_adc_stages_611x = 3;
244
245 static void ni_writel(struct comedi_device *dev, uint32_t data, int reg)
246 {
247 if (dev->mmio)
248 writel(data, dev->mmio + reg);
249
250 outl(data, dev->iobase + reg);
251 }
252
253 static void ni_writew(struct comedi_device *dev, uint16_t data, int reg)
254 {
255 if (dev->mmio)
256 writew(data, dev->mmio + reg);
257
258 outw(data, dev->iobase + reg);
259 }
260
261 static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg)
262 {
263 if (dev->mmio)
264 writeb(data, dev->mmio + reg);
265
266 outb(data, dev->iobase + reg);
267 }
268
269 static uint32_t ni_readl(struct comedi_device *dev, int reg)
270 {
271 if (dev->mmio)
272 return readl(dev->mmio + reg);
273
274 return inl(dev->iobase + reg);
275 }
276
277 static uint16_t ni_readw(struct comedi_device *dev, int reg)
278 {
279 if (dev->mmio)
280 return readw(dev->mmio + reg);
281
282 return inw(dev->iobase + reg);
283 }
284
285 static uint8_t ni_readb(struct comedi_device *dev, int reg)
286 {
287 if (dev->mmio)
288 return readb(dev->mmio + reg);
289
290 return inb(dev->iobase + reg);
291 }
292
293 /*
294 * We automatically take advantage of STC registers that can be
295 * read/written directly in the I/O space of the board.
296 *
297 * The AT-MIO and DAQCard devices map the low 8 STC registers to
298 * iobase+reg*2.
299 *
300 * Most PCIMIO devices also map the low 8 STC registers but the
301 * 611x devices map the read registers to iobase+(addr-1)*2.
302 * For now non-windowed STC access is disabled if a PCIMIO device
303 * is detected (devpriv->mite has been initialized).
304 *
305 * The M series devices do not used windowed registers for the
306 * STC registers. The functions below handle the mapping of the
307 * windowed STC registers to the m series register offsets.
308 */
309
310 struct mio_regmap {
311 unsigned int mio_reg;
312 int size;
313 };
314
315 static const struct mio_regmap m_series_stc_write_regmap[] = {
316 [NISTC_INTA_ACK_REG] = { 0x104, 2 },
317 [NISTC_INTB_ACK_REG] = { 0x106, 2 },
318 [NISTC_AI_CMD2_REG] = { 0x108, 2 },
319 [NISTC_AO_CMD2_REG] = { 0x10a, 2 },
320 [NISTC_G0_CMD_REG] = { 0x10c, 2 },
321 [NISTC_G1_CMD_REG] = { 0x10e, 2 },
322 [NISTC_AI_CMD1_REG] = { 0x110, 2 },
323 [NISTC_AO_CMD1_REG] = { 0x112, 2 },
324 /*
325 * NISTC_DIO_OUT_REG maps to:
326 * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
327 */
328 [NISTC_DIO_OUT_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
329 [NISTC_DIO_CTRL_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
330 [NISTC_AI_MODE1_REG] = { 0x118, 2 },
331 [NISTC_AI_MODE2_REG] = { 0x11a, 2 },
332 [NISTC_AI_SI_LOADA_REG] = { 0x11c, 4 },
333 [NISTC_AI_SI_LOADB_REG] = { 0x120, 4 },
334 [NISTC_AI_SC_LOADA_REG] = { 0x124, 4 },
335 [NISTC_AI_SC_LOADB_REG] = { 0x128, 4 },
336 [NISTC_AI_SI2_LOADA_REG] = { 0x12c, 4 },
337 [NISTC_AI_SI2_LOADB_REG] = { 0x130, 4 },
338 [NISTC_G0_MODE_REG] = { 0x134, 2 },
339 [NISTC_G1_MODE_REG] = { 0x136, 2 },
340 [NISTC_G0_LOADA_REG] = { 0x138, 4 },
341 [NISTC_G0_LOADB_REG] = { 0x13c, 4 },
342 [NISTC_G1_LOADA_REG] = { 0x140, 4 },
343 [NISTC_G1_LOADB_REG] = { 0x144, 4 },
344 [NISTC_G0_INPUT_SEL_REG] = { 0x148, 2 },
345 [NISTC_G1_INPUT_SEL_REG] = { 0x14a, 2 },
346 [NISTC_AO_MODE1_REG] = { 0x14c, 2 },
347 [NISTC_AO_MODE2_REG] = { 0x14e, 2 },
348 [NISTC_AO_UI_LOADA_REG] = { 0x150, 4 },
349 [NISTC_AO_UI_LOADB_REG] = { 0x154, 4 },
350 [NISTC_AO_BC_LOADA_REG] = { 0x158, 4 },
351 [NISTC_AO_BC_LOADB_REG] = { 0x15c, 4 },
352 [NISTC_AO_UC_LOADA_REG] = { 0x160, 4 },
353 [NISTC_AO_UC_LOADB_REG] = { 0x164, 4 },
354 [NISTC_CLK_FOUT_REG] = { 0x170, 2 },
355 [NISTC_IO_BIDIR_PIN_REG] = { 0x172, 2 },
356 [NISTC_RTSI_TRIG_DIR_REG] = { 0x174, 2 },
357 [NISTC_INT_CTRL_REG] = { 0x176, 2 },
358 [NISTC_AI_OUT_CTRL_REG] = { 0x178, 2 },
359 [NISTC_ATRIG_ETC_REG] = { 0x17a, 2 },
360 [NISTC_AI_START_STOP_REG] = { 0x17c, 2 },
361 [NISTC_AI_TRIG_SEL_REG] = { 0x17e, 2 },
362 [NISTC_AI_DIV_LOADA_REG] = { 0x180, 4 },
363 [NISTC_AO_START_SEL_REG] = { 0x184, 2 },
364 [NISTC_AO_TRIG_SEL_REG] = { 0x186, 2 },
365 [NISTC_G0_AUTOINC_REG] = { 0x188, 2 },
366 [NISTC_G1_AUTOINC_REG] = { 0x18a, 2 },
367 [NISTC_AO_MODE3_REG] = { 0x18c, 2 },
368 [NISTC_RESET_REG] = { 0x190, 2 },
369 [NISTC_INTA_ENA_REG] = { 0x192, 2 },
370 [NISTC_INTA2_ENA_REG] = { 0, 0 }, /* E-Series only */
371 [NISTC_INTB_ENA_REG] = { 0x196, 2 },
372 [NISTC_INTB2_ENA_REG] = { 0, 0 }, /* E-Series only */
373 [NISTC_AI_PERSONAL_REG] = { 0x19a, 2 },
374 [NISTC_AO_PERSONAL_REG] = { 0x19c, 2 },
375 [NISTC_RTSI_TRIGA_OUT_REG] = { 0x19e, 2 },
376 [NISTC_RTSI_TRIGB_OUT_REG] = { 0x1a0, 2 },
377 [NISTC_RTSI_BOARD_REG] = { 0, 0 }, /* Unknown */
378 [NISTC_CFG_MEM_CLR_REG] = { 0x1a4, 2 },
379 [NISTC_ADC_FIFO_CLR_REG] = { 0x1a6, 2 },
380 [NISTC_DAC_FIFO_CLR_REG] = { 0x1a8, 2 },
381 [NISTC_AO_OUT_CTRL_REG] = { 0x1ac, 2 },
382 [NISTC_AI_MODE3_REG] = { 0x1ae, 2 },
383 };
384
385 static void m_series_stc_write(struct comedi_device *dev,
386 unsigned int data, unsigned int reg)
387 {
388 const struct mio_regmap *regmap;
389
390 if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
391 regmap = &m_series_stc_write_regmap[reg];
392 } else {
393 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
394 __func__, reg);
395 return;
396 }
397
398 switch (regmap->size) {
399 case 4:
400 ni_writel(dev, data, regmap->mio_reg);
401 break;
402 case 2:
403 ni_writew(dev, data, regmap->mio_reg);
404 break;
405 default:
406 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
407 __func__, reg);
408 break;
409 }
410 }
411
412 static const struct mio_regmap m_series_stc_read_regmap[] = {
413 [NISTC_AI_STATUS1_REG] = { 0x104, 2 },
414 [NISTC_AO_STATUS1_REG] = { 0x106, 2 },
415 [NISTC_G01_STATUS_REG] = { 0x108, 2 },
416 [NISTC_AI_STATUS2_REG] = { 0, 0 }, /* Unknown */
417 [NISTC_AO_STATUS2_REG] = { 0x10c, 2 },
418 [NISTC_DIO_IN_REG] = { 0, 0 }, /* Unknown */
419 [NISTC_G0_HW_SAVE_REG] = { 0x110, 4 },
420 [NISTC_G1_HW_SAVE_REG] = { 0x114, 4 },
421 [NISTC_G0_SAVE_REG] = { 0x118, 4 },
422 [NISTC_G1_SAVE_REG] = { 0x11c, 4 },
423 [NISTC_AO_UI_SAVE_REG] = { 0x120, 4 },
424 [NISTC_AO_BC_SAVE_REG] = { 0x124, 4 },
425 [NISTC_AO_UC_SAVE_REG] = { 0x128, 4 },
426 [NISTC_STATUS1_REG] = { 0x136, 2 },
427 [NISTC_DIO_SERIAL_IN_REG] = { 0x009, 1 },
428 [NISTC_STATUS2_REG] = { 0x13a, 2 },
429 [NISTC_AI_SI_SAVE_REG] = { 0x180, 4 },
430 [NISTC_AI_SC_SAVE_REG] = { 0x184, 4 },
431 };
432
433 static unsigned int m_series_stc_read(struct comedi_device *dev,
434 unsigned int reg)
435 {
436 const struct mio_regmap *regmap;
437
438 if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
439 regmap = &m_series_stc_read_regmap[reg];
440 } else {
441 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
442 __func__, reg);
443 return 0;
444 }
445
446 switch (regmap->size) {
447 case 4:
448 return ni_readl(dev, regmap->mio_reg);
449 case 2:
450 return ni_readw(dev, regmap->mio_reg);
451 case 1:
452 return ni_readb(dev, regmap->mio_reg);
453 default:
454 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
455 __func__, reg);
456 return 0;
457 }
458 }
459
460 static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg)
461 {
462 struct ni_private *devpriv = dev->private;
463 unsigned long flags;
464
465 if (devpriv->is_m_series) {
466 m_series_stc_write(dev, data, reg);
467 } else {
468 spin_lock_irqsave(&devpriv->window_lock, flags);
469 if (!devpriv->mite && reg < 8) {
470 ni_writew(dev, data, reg * 2);
471 } else {
472 ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
473 ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
474 }
475 spin_unlock_irqrestore(&devpriv->window_lock, flags);
476 }
477 }
478
479 static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg)
480 {
481 struct ni_private *devpriv = dev->private;
482
483 if (devpriv->is_m_series) {
484 m_series_stc_write(dev, data, reg);
485 } else {
486 ni_stc_writew(dev, data >> 16, reg);
487 ni_stc_writew(dev, data & 0xffff, reg + 1);
488 }
489 }
490
491 static uint16_t ni_stc_readw(struct comedi_device *dev, int reg)
492 {
493 struct ni_private *devpriv = dev->private;
494 unsigned long flags;
495 uint16_t val;
496
497 if (devpriv->is_m_series) {
498 val = m_series_stc_read(dev, reg);
499 } else {
500 spin_lock_irqsave(&devpriv->window_lock, flags);
501 if (!devpriv->mite && reg < 8) {
502 val = ni_readw(dev, reg * 2);
503 } else {
504 ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
505 val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
506 }
507 spin_unlock_irqrestore(&devpriv->window_lock, flags);
508 }
509 return val;
510 }
511
512 static uint32_t ni_stc_readl(struct comedi_device *dev, int reg)
513 {
514 struct ni_private *devpriv = dev->private;
515 uint32_t val;
516
517 if (devpriv->is_m_series) {
518 val = m_series_stc_read(dev, reg);
519 } else {
520 val = ni_stc_readw(dev, reg) << 16;
521 val |= ni_stc_readw(dev, reg + 1);
522 }
523 return val;
524 }
525
526 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
527 unsigned bit_mask, unsigned bit_values)
528 {
529 struct ni_private *devpriv = dev->private;
530 unsigned long flags;
531
532 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
533 switch (reg) {
534 case NISTC_INTA_ENA_REG:
535 devpriv->int_a_enable_reg &= ~bit_mask;
536 devpriv->int_a_enable_reg |= bit_values & bit_mask;
537 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
538 break;
539 case NISTC_INTB_ENA_REG:
540 devpriv->int_b_enable_reg &= ~bit_mask;
541 devpriv->int_b_enable_reg |= bit_values & bit_mask;
542 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
543 break;
544 case NISTC_IO_BIDIR_PIN_REG:
545 devpriv->io_bidirection_pin_reg &= ~bit_mask;
546 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
547 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
548 break;
549 case NI_E_DMA_AI_AO_SEL_REG:
550 devpriv->ai_ao_select_reg &= ~bit_mask;
551 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
552 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
553 break;
554 case NI_E_DMA_G0_G1_SEL_REG:
555 devpriv->g0_g1_select_reg &= ~bit_mask;
556 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
557 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
558 break;
559 default:
560 dev_err(dev->class_dev, "called with invalid register %d\n",
561 reg);
562 break;
563 }
564 mmiowb();
565 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
566 }
567
568 #ifdef PCIDMA
569 /* DMA channel setup */
570 static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel)
571 {
572 if (channel < 4)
573 return 1 << channel;
574 if (channel == 4)
575 return 0x3;
576 if (channel == 5)
577 return 0x5;
578 BUG();
579 return 0;
580 }
581
582 /* negative channel means no channel */
583 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
584 {
585 unsigned bits = 0;
586
587 if (channel >= 0)
588 bits = ni_stc_dma_channel_select_bitfield(channel);
589
590 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
591 NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits));
592 }
593
594 /* negative channel means no channel */
595 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
596 {
597 unsigned bits = 0;
598
599 if (channel >= 0)
600 bits = ni_stc_dma_channel_select_bitfield(channel);
601
602 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
603 NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits));
604 }
605
606 /* negative channel means no channel */
607 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
608 unsigned gpct_index,
609 int channel)
610 {
611 unsigned bits = 0;
612
613 if (channel >= 0)
614 bits = ni_stc_dma_channel_select_bitfield(channel);
615
616 ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
617 NI_E_DMA_G0_G1_SEL_MASK(gpct_index),
618 NI_E_DMA_G0_G1_SEL(gpct_index, bits));
619 }
620
621 /* negative mite_channel means no channel */
622 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
623 int mite_channel)
624 {
625 struct ni_private *devpriv = dev->private;
626 unsigned long flags;
627 unsigned bits;
628
629 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
630 devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK;
631 if (mite_channel >= 0) {
632 /*
633 * XXX just guessing ni_stc_dma_channel_select_bitfield()
634 * returns the right bits, under the assumption the cdio dma
635 * selection works just like ai/ao/gpct.
636 * Definitely works for dma channels 0 and 1.
637 */
638 bits = ni_stc_dma_channel_select_bitfield(mite_channel);
639 devpriv->cdio_dma_select_reg |= NI_M_CDIO_DMA_SEL_CDO(bits);
640 }
641 ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG);
642 mmiowb();
643 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
644 }
645
646 static int ni_request_ai_mite_channel(struct comedi_device *dev)
647 {
648 struct ni_private *devpriv = dev->private;
649 unsigned long flags;
650
651 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
652 BUG_ON(devpriv->ai_mite_chan);
653 devpriv->ai_mite_chan =
654 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
655 if (!devpriv->ai_mite_chan) {
656 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
657 dev_err(dev->class_dev,
658 "failed to reserve mite dma channel for analog input\n");
659 return -EBUSY;
660 }
661 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
662 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
663 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
664 return 0;
665 }
666
667 static int ni_request_ao_mite_channel(struct comedi_device *dev)
668 {
669 struct ni_private *devpriv = dev->private;
670 unsigned long flags;
671
672 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
673 BUG_ON(devpriv->ao_mite_chan);
674 devpriv->ao_mite_chan =
675 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
676 if (!devpriv->ao_mite_chan) {
677 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
678 dev_err(dev->class_dev,
679 "failed to reserve mite dma channel for analog outut\n");
680 return -EBUSY;
681 }
682 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
683 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
684 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
685 return 0;
686 }
687
688 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
689 unsigned gpct_index,
690 enum comedi_io_direction direction)
691 {
692 struct ni_private *devpriv = dev->private;
693 unsigned long flags;
694 struct mite_channel *mite_chan;
695
696 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
697 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
698 mite_chan =
699 mite_request_channel(devpriv->mite,
700 devpriv->gpct_mite_ring[gpct_index]);
701 if (!mite_chan) {
702 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
703 dev_err(dev->class_dev,
704 "failed to reserve mite dma channel for counter\n");
705 return -EBUSY;
706 }
707 mite_chan->dir = direction;
708 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
709 mite_chan);
710 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
711 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
712 return 0;
713 }
714
715 #endif /* PCIDMA */
716
717 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
718 {
719 #ifdef PCIDMA
720 struct ni_private *devpriv = dev->private;
721 unsigned long flags;
722
723 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
724 BUG_ON(devpriv->cdo_mite_chan);
725 devpriv->cdo_mite_chan =
726 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
727 if (!devpriv->cdo_mite_chan) {
728 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
729 dev_err(dev->class_dev,
730 "failed to reserve mite dma channel for correlated digital output\n");
731 return -EBUSY;
732 }
733 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
734 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
735 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
736 #endif /* PCIDMA */
737 return 0;
738 }
739
740 static void ni_release_ai_mite_channel(struct comedi_device *dev)
741 {
742 #ifdef PCIDMA
743 struct ni_private *devpriv = dev->private;
744 unsigned long flags;
745
746 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
747 if (devpriv->ai_mite_chan) {
748 ni_set_ai_dma_channel(dev, -1);
749 mite_release_channel(devpriv->ai_mite_chan);
750 devpriv->ai_mite_chan = NULL;
751 }
752 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
753 #endif /* PCIDMA */
754 }
755
756 static void ni_release_ao_mite_channel(struct comedi_device *dev)
757 {
758 #ifdef PCIDMA
759 struct ni_private *devpriv = dev->private;
760 unsigned long flags;
761
762 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
763 if (devpriv->ao_mite_chan) {
764 ni_set_ao_dma_channel(dev, -1);
765 mite_release_channel(devpriv->ao_mite_chan);
766 devpriv->ao_mite_chan = NULL;
767 }
768 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
769 #endif /* PCIDMA */
770 }
771
772 #ifdef PCIDMA
773 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
774 unsigned gpct_index)
775 {
776 struct ni_private *devpriv = dev->private;
777 unsigned long flags;
778
779 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
780 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
781 struct mite_channel *mite_chan =
782 devpriv->counter_dev->counters[gpct_index].mite_chan;
783
784 ni_set_gpct_dma_channel(dev, gpct_index, -1);
785 ni_tio_set_mite_channel(&devpriv->
786 counter_dev->counters[gpct_index],
787 NULL);
788 mite_release_channel(mite_chan);
789 }
790 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
791 }
792 #endif /* PCIDMA */
793
794 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
795 {
796 #ifdef PCIDMA
797 struct ni_private *devpriv = dev->private;
798 unsigned long flags;
799
800 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
801 if (devpriv->cdo_mite_chan) {
802 ni_set_cdo_dma_channel(dev, -1);
803 mite_release_channel(devpriv->cdo_mite_chan);
804 devpriv->cdo_mite_chan = NULL;
805 }
806 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
807 #endif /* PCIDMA */
808 }
809
810 #ifdef PCIDMA
811 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
812 unsigned gpct_index, short enable)
813 {
814 struct ni_private *devpriv = dev->private;
815 uint16_t val = 0;
816 int reg;
817
818 if (devpriv->is_m_series || gpct_index > 1)
819 return;
820
821 /*
822 * e-series boards use the second irq signals to generate
823 * dma requests for their counters
824 */
825 if (gpct_index == 0) {
826 reg = NISTC_INTA2_ENA_REG;
827 if (enable)
828 val = NISTC_INTA_ENA_G0_GATE;
829 } else {
830 reg = NISTC_INTB2_ENA_REG;
831 if (enable)
832 val = NISTC_INTB_ENA_G1_GATE;
833 }
834 ni_stc_writew(dev, val, reg);
835 }
836 #endif /* PCIDMA */
837
838 static void ni_clear_ai_fifo(struct comedi_device *dev)
839 {
840 struct ni_private *devpriv = dev->private;
841 static const int timeout = 10000;
842 int i;
843
844 if (devpriv->is_6143) {
845 /* Flush the 6143 data FIFO */
846 ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG);
847 ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG);
848 /* Wait for complete */
849 for (i = 0; i < timeout; i++) {
850 if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10))
851 break;
852 udelay(1);
853 }
854 if (i == timeout)
855 dev_err(dev->class_dev, "FIFO flush timeout\n");
856 } else {
857 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
858 if (devpriv->is_625x) {
859 ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
860 ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
861 #if 0
862 /* the NI example code does 3 convert pulses for 625x boards,
863 but that appears to be wrong in practice. */
864 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
865 NISTC_AI_CMD1_REG);
866 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
867 NISTC_AI_CMD1_REG);
868 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
869 NISTC_AI_CMD1_REG);
870 #endif
871 }
872 }
873 }
874
875 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
876 int addr)
877 {
878 struct ni_private *devpriv = dev->private;
879 unsigned long flags;
880
881 spin_lock_irqsave(&devpriv->window_lock, flags);
882 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
883 ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG);
884 spin_unlock_irqrestore(&devpriv->window_lock, flags);
885 }
886
887 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
888 int addr)
889 {
890 struct ni_private *devpriv = dev->private;
891 unsigned long flags;
892
893 spin_lock_irqsave(&devpriv->window_lock, flags);
894 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
895 ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG);
896 spin_unlock_irqrestore(&devpriv->window_lock, flags);
897 }
898
899 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
900 {
901 struct ni_private *devpriv = dev->private;
902 unsigned long flags;
903 unsigned short data;
904
905 spin_lock_irqsave(&devpriv->window_lock, flags);
906 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
907 data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG);
908 spin_unlock_irqrestore(&devpriv->window_lock, flags);
909 return data;
910 }
911
912 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
913 * share registers (such as Interrupt_A_Register) without interfering with
914 * each other.
915 *
916 * NOTE: the switch/case statements are optimized out for a constant argument
917 * so this is actually quite fast--- If you must wrap another function around this
918 * make it inline to avoid a large speed penalty.
919 *
920 * value should only be 1 or 0.
921 */
922 static inline void ni_set_bits(struct comedi_device *dev, int reg,
923 unsigned bits, unsigned value)
924 {
925 unsigned bit_values;
926
927 if (value)
928 bit_values = bits;
929 else
930 bit_values = 0;
931 ni_set_bitfield(dev, reg, bits, bit_values);
932 }
933
934 #ifdef PCIDMA
935 static void ni_sync_ai_dma(struct comedi_device *dev)
936 {
937 struct ni_private *devpriv = dev->private;
938 struct comedi_subdevice *s = dev->read_subdev;
939 unsigned long flags;
940
941 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
942 if (devpriv->ai_mite_chan)
943 mite_sync_input_dma(devpriv->ai_mite_chan, s);
944 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
945 }
946
947 static int ni_ai_drain_dma(struct comedi_device *dev)
948 {
949 struct ni_private *devpriv = dev->private;
950 int i;
951 static const int timeout = 10000;
952 unsigned long flags;
953 int retval = 0;
954
955 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
956 if (devpriv->ai_mite_chan) {
957 for (i = 0; i < timeout; i++) {
958 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
959 NISTC_AI_STATUS1_FIFO_E)
960 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
961 0)
962 break;
963 udelay(5);
964 }
965 if (i == timeout) {
966 dev_err(dev->class_dev, "timed out\n");
967 dev_err(dev->class_dev,
968 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
969 mite_bytes_in_transit(devpriv->ai_mite_chan),
970 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
971 retval = -1;
972 }
973 }
974 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
975
976 ni_sync_ai_dma(dev);
977
978 return retval;
979 }
980
981 static void mite_handle_b_linkc(struct mite_struct *mite,
982 struct comedi_device *dev)
983 {
984 struct ni_private *devpriv = dev->private;
985 struct comedi_subdevice *s = dev->write_subdev;
986 unsigned long flags;
987
988 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
989 if (devpriv->ao_mite_chan)
990 mite_sync_output_dma(devpriv->ao_mite_chan, s);
991 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
992 }
993
994 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
995 {
996 static const int timeout = 10000;
997 int i;
998
999 for (i = 0; i < timeout; i++) {
1000 unsigned short b_status;
1001
1002 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
1003 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
1004 break;
1005 /* if we poll too often, the pci bus activity seems
1006 to slow the dma transfer down */
1007 udelay(10);
1008 }
1009 if (i == timeout) {
1010 dev_err(dev->class_dev, "timed out waiting for dma load\n");
1011 return -EPIPE;
1012 }
1013 return 0;
1014 }
1015 #endif /* PCIDMA */
1016
1017 #ifndef PCIDMA
1018
1019 static void ni_ao_fifo_load(struct comedi_device *dev,
1020 struct comedi_subdevice *s, int n)
1021 {
1022 struct ni_private *devpriv = dev->private;
1023 int i;
1024 unsigned short d;
1025 u32 packed_data;
1026
1027 for (i = 0; i < n; i++) {
1028 comedi_buf_read_samples(s, &d, 1);
1029
1030 if (devpriv->is_6xxx) {
1031 packed_data = d & 0xffff;
1032 /* 6711 only has 16 bit wide ao fifo */
1033 if (!devpriv->is_6711) {
1034 comedi_buf_read_samples(s, &d, 1);
1035 i++;
1036 packed_data |= (d << 16) & 0xffff0000;
1037 }
1038 ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG);
1039 } else {
1040 ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG);
1041 }
1042 }
1043 }
1044
1045 /*
1046 * There's a small problem if the FIFO gets really low and we
1047 * don't have the data to fill it. Basically, if after we fill
1048 * the FIFO with all the data available, the FIFO is _still_
1049 * less than half full, we never clear the interrupt. If the
1050 * IRQ is in edge mode, we never get another interrupt, because
1051 * this one wasn't cleared. If in level mode, we get flooded
1052 * with interrupts that we can't fulfill, because nothing ever
1053 * gets put into the buffer.
1054 *
1055 * This kind of situation is recoverable, but it is easier to
1056 * just pretend we had a FIFO underrun, since there is a good
1057 * chance it will happen anyway. This is _not_ the case for
1058 * RT code, as RT code might purposely be running close to the
1059 * metal. Needs to be fixed eventually.
1060 */
1061 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1062 struct comedi_subdevice *s)
1063 {
1064 const struct ni_board_struct *board = dev->board_ptr;
1065 unsigned int nbytes;
1066 unsigned int nsamples;
1067
1068 nbytes = comedi_buf_read_n_available(s);
1069 if (nbytes == 0) {
1070 s->async->events |= COMEDI_CB_OVERFLOW;
1071 return 0;
1072 }
1073
1074 nsamples = comedi_bytes_to_samples(s, nbytes);
1075 if (nsamples > board->ao_fifo_depth / 2)
1076 nsamples = board->ao_fifo_depth / 2;
1077
1078 ni_ao_fifo_load(dev, s, nsamples);
1079
1080 return 1;
1081 }
1082
1083 static int ni_ao_prep_fifo(struct comedi_device *dev,
1084 struct comedi_subdevice *s)
1085 {
1086 const struct ni_board_struct *board = dev->board_ptr;
1087 struct ni_private *devpriv = dev->private;
1088 unsigned int nbytes;
1089 unsigned int nsamples;
1090
1091 /* reset fifo */
1092 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1093 if (devpriv->is_6xxx)
1094 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
1095
1096 /* load some data */
1097 nbytes = comedi_buf_read_n_available(s);
1098 if (nbytes == 0)
1099 return 0;
1100
1101 nsamples = comedi_bytes_to_samples(s, nbytes);
1102 if (nsamples > board->ao_fifo_depth)
1103 nsamples = board->ao_fifo_depth;
1104
1105 ni_ao_fifo_load(dev, s, nsamples);
1106
1107 return nsamples;
1108 }
1109
1110 static void ni_ai_fifo_read(struct comedi_device *dev,
1111 struct comedi_subdevice *s, int n)
1112 {
1113 struct ni_private *devpriv = dev->private;
1114 struct comedi_async *async = s->async;
1115 u32 dl;
1116 unsigned short data;
1117 int i;
1118
1119 if (devpriv->is_611x) {
1120 for (i = 0; i < n / 2; i++) {
1121 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1122 /* This may get the hi/lo data in the wrong order */
1123 data = (dl >> 16) & 0xffff;
1124 comedi_buf_write_samples(s, &data, 1);
1125 data = dl & 0xffff;
1126 comedi_buf_write_samples(s, &data, 1);
1127 }
1128 /* Check if there's a single sample stuck in the FIFO */
1129 if (n % 2) {
1130 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1131 data = dl & 0xffff;
1132 comedi_buf_write_samples(s, &data, 1);
1133 }
1134 } else if (devpriv->is_6143) {
1135 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1136 for (i = 0; i < n / 2; i++) {
1137 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1138
1139 data = (dl >> 16) & 0xffff;
1140 comedi_buf_write_samples(s, &data, 1);
1141 data = dl & 0xffff;
1142 comedi_buf_write_samples(s, &data, 1);
1143 }
1144 if (n % 2) {
1145 /* Assume there is a single sample stuck in the FIFO */
1146 /* Get stranded sample into FIFO */
1147 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1148 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1149 data = (dl >> 16) & 0xffff;
1150 comedi_buf_write_samples(s, &data, 1);
1151 }
1152 } else {
1153 if (n > sizeof(devpriv->ai_fifo_buffer) /
1154 sizeof(devpriv->ai_fifo_buffer[0])) {
1155 dev_err(dev->class_dev,
1156 "bug! ai_fifo_buffer too small\n");
1157 async->events |= COMEDI_CB_ERROR;
1158 return;
1159 }
1160 for (i = 0; i < n; i++) {
1161 devpriv->ai_fifo_buffer[i] =
1162 ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1163 }
1164 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1165 }
1166 }
1167
1168 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1169 {
1170 const struct ni_board_struct *board = dev->board_ptr;
1171 struct comedi_subdevice *s = dev->read_subdev;
1172 int n;
1173
1174 n = board->ai_fifo_depth / 2;
1175
1176 ni_ai_fifo_read(dev, s, n);
1177 }
1178 #endif
1179
1180 /*
1181 Empties the AI fifo
1182 */
1183 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1184 {
1185 struct ni_private *devpriv = dev->private;
1186 struct comedi_subdevice *s = dev->read_subdev;
1187 u32 dl;
1188 unsigned short data;
1189 unsigned short fifo_empty;
1190 int i;
1191
1192 if (devpriv->is_611x) {
1193 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1194 NISTC_AI_STATUS1_FIFO_E) == 0) {
1195 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1196
1197 /* This may get the hi/lo data in the wrong order */
1198 data = dl >> 16;
1199 comedi_buf_write_samples(s, &data, 1);
1200 data = dl & 0xffff;
1201 comedi_buf_write_samples(s, &data, 1);
1202 }
1203 } else if (devpriv->is_6143) {
1204 i = 0;
1205 while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) {
1206 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1207
1208 /* This may get the hi/lo data in the wrong order */
1209 data = dl >> 16;
1210 comedi_buf_write_samples(s, &data, 1);
1211 data = dl & 0xffff;
1212 comedi_buf_write_samples(s, &data, 1);
1213 i += 2;
1214 }
1215 /* Check if stranded sample is present */
1216 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1217 /* Get stranded sample into FIFO */
1218 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1219 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1220 data = (dl >> 16) & 0xffff;
1221 comedi_buf_write_samples(s, &data, 1);
1222 }
1223
1224 } else {
1225 fifo_empty = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1226 NISTC_AI_STATUS1_FIFO_E;
1227 while (fifo_empty == 0) {
1228 for (i = 0;
1229 i <
1230 sizeof(devpriv->ai_fifo_buffer) /
1231 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1232 fifo_empty = ni_stc_readw(dev,
1233 NISTC_AI_STATUS1_REG) &
1234 NISTC_AI_STATUS1_FIFO_E;
1235 if (fifo_empty)
1236 break;
1237 devpriv->ai_fifo_buffer[i] =
1238 ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1239 }
1240 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1241 }
1242 }
1243 }
1244
1245 static void get_last_sample_611x(struct comedi_device *dev)
1246 {
1247 struct ni_private *devpriv = dev->private;
1248 struct comedi_subdevice *s = dev->read_subdev;
1249 unsigned short data;
1250 u32 dl;
1251
1252 if (!devpriv->is_611x)
1253 return;
1254
1255 /* Check if there's a single sample stuck in the FIFO */
1256 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1257 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1258 data = dl & 0xffff;
1259 comedi_buf_write_samples(s, &data, 1);
1260 }
1261 }
1262
1263 static void get_last_sample_6143(struct comedi_device *dev)
1264 {
1265 struct ni_private *devpriv = dev->private;
1266 struct comedi_subdevice *s = dev->read_subdev;
1267 unsigned short data;
1268 u32 dl;
1269
1270 if (!devpriv->is_6143)
1271 return;
1272
1273 /* Check if there's a single sample stuck in the FIFO */
1274 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1275 /* Get stranded sample into FIFO */
1276 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1277 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1278
1279 /* This may get the hi/lo data in the wrong order */
1280 data = (dl >> 16) & 0xffff;
1281 comedi_buf_write_samples(s, &data, 1);
1282 }
1283 }
1284
1285 static void shutdown_ai_command(struct comedi_device *dev)
1286 {
1287 struct comedi_subdevice *s = dev->read_subdev;
1288
1289 #ifdef PCIDMA
1290 ni_ai_drain_dma(dev);
1291 #endif
1292 ni_handle_fifo_dregs(dev);
1293 get_last_sample_611x(dev);
1294 get_last_sample_6143(dev);
1295
1296 s->async->events |= COMEDI_CB_EOA;
1297 }
1298
1299 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1300 {
1301 struct ni_private *devpriv = dev->private;
1302
1303 if (devpriv->aimode == AIMODE_SCAN) {
1304 #ifdef PCIDMA
1305 static const int timeout = 10;
1306 int i;
1307
1308 for (i = 0; i < timeout; i++) {
1309 ni_sync_ai_dma(dev);
1310 if ((s->async->events & COMEDI_CB_EOS))
1311 break;
1312 udelay(1);
1313 }
1314 #else
1315 ni_handle_fifo_dregs(dev);
1316 s->async->events |= COMEDI_CB_EOS;
1317 #endif
1318 }
1319 /* handle special case of single scan */
1320 if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1321 shutdown_ai_command(dev);
1322 }
1323
1324 static void handle_gpct_interrupt(struct comedi_device *dev,
1325 unsigned short counter_index)
1326 {
1327 #ifdef PCIDMA
1328 struct ni_private *devpriv = dev->private;
1329 struct comedi_subdevice *s;
1330
1331 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1332
1333 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1334 s);
1335 comedi_handle_events(dev, s);
1336 #endif
1337 }
1338
1339 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1340 {
1341 unsigned short ack = 0;
1342
1343 if (a_status & NISTC_AI_STATUS1_SC_TC)
1344 ack |= NISTC_INTA_ACK_AI_SC_TC;
1345 if (a_status & NISTC_AI_STATUS1_START1)
1346 ack |= NISTC_INTA_ACK_AI_START1;
1347 if (a_status & NISTC_AI_STATUS1_START)
1348 ack |= NISTC_INTA_ACK_AI_START;
1349 if (a_status & NISTC_AI_STATUS1_STOP)
1350 ack |= NISTC_INTA_ACK_AI_STOP;
1351 if (ack)
1352 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1353 }
1354
1355 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1356 unsigned ai_mite_status)
1357 {
1358 struct comedi_subdevice *s = dev->read_subdev;
1359 struct comedi_cmd *cmd = &s->async->cmd;
1360
1361 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1362 if (s->type == COMEDI_SUBD_UNUSED)
1363 return;
1364
1365 #ifdef PCIDMA
1366 if (ai_mite_status & CHSR_LINKC)
1367 ni_sync_ai_dma(dev);
1368
1369 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1370 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1371 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1372 dev_err(dev->class_dev,
1373 "unknown mite interrupt (ai_mite_status=%08x)\n",
1374 ai_mite_status);
1375 s->async->events |= COMEDI_CB_ERROR;
1376 /* disable_irq(dev->irq); */
1377 }
1378 #endif
1379
1380 /* test for all uncommon interrupt events at the same time */
1381 if (status & (NISTC_AI_STATUS1_ERR |
1382 NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1383 if (status == 0xffff) {
1384 dev_err(dev->class_dev, "Card removed?\n");
1385 /* we probably aren't even running a command now,
1386 * so it's a good idea to be careful. */
1387 if (comedi_is_subdevice_running(s)) {
1388 s->async->events |= COMEDI_CB_ERROR;
1389 comedi_handle_events(dev, s);
1390 }
1391 return;
1392 }
1393 if (status & NISTC_AI_STATUS1_ERR) {
1394 dev_err(dev->class_dev, "ai error a_status=%04x\n",
1395 status);
1396
1397 shutdown_ai_command(dev);
1398
1399 s->async->events |= COMEDI_CB_ERROR;
1400 if (status & NISTC_AI_STATUS1_OVER)
1401 s->async->events |= COMEDI_CB_OVERFLOW;
1402
1403 comedi_handle_events(dev, s);
1404 return;
1405 }
1406 if (status & NISTC_AI_STATUS1_SC_TC) {
1407 if (cmd->stop_src == TRIG_COUNT)
1408 shutdown_ai_command(dev);
1409 }
1410 }
1411 #ifndef PCIDMA
1412 if (status & NISTC_AI_STATUS1_FIFO_HF) {
1413 int i;
1414 static const int timeout = 10;
1415 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1416 *fail to get the fifo less than half full, so loop to be sure.*/
1417 for (i = 0; i < timeout; ++i) {
1418 ni_handle_fifo_half_full(dev);
1419 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1420 NISTC_AI_STATUS1_FIFO_HF) == 0)
1421 break;
1422 }
1423 }
1424 #endif /* !PCIDMA */
1425
1426 if (status & NISTC_AI_STATUS1_STOP)
1427 ni_handle_eos(dev, s);
1428
1429 comedi_handle_events(dev, s);
1430 }
1431
1432 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1433 {
1434 unsigned short ack = 0;
1435
1436 if (b_status & NISTC_AO_STATUS1_BC_TC)
1437 ack |= NISTC_INTB_ACK_AO_BC_TC;
1438 if (b_status & NISTC_AO_STATUS1_OVERRUN)
1439 ack |= NISTC_INTB_ACK_AO_ERR;
1440 if (b_status & NISTC_AO_STATUS1_START)
1441 ack |= NISTC_INTB_ACK_AO_START;
1442 if (b_status & NISTC_AO_STATUS1_START1)
1443 ack |= NISTC_INTB_ACK_AO_START1;
1444 if (b_status & NISTC_AO_STATUS1_UC_TC)
1445 ack |= NISTC_INTB_ACK_AO_UC_TC;
1446 if (b_status & NISTC_AO_STATUS1_UI2_TC)
1447 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1448 if (b_status & NISTC_AO_STATUS1_UPDATE)
1449 ack |= NISTC_INTB_ACK_AO_UPDATE;
1450 if (ack)
1451 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1452 }
1453
1454 static void handle_b_interrupt(struct comedi_device *dev,
1455 unsigned short b_status, unsigned ao_mite_status)
1456 {
1457 struct comedi_subdevice *s = dev->write_subdev;
1458 /* unsigned short ack=0; */
1459
1460 #ifdef PCIDMA
1461 /* Currently, mite.c requires us to handle LINKC */
1462 if (ao_mite_status & CHSR_LINKC) {
1463 struct ni_private *devpriv = dev->private;
1464
1465 mite_handle_b_linkc(devpriv->mite, dev);
1466 }
1467
1468 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1469 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1470 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1471 dev_err(dev->class_dev,
1472 "unknown mite interrupt (ao_mite_status=%08x)\n",
1473 ao_mite_status);
1474 s->async->events |= COMEDI_CB_ERROR;
1475 }
1476 #endif
1477
1478 if (b_status == 0xffff)
1479 return;
1480 if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1481 dev_err(dev->class_dev,
1482 "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1483 b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1484 s->async->events |= COMEDI_CB_OVERFLOW;
1485 }
1486
1487 if (b_status & NISTC_AO_STATUS1_BC_TC)
1488 s->async->events |= COMEDI_CB_EOA;
1489
1490 #ifndef PCIDMA
1491 if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1492 int ret;
1493
1494 ret = ni_ao_fifo_half_empty(dev, s);
1495 if (!ret) {
1496 dev_err(dev->class_dev, "AO buffer underrun\n");
1497 ni_set_bits(dev, NISTC_INTB_ENA_REG,
1498 NISTC_INTB_ENA_AO_FIFO |
1499 NISTC_INTB_ENA_AO_ERR, 0);
1500 s->async->events |= COMEDI_CB_OVERFLOW;
1501 }
1502 }
1503 #endif
1504
1505 comedi_handle_events(dev, s);
1506 }
1507
1508 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1509 void *data, unsigned int num_bytes,
1510 unsigned int chan_index)
1511 {
1512 struct ni_private *devpriv = dev->private;
1513 struct comedi_async *async = s->async;
1514 struct comedi_cmd *cmd = &async->cmd;
1515 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1516 unsigned short *array = data;
1517 unsigned int *larray = data;
1518 unsigned int i;
1519 #ifdef PCIDMA
1520 __le16 *barray = data;
1521 __le32 *blarray = data;
1522 #endif
1523
1524 for (i = 0; i < nsamples; i++) {
1525 #ifdef PCIDMA
1526 if (s->subdev_flags & SDF_LSAMPL)
1527 larray[i] = le32_to_cpu(blarray[i]);
1528 else
1529 array[i] = le16_to_cpu(barray[i]);
1530 #endif
1531 if (s->subdev_flags & SDF_LSAMPL)
1532 larray[i] += devpriv->ai_offset[chan_index];
1533 else
1534 array[i] += devpriv->ai_offset[chan_index];
1535 chan_index++;
1536 chan_index %= cmd->chanlist_len;
1537 }
1538 }
1539
1540 #ifdef PCIDMA
1541
1542 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1543 {
1544 struct ni_private *devpriv = dev->private;
1545 struct comedi_subdevice *s = dev->read_subdev;
1546 int retval;
1547 unsigned long flags;
1548
1549 retval = ni_request_ai_mite_channel(dev);
1550 if (retval)
1551 return retval;
1552
1553 /* write alloc the entire buffer */
1554 comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1555
1556 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1557 if (!devpriv->ai_mite_chan) {
1558 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1559 return -EIO;
1560 }
1561
1562 if (devpriv->is_611x || devpriv->is_6143)
1563 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1564 else if (devpriv->is_628x)
1565 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1566 else
1567 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1568
1569 /*start the MITE */
1570 mite_dma_arm(devpriv->ai_mite_chan);
1571 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1572
1573 return 0;
1574 }
1575
1576 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1577 {
1578 struct ni_private *devpriv = dev->private;
1579 struct comedi_subdevice *s = dev->write_subdev;
1580 int retval;
1581 unsigned long flags;
1582
1583 retval = ni_request_ao_mite_channel(dev);
1584 if (retval)
1585 return retval;
1586
1587 /* read alloc the entire buffer */
1588 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1589
1590 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1591 if (devpriv->ao_mite_chan) {
1592 if (devpriv->is_611x || devpriv->is_6713) {
1593 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1594 } else {
1595 /* doing 32 instead of 16 bit wide transfers from memory
1596 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1597 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1598 }
1599 mite_dma_arm(devpriv->ao_mite_chan);
1600 } else {
1601 retval = -EIO;
1602 }
1603 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1604
1605 return retval;
1606 }
1607
1608 #endif /* PCIDMA */
1609
1610 /*
1611 used for both cancel ioctl and board initialization
1612
1613 this is pretty harsh for a cancel, but it works...
1614 */
1615
1616 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1617 {
1618 struct ni_private *devpriv = dev->private;
1619 unsigned ai_personal;
1620 unsigned ai_out_ctrl;
1621
1622 ni_release_ai_mite_channel(dev);
1623 /* ai configuration */
1624 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1625 NISTC_RESET_REG);
1626
1627 ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1628
1629 ni_clear_ai_fifo(dev);
1630
1631 if (!devpriv->is_6143)
1632 ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
1633
1634 ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1635 ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1636 NISTC_AI_MODE1_RSVD
1637 /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1638 NISTC_AI_MODE1_REG);
1639 ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1640 /* generate FIFO interrupts on non-empty */
1641 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1642 NISTC_AI_MODE3_REG);
1643
1644 ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1645 NISTC_AI_PERSONAL_SOC_POLARITY |
1646 NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1647 ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1648 NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1649 NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1650 NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1651 if (devpriv->is_611x) {
1652 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1653 } else if (devpriv->is_6143) {
1654 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1655 } else {
1656 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1657 if (devpriv->is_622x)
1658 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1659 else
1660 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1661 }
1662 ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1663 ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1664
1665 /* the following registers should not be changed, because there
1666 * are no backup registers in devpriv. If you want to change
1667 * any of these, add a backup register and other appropriate code:
1668 * NISTC_AI_MODE1_REG
1669 * NISTC_AI_MODE3_REG
1670 * NISTC_AI_PERSONAL_REG
1671 * NISTC_AI_OUT_CTRL_REG
1672 */
1673
1674 /* clear interrupts */
1675 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1676
1677 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1678
1679 return 0;
1680 }
1681
1682 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1683 {
1684 unsigned long flags;
1685 int count;
1686
1687 /* lock to avoid race with interrupt handler */
1688 spin_lock_irqsave(&dev->spinlock, flags);
1689 #ifndef PCIDMA
1690 ni_handle_fifo_dregs(dev);
1691 #else
1692 ni_sync_ai_dma(dev);
1693 #endif
1694 count = comedi_buf_n_bytes_ready(s);
1695 spin_unlock_irqrestore(&dev->spinlock, flags);
1696
1697 return count;
1698 }
1699
1700 static void ni_prime_channelgain_list(struct comedi_device *dev)
1701 {
1702 int i;
1703
1704 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1705 for (i = 0; i < NI_TIMEOUT; ++i) {
1706 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1707 NISTC_AI_STATUS1_FIFO_E)) {
1708 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1709 return;
1710 }
1711 udelay(1);
1712 }
1713 dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1714 }
1715
1716 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1717 unsigned int n_chan,
1718 unsigned int *list)
1719 {
1720 const struct ni_board_struct *board = dev->board_ptr;
1721 struct ni_private *devpriv = dev->private;
1722 unsigned int chan, range, aref;
1723 unsigned int i;
1724 unsigned int dither;
1725 unsigned range_code;
1726
1727 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1728
1729 if ((list[0] & CR_ALT_SOURCE)) {
1730 unsigned bypass_bits;
1731
1732 chan = CR_CHAN(list[0]);
1733 range = CR_RANGE(list[0]);
1734 range_code = ni_gainlkup[board->gainlkup][range];
1735 dither = (list[0] & CR_ALT_FILTER) != 0;
1736 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1737 NI_M_CFG_BYPASS_AI_CHAN(chan) |
1738 NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1739 devpriv->ai_calib_source;
1740 if (dither)
1741 bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1742 /* don't use 2's complement encoding */
1743 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1744 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1745 } else {
1746 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1747 }
1748 for (i = 0; i < n_chan; i++) {
1749 unsigned config_bits = 0;
1750
1751 chan = CR_CHAN(list[i]);
1752 aref = CR_AREF(list[i]);
1753 range = CR_RANGE(list[i]);
1754 dither = (list[i] & CR_ALT_FILTER) != 0;
1755
1756 range_code = ni_gainlkup[board->gainlkup][range];
1757 devpriv->ai_offset[i] = 0;
1758 switch (aref) {
1759 case AREF_DIFF:
1760 config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1761 break;
1762 case AREF_COMMON:
1763 config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1764 break;
1765 case AREF_GROUND:
1766 config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1767 break;
1768 case AREF_OTHER:
1769 break;
1770 }
1771 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1772 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1773 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1774 if (i == n_chan - 1)
1775 config_bits |= NI_M_AI_CFG_LAST_CHAN;
1776 if (dither)
1777 config_bits |= NI_M_AI_CFG_DITHER;
1778 /* don't use 2's complement encoding */
1779 config_bits |= NI_M_AI_CFG_POLARITY;
1780 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1781 }
1782 ni_prime_channelgain_list(dev);
1783 }
1784
1785 /*
1786 * Notes on the 6110 and 6111:
1787 * These boards a slightly different than the rest of the series, since
1788 * they have multiple A/D converters.
1789 * From the driver side, the configuration memory is a
1790 * little different.
1791 * Configuration Memory Low:
1792 * bits 15-9: same
1793 * bit 8: unipolar/bipolar (should be 0 for bipolar)
1794 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1795 * 1001 gain=0.1 (+/- 50)
1796 * 1010 0.2
1797 * 1011 0.1
1798 * 0001 1
1799 * 0010 2
1800 * 0011 5
1801 * 0100 10
1802 * 0101 20
1803 * 0110 50
1804 * Configuration Memory High:
1805 * bits 12-14: Channel Type
1806 * 001 for differential
1807 * 000 for calibration
1808 * bit 11: coupling (this is not currently handled)
1809 * 1 AC coupling
1810 * 0 DC coupling
1811 * bits 0-2: channel
1812 * valid channels are 0-3
1813 */
1814 static void ni_load_channelgain_list(struct comedi_device *dev,
1815 struct comedi_subdevice *s,
1816 unsigned int n_chan, unsigned int *list)
1817 {
1818 const struct ni_board_struct *board = dev->board_ptr;
1819 struct ni_private *devpriv = dev->private;
1820 unsigned int offset = (s->maxdata + 1) >> 1;
1821 unsigned int chan, range, aref;
1822 unsigned int i;
1823 unsigned int hi, lo;
1824 unsigned int dither;
1825
1826 if (devpriv->is_m_series) {
1827 ni_m_series_load_channelgain_list(dev, n_chan, list);
1828 return;
1829 }
1830 if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1831 if (devpriv->changain_state
1832 && devpriv->changain_spec == list[0]) {
1833 /* ready to go. */
1834 return;
1835 }
1836 devpriv->changain_state = 1;
1837 devpriv->changain_spec = list[0];
1838 } else {
1839 devpriv->changain_state = 0;
1840 }
1841
1842 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1843
1844 /* Set up Calibration mode if required */
1845 if (devpriv->is_6143) {
1846 if ((list[0] & CR_ALT_SOURCE)
1847 && !devpriv->ai_calib_source_enabled) {
1848 /* Strobe Relay enable bit */
1849 ni_writew(dev, devpriv->ai_calib_source |
1850 NI6143_CALIB_CHAN_RELAY_ON,
1851 NI6143_CALIB_CHAN_REG);
1852 ni_writew(dev, devpriv->ai_calib_source,
1853 NI6143_CALIB_CHAN_REG);
1854 devpriv->ai_calib_source_enabled = 1;
1855 msleep_interruptible(100); /* Allow relays to change */
1856 } else if (!(list[0] & CR_ALT_SOURCE)
1857 && devpriv->ai_calib_source_enabled) {
1858 /* Strobe Relay disable bit */
1859 ni_writew(dev, devpriv->ai_calib_source |
1860 NI6143_CALIB_CHAN_RELAY_OFF,
1861 NI6143_CALIB_CHAN_REG);
1862 ni_writew(dev, devpriv->ai_calib_source,
1863 NI6143_CALIB_CHAN_REG);
1864 devpriv->ai_calib_source_enabled = 0;
1865 msleep_interruptible(100); /* Allow relays to change */
1866 }
1867 }
1868
1869 for (i = 0; i < n_chan; i++) {
1870 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1871 chan = devpriv->ai_calib_source;
1872 else
1873 chan = CR_CHAN(list[i]);
1874 aref = CR_AREF(list[i]);
1875 range = CR_RANGE(list[i]);
1876 dither = (list[i] & CR_ALT_FILTER) != 0;
1877
1878 /* fix the external/internal range differences */
1879 range = ni_gainlkup[board->gainlkup][range];
1880 if (devpriv->is_611x)
1881 devpriv->ai_offset[i] = offset;
1882 else
1883 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1884
1885 hi = 0;
1886 if ((list[i] & CR_ALT_SOURCE)) {
1887 if (devpriv->is_611x)
1888 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1889 NI611X_CALIB_CHAN_SEL_REG);
1890 } else {
1891 if (devpriv->is_611x)
1892 aref = AREF_DIFF;
1893 else if (devpriv->is_6143)
1894 aref = AREF_OTHER;
1895 switch (aref) {
1896 case AREF_DIFF:
1897 hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
1898 break;
1899 case AREF_COMMON:
1900 hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
1901 break;
1902 case AREF_GROUND:
1903 hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
1904 break;
1905 case AREF_OTHER:
1906 break;
1907 }
1908 }
1909 hi |= NI_E_AI_CFG_HI_CHAN(chan);
1910
1911 ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
1912
1913 if (!devpriv->is_6143) {
1914 lo = NI_E_AI_CFG_LO_GAIN(range);
1915
1916 if (i == n_chan - 1)
1917 lo |= NI_E_AI_CFG_LO_LAST_CHAN;
1918 if (dither)
1919 lo |= NI_E_AI_CFG_LO_DITHER;
1920
1921 ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
1922 }
1923 }
1924
1925 /* prime the channel/gain list */
1926 if (!devpriv->is_611x && !devpriv->is_6143)
1927 ni_prime_channelgain_list(dev);
1928 }
1929
1930 static int ni_ai_insn_read(struct comedi_device *dev,
1931 struct comedi_subdevice *s,
1932 struct comedi_insn *insn,
1933 unsigned int *data)
1934 {
1935 struct ni_private *devpriv = dev->private;
1936 unsigned int mask = (s->maxdata + 1) >> 1;
1937 int i, n;
1938 unsigned signbits;
1939 unsigned int d;
1940 unsigned long dl;
1941
1942 ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1943
1944 ni_clear_ai_fifo(dev);
1945
1946 signbits = devpriv->ai_offset[0];
1947 if (devpriv->is_611x) {
1948 for (n = 0; n < num_adc_stages_611x; n++) {
1949 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1950 NISTC_AI_CMD1_REG);
1951 udelay(1);
1952 }
1953 for (n = 0; n < insn->n; n++) {
1954 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1955 NISTC_AI_CMD1_REG);
1956 /* The 611x has screwy 32-bit FIFOs. */
1957 d = 0;
1958 for (i = 0; i < NI_TIMEOUT; i++) {
1959 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1960 d = ni_readl(dev,
1961 NI611X_AI_FIFO_DATA_REG);
1962 d >>= 16;
1963 d &= 0xffff;
1964 break;
1965 }
1966 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1967 NISTC_AI_STATUS1_FIFO_E)) {
1968 d = ni_readl(dev,
1969 NI611X_AI_FIFO_DATA_REG);
1970 d &= 0xffff;
1971 break;
1972 }
1973 }
1974 if (i == NI_TIMEOUT) {
1975 dev_err(dev->class_dev, "timeout\n");
1976 return -ETIME;
1977 }
1978 d += signbits;
1979 data[n] = d;
1980 }
1981 } else if (devpriv->is_6143) {
1982 for (n = 0; n < insn->n; n++) {
1983 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1984 NISTC_AI_CMD1_REG);
1985
1986 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1987 dl = 0;
1988 for (i = 0; i < NI_TIMEOUT; i++) {
1989 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) &
1990 0x01) {
1991 /* Get stranded sample into FIFO */
1992 ni_writel(dev, 0x01,
1993 NI6143_AI_FIFO_CTRL_REG);
1994 dl = ni_readl(dev,
1995 NI6143_AI_FIFO_DATA_REG);
1996 break;
1997 }
1998 }
1999 if (i == NI_TIMEOUT) {
2000 dev_err(dev->class_dev, "timeout\n");
2001 return -ETIME;
2002 }
2003 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
2004 }
2005 } else {
2006 for (n = 0; n < insn->n; n++) {
2007 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
2008 NISTC_AI_CMD1_REG);
2009 for (i = 0; i < NI_TIMEOUT; i++) {
2010 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
2011 NISTC_AI_STATUS1_FIFO_E))
2012 break;
2013 }
2014 if (i == NI_TIMEOUT) {
2015 dev_err(dev->class_dev, "timeout\n");
2016 return -ETIME;
2017 }
2018 if (devpriv->is_m_series) {
2019 dl = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
2020 dl &= mask;
2021 data[n] = dl;
2022 } else {
2023 d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
2024 d += signbits; /* subtle: needs to be short addition */
2025 data[n] = d;
2026 }
2027 }
2028 }
2029 return insn->n;
2030 }
2031
2032 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2033 unsigned int flags)
2034 {
2035 struct ni_private *devpriv = dev->private;
2036 int divider;
2037
2038 switch (flags & CMDF_ROUND_MASK) {
2039 case CMDF_ROUND_NEAREST:
2040 default:
2041 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2042 break;
2043 case CMDF_ROUND_DOWN:
2044 divider = (nanosec) / devpriv->clock_ns;
2045 break;
2046 case CMDF_ROUND_UP:
2047 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2048 break;
2049 }
2050 return divider - 1;
2051 }
2052
2053 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2054 {
2055 struct ni_private *devpriv = dev->private;
2056
2057 return devpriv->clock_ns * (timer + 1);
2058 }
2059
2060 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2061 unsigned num_channels)
2062 {
2063 const struct ni_board_struct *board = dev->board_ptr;
2064 struct ni_private *devpriv = dev->private;
2065
2066 /* simultaneously-sampled inputs */
2067 if (devpriv->is_611x || devpriv->is_6143)
2068 return board->ai_speed;
2069
2070 /* multiplexed inputs */
2071 return board->ai_speed * num_channels;
2072 }
2073
2074 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2075 struct comedi_cmd *cmd)
2076 {
2077 const struct ni_board_struct *board = dev->board_ptr;
2078 struct ni_private *devpriv = dev->private;
2079 int err = 0;
2080 unsigned int tmp;
2081 unsigned int sources;
2082
2083 /* Step 1 : check if triggers are trivially valid */
2084
2085 err |= comedi_check_trigger_src(&cmd->start_src,
2086 TRIG_NOW | TRIG_INT | TRIG_EXT);
2087 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2088 TRIG_TIMER | TRIG_EXT);
2089
2090 sources = TRIG_TIMER | TRIG_EXT;
2091 if (devpriv->is_611x || devpriv->is_6143)
2092 sources |= TRIG_NOW;
2093 err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2094
2095 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2096 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2097
2098 if (err)
2099 return 1;
2100
2101 /* Step 2a : make sure trigger sources are unique */
2102
2103 err |= comedi_check_trigger_is_unique(cmd->start_src);
2104 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2105 err |= comedi_check_trigger_is_unique(cmd->convert_src);
2106 err |= comedi_check_trigger_is_unique(cmd->stop_src);
2107
2108 /* Step 2b : and mutually compatible */
2109
2110 if (err)
2111 return 2;
2112
2113 /* Step 3: check if arguments are trivially valid */
2114
2115 switch (cmd->start_src) {
2116 case TRIG_NOW:
2117 case TRIG_INT:
2118 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2119 break;
2120 case TRIG_EXT:
2121 tmp = CR_CHAN(cmd->start_arg);
2122
2123 if (tmp > 16)
2124 tmp = 16;
2125 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2126 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
2127 break;
2128 }
2129
2130 if (cmd->scan_begin_src == TRIG_TIMER) {
2131 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2132 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2133 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2134 devpriv->clock_ns *
2135 0xffffff);
2136 } else if (cmd->scan_begin_src == TRIG_EXT) {
2137 /* external trigger */
2138 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2139
2140 if (tmp > 16)
2141 tmp = 16;
2142 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2143 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2144 } else { /* TRIG_OTHER */
2145 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2146 }
2147
2148 if (cmd->convert_src == TRIG_TIMER) {
2149 if (devpriv->is_611x || devpriv->is_6143) {
2150 err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2151 0);
2152 } else {
2153 err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2154 board->ai_speed);
2155 err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2156 devpriv->clock_ns *
2157 0xffff);
2158 }
2159 } else if (cmd->convert_src == TRIG_EXT) {
2160 /* external trigger */
2161 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2162
2163 if (tmp > 16)
2164 tmp = 16;
2165 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2166 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
2167 } else if (cmd->convert_src == TRIG_NOW) {
2168 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2169 }
2170
2171 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2172 cmd->chanlist_len);
2173
2174 if (cmd->stop_src == TRIG_COUNT) {
2175 unsigned int max_count = 0x01000000;
2176
2177 if (devpriv->is_611x)
2178 max_count -= num_adc_stages_611x;
2179 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2180 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2181 } else {
2182 /* TRIG_NONE */
2183 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2184 }
2185
2186 if (err)
2187 return 3;
2188
2189 /* step 4: fix up any arguments */
2190
2191 if (cmd->scan_begin_src == TRIG_TIMER) {
2192 tmp = cmd->scan_begin_arg;
2193 cmd->scan_begin_arg =
2194 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2195 cmd->scan_begin_arg,
2196 cmd->flags));
2197 if (tmp != cmd->scan_begin_arg)
2198 err++;
2199 }
2200 if (cmd->convert_src == TRIG_TIMER) {
2201 if (!devpriv->is_611x && !devpriv->is_6143) {
2202 tmp = cmd->convert_arg;
2203 cmd->convert_arg =
2204 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2205 cmd->convert_arg,
2206 cmd->flags));
2207 if (tmp != cmd->convert_arg)
2208 err++;
2209 if (cmd->scan_begin_src == TRIG_TIMER &&
2210 cmd->scan_begin_arg <
2211 cmd->convert_arg * cmd->scan_end_arg) {
2212 cmd->scan_begin_arg =
2213 cmd->convert_arg * cmd->scan_end_arg;
2214 err++;
2215 }
2216 }
2217 }
2218
2219 if (err)
2220 return 4;
2221
2222 return 0;
2223 }
2224
2225 static int ni_ai_inttrig(struct comedi_device *dev,
2226 struct comedi_subdevice *s,
2227 unsigned int trig_num)
2228 {
2229 struct ni_private *devpriv = dev->private;
2230 struct comedi_cmd *cmd = &s->async->cmd;
2231
2232 if (trig_num != cmd->start_arg)
2233 return -EINVAL;
2234
2235 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2236 NISTC_AI_CMD2_REG);
2237 s->async->inttrig = NULL;
2238
2239 return 1;
2240 }
2241
2242 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2243 {
2244 struct ni_private *devpriv = dev->private;
2245 const struct comedi_cmd *cmd = &s->async->cmd;
2246 int timer;
2247 int mode1 = 0; /* mode1 is needed for both stop and convert */
2248 int mode2 = 0;
2249 int start_stop_select = 0;
2250 unsigned int stop_count;
2251 int interrupt_a_enable = 0;
2252 unsigned ai_trig;
2253
2254 if (dev->irq == 0) {
2255 dev_err(dev->class_dev, "cannot run command without an irq\n");
2256 return -EIO;
2257 }
2258 ni_clear_ai_fifo(dev);
2259
2260 ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2261
2262 /* start configuration */
2263 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2264
2265 /* disable analog triggering for now, since it
2266 * interferes with the use of pfi0 */
2267 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2268 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2269
2270 ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2271 switch (cmd->start_src) {
2272 case TRIG_INT:
2273 case TRIG_NOW:
2274 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2275 NISTC_AI_TRIG_START1_SEL(0);
2276 break;
2277 case TRIG_EXT:
2278 ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) +
2279 1);
2280
2281 if (cmd->start_arg & CR_INVERT)
2282 ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2283 if (cmd->start_arg & CR_EDGE)
2284 ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2285 break;
2286 }
2287 ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2288
2289 mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2290 mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2291 mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2292 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2293
2294 if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2295 /* logic low */
2296 start_stop_select |= NISTC_AI_STOP_POLARITY |
2297 NISTC_AI_STOP_SEL(31) |
2298 NISTC_AI_STOP_SYNC;
2299 } else {
2300 /* ai configuration memory */
2301 start_stop_select |= NISTC_AI_STOP_SEL(19);
2302 }
2303 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2304
2305 devpriv->ai_cmd2 = 0;
2306 switch (cmd->stop_src) {
2307 case TRIG_COUNT:
2308 stop_count = cmd->stop_arg - 1;
2309
2310 if (devpriv->is_611x) {
2311 /* have to take 3 stage adc pipeline into account */
2312 stop_count += num_adc_stages_611x;
2313 }
2314 /* stage number of scans */
2315 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2316
2317 mode1 |= NISTC_AI_MODE1_START_STOP |
2318 NISTC_AI_MODE1_RSVD |
2319 NISTC_AI_MODE1_TRIGGER_ONCE;
2320 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2321 /* load SC (Scan Count) */
2322 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2323
2324 if (stop_count == 0) {
2325 devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2326 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2327 /* this is required to get the last sample for chanlist_len > 1, not sure why */
2328 if (cmd->chanlist_len > 1)
2329 start_stop_select |= NISTC_AI_STOP_POLARITY |
2330 NISTC_AI_STOP_EDGE;
2331 }
2332 break;
2333 case TRIG_NONE:
2334 /* stage number of scans */
2335 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2336
2337 mode1 |= NISTC_AI_MODE1_START_STOP |
2338 NISTC_AI_MODE1_RSVD |
2339 NISTC_AI_MODE1_CONTINUOUS;
2340 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2341
2342 /* load SC (Scan Count) */
2343 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2344 break;
2345 }
2346
2347 switch (cmd->scan_begin_src) {
2348 case TRIG_TIMER:
2349 /*
2350 * stop bits for non 611x boards
2351 * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2352 * NISTC_AI_MODE2_PRE_TRIGGER=0
2353 * NISTC_AI_START_STOP_REG:
2354 * NISTC_AI_START_POLARITY=0 (?) rising edge
2355 * NISTC_AI_START_EDGE=1 edge triggered
2356 * NISTC_AI_START_SYNC=1 (?)
2357 * NISTC_AI_START_SEL=0 SI_TC
2358 * NISTC_AI_STOP_POLARITY=0 rising edge
2359 * NISTC_AI_STOP_EDGE=0 level
2360 * NISTC_AI_STOP_SYNC=1
2361 * NISTC_AI_STOP_SEL=19 external pin (configuration mem)
2362 */
2363 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2364 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2365
2366 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC; /* A */
2367 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2368 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2369 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2370
2371 /* load SI */
2372 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2373 CMDF_ROUND_NEAREST);
2374 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2375 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2376 break;
2377 case TRIG_EXT:
2378 if (cmd->scan_begin_arg & CR_EDGE)
2379 start_stop_select |= NISTC_AI_START_EDGE;
2380 if (cmd->scan_begin_arg & CR_INVERT) /* falling edge */
2381 start_stop_select |= NISTC_AI_START_POLARITY;
2382 if (cmd->scan_begin_src != cmd->convert_src ||
2383 (cmd->scan_begin_arg & ~CR_EDGE) !=
2384 (cmd->convert_arg & ~CR_EDGE))
2385 start_stop_select |= NISTC_AI_START_SYNC;
2386 start_stop_select |=
2387 NISTC_AI_START_SEL(1 + CR_CHAN(cmd->scan_begin_arg));
2388 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2389 break;
2390 }
2391
2392 switch (cmd->convert_src) {
2393 case TRIG_TIMER:
2394 case TRIG_NOW:
2395 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2396 timer = 1;
2397 else
2398 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2399 CMDF_ROUND_NEAREST);
2400 /* 0,0 does not work */
2401 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2402 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2403
2404 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* A */
2405 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2406 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2407
2408 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2409
2410 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* B */
2411 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2412 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2413 break;
2414 case TRIG_EXT:
2415 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 + cmd->convert_arg);
2416 if ((cmd->convert_arg & CR_INVERT) == 0)
2417 mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2418 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2419
2420 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2421 NISTC_AI_MODE2_START_STOP_GATE_ENA;
2422 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2423
2424 break;
2425 }
2426
2427 if (dev->irq) {
2428 /* interrupt on FIFO, errors, SC_TC */
2429 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2430 NISTC_INTA_ENA_AI_SC_TC;
2431
2432 #ifndef PCIDMA
2433 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2434 #endif
2435
2436 if ((cmd->flags & CMDF_WAKE_EOS) ||
2437 (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2438 /* wake on end-of-scan */
2439 devpriv->aimode = AIMODE_SCAN;
2440 } else {
2441 devpriv->aimode = AIMODE_HALF_FULL;
2442 }
2443
2444 switch (devpriv->aimode) {
2445 case AIMODE_HALF_FULL:
2446 /*generate FIFO interrupts and DMA requests on half-full */
2447 #ifdef PCIDMA
2448 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2449 NISTC_AI_MODE3_REG);
2450 #else
2451 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2452 NISTC_AI_MODE3_REG);
2453 #endif
2454 break;
2455 case AIMODE_SAMPLE:
2456 /*generate FIFO interrupts on non-empty */
2457 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2458 NISTC_AI_MODE3_REG);
2459 break;
2460 case AIMODE_SCAN:
2461 #ifdef PCIDMA
2462 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2463 NISTC_AI_MODE3_REG);
2464 #else
2465 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2466 NISTC_AI_MODE3_REG);
2467 #endif
2468 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2469 break;
2470 default:
2471 break;
2472 }
2473
2474 /* clear interrupts */
2475 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2476
2477 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2478 } else {
2479 /* interrupt on nothing */
2480 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2481
2482 /* XXX start polling if necessary */
2483 }
2484
2485 /* end configuration */
2486 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2487
2488 switch (cmd->scan_begin_src) {
2489 case TRIG_TIMER:
2490 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2491 NISTC_AI_CMD1_SI_ARM |
2492 NISTC_AI_CMD1_DIV_ARM |
2493 NISTC_AI_CMD1_SC_ARM,
2494 NISTC_AI_CMD1_REG);
2495 break;
2496 case TRIG_EXT:
2497 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2498 NISTC_AI_CMD1_SI_ARM | /* XXX ? */
2499 NISTC_AI_CMD1_DIV_ARM |
2500 NISTC_AI_CMD1_SC_ARM,
2501 NISTC_AI_CMD1_REG);
2502 break;
2503 }
2504
2505 #ifdef PCIDMA
2506 {
2507 int retval = ni_ai_setup_MITE_dma(dev);
2508
2509 if (retval)
2510 return retval;
2511 }
2512 #endif
2513
2514 if (cmd->start_src == TRIG_NOW) {
2515 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2516 devpriv->ai_cmd2,
2517 NISTC_AI_CMD2_REG);
2518 s->async->inttrig = NULL;
2519 } else if (cmd->start_src == TRIG_EXT) {
2520 s->async->inttrig = NULL;
2521 } else { /* TRIG_INT */
2522 s->async->inttrig = ni_ai_inttrig;
2523 }
2524
2525 return 0;
2526 }
2527
2528 static int ni_ai_insn_config(struct comedi_device *dev,
2529 struct comedi_subdevice *s,
2530 struct comedi_insn *insn, unsigned int *data)
2531 {
2532 struct ni_private *devpriv = dev->private;
2533
2534 if (insn->n < 1)
2535 return -EINVAL;
2536
2537 switch (data[0]) {
2538 case INSN_CONFIG_ALT_SOURCE:
2539 if (devpriv->is_m_series) {
2540 if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2541 return -EINVAL;
2542 devpriv->ai_calib_source = data[1];
2543 } else if (devpriv->is_6143) {
2544 unsigned int calib_source;
2545
2546 calib_source = data[1] & 0xf;
2547
2548 devpriv->ai_calib_source = calib_source;
2549 ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG);
2550 } else {
2551 unsigned int calib_source;
2552 unsigned int calib_source_adjust;
2553
2554 calib_source = data[1] & 0xf;
2555 calib_source_adjust = (data[1] >> 4) & 0xff;
2556
2557 if (calib_source >= 8)
2558 return -EINVAL;
2559 devpriv->ai_calib_source = calib_source;
2560 if (devpriv->is_611x) {
2561 ni_writeb(dev, calib_source_adjust,
2562 NI611X_CAL_GAIN_SEL_REG);
2563 }
2564 }
2565 return 2;
2566 default:
2567 break;
2568 }
2569
2570 return -EINVAL;
2571 }
2572
2573 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2574 void *data, unsigned int num_bytes,
2575 unsigned int chan_index)
2576 {
2577 struct comedi_cmd *cmd = &s->async->cmd;
2578 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2579 unsigned short *array = data;
2580 unsigned int i;
2581 #ifdef PCIDMA
2582 __le16 buf, *barray = data;
2583 #endif
2584
2585 for (i = 0; i < nsamples; i++) {
2586 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2587 unsigned short val = array[i];
2588
2589 /*
2590 * Munge data from unsigned to two's complement for
2591 * bipolar ranges.
2592 */
2593 if (comedi_range_is_bipolar(s, range))
2594 val = comedi_offset_munge(s, val);
2595 #ifdef PCIDMA
2596 buf = cpu_to_le16(val);
2597 barray[i] = buf;
2598 #else
2599 array[i] = val;
2600 #endif
2601 chan_index++;
2602 chan_index %= cmd->chanlist_len;
2603 }
2604 }
2605
2606 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2607 struct comedi_subdevice *s,
2608 unsigned int chanspec[],
2609 unsigned int n_chans, int timed)
2610 {
2611 struct ni_private *devpriv = dev->private;
2612 unsigned int range;
2613 unsigned int chan;
2614 unsigned int conf;
2615 int i;
2616 int invert = 0;
2617
2618 if (timed) {
2619 for (i = 0; i < s->n_chan; ++i) {
2620 devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2621 ni_writeb(dev, devpriv->ao_conf[i],
2622 NI_M_AO_CFG_BANK_REG(i));
2623 ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2624 }
2625 }
2626 for (i = 0; i < n_chans; i++) {
2627 const struct comedi_krange *krange;
2628
2629 chan = CR_CHAN(chanspec[i]);
2630 range = CR_RANGE(chanspec[i]);
2631 krange = s->range_table->range + range;
2632 invert = 0;
2633 conf = 0;
2634 switch (krange->max - krange->min) {
2635 case 20000000:
2636 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2637 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2638 break;
2639 case 10000000:
2640 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2641 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2642 break;
2643 case 4000000:
2644 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2645 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2646 NI_M_AO_REF_ATTENUATION_REG(chan));
2647 break;
2648 case 2000000:
2649 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2650 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2651 NI_M_AO_REF_ATTENUATION_REG(chan));
2652 break;
2653 default:
2654 dev_err(dev->class_dev,
2655 "bug! unhandled ao reference voltage\n");
2656 break;
2657 }
2658 switch (krange->max + krange->min) {
2659 case 0:
2660 conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2661 break;
2662 case 10000000:
2663 conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2664 break;
2665 default:
2666 dev_err(dev->class_dev,
2667 "bug! unhandled ao offset voltage\n");
2668 break;
2669 }
2670 if (timed)
2671 conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2672 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2673 devpriv->ao_conf[chan] = conf;
2674 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2675 }
2676 return invert;
2677 }
2678
2679 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2680 struct comedi_subdevice *s,
2681 unsigned int chanspec[],
2682 unsigned int n_chans)
2683 {
2684 struct ni_private *devpriv = dev->private;
2685 unsigned int range;
2686 unsigned int chan;
2687 unsigned int conf;
2688 int i;
2689 int invert = 0;
2690
2691 for (i = 0; i < n_chans; i++) {
2692 chan = CR_CHAN(chanspec[i]);
2693 range = CR_RANGE(chanspec[i]);
2694 conf = NI_E_AO_DACSEL(chan);
2695
2696 if (comedi_range_is_bipolar(s, range)) {
2697 conf |= NI_E_AO_CFG_BIP;
2698 invert = (s->maxdata + 1) >> 1;
2699 } else {
2700 invert = 0;
2701 }
2702 if (comedi_range_is_external(s, range))
2703 conf |= NI_E_AO_EXT_REF;
2704
2705 /* not all boards can deglitch, but this shouldn't hurt */
2706 if (chanspec[i] & CR_DEGLITCH)
2707 conf |= NI_E_AO_DEGLITCH;
2708
2709 /* analog reference */
2710 /* AREF_OTHER connects AO ground to AI ground, i think */
2711 if (CR_AREF(chanspec[i]) == AREF_OTHER)
2712 conf |= NI_E_AO_GROUND_REF;
2713
2714 ni_writew(dev, conf, NI_E_AO_CFG_REG);
2715 devpriv->ao_conf[chan] = conf;
2716 }
2717 return invert;
2718 }
2719
2720 static int ni_ao_config_chanlist(struct comedi_device *dev,
2721 struct comedi_subdevice *s,
2722 unsigned int chanspec[], unsigned int n_chans,
2723 int timed)
2724 {
2725 struct ni_private *devpriv = dev->private;
2726
2727 if (devpriv->is_m_series)
2728 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2729 timed);
2730 else
2731 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2732 }
2733
2734 static int ni_ao_insn_write(struct comedi_device *dev,
2735 struct comedi_subdevice *s,
2736 struct comedi_insn *insn,
2737 unsigned int *data)
2738 {
2739 struct ni_private *devpriv = dev->private;
2740 unsigned int chan = CR_CHAN(insn->chanspec);
2741 unsigned int range = CR_RANGE(insn->chanspec);
2742 int reg;
2743 int i;
2744
2745 if (devpriv->is_6xxx) {
2746 ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
2747
2748 reg = NI671X_DAC_DIRECT_DATA_REG(chan);
2749 } else if (devpriv->is_m_series) {
2750 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2751 } else {
2752 reg = NI_E_DAC_DIRECT_DATA_REG(chan);
2753 }
2754
2755 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2756
2757 for (i = 0; i < insn->n; i++) {
2758 unsigned int val = data[i];
2759
2760 s->readback[chan] = val;
2761
2762 if (devpriv->is_6xxx) {
2763 /*
2764 * 6xxx boards have bipolar outputs, munge the
2765 * unsigned comedi values to 2's complement
2766 */
2767 val = comedi_offset_munge(s, val);
2768
2769 ni_ao_win_outw(dev, val, reg);
2770 } else if (devpriv->is_m_series) {
2771 /*
2772 * M-series boards use offset binary values for
2773 * bipolar and uinpolar outputs
2774 */
2775 ni_writew(dev, val, reg);
2776 } else {
2777 /*
2778 * Non-M series boards need two's complement values
2779 * for bipolar ranges.
2780 */
2781 if (comedi_range_is_bipolar(s, range))
2782 val = comedi_offset_munge(s, val);
2783
2784 ni_writew(dev, val, reg);
2785 }
2786 }
2787
2788 return insn->n;
2789 }
2790
2791 static int ni_ao_insn_config(struct comedi_device *dev,
2792 struct comedi_subdevice *s,
2793 struct comedi_insn *insn, unsigned int *data)
2794 {
2795 const struct ni_board_struct *board = dev->board_ptr;
2796 struct ni_private *devpriv = dev->private;
2797 unsigned int nbytes;
2798
2799 switch (data[0]) {
2800 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2801 switch (data[1]) {
2802 case COMEDI_OUTPUT:
2803 nbytes = comedi_samples_to_bytes(s,
2804 board->ao_fifo_depth);
2805 data[2] = 1 + nbytes;
2806 if (devpriv->mite)
2807 data[2] += devpriv->mite->fifo_size;
2808 break;
2809 case COMEDI_INPUT:
2810 data[2] = 0;
2811 break;
2812 default:
2813 return -EINVAL;
2814 }
2815 return 0;
2816 default:
2817 break;
2818 }
2819
2820 return -EINVAL;
2821 }
2822
2823 static int ni_ao_inttrig(struct comedi_device *dev,
2824 struct comedi_subdevice *s,
2825 unsigned int trig_num)
2826 {
2827 struct ni_private *devpriv = dev->private;
2828 struct comedi_cmd *cmd = &s->async->cmd;
2829 int ret;
2830 int interrupt_b_bits;
2831 int i;
2832 static const int timeout = 1000;
2833
2834 if (trig_num != cmd->start_arg)
2835 return -EINVAL;
2836
2837 /* Null trig at beginning prevent ao start trigger from executing more than
2838 once per command (and doing things like trying to allocate the ao dma channel
2839 multiple times) */
2840 s->async->inttrig = NULL;
2841
2842 ni_set_bits(dev, NISTC_INTB_ENA_REG,
2843 NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2844 interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2845 #ifdef PCIDMA
2846 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2847 if (devpriv->is_6xxx)
2848 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
2849 ret = ni_ao_setup_MITE_dma(dev);
2850 if (ret)
2851 return ret;
2852 ret = ni_ao_wait_for_dma_load(dev);
2853 if (ret < 0)
2854 return ret;
2855 #else
2856 ret = ni_ao_prep_fifo(dev, s);
2857 if (ret == 0)
2858 return -EPIPE;
2859
2860 interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2861 #endif
2862
2863 ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2864 NISTC_AO_MODE3_REG);
2865 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2866 /* wait for DACs to be loaded */
2867 for (i = 0; i < timeout; i++) {
2868 udelay(1);
2869 if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2870 NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
2871 break;
2872 }
2873 if (i == timeout) {
2874 dev_err(dev->class_dev,
2875 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2876 return -EIO;
2877 }
2878 /*
2879 * stc manual says we are need to clear error interrupt after
2880 * AO_TMRDACWRs_In_Progress_St clears
2881 */
2882 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2883
2884 ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2885
2886 ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2887 NISTC_AO_CMD1_UC_ARM |
2888 NISTC_AO_CMD1_BC_ARM |
2889 NISTC_AO_CMD1_DAC1_UPDATE_MODE |
2890 NISTC_AO_CMD1_DAC0_UPDATE_MODE |
2891 devpriv->ao_cmd1,
2892 NISTC_AO_CMD1_REG);
2893
2894 ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2895 NISTC_AO_CMD2_REG);
2896
2897 return 0;
2898 }
2899
2900 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2901 {
2902 const struct ni_board_struct *board = dev->board_ptr;
2903 struct ni_private *devpriv = dev->private;
2904 const struct comedi_cmd *cmd = &s->async->cmd;
2905 int bits;
2906 int i;
2907 unsigned trigvar;
2908 unsigned val;
2909
2910 if (dev->irq == 0) {
2911 dev_err(dev->class_dev, "cannot run command without an irq\n");
2912 return -EIO;
2913 }
2914
2915 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2916
2917 ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
2918
2919 if (devpriv->is_6xxx) {
2920 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
2921 NI611X_AO_MISC_REG);
2922
2923 bits = 0;
2924 for (i = 0; i < cmd->chanlist_len; i++) {
2925 int chan;
2926
2927 chan = CR_CHAN(cmd->chanlist[i]);
2928 bits |= 1 << chan;
2929 ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
2930 }
2931 ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
2932 }
2933
2934 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
2935
2936 if (cmd->stop_src == TRIG_NONE) {
2937 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2938 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2939 } else {
2940 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2941 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2942 }
2943 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2944
2945 val = devpriv->ao_trigger_select;
2946 switch (cmd->start_src) {
2947 case TRIG_INT:
2948 case TRIG_NOW:
2949 val &= ~(NISTC_AO_TRIG_START1_POLARITY |
2950 NISTC_AO_TRIG_START1_SEL_MASK);
2951 val |= NISTC_AO_TRIG_START1_EDGE |
2952 NISTC_AO_TRIG_START1_SYNC;
2953 break;
2954 case TRIG_EXT:
2955 val = NISTC_AO_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + 1);
2956 if (cmd->start_arg & CR_INVERT) {
2957 /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
2958 val |= NISTC_AO_TRIG_START1_POLARITY;
2959 }
2960 if (cmd->start_arg & CR_EDGE) {
2961 /* 0=edge detection disabled, 1=enabled */
2962 val |= NISTC_AO_TRIG_START1_EDGE;
2963 }
2964 ni_stc_writew(dev, devpriv->ao_trigger_select,
2965 NISTC_AO_TRIG_SEL_REG);
2966 break;
2967 default:
2968 BUG();
2969 break;
2970 }
2971 devpriv->ao_trigger_select = val;
2972 ni_stc_writew(dev, devpriv->ao_trigger_select, NISTC_AO_TRIG_SEL_REG);
2973
2974 devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
2975 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2976
2977 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2978 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
2979 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2980 if (cmd->stop_src == TRIG_NONE)
2981 ni_stc_writel(dev, 0xffffff, NISTC_AO_BC_LOADA_REG);
2982 else
2983 ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG);
2984 ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
2985 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
2986 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2987 switch (cmd->stop_src) {
2988 case TRIG_COUNT:
2989 if (devpriv->is_m_series) {
2990 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
2991 ni_stc_writel(dev, cmd->stop_arg - 1,
2992 NISTC_AO_UC_LOADA_REG);
2993 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
2994 NISTC_AO_CMD1_REG);
2995 } else {
2996 ni_stc_writel(dev, cmd->stop_arg,
2997 NISTC_AO_UC_LOADA_REG);
2998 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
2999 NISTC_AO_CMD1_REG);
3000 ni_stc_writel(dev, cmd->stop_arg - 1,
3001 NISTC_AO_UC_LOADA_REG);
3002 }
3003 break;
3004 case TRIG_NONE:
3005 ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
3006 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
3007 ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
3008 break;
3009 default:
3010 ni_stc_writel(dev, 0, NISTC_AO_UC_LOADA_REG);
3011 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
3012 ni_stc_writel(dev, cmd->stop_arg, NISTC_AO_UC_LOADA_REG);
3013 }
3014
3015 devpriv->ao_mode1 &= ~(NISTC_AO_MODE1_UPDATE_SRC_MASK |
3016 NISTC_AO_MODE1_UI_SRC_MASK |
3017 NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3018 NISTC_AO_MODE1_UI_SRC_POLARITY);
3019 switch (cmd->scan_begin_src) {
3020 case TRIG_TIMER:
3021 devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3022 trigvar =
3023 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3024 CMDF_ROUND_NEAREST);
3025 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3026 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3027 ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
3028 break;
3029 case TRIG_EXT:
3030 devpriv->ao_mode1 |=
3031 NISTC_AO_MODE1_UPDATE_SRC(cmd->scan_begin_arg);
3032 if (cmd->scan_begin_arg & CR_INVERT)
3033 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3034 devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA;
3035 break;
3036 default:
3037 BUG();
3038 break;
3039 }
3040 ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3041 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3042 devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3043 NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3044 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3045
3046 if (cmd->scan_end_arg > 1) {
3047 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3048 ni_stc_writew(dev,
3049 NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1) |
3050 NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ,
3051 NISTC_AO_OUT_CTRL_REG);
3052 } else {
3053 unsigned bits;
3054
3055 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3056 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3057 if (devpriv->is_m_series || devpriv->is_6xxx) {
3058 bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3059 } else {
3060 bits |=
3061 NISTC_AO_OUT_CTRL_CHANS(CR_CHAN(cmd->chanlist[0]));
3062 }
3063 ni_stc_writew(dev, bits, NISTC_AO_OUT_CTRL_REG);
3064 }
3065 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3066
3067 ni_stc_writew(dev, NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3068 NISTC_AO_CMD1_DAC0_UPDATE_MODE,
3069 NISTC_AO_CMD1_REG);
3070
3071 devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3072 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3073
3074 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3075 #ifdef PCIDMA
3076 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3077 #else
3078 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3079 #endif
3080 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3081 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3082
3083 bits = NISTC_AO_PERSONAL_BC_SRC_SEL |
3084 NISTC_AO_PERSONAL_UPDATE_PW |
3085 NISTC_AO_PERSONAL_TMRDACWR_PW;
3086 if (board->ao_fifo_depth)
3087 bits |= NISTC_AO_PERSONAL_FIFO_ENA;
3088 else
3089 bits |= NISTC_AO_PERSONAL_DMA_PIO_CTRL;
3090 #if 0
3091 /*
3092 * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit
3093 * for 6281, verified with bus analyzer.
3094 */
3095 if (devpriv->is_m_series)
3096 bits |= NISTC_AO_PERSONAL_NUM_DAC;
3097 #endif
3098 ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
3099 /* enable sending of ao dma requests */
3100 ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3101
3102 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3103
3104 if (cmd->stop_src == TRIG_COUNT) {
3105 ni_stc_writew(dev, NISTC_INTB_ACK_AO_BC_TC,
3106 NISTC_INTB_ACK_REG);
3107 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3108 NISTC_INTB_ENA_AO_BC_TC, 1);
3109 }
3110
3111 s->async->inttrig = ni_ao_inttrig;
3112
3113 return 0;
3114 }
3115
3116 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3117 struct comedi_cmd *cmd)
3118 {
3119 const struct ni_board_struct *board = dev->board_ptr;
3120 struct ni_private *devpriv = dev->private;
3121 int err = 0;
3122 unsigned int tmp;
3123
3124 /* Step 1 : check if triggers are trivially valid */
3125
3126 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3127 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3128 TRIG_TIMER | TRIG_EXT);
3129 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3130 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3131 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3132
3133 if (err)
3134 return 1;
3135
3136 /* Step 2a : make sure trigger sources are unique */
3137
3138 err |= comedi_check_trigger_is_unique(cmd->start_src);
3139 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3140 err |= comedi_check_trigger_is_unique(cmd->stop_src);
3141
3142 /* Step 2b : and mutually compatible */
3143
3144 if (err)
3145 return 2;
3146
3147 /* Step 3: check if arguments are trivially valid */
3148
3149 switch (cmd->start_src) {
3150 case TRIG_INT:
3151 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3152 break;
3153 case TRIG_EXT:
3154 tmp = CR_CHAN(cmd->start_arg);
3155
3156 if (tmp > 18)
3157 tmp = 18;
3158 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3159 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
3160 break;
3161 }
3162
3163 if (cmd->scan_begin_src == TRIG_TIMER) {
3164 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3165 board->ao_speed);
3166 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3167 devpriv->clock_ns *
3168 0xffffff);
3169 }
3170
3171 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3172 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3173 cmd->chanlist_len);
3174
3175 if (cmd->stop_src == TRIG_COUNT)
3176 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3177 else /* TRIG_NONE */
3178 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3179
3180 if (err)
3181 return 3;
3182
3183 /* step 4: fix up any arguments */
3184 if (cmd->scan_begin_src == TRIG_TIMER) {
3185 tmp = cmd->scan_begin_arg;
3186 cmd->scan_begin_arg =
3187 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3188 cmd->scan_begin_arg,
3189 cmd->flags));
3190 if (tmp != cmd->scan_begin_arg)
3191 err++;
3192 }
3193 if (err)
3194 return 4;
3195
3196 return 0;
3197 }
3198
3199 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3200 {
3201 struct ni_private *devpriv = dev->private;
3202
3203 ni_release_ao_mite_channel(dev);
3204
3205 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3206 ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3207 ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3208 ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3209 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3210 ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL |
3211 NISTC_AO_PERSONAL_UPDATE_PW |
3212 NISTC_AO_PERSONAL_TMRDACWR_PW,
3213 NISTC_AO_PERSONAL_REG);
3214 ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3215 ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3216 devpriv->ao_cmd1 = 0;
3217 ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3218 devpriv->ao_cmd2 = 0;
3219 ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3220 devpriv->ao_mode1 = 0;
3221 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3222 devpriv->ao_mode2 = 0;
3223 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3224 if (devpriv->is_m_series)
3225 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3226 else
3227 devpriv->ao_mode3 = 0;
3228 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3229 devpriv->ao_trigger_select = 0;
3230 ni_stc_writew(dev, devpriv->ao_trigger_select,
3231 NISTC_AO_TRIG_SEL_REG);
3232 if (devpriv->is_6xxx) {
3233 unsigned immediate_bits = 0;
3234 unsigned i;
3235
3236 for (i = 0; i < s->n_chan; ++i)
3237 immediate_bits |= 1 << i;
3238 ni_ao_win_outw(dev, immediate_bits, NI671X_AO_IMMEDIATE_REG);
3239 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
3240 NI611X_AO_MISC_REG);
3241 }
3242 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3243
3244 return 0;
3245 }
3246
3247 /* digital io */
3248
3249 static int ni_dio_insn_config(struct comedi_device *dev,
3250 struct comedi_subdevice *s,
3251 struct comedi_insn *insn,
3252 unsigned int *data)
3253 {
3254 struct ni_private *devpriv = dev->private;
3255 int ret;
3256
3257 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3258 if (ret)
3259 return ret;
3260
3261 devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3262 devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3263 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3264
3265 return insn->n;
3266 }
3267
3268 static int ni_dio_insn_bits(struct comedi_device *dev,
3269 struct comedi_subdevice *s,
3270 struct comedi_insn *insn,
3271 unsigned int *data)
3272 {
3273 struct ni_private *devpriv = dev->private;
3274
3275 /* Make sure we're not using the serial part of the dio */
3276 if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3277 devpriv->serial_interval_ns)
3278 return -EBUSY;
3279
3280 if (comedi_dio_update_state(s, data)) {
3281 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3282 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3283 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3284 }
3285
3286 data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3287
3288 return insn->n;
3289 }
3290
3291 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3292 struct comedi_subdevice *s,
3293 struct comedi_insn *insn,
3294 unsigned int *data)
3295 {
3296 int ret;
3297
3298 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3299 if (ret)
3300 return ret;
3301
3302 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3303
3304 return insn->n;
3305 }
3306
3307 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3308 struct comedi_subdevice *s,
3309 struct comedi_insn *insn,
3310 unsigned int *data)
3311 {
3312 if (comedi_dio_update_state(s, data))
3313 ni_writel(dev, s->state, NI_M_DIO_REG);
3314
3315 data[1] = ni_readl(dev, NI_M_DIO_REG);
3316
3317 return insn->n;
3318 }
3319
3320 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3321 struct comedi_subdevice *s,
3322 struct comedi_cmd *cmd)
3323 {
3324 int i;
3325
3326 for (i = 0; i < cmd->chanlist_len; ++i) {
3327 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3328
3329 if (chan != i)
3330 return -EINVAL;
3331 }
3332
3333 return 0;
3334 }
3335
3336 static int ni_cdio_cmdtest(struct comedi_device *dev,
3337 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3338 {
3339 int err = 0;
3340 int tmp;
3341
3342 /* Step 1 : check if triggers are trivially valid */
3343
3344 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3345 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3346 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3347 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3348 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3349
3350 if (err)
3351 return 1;
3352
3353 /* Step 2a : make sure trigger sources are unique */
3354 /* Step 2b : and mutually compatible */
3355
3356 /* Step 3: check if arguments are trivially valid */
3357
3358 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3359
3360 tmp = cmd->scan_begin_arg;
3361 tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT);
3362 if (tmp != cmd->scan_begin_arg)
3363 err |= -EINVAL;
3364
3365 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3366 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3367 cmd->chanlist_len);
3368 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3369
3370 if (err)
3371 return 3;
3372
3373 /* Step 4: fix up any arguments */
3374
3375 /* Step 5: check channel list if it exists */
3376
3377 if (cmd->chanlist && cmd->chanlist_len > 0)
3378 err |= ni_cdio_check_chanlist(dev, s, cmd);
3379
3380 if (err)
3381 return 5;
3382
3383 return 0;
3384 }
3385
3386 static int ni_cdo_inttrig(struct comedi_device *dev,
3387 struct comedi_subdevice *s,
3388 unsigned int trig_num)
3389 {
3390 struct comedi_cmd *cmd = &s->async->cmd;
3391 const unsigned timeout = 1000;
3392 int retval = 0;
3393 unsigned i;
3394 #ifdef PCIDMA
3395 struct ni_private *devpriv = dev->private;
3396 unsigned long flags;
3397 #endif
3398
3399 if (trig_num != cmd->start_arg)
3400 return -EINVAL;
3401
3402 s->async->inttrig = NULL;
3403
3404 /* read alloc the entire buffer */
3405 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3406
3407 #ifdef PCIDMA
3408 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3409 if (devpriv->cdo_mite_chan) {
3410 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3411 mite_dma_arm(devpriv->cdo_mite_chan);
3412 } else {
3413 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3414 retval = -EIO;
3415 }
3416 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3417 if (retval < 0)
3418 return retval;
3419 #endif
3420 /*
3421 * XXX not sure what interrupt C group does
3422 * wait for dma to fill output fifo
3423 * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3424 */
3425 for (i = 0; i < timeout; ++i) {
3426 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3427 NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3428 break;
3429 udelay(10);
3430 }
3431 if (i == timeout) {
3432 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3433 s->cancel(dev, s);
3434 return -EIO;
3435 }
3436 ni_writel(dev, NI_M_CDO_CMD_ARM |
3437 NI_M_CDO_CMD_ERR_INT_ENA_SET |
3438 NI_M_CDO_CMD_F_E_INT_ENA_SET,
3439 NI_M_CDIO_CMD_REG);
3440 return retval;
3441 }
3442
3443 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3444 {
3445 const struct comedi_cmd *cmd = &s->async->cmd;
3446 unsigned cdo_mode_bits;
3447 int retval;
3448
3449 ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3450 cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3451 NI_M_CDO_MODE_HALT_ON_ERROR |
3452 NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg));
3453 if (cmd->scan_begin_arg & CR_INVERT)
3454 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3455 ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3456 if (s->io_bits) {
3457 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3458 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3459 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3460 } else {
3461 dev_err(dev->class_dev,
3462 "attempted to run digital output command with no lines configured as outputs\n");
3463 return -EIO;
3464 }
3465 retval = ni_request_cdo_mite_channel(dev);
3466 if (retval < 0)
3467 return retval;
3468
3469 s->async->inttrig = ni_cdo_inttrig;
3470
3471 return 0;
3472 }
3473
3474 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3475 {
3476 ni_writel(dev, NI_M_CDO_CMD_DISARM |
3477 NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3478 NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3479 NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3480 NI_M_CDIO_CMD_REG);
3481 /*
3482 * XXX not sure what interrupt C group does
3483 * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3484 */
3485 ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3486 ni_release_cdo_mite_channel(dev);
3487 return 0;
3488 }
3489
3490 static void handle_cdio_interrupt(struct comedi_device *dev)
3491 {
3492 struct ni_private *devpriv = dev->private;
3493 unsigned cdio_status;
3494 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3495 #ifdef PCIDMA
3496 unsigned long flags;
3497 #endif
3498
3499 if (!devpriv->is_m_series)
3500 return;
3501 #ifdef PCIDMA
3502 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3503 if (devpriv->cdo_mite_chan) {
3504 unsigned cdo_mite_status =
3505 mite_get_status(devpriv->cdo_mite_chan);
3506 if (cdo_mite_status & CHSR_LINKC) {
3507 writel(CHOR_CLRLC,
3508 devpriv->mite->mite_io_addr +
3509 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3510 }
3511 mite_sync_output_dma(devpriv->cdo_mite_chan, s);
3512 }
3513 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3514 #endif
3515
3516 cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3517 if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3518 /* XXX just guessing this is needed and does something useful */
3519 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3520 NI_M_CDIO_CMD_REG);
3521 s->async->events |= COMEDI_CB_OVERFLOW;
3522 }
3523 if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3524 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3525 NI_M_CDIO_CMD_REG);
3526 /* s->async->events |= COMEDI_CB_EOA; */
3527 }
3528 comedi_handle_events(dev, s);
3529 }
3530
3531 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3532 struct comedi_subdevice *s,
3533 unsigned char data_out,
3534 unsigned char *data_in)
3535 {
3536 struct ni_private *devpriv = dev->private;
3537 unsigned int status1;
3538 int err = 0, count = 20;
3539
3540 devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3541 devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3542 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3543
3544 status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3545 if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
3546 err = -EBUSY;
3547 goto Error;
3548 }
3549
3550 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3551 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3552 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3553
3554 /* Wait until STC says we're done, but don't loop infinitely. */
3555 while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3556 NISTC_STATUS1_SERIO_IN_PROG) {
3557 /* Delay one bit per loop */
3558 udelay((devpriv->serial_interval_ns + 999) / 1000);
3559 if (--count < 0) {
3560 dev_err(dev->class_dev,
3561 "SPI serial I/O didn't finish in time!\n");
3562 err = -ETIME;
3563 goto Error;
3564 }
3565 }
3566
3567 /*
3568 * Delay for last bit. This delay is absolutely necessary, because
3569 * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3570 */
3571 udelay((devpriv->serial_interval_ns + 999) / 1000);
3572
3573 if (data_in)
3574 *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
3575
3576 Error:
3577 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3578
3579 return err;
3580 }
3581
3582 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3583 struct comedi_subdevice *s,
3584 unsigned char data_out,
3585 unsigned char *data_in)
3586 {
3587 struct ni_private *devpriv = dev->private;
3588 unsigned char mask, input = 0;
3589
3590 /* Wait for one bit before transfer */
3591 udelay((devpriv->serial_interval_ns + 999) / 1000);
3592
3593 for (mask = 0x80; mask; mask >>= 1) {
3594 /* Output current bit; note that we cannot touch s->state
3595 because it is a per-subdevice field, and serial is
3596 a separate subdevice from DIO. */
3597 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3598 if (data_out & mask)
3599 devpriv->dio_output |= NISTC_DIO_SDOUT;
3600 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3601
3602 /* Assert SDCLK (active low, inverted), wait for half of
3603 the delay, deassert SDCLK, and wait for the other half. */
3604 devpriv->dio_control |= NISTC_DIO_SDCLK;
3605 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3606
3607 udelay((devpriv->serial_interval_ns + 999) / 2000);
3608
3609 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3610 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3611
3612 udelay((devpriv->serial_interval_ns + 999) / 2000);
3613
3614 /* Input current bit */
3615 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3616 input |= mask;
3617 }
3618
3619 if (data_in)
3620 *data_in = input;
3621
3622 return 0;
3623 }
3624
3625 static int ni_serial_insn_config(struct comedi_device *dev,
3626 struct comedi_subdevice *s,
3627 struct comedi_insn *insn,
3628 unsigned int *data)
3629 {
3630 struct ni_private *devpriv = dev->private;
3631 unsigned clk_fout = devpriv->clock_and_fout;
3632 int err = insn->n;
3633 unsigned char byte_out, byte_in = 0;
3634
3635 if (insn->n != 2)
3636 return -EINVAL;
3637
3638 switch (data[0]) {
3639 case INSN_CONFIG_SERIAL_CLOCK:
3640 devpriv->serial_hw_mode = 1;
3641 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3642
3643 if (data[1] == SERIAL_DISABLED) {
3644 devpriv->serial_hw_mode = 0;
3645 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3646 NISTC_DIO_SDCLK);
3647 data[1] = SERIAL_DISABLED;
3648 devpriv->serial_interval_ns = data[1];
3649 } else if (data[1] <= SERIAL_600NS) {
3650 /* Warning: this clock speed is too fast to reliably
3651 control SCXI. */
3652 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3653 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3654 clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3655 data[1] = SERIAL_600NS;
3656 devpriv->serial_interval_ns = data[1];
3657 } else if (data[1] <= SERIAL_1_2US) {
3658 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3659 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3660 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3661 data[1] = SERIAL_1_2US;
3662 devpriv->serial_interval_ns = data[1];
3663 } else if (data[1] <= SERIAL_10US) {
3664 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3665 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3666 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3667 /* Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3668 600ns/1.2us. If you turn divide_by_2 off with the
3669 slow clock, you will still get 10us, except then
3670 all your delays are wrong. */
3671 data[1] = SERIAL_10US;
3672 devpriv->serial_interval_ns = data[1];
3673 } else {
3674 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3675 NISTC_DIO_SDCLK);
3676 devpriv->serial_hw_mode = 0;
3677 data[1] = (data[1] / 1000) * 1000;
3678 devpriv->serial_interval_ns = data[1];
3679 }
3680 devpriv->clock_and_fout = clk_fout;
3681
3682 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3683 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3684 return 1;
3685
3686 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3687
3688 if (devpriv->serial_interval_ns == 0)
3689 return -EINVAL;
3690
3691 byte_out = data[1] & 0xFF;
3692
3693 if (devpriv->serial_hw_mode) {
3694 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3695 &byte_in);
3696 } else if (devpriv->serial_interval_ns > 0) {
3697 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3698 &byte_in);
3699 } else {
3700 dev_err(dev->class_dev, "serial disabled!\n");
3701 return -EINVAL;
3702 }
3703 if (err < 0)
3704 return err;
3705 data[1] = byte_in & 0xFF;
3706 return insn->n;
3707
3708 break;
3709 default:
3710 return -EINVAL;
3711 }
3712 }
3713
3714 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3715 {
3716 int i;
3717
3718 for (i = 0; i < s->n_chan; i++) {
3719 ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
3720 NI67XX_AO_CFG2_REG);
3721 }
3722 ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
3723 }
3724
3725 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3726 [NITIO_G0_AUTO_INC] = { NISTC_G0_AUTOINC_REG, 2 },
3727 [NITIO_G1_AUTO_INC] = { NISTC_G1_AUTOINC_REG, 2 },
3728 [NITIO_G0_CMD] = { NISTC_G0_CMD_REG, 2 },
3729 [NITIO_G1_CMD] = { NISTC_G1_CMD_REG, 2 },
3730 [NITIO_G0_HW_SAVE] = { NISTC_G0_HW_SAVE_REG, 4 },
3731 [NITIO_G1_HW_SAVE] = { NISTC_G1_HW_SAVE_REG, 4 },
3732 [NITIO_G0_SW_SAVE] = { NISTC_G0_SAVE_REG, 4 },
3733 [NITIO_G1_SW_SAVE] = { NISTC_G1_SAVE_REG, 4 },
3734 [NITIO_G0_MODE] = { NISTC_G0_MODE_REG, 2 },
3735 [NITIO_G1_MODE] = { NISTC_G1_MODE_REG, 2 },
3736 [NITIO_G0_LOADA] = { NISTC_G0_LOADA_REG, 4 },
3737 [NITIO_G1_LOADA] = { NISTC_G1_LOADA_REG, 4 },
3738 [NITIO_G0_LOADB] = { NISTC_G0_LOADB_REG, 4 },
3739 [NITIO_G1_LOADB] = { NISTC_G1_LOADB_REG, 4 },
3740 [NITIO_G0_INPUT_SEL] = { NISTC_G0_INPUT_SEL_REG, 2 },
3741 [NITIO_G1_INPUT_SEL] = { NISTC_G1_INPUT_SEL_REG, 2 },
3742 [NITIO_G0_CNT_MODE] = { 0x1b0, 2 }, /* M-Series only */
3743 [NITIO_G1_CNT_MODE] = { 0x1b2, 2 }, /* M-Series only */
3744 [NITIO_G0_GATE2] = { 0x1b4, 2 }, /* M-Series only */
3745 [NITIO_G1_GATE2] = { 0x1b6, 2 }, /* M-Series only */
3746 [NITIO_G01_STATUS] = { NISTC_G01_STATUS_REG, 2 },
3747 [NITIO_G01_RESET] = { NISTC_RESET_REG, 2 },
3748 [NITIO_G01_STATUS1] = { NISTC_STATUS1_REG, 2 },
3749 [NITIO_G01_STATUS2] = { NISTC_STATUS2_REG, 2 },
3750 [NITIO_G0_DMA_CFG] = { 0x1b8, 2 }, /* M-Series only */
3751 [NITIO_G1_DMA_CFG] = { 0x1ba, 2 }, /* M-Series only */
3752 [NITIO_G0_DMA_STATUS] = { 0x1b8, 2 }, /* M-Series only */
3753 [NITIO_G1_DMA_STATUS] = { 0x1ba, 2 }, /* M-Series only */
3754 [NITIO_G0_ABZ] = { 0x1c0, 2 }, /* M-Series only */
3755 [NITIO_G1_ABZ] = { 0x1c2, 2 }, /* M-Series only */
3756 [NITIO_G0_INT_ACK] = { NISTC_INTA_ACK_REG, 2 },
3757 [NITIO_G1_INT_ACK] = { NISTC_INTB_ACK_REG, 2 },
3758 [NITIO_G0_STATUS] = { NISTC_AI_STATUS1_REG, 2 },
3759 [NITIO_G1_STATUS] = { NISTC_AO_STATUS1_REG, 2 },
3760 [NITIO_G0_INT_ENA] = { NISTC_INTA_ENA_REG, 2 },
3761 [NITIO_G1_INT_ENA] = { NISTC_INTB_ENA_REG, 2 },
3762 };
3763
3764 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3765 enum ni_gpct_register reg)
3766 {
3767 const struct mio_regmap *regmap;
3768
3769 if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
3770 regmap = &ni_gpct_to_stc_regmap[reg];
3771 } else {
3772 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
3773 __func__, reg);
3774 return 0;
3775 }
3776
3777 return regmap->mio_reg;
3778 }
3779
3780 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
3781 enum ni_gpct_register reg)
3782 {
3783 struct comedi_device *dev = counter->counter_dev->dev;
3784 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3785 static const unsigned gpct_interrupt_a_enable_mask =
3786 NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC;
3787 static const unsigned gpct_interrupt_b_enable_mask =
3788 NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC;
3789
3790 if (stc_register == 0)
3791 return;
3792
3793 switch (reg) {
3794 /* m-series only registers */
3795 case NITIO_G0_CNT_MODE:
3796 case NITIO_G1_CNT_MODE:
3797 case NITIO_G0_GATE2:
3798 case NITIO_G1_GATE2:
3799 case NITIO_G0_DMA_CFG:
3800 case NITIO_G1_DMA_CFG:
3801 case NITIO_G0_ABZ:
3802 case NITIO_G1_ABZ:
3803 ni_writew(dev, bits, stc_register);
3804 break;
3805
3806 /* 32 bit registers */
3807 case NITIO_G0_LOADA:
3808 case NITIO_G1_LOADA:
3809 case NITIO_G0_LOADB:
3810 case NITIO_G1_LOADB:
3811 ni_stc_writel(dev, bits, stc_register);
3812 break;
3813
3814 /* 16 bit registers */
3815 case NITIO_G0_INT_ENA:
3816 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
3817 ni_set_bitfield(dev, stc_register,
3818 gpct_interrupt_a_enable_mask, bits);
3819 break;
3820 case NITIO_G1_INT_ENA:
3821 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
3822 ni_set_bitfield(dev, stc_register,
3823 gpct_interrupt_b_enable_mask, bits);
3824 break;
3825 case NITIO_G01_RESET:
3826 BUG_ON(bits & ~(NISTC_RESET_G0 | NISTC_RESET_G1));
3827 /* fall-through */
3828 default:
3829 ni_stc_writew(dev, bits, stc_register);
3830 }
3831 }
3832
3833 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
3834 enum ni_gpct_register reg)
3835 {
3836 struct comedi_device *dev = counter->counter_dev->dev;
3837 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3838
3839 if (stc_register == 0)
3840 return 0;
3841
3842 switch (reg) {
3843 /* m-series only registers */
3844 case NITIO_G0_DMA_STATUS:
3845 case NITIO_G1_DMA_STATUS:
3846 return ni_readw(dev, stc_register);
3847
3848 /* 32 bit registers */
3849 case NITIO_G0_HW_SAVE:
3850 case NITIO_G1_HW_SAVE:
3851 case NITIO_G0_SW_SAVE:
3852 case NITIO_G1_SW_SAVE:
3853 return ni_stc_readl(dev, stc_register);
3854
3855 /* 16 bit registers */
3856 default:
3857 return ni_stc_readw(dev, stc_register);
3858 }
3859 }
3860
3861 static int ni_freq_out_insn_read(struct comedi_device *dev,
3862 struct comedi_subdevice *s,
3863 struct comedi_insn *insn,
3864 unsigned int *data)
3865 {
3866 struct ni_private *devpriv = dev->private;
3867 unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
3868 int i;
3869
3870 for (i = 0; i < insn->n; i++)
3871 data[i] = val;
3872
3873 return insn->n;
3874 }
3875
3876 static int ni_freq_out_insn_write(struct comedi_device *dev,
3877 struct comedi_subdevice *s,
3878 struct comedi_insn *insn,
3879 unsigned int *data)
3880 {
3881 struct ni_private *devpriv = dev->private;
3882
3883 if (insn->n) {
3884 unsigned int val = data[insn->n - 1];
3885
3886 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
3887 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3888 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
3889
3890 /* use the last data value to set the fout divider */
3891 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
3892
3893 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
3894 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3895 }
3896 return insn->n;
3897 }
3898
3899 static int ni_freq_out_insn_config(struct comedi_device *dev,
3900 struct comedi_subdevice *s,
3901 struct comedi_insn *insn,
3902 unsigned int *data)
3903 {
3904 struct ni_private *devpriv = dev->private;
3905
3906 switch (data[0]) {
3907 case INSN_CONFIG_SET_CLOCK_SRC:
3908 switch (data[1]) {
3909 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
3910 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
3911 break;
3912 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
3913 devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
3914 break;
3915 default:
3916 return -EINVAL;
3917 }
3918 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3919 break;
3920 case INSN_CONFIG_GET_CLOCK_SRC:
3921 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
3922 data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
3923 data[2] = TIMEBASE_2_NS;
3924 } else {
3925 data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
3926 data[2] = TIMEBASE_1_NS * 2;
3927 }
3928 break;
3929 default:
3930 return -EINVAL;
3931 }
3932 return insn->n;
3933 }
3934
3935 static int ni_8255_callback(struct comedi_device *dev,
3936 int dir, int port, int data, unsigned long iobase)
3937 {
3938 if (dir) {
3939 ni_writeb(dev, data, iobase + 2 * port);
3940 return 0;
3941 }
3942
3943 return ni_readb(dev, iobase + 2 * port);
3944 }
3945
3946 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
3947 {
3948 struct ni_private *devpriv = dev->private;
3949
3950 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
3951 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
3952 return 3;
3953 }
3954
3955 static int ni_m_series_pwm_config(struct comedi_device *dev,
3956 struct comedi_subdevice *s,
3957 struct comedi_insn *insn,
3958 unsigned int *data)
3959 {
3960 struct ni_private *devpriv = dev->private;
3961 unsigned up_count, down_count;
3962
3963 switch (data[0]) {
3964 case INSN_CONFIG_PWM_OUTPUT:
3965 switch (data[1]) {
3966 case CMDF_ROUND_NEAREST:
3967 up_count =
3968 (data[2] +
3969 devpriv->clock_ns / 2) / devpriv->clock_ns;
3970 break;
3971 case CMDF_ROUND_DOWN:
3972 up_count = data[2] / devpriv->clock_ns;
3973 break;
3974 case CMDF_ROUND_UP:
3975 up_count =
3976 (data[2] + devpriv->clock_ns -
3977 1) / devpriv->clock_ns;
3978 break;
3979 default:
3980 return -EINVAL;
3981 }
3982 switch (data[3]) {
3983 case CMDF_ROUND_NEAREST:
3984 down_count =
3985 (data[4] +
3986 devpriv->clock_ns / 2) / devpriv->clock_ns;
3987 break;
3988 case CMDF_ROUND_DOWN:
3989 down_count = data[4] / devpriv->clock_ns;
3990 break;
3991 case CMDF_ROUND_UP:
3992 down_count =
3993 (data[4] + devpriv->clock_ns -
3994 1) / devpriv->clock_ns;
3995 break;
3996 default:
3997 return -EINVAL;
3998 }
3999 if (up_count * devpriv->clock_ns != data[2] ||
4000 down_count * devpriv->clock_ns != data[4]) {
4001 data[2] = up_count * devpriv->clock_ns;
4002 data[4] = down_count * devpriv->clock_ns;
4003 return -EAGAIN;
4004 }
4005 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
4006 NI_M_CAL_PWM_LOW_TIME(down_count),
4007 NI_M_CAL_PWM_REG);
4008 devpriv->pwm_up_count = up_count;
4009 devpriv->pwm_down_count = down_count;
4010 return 5;
4011 case INSN_CONFIG_GET_PWM_OUTPUT:
4012 return ni_get_pwm_config(dev, data);
4013 default:
4014 return -EINVAL;
4015 }
4016 return 0;
4017 }
4018
4019 static int ni_6143_pwm_config(struct comedi_device *dev,
4020 struct comedi_subdevice *s,
4021 struct comedi_insn *insn,
4022 unsigned int *data)
4023 {
4024 struct ni_private *devpriv = dev->private;
4025 unsigned up_count, down_count;
4026
4027 switch (data[0]) {
4028 case INSN_CONFIG_PWM_OUTPUT:
4029 switch (data[1]) {
4030 case CMDF_ROUND_NEAREST:
4031 up_count =
4032 (data[2] +
4033 devpriv->clock_ns / 2) / devpriv->clock_ns;
4034 break;
4035 case CMDF_ROUND_DOWN:
4036 up_count = data[2] / devpriv->clock_ns;
4037 break;
4038 case CMDF_ROUND_UP:
4039 up_count =
4040 (data[2] + devpriv->clock_ns -
4041 1) / devpriv->clock_ns;
4042 break;
4043 default:
4044 return -EINVAL;
4045 }
4046 switch (data[3]) {
4047 case CMDF_ROUND_NEAREST:
4048 down_count =
4049 (data[4] +
4050 devpriv->clock_ns / 2) / devpriv->clock_ns;
4051 break;
4052 case CMDF_ROUND_DOWN:
4053 down_count = data[4] / devpriv->clock_ns;
4054 break;
4055 case CMDF_ROUND_UP:
4056 down_count =
4057 (data[4] + devpriv->clock_ns -
4058 1) / devpriv->clock_ns;
4059 break;
4060 default:
4061 return -EINVAL;
4062 }
4063 if (up_count * devpriv->clock_ns != data[2] ||
4064 down_count * devpriv->clock_ns != data[4]) {
4065 data[2] = up_count * devpriv->clock_ns;
4066 data[4] = down_count * devpriv->clock_ns;
4067 return -EAGAIN;
4068 }
4069 ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG);
4070 devpriv->pwm_up_count = up_count;
4071 ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG);
4072 devpriv->pwm_down_count = down_count;
4073 return 5;
4074 case INSN_CONFIG_GET_PWM_OUTPUT:
4075 return ni_get_pwm_config(dev, data);
4076 default:
4077 return -EINVAL;
4078 }
4079 return 0;
4080 }
4081
4082 static int pack_mb88341(int addr, int val, int *bitstring)
4083 {
4084 /*
4085 Fujitsu MB 88341
4086 Note that address bits are reversed. Thanks to
4087 Ingo Keen for noticing this.
4088
4089 Note also that the 88341 expects address values from
4090 1-12, whereas we use channel numbers 0-11. The NI
4091 docs use 1-12, also, so be careful here.
4092 */
4093 addr++;
4094 *bitstring = ((addr & 0x1) << 11) |
4095 ((addr & 0x2) << 9) |
4096 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4097 return 12;
4098 }
4099
4100 static int pack_dac8800(int addr, int val, int *bitstring)
4101 {
4102 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4103 return 11;
4104 }
4105
4106 static int pack_dac8043(int addr, int val, int *bitstring)
4107 {
4108 *bitstring = val & 0xfff;
4109 return 12;
4110 }
4111
4112 static int pack_ad8522(int addr, int val, int *bitstring)
4113 {
4114 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4115 return 16;
4116 }
4117
4118 static int pack_ad8804(int addr, int val, int *bitstring)
4119 {
4120 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4121 return 12;
4122 }
4123
4124 static int pack_ad8842(int addr, int val, int *bitstring)
4125 {
4126 *bitstring = ((addr + 1) << 8) | (val & 0xff);
4127 return 12;
4128 }
4129
4130 struct caldac_struct {
4131 int n_chans;
4132 int n_bits;
4133 int (*packbits)(int, int, int *);
4134 };
4135
4136 static struct caldac_struct caldacs[] = {
4137 [mb88341] = {12, 8, pack_mb88341},
4138 [dac8800] = {8, 8, pack_dac8800},
4139 [dac8043] = {1, 12, pack_dac8043},
4140 [ad8522] = {2, 12, pack_ad8522},
4141 [ad8804] = {12, 8, pack_ad8804},
4142 [ad8842] = {8, 8, pack_ad8842},
4143 [ad8804_debug] = {16, 8, pack_ad8804},
4144 };
4145
4146 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4147 {
4148 const struct ni_board_struct *board = dev->board_ptr;
4149 struct ni_private *devpriv = dev->private;
4150 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4151 unsigned int cmd;
4152 int i;
4153 int type;
4154
4155 if (devpriv->caldacs[addr] == val)
4156 return;
4157 devpriv->caldacs[addr] = val;
4158
4159 for (i = 0; i < 3; i++) {
4160 type = board->caldac[i];
4161 if (type == caldac_none)
4162 break;
4163 if (addr < caldacs[type].n_chans) {
4164 bits = caldacs[type].packbits(addr, val, &bitstring);
4165 loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
4166 break;
4167 }
4168 addr -= caldacs[type].n_chans;
4169 }
4170
4171 /* bits will be 0 if there is no caldac for the given addr */
4172 if (bits == 0)
4173 return;
4174
4175 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4176 cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4177 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4178 udelay(1);
4179 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4180 udelay(1);
4181 }
4182 ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
4183 udelay(1);
4184 ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4185 }
4186
4187 static int ni_calib_insn_write(struct comedi_device *dev,
4188 struct comedi_subdevice *s,
4189 struct comedi_insn *insn,
4190 unsigned int *data)
4191 {
4192 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4193
4194 return 1;
4195 }
4196
4197 static int ni_calib_insn_read(struct comedi_device *dev,
4198 struct comedi_subdevice *s,
4199 struct comedi_insn *insn,
4200 unsigned int *data)
4201 {
4202 struct ni_private *devpriv = dev->private;
4203
4204 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4205
4206 return 1;
4207 }
4208
4209 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4210 {
4211 const struct ni_board_struct *board = dev->board_ptr;
4212 struct ni_private *devpriv = dev->private;
4213 int i, j;
4214 int n_dacs;
4215 int n_chans = 0;
4216 int n_bits;
4217 int diffbits = 0;
4218 int type;
4219 int chan;
4220
4221 type = board->caldac[0];
4222 if (type == caldac_none)
4223 return;
4224 n_bits = caldacs[type].n_bits;
4225 for (i = 0; i < 3; i++) {
4226 type = board->caldac[i];
4227 if (type == caldac_none)
4228 break;
4229 if (caldacs[type].n_bits != n_bits)
4230 diffbits = 1;
4231 n_chans += caldacs[type].n_chans;
4232 }
4233 n_dacs = i;
4234 s->n_chan = n_chans;
4235
4236 if (diffbits) {
4237 unsigned int *maxdata_list;
4238
4239 if (n_chans > MAX_N_CALDACS)
4240 dev_err(dev->class_dev,
4241 "BUG! MAX_N_CALDACS too small\n");
4242 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4243 chan = 0;
4244 for (i = 0; i < n_dacs; i++) {
4245 type = board->caldac[i];
4246 for (j = 0; j < caldacs[type].n_chans; j++) {
4247 maxdata_list[chan] =
4248 (1 << caldacs[type].n_bits) - 1;
4249 chan++;
4250 }
4251 }
4252
4253 for (chan = 0; chan < s->n_chan; chan++)
4254 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4255 } else {
4256 type = board->caldac[0];
4257 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4258
4259 for (chan = 0; chan < s->n_chan; chan++)
4260 ni_write_caldac(dev, i, s->maxdata / 2);
4261 }
4262 }
4263
4264 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4265 {
4266 unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4267 int bit;
4268 int bitstring;
4269
4270 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4271 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4272 for (bit = 0x8000; bit; bit >>= 1) {
4273 if (bit & bitstring)
4274 cmd |= NI_E_SERIAL_CMD_SDATA;
4275 else
4276 cmd &= ~NI_E_SERIAL_CMD_SDATA;
4277
4278 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4279 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4280 }
4281 cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4282 bitstring = 0;
4283 for (bit = 0x80; bit; bit >>= 1) {
4284 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4285 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4286 if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4287 bitstring |= bit;
4288 }
4289 ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4290
4291 return bitstring;
4292 }
4293
4294 static int ni_eeprom_insn_read(struct comedi_device *dev,
4295 struct comedi_subdevice *s,
4296 struct comedi_insn *insn,
4297 unsigned int *data)
4298 {
4299 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4300
4301 return 1;
4302 }
4303
4304 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4305 struct comedi_subdevice *s,
4306 struct comedi_insn *insn,
4307 unsigned int *data)
4308 {
4309 struct ni_private *devpriv = dev->private;
4310
4311 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4312
4313 return 1;
4314 }
4315
4316 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
4317 unsigned chan)
4318 {
4319 /* pre-m-series boards have fixed signals on pfi pins */
4320 switch (chan) {
4321 case 0:
4322 return NI_PFI_OUTPUT_AI_START1;
4323 case 1:
4324 return NI_PFI_OUTPUT_AI_START2;
4325 case 2:
4326 return NI_PFI_OUTPUT_AI_CONVERT;
4327 case 3:
4328 return NI_PFI_OUTPUT_G_SRC1;
4329 case 4:
4330 return NI_PFI_OUTPUT_G_GATE1;
4331 case 5:
4332 return NI_PFI_OUTPUT_AO_UPDATE_N;
4333 case 6:
4334 return NI_PFI_OUTPUT_AO_START1;
4335 case 7:
4336 return NI_PFI_OUTPUT_AI_START_PULSE;
4337 case 8:
4338 return NI_PFI_OUTPUT_G_SRC0;
4339 case 9:
4340 return NI_PFI_OUTPUT_G_GATE0;
4341 default:
4342 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4343 break;
4344 }
4345 return 0;
4346 }
4347
4348 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4349 unsigned chan, unsigned source)
4350 {
4351 /* pre-m-series boards have fixed signals on pfi pins */
4352 if (source != ni_old_get_pfi_routing(dev, chan))
4353 return -EINVAL;
4354 return 2;
4355 }
4356
4357 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
4358 unsigned chan)
4359 {
4360 struct ni_private *devpriv = dev->private;
4361 const unsigned array_offset = chan / 3;
4362
4363 return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4364 devpriv->pfi_output_select_reg[array_offset]);
4365 }
4366
4367 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4368 unsigned chan, unsigned source)
4369 {
4370 struct ni_private *devpriv = dev->private;
4371 unsigned index = chan / 3;
4372 unsigned short val = devpriv->pfi_output_select_reg[index];
4373
4374 if ((source & 0x1f) != source)
4375 return -EINVAL;
4376
4377 val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4378 val |= NI_M_PFI_OUT_SEL(chan, source);
4379 ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4380 devpriv->pfi_output_select_reg[index] = val;
4381
4382 return 2;
4383 }
4384
4385 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
4386 {
4387 struct ni_private *devpriv = dev->private;
4388
4389 return (devpriv->is_m_series)
4390 ? ni_m_series_get_pfi_routing(dev, chan)
4391 : ni_old_get_pfi_routing(dev, chan);
4392 }
4393
4394 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
4395 unsigned source)
4396 {
4397 struct ni_private *devpriv = dev->private;
4398
4399 return (devpriv->is_m_series)
4400 ? ni_m_series_set_pfi_routing(dev, chan, source)
4401 : ni_old_set_pfi_routing(dev, chan, source);
4402 }
4403
4404 static int ni_config_filter(struct comedi_device *dev,
4405 unsigned pfi_channel,
4406 enum ni_pfi_filter_select filter)
4407 {
4408 struct ni_private *devpriv = dev->private;
4409 unsigned bits;
4410
4411 if (!devpriv->is_m_series)
4412 return -ENOTSUPP;
4413
4414 bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4415 bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel);
4416 bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter);
4417 ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4418 return 0;
4419 }
4420
4421 static int ni_pfi_insn_config(struct comedi_device *dev,
4422 struct comedi_subdevice *s,
4423 struct comedi_insn *insn,
4424 unsigned int *data)
4425 {
4426 struct ni_private *devpriv = dev->private;
4427 unsigned int chan;
4428
4429 if (insn->n < 1)
4430 return -EINVAL;
4431
4432 chan = CR_CHAN(insn->chanspec);
4433
4434 switch (data[0]) {
4435 case COMEDI_OUTPUT:
4436 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 1);
4437 break;
4438 case COMEDI_INPUT:
4439 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 0);
4440 break;
4441 case INSN_CONFIG_DIO_QUERY:
4442 data[1] =
4443 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4444 COMEDI_OUTPUT : COMEDI_INPUT;
4445 return 0;
4446 case INSN_CONFIG_SET_ROUTING:
4447 return ni_set_pfi_routing(dev, chan, data[1]);
4448 case INSN_CONFIG_GET_ROUTING:
4449 data[1] = ni_get_pfi_routing(dev, chan);
4450 break;
4451 case INSN_CONFIG_FILTER:
4452 return ni_config_filter(dev, chan, data[1]);
4453 default:
4454 return -EINVAL;
4455 }
4456 return 0;
4457 }
4458
4459 static int ni_pfi_insn_bits(struct comedi_device *dev,
4460 struct comedi_subdevice *s,
4461 struct comedi_insn *insn,
4462 unsigned int *data)
4463 {
4464 struct ni_private *devpriv = dev->private;
4465
4466 if (!devpriv->is_m_series)
4467 return -ENOTSUPP;
4468
4469 if (comedi_dio_update_state(s, data))
4470 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4471
4472 data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4473
4474 return insn->n;
4475 }
4476
4477 static int cs5529_wait_for_idle(struct comedi_device *dev)
4478 {
4479 unsigned short status;
4480 const int timeout = HZ;
4481 int i;
4482
4483 for (i = 0; i < timeout; i++) {
4484 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4485 if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
4486 break;
4487 set_current_state(TASK_INTERRUPTIBLE);
4488 if (schedule_timeout(1))
4489 return -EIO;
4490 }
4491 if (i == timeout) {
4492 dev_err(dev->class_dev, "timeout\n");
4493 return -ETIME;
4494 }
4495 return 0;
4496 }
4497
4498 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4499 {
4500 static const int timeout = 100;
4501 int i;
4502
4503 ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
4504 /* give time for command to start being serially clocked into cs5529.
4505 * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
4506 * set before we exit this function.
4507 */
4508 for (i = 0; i < timeout; i++) {
4509 if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
4510 NI67XX_CAL_STATUS_BUSY)
4511 break;
4512 udelay(1);
4513 }
4514 if (i == timeout)
4515 dev_err(dev->class_dev,
4516 "possible problem - never saw adc go busy?\n");
4517 }
4518
4519 static int cs5529_do_conversion(struct comedi_device *dev,
4520 unsigned short *data)
4521 {
4522 int retval;
4523 unsigned short status;
4524
4525 cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV);
4526 retval = cs5529_wait_for_idle(dev);
4527 if (retval) {
4528 dev_err(dev->class_dev,
4529 "timeout or signal in cs5529_do_conversion()\n");
4530 return -ETIME;
4531 }
4532 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4533 if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
4534 dev_err(dev->class_dev,
4535 "cs5529 conversion error, status CSS_OSC_DETECT\n");
4536 return -EIO;
4537 }
4538 if (status & NI67XX_CAL_STATUS_OVERRANGE) {
4539 dev_err(dev->class_dev,
4540 "cs5529 conversion error, overrange (ignoring)\n");
4541 }
4542 if (data) {
4543 *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
4544 /* cs5529 returns 16 bit signed data in bipolar mode */
4545 *data ^= (1 << 15);
4546 }
4547 return 0;
4548 }
4549
4550 static int cs5529_ai_insn_read(struct comedi_device *dev,
4551 struct comedi_subdevice *s,
4552 struct comedi_insn *insn,
4553 unsigned int *data)
4554 {
4555 int n, retval;
4556 unsigned short sample;
4557 unsigned int channel_select;
4558 const unsigned int INTERNAL_REF = 0x1000;
4559
4560 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
4561 * do nothing. bit 12 seems to chooses internal reference voltage, bit
4562 * 13 causes the adc input to go overrange (maybe reads external reference?) */
4563 if (insn->chanspec & CR_ALT_SOURCE)
4564 channel_select = INTERNAL_REF;
4565 else
4566 channel_select = CR_CHAN(insn->chanspec);
4567 ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
4568
4569 for (n = 0; n < insn->n; n++) {
4570 retval = cs5529_do_conversion(dev, &sample);
4571 if (retval < 0)
4572 return retval;
4573 data[n] = sample;
4574 }
4575 return insn->n;
4576 }
4577
4578 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4579 unsigned int reg_select_bits)
4580 {
4581 ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
4582 ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
4583 reg_select_bits &= CS5529_CMD_REG_MASK;
4584 cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
4585 if (cs5529_wait_for_idle(dev))
4586 dev_err(dev->class_dev,
4587 "timeout or signal in %s\n", __func__);
4588 }
4589
4590 static int init_cs5529(struct comedi_device *dev)
4591 {
4592 unsigned int config_bits = CS5529_CFG_PORT_FLAG |
4593 CS5529_CFG_WORD_RATE_2180;
4594
4595 #if 1
4596 /* do self-calibration */
4597 cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF,
4598 CS5529_CFG_REG);
4599 /* need to force a conversion for calibration to run */
4600 cs5529_do_conversion(dev, NULL);
4601 #else
4602 /* force gain calibration to 1 */
4603 cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG);
4604 cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF,
4605 CS5529_CFG_REG);
4606 if (cs5529_wait_for_idle(dev))
4607 dev_err(dev->class_dev,
4608 "timeout or signal in %s\n", __func__);
4609 #endif
4610 return 0;
4611 }
4612
4613 /*
4614 * Find best multiplier/divider to try and get the PLL running at 80 MHz
4615 * given an arbitrary frequency input clock.
4616 */
4617 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4618 unsigned *freq_divider,
4619 unsigned *freq_multiplier,
4620 unsigned *actual_period_ns)
4621 {
4622 unsigned div;
4623 unsigned best_div = 1;
4624 unsigned mult;
4625 unsigned best_mult = 1;
4626 static const unsigned pico_per_nano = 1000;
4627
4628 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4629 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4630 * 20 MHz for most timing clocks */
4631 static const unsigned target_picosec = 12500;
4632 static const unsigned fudge_factor_80_to_20Mhz = 4;
4633 int best_period_picosec = 0;
4634
4635 for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4636 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4637 unsigned new_period_ps =
4638 (reference_picosec * div) / mult;
4639 if (abs(new_period_ps - target_picosec) <
4640 abs(best_period_picosec - target_picosec)) {
4641 best_period_picosec = new_period_ps;
4642 best_div = div;
4643 best_mult = mult;
4644 }
4645 }
4646 }
4647 if (best_period_picosec == 0)
4648 return -EIO;
4649
4650 *freq_divider = best_div;
4651 *freq_multiplier = best_mult;
4652 *actual_period_ns =
4653 (best_period_picosec * fudge_factor_80_to_20Mhz +
4654 (pico_per_nano / 2)) / pico_per_nano;
4655 return 0;
4656 }
4657
4658 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4659 unsigned source, unsigned period_ns)
4660 {
4661 struct ni_private *devpriv = dev->private;
4662 static const unsigned min_period_ns = 50;
4663 static const unsigned max_period_ns = 1000;
4664 static const unsigned timeout = 1000;
4665 unsigned pll_control_bits;
4666 unsigned freq_divider;
4667 unsigned freq_multiplier;
4668 unsigned rtsi;
4669 unsigned i;
4670 int retval;
4671
4672 if (source == NI_MIO_PLL_PXI10_CLOCK)
4673 period_ns = 100;
4674 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
4675 if (period_ns < min_period_ns || period_ns > max_period_ns) {
4676 dev_err(dev->class_dev,
4677 "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4678 __func__, min_period_ns, max_period_ns);
4679 return -EINVAL;
4680 }
4681 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4682 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4683 NISTC_RTSI_TRIG_DIR_REG);
4684 pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4685 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4686 NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4687 devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4688 switch (source) {
4689 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4690 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4691 break;
4692 case NI_MIO_PLL_PXI10_CLOCK:
4693 /* pxi clock is 10MHz */
4694 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4695 break;
4696 default:
4697 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4698 if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4699 devpriv->clock_and_fout2 |=
4700 NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4701 break;
4702 }
4703 }
4704 if (rtsi > NI_M_MAX_RTSI_CHAN)
4705 return -EINVAL;
4706 break;
4707 }
4708 retval = ni_mseries_get_pll_parameters(period_ns,
4709 &freq_divider,
4710 &freq_multiplier,
4711 &devpriv->clock_ns);
4712 if (retval < 0) {
4713 dev_err(dev->class_dev,
4714 "bug, failed to find pll parameters\n");
4715 return retval;
4716 }
4717
4718 ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4719 pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4720 NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4721
4722 ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4723 devpriv->clock_source = source;
4724 /* it seems to typically take a few hundred microseconds for PLL to lock */
4725 for (i = 0; i < timeout; ++i) {
4726 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4727 break;
4728 udelay(1);
4729 }
4730 if (i == timeout) {
4731 dev_err(dev->class_dev,
4732 "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4733 __func__, source, period_ns);
4734 return -ETIMEDOUT;
4735 }
4736 return 3;
4737 }
4738
4739 static int ni_set_master_clock(struct comedi_device *dev,
4740 unsigned source, unsigned period_ns)
4741 {
4742 struct ni_private *devpriv = dev->private;
4743
4744 if (source == NI_MIO_INTERNAL_CLOCK) {
4745 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4746 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4747 NISTC_RTSI_TRIG_DIR_REG);
4748 devpriv->clock_ns = TIMEBASE_1_NS;
4749 if (devpriv->is_m_series) {
4750 devpriv->clock_and_fout2 &=
4751 ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4752 NI_M_CLK_FOUT2_TIMEBASE3_PLL);
4753 ni_writew(dev, devpriv->clock_and_fout2,
4754 NI_M_CLK_FOUT2_REG);
4755 ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
4756 }
4757 devpriv->clock_source = source;
4758 } else {
4759 if (devpriv->is_m_series) {
4760 return ni_mseries_set_pll_master_clock(dev, source,
4761 period_ns);
4762 } else {
4763 if (source == NI_MIO_RTSI_CLOCK) {
4764 devpriv->rtsi_trig_direction_reg |=
4765 NISTC_RTSI_TRIG_USE_CLK;
4766 ni_stc_writew(dev,
4767 devpriv->rtsi_trig_direction_reg,
4768 NISTC_RTSI_TRIG_DIR_REG);
4769 if (period_ns == 0) {
4770 dev_err(dev->class_dev,
4771 "we don't handle an unspecified clock period correctly yet, returning error\n");
4772 return -EINVAL;
4773 }
4774 devpriv->clock_ns = period_ns;
4775 devpriv->clock_source = source;
4776 } else {
4777 return -EINVAL;
4778 }
4779 }
4780 }
4781 return 3;
4782 }
4783
4784 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
4785 unsigned chan, unsigned source)
4786 {
4787 struct ni_private *devpriv = dev->private;
4788
4789 if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4790 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4791 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
4792 return 1;
4793
4794 dev_err(dev->class_dev,
4795 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
4796 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
4797 return 0;
4798 }
4799 return 0;
4800 }
4801 switch (source) {
4802 case NI_RTSI_OUTPUT_ADR_START1:
4803 case NI_RTSI_OUTPUT_ADR_START2:
4804 case NI_RTSI_OUTPUT_SCLKG:
4805 case NI_RTSI_OUTPUT_DACUPDN:
4806 case NI_RTSI_OUTPUT_DA_START1:
4807 case NI_RTSI_OUTPUT_G_SRC0:
4808 case NI_RTSI_OUTPUT_G_GATE0:
4809 case NI_RTSI_OUTPUT_RGOUT0:
4810 case NI_RTSI_OUTPUT_RTSI_BRD_0:
4811 return 1;
4812 case NI_RTSI_OUTPUT_RTSI_OSC:
4813 return (devpriv->is_m_series) ? 1 : 0;
4814 default:
4815 return 0;
4816 }
4817 }
4818
4819 static int ni_set_rtsi_routing(struct comedi_device *dev,
4820 unsigned chan, unsigned src)
4821 {
4822 struct ni_private *devpriv = dev->private;
4823
4824 if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
4825 return -EINVAL;
4826 if (chan < 4) {
4827 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
4828 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
4829 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4830 NISTC_RTSI_TRIGA_OUT_REG);
4831 } else if (chan < 8) {
4832 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
4833 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
4834 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4835 NISTC_RTSI_TRIGB_OUT_REG);
4836 }
4837 return 2;
4838 }
4839
4840 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
4841 {
4842 struct ni_private *devpriv = dev->private;
4843
4844 if (chan < 4) {
4845 return NISTC_RTSI_TRIG_TO_SRC(chan,
4846 devpriv->rtsi_trig_a_output_reg);
4847 } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4848 return NISTC_RTSI_TRIG_TO_SRC(chan,
4849 devpriv->rtsi_trig_b_output_reg);
4850 } else {
4851 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN)
4852 return NI_RTSI_OUTPUT_RTSI_OSC;
4853 dev_err(dev->class_dev, "bug! should never get here?\n");
4854 return 0;
4855 }
4856 }
4857
4858 static int ni_rtsi_insn_config(struct comedi_device *dev,
4859 struct comedi_subdevice *s,
4860 struct comedi_insn *insn,
4861 unsigned int *data)
4862 {
4863 struct ni_private *devpriv = dev->private;
4864 unsigned int chan = CR_CHAN(insn->chanspec);
4865 unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
4866
4867 switch (data[0]) {
4868 case INSN_CONFIG_DIO_OUTPUT:
4869 if (chan < max_chan) {
4870 devpriv->rtsi_trig_direction_reg |=
4871 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
4872 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4873 devpriv->rtsi_trig_direction_reg |=
4874 NISTC_RTSI_TRIG_DRV_CLK;
4875 }
4876 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4877 NISTC_RTSI_TRIG_DIR_REG);
4878 break;
4879 case INSN_CONFIG_DIO_INPUT:
4880 if (chan < max_chan) {
4881 devpriv->rtsi_trig_direction_reg &=
4882 ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
4883 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4884 devpriv->rtsi_trig_direction_reg &=
4885 ~NISTC_RTSI_TRIG_DRV_CLK;
4886 }
4887 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4888 NISTC_RTSI_TRIG_DIR_REG);
4889 break;
4890 case INSN_CONFIG_DIO_QUERY:
4891 if (chan < max_chan) {
4892 data[1] =
4893 (devpriv->rtsi_trig_direction_reg &
4894 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
4895 ? INSN_CONFIG_DIO_OUTPUT
4896 : INSN_CONFIG_DIO_INPUT;
4897 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4898 data[1] = (devpriv->rtsi_trig_direction_reg &
4899 NISTC_RTSI_TRIG_DRV_CLK)
4900 ? INSN_CONFIG_DIO_OUTPUT
4901 : INSN_CONFIG_DIO_INPUT;
4902 }
4903 return 2;
4904 case INSN_CONFIG_SET_CLOCK_SRC:
4905 return ni_set_master_clock(dev, data[1], data[2]);
4906 case INSN_CONFIG_GET_CLOCK_SRC:
4907 data[1] = devpriv->clock_source;
4908 data[2] = devpriv->clock_ns;
4909 return 3;
4910 case INSN_CONFIG_SET_ROUTING:
4911 return ni_set_rtsi_routing(dev, chan, data[1]);
4912 case INSN_CONFIG_GET_ROUTING:
4913 data[1] = ni_get_rtsi_routing(dev, chan);
4914 return 2;
4915 default:
4916 return -EINVAL;
4917 }
4918 return 1;
4919 }
4920
4921 static int ni_rtsi_insn_bits(struct comedi_device *dev,
4922 struct comedi_subdevice *s,
4923 struct comedi_insn *insn,
4924 unsigned int *data)
4925 {
4926 data[1] = 0;
4927
4928 return insn->n;
4929 }
4930
4931 static void ni_rtsi_init(struct comedi_device *dev)
4932 {
4933 struct ni_private *devpriv = dev->private;
4934
4935 /* Initialises the RTSI bus signal switch to a default state */
4936
4937 /*
4938 * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
4939 * to have no effect, at least on pxi-6281, which always uses
4940 * 20MHz rtsi clock frequency
4941 */
4942 devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
4943 /* Set clock mode to internal */
4944 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
4945 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
4946 /* default internal lines routing to RTSI bus lines */
4947 devpriv->rtsi_trig_a_output_reg =
4948 NISTC_RTSI_TRIG(0, NI_RTSI_OUTPUT_ADR_START1) |
4949 NISTC_RTSI_TRIG(1, NI_RTSI_OUTPUT_ADR_START2) |
4950 NISTC_RTSI_TRIG(2, NI_RTSI_OUTPUT_SCLKG) |
4951 NISTC_RTSI_TRIG(3, NI_RTSI_OUTPUT_DACUPDN);
4952 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4953 NISTC_RTSI_TRIGA_OUT_REG);
4954 devpriv->rtsi_trig_b_output_reg =
4955 NISTC_RTSI_TRIG(4, NI_RTSI_OUTPUT_DA_START1) |
4956 NISTC_RTSI_TRIG(5, NI_RTSI_OUTPUT_G_SRC0) |
4957 NISTC_RTSI_TRIG(6, NI_RTSI_OUTPUT_G_GATE0);
4958 if (devpriv->is_m_series)
4959 devpriv->rtsi_trig_b_output_reg |=
4960 NISTC_RTSI_TRIG(7, NI_RTSI_OUTPUT_RTSI_OSC);
4961 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4962 NISTC_RTSI_TRIGB_OUT_REG);
4963
4964 /*
4965 * Sets the source and direction of the 4 on board lines
4966 * ni_stc_writew(dev, 0, NISTC_RTSI_BOARD_REG);
4967 */
4968 }
4969
4970 #ifdef PCIDMA
4971 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
4972 {
4973 struct ni_gpct *counter = s->private;
4974 int retval;
4975
4976 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
4977 COMEDI_INPUT);
4978 if (retval) {
4979 dev_err(dev->class_dev,
4980 "no dma channel available for use by counter\n");
4981 return retval;
4982 }
4983 ni_tio_acknowledge(counter);
4984 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
4985
4986 return ni_tio_cmd(dev, s);
4987 }
4988
4989 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
4990 {
4991 struct ni_gpct *counter = s->private;
4992 int retval;
4993
4994 retval = ni_tio_cancel(counter);
4995 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
4996 ni_release_gpct_mite_channel(dev, counter->counter_index);
4997 return retval;
4998 }
4999 #endif
5000
5001 static irqreturn_t ni_E_interrupt(int irq, void *d)
5002 {
5003 struct comedi_device *dev = d;
5004 unsigned short a_status;
5005 unsigned short b_status;
5006 unsigned int ai_mite_status = 0;
5007 unsigned int ao_mite_status = 0;
5008 unsigned long flags;
5009 #ifdef PCIDMA
5010 struct ni_private *devpriv = dev->private;
5011 struct mite_struct *mite = devpriv->mite;
5012 #endif
5013
5014 if (!dev->attached)
5015 return IRQ_NONE;
5016 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
5017
5018 /* lock to avoid race with comedi_poll */
5019 spin_lock_irqsave(&dev->spinlock, flags);
5020 a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
5021 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
5022 #ifdef PCIDMA
5023 if (mite) {
5024 struct ni_private *devpriv = dev->private;
5025 unsigned long flags_too;
5026
5027 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5028 if (devpriv->ai_mite_chan) {
5029 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
5030 if (ai_mite_status & CHSR_LINKC)
5031 writel(CHOR_CLRLC,
5032 devpriv->mite->mite_io_addr +
5033 MITE_CHOR(devpriv->
5034 ai_mite_chan->channel));
5035 }
5036 if (devpriv->ao_mite_chan) {
5037 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
5038 if (ao_mite_status & CHSR_LINKC)
5039 writel(CHOR_CLRLC,
5040 mite->mite_io_addr +
5041 MITE_CHOR(devpriv->
5042 ao_mite_chan->channel));
5043 }
5044 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5045 }
5046 #endif
5047 ack_a_interrupt(dev, a_status);
5048 ack_b_interrupt(dev, b_status);
5049 if ((a_status & NISTC_AI_STATUS1_INTA) || (ai_mite_status & CHSR_INT))
5050 handle_a_interrupt(dev, a_status, ai_mite_status);
5051 if ((b_status & NISTC_AO_STATUS1_INTB) || (ao_mite_status & CHSR_INT))
5052 handle_b_interrupt(dev, b_status, ao_mite_status);
5053 handle_gpct_interrupt(dev, 0);
5054 handle_gpct_interrupt(dev, 1);
5055 handle_cdio_interrupt(dev);
5056
5057 spin_unlock_irqrestore(&dev->spinlock, flags);
5058 return IRQ_HANDLED;
5059 }
5060
5061 static int ni_alloc_private(struct comedi_device *dev)
5062 {
5063 struct ni_private *devpriv;
5064
5065 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5066 if (!devpriv)
5067 return -ENOMEM;
5068
5069 spin_lock_init(&devpriv->window_lock);
5070 spin_lock_init(&devpriv->soft_reg_copy_lock);
5071 spin_lock_init(&devpriv->mite_channel_lock);
5072
5073 return 0;
5074 }
5075
5076 static int ni_E_init(struct comedi_device *dev,
5077 unsigned interrupt_pin, unsigned irq_polarity)
5078 {
5079 const struct ni_board_struct *board = dev->board_ptr;
5080 struct ni_private *devpriv = dev->private;
5081 struct comedi_subdevice *s;
5082 int ret;
5083 int i;
5084
5085 if (board->n_aochan > MAX_N_AO_CHAN) {
5086 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5087 return -EINVAL;
5088 }
5089
5090 /* initialize clock dividers */
5091 devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
5092 NISTC_CLK_FOUT_SLOW_TIMEBASE |
5093 NISTC_CLK_FOUT_TO_BOARD_DIV2 |
5094 NISTC_CLK_FOUT_TO_BOARD;
5095 if (!devpriv->is_6xxx) {
5096 /* BEAM is this needed for PCI-6143 ?? */
5097 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
5098 NISTC_CLK_FOUT_AO_OUT_DIV2);
5099 }
5100 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
5101
5102 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5103 if (ret)
5104 return ret;
5105
5106 /* Analog Input subdevice */
5107 s = &dev->subdevices[NI_AI_SUBDEV];
5108 if (board->n_adchan) {
5109 s->type = COMEDI_SUBD_AI;
5110 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5111 if (!devpriv->is_611x)
5112 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5113 if (board->ai_maxdata > 0xffff)
5114 s->subdev_flags |= SDF_LSAMPL;
5115 if (devpriv->is_m_series)
5116 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5117 s->n_chan = board->n_adchan;
5118 s->maxdata = board->ai_maxdata;
5119 s->range_table = ni_range_lkup[board->gainlkup];
5120 s->insn_read = ni_ai_insn_read;
5121 s->insn_config = ni_ai_insn_config;
5122 if (dev->irq) {
5123 dev->read_subdev = s;
5124 s->subdev_flags |= SDF_CMD_READ;
5125 s->len_chanlist = 512;
5126 s->do_cmdtest = ni_ai_cmdtest;
5127 s->do_cmd = ni_ai_cmd;
5128 s->cancel = ni_ai_reset;
5129 s->poll = ni_ai_poll;
5130 s->munge = ni_ai_munge;
5131
5132 if (devpriv->mite)
5133 s->async_dma_dir = DMA_FROM_DEVICE;
5134 }
5135
5136 /* reset the analog input configuration */
5137 ni_ai_reset(dev, s);
5138 } else {
5139 s->type = COMEDI_SUBD_UNUSED;
5140 }
5141
5142 /* Analog Output subdevice */
5143 s = &dev->subdevices[NI_AO_SUBDEV];
5144 if (board->n_aochan) {
5145 s->type = COMEDI_SUBD_AO;
5146 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5147 if (devpriv->is_m_series)
5148 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5149 s->n_chan = board->n_aochan;
5150 s->maxdata = board->ao_maxdata;
5151 s->range_table = board->ao_range_table;
5152 s->insn_config = ni_ao_insn_config;
5153 s->insn_write = ni_ao_insn_write;
5154
5155 ret = comedi_alloc_subdev_readback(s);
5156 if (ret)
5157 return ret;
5158
5159 /*
5160 * Along with the IRQ we need either a FIFO or DMA for
5161 * async command support.
5162 */
5163 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5164 dev->write_subdev = s;
5165 s->subdev_flags |= SDF_CMD_WRITE;
5166 s->len_chanlist = s->n_chan;
5167 s->do_cmdtest = ni_ao_cmdtest;
5168 s->do_cmd = ni_ao_cmd;
5169 s->cancel = ni_ao_reset;
5170 if (!devpriv->is_m_series)
5171 s->munge = ni_ao_munge;
5172
5173 if (devpriv->mite)
5174 s->async_dma_dir = DMA_TO_DEVICE;
5175 }
5176
5177 if (devpriv->is_67xx)
5178 init_ao_67xx(dev, s);
5179
5180 /* reset the analog output configuration */
5181 ni_ao_reset(dev, s);
5182 } else {
5183 s->type = COMEDI_SUBD_UNUSED;
5184 }
5185
5186 /* Digital I/O subdevice */
5187 s = &dev->subdevices[NI_DIO_SUBDEV];
5188 s->type = COMEDI_SUBD_DIO;
5189 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5190 s->n_chan = board->has_32dio_chan ? 32 : 8;
5191 s->maxdata = 1;
5192 s->range_table = &range_digital;
5193 if (devpriv->is_m_series) {
5194 s->subdev_flags |= SDF_LSAMPL;
5195 s->insn_bits = ni_m_series_dio_insn_bits;
5196 s->insn_config = ni_m_series_dio_insn_config;
5197 if (dev->irq) {
5198 s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5199 s->len_chanlist = s->n_chan;
5200 s->do_cmdtest = ni_cdio_cmdtest;
5201 s->do_cmd = ni_cdio_cmd;
5202 s->cancel = ni_cdio_cancel;
5203
5204 /* M-series boards use DMA */
5205 s->async_dma_dir = DMA_BIDIRECTIONAL;
5206 }
5207
5208 /* reset DIO and set all channels to inputs */
5209 ni_writel(dev, NI_M_CDO_CMD_RESET |
5210 NI_M_CDI_CMD_RESET,
5211 NI_M_CDIO_CMD_REG);
5212 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
5213 } else {
5214 s->insn_bits = ni_dio_insn_bits;
5215 s->insn_config = ni_dio_insn_config;
5216
5217 /* set all channels to inputs */
5218 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
5219 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
5220 }
5221
5222 /* 8255 device */
5223 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5224 if (board->has_8255) {
5225 ret = subdev_8255_init(dev, s, ni_8255_callback,
5226 NI_E_8255_BASE);
5227 if (ret)
5228 return ret;
5229 } else {
5230 s->type = COMEDI_SUBD_UNUSED;
5231 }
5232
5233 /* formerly general purpose counter/timer device, but no longer used */
5234 s = &dev->subdevices[NI_UNUSED_SUBDEV];
5235 s->type = COMEDI_SUBD_UNUSED;
5236
5237 /* Calibration subdevice */
5238 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5239 s->type = COMEDI_SUBD_CALIB;
5240 s->subdev_flags = SDF_INTERNAL;
5241 s->n_chan = 1;
5242 s->maxdata = 0;
5243 if (devpriv->is_m_series) {
5244 /* internal PWM output used for AI nonlinearity calibration */
5245 s->insn_config = ni_m_series_pwm_config;
5246
5247 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
5248 } else if (devpriv->is_6143) {
5249 /* internal PWM output used for AI nonlinearity calibration */
5250 s->insn_config = ni_6143_pwm_config;
5251 } else {
5252 s->subdev_flags |= SDF_WRITABLE;
5253 s->insn_read = ni_calib_insn_read;
5254 s->insn_write = ni_calib_insn_write;
5255
5256 /* setup the caldacs and find the real n_chan and maxdata */
5257 caldac_setup(dev, s);
5258 }
5259
5260 /* EEPROM subdevice */
5261 s = &dev->subdevices[NI_EEPROM_SUBDEV];
5262 s->type = COMEDI_SUBD_MEMORY;
5263 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5264 s->maxdata = 0xff;
5265 if (devpriv->is_m_series) {
5266 s->n_chan = M_SERIES_EEPROM_SIZE;
5267 s->insn_read = ni_m_series_eeprom_insn_read;
5268 } else {
5269 s->n_chan = 512;
5270 s->insn_read = ni_eeprom_insn_read;
5271 }
5272
5273 /* Digital I/O (PFI) subdevice */
5274 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5275 s->type = COMEDI_SUBD_DIO;
5276 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5277 s->maxdata = 1;
5278 if (devpriv->is_m_series) {
5279 s->n_chan = 16;
5280 s->insn_bits = ni_pfi_insn_bits;
5281
5282 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
5283 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5284 ni_writew(dev, devpriv->pfi_output_select_reg[i],
5285 NI_M_PFI_OUT_SEL_REG(i));
5286 }
5287 } else {
5288 s->n_chan = 10;
5289 }
5290 s->insn_config = ni_pfi_insn_config;
5291
5292 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
5293
5294 /* cs5529 calibration adc */
5295 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5296 if (devpriv->is_67xx) {
5297 s->type = COMEDI_SUBD_AI;
5298 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5299 /* one channel for each analog output channel */
5300 s->n_chan = board->n_aochan;
5301 s->maxdata = (1 << 16) - 1;
5302 s->range_table = &range_unknown; /* XXX */
5303 s->insn_read = cs5529_ai_insn_read;
5304 s->insn_config = NULL;
5305 init_cs5529(dev);
5306 } else {
5307 s->type = COMEDI_SUBD_UNUSED;
5308 }
5309
5310 /* Serial */
5311 s = &dev->subdevices[NI_SERIAL_SUBDEV];
5312 s->type = COMEDI_SUBD_SERIAL;
5313 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5314 s->n_chan = 1;
5315 s->maxdata = 0xff;
5316 s->insn_config = ni_serial_insn_config;
5317 devpriv->serial_interval_ns = 0;
5318 devpriv->serial_hw_mode = 0;
5319
5320 /* RTSI */
5321 s = &dev->subdevices[NI_RTSI_SUBDEV];
5322 s->type = COMEDI_SUBD_DIO;
5323 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5324 s->n_chan = 8;
5325 s->maxdata = 1;
5326 s->insn_bits = ni_rtsi_insn_bits;
5327 s->insn_config = ni_rtsi_insn_config;
5328 ni_rtsi_init(dev);
5329
5330 /* allocate and initialize the gpct counter device */
5331 devpriv->counter_dev = ni_gpct_device_construct(dev,
5332 ni_gpct_write_register,
5333 ni_gpct_read_register,
5334 (devpriv->is_m_series)
5335 ? ni_gpct_variant_m_series
5336 : ni_gpct_variant_e_series,
5337 NUM_GPCT);
5338 if (!devpriv->counter_dev)
5339 return -ENOMEM;
5340
5341 /* Counter (gpct) subdevices */
5342 for (i = 0; i < NUM_GPCT; ++i) {
5343 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5344
5345 /* setup and initialize the counter */
5346 gpct->chip_index = 0;
5347 gpct->counter_index = i;
5348 ni_tio_init_counter(gpct);
5349
5350 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5351 s->type = COMEDI_SUBD_COUNTER;
5352 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5353 s->n_chan = 3;
5354 s->maxdata = (devpriv->is_m_series) ? 0xffffffff
5355 : 0x00ffffff;
5356 s->insn_read = ni_tio_insn_read;
5357 s->insn_write = ni_tio_insn_read;
5358 s->insn_config = ni_tio_insn_config;
5359 #ifdef PCIDMA
5360 if (dev->irq && devpriv->mite) {
5361 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5362 s->len_chanlist = 1;
5363 s->do_cmdtest = ni_tio_cmdtest;
5364 s->do_cmd = ni_gpct_cmd;
5365 s->cancel = ni_gpct_cancel;
5366
5367 s->async_dma_dir = DMA_BIDIRECTIONAL;
5368 }
5369 #endif
5370 s->private = gpct;
5371 }
5372
5373 /* Frequency output subdevice */
5374 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5375 s->type = COMEDI_SUBD_COUNTER;
5376 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5377 s->n_chan = 1;
5378 s->maxdata = 0xf;
5379 s->insn_read = ni_freq_out_insn_read;
5380 s->insn_write = ni_freq_out_insn_write;
5381 s->insn_config = ni_freq_out_insn_config;
5382
5383 if (dev->irq) {
5384 ni_stc_writew(dev,
5385 (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
5386 (NISTC_INT_CTRL_3PIN_INT & 0) |
5387 NISTC_INT_CTRL_INTA_ENA |
5388 NISTC_INT_CTRL_INTB_ENA |
5389 NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
5390 NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
5391 NISTC_INT_CTRL_REG);
5392 }
5393
5394 /* DMA setup */
5395 ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG);
5396 ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG);
5397
5398 if (devpriv->is_6xxx) {
5399 ni_writeb(dev, 0, NI611X_MAGIC_REG);
5400 } else if (devpriv->is_m_series) {
5401 int channel;
5402
5403 for (channel = 0; channel < board->n_aochan; ++channel) {
5404 ni_writeb(dev, 0xf,
5405 NI_M_AO_WAVEFORM_ORDER_REG(channel));
5406 ni_writeb(dev, 0x0,
5407 NI_M_AO_REF_ATTENUATION_REG(channel));
5408 }
5409 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
5410 }
5411
5412 return 0;
5413 }
5414
5415 static void mio_common_detach(struct comedi_device *dev)
5416 {
5417 struct ni_private *devpriv = dev->private;
5418
5419 if (devpriv) {
5420 if (devpriv->counter_dev)
5421 ni_gpct_device_destroy(devpriv->counter_dev);
5422 }
5423 }
Linux kernel - Deliverables
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