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[deliverable/linux.git] / drivers / staging / rtl8192u / r819xU_phy.c
1 #include "r8192U.h"
2 #include "r8192U_hw.h"
3 #include "r819xU_phy.h"
4 #include "r819xU_phyreg.h"
5 #include "r8190_rtl8256.h"
6 #include "r8192U_dm.h"
7 #include "r819xU_firmware_img.h"
8
9 #include "dot11d.h"
10 #include <linux/bitops.h>
11
12 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
13 0,
14 0x085c, /* 2412 1 */
15 0x08dc, /* 2417 2 */
16 0x095c, /* 2422 3 */
17 0x09dc, /* 2427 4 */
18 0x0a5c, /* 2432 5 */
19 0x0adc, /* 2437 6 */
20 0x0b5c, /* 2442 7 */
21 0x0bdc, /* 2447 8 */
22 0x0c5c, /* 2452 9 */
23 0x0cdc, /* 2457 10 */
24 0x0d5c, /* 2462 11 */
25 0x0ddc, /* 2467 12 */
26 0x0e5c, /* 2472 13 */
27 0x0f72, /* 2484 */
28 };
29
30
31 #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
32 #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
33 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
34 #define rtl819XRadioA_Array Rtl8192UsbRadioA_Array
35 #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array
36 #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array
37 #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array
38 #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array
39
40 /******************************************************************************
41 * function: This function reads BB parameters from header file we generate,
42 * and does register read/write
43 * input: u32 bitmask //taget bit pos in the addr to be modified
44 * output: none
45 * return: u32 return the shift bit position of the mask
46 ******************************************************************************/
47 static u32 rtl8192_CalculateBitShift(u32 bitmask)
48 {
49 u32 i;
50
51 i = ffs(bitmask) - 1;
52 return i;
53 }
54
55 /******************************************************************************
56 * function: This function checks different RF type to execute legal judgement.
57 * If RF Path is illegal, we will return false.
58 * input: net_device *dev
59 * u32 eRFPath
60 * output: none
61 * return: 0(illegal, false), 1(legal, true)
62 *****************************************************************************/
63 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
64 {
65 u8 ret = 1;
66 struct r8192_priv *priv = ieee80211_priv(dev);
67
68 if (priv->rf_type == RF_2T4R) {
69 ret = 0;
70 } else if (priv->rf_type == RF_1T2R) {
71 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
72 ret = 1;
73 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
74 ret = 0;
75 }
76 return ret;
77 }
78
79 /******************************************************************************
80 * function: This function sets specific bits to BB register
81 * input: net_device *dev
82 * u32 reg_addr //target addr to be modified
83 * u32 bitmask //taget bit pos to be modified
84 * u32 data //value to be write
85 * output: none
86 * return: none
87 * notice:
88 ******************************************************************************/
89 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask,
90 u32 data)
91 {
92
93 u32 reg, bitshift;
94
95 if (bitmask != bMaskDWord) {
96 read_nic_dword(dev, reg_addr, &reg);
97 bitshift = rtl8192_CalculateBitShift(bitmask);
98 reg &= ~bitmask;
99 reg |= data << bitshift;
100 write_nic_dword(dev, reg_addr, reg);
101 } else {
102 write_nic_dword(dev, reg_addr, data);
103 }
104 }
105
106 /******************************************************************************
107 * function: This function reads specific bits from BB register
108 * input: net_device *dev
109 * u32 reg_addr //target addr to be readback
110 * u32 bitmask //taget bit pos to be readback
111 * output: none
112 * return: u32 data //the readback register value
113 * notice:
114 ******************************************************************************/
115 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask)
116 {
117 u32 reg, bitshift;
118
119 read_nic_dword(dev, reg_addr, &reg);
120 bitshift = rtl8192_CalculateBitShift(bitmask);
121
122 return (reg & bitmask) >> bitshift;
123 }
124
125 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
126 u32 offset);
127
128 static void phy_FwRFSerialWrite(struct net_device *dev,
129 RF90_RADIO_PATH_E eRFPath, u32 offset,
130 u32 data);
131
132 /******************************************************************************
133 * function: This function reads register from RF chip
134 * input: net_device *dev
135 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
136 * u32 offset //target address to be read
137 * output: none
138 * return: u32 readback value
139 * notice: There are three types of serial operations:
140 * (1) Software serial write.
141 * (2)Hardware LSSI-Low Speed Serial Interface.
142 * (3)Hardware HSSI-High speed serial write.
143 * Driver here need to implement (1) and (2)
144 * ---need more spec for this information.
145 ******************************************************************************/
146 static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
147 RF90_RADIO_PATH_E eRFPath, u32 offset)
148 {
149 struct r8192_priv *priv = ieee80211_priv(dev);
150 u32 ret = 0;
151 u32 new_offset = 0;
152 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
153
154 rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
155 /* Make sure RF register offset is correct */
156 offset &= 0x3f;
157
158 /* Switch page for 8256 RF IC */
159 if (priv->rf_chip == RF_8256) {
160 if (offset >= 31) {
161 priv->RfReg0Value[eRFPath] |= 0x140;
162 /* Switch to Reg_Mode2 for Reg 31-45 */
163 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
164 bMaskDWord,
165 priv->RfReg0Value[eRFPath]<<16);
166 /* Modify offset */
167 new_offset = offset - 30;
168 } else if (offset >= 16) {
169 priv->RfReg0Value[eRFPath] |= 0x100;
170 priv->RfReg0Value[eRFPath] &= (~0x40);
171 /* Switch to Reg_Mode1 for Reg16-30 */
172 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
173 bMaskDWord,
174 priv->RfReg0Value[eRFPath]<<16);
175
176 new_offset = offset - 15;
177 } else {
178 new_offset = offset;
179 }
180 } else {
181 RT_TRACE((COMP_PHY|COMP_ERR),
182 "check RF type here, need to be 8256\n");
183 new_offset = offset;
184 }
185 /* Put desired read addr to LSSI control Register */
186 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
187 new_offset);
188 /* Issue a posedge trigger */
189 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
190 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
191
192
193 /* TODO: we should not delay such a long time. Ask for help from SD3 */
194 usleep_range(1000, 1000);
195
196 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
197 bLSSIReadBackData);
198
199
200 /* Switch back to Reg_Mode0 */
201 if (priv->rf_chip == RF_8256) {
202 priv->RfReg0Value[eRFPath] &= 0xebf;
203
204 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
205 priv->RfReg0Value[eRFPath] << 16);
206 }
207
208 return ret;
209 }
210
211 /******************************************************************************
212 * function: This function writes data to RF register
213 * input: net_device *dev
214 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
215 * u32 offset //target address to be written
216 * u32 data //the new register data to be written
217 * output: none
218 * return: none
219 * notice: For RF8256 only.
220 * ===========================================================================
221 * Reg Mode RegCTL[1] RegCTL[0] Note
222 * (Reg00[12]) (Reg00[10])
223 * ===========================================================================
224 * Reg_Mode0 0 x Reg 0 ~ 15(0x0 ~ 0xf)
225 * ---------------------------------------------------------------------------
226 * Reg_Mode1 1 0 Reg 16 ~ 30(0x1 ~ 0xf)
227 * ---------------------------------------------------------------------------
228 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
229 * ---------------------------------------------------------------------------
230 *****************************************************************************/
231 static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
232 RF90_RADIO_PATH_E eRFPath, u32 offset,
233 u32 data)
234 {
235 struct r8192_priv *priv = ieee80211_priv(dev);
236 u32 DataAndAddr = 0, new_offset = 0;
237 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
238
239 offset &= 0x3f;
240 if (priv->rf_chip == RF_8256) {
241
242 if (offset >= 31) {
243 priv->RfReg0Value[eRFPath] |= 0x140;
244 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
245 bMaskDWord,
246 priv->RfReg0Value[eRFPath] << 16);
247 new_offset = offset - 30;
248 } else if (offset >= 16) {
249 priv->RfReg0Value[eRFPath] |= 0x100;
250 priv->RfReg0Value[eRFPath] &= (~0x40);
251 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
252 bMaskDWord,
253 priv->RfReg0Value[eRFPath]<<16);
254 new_offset = offset - 15;
255 } else {
256 new_offset = offset;
257 }
258 } else {
259 RT_TRACE((COMP_PHY|COMP_ERR),
260 "check RF type here, need to be 8256\n");
261 new_offset = offset;
262 }
263
264 /* Put write addr in [5:0] and write data in [31:16] */
265 DataAndAddr = (data<<16) | (new_offset&0x3f);
266
267 /* Write operation */
268 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
269
270
271 if (offset == 0x0)
272 priv->RfReg0Value[eRFPath] = data;
273
274 /* Switch back to Reg_Mode0 */
275 if (priv->rf_chip == RF_8256) {
276 if (offset != 0) {
277 priv->RfReg0Value[eRFPath] &= 0xebf;
278 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
279 bMaskDWord,
280 priv->RfReg0Value[eRFPath] << 16);
281 }
282 }
283 }
284
285 /******************************************************************************
286 * function: This function set specific bits to RF register
287 * input: net_device dev
288 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
289 * u32 reg_addr //target addr to be modified
290 * u32 bitmask //taget bit pos to be modified
291 * u32 data //value to be written
292 * output: none
293 * return: none
294 * notice:
295 *****************************************************************************/
296 void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
297 u32 reg_addr, u32 bitmask, u32 data)
298 {
299 struct r8192_priv *priv = ieee80211_priv(dev);
300 u32 reg, bitshift;
301
302 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
303 return;
304
305 if (priv->Rf_Mode == RF_OP_By_FW) {
306 if (bitmask != bMask12Bits) {
307 /* RF data is 12 bits only */
308 reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
309 bitshift = rtl8192_CalculateBitShift(bitmask);
310 reg &= ~bitmask;
311 reg |= data << bitshift;
312
313 phy_FwRFSerialWrite(dev, eRFPath, reg_addr, reg);
314 } else {
315 phy_FwRFSerialWrite(dev, eRFPath, reg_addr, data);
316 }
317
318 udelay(200);
319
320 } else {
321 if (bitmask != bMask12Bits) {
322 /* RF data is 12 bits only */
323 reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
324 bitshift = rtl8192_CalculateBitShift(bitmask);
325 reg &= ~bitmask;
326 reg |= data << bitshift;
327
328 rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, reg);
329 } else {
330 rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, data);
331 }
332 }
333 }
334
335 /******************************************************************************
336 * function: This function reads specific bits from RF register
337 * input: net_device *dev
338 * u32 reg_addr //target addr to be readback
339 * u32 bitmask //taget bit pos to be readback
340 * output: none
341 * return: u32 data //the readback register value
342 * notice:
343 *****************************************************************************/
344 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
345 u32 reg_addr, u32 bitmask)
346 {
347 u32 reg, bitshift;
348 struct r8192_priv *priv = ieee80211_priv(dev);
349
350
351 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
352 return 0;
353 if (priv->Rf_Mode == RF_OP_By_FW) {
354 reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
355 bitshift = rtl8192_CalculateBitShift(bitmask);
356 reg = (reg & bitmask) >> bitshift;
357 udelay(200);
358 return reg;
359 } else {
360 reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
361 bitshift = rtl8192_CalculateBitShift(bitmask);
362 reg = (reg & bitmask) >> bitshift;
363 return reg;
364 }
365 }
366
367 /******************************************************************************
368 * function: We support firmware to execute RF-R/W.
369 * input: net_device *dev
370 * RF90_RADIO_PATH_E eRFPath
371 * u32 offset
372 * output: none
373 * return: u32
374 * notice:
375 ****************************************************************************/
376 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
377 u32 offset)
378 {
379 u32 reg = 0;
380 u32 data = 0;
381 u8 time = 0;
382 u32 tmp;
383
384 /* Firmware RF Write control.
385 * We can not execute the scheme in the initial step.
386 * Otherwise, RF-R/W will waste much time.
387 * This is only for site survey. */
388 /* 1. Read operation need not insert data. bit 0-11 */
389 /* 2. Write RF register address. bit 12-19 */
390 data |= ((offset&0xFF)<<12);
391 /* 3. Write RF path. bit 20-21 */
392 data |= ((eRFPath&0x3)<<20);
393 /* 4. Set RF read indicator. bit 22=0 */
394 /* 5. Trigger Fw to operate the command. bit 31 */
395 data |= 0x80000000;
396 /* 6. We can not execute read operation if bit 31 is 1. */
397 read_nic_dword(dev, QPNR, &tmp);
398 while (tmp & 0x80000000) {
399 /* If FW can not finish RF-R/W for more than ?? times.
400 We must reset FW. */
401 if (time++ < 100) {
402 udelay(10);
403 read_nic_dword(dev, QPNR, &tmp);
404 } else {
405 break;
406 }
407 }
408 /* 7. Execute read operation. */
409 write_nic_dword(dev, QPNR, data);
410 /* 8. Check if firmware send back RF content. */
411 read_nic_dword(dev, QPNR, &tmp);
412 while (tmp & 0x80000000) {
413 /* If FW can not finish RF-R/W for more than ?? times.
414 We must reset FW. */
415 if (time++ < 100) {
416 udelay(10);
417 read_nic_dword(dev, QPNR, &tmp);
418 } else {
419 return 0;
420 }
421 }
422 read_nic_dword(dev, RF_DATA, &reg);
423
424 return reg;
425 }
426
427 /******************************************************************************
428 * function: We support firmware to execute RF-R/W.
429 * input: net_device *dev
430 * RF90_RADIO_PATH_E eRFPath
431 * u32 offset
432 * u32 data
433 * output: none
434 * return: none
435 * notice:
436 ****************************************************************************/
437 static void phy_FwRFSerialWrite(struct net_device *dev,
438 RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data)
439 {
440 u8 time = 0;
441 u32 tmp;
442
443 /* Firmware RF Write control.
444 * We can not execute the scheme in the initial step.
445 * Otherwise, RF-R/W will waste much time.
446 * This is only for site survey. */
447
448 /* 1. Set driver write bit and 12 bit data. bit 0-11 */
449 /* 2. Write RF register address. bit 12-19 */
450 data |= ((offset&0xFF)<<12);
451 /* 3. Write RF path. bit 20-21 */
452 data |= ((eRFPath&0x3)<<20);
453 /* 4. Set RF write indicator. bit 22=1 */
454 data |= 0x400000;
455 /* 5. Trigger Fw to operate the command. bit 31=1 */
456 data |= 0x80000000;
457
458 /* 6. Write operation. We can not write if bit 31 is 1. */
459 read_nic_dword(dev, QPNR, &tmp);
460 while (tmp & 0x80000000) {
461 /* If FW can not finish RF-R/W for more than ?? times.
462 We must reset FW. */
463 if (time++ < 100) {
464 udelay(10);
465 read_nic_dword(dev, QPNR, &tmp);
466 } else {
467 break;
468 }
469 }
470 /* 7. No matter check bit. We always force the write.
471 Because FW will not accept the command. */
472 write_nic_dword(dev, QPNR, data);
473 /* According to test, we must delay 20us to wait firmware
474 to finish RF write operation. */
475 /* We support delay in firmware side now. */
476 }
477
478 /******************************************************************************
479 * function: This function reads BB parameters from header file we generate,
480 * and do register read/write
481 * input: net_device *dev
482 * output: none
483 * return: none
484 * notice: BB parameters may change all the time, so please make
485 * sure it has been synced with the newest.
486 *****************************************************************************/
487 void rtl8192_phy_configmac(struct net_device *dev)
488 {
489 u32 dwArrayLen = 0, i;
490 u32 *pdwArray = NULL;
491 struct r8192_priv *priv = ieee80211_priv(dev);
492
493 if (priv->btxpowerdata_readfromEEPORM) {
494 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
495 dwArrayLen = MACPHY_Array_PGLength;
496 pdwArray = rtl819XMACPHY_Array_PG;
497
498 } else {
499 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n");
500 dwArrayLen = MACPHY_ArrayLength;
501 pdwArray = rtl819XMACPHY_Array;
502 }
503 for (i = 0; i < dwArrayLen; i = i+3) {
504 if (pdwArray[i] == 0x318)
505 pdwArray[i+2] = 0x00000800;
506
507 RT_TRACE(COMP_DBG,
508 "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n",
509 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
510 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
511 pdwArray[i+2]);
512 }
513 }
514
515 /******************************************************************************
516 * function: This function does dirty work
517 * input: net_device *dev
518 * u8 ConfigType
519 * output: none
520 * return: none
521 * notice: BB parameters may change all the time, so please make
522 * sure it has been synced with the newest.
523 *****************************************************************************/
524 void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
525 {
526 u32 i;
527
528 #ifdef TO_DO_LIST
529 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
530
531 if (Adapter->bInHctTest) {
532 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
533 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
534 Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
535 Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
536 }
537 #endif
538 if (ConfigType == BaseBand_Config_PHY_REG) {
539 for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) {
540 rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i],
541 bMaskDWord,
542 rtl819XPHY_REG_1T2RArray[i+1]);
543 RT_TRACE(COMP_DBG,
544 "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n",
545 i, rtl819XPHY_REG_1T2RArray[i],
546 rtl819XPHY_REG_1T2RArray[i+1]);
547 }
548 } else if (ConfigType == BaseBand_Config_AGC_TAB) {
549 for (i = 0; i < AGCTAB_ArrayLength; i += 2) {
550 rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i],
551 bMaskDWord, rtl819XAGCTAB_Array[i+1]);
552 RT_TRACE(COMP_DBG,
553 "i: %x, rtl819XAGCTAB_Array[0]=%x rtl819XAGCTAB_Array[1]=%x\n",
554 i, rtl819XAGCTAB_Array[i],
555 rtl819XAGCTAB_Array[i+1]);
556 }
557 }
558 }
559
560 /******************************************************************************
561 * function: This function initializes Register definition offset for
562 * Radio Path A/B/C/D
563 * input: net_device *dev
564 * output: none
565 * return: none
566 * notice: Initialization value here is constant and it should never
567 * be changed
568 *****************************************************************************/
569 static void rtl8192_InitBBRFRegDef(struct net_device *dev)
570 {
571 struct r8192_priv *priv = ieee80211_priv(dev);
572
573 /* RF Interface Software Control */
574 /* 16 LSBs if read 32-bit from 0x870 */
575 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
576 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
577 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
578 /* 16 LSBs if read 32-bit from 0x874 */
579 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
580 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
581 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
582
583 /* RF Interface Readback Value */
584 /* 16 LSBs if read 32-bit from 0x8E0 */
585 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
586 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
587 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
588 /* 16 LSBs if read 32-bit from 0x8E4 */
589 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
590 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
591 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
592
593 /* RF Interface Output (and Enable) */
594 /* 16 LSBs if read 32-bit from 0x860 */
595 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
596 /* 16 LSBs if read 32-bit from 0x864 */
597 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
598 /* 16 LSBs if read 32-bit from 0x868 */
599 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
600 /* 16 LSBs if read 32-bit from 0x86C */
601 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
602
603 /* RF Interface (Output and) Enable */
604 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
605 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
606 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
607 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
608 /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */
609 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
610 /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */
611 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
612
613 /* Addr of LSSI. Write RF register by driver */
614 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
615 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
616 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
617 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
618
619 /* RF parameter */
620 /* BB Band Select */
621 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
622 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
623 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
624 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
625
626 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
627 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
628 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
629 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
630 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
631
632 /* Tranceiver A~D HSSI Parameter-1 */
633 /* wire control parameter1 */
634 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
635 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
636 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
637 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
638
639 /* Tranceiver A~D HSSI Parameter-2 */
640 /* wire control parameter2 */
641 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
642 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
643 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
644 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
645
646 /* RF Switch Control */
647 /* TR/Ant switch control */
648 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
649 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
650 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
651 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
652
653 /* AGC control 1 */
654 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
655 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
656 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
657 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
658
659 /* AGC control 2 */
660 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
661 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
662 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
663 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
664
665 /* RX AFE control 1 */
666 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
667 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
668 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
669 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
670
671 /* RX AFE control 1 */
672 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
673 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
674 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
675 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
676
677 /* Tx AFE control 1 */
678 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
679 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
680 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
681 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
682
683 /* Tx AFE control 2 */
684 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
685 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
686 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
687 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
688
689 /* Tranceiver LSSI Readback */
690 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
691 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
692 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
693 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
694 }
695
696 /******************************************************************************
697 * function: This function is to write register and then readback to make
698 * sure whether BB and RF is OK
699 * input: net_device *dev
700 * HW90_BLOCK_E CheckBlock
701 * RF90_RADIO_PATH_E eRFPath //only used when checkblock is
702 * //HW90_BLOCK_RF
703 * output: none
704 * return: return whether BB and RF is ok (0:OK, 1:Fail)
705 * notice: This function may be removed in the ASIC
706 ******************************************************************************/
707 u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock,
708 RF90_RADIO_PATH_E eRFPath)
709 {
710 u8 ret = 0;
711 u32 i, CheckTimes = 4, reg = 0;
712 u32 WriteAddr[4];
713 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
714
715 /* Initialize register address offset to be checked */
716 WriteAddr[HW90_BLOCK_MAC] = 0x100;
717 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
718 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
719 WriteAddr[HW90_BLOCK_RF] = 0x3;
720 RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __func__, CheckBlock);
721 for (i = 0; i < CheckTimes; i++) {
722
723 /* Write data to register and readback */
724 switch (CheckBlock) {
725 case HW90_BLOCK_MAC:
726 RT_TRACE(COMP_ERR,
727 "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
728 break;
729
730 case HW90_BLOCK_PHY0:
731 case HW90_BLOCK_PHY1:
732 write_nic_dword(dev, WriteAddr[CheckBlock],
733 WriteData[i]);
734 read_nic_dword(dev, WriteAddr[CheckBlock], &reg);
735 break;
736
737 case HW90_BLOCK_RF:
738 WriteData[i] &= 0xfff;
739 rtl8192_phy_SetRFReg(dev, eRFPath,
740 WriteAddr[HW90_BLOCK_RF],
741 bMask12Bits, WriteData[i]);
742 /* TODO: we should not delay for such a long time.
743 Ask SD3 */
744 usleep_range(1000, 1000);
745 reg = rtl8192_phy_QueryRFReg(dev, eRFPath,
746 WriteAddr[HW90_BLOCK_RF],
747 bMask12Bits);
748 usleep_range(1000, 1000);
749 break;
750
751 default:
752 ret = 1;
753 break;
754 }
755
756
757 /* Check whether readback data is correct */
758 if (reg != WriteData[i]) {
759 RT_TRACE((COMP_PHY|COMP_ERR),
760 "error reg: %x, WriteData: %x\n",
761 reg, WriteData[i]);
762 ret = 1;
763 break;
764 }
765 }
766
767 return ret;
768 }
769
770 /******************************************************************************
771 * function: This function initializes BB&RF
772 * input: net_device *dev
773 * output: none
774 * return: none
775 * notice: Initialization value may change all the time, so please make
776 * sure it has been synced with the newest.
777 ******************************************************************************/
778 static void rtl8192_BB_Config_ParaFile(struct net_device *dev)
779 {
780 struct r8192_priv *priv = ieee80211_priv(dev);
781 u8 reg_u8 = 0, eCheckItem = 0, status = 0;
782 u32 reg_u32 = 0;
783
784 /**************************************
785 * <1> Initialize BaseBand
786 *************************************/
787
788 /* --set BB Global Reset-- */
789 read_nic_byte(dev, BB_GLOBAL_RESET, &reg_u8);
790 write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT));
791 mdelay(50);
792 /* ---set BB reset Active--- */
793 read_nic_dword(dev, CPU_GEN, &reg_u32);
794 write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST)));
795
796 /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */
797 /* TODO: this function should be removed on ASIC */
798 for (eCheckItem = (HW90_BLOCK_E)HW90_BLOCK_PHY0;
799 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
800 /* don't care RF path */
801 status = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem,
802 (RF90_RADIO_PATH_E)0);
803 if (status != 0) {
804 RT_TRACE((COMP_ERR | COMP_PHY),
805 "PHY_RF8256_Config(): Check PHY%d Fail!!\n",
806 eCheckItem-1);
807 return;
808 }
809 }
810 /* ---- Set CCK and OFDM Block "OFF"---- */
811 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
812 /* ----BB Register Initilazation---- */
813 /* ==m==>Set PHY REG From Header<==m== */
814 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
815
816 /* ----Set BB reset de-Active---- */
817 read_nic_dword(dev, CPU_GEN, &reg_u32);
818 write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST));
819
820 /* ----BB AGC table Initialization---- */
821 /* ==m==>Set PHY REG From Header<==m== */
822 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
823
824 /* ----Enable XSTAL ---- */
825 write_nic_byte_E(dev, 0x5e, 0x00);
826 if (priv->card_8192_version == (u8)VERSION_819xU_A) {
827 /* Antenna gain offset from B/C/D to A */
828 reg_u32 = (priv->AntennaTxPwDiff[1]<<4 |
829 priv->AntennaTxPwDiff[0]);
830 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC),
831 reg_u32);
832
833 /* XSTALLCap */
834 reg_u32 = priv->CrystalCap & 0xf;
835 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap,
836 reg_u32);
837 }
838
839 /* Check if the CCK HighPower is turned ON.
840 This is used to calculate PWDB. */
841 priv->bCckHighPower = (u8)rtl8192_QueryBBReg(dev,
842 rFPGA0_XA_HSSIParameter2,
843 0x200);
844 }
845
846 /******************************************************************************
847 * function: This function initializes BB&RF
848 * input: net_device *dev
849 * output: none
850 * return: none
851 * notice: Initialization value may change all the time, so please make
852 * sure it has been synced with the newest.
853 *****************************************************************************/
854 void rtl8192_BBConfig(struct net_device *dev)
855 {
856 rtl8192_InitBBRFRegDef(dev);
857 /* config BB&RF. As hardCode based initialization has not been well
858 * implemented, so use file first.
859 * FIXME: should implement it for hardcode? */
860 rtl8192_BB_Config_ParaFile(dev);
861 }
862
863
864 /******************************************************************************
865 * function: This function obtains the initialization value of Tx power Level
866 * offset
867 * input: net_device *dev
868 * output: none
869 * return: none
870 *****************************************************************************/
871 void rtl8192_phy_getTxPower(struct net_device *dev)
872 {
873 struct r8192_priv *priv = ieee80211_priv(dev);
874 u8 tmp;
875
876 read_nic_dword(dev, rTxAGC_Rate18_06,
877 &priv->MCSTxPowerLevelOriginalOffset[0]);
878 read_nic_dword(dev, rTxAGC_Rate54_24,
879 &priv->MCSTxPowerLevelOriginalOffset[1]);
880 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00,
881 &priv->MCSTxPowerLevelOriginalOffset[2]);
882 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04,
883 &priv->MCSTxPowerLevelOriginalOffset[3]);
884 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08,
885 &priv->MCSTxPowerLevelOriginalOffset[4]);
886 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12,
887 &priv->MCSTxPowerLevelOriginalOffset[5]);
888
889 /* Read rx initial gain */
890 read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
891 read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
892 read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
893 read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
894 RT_TRACE(COMP_INIT,
895 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
896 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
897 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
898
899 /* Read framesync */
900 read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
901 read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
902 priv->framesyncC34 = tmp;
903 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
904 rOFDM0_RxDetector3, priv->framesync);
905
906 /* Read SIFS (save the value read fome MACPHY_REG.txt) */
907 read_nic_word(dev, SIFS, &priv->SifsTime);
908 }
909
910 /******************************************************************************
911 * function: This function sets the initialization value of Tx power Level
912 * offset
913 * input: net_device *dev
914 * u8 channel
915 * output: none
916 * return: none
917 ******************************************************************************/
918 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
919 {
920 struct r8192_priv *priv = ieee80211_priv(dev);
921 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
922 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
923
924 switch (priv->rf_chip) {
925 case RF_8256:
926 /* need further implement */
927 PHY_SetRF8256CCKTxPower(dev, powerlevel);
928 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
929 break;
930 default:
931 RT_TRACE((COMP_PHY|COMP_ERR),
932 "error RF chipID(8225 or 8258) in function %s()\n",
933 __func__);
934 break;
935 }
936 }
937
938 /******************************************************************************
939 * function: This function checks Rf chip to do RF config
940 * input: net_device *dev
941 * output: none
942 * return: only 8256 is supported
943 ******************************************************************************/
944 void rtl8192_phy_RFConfig(struct net_device *dev)
945 {
946 struct r8192_priv *priv = ieee80211_priv(dev);
947
948 switch (priv->rf_chip) {
949 case RF_8256:
950 PHY_RF8256_Config(dev);
951 break;
952 default:
953 RT_TRACE(COMP_ERR, "error chip id\n");
954 break;
955 }
956 }
957
958 /******************************************************************************
959 * function: This function updates Initial gain
960 * input: net_device *dev
961 * output: none
962 * return: As Windows has not implemented this, wait for complement
963 ******************************************************************************/
964 void rtl8192_phy_updateInitGain(struct net_device *dev)
965 {
966 }
967
968 /******************************************************************************
969 * function: This function read RF parameters from general head file,
970 * and do RF 3-wire
971 * input: net_device *dev
972 * RF90_RADIO_PATH_E eRFPath
973 * output: none
974 * return: return code show if RF configuration is successful(0:pass, 1:fail)
975 * notice: Delay may be required for RF configuration
976 *****************************************************************************/
977 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
978 RF90_RADIO_PATH_E eRFPath)
979 {
980
981 int i;
982
983 switch (eRFPath) {
984 case RF90_PATH_A:
985 for (i = 0; i < RadioA_ArrayLength; i = i+2) {
986
987 if (rtl819XRadioA_Array[i] == 0xfe) {
988 mdelay(100);
989 continue;
990 }
991 rtl8192_phy_SetRFReg(dev, eRFPath,
992 rtl819XRadioA_Array[i],
993 bMask12Bits,
994 rtl819XRadioA_Array[i+1]);
995 mdelay(1);
996
997 }
998 break;
999 case RF90_PATH_B:
1000 for (i = 0; i < RadioB_ArrayLength; i = i+2) {
1001
1002 if (rtl819XRadioB_Array[i] == 0xfe) {
1003 mdelay(100);
1004 continue;
1005 }
1006 rtl8192_phy_SetRFReg(dev, eRFPath,
1007 rtl819XRadioB_Array[i],
1008 bMask12Bits,
1009 rtl819XRadioB_Array[i+1]);
1010 mdelay(1);
1011
1012 }
1013 break;
1014 case RF90_PATH_C:
1015 for (i = 0; i < RadioC_ArrayLength; i = i+2) {
1016
1017 if (rtl819XRadioC_Array[i] == 0xfe) {
1018 mdelay(100);
1019 continue;
1020 }
1021 rtl8192_phy_SetRFReg(dev, eRFPath,
1022 rtl819XRadioC_Array[i],
1023 bMask12Bits,
1024 rtl819XRadioC_Array[i+1]);
1025 mdelay(1);
1026
1027 }
1028 break;
1029 case RF90_PATH_D:
1030 for (i = 0; i < RadioD_ArrayLength; i = i+2) {
1031
1032 if (rtl819XRadioD_Array[i] == 0xfe) {
1033 mdelay(100);
1034 continue;
1035 }
1036 rtl8192_phy_SetRFReg(dev, eRFPath,
1037 rtl819XRadioD_Array[i],
1038 bMask12Bits,
1039 rtl819XRadioD_Array[i+1]);
1040 mdelay(1);
1041
1042 }
1043 break;
1044 default:
1045 break;
1046 }
1047
1048 return 0;
1049
1050 }
1051
1052 /******************************************************************************
1053 * function: This function sets Tx Power of the channel
1054 * input: net_device *dev
1055 * u8 channel
1056 * output: none
1057 * return: none
1058 * notice:
1059 ******************************************************************************/
1060 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
1061 {
1062 struct r8192_priv *priv = ieee80211_priv(dev);
1063 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
1064 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1065
1066 switch (priv->rf_chip) {
1067 case RF_8225:
1068 #ifdef TO_DO_LIST
1069 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
1070 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
1071 #endif
1072 break;
1073
1074 case RF_8256:
1075 PHY_SetRF8256CCKTxPower(dev, powerlevel);
1076 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
1077 break;
1078
1079 case RF_8258:
1080 break;
1081 default:
1082 RT_TRACE(COMP_ERR, "unknown rf chip ID in %s()\n", __func__);
1083 break;
1084 }
1085 }
1086
1087 /******************************************************************************
1088 * function: This function sets RF state on or off
1089 * input: net_device *dev
1090 * RT_RF_POWER_STATE eRFPowerState //Power State to set
1091 * output: none
1092 * return: none
1093 * notice:
1094 *****************************************************************************/
1095 bool rtl8192_SetRFPowerState(struct net_device *dev,
1096 RT_RF_POWER_STATE eRFPowerState)
1097 {
1098 bool bResult = true;
1099 struct r8192_priv *priv = ieee80211_priv(dev);
1100
1101 if (eRFPowerState == priv->ieee80211->eRFPowerState)
1102 return false;
1103
1104 if (priv->SetRFPowerStateInProgress == true)
1105 return false;
1106
1107 priv->SetRFPowerStateInProgress = true;
1108
1109 switch (priv->rf_chip) {
1110 case RF_8256:
1111 switch (eRFPowerState) {
1112 case eRfOn:
1113 /* RF-A, RF-B */
1114 /* enable RF-Chip A/B - 0x860[4] */
1115 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4,
1116 0x1);
1117 /* analog to digital on - 0x88c[9:8] */
1118 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300,
1119 0x3);
1120 /* digital to analog on - 0x880[4:3] */
1121 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1122 0x3);
1123 /* rx antenna on - 0xc04[1:0] */
1124 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);
1125 /* rx antenna on - 0xd04[1:0] */
1126 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);
1127 /* analog to digital part2 on - 0x880[6:5] */
1128 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1129 0x3);
1130
1131 break;
1132
1133 case eRfSleep:
1134
1135 break;
1136
1137 case eRfOff:
1138 /* RF-A, RF-B */
1139 /* disable RF-Chip A/B - 0x860[4] */
1140 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4,
1141 0x0);
1142 /* analog to digital off, for power save */
1143 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00,
1144 0x0); /* 0x88c[11:8] */
1145 /* digital to analog off, for power save - 0x880[4:3] */
1146 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1147 0x0);
1148 /* rx antenna off - 0xc04[3:0] */
1149 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1150 /* rx antenna off - 0xd04[3:0] */
1151 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1152 /* analog to digital part2 off, for power save */
1153 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1154 0x0); /* 0x880[6:5] */
1155
1156 break;
1157
1158 default:
1159 bResult = false;
1160 RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n",
1161 __func__, eRFPowerState);
1162 break;
1163 }
1164 break;
1165 default:
1166 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
1167 break;
1168 }
1169 #ifdef TO_DO_LIST
1170 if (bResult) {
1171 /* Update current RF state variable. */
1172 pHalData->eRFPowerState = eRFPowerState;
1173 switch (pHalData->RFChipID) {
1174 case RF_8256:
1175 switch (pHalData->eRFPowerState) {
1176 case eRfOff:
1177 /* If Rf off reason is from IPS,
1178 LED should blink with no link */
1179 if (pMgntInfo->RfOffReason == RF_CHANGE_BY_IPS)
1180 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1181 else
1182 /* Turn off LED if RF is not ON. */
1183 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF);
1184 break;
1185
1186 case eRfOn:
1187 /* Turn on RF we are still linked, which might
1188 happen when we quickly turn off and on HW RF.
1189 */
1190 if (pMgntInfo->bMediaConnect)
1191 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK);
1192 else
1193 /* Turn off LED if RF is not ON. */
1194 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1195 break;
1196
1197 default:
1198 break;
1199 }
1200 break;
1201
1202 default:
1203 RT_TRACE(COMP_RF, DBG_LOUD, "%s(): Unknown RF type\n",
1204 __func__);
1205 break;
1206 }
1207
1208 }
1209 #endif
1210 priv->SetRFPowerStateInProgress = false;
1211
1212 return bResult;
1213 }
1214
1215 /******************************************************************************
1216 * function: This function sets command table variable (struct SwChnlCmd).
1217 * input: SwChnlCmd *CmdTable //table to be set
1218 * u32 CmdTableIdx //variable index in table to be set
1219 * u32 CmdTableSz //table size
1220 * SwChnlCmdID CmdID //command ID to set
1221 * u32 Para1
1222 * u32 Para2
1223 * u32 msDelay
1224 * output:
1225 * return: true if finished, false otherwise
1226 * notice:
1227 ******************************************************************************/
1228 static u8 rtl8192_phy_SetSwChnlCmdArray(SwChnlCmd *CmdTable, u32 CmdTableIdx,
1229 u32 CmdTableSz, SwChnlCmdID CmdID,
1230 u32 Para1, u32 Para2, u32 msDelay)
1231 {
1232 SwChnlCmd *pCmd;
1233
1234 if (CmdTable == NULL) {
1235 RT_TRACE(COMP_ERR, "%s(): CmdTable cannot be NULL\n", __func__);
1236 return false;
1237 }
1238 if (CmdTableIdx >= CmdTableSz) {
1239 RT_TRACE(COMP_ERR, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1240 __func__, CmdTableIdx, CmdTableSz);
1241 return false;
1242 }
1243
1244 pCmd = CmdTable + CmdTableIdx;
1245 pCmd->CmdID = CmdID;
1246 pCmd->Para1 = Para1;
1247 pCmd->Para2 = Para2;
1248 pCmd->msDelay = msDelay;
1249
1250 return true;
1251 }
1252
1253 /******************************************************************************
1254 * function: This function sets channel step by step
1255 * input: net_device *dev
1256 * u8 channel
1257 * u8 *stage //3 stages
1258 * u8 *step
1259 * u32 *delay //whether need to delay
1260 * output: store new stage, step and delay for next step
1261 * (combine with function above)
1262 * return: true if finished, false otherwise
1263 * notice: Wait for simpler function to replace it
1264 *****************************************************************************/
1265 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel,
1266 u8 *stage, u8 *step, u32 *delay)
1267 {
1268 struct r8192_priv *priv = ieee80211_priv(dev);
1269 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
1270 u32 PreCommonCmdCnt;
1271 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
1272 u32 PostCommonCmdCnt;
1273 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
1274 u32 RfDependCmdCnt;
1275 SwChnlCmd *CurrentCmd = NULL;
1276 u8 eRFPath;
1277
1278 RT_TRACE(COMP_CH, "%s() stage: %d, step: %d, channel: %d\n",
1279 __func__, *stage, *step, channel);
1280 if (!IsLegalChannel(priv->ieee80211, channel)) {
1281 RT_TRACE(COMP_ERR, "set to illegal channel: %d\n", channel);
1282 /* return true to tell upper caller function this channel
1283 setting is finished! Or it will in while loop. */
1284 return true;
1285 }
1286 /* FIXME: need to check whether channel is legal or not here */
1287
1288
1289 /* <1> Fill up pre common command. */
1290 PreCommonCmdCnt = 0;
1291 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1292 MAX_PRECMD_CNT, CmdID_SetTxPowerLevel,
1293 0, 0, 0);
1294 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1295 MAX_PRECMD_CNT, CmdID_End, 0, 0, 0);
1296
1297 /* <2> Fill up post common command. */
1298 PostCommonCmdCnt = 0;
1299
1300 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++,
1301 MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0);
1302
1303 /* <3> Fill up RF dependent command. */
1304 RfDependCmdCnt = 0;
1305 switch (priv->rf_chip) {
1306 case RF_8225:
1307 if (!(channel >= 1 && channel <= 14)) {
1308 RT_TRACE(COMP_ERR,
1309 "illegal channel for Zebra 8225: %d\n",
1310 channel);
1311 return true;
1312 }
1313 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1314 MAX_RFDEPENDCMD_CNT,
1315 CmdID_RF_WriteReg,
1316 rZebra1_Channel,
1317 RF_CHANNEL_TABLE_ZEBRA[channel],
1318 10);
1319 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1320 MAX_RFDEPENDCMD_CNT,
1321 CmdID_End, 0, 0, 0);
1322 break;
1323
1324 case RF_8256:
1325 /* TEST!! This is not the table for 8256!! */
1326 if (!(channel >= 1 && channel <= 14)) {
1327 RT_TRACE(COMP_ERR,
1328 "illegal channel for Zebra 8256: %d\n",
1329 channel);
1330 return true;
1331 }
1332 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1333 MAX_RFDEPENDCMD_CNT,
1334 CmdID_RF_WriteReg,
1335 rZebra1_Channel, channel, 10);
1336 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1337 MAX_RFDEPENDCMD_CNT,
1338 CmdID_End, 0, 0, 0);
1339 break;
1340
1341 case RF_8258:
1342 break;
1343
1344 default:
1345 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1346 return true;
1347 break;
1348 }
1349
1350
1351 do {
1352 switch (*stage) {
1353 case 0:
1354 CurrentCmd = &PreCommonCmd[*step];
1355 break;
1356 case 1:
1357 CurrentCmd = &RfDependCmd[*step];
1358 break;
1359 case 2:
1360 CurrentCmd = &PostCommonCmd[*step];
1361 break;
1362 }
1363
1364 if (CurrentCmd->CmdID == CmdID_End) {
1365 if ((*stage) == 2) {
1366 (*delay) = CurrentCmd->msDelay;
1367 return true;
1368 }
1369 (*stage)++;
1370 (*step) = 0;
1371 continue;
1372 }
1373
1374 switch (CurrentCmd->CmdID) {
1375 case CmdID_SetTxPowerLevel:
1376 if (priv->card_8192_version == (u8)VERSION_819xU_A)
1377 /* consider it later! */
1378 rtl8192_SetTxPowerLevel(dev, channel);
1379 break;
1380 case CmdID_WritePortUlong:
1381 write_nic_dword(dev, CurrentCmd->Para1,
1382 CurrentCmd->Para2);
1383 break;
1384 case CmdID_WritePortUshort:
1385 write_nic_word(dev, CurrentCmd->Para1,
1386 (u16)CurrentCmd->Para2);
1387 break;
1388 case CmdID_WritePortUchar:
1389 write_nic_byte(dev, CurrentCmd->Para1,
1390 (u8)CurrentCmd->Para2);
1391 break;
1392 case CmdID_RF_WriteReg:
1393 for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) {
1394 rtl8192_phy_SetRFReg(dev,
1395 (RF90_RADIO_PATH_E)eRFPath,
1396 CurrentCmd->Para1,
1397 bZebra1_ChannelNum,
1398 CurrentCmd->Para2);
1399 }
1400 break;
1401 default:
1402 break;
1403 }
1404
1405 break;
1406 } while (true);
1407
1408 (*delay) = CurrentCmd->msDelay;
1409 (*step)++;
1410 return false;
1411 }
1412
1413 /******************************************************************************
1414 * function: This function does actually set channel work
1415 * input: net_device *dev
1416 * u8 channel
1417 * output: none
1418 * return: none
1419 * notice: We should not call this function directly
1420 *****************************************************************************/
1421 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1422 {
1423 struct r8192_priv *priv = ieee80211_priv(dev);
1424 u32 delay = 0;
1425
1426 while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
1427 &priv->SwChnlStep, &delay)) {
1428 if (!priv->up)
1429 break;
1430 }
1431 }
1432
1433 /******************************************************************************
1434 * function: Callback routine of the work item for switch channel.
1435 * input: net_device *dev
1436 *
1437 * output: none
1438 * return: none
1439 *****************************************************************************/
1440 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1441 {
1442
1443 struct r8192_priv *priv = ieee80211_priv(dev);
1444
1445 RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n",
1446 priv->chan);
1447
1448
1449 rtl8192_phy_FinishSwChnlNow(dev, priv->chan);
1450
1451 RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n");
1452 }
1453
1454 /******************************************************************************
1455 * function: This function scheduled actual work item to set channel
1456 * input: net_device *dev
1457 * u8 channel //channel to set
1458 * output: none
1459 * return: return code show if workitem is scheduled (1:pass, 0:fail)
1460 * notice: Delay may be required for RF configuration
1461 ******************************************************************************/
1462 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1463 {
1464 struct r8192_priv *priv = ieee80211_priv(dev);
1465
1466 RT_TRACE(COMP_CH, "%s(), SwChnlInProgress: %d\n", __func__,
1467 priv->SwChnlInProgress);
1468 if (!priv->up)
1469 return false;
1470 if (priv->SwChnlInProgress)
1471 return false;
1472
1473 /* -------------------------------------------- */
1474 switch (priv->ieee80211->mode) {
1475 case WIRELESS_MODE_A:
1476 case WIRELESS_MODE_N_5G:
1477 if (channel <= 14) {
1478 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n");
1479 return false;
1480 }
1481 break;
1482 case WIRELESS_MODE_B:
1483 if (channel > 14) {
1484 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n");
1485 return false;
1486 }
1487 break;
1488 case WIRELESS_MODE_G:
1489 case WIRELESS_MODE_N_24G:
1490 if (channel > 14) {
1491 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n");
1492 return false;
1493 }
1494 break;
1495 }
1496 /* -------------------------------------------- */
1497
1498 priv->SwChnlInProgress = true;
1499 if (channel == 0)
1500 channel = 1;
1501
1502 priv->chan = channel;
1503
1504 priv->SwChnlStage = 0;
1505 priv->SwChnlStep = 0;
1506 if (priv->up)
1507 rtl8192_SwChnl_WorkItem(dev);
1508
1509 priv->SwChnlInProgress = false;
1510 return true;
1511 }
1512
1513 /******************************************************************************
1514 * function: Callback routine of the work item for set bandwidth mode.
1515 * input: net_device *dev
1516 * output: none
1517 * return: none
1518 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can
1519 * test whether current work in the queue or not.//do I?
1520 *****************************************************************************/
1521 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1522 {
1523
1524 struct r8192_priv *priv = ieee80211_priv(dev);
1525 u8 regBwOpMode;
1526
1527 RT_TRACE(COMP_SWBW, "%s() Switch to %s bandwidth\n", __func__,
1528 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
1529
1530
1531 if (priv->rf_chip == RF_PSEUDO_11N) {
1532 priv->SetBWModeInProgress = false;
1533 return;
1534 }
1535
1536 /* <1> Set MAC register */
1537 read_nic_byte(dev, BW_OPMODE, &regBwOpMode);
1538
1539 switch (priv->CurrentChannelBW) {
1540 case HT_CHANNEL_WIDTH_20:
1541 regBwOpMode |= BW_OPMODE_20MHZ;
1542 /* We have not verify whether this register works */
1543 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1544 break;
1545
1546 case HT_CHANNEL_WIDTH_20_40:
1547 regBwOpMode &= ~BW_OPMODE_20MHZ;
1548 /* We have not verify whether this register works */
1549 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1550 break;
1551
1552 default:
1553 RT_TRACE(COMP_ERR,
1554 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1555 priv->CurrentChannelBW);
1556 break;
1557 }
1558
1559 /* <2> Set PHY related register */
1560 switch (priv->CurrentChannelBW) {
1561 case HT_CHANNEL_WIDTH_20:
1562 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1563 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1564 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1565 0x00100000, 1);
1566
1567 /* Correct the tx power for CCK rate in 20M. */
1568 priv->cck_present_attentuation =
1569 priv->cck_present_attentuation_20Mdefault +
1570 priv->cck_present_attentuation_difference;
1571
1572 if (priv->cck_present_attentuation > 22)
1573 priv->cck_present_attentuation = 22;
1574 if (priv->cck_present_attentuation < 0)
1575 priv->cck_present_attentuation = 0;
1576 RT_TRACE(COMP_INIT,
1577 "20M, pHalData->CCKPresentAttentuation = %d\n",
1578 priv->cck_present_attentuation);
1579
1580 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1581 priv->bcck_in_ch14 = TRUE;
1582 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1583 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1584 priv->bcck_in_ch14 = FALSE;
1585 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1586 } else {
1587 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1588 }
1589
1590 break;
1591 case HT_CHANNEL_WIDTH_20_40:
1592 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1593 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1594 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
1595 priv->nCur40MhzPrimeSC>>1);
1596 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1597 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
1598 priv->nCur40MhzPrimeSC);
1599 priv->cck_present_attentuation =
1600 priv->cck_present_attentuation_40Mdefault +
1601 priv->cck_present_attentuation_difference;
1602
1603 if (priv->cck_present_attentuation > 22)
1604 priv->cck_present_attentuation = 22;
1605 if (priv->cck_present_attentuation < 0)
1606 priv->cck_present_attentuation = 0;
1607
1608 RT_TRACE(COMP_INIT,
1609 "40M, pHalData->CCKPresentAttentuation = %d\n",
1610 priv->cck_present_attentuation);
1611 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1612 priv->bcck_in_ch14 = true;
1613 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1614 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1615 priv->bcck_in_ch14 = false;
1616 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1617 } else {
1618 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1619 }
1620
1621 break;
1622 default:
1623 RT_TRACE(COMP_ERR,
1624 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1625 priv->CurrentChannelBW);
1626 break;
1627
1628 }
1629 /* Skip over setting of J-mode in BB register here.
1630 Default value is "None J mode". */
1631
1632 /* <3> Set RF related register */
1633 switch (priv->rf_chip) {
1634 case RF_8225:
1635 #ifdef TO_DO_LIST
1636 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
1637 #endif
1638 break;
1639
1640 case RF_8256:
1641 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1642 break;
1643
1644 case RF_8258:
1645 break;
1646
1647 case RF_PSEUDO_11N:
1648 break;
1649
1650 default:
1651 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1652 break;
1653 }
1654 priv->SetBWModeInProgress = false;
1655
1656 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d\n",
1657 atomic_read(&priv->ieee80211->atm_swbw));
1658 }
1659
1660 /******************************************************************************
1661 * function: This function schedules bandwidth switch work.
1662 * input: struct net_deviceq *dev
1663 * HT_CHANNEL_WIDTH bandwidth //20M or 40M
1664 * HT_EXTCHNL_OFFSET offset //Upper, Lower, or Don't care
1665 * output: none
1666 * return: none
1667 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can
1668 * test whether current work in the queue or not.//do I?
1669 *****************************************************************************/
1670 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH bandwidth,
1671 HT_EXTCHNL_OFFSET offset)
1672 {
1673 struct r8192_priv *priv = ieee80211_priv(dev);
1674
1675 if (priv->SetBWModeInProgress)
1676 return;
1677 priv->SetBWModeInProgress = true;
1678
1679 priv->CurrentChannelBW = bandwidth;
1680
1681 if (offset == HT_EXTCHNL_OFFSET_LOWER)
1682 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1683 else if (offset == HT_EXTCHNL_OFFSET_UPPER)
1684 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1685 else
1686 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1687
1688 rtl8192_SetBWModeWorkItem(dev);
1689
1690 }
1691
1692 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
1693 {
1694 struct r8192_priv *priv = ieee80211_priv(dev);
1695
1696 priv->InitialGainOperateType = Operation;
1697
1698 if (priv->up)
1699 queue_delayed_work(priv->priv_wq, &priv->initialgain_operate_wq, 0);
1700 }
1701
1702 void InitialGainOperateWorkItemCallBack(struct work_struct *work)
1703 {
1704 struct delayed_work *dwork = container_of(work, struct delayed_work,
1705 work);
1706 struct r8192_priv *priv = container_of(dwork, struct r8192_priv,
1707 initialgain_operate_wq);
1708 struct net_device *dev = priv->ieee80211->dev;
1709 #define SCAN_RX_INITIAL_GAIN 0x17
1710 #define POWER_DETECTION_TH 0x08
1711 u32 bitmask;
1712 u8 initial_gain;
1713 u8 Operation;
1714
1715 Operation = priv->InitialGainOperateType;
1716
1717 switch (Operation) {
1718 case IG_Backup:
1719 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1720 initial_gain = SCAN_RX_INITIAL_GAIN;
1721 bitmask = bMaskByte0;
1722 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1723 /* FW DIG OFF */
1724 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1725 priv->initgain_backup.xaagccore1 =
1726 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask);
1727 priv->initgain_backup.xbagccore1 =
1728 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask);
1729 priv->initgain_backup.xcagccore1 =
1730 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask);
1731 priv->initgain_backup.xdagccore1 =
1732 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bitmask);
1733 bitmask = bMaskByte2;
1734 priv->initgain_backup.cca =
1735 (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bitmask);
1736
1737 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",
1738 priv->initgain_backup.xaagccore1);
1739 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",
1740 priv->initgain_backup.xbagccore1);
1741 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",
1742 priv->initgain_backup.xcagccore1);
1743 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",
1744 priv->initgain_backup.xdagccore1);
1745 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",
1746 priv->initgain_backup.cca);
1747
1748 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n",
1749 initial_gain);
1750 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1751 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1752 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1753 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1754 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n",
1755 POWER_DETECTION_TH);
1756 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1757 break;
1758 case IG_Restore:
1759 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1760 bitmask = 0x7f; /* Bit0 ~ Bit6 */
1761 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1762 /* FW DIG OFF */
1763 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1764
1765 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask,
1766 (u32)priv->initgain_backup.xaagccore1);
1767 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask,
1768 (u32)priv->initgain_backup.xbagccore1);
1769 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask,
1770 (u32)priv->initgain_backup.xcagccore1);
1771 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask,
1772 (u32)priv->initgain_backup.xdagccore1);
1773 bitmask = bMaskByte2;
1774 rtl8192_setBBreg(dev, rCCK0_CCA, bitmask,
1775 (u32)priv->initgain_backup.cca);
1776
1777 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",
1778 priv->initgain_backup.xaagccore1);
1779 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",
1780 priv->initgain_backup.xbagccore1);
1781 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",
1782 priv->initgain_backup.xcagccore1);
1783 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",
1784 priv->initgain_backup.xdagccore1);
1785 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",
1786 priv->initgain_backup.cca);
1787
1788 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel);
1789
1790 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1791 /* FW DIG ON */
1792 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1793 break;
1794 default:
1795 RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
1796 break;
1797 }
1798 }
Linux kernel - Deliverables
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