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Merge remote-tracking branch 'usb-chipidea-next/ci-for-usb-next'
[deliverable/linux.git] / drivers / staging / rtl8723au / hal / rtl8723a_hal_init.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 ******************************************************************************/
15 #define _HAL_INIT_C_
16
17 #include <linux/firmware.h>
18 #include <drv_types.h>
19 #include <rtw_efuse.h>
20
21 #include <rtl8723a_hal.h>
22 #include <usb_ops_linux.h>
23
24 static void _FWDownloadEnable(struct rtw_adapter *padapter, bool enable)
25 {
26 u8 tmp;
27
28 if (enable) {
29 /* 8051 enable */
30 tmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
31 rtl8723au_write8(padapter, REG_SYS_FUNC_EN + 1, tmp | 0x04);
32
33 /* MCU firmware download enable. */
34 tmp = rtl8723au_read8(padapter, REG_MCUFWDL);
35 rtl8723au_write8(padapter, REG_MCUFWDL, tmp | 0x01);
36
37 /* 8051 reset */
38 tmp = rtl8723au_read8(padapter, REG_MCUFWDL + 2);
39 rtl8723au_write8(padapter, REG_MCUFWDL + 2, tmp & 0xf7);
40 } else {
41 /* MCU firmware download disable. */
42 tmp = rtl8723au_read8(padapter, REG_MCUFWDL);
43 rtl8723au_write8(padapter, REG_MCUFWDL, tmp & 0xfe);
44
45 /* Reserved for fw extension. */
46 rtl8723au_write8(padapter, REG_MCUFWDL + 1, 0x00);
47 }
48 }
49
50 static int
51 _PageWrite(struct rtw_adapter *padapter, u32 page, void *buffer, u32 size)
52 {
53 u8 value8;
54 u8 u8Page = (u8) (page & 0x07);
55
56 if (size > MAX_PAGE_SIZE)
57 return _FAIL;
58
59 value8 = (rtl8723au_read8(padapter, REG_MCUFWDL + 2) & 0xF8) | u8Page;
60 rtl8723au_write8(padapter, REG_MCUFWDL + 2, value8);
61
62 return rtl8723au_writeN(padapter, FW_8723A_START_ADDRESS, size, buffer);
63 }
64
65 static int _WriteFW(struct rtw_adapter *padapter, void *buffer, u32 size)
66 {
67 /* Since we need dynamic decide method of dwonload fw, so we
68 call this function to get chip version. */
69 /* We can remove _ReadChipVersion from ReadpadapterInfo8192C later. */
70 int ret = _SUCCESS;
71 u32 pageNums, remainSize;
72 u32 page, offset;
73 u8 *bufferPtr = (u8 *) buffer;
74
75 pageNums = size / MAX_PAGE_SIZE;
76 /* RT_ASSERT((pageNums <= 4),
77 ("Page numbers should not greater then 4 \n")); */
78 remainSize = size % MAX_PAGE_SIZE;
79
80 for (page = 0; page < pageNums; page++) {
81 offset = page * MAX_PAGE_SIZE;
82 ret = _PageWrite(padapter, page, bufferPtr + offset,
83 MAX_PAGE_SIZE);
84
85 if (ret == _FAIL)
86 goto exit;
87 }
88 if (remainSize) {
89 offset = pageNums * MAX_PAGE_SIZE;
90 page = pageNums;
91 ret = _PageWrite(padapter, page, bufferPtr + offset,
92 remainSize);
93
94 if (ret == _FAIL)
95 goto exit;
96 }
97 RT_TRACE(_module_hal_init_c_, _drv_info_,
98 "_WriteFW Done- for Normal chip.\n");
99
100 exit:
101 return ret;
102 }
103
104 static int _FWFreeToGo(struct rtw_adapter *padapter)
105 {
106 u32 counter = 0;
107 u32 value32;
108
109 /* polling CheckSum report */
110 do {
111 value32 = rtl8723au_read32(padapter, REG_MCUFWDL);
112 if (value32 & FWDL_ChkSum_rpt)
113 break;
114 } while (counter++ < POLLING_READY_TIMEOUT_COUNT);
115
116 if (counter >= POLLING_READY_TIMEOUT_COUNT) {
117 RT_TRACE(_module_hal_init_c_, _drv_err_,
118 "%s: chksum report fail! REG_MCUFWDL:0x%08x\n",
119 __func__, value32);
120 return _FAIL;
121 }
122 RT_TRACE(_module_hal_init_c_, _drv_info_,
123 "%s: Checksum report OK! REG_MCUFWDL:0x%08x\n", __func__,
124 value32);
125
126 value32 = rtl8723au_read32(padapter, REG_MCUFWDL);
127 value32 |= MCUFWDL_RDY;
128 value32 &= ~WINTINI_RDY;
129 rtl8723au_write32(padapter, REG_MCUFWDL, value32);
130
131 /* polling for FW ready */
132 counter = 0;
133 do {
134 value32 = rtl8723au_read32(padapter, REG_MCUFWDL);
135 if (value32 & WINTINI_RDY) {
136 RT_TRACE(_module_hal_init_c_, _drv_info_,
137 "%s: Polling FW ready success!! REG_MCUFWDL:0x%08x\n",
138 __func__, value32);
139 return _SUCCESS;
140 }
141 udelay(5);
142 } while (counter++ < POLLING_READY_TIMEOUT_COUNT);
143
144 RT_TRACE(_module_hal_init_c_, _drv_err_,
145 "%s: Polling FW ready fail!! REG_MCUFWDL:0x%08x\n",
146 __func__, value32);
147 return _FAIL;
148 }
149
150 #define IS_FW_81xxC(padapter) (((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0)
151
152 void rtl8723a_FirmwareSelfReset(struct rtw_adapter *padapter)
153 {
154 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
155 u8 u1bTmp;
156 u8 Delay = 100;
157
158 if (!(IS_FW_81xxC(padapter) &&
159 ((pHalData->FirmwareVersion < 0x21) ||
160 (pHalData->FirmwareVersion == 0x21 &&
161 pHalData->FirmwareSubVersion < 0x01)))) {
162 /* after 88C Fw v33.1 */
163 /* 0x1cf = 0x20. Inform 8051 to reset. 2009.12.25. tynli_test */
164 rtl8723au_write8(padapter, REG_HMETFR + 3, 0x20);
165
166 u1bTmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
167 while (u1bTmp & BIT(2)) {
168 Delay--;
169 if (Delay == 0)
170 break;
171 udelay(50);
172 u1bTmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
173 }
174 RT_TRACE(_module_hal_init_c_, _drv_info_,
175 "-%s: 8051 reset success (%d)\n", __func__,
176 Delay);
177
178 if ((Delay == 0)) {
179 /* force firmware reset */
180 u1bTmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
181 rtl8723au_write8(padapter, REG_SYS_FUNC_EN + 1,
182 u1bTmp & ~BIT(2));
183 }
184 }
185 }
186
187 /* */
188 /* Description: */
189 /* Download 8192C firmware code. */
190 /* */
191 /* */
192 int rtl8723a_FirmwareDownload(struct rtw_adapter *padapter)
193 {
194 int rtStatus = _SUCCESS;
195 u8 writeFW_retry = 0;
196 unsigned long fwdl_start_time;
197 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
198 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
199 struct device *device = dvobj_to_dev(dvobj);
200 struct rt_8723a_firmware_hdr *pFwHdr = NULL;
201 const struct firmware *fw;
202 char *fw_name;
203 u8 *firmware_buf = NULL;
204 u8 *buf;
205 int fw_size;
206 static int log_version;
207
208 RT_TRACE(_module_hal_init_c_, _drv_info_, "+%s\n", __func__);
209
210 if (IS_8723A_A_CUT(pHalData->VersionID)) {
211 fw_name = "rtlwifi/rtl8723aufw_A.bin";
212 RT_TRACE(_module_hal_init_c_, _drv_info_,
213 "rtl8723a_FirmwareDownload: R8723FwImageArray_UMC for RTL8723A A CUT\n");
214 } else if (IS_8723A_B_CUT(pHalData->VersionID)) {
215 /* WLAN Fw. */
216 if (padapter->registrypriv.wifi_spec == 1) {
217 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
218 DBG_8723A(" Rtl8723_FwUMCBCutImageArrayWithoutBT for "
219 "RTL8723A B CUT\n");
220 } else {
221 if (rtl8723a_BT_coexist(padapter)) {
222 fw_name = "rtlwifi/rtl8723aufw_B.bin";
223 DBG_8723A(" Rtl8723_FwUMCBCutImageArrayWithBT "
224 "for RTL8723A B CUT\n");
225 } else {
226 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
227 DBG_8723A(" Rtl8723_FwUMCBCutImageArrayWithout "
228 "BT for RTL8723A B CUT\n");
229 }
230 }
231 } else {
232 /* <Roger_TODO> We should download proper RAM Code here
233 to match the ROM code. */
234 RT_TRACE(_module_hal_init_c_, _drv_err_,
235 "%s: unknown version!\n", __func__);
236 rtStatus = _FAIL;
237 goto Exit;
238 }
239
240 pr_info("rtl8723au: Loading firmware %s\n", fw_name);
241 if (request_firmware(&fw, fw_name, device)) {
242 pr_err("rtl8723au: request_firmware load failed\n");
243 rtStatus = _FAIL;
244 goto Exit;
245 }
246 if (!fw) {
247 pr_err("rtl8723au: Firmware %s not available\n", fw_name);
248 rtStatus = _FAIL;
249 goto Exit;
250 }
251 firmware_buf = kmemdup(fw->data, fw->size, GFP_KERNEL);
252 fw_size = fw->size;
253 release_firmware(fw);
254 if (!firmware_buf) {
255 rtStatus = _FAIL;
256 goto Exit;
257 }
258 buf = firmware_buf;
259
260 /* To Check Fw header. Added by tynli. 2009.12.04. */
261 pFwHdr = (struct rt_8723a_firmware_hdr *)firmware_buf;
262
263 pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->Version);
264 pHalData->FirmwareSubVersion = pFwHdr->Subversion;
265 pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->Signature);
266
267 DBG_8723A("%s: fw_ver =%d fw_subver =%d sig = 0x%x\n",
268 __func__, pHalData->FirmwareVersion,
269 pHalData->FirmwareSubVersion, pHalData->FirmwareSignature);
270
271 if (!log_version++)
272 pr_info("%sFirmware Version %d, SubVersion %d, Signature "
273 "0x%x\n", DRIVER_PREFIX, pHalData->FirmwareVersion,
274 pHalData->FirmwareSubVersion,
275 pHalData->FirmwareSignature);
276
277 if (IS_FW_HEADER_EXIST(pFwHdr)) {
278 /* Shift 32 bytes for FW header */
279 buf = buf + 32;
280 fw_size = fw_size - 32;
281 }
282
283 /* Suggested by Filen. If 8051 is running in RAM code, driver should
284 inform Fw to reset by itself, */
285 /* or it will cause download Fw fail. 2010.02.01. by tynli. */
286 if (rtl8723au_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) {
287 /* 8051 RAM code */
288 rtl8723a_FirmwareSelfReset(padapter);
289 rtl8723au_write8(padapter, REG_MCUFWDL, 0x00);
290 }
291
292 _FWDownloadEnable(padapter, true);
293 fwdl_start_time = jiffies;
294 while (1) {
295 /* reset the FWDL chksum */
296 rtl8723au_write8(padapter, REG_MCUFWDL,
297 rtl8723au_read8(padapter, REG_MCUFWDL) |
298 FWDL_ChkSum_rpt);
299
300 rtStatus = _WriteFW(padapter, buf, fw_size);
301
302 if (rtStatus == _SUCCESS ||
303 (jiffies_to_msecs(jiffies - fwdl_start_time) > 500 &&
304 writeFW_retry++ >= 3))
305 break;
306
307 DBG_8723A("%s writeFW_retry:%u, time after fwdl_start_time:"
308 "%ums\n", __func__, writeFW_retry,
309 jiffies_to_msecs(jiffies - fwdl_start_time));
310 }
311 _FWDownloadEnable(padapter, false);
312 if (_SUCCESS != rtStatus) {
313 DBG_8723A("DL Firmware failed!\n");
314 goto Exit;
315 }
316
317 rtStatus = _FWFreeToGo(padapter);
318 if (_SUCCESS != rtStatus) {
319 RT_TRACE(_module_hal_init_c_, _drv_err_,
320 "DL Firmware failed!\n");
321 goto Exit;
322 }
323 RT_TRACE(_module_hal_init_c_, _drv_info_,
324 "Firmware is ready to run!\n");
325
326 Exit:
327 kfree(firmware_buf);
328 return rtStatus;
329 }
330
331 void rtl8723a_InitializeFirmwareVars(struct rtw_adapter *padapter)
332 {
333 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
334
335 /* Init Fw LPS related. */
336 padapter->pwrctrlpriv.bFwCurrentInPSMode = false;
337
338 /* Init H2C counter. by tynli. 2009.12.09. */
339 pHalData->LastHMEBoxNum = 0;
340 }
341
342 /* */
343 /* Efuse related code */
344 /* */
345 static u8
346 hal_EfuseSwitchToBank(struct rtw_adapter *padapter, u8 bank)
347 {
348 u8 bRet = false;
349 u32 value32 = 0;
350
351 DBG_8723A("%s: Efuse switch bank to %d\n", __func__, bank);
352 value32 = rtl8723au_read32(padapter, EFUSE_TEST);
353 bRet = true;
354 switch (bank) {
355 case 0:
356 value32 = (value32 & ~EFUSE_SEL_MASK) |
357 EFUSE_SEL(EFUSE_WIFI_SEL_0);
358 break;
359 case 1:
360 value32 = (value32 & ~EFUSE_SEL_MASK) |
361 EFUSE_SEL(EFUSE_BT_SEL_0);
362 break;
363 case 2:
364 value32 = (value32 & ~EFUSE_SEL_MASK) |
365 EFUSE_SEL(EFUSE_BT_SEL_1);
366 break;
367 case 3:
368 value32 = (value32 & ~EFUSE_SEL_MASK) |
369 EFUSE_SEL(EFUSE_BT_SEL_2);
370 break;
371 default:
372 value32 = (value32 & ~EFUSE_SEL_MASK) |
373 EFUSE_SEL(EFUSE_WIFI_SEL_0);
374 bRet = false;
375 break;
376 }
377 rtl8723au_write32(padapter, EFUSE_TEST, value32);
378
379 return bRet;
380 }
381
382 static void
383 hal_ReadEFuse_WiFi(struct rtw_adapter *padapter,
384 u16 _offset, u16 _size_byte, u8 *pbuf)
385 {
386 u8 *efuseTbl = NULL;
387 u16 eFuse_Addr = 0;
388 u8 offset, wden;
389 u8 efuseHeader, efuseExtHdr, efuseData;
390 u16 i, total, used;
391 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
392
393 /* Do NOT excess total size of EFuse table.
394 Added by Roger, 2008.11.10. */
395 if ((_offset + _size_byte) > EFUSE_MAP_LEN_8723A) {
396 DBG_8723A("%s: Invalid offset(%#x) with read bytes(%#x)!!\n",
397 __func__, _offset, _size_byte);
398 return;
399 }
400
401 efuseTbl = kmalloc(EFUSE_MAP_LEN_8723A, GFP_KERNEL);
402 if (!efuseTbl)
403 return;
404 /* 0xff will be efuse default value instead of 0x00. */
405 memset(efuseTbl, 0xFF, EFUSE_MAP_LEN_8723A);
406
407 /* switch bank back to bank 0 for later BT and wifi use. */
408 hal_EfuseSwitchToBank(padapter, 0);
409
410 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
411 ReadEFuseByte23a(padapter, eFuse_Addr++, &efuseHeader);
412 if (efuseHeader == 0xFF) {
413 DBG_8723A("%s: data end at address =%#x\n", __func__,
414 eFuse_Addr);
415 break;
416 }
417
418 /* Check PG header for section num. */
419 if (EXT_HEADER(efuseHeader)) { /* extended header */
420 offset = GET_HDR_OFFSET_2_0(efuseHeader);
421
422 ReadEFuseByte23a(padapter, eFuse_Addr++, &efuseExtHdr);
423 if (ALL_WORDS_DISABLED(efuseExtHdr))
424 continue;
425
426 offset |= ((efuseExtHdr & 0xF0) >> 1);
427 wden = efuseExtHdr & 0x0F;
428 } else {
429 offset = (efuseHeader >> 4) & 0x0f;
430 wden = efuseHeader & 0x0f;
431 }
432
433 if (offset < EFUSE_MAX_SECTION_8723A) {
434 u16 addr;
435 /* Get word enable value from PG header */
436
437 addr = offset * PGPKT_DATA_SIZE;
438 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
439 /* Check word enable condition in the section */
440 if (!(wden & (0x01 << i))) {
441 ReadEFuseByte23a(padapter, eFuse_Addr++,
442 &efuseData);
443 efuseTbl[addr] = efuseData;
444
445 ReadEFuseByte23a(padapter, eFuse_Addr++,
446 &efuseData);
447 efuseTbl[addr + 1] = efuseData;
448 }
449 addr += 2;
450 }
451 } else {
452 DBG_8723A(KERN_ERR "%s: offset(%d) is illegal!!\n",
453 __func__, offset);
454 eFuse_Addr += Efuse_CalculateWordCnts23a(wden) * 2;
455 }
456 }
457
458 /* Copy from Efuse map to output pointer memory!!! */
459 for (i = 0; i < _size_byte; i++)
460 pbuf[i] = efuseTbl[_offset + i];
461
462 /* Calculate Efuse utilization */
463 EFUSE_GetEfuseDefinition23a(padapter, EFUSE_WIFI,
464 TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total);
465 used = eFuse_Addr - 1;
466 pHalData->EfuseUsedBytes = used;
467
468 kfree(efuseTbl);
469 }
470
471 static void
472 hal_ReadEFuse_BT(struct rtw_adapter *padapter,
473 u16 _offset, u16 _size_byte, u8 *pbuf)
474 {
475 u8 *efuseTbl;
476 u8 bank;
477 u16 eFuse_Addr;
478 u8 efuseHeader, efuseExtHdr, efuseData;
479 u8 offset, wden;
480 u16 i, total, used;
481 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
482
483 /* Do NOT excess total size of EFuse table.
484 Added by Roger, 2008.11.10. */
485 if ((_offset + _size_byte) > EFUSE_BT_MAP_LEN) {
486 DBG_8723A("%s: Invalid offset(%#x) with read bytes(%#x)!!\n",
487 __func__, _offset, _size_byte);
488 return;
489 }
490
491 efuseTbl = kmalloc(EFUSE_BT_MAP_LEN, GFP_KERNEL);
492 if (!efuseTbl)
493 return;
494 /* 0xff will be efuse default value instead of 0x00. */
495 memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN);
496
497 EFUSE_GetEfuseDefinition23a(padapter, EFUSE_BT,
498 TYPE_AVAILABLE_EFUSE_BYTES_BANK, &total);
499
500 for (bank = 1; bank < EFUSE_MAX_BANK; bank++) {
501 if (hal_EfuseSwitchToBank(padapter, bank) == false) {
502 DBG_8723A("%s: hal_EfuseSwitchToBank Fail!!\n",
503 __func__);
504 goto exit;
505 }
506
507 eFuse_Addr = 0;
508
509 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
510 ReadEFuseByte23a(padapter, eFuse_Addr++, &efuseHeader);
511 if (efuseHeader == 0xFF)
512 break;
513
514 /* Check PG header for section num. */
515 if (EXT_HEADER(efuseHeader)) { /* extended header */
516 offset = GET_HDR_OFFSET_2_0(efuseHeader);
517
518 ReadEFuseByte23a(padapter, eFuse_Addr++,
519 &efuseExtHdr);
520 if (ALL_WORDS_DISABLED(efuseExtHdr))
521 continue;
522
523 offset |= ((efuseExtHdr & 0xF0) >> 1);
524 wden = efuseExtHdr & 0x0F;
525 } else {
526 offset = (efuseHeader >> 4) & 0x0f;
527 wden = efuseHeader & 0x0f;
528 }
529
530 if (offset < EFUSE_BT_MAX_SECTION) {
531 u16 addr;
532
533 /* Get word enable value from PG header */
534
535 addr = offset * PGPKT_DATA_SIZE;
536 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
537 /* Check word enable condition in
538 the section */
539 if (!(wden & (0x01 << i))) {
540 ReadEFuseByte23a(padapter,
541 eFuse_Addr++,
542 &efuseData);
543 efuseTbl[addr] = efuseData;
544
545 ReadEFuseByte23a(padapter,
546 eFuse_Addr++,
547 &efuseData);
548 efuseTbl[addr + 1] = efuseData;
549 }
550 addr += 2;
551 }
552 } else {
553 DBG_8723A(KERN_ERR
554 "%s: offset(%d) is illegal!!\n",
555 __func__, offset);
556 eFuse_Addr += Efuse_CalculateWordCnts23a(wden) * 2;
557 }
558 }
559
560 if ((eFuse_Addr - 1) < total) {
561 DBG_8723A("%s: bank(%d) data end at %#x\n",
562 __func__, bank, eFuse_Addr - 1);
563 break;
564 }
565 }
566
567 /* switch bank back to bank 0 for later BT and wifi use. */
568 hal_EfuseSwitchToBank(padapter, 0);
569
570 /* Copy from Efuse map to output pointer memory!!! */
571 for (i = 0; i < _size_byte; i++)
572 pbuf[i] = efuseTbl[_offset + i];
573
574 /* */
575 /* Calculate Efuse utilization. */
576 /* */
577 EFUSE_GetEfuseDefinition23a(padapter, EFUSE_BT,
578 TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total);
579 used = (EFUSE_BT_REAL_BANK_CONTENT_LEN * (bank - 1)) + eFuse_Addr - 1;
580 pHalData->BTEfuseUsedBytes = used;
581
582 exit:
583 kfree(efuseTbl);
584 }
585
586 void
587 rtl8723a_readefuse(struct rtw_adapter *padapter,
588 u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf)
589 {
590 if (efuseType == EFUSE_WIFI)
591 hal_ReadEFuse_WiFi(padapter, _offset, _size_byte, pbuf);
592 else
593 hal_ReadEFuse_BT(padapter, _offset, _size_byte, pbuf);
594 }
595
596 u16 rtl8723a_EfuseGetCurrentSize_WiFi(struct rtw_adapter *padapter)
597 {
598 u16 efuse_addr = 0;
599 u8 hoffset = 0, hworden = 0;
600 u8 efuse_data, word_cnts = 0;
601 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
602
603 efuse_addr = pHalData->EfuseUsedBytes;
604
605 DBG_8723A("%s: start_efuse_addr = 0x%X\n", __func__, efuse_addr);
606
607 /* switch bank back to bank 0 for later BT and wifi use. */
608 hal_EfuseSwitchToBank(padapter, 0);
609
610 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
611 if (efuse_OneByteRead23a(padapter, efuse_addr, &efuse_data) ==
612 _FAIL) {
613 DBG_8723A(KERN_ERR "%s: efuse_OneByteRead23a Fail! "
614 "addr = 0x%X !!\n", __func__, efuse_addr);
615 break;
616 }
617
618 if (efuse_data == 0xFF)
619 break;
620
621 if (EXT_HEADER(efuse_data)) {
622 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
623 efuse_addr++;
624 efuse_OneByteRead23a(padapter, efuse_addr, &efuse_data);
625 if (ALL_WORDS_DISABLED(efuse_data))
626 continue;
627
628 hoffset |= ((efuse_data & 0xF0) >> 1);
629 hworden = efuse_data & 0x0F;
630 } else {
631 hoffset = (efuse_data >> 4) & 0x0F;
632 hworden = efuse_data & 0x0F;
633 }
634
635 word_cnts = Efuse_CalculateWordCnts23a(hworden);
636 efuse_addr += (word_cnts * 2) + 1;
637 }
638
639 pHalData->EfuseUsedBytes = efuse_addr;
640
641 DBG_8723A("%s: CurrentSize =%d\n", __func__, efuse_addr);
642
643 return efuse_addr;
644 }
645
646 u16 rtl8723a_EfuseGetCurrentSize_BT(struct rtw_adapter *padapter)
647 {
648 u16 btusedbytes;
649 u16 efuse_addr;
650 u8 bank, startBank;
651 u8 hoffset = 0, hworden = 0;
652 u8 efuse_data, word_cnts = 0;
653 u16 retU2 = 0;
654 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
655
656 btusedbytes = pHalData->BTEfuseUsedBytes;
657
658 efuse_addr = (u16) ((btusedbytes % EFUSE_BT_REAL_BANK_CONTENT_LEN));
659 startBank = (u8) (1 + (btusedbytes / EFUSE_BT_REAL_BANK_CONTENT_LEN));
660
661 DBG_8723A("%s: start from bank =%d addr = 0x%X\n", __func__, startBank,
662 efuse_addr);
663
664 EFUSE_GetEfuseDefinition23a(padapter, EFUSE_BT,
665 TYPE_AVAILABLE_EFUSE_BYTES_BANK, &retU2);
666
667 for (bank = startBank; bank < EFUSE_MAX_BANK; bank++) {
668 if (hal_EfuseSwitchToBank(padapter, bank) == false) {
669 DBG_8723A(KERN_ERR "%s: switch bank(%d) Fail!!\n",
670 __func__, bank);
671 bank = EFUSE_MAX_BANK;
672 break;
673 }
674
675 /* only when bank is switched we have to reset
676 the efuse_addr. */
677 if (bank != startBank)
678 efuse_addr = 0;
679
680 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
681 if (efuse_OneByteRead23a(padapter, efuse_addr,
682 &efuse_data) == _FAIL) {
683 DBG_8723A(KERN_ERR "%s: efuse_OneByteRead23a Fail!"
684 " addr = 0x%X !!\n",
685 __func__, efuse_addr);
686 bank = EFUSE_MAX_BANK;
687 break;
688 }
689
690 if (efuse_data == 0xFF)
691 break;
692
693 if (EXT_HEADER(efuse_data)) {
694 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
695 efuse_addr++;
696 efuse_OneByteRead23a(padapter, efuse_addr,
697 &efuse_data);
698 if (ALL_WORDS_DISABLED(efuse_data)) {
699 efuse_addr++;
700 continue;
701 }
702
703 hoffset |= ((efuse_data & 0xF0) >> 1);
704 hworden = efuse_data & 0x0F;
705 } else {
706 hoffset = (efuse_data >> 4) & 0x0F;
707 hworden = efuse_data & 0x0F;
708 }
709 word_cnts = Efuse_CalculateWordCnts23a(hworden);
710 /* read next header */
711 efuse_addr += (word_cnts * 2) + 1;
712 }
713
714 /* Check if we need to check next bank efuse */
715 if (efuse_addr < retU2)
716 break; /* don't need to check next bank. */
717 }
718
719 retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr;
720 pHalData->BTEfuseUsedBytes = retU2;
721
722 DBG_8723A("%s: CurrentSize =%d\n", __func__, retU2);
723 return retU2;
724 }
725
726 void rtl8723a_read_chip_version(struct rtw_adapter *padapter)
727 {
728 u32 value32;
729 struct hal_version ChipVersion;
730 struct hal_data_8723a *pHalData;
731
732 pHalData = GET_HAL_DATA(padapter);
733
734 value32 = rtl8723au_read32(padapter, REG_SYS_CFG);
735 ChipVersion.ICType = CHIP_8723A;
736 ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
737 pHalData->rf_type = RF_1T1R;
738 ChipVersion.VendorType =
739 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
740 ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK) >> CHIP_VER_RTL_SHIFT; /* IC version (CUT) */
741
742 /* For regulator mode. by tynli. 2011.01.14 */
743 pHalData->RegulatorMode = ((value32 & SPS_SEL) ?
744 RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
745
746 value32 = rtl8723au_read32(padapter, REG_GPIO_OUTSTS);
747 /* ROM code version. */
748 ChipVersion.ROMVer = (value32 & RF_RL_ID) >> 20;
749
750 /* For multi-function consideration. Added by Roger, 2010.10.06. */
751 pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
752 value32 = rtl8723au_read32(padapter, REG_MULTI_FUNC_CTRL);
753 pHalData->MultiFunc |=
754 ((value32 & WL_FUNC_EN) ? RT_MULTI_FUNC_WIFI : 0);
755 pHalData->MultiFunc |= ((value32 & BT_FUNC_EN) ? RT_MULTI_FUNC_BT : 0);
756 pHalData->MultiFunc |=
757 ((value32 & GPS_FUNC_EN) ? RT_MULTI_FUNC_GPS : 0);
758 pHalData->PolarityCtl =
759 ((value32 & WL_HWPDN_SL) ? RT_POLARITY_HIGH_ACT :
760 RT_POLARITY_LOW_ACT);
761 pHalData->VersionID = ChipVersion;
762
763 MSG_8723A("RF_Type is %x!!\n", pHalData->rf_type);
764 }
765
766 /* */
767 /* */
768 /* 20100209 Joseph: */
769 /* This function is used only for 92C to set REG_BCN_CTRL(0x550) register. */
770 /* We just reserve the value of the register in variable
771 pHalData->RegBcnCtrlVal and then operate */
772 /* the value of the register via atomic operation. */
773 /* This prevents from race condition when setting this register. */
774 /* The value of pHalData->RegBcnCtrlVal is initialized in
775 HwConfigureRTL8192CE() function. */
776 /* */
777 void SetBcnCtrlReg23a(struct rtw_adapter *padapter, u8 SetBits, u8 ClearBits)
778 {
779 u8 val8;
780
781 val8 = rtl8723au_read8(padapter, REG_BCN_CTRL);
782 val8 |= SetBits;
783 val8 &= ~ClearBits;
784
785 rtl8723au_write8(padapter, REG_BCN_CTRL, val8);
786 }
787
788 void rtl8723a_InitBeaconParameters(struct rtw_adapter *padapter)
789 {
790 rtl8723au_write16(padapter, REG_BCN_CTRL, 0x1010);
791
792 /* TODO: Remove these magic number */
793 rtl8723au_write16(padapter, REG_TBTT_PROHIBIT, 0x6404); /* ms */
794 /* Firmware will control REG_DRVERLYINT when power saving is enable, */
795 /* so don't set this register on STA mode. */
796 if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == false)
797 rtl8723au_write8(padapter, REG_DRVERLYINT,
798 DRIVER_EARLY_INT_TIME);
799 /* 2ms */
800 rtl8723au_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
801
802 /* Suggested by designer timchen. Change beacon AIFS to the
803 largest number beacause test chip does not contension before
804 sending beacon. by tynli. 2009.11.03 */
805 rtl8723au_write16(padapter, REG_BCNTCFG, 0x660F);
806 }
807
808 static void ResumeTxBeacon(struct rtw_adapter *padapter)
809 {
810 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
811
812 /* 2010.03.01. Marked by tynli. No need to call workitem beacause
813 we record the value */
814 /* which should be read from register to a global variable. */
815
816 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, "+ResumeTxBeacon\n");
817
818 pHalData->RegFwHwTxQCtrl |= BIT(6);
819 rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
820 pHalData->RegFwHwTxQCtrl);
821 rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 1, 0xff);
822 pHalData->RegReg542 |= BIT(0);
823 rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542);
824 }
825
826 static void StopTxBeacon(struct rtw_adapter *padapter)
827 {
828 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
829
830 /* 2010.03.01. Marked by tynli. No need to call workitem beacause
831 we record the value */
832 /* which should be read from register to a global variable. */
833
834 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, "+StopTxBeacon\n");
835
836 pHalData->RegFwHwTxQCtrl &= ~BIT(6);
837 rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
838 pHalData->RegFwHwTxQCtrl);
839 rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 1, 0x64);
840 pHalData->RegReg542 &= ~BIT(0);
841 rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542);
842 }
843
844 static void _BeaconFunctionEnable(struct rtw_adapter *padapter, u8 Enable,
845 u8 Linked)
846 {
847 SetBcnCtrlReg23a(padapter, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB,
848 0);
849 rtl8723au_write8(padapter, REG_RD_CTRL + 1, 0x6F);
850 }
851
852 void rtl8723a_SetBeaconRelatedRegisters(struct rtw_adapter *padapter)
853 {
854 u32 value32;
855 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
856 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
857
858 /* reset TSF, enable update TSF, correcting TSF On Beacon */
859
860 /* REG_BCN_INTERVAL */
861 /* REG_BCNDMATIM */
862 /* REG_ATIMWND */
863 /* REG_TBTT_PROHIBIT */
864 /* REG_DRVERLYINT */
865 /* REG_BCN_MAX_ERR */
866 /* REG_BCNTCFG (0x510) */
867 /* REG_DUAL_TSF_RST */
868 /* REG_BCN_CTRL (0x550) */
869
870 /* */
871 /* ATIM window */
872 /* */
873 rtl8723au_write16(padapter, REG_ATIMWND, 2);
874
875 /* */
876 /* Beacon interval (in unit of TU). */
877 /* */
878 rtl8723au_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
879
880 rtl8723a_InitBeaconParameters(padapter);
881
882 rtl8723au_write8(padapter, REG_SLOT, 0x09);
883
884 /* */
885 /* Reset TSF Timer to zero, added by Roger. 2008.06.24 */
886 /* */
887 value32 = rtl8723au_read32(padapter, REG_TCR);
888 value32 &= ~TSFRST;
889 rtl8723au_write32(padapter, REG_TCR, value32);
890
891 value32 |= TSFRST;
892 rtl8723au_write32(padapter, REG_TCR, value32);
893
894 /* NOTE: Fix test chip's bug (about contention windows's randomness) */
895 if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE |
896 WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE) == true) {
897 rtl8723au_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
898 rtl8723au_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
899 }
900
901 _BeaconFunctionEnable(padapter, true, true);
902
903 ResumeTxBeacon(padapter);
904 SetBcnCtrlReg23a(padapter, DIS_BCNQ_SUB, 0);
905 }
906
907 void rtl8723a_SetHalODMVar(struct rtw_adapter *Adapter,
908 enum hal_odm_variable eVariable,
909 void *pValue1, bool bSet)
910 {
911 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
912 struct dm_odm_t *podmpriv = &pHalData->odmpriv;
913 switch (eVariable) {
914 case HAL_ODM_STA_INFO:
915 {
916 struct sta_info *psta = (struct sta_info *)pValue1;
917
918 if (bSet) {
919 DBG_8723A("Set STA_(%d) info\n", psta->mac_id);
920 ODM_CmnInfoPtrArrayHook23a(podmpriv,
921 ODM_CMNINFO_STA_STATUS,
922 psta->mac_id, psta);
923 } else {
924 DBG_8723A("Clean STA_(%d) info\n", psta->mac_id);
925 ODM_CmnInfoPtrArrayHook23a(podmpriv,
926 ODM_CMNINFO_STA_STATUS,
927 psta->mac_id, NULL);
928 }
929 }
930 break;
931 case HAL_ODM_P2P_STATE:
932 ODM_CmnInfoUpdate23a(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
933 break;
934 case HAL_ODM_WIFI_DISPLAY_STATE:
935 ODM_CmnInfoUpdate23a(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
936 break;
937 default:
938 break;
939 }
940 }
941
942 void rtl8723a_notch_filter(struct rtw_adapter *adapter, bool enable)
943 {
944 if (enable) {
945 DBG_8723A("Enable notch filter\n");
946 rtl8723au_write8(adapter, rOFDM0_RxDSP + 1,
947 rtl8723au_read8(adapter, rOFDM0_RxDSP + 1) |
948 BIT(1));
949 } else {
950 DBG_8723A("Disable notch filter\n");
951 rtl8723au_write8(adapter, rOFDM0_RxDSP + 1,
952 rtl8723au_read8(adapter, rOFDM0_RxDSP + 1) &
953 ~BIT(1));
954 }
955 }
956
957 bool c2h_id_filter_ccx_8723a(u8 id)
958 {
959 bool ret = false;
960 if (id == C2H_CCX_TX_RPT)
961 ret = true;
962
963 return ret;
964 }
965
966 int c2h_handler_8723a(struct rtw_adapter *padapter, struct c2h_evt_hdr *c2h_evt)
967 {
968 int ret = _SUCCESS;
969 u8 i = 0;
970
971 if (c2h_evt == NULL) {
972 DBG_8723A("%s c2h_evt is NULL\n", __func__);
973 ret = _FAIL;
974 goto exit;
975 }
976
977 switch (c2h_evt->id) {
978 case C2H_DBG:
979 RT_TRACE(_module_hal_init_c_, _drv_info_,
980 "C2HCommandHandler: %s\n", c2h_evt->payload);
981 break;
982
983 case C2H_CCX_TX_RPT:
984 handle_txrpt_ccx_8723a(padapter, c2h_evt->payload);
985 break;
986 case C2H_EXT_RA_RPT:
987 break;
988 case C2H_HW_INFO_EXCH:
989 RT_TRACE(_module_hal_init_c_, _drv_info_,
990 "[BT], C2H_HW_INFO_EXCH\n");
991 for (i = 0; i < c2h_evt->plen; i++) {
992 RT_TRACE(_module_hal_init_c_, _drv_info_,
993 "[BT], tmpBuf[%d]= 0x%x\n", i,
994 c2h_evt->payload[i]);
995 }
996 break;
997
998 case C2H_C2H_H2C_TEST:
999 RT_TRACE(_module_hal_init_c_, _drv_info_,
1000 "[BT], C2H_H2C_TEST\n");
1001 RT_TRACE(_module_hal_init_c_, _drv_info_,
1002 "[BT], tmpBuf[0]/[1]/[2]/[3]/[4]= 0x%x/ 0x%x/ 0x%x/ 0x%x/ 0x%x\n",
1003 c2h_evt->payload[0],
1004 c2h_evt->payload[1], c2h_evt->payload[2],
1005 c2h_evt->payload[3], c2h_evt->payload[4]);
1006 break;
1007
1008 case C2H_BT_INFO:
1009 DBG_8723A("%s , Got C2H_BT_INFO \n", __func__);
1010 rtl8723a_fw_c2h_BT_info(padapter,
1011 c2h_evt->payload, c2h_evt->plen);
1012 break;
1013
1014 default:
1015 ret = _FAIL;
1016 break;
1017 }
1018
1019 exit:
1020 return ret;
1021 }
1022
1023 void handle_txrpt_ccx_8723a(struct rtw_adapter *adapter, void *buf)
1024 {
1025 struct txrpt_ccx_8723a *txrpt_ccx = buf;
1026 struct submit_ctx *pack_tx_ops = &adapter->xmitpriv.ack_tx_ops;
1027
1028 if (txrpt_ccx->int_ccx && adapter->xmitpriv.ack_tx) {
1029 if (txrpt_ccx->pkt_ok)
1030 rtw23a_sctx_done_err(&pack_tx_ops,
1031 RTW_SCTX_DONE_SUCCESS);
1032 else
1033 rtw23a_sctx_done_err(&pack_tx_ops,
1034 RTW_SCTX_DONE_CCX_PKT_FAIL);
1035 }
1036 }
1037
1038 void rtl8723a_InitAntenna_Selection(struct rtw_adapter *padapter)
1039 {
1040 u8 val;
1041
1042 val = rtl8723au_read8(padapter, REG_LEDCFG2);
1043 /* Let 8051 take control antenna setting */
1044 val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */
1045 rtl8723au_write8(padapter, REG_LEDCFG2, val);
1046 }
1047
1048 void rtl8723a_CheckAntenna_Selection(struct rtw_adapter *padapter)
1049 {
1050 u8 val;
1051
1052 val = rtl8723au_read8(padapter, REG_LEDCFG2);
1053 /* Let 8051 take control antenna setting */
1054 if (!(val & BIT(7))) {
1055 val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */
1056 rtl8723au_write8(padapter, REG_LEDCFG2, val);
1057 }
1058 }
1059
1060 void rtl8723a_DeinitAntenna_Selection(struct rtw_adapter *padapter)
1061 {
1062 u8 val;
1063
1064 val = rtl8723au_read8(padapter, REG_LEDCFG2);
1065 /* Let 8051 take control antenna setting */
1066 val &= ~BIT(7); /* DPDT_SEL_EN, clear 0x4C[23] */
1067 rtl8723au_write8(padapter, REG_LEDCFG2, val);
1068 }
1069
1070 void rtl8723a_init_default_value(struct rtw_adapter *padapter)
1071 {
1072 struct hal_data_8723a *pHalData;
1073 struct dm_priv *pdmpriv;
1074 u8 i;
1075
1076 pHalData = GET_HAL_DATA(padapter);
1077 pdmpriv = &pHalData->dmpriv;
1078
1079 /* init default value */
1080 pHalData->bIQKInitialized = false;
1081 if (!padapter->pwrctrlpriv.bkeepfwalive)
1082 pHalData->LastHMEBoxNum = 0;
1083
1084 pHalData->bIQKInitialized = false;
1085
1086 /* init dm default value */
1087 pdmpriv->TM_Trigger = 0; /* for IQK */
1088 /* pdmpriv->binitialized = false; */
1089 /* pdmpriv->prv_traffic_idx = 3; */
1090 /* pdmpriv->initialize = 0; */
1091
1092 pdmpriv->ThermalValue_HP_index = 0;
1093 for (i = 0; i < HP_THERMAL_NUM; i++)
1094 pdmpriv->ThermalValue_HP[i] = 0;
1095
1096 /* init Efuse variables */
1097 pHalData->EfuseUsedBytes = 0;
1098 pHalData->BTEfuseUsedBytes = 0;
1099 }
1100
1101 u8 GetEEPROMSize8723A(struct rtw_adapter *padapter)
1102 {
1103 u8 size = 0;
1104 u32 cr;
1105
1106 cr = rtl8723au_read16(padapter, REG_9346CR);
1107 /* 6: EEPROM used is 93C46, 4: boot from E-Fuse. */
1108 size = (cr & BOOT_FROM_EEPROM) ? 6 : 4;
1109
1110 MSG_8723A("EEPROM type is %s\n", size == 4 ? "E-FUSE" : "93C46");
1111
1112 return size;
1113 }
1114
1115 /* */
1116 /* */
1117 /* LLT R/W/Init function */
1118 /* */
1119 /* */
1120 static int _LLTWrite(struct rtw_adapter *padapter, u32 address, u32 data)
1121 {
1122 int status = _SUCCESS;
1123 s32 count = 0;
1124 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
1125 _LLT_OP(_LLT_WRITE_ACCESS);
1126 u16 LLTReg = REG_LLT_INIT;
1127
1128 rtl8723au_write32(padapter, LLTReg, value);
1129
1130 /* polling */
1131 do {
1132 value = rtl8723au_read32(padapter, LLTReg);
1133 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
1134 break;
1135
1136 if (count > POLLING_LLT_THRESHOLD) {
1137 RT_TRACE(_module_hal_init_c_, _drv_err_,
1138 "Failed to polling write LLT done at address %d!\n",
1139 address);
1140 status = _FAIL;
1141 break;
1142 }
1143 } while (count++);
1144
1145 return status;
1146 }
1147
1148 int InitLLTTable23a(struct rtw_adapter *padapter, u32 boundary)
1149 {
1150 int status = _SUCCESS;
1151 u32 i;
1152 u32 txpktbuf_bndy = boundary;
1153 u32 Last_Entry_Of_TxPktBuf = LAST_ENTRY_OF_TX_PKT_BUFFER;
1154
1155 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
1156 status = _LLTWrite(padapter, i, i + 1);
1157 if (status != _SUCCESS)
1158 return status;
1159 }
1160
1161 /* end of list */
1162 status = _LLTWrite(padapter, (txpktbuf_bndy - 1), 0xFF);
1163 if (status != _SUCCESS)
1164 return status;
1165
1166 /* Make the other pages as ring buffer */
1167 /* This ring buffer is used as beacon buffer if we config this
1168 MAC as two MAC transfer. */
1169 /* Otherwise used as local loopback buffer. */
1170 for (i = txpktbuf_bndy; i < Last_Entry_Of_TxPktBuf; i++) {
1171 status = _LLTWrite(padapter, i, (i + 1));
1172 if (_SUCCESS != status)
1173 return status;
1174 }
1175
1176 /* Let last entry point to the start entry of ring buffer */
1177 status = _LLTWrite(padapter, Last_Entry_Of_TxPktBuf, txpktbuf_bndy);
1178
1179 return status;
1180 }
1181
1182 static void _DisableGPIO(struct rtw_adapter *padapter)
1183 {
1184 /***************************************
1185 j. GPIO_PIN_CTRL 0x44[31:0]= 0x000
1186 k.Value = GPIO_PIN_CTRL[7:0]
1187 l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write external PIN level
1188 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1189 n. LEDCFG 0x4C[15:0] = 0x8080
1190 ***************************************/
1191 u32 value32;
1192 u32 u4bTmp;
1193
1194 /* 1. Disable GPIO[7:0] */
1195 rtl8723au_write16(padapter, REG_GPIO_PIN_CTRL + 2, 0x0000);
1196 value32 = rtl8723au_read32(padapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1197 u4bTmp = value32 & 0x000000FF;
1198 value32 |= ((u4bTmp << 8) | 0x00FF0000);
1199 rtl8723au_write32(padapter, REG_GPIO_PIN_CTRL, value32);
1200
1201 /* */
1202 /* <Roger_Notes> For RTL8723u multi-function configuration which
1203 was autoload from Efuse offset 0x0a and 0x0b, */
1204 /* WLAN HW GPIO[9], GPS HW GPIO[10] and BT HW GPIO[11]. */
1205 /* Added by Roger, 2010.10.07. */
1206 /* */
1207 /* 2. Disable GPIO[8] and GPIO[12] */
1208
1209 /* Configure all pins as input mode. */
1210 rtl8723au_write16(padapter, REG_GPIO_IO_SEL_2, 0x0000);
1211 value32 = rtl8723au_read32(padapter, REG_GPIO_PIN_CTRL_2) & 0xFFFF001F;
1212 u4bTmp = value32 & 0x0000001F;
1213 /* Set pin 8, 10, 11 and pin 12 to output mode. */
1214 value32 |= ((u4bTmp << 8) | 0x001D0000);
1215 rtl8723au_write32(padapter, REG_GPIO_PIN_CTRL_2, value32);
1216
1217 /* 3. Disable LED0 & 1 */
1218 rtl8723au_write16(padapter, REG_LEDCFG0, 0x8080);
1219 } /* end of _DisableGPIO() */
1220
1221 static void _DisableRFAFEAndResetBB8192C(struct rtw_adapter *padapter)
1222 {
1223 /**************************************
1224 a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue
1225 b. RF path 0 offset 0x00 = 0x00 disable RF
1226 c. APSD_CTRL 0x600[7:0] = 0x40
1227 d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine
1228 e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine
1229 ***************************************/
1230 u8 value8;
1231
1232 rtl8723au_write8(padapter, REG_TXPAUSE, 0xFF);
1233
1234 PHY_SetRFReg(padapter, RF_PATH_A, 0x0, bMaskByte0, 0x0);
1235
1236 value8 = APSDOFF;
1237 rtl8723au_write8(padapter, REG_APSD_CTRL, value8); /* 0x40 */
1238
1239 /* Set BB reset at first */
1240 value8 = FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn;
1241 rtl8723au_write8(padapter, REG_SYS_FUNC_EN, value8); /* 0x16 */
1242
1243 /* Set global reset. */
1244 value8 &= ~FEN_BB_GLB_RSTn;
1245 rtl8723au_write8(padapter, REG_SYS_FUNC_EN, value8); /* 0x14 */
1246
1247 /* 2010/08/12 MH We need to set BB/GLBAL reset to save power
1248 for SS mode. */
1249 }
1250
1251 static void _ResetDigitalProcedure1_92C(struct rtw_adapter *padapter,
1252 bool bWithoutHWSM)
1253 {
1254 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1255
1256 if (IS_FW_81xxC(padapter) && (pHalData->FirmwareVersion <= 0x20)) {
1257 /*****************************
1258 f. MCUFWDL 0x80[7:0]= 0 reset MCU ready status
1259 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU register, (8051 reset)
1260 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC register, DCORE
1261 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU register,
1262 (8051 enable)
1263 ******************************/
1264 u16 valu16;
1265 rtl8723au_write8(padapter, REG_MCUFWDL, 0);
1266
1267 valu16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN);
1268 /* reset MCU , 8051 */
1269 rtl8723au_write16(padapter, REG_SYS_FUNC_EN,
1270 valu16 & ~FEN_CPUEN);
1271
1272 valu16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN) & 0x0FFF;
1273 /* reset MAC */
1274 rtl8723au_write16(padapter, REG_SYS_FUNC_EN,
1275 valu16 | FEN_HWPDN | FEN_ELDR);
1276
1277 valu16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN);
1278 /* enable MCU , 8051 */
1279 rtl8723au_write16(padapter, REG_SYS_FUNC_EN,
1280 valu16 | FEN_CPUEN);
1281 } else {
1282 u8 retry_cnts = 0;
1283 u8 val8;
1284
1285 val8 = rtl8723au_read8(padapter, REG_MCUFWDL);
1286
1287 /* 2010/08/12 MH For USB SS, we can not stop 8051 when we
1288 are trying to enter IPS/HW&SW radio off. For
1289 S3/S4/S5/Disable, we can stop 8051 because */
1290 /* we will init FW when power on again. */
1291 /* If we want to SS mode, we can not reset 8051. */
1292 if ((val8 & BIT(1)) && padapter->bFWReady) {
1293 /* IF fw in RAM code, do reset */
1294 /* 2010/08/25 MH According to RD alfred's
1295 suggestion, we need to disable other */
1296 /* HRCV INT to influence 8051 reset. */
1297 rtl8723au_write8(padapter, REG_FWIMR, 0x20);
1298 /* 2011/02/15 MH According to Alex's
1299 suggestion, close mask to prevent
1300 incorrect FW write operation. */
1301 rtl8723au_write8(padapter, REG_FTIMR, 0x00);
1302 rtl8723au_write8(padapter, REG_FSIMR, 0x00);
1303
1304 /* 8051 reset by self */
1305 rtl8723au_write8(padapter, REG_HMETFR + 3, 0x20);
1306
1307 while ((retry_cnts++ < 100) &&
1308 (rtl8723au_read16(padapter, REG_SYS_FUNC_EN) &
1309 FEN_CPUEN)) {
1310 udelay(50); /* us */
1311 }
1312
1313 if (retry_cnts >= 100) {
1314 /* Reset MAC and Enable 8051 */
1315 rtl8723au_write8(padapter,
1316 REG_SYS_FUNC_EN + 1, 0x50);
1317 mdelay(10);
1318 }
1319 }
1320 /* Reset MAC and Enable 8051 */
1321 rtl8723au_write8(padapter, REG_SYS_FUNC_EN + 1, 0x54);
1322 rtl8723au_write8(padapter, REG_MCUFWDL, 0);
1323 }
1324
1325 if (bWithoutHWSM) {
1326 /*****************************
1327 Without HW auto state machine
1328 g. SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock
1329 h. AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL
1330 i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK
1331 j. SYS_ISO_CTRL 0x00[7:0] = 0xF9 isolated digital to PON
1332 ******************************/
1333 /* modify to 0x70A3 by Scott. */
1334 rtl8723au_write16(padapter, REG_SYS_CLKR, 0x70A3);
1335 rtl8723au_write8(padapter, REG_AFE_PLL_CTRL, 0x80);
1336 rtl8723au_write16(padapter, REG_AFE_XTAL_CTRL, 0x880F);
1337 rtl8723au_write8(padapter, REG_SYS_ISO_CTRL, 0xF9);
1338 } else {
1339 /* Disable all RF/BB power */
1340 rtl8723au_write8(padapter, REG_RF_CTRL, 0x00);
1341 }
1342 }
1343
1344 static void _ResetDigitalProcedure2(struct rtw_adapter *padapter)
1345 {
1346 /*****************************
1347 k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction
1348 l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock
1349 m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
1350 ******************************/
1351 /* modify to 0x70a3 by Scott. */
1352 rtl8723au_write16(padapter, REG_SYS_CLKR, 0x70a3);
1353 /* modify to 0x82 by Scott. */
1354 rtl8723au_write8(padapter, REG_SYS_ISO_CTRL + 1, 0x82);
1355 }
1356
1357 static void _DisableAnalog(struct rtw_adapter *padapter, bool bWithoutHWSM)
1358 {
1359 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1360 u16 value16;
1361 u8 value8;
1362
1363 if (bWithoutHWSM) {
1364 /*****************************
1365 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power
1366 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1367 r. When driver call disable, the ASIC will turn off remaining
1368 clock automatically
1369 ******************************/
1370
1371 rtl8723au_write8(padapter, REG_LDOA15_CTRL, 0x04);
1372 /* rtl8723au_write8(padapter, REG_LDOV12D_CTRL, 0x54); */
1373
1374 value8 = rtl8723au_read8(padapter, REG_LDOV12D_CTRL);
1375 value8 &= ~LDV12_EN;
1376 rtl8723au_write8(padapter, REG_LDOV12D_CTRL, value8);
1377 }
1378
1379 /*****************************
1380 h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode
1381 i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend
1382 ******************************/
1383 value8 = 0x23;
1384 if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
1385 value8 |= BIT(3);
1386
1387 rtl8723au_write8(padapter, REG_SPS0_CTRL, value8);
1388
1389 if (bWithoutHWSM) {
1390 /* value16 |= (APDM_HOST | FSM_HSUS |/PFM_ALDN); */
1391 /* 2010/08/31 According to Filen description, we need to
1392 use HW to shut down 8051 automatically. */
1393 /* Because suspend operation need the asistance of 8051
1394 to wait for 3ms. */
1395 value16 = APDM_HOST | AFSM_HSUS | PFM_ALDN;
1396 } else {
1397 value16 = APDM_HOST | AFSM_HSUS | PFM_ALDN;
1398 }
1399
1400 rtl8723au_write16(padapter, REG_APS_FSMCO, value16); /* 0x4802 */
1401
1402 rtl8723au_write8(padapter, REG_RSV_CTRL, 0x0e);
1403 }
1404
1405 /* HW Auto state machine */
1406 int CardDisableHWSM(struct rtw_adapter *padapter, u8 resetMCU)
1407 {
1408 if (padapter->bSurpriseRemoved)
1409 return _SUCCESS;
1410
1411 /* RF Off Sequence ==== */
1412 _DisableRFAFEAndResetBB8192C(padapter);
1413
1414 /* ==== Reset digital sequence ====== */
1415 _ResetDigitalProcedure1_92C(padapter, false);
1416
1417 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1418 _DisableGPIO(padapter);
1419
1420 /* ==== Disable analog sequence === */
1421 _DisableAnalog(padapter, false);
1422
1423 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1424 "======> Card disable finished.\n");
1425
1426 return _SUCCESS;
1427 }
1428
1429 /* without HW Auto state machine */
1430 int CardDisableWithoutHWSM(struct rtw_adapter *padapter)
1431 {
1432 if (padapter->bSurpriseRemoved)
1433 return _SUCCESS;
1434
1435 /* RF Off Sequence ==== */
1436 _DisableRFAFEAndResetBB8192C(padapter);
1437
1438 /* ==== Reset digital sequence ====== */
1439 _ResetDigitalProcedure1_92C(padapter, true);
1440
1441 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1442 _DisableGPIO(padapter);
1443
1444 /* ==== Reset digital sequence ====== */
1445 _ResetDigitalProcedure2(padapter);
1446
1447 /* ==== Disable analog sequence === */
1448 _DisableAnalog(padapter, true);
1449
1450 return _SUCCESS;
1451 }
1452
1453 void Hal_InitPGData(struct rtw_adapter *padapter, u8 *PROMContent)
1454 {
1455 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1456
1457 if (!pEEPROM->bautoload_fail_flag) { /* autoload OK. */
1458 if (!pEEPROM->EepromOrEfuse) {
1459 /* Read EFUSE real map to shadow. */
1460 EFUSE_ShadowMapUpdate23a(padapter, EFUSE_WIFI);
1461 memcpy(PROMContent, pEEPROM->efuse_eeprom_data,
1462 HWSET_MAX_SIZE);
1463 }
1464 } else {
1465 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
1466 "AutoLoad Fail reported from CR9346!!\n");
1467 /* update to default value 0xFF */
1468 if (!pEEPROM->EepromOrEfuse)
1469 EFUSE_ShadowMapUpdate23a(padapter, EFUSE_WIFI);
1470 memcpy(PROMContent, pEEPROM->efuse_eeprom_data,
1471 HWSET_MAX_SIZE);
1472 }
1473 }
1474
1475 void Hal_EfuseParseIDCode(struct rtw_adapter *padapter, u8 *hwinfo)
1476 {
1477 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1478 /* struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter); */
1479 u16 EEPROMId;
1480
1481 /* Checl 0x8129 again for making sure autoload status!! */
1482 EEPROMId = le16_to_cpu(*((__le16 *) hwinfo));
1483 if (EEPROMId != RTL_EEPROM_ID) {
1484 DBG_8723A("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
1485 pEEPROM->bautoload_fail_flag = true;
1486 } else {
1487 pEEPROM->bautoload_fail_flag = false;
1488 }
1489
1490 RT_TRACE(_module_hal_init_c_, _drv_info_,
1491 "EEPROM ID = 0x%04x\n", EEPROMId);
1492 }
1493
1494 static void
1495 Hal_ReadPowerValueFromPROM_8723A(struct txpowerinfo *pwrInfo,
1496 u8 *PROMContent, bool AutoLoadFail)
1497 {
1498 u32 rfPath, eeAddr, group, rfPathMax = 1;
1499
1500 memset(pwrInfo, 0, sizeof(*pwrInfo));
1501
1502 if (AutoLoadFail) {
1503 for (group = 0; group < MAX_CHNL_GROUP; group++) {
1504 for (rfPath = 0; rfPath < rfPathMax; rfPath++) {
1505 pwrInfo->CCKIndex[rfPath][group] =
1506 EEPROM_Default_TxPowerLevel;
1507 pwrInfo->HT40_1SIndex[rfPath][group] =
1508 EEPROM_Default_TxPowerLevel;
1509 pwrInfo->HT40_2SIndexDiff[rfPath][group] =
1510 EEPROM_Default_HT40_2SDiff;
1511 pwrInfo->HT20IndexDiff[rfPath][group] =
1512 EEPROM_Default_HT20_Diff;
1513 pwrInfo->OFDMIndexDiff[rfPath][group] =
1514 EEPROM_Default_LegacyHTTxPowerDiff;
1515 pwrInfo->HT40MaxOffset[rfPath][group] =
1516 EEPROM_Default_HT40_PwrMaxOffset;
1517 pwrInfo->HT20MaxOffset[rfPath][group] =
1518 EEPROM_Default_HT20_PwrMaxOffset;
1519 }
1520 }
1521 pwrInfo->TSSI_A[0] = EEPROM_Default_TSSI;
1522 return;
1523 }
1524
1525 for (rfPath = 0; rfPath < rfPathMax; rfPath++) {
1526 for (group = 0; group < MAX_CHNL_GROUP; group++) {
1527 eeAddr =
1528 EEPROM_CCK_TX_PWR_INX_8723A + (rfPath * 3) + group;
1529
1530 pwrInfo->CCKIndex[rfPath][group] = PROMContent[eeAddr];
1531 if (pwrInfo->CCKIndex[rfPath][group] > 63)
1532 pwrInfo->CCKIndex[rfPath][group] =
1533 EEPROM_Default_TxPowerLevel;
1534
1535 eeAddr = EEPROM_HT40_1S_TX_PWR_INX_8723A +
1536 (rfPath * 3) + group;
1537 pwrInfo->HT40_1SIndex[rfPath][group] =
1538 PROMContent[eeAddr];
1539 if (pwrInfo->HT40_1SIndex[rfPath][group] > 63)
1540 pwrInfo->HT40_1SIndex[rfPath][group] =
1541 EEPROM_Default_TxPowerLevel;
1542 }
1543 }
1544
1545 for (group = 0; group < MAX_CHNL_GROUP; group++) {
1546 for (rfPath = 0; rfPath < rfPathMax; rfPath++) {
1547 pwrInfo->HT40_2SIndexDiff[rfPath][group] = 0;
1548 pwrInfo->HT20IndexDiff[rfPath][group] =
1549 (PROMContent
1550 [EEPROM_HT20_TX_PWR_INX_DIFF_8723A +
1551 group] >> (rfPath * 4)) & 0xF;
1552 /* 4bit sign number to 8 bit sign number */
1553 if (pwrInfo->HT20IndexDiff[rfPath][group] & BIT(3))
1554 pwrInfo->HT20IndexDiff[rfPath][group] |= 0xF0;
1555
1556 pwrInfo->OFDMIndexDiff[rfPath][group] =
1557 (PROMContent[EEPROM_OFDM_TX_PWR_INX_DIFF_8723A +
1558 group] >> (rfPath * 4)) & 0xF;
1559
1560 pwrInfo->HT40MaxOffset[rfPath][group] =
1561 (PROMContent[EEPROM_HT40_MAX_PWR_OFFSET_8723A +
1562 group] >> (rfPath * 4)) & 0xF;
1563
1564 pwrInfo->HT20MaxOffset[rfPath][group] =
1565 (PROMContent[EEPROM_HT20_MAX_PWR_OFFSET_8723A +
1566 group] >> (rfPath * 4)) & 0xF;
1567 }
1568 }
1569
1570 pwrInfo->TSSI_A[0] = PROMContent[EEPROM_TSSI_A_8723A];
1571 }
1572
1573 static u8 Hal_GetChnlGroup(u8 chnl)
1574 {
1575 u8 group = 0;
1576
1577 if (chnl < 3) /* Cjanel 1-3 */
1578 group = 0;
1579 else if (chnl < 9) /* Channel 4-9 */
1580 group = 1;
1581 else /* Channel 10-14 */
1582 group = 2;
1583
1584 return group;
1585 }
1586
1587 void
1588 Hal_EfuseParsetxpowerinfo_8723A(struct rtw_adapter *padapter,
1589 u8 *PROMContent, bool AutoLoadFail)
1590 {
1591 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1592 struct txpowerinfo pwrInfo;
1593 u8 rfPath, ch, group, rfPathMax = 1;
1594 u8 pwr, diff;
1595
1596 Hal_ReadPowerValueFromPROM_8723A(&pwrInfo, PROMContent, AutoLoadFail);
1597 for (rfPath = 0; rfPath < rfPathMax; rfPath++) {
1598 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1599 group = Hal_GetChnlGroup(ch);
1600
1601 pHalData->TxPwrLevelCck[rfPath][ch] =
1602 pwrInfo.CCKIndex[rfPath][group];
1603 pHalData->TxPwrLevelHT40_1S[rfPath][ch] =
1604 pwrInfo.HT40_1SIndex[rfPath][group];
1605
1606 pHalData->TxPwrHt20Diff[rfPath][ch] =
1607 pwrInfo.HT20IndexDiff[rfPath][group];
1608 pHalData->TxPwrLegacyHtDiff[rfPath][ch] =
1609 pwrInfo.OFDMIndexDiff[rfPath][group];
1610 pHalData->PwrGroupHT20[rfPath][ch] =
1611 pwrInfo.HT20MaxOffset[rfPath][group];
1612 pHalData->PwrGroupHT40[rfPath][ch] =
1613 pwrInfo.HT40MaxOffset[rfPath][group];
1614
1615 pwr = pwrInfo.HT40_1SIndex[rfPath][group];
1616 diff = pwrInfo.HT40_2SIndexDiff[rfPath][group];
1617
1618 pHalData->TxPwrLevelHT40_2S[rfPath][ch] =
1619 (pwr > diff) ? (pwr - diff) : 0;
1620 }
1621 }
1622 for (rfPath = 0; rfPath < RF_PATH_MAX; rfPath++) {
1623 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1624 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1625 "RF(%u)-Ch(%u) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1626 rfPath, ch,
1627 pHalData->TxPwrLevelCck[rfPath][ch],
1628 pHalData->TxPwrLevelHT40_1S[rfPath][ch],
1629 pHalData->TxPwrLevelHT40_2S[rfPath][ch]);
1630
1631 }
1632 }
1633 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1634 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1635 "RF-A Ht20 to HT40 Diff[%u] = 0x%x(%d)\n", ch,
1636 pHalData->TxPwrHt20Diff[RF_PATH_A][ch],
1637 pHalData->TxPwrHt20Diff[RF_PATH_A][ch]);
1638 }
1639 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++)
1640 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1641 "RF-A Legacy to Ht40 Diff[%u] = 0x%x\n", ch,
1642 pHalData->TxPwrLegacyHtDiff[RF_PATH_A][ch]);
1643 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1644 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1645 "RF-B Ht20 to HT40 Diff[%u] = 0x%x(%d)\n", ch,
1646 pHalData->TxPwrHt20Diff[RF_PATH_B][ch],
1647 pHalData->TxPwrHt20Diff[RF_PATH_B][ch]);
1648 }
1649 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++)
1650 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1651 "RF-B Legacy to HT40 Diff[%u] = 0x%x\n", ch,
1652 pHalData->TxPwrLegacyHtDiff[RF_PATH_B][ch]);
1653 if (!AutoLoadFail) {
1654 struct registry_priv *registry_par = &padapter->registrypriv;
1655 if (registry_par->regulatory_tid == 0xff) {
1656 if (PROMContent[RF_OPTION1_8723A] == 0xff)
1657 pHalData->EEPROMRegulatory = 0;
1658 else
1659 pHalData->EEPROMRegulatory =
1660 PROMContent[RF_OPTION1_8723A] & 0x7;
1661 } else {
1662 pHalData->EEPROMRegulatory =
1663 registry_par->regulatory_tid;
1664 }
1665 } else {
1666 pHalData->EEPROMRegulatory = 0;
1667 }
1668 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1669 "EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory);
1670
1671 if (!AutoLoadFail)
1672 pHalData->bTXPowerDataReadFromEEPORM = true;
1673 }
1674
1675 void
1676 Hal_EfuseParseBTCoexistInfo_8723A(struct rtw_adapter *padapter,
1677 u8 *hwinfo, bool AutoLoadFail)
1678 {
1679 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1680 u8 tempval;
1681 u32 tmpu4;
1682
1683 if (!AutoLoadFail) {
1684 tmpu4 = rtl8723au_read32(padapter, REG_MULTI_FUNC_CTRL);
1685 if (tmpu4 & BT_FUNC_EN)
1686 pHalData->EEPROMBluetoothCoexist = 1;
1687 else
1688 pHalData->EEPROMBluetoothCoexist = 0;
1689 pHalData->EEPROMBluetoothType = BT_RTL8723A;
1690
1691 /* The following need to be checked with newer version of */
1692 /* eeprom spec */
1693 tempval = hwinfo[RF_OPTION4_8723A];
1694 pHalData->EEPROMBluetoothAntNum = (tempval & 0x1);
1695 pHalData->EEPROMBluetoothAntIsolation = (tempval & 0x10) >> 4;
1696 pHalData->EEPROMBluetoothRadioShared = (tempval & 0x20) >> 5;
1697 } else {
1698 pHalData->EEPROMBluetoothCoexist = 0;
1699 pHalData->EEPROMBluetoothType = BT_RTL8723A;
1700 pHalData->EEPROMBluetoothAntNum = Ant_x2;
1701 pHalData->EEPROMBluetoothAntIsolation = 0;
1702 pHalData->EEPROMBluetoothRadioShared = BT_Radio_Shared;
1703 }
1704
1705 rtl8723a_BT_init_hal_vars(padapter);
1706 }
1707
1708 void
1709 Hal_EfuseParseEEPROMVer(struct rtw_adapter *padapter,
1710 u8 *hwinfo, bool AutoLoadFail)
1711 {
1712 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1713
1714 if (!AutoLoadFail)
1715 pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_8723A];
1716 else
1717 pHalData->EEPROMVersion = 1;
1718 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1719 "Hal_EfuseParseEEPROMVer(), EEVer = %d\n",
1720 pHalData->EEPROMVersion);
1721 }
1722
1723 void
1724 rtl8723a_EfuseParseChnlPlan(struct rtw_adapter *padapter,
1725 u8 *hwinfo, bool AutoLoadFail)
1726 {
1727 padapter->mlmepriv.ChannelPlan =
1728 hal_com_get_channel_plan23a(padapter, hwinfo ?
1729 hwinfo[EEPROM_ChannelPlan_8723A]:0xFF,
1730 padapter->registrypriv.channel_plan,
1731 RT_CHANNEL_DOMAIN_WORLD_WIDE_13,
1732 AutoLoadFail);
1733
1734 DBG_8723A("mlmepriv.ChannelPlan = 0x%02x\n",
1735 padapter->mlmepriv.ChannelPlan);
1736 }
1737
1738 void
1739 Hal_EfuseParseCustomerID(struct rtw_adapter *padapter,
1740 u8 *hwinfo, bool AutoLoadFail)
1741 {
1742 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1743
1744 if (!AutoLoadFail) {
1745 pHalData->EEPROMCustomerID = hwinfo[EEPROM_CustomID_8723A];
1746 pHalData->EEPROMSubCustomerID =
1747 hwinfo[EEPROM_SubCustomID_8723A];
1748 } else {
1749 pHalData->EEPROMCustomerID = 0;
1750 pHalData->EEPROMSubCustomerID = 0;
1751 }
1752 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1753 "EEPROM Customer ID: 0x%2x\n", pHalData->EEPROMCustomerID);
1754 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1755 "EEPROM SubCustomer ID: 0x%02x\n",
1756 pHalData->EEPROMSubCustomerID);
1757 }
1758
1759 void
1760 Hal_EfuseParseAntennaDiversity(struct rtw_adapter *padapter,
1761 u8 *hwinfo, bool AutoLoadFail)
1762 {
1763 }
1764
1765 void
1766 Hal_EfuseParseRateIndicationOption(struct rtw_adapter *padapter,
1767 u8 *hwinfo, bool AutoLoadFail)
1768 {
1769 }
1770
1771 void
1772 Hal_EfuseParseXtal_8723A(struct rtw_adapter *pAdapter,
1773 u8 *hwinfo, u8 AutoLoadFail)
1774 {
1775 struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
1776
1777 if (!AutoLoadFail) {
1778 pHalData->CrystalCap = hwinfo[EEPROM_XTAL_K_8723A];
1779 if (pHalData->CrystalCap == 0xFF)
1780 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723A;
1781 } else {
1782 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723A;
1783 }
1784 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1785 "%s: CrystalCap = 0x%2x\n", __func__,
1786 pHalData->CrystalCap);
1787 }
1788
1789 void
1790 Hal_EfuseParseThermalMeter_8723A(struct rtw_adapter *padapter,
1791 u8 *PROMContent, bool AutoloadFail)
1792 {
1793 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1794
1795 /* */
1796 /* ThermalMeter from EEPROM */
1797 /* */
1798 if (!AutoloadFail)
1799 pHalData->EEPROMThermalMeter =
1800 PROMContent[EEPROM_THERMAL_METER_8723A];
1801 else
1802 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
1803
1804 if ((pHalData->EEPROMThermalMeter == 0xff) || AutoloadFail) {
1805 pHalData->bAPKThermalMeterIgnore = true;
1806 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
1807 }
1808
1809 DBG_8723A("%s: ThermalMeter = 0x%x\n", __func__,
1810 pHalData->EEPROMThermalMeter);
1811 }
1812
1813 static void rtl8723a_cal_txdesc_chksum(struct tx_desc *ptxdesc)
1814 {
1815 __le16 *usPtr = (__le16 *)ptxdesc;
1816 u32 count = 16; /* (32 bytes / 2 bytes per XOR) => 16 times */
1817 u32 index;
1818 u16 checksum = 0;
1819
1820 /* Clear first */
1821 ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
1822
1823 for (index = 0; index < count; index++)
1824 checksum ^= le16_to_cpu(usPtr[index]);
1825
1826 ptxdesc->txdw7 |= cpu_to_le32(checksum & 0x0000ffff);
1827 }
1828
1829 /*
1830 * Description: In normal chip, we should send some packet to Hw which
1831 * will be used by Fw in FW LPS mode. The function is to fill the Tx
1832 * descriptor of this packets, then
1833 */
1834 /* Fw can tell Hw to send these packet derectly. */
1835 /* Added by tynli. 2009.10.15. */
1836 /* */
1837 void rtl8723a_fill_fake_txdesc(struct rtw_adapter *padapter, u8 *pDesc,
1838 u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull)
1839 {
1840 struct tx_desc *ptxdesc;
1841
1842 /* Clear all status */
1843 ptxdesc = (struct tx_desc *)pDesc;
1844 memset(pDesc, 0, TXDESC_SIZE);
1845
1846 /* offset 0 */
1847 /* own, bFirstSeg, bLastSeg; */
1848 ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
1849
1850 /* 32 bytes for TX Desc */
1851 ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) <<
1852 OFFSET_SHT) & 0x00ff0000);
1853
1854 /* Buffer size + command header */
1855 ptxdesc->txdw0 |= cpu_to_le32(BufferLen & 0x0000ffff);
1856
1857 /* offset 4 */
1858 /* Fixed queue of Mgnt queue */
1859 ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT << QSEL_SHT) & 0x00001f00);
1860
1861 /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed
1862 to error vlaue by Hw. */
1863 if (IsPsPoll) {
1864 ptxdesc->txdw1 |= cpu_to_le32(NAVUSEHDR);
1865 } else {
1866 /* Hw set sequence number */
1867 ptxdesc->txdw4 |= cpu_to_le32(BIT(7));
1868 /* set bit3 to 1. Suugested by TimChen. 2009.12.29. */
1869 ptxdesc->txdw3 |= cpu_to_le32((8 << 28));
1870 }
1871
1872 if (true == IsBTQosNull)
1873 ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); /* BT NULL */
1874
1875 /* offset 16 */
1876 ptxdesc->txdw4 |= cpu_to_le32(BIT(8)); /* driver uses rate */
1877
1878 /* USB interface drop packet if the checksum of descriptor isn't
1879 correct. */
1880 /* Using this checksum can let hardware recovery from packet bulk
1881 out error (e.g. Cancel URC, Bulk out error.). */
1882 rtl8723a_cal_txdesc_chksum(ptxdesc);
1883 }
1884
1885 void hw_var_set_opmode(struct rtw_adapter *padapter, u8 mode)
1886 {
1887 u8 val8;
1888
1889 if (mode == MSR_INFRA || mode == MSR_NOLINK) {
1890 StopTxBeacon(padapter);
1891
1892 /* disable atim wnd */
1893 val8 = DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_ATIM;
1894 SetBcnCtrlReg23a(padapter, val8, ~val8);
1895 } else if (mode == MSR_ADHOC) {
1896 ResumeTxBeacon(padapter);
1897
1898 val8 = DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB;
1899 SetBcnCtrlReg23a(padapter, val8, ~val8);
1900 } else if (mode == MSR_AP) {
1901 /* add NULL Data and BT NULL Data Packets to FW RSVD Page */
1902 rtl8723a_set_BTCoex_AP_mode_FwRsvdPkt_cmd(padapter);
1903
1904 ResumeTxBeacon(padapter);
1905
1906 val8 = DIS_TSF_UDT | DIS_BCNQ_SUB;
1907 SetBcnCtrlReg23a(padapter, val8, ~val8);
1908
1909 /* Set RCR */
1910 /* rtl8723au_write32(padapter, REG_RCR, 0x70002a8e);
1911 CBSSID_DATA must set to 0 */
1912 /* CBSSID_DATA must set to 0 */
1913 rtl8723au_write32(padapter, REG_RCR, 0x7000228e);
1914 /* enable to rx data frame */
1915 rtl8723au_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
1916 /* enable to rx ps-poll */
1917 rtl8723au_write16(padapter, REG_RXFLTMAP1, 0x0400);
1918
1919 /* Beacon Control related register for first time */
1920 /* 2ms */
1921 rtl8723au_write8(padapter, REG_BCNDMATIM, 0x02);
1922 /* 5ms */
1923 rtl8723au_write8(padapter, REG_DRVERLYINT, 0x05);
1924 /* 10ms for port0 */
1925 rtl8723au_write8(padapter, REG_ATIMWND, 0x0a);
1926 rtl8723au_write16(padapter, REG_BCNTCFG, 0x00);
1927 rtl8723au_write16(padapter, REG_TBTT_PROHIBIT, 0xff04);
1928 /* +32767 (~32ms) */
1929 rtl8723au_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);
1930
1931 /* reset TSF */
1932 rtl8723au_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
1933
1934 /* enable BCN Function */
1935 /* don't enable update TSF (due to TSF update when
1936 beacon/probe rsp are received) */
1937 val8 = DIS_TSF_UDT | EN_BCN_FUNCTION |
1938 EN_TXBCN_RPT | DIS_BCNQ_SUB;
1939 SetBcnCtrlReg23a(padapter, val8, ~val8);
1940 }
1941
1942 val8 = rtl8723au_read8(padapter, MSR);
1943 val8 = (val8 & 0xC) | mode;
1944 rtl8723au_write8(padapter, MSR, val8);
1945 }
1946
1947 void hw_var_set_macaddr(struct rtw_adapter *padapter, u8 *val)
1948 {
1949 u8 idx = 0;
1950 u32 reg_macid;
1951
1952 reg_macid = REG_MACID;
1953
1954 for (idx = 0; idx < 6; idx++)
1955 rtl8723au_write8(padapter, (reg_macid + idx), val[idx]);
1956 }
1957
1958 void hw_var_set_bssid(struct rtw_adapter *padapter, u8 *val)
1959 {
1960 u8 idx = 0;
1961 u32 reg_bssid;
1962
1963 reg_bssid = REG_BSSID;
1964
1965 for (idx = 0; idx < 6; idx++)
1966 rtl8723au_write8(padapter, (reg_bssid + idx), val[idx]);
1967 }
1968
1969 void hw_var_set_correct_tsf(struct rtw_adapter *padapter)
1970 {
1971 u64 tsf;
1972 u32 reg_tsftr;
1973 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
1974 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1975
1976 /* tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue %
1977 (pmlmeinfo->bcn_interval*1024)) - 1024; us */
1978 tsf = pmlmeext->TSFValue -
1979 do_div(pmlmeext->TSFValue,
1980 (pmlmeinfo->bcn_interval * 1024)) - 1024; /* us */
1981
1982 if (((pmlmeinfo->state & 0x03) == MSR_ADHOC) ||
1983 ((pmlmeinfo->state & 0x03) == MSR_AP)) {
1984 /* pHalData->RegTxPause |= STOP_BCNQ;BIT(6) */
1985 /* rtl8723au_write8(padapter, REG_TXPAUSE,
1986 (rtl8723au_read8(Adapter, REG_TXPAUSE)|BIT(6))); */
1987 StopTxBeacon(padapter);
1988 }
1989
1990 reg_tsftr = REG_TSFTR;
1991
1992 /* disable related TSF function */
1993 SetBcnCtrlReg23a(padapter, 0, EN_BCN_FUNCTION);
1994
1995 rtl8723au_write32(padapter, reg_tsftr, tsf);
1996 rtl8723au_write32(padapter, reg_tsftr + 4, tsf >> 32);
1997
1998 /* enable related TSF function */
1999 SetBcnCtrlReg23a(padapter, EN_BCN_FUNCTION, 0);
2000
2001 if (((pmlmeinfo->state & 0x03) == MSR_ADHOC) ||
2002 ((pmlmeinfo->state & 0x03) == MSR_AP))
2003 ResumeTxBeacon(padapter);
2004 }
2005
2006 void hw_var_set_mlme_disconnect(struct rtw_adapter *padapter)
2007 {
2008 /* reject all data frames */
2009 rtl8723au_write16(padapter, REG_RXFLTMAP2, 0);
2010
2011 /* reset TSF */
2012 rtl8723au_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
2013
2014 /* disable update TSF */
2015 SetBcnCtrlReg23a(padapter, DIS_TSF_UDT, 0);
2016 }
2017
2018 void hw_var_set_mlme_join(struct rtw_adapter *padapter, u8 type)
2019 {
2020 u8 RetryLimit = 0x30;
2021
2022 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
2023 struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
2024
2025 if (type == 0) { /* prepare to join */
2026 u32 v32;
2027
2028 /* enable to rx data frame.Accept all data frame */
2029 /* rtl8723au_write32(padapter, REG_RCR,
2030 rtl8723au_read32(padapter, REG_RCR)|RCR_ADF); */
2031 rtl8723au_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
2032
2033 v32 = rtl8723au_read32(padapter, REG_RCR);
2034 v32 |= RCR_CBSSID_DATA | RCR_CBSSID_BCN;
2035 rtl8723au_write32(padapter, REG_RCR, v32);
2036
2037 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == true)
2038 RetryLimit =
2039 (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48;
2040 else /* Ad-hoc Mode */
2041 RetryLimit = 0x7;
2042 } else if (type == 1) { /* joinbss_event callback when join res < 0 */
2043 /* config RCR to receive different BSSID & not to
2044 receive data frame during linking */
2045 rtl8723au_write16(padapter, REG_RXFLTMAP2, 0);
2046 } else if (type == 2) { /* sta add event callback */
2047 /* enable update TSF */
2048 SetBcnCtrlReg23a(padapter, 0, DIS_TSF_UDT);
2049
2050 if (check_fwstate(pmlmepriv,
2051 WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
2052 /* fixed beacon issue for 8191su........... */
2053 rtl8723au_write8(padapter, 0x542, 0x02);
2054 RetryLimit = 0x7;
2055 }
2056 }
2057
2058 rtl8723au_write16(padapter, REG_RL,
2059 RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit <<
2060 RETRY_LIMIT_LONG_SHIFT);
2061
2062 switch (type) {
2063 case 0:
2064 /* prepare to join */
2065 rtl8723a_BT_wifiassociate_notify(padapter, true);
2066 break;
2067 case 1:
2068 /* joinbss_event callback when join res < 0 */
2069 rtl8723a_BT_wifiassociate_notify(padapter, false);
2070 break;
2071 case 2:
2072 /* sta add event callback */
2073 /* BT_WifiMediaStatusNotify(padapter, RT_MEDIA_CONNECT); */
2074 break;
2075 }
2076 }
Linux kernel - Deliverables
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