drivers/staging/slicoss/slichw.h

   1 /**************************************************************************
   2  *
   3  * Copyright (c) 2000-2002 Alacritech, Inc.  All rights reserved.
   4  *
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above
  13  *    copyright notice, this list of conditions and the following
  14  *    disclaimer in the documentation and/or other materials provided
  15  *    with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
  18  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  20  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ALACRITECH, INC. OR
  21  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  24  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  25  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  26  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  27  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * The views and conclusions contained in the software and documentation
  31  * are those of the authors and should not be interpreted as representing
  32  * official policies, either expressed or implied, of Alacritech, Inc.
  33  *
  34  **************************************************************************/
  35
  36 /*
  37  * FILENAME: slichw.h
  38  *
  39  * This header file contains definitions that are common to our hardware.
  40  */
  41 #ifndef __SLICHW_H__
  42 #define __SLICHW_H__
  43
  44 #define PCI_VENDOR_ID_ALACRITECH        0x139A
  45 #define SLIC_1GB_DEVICE_ID              0x0005
  46 #define SLIC_2GB_DEVICE_ID              0x0007  /* Oasis Device ID */
  47
  48 #define SLIC_1GB_CICADA_SUBSYS_ID       0x0008
  49
  50 #define SLIC_NBR_MACS           4
  51
  52 #define SLIC_RCVBUF_SIZE        2048
  53 #define SLIC_RCVBUF_HEADSIZE    34
  54 #define SLIC_RCVBUF_TAILSIZE    0
  55 #define SLIC_RCVBUF_DATASIZE    (SLIC_RCVBUF_SIZE -             \
  56                                  (SLIC_RCVBUF_HEADSIZE +        \
  57                                   SLIC_RCVBUF_TAILSIZE))
  58
  59 #define VGBSTAT_XPERR           0x40000000
  60 #define VGBSTAT_XERRSHFT        25
  61 #define VGBSTAT_XCSERR          0x23
  62 #define VGBSTAT_XUFLOW          0x22
  63 #define VGBSTAT_XHLEN           0x20
  64 #define VGBSTAT_NETERR          0x01000000
  65 #define VGBSTAT_NERRSHFT        16
  66 #define VGBSTAT_NERRMSK         0x1ff
  67 #define VGBSTAT_NCSERR          0x103
  68 #define VGBSTAT_NUFLOW          0x102
  69 #define VGBSTAT_NHLEN           0x100
  70 #define VGBSTAT_LNKERR          0x00000080
  71 #define VGBSTAT_LERRMSK         0xff
  72 #define VGBSTAT_LDEARLY         0x86
  73 #define VGBSTAT_LBOFLO          0x85
  74 #define VGBSTAT_LCODERR         0x84
  75 #define VGBSTAT_LDBLNBL         0x83
  76 #define VGBSTAT_LCRCERR         0x82
  77 #define VGBSTAT_LOFLO           0x81
  78 #define VGBSTAT_LUFLO           0x80
  79 #define IRHDDR_FLEN_MSK         0x0000ffff
  80 #define IRHDDR_SVALID           0x80000000
  81 #define IRHDDR_ERR              0x10000000
  82 #define VRHSTAT_802OE           0x80000000
  83 #define VRHSTAT_TPOFLO          0x10000000
  84 #define VRHSTATB_802UE          0x80000000
  85 #define VRHSTATB_RCVE           0x40000000
  86 #define VRHSTATB_BUFF           0x20000000
  87 #define VRHSTATB_CARRE          0x08000000
  88 #define VRHSTATB_LONGE          0x02000000
  89 #define VRHSTATB_PREA           0x01000000
  90 #define VRHSTATB_CRC            0x00800000
  91 #define VRHSTATB_DRBL           0x00400000
  92 #define VRHSTATB_CODE           0x00200000
  93 #define VRHSTATB_TPCSUM         0x00100000
  94 #define VRHSTATB_TPHLEN         0x00080000
  95 #define VRHSTATB_IPCSUM         0x00040000
  96 #define VRHSTATB_IPLERR         0x00020000
  97 #define VRHSTATB_IPHERR         0x00010000
  98 #define SLIC_MAX64_BCNT         23
  99 #define SLIC_MAX32_BCNT         26
 100 #define IHCMD_XMT_REQ           0x01
 101 #define IHFLG_IFSHFT            2
 102 #define SLIC_RSPBUF_SIZE        32
 103
 104 #define SLIC_RESET_MAGIC        0xDEAD
 105 #define ICR_INT_OFF             0
 106 #define ICR_INT_ON              1
 107 #define ICR_INT_MASK            2
 108
 109 #define ISR_ERR                 0x80000000
 110 #define ISR_RCV                 0x40000000
 111 #define ISR_CMD                 0x20000000
 112 #define ISR_IO                  0x60000000
 113 #define ISR_UPC                 0x10000000
 114 #define ISR_LEVENT              0x08000000
 115 #define ISR_RMISS               0x02000000
 116 #define ISR_UPCERR              0x01000000
 117 #define ISR_XDROP               0x00800000
 118 #define ISR_UPCBSY              0x00020000
 119 #define ISR_EVMSK               0xffff0000
 120 #define ISR_PINGMASK            0x00700000
 121 #define ISR_PINGDSMASK          0x00710000
 122 #define ISR_UPCMASK             0x11000000
 123 #define SLIC_WCS_START          0x80000000
 124 #define SLIC_WCS_COMPARE        0x40000000
 125 #define SLIC_RCVWCS_BEGIN       0x40000000
 126 #define SLIC_RCVWCS_FINISH      0x80000000
 127 #define SLIC_PM_MAXPATTERNS     6
 128 #define SLIC_PM_PATTERNSIZE     128
 129 #define SLIC_PMCAPS_WAKEONLAN   0x00000001
 130 #define MIICR_REG_PCR           0x00000000
 131 #define MIICR_REG_4             0x00040000
 132 #define MIICR_REG_9             0x00090000
 133 #define MIICR_REG_16            0x00100000
 134 #define PCR_RESET               0x8000
 135 #define PCR_POWERDOWN           0x0800
 136 #define PCR_SPEED_100           0x2000
 137 #define PCR_SPEED_1000          0x0040
 138 #define PCR_AUTONEG             0x1000
 139 #define PCR_AUTONEG_RST         0x0200
 140 #define PCR_DUPLEX_FULL         0x0100
 141 #define PSR_LINKUP              0x0004
 142
 143 #define PAR_ADV100FD            0x0100
 144 #define PAR_ADV100HD            0x0080
 145 #define PAR_ADV10FD             0x0040
 146 #define PAR_ADV10HD             0x0020
 147 #define PAR_ASYMPAUSE           0x0C00
 148 #define PAR_802_3               0x0001
 149
 150 #define PAR_ADV1000XFD          0x0020
 151 #define PAR_ADV1000XHD          0x0040
 152 #define PAR_ASYMPAUSE_FIBER     0x0180
 153
 154 #define PGC_ADV1000FD           0x0200
 155 #define PGC_ADV1000HD           0x0100
 156 #define SEEQ_LINKFAIL           0x4000
 157 #define SEEQ_SPEED              0x0080
 158 #define SEEQ_DUPLEX             0x0040
 159 #define TDK_DUPLEX              0x0800
 160 #define TDK_SPEED               0x0400
 161 #define MRV_REG16_XOVERON       0x0068
 162 #define MRV_REG16_XOVEROFF      0x0008
 163 #define MRV_SPEED_1000          0x8000
 164 #define MRV_SPEED_100           0x4000
 165 #define MRV_SPEED_10            0x0000
 166 #define MRV_FULLDUPLEX          0x2000
 167 #define MRV_LINKUP              0x0400
 168
 169 #define GIG_LINKUP              0x0001
 170 #define GIG_FULLDUPLEX          0x0002
 171 #define GIG_SPEED_MASK          0x000C
 172 #define GIG_SPEED_1000          0x0008
 173 #define GIG_SPEED_100           0x0004
 174 #define GIG_SPEED_10            0x0000
 175
 176 #define MCR_RESET               0x80000000
 177 #define MCR_CRCEN               0x40000000
 178 #define MCR_FULLD               0x10000000
 179 #define MCR_PAD                 0x02000000
 180 #define MCR_RETRYLATE           0x01000000
 181 #define MCR_BOL_SHIFT           21
 182 #define MCR_IPG1_SHIFT          14
 183 #define MCR_IPG2_SHIFT          7
 184 #define MCR_IPG3_SHIFT          0
 185 #define GMCR_RESET              0x80000000
 186 #define GMCR_GBIT               0x20000000
 187 #define GMCR_FULLD              0x10000000
 188 #define GMCR_GAPBB_SHIFT        14
 189 #define GMCR_GAPR1_SHIFT        7
 190 #define GMCR_GAPR2_SHIFT        0
 191 #define GMCR_GAPBB_1000         0x60
 192 #define GMCR_GAPR1_1000         0x2C
 193 #define GMCR_GAPR2_1000         0x40
 194 #define GMCR_GAPBB_100          0x70
 195 #define GMCR_GAPR1_100          0x2C
 196 #define GMCR_GAPR2_100          0x40
 197 #define XCR_RESET               0x80000000
 198 #define XCR_XMTEN               0x40000000
 199 #define XCR_PAUSEEN             0x20000000
 200 #define XCR_LOADRNG             0x10000000
 201 #define RCR_RESET               0x80000000
 202 #define RCR_RCVEN               0x40000000
 203 #define RCR_RCVALL              0x20000000
 204 #define RCR_RCVBAD              0x10000000
 205 #define RCR_CTLEN               0x08000000
 206 #define RCR_ADDRAEN             0x02000000
 207 #define GXCR_RESET              0x80000000
 208 #define GXCR_XMTEN              0x40000000
 209 #define GXCR_PAUSEEN            0x20000000
 210 #define GRCR_RESET              0x80000000
 211 #define GRCR_RCVEN              0x40000000
 212 #define GRCR_RCVALL             0x20000000
 213 #define GRCR_RCVBAD             0x10000000
 214 #define GRCR_CTLEN              0x08000000
 215 #define GRCR_ADDRAEN            0x02000000
 216 #define GRCR_HASHSIZE_SHIFT     17
 217 #define GRCR_HASHSIZE           14
 218
 219 #define SLIC_EEPROM_ID          0xA5A5
 220 #define SLIC_SRAM_SIZE2GB       (64 * 1024)
 221 #define SLIC_SRAM_SIZE1GB       (32 * 1024)
 222 #define SLIC_HOSTID_DEFAULT     0xFFFF          /* uninitialized hostid */
 223 #define SLIC_NBR_MACS           4
 224
 225 struct slic_rcvbuf {
 226         u8 pad1[6];
 227         u16 pad2;
 228         u32 pad3;
 229         u32 pad4;
 230         u32 buffer;
 231         u32 length;
 232         u32 status;
 233         u32 pad5;
 234         u16 pad6;
 235         u8 data[SLIC_RCVBUF_DATASIZE];
 236 };
 237
 238 struct slic_hddr_wds {
 239         union {
 240                 struct {
 241                         u32 frame_status;
 242                         u32 frame_status_b;
 243                         u32 time_stamp;
 244                         u32 checksum;
 245                 } hdrs_14port;
 246                 struct {
 247                         u32 frame_status;
 248                         u16 ByteCnt;
 249                         u16 TpChksum;
 250                         u16 CtxHash;
 251                         u16 MacHash;
 252                         u32 BufLnk;
 253                 } hdrs_gbit;
 254         } u0;
 255 };
 256
 257 #define frame_status14          u0.hdrs_14port.frame_status
 258 #define frame_status_b14        u0.hdrs_14port.frame_status_b
 259 #define frame_statusGB          u0.hdrs_gbit.frame_status
 260
 261 struct slic_host64sg {
 262         u32 paddrl;
 263         u32 paddrh;
 264         u32 length;
 265 };
 266
 267 struct slic_host64_cmd {
 268         u32 hosthandle;
 269         u32 RSVD;
 270         u8 command;
 271         u8 flags;
 272         union {
 273                 u16 rsv1;
 274                 u16 rsv2;
 275         } u0;
 276         union {
 277                 struct {
 278                         u32 totlen;
 279                         struct slic_host64sg bufs[SLIC_MAX64_BCNT];
 280                 } slic_buffers;
 281         } u;
 282 };
 283
 284 struct slic_rspbuf {
 285         u32 hosthandle;
 286         u32 pad0;
 287         u32 pad1;
 288         u32 status;
 289         u32 pad2[4];
 290 };
 291
 292 struct slic_regs {
 293         u32     slic_reset;     /* Reset Register */
 294         u32     pad0;
 295
 296         u32     slic_icr;       /* Interrupt Control Register */
 297         u32     pad2;
 298 #define SLIC_ICR                0x0008
 299
 300         u32     slic_isp;       /* Interrupt status pointer */
 301         u32     pad1;
 302 #define SLIC_ISP                0x0010
 303
 304         u32     slic_isr;       /* Interrupt status */
 305         u32     pad3;
 306 #define SLIC_ISR                0x0018
 307
 308         u32     slic_hbar;      /* Header buffer address reg */
 309         u32     pad4;
 310         /*
 311          * 31-8 - phy addr of set of contiguous hdr buffers
 312          *  7-0 - number of buffers passed
 313          * Buffers are 256 bytes long on 256-byte boundaries.
 314          */
 315 #define SLIC_HBAR               0x0020
 316 #define SLIC_HBAR_CNT_MSK       0x000000FF
 317
 318         u32     slic_dbar;      /* Data buffer handle & address reg */
 319         u32     pad5;
 320
 321         /* 4 sets of registers; Buffers are 2K bytes long 2 per 4K page. */
 322 #define SLIC_DBAR               0x0028
 323 #define SLIC_DBAR_SIZE          2048
 324
 325         u32     slic_cbar;      /* Xmt Cmd buf addr regs.*/
 326         /*
 327          * 1 per XMT interface
 328          * 31-5 - phy addr of host command buffer
 329          *  4-0 - length of cmd in multiples of 32 bytes
 330          * Buffers are 32 bytes up to 512 bytes long
 331          */
 332 #define SLIC_CBAR               0x0030
 333 #define SLIC_CBAR_LEN_MSK       0x0000001F
 334 #define SLIC_CBAR_ALIGN         0x00000020
 335
 336         u32     slic_wcs;       /* write control store*/
 337 #define SLIC_WCS                0x0034
 338 #define SLIC_WCS_START          0x80000000      /*Start the SLIC (Jump to WCS)*/
 339 #define SLIC_WCS_COMPARE        0x40000000      /* Compare with value in WCS*/
 340
 341         u32     slic_rbar;      /* Response buffer address reg.*/
 342         u32     pad7;
 343         /*
 344          * 31-8 - phy addr of set of contiguous response buffers
 345          * 7-0 - number of buffers passed
 346          * Buffers are 32 bytes long on 32-byte boundaries.
 347          */
 348 #define SLIC_RBAR               0x0038
 349 #define SLIC_RBAR_CNT_MSK       0x000000FF
 350 #define SLIC_RBAR_SIZE          32
 351
 352         u32     slic_stats;     /* read statistics (UPR) */
 353         u32     pad8;
 354 #define SLIC_RSTAT              0x0040
 355
 356         u32     slic_rlsr;      /* read link status */
 357         u32     pad9;
 358 #define SLIC_LSTAT              0x0048
 359
 360         u32     slic_wmcfg;     /* Write Mac Config */
 361         u32     pad10;
 362 #define SLIC_WMCFG              0x0050
 363
 364         u32     slic_wphy;      /* Write phy register */
 365         u32     pad11;
 366 #define SLIC_WPHY               0x0058
 367
 368         u32     slic_rcbar;     /* Rcv Cmd buf addr reg */
 369         u32     pad12;
 370 #define SLIC_RCBAR              0x0060
 371
 372         u32     slic_rconfig;   /* Read SLIC Config*/
 373         u32     pad13;
 374 #define SLIC_RCONFIG    0x0068
 375
 376         u32     slic_intagg;    /* Interrupt aggregation time */
 377         u32     pad14;
 378 #define SLIC_INTAGG             0x0070
 379
 380         u32     slic_wxcfg;     /* Write XMIT config reg*/
 381         u32     pad16;
 382 #define SLIC_WXCFG              0x0078
 383
 384         u32     slic_wrcfg;     /* Write RCV config reg*/
 385         u32     pad17;
 386 #define SLIC_WRCFG              0x0080
 387
 388         u32     slic_wraddral;  /* Write rcv addr a low*/
 389         u32     pad18;
 390 #define SLIC_WRADDRAL   0x0088
 391
 392         u32     slic_wraddrah;  /* Write rcv addr a high*/
 393         u32     pad19;
 394 #define SLIC_WRADDRAH   0x0090
 395
 396         u32     slic_wraddrbl;  /* Write rcv addr b low*/
 397         u32     pad20;
 398 #define SLIC_WRADDRBL   0x0098
 399
 400         u32     slic_wraddrbh;  /* Write rcv addr b high*/
 401         u32             pad21;
 402 #define SLIC_WRADDRBH   0x00a0
 403
 404         u32     slic_mcastlow;  /* Low bits of mcast mask*/
 405         u32             pad22;
 406 #define SLIC_MCASTLOW   0x00a8
 407
 408         u32     slic_mcasthigh; /* High bits of mcast mask*/
 409         u32             pad23;
 410 #define SLIC_MCASTHIGH  0x00b0
 411
 412         u32     slic_ping;      /* Ping the card*/
 413         u32     pad24;
 414 #define SLIC_PING               0x00b8
 415
 416         u32     slic_dump_cmd;  /* Dump command */
 417         u32     pad25;
 418 #define SLIC_DUMP_CMD   0x00c0
 419
 420         u32     slic_dump_data; /* Dump data pointer */
 421         u32     pad26;
 422 #define SLIC_DUMP_DATA  0x00c8
 423
 424         u32     slic_pcistatus; /* Read card's pci_status register */
 425         u32     pad27;
 426 #define SLIC_PCISTATUS  0x00d0
 427
 428         u32     slic_wrhostid;  /* Write hostid field */
 429         u32             pad28;
 430 #define SLIC_WRHOSTID            0x00d8
 431 #define SLIC_RDHOSTID_1GB        0x1554
 432 #define SLIC_RDHOSTID_2GB        0x1554
 433
 434         u32     slic_low_power; /* Put card in a low power state */
 435         u32     pad29;
 436 #define SLIC_LOW_POWER  0x00e0
 437
 438         u32     slic_quiesce;   /* force slic into quiescent state
 439                                  * before soft reset
 440                                  */
 441         u32     pad30;
 442 #define SLIC_QUIESCE    0x00e8
 443
 444         u32     slic_reset_iface;/* reset interface queues */
 445         u32     pad31;
 446 #define SLIC_RESET_IFACE 0x00f0
 447
 448         u32     slic_addr_upper;/* Bits 63-32 for host i/f addrs */
 449         u32     pad32;
 450 #define SLIC_ADDR_UPPER 0x00f8 /*Register is only written when it has changed*/
 451
 452         u32     slic_hbar64;    /* 64 bit Header buffer address reg */
 453         u32     pad33;
 454 #define SLIC_HBAR64             0x0100
 455
 456         u32     slic_dbar64;    /* 64 bit Data buffer handle & address reg */
 457         u32     pad34;
 458 #define SLIC_DBAR64             0x0108
 459
 460         u32     slic_cbar64;    /* 64 bit Xmt Cmd buf addr regs. */
 461         u32     pad35;
 462 #define SLIC_CBAR64             0x0110
 463
 464         u32     slic_rbar64;    /* 64 bit Response buffer address reg.*/
 465         u32     pad36;
 466 #define SLIC_RBAR64             0x0118
 467
 468         u32     slic_rcbar64;   /* 64 bit Rcv Cmd buf addr reg*/
 469         u32     pad37;
 470 #define SLIC_RCBAR64    0x0120
 471
 472         u32     slic_stats64;   /* read statistics (64 bit UPR) */
 473         u32     pad38;
 474 #define SLIC_RSTAT64    0x0128
 475
 476         u32     slic_rcv_wcs;   /*Download Gigabit RCV sequencer ucode*/
 477         u32     pad39;
 478 #define SLIC_RCV_WCS    0x0130
 479 #define SLIC_RCVWCS_BEGIN       0x40000000
 480 #define SLIC_RCVWCS_FINISH      0x80000000
 481
 482         u32     slic_wrvlanid;  /* Write VlanId field */
 483         u32     pad40;
 484 #define SLIC_WRVLANID   0x0138
 485
 486         u32     slic_read_xf_info;      /* Read Transformer info */
 487         u32     pad41;
 488 #define SLIC_READ_XF_INFO       0x0140
 489
 490         u32     slic_write_xf_info;     /* Write Transformer info */
 491         u32     pad42;
 492 #define SLIC_WRITE_XF_INFO      0x0148
 493
 494         u32     RSVD1;          /* TOE Only */
 495         u32     pad43;
 496
 497         u32     RSVD2;          /* TOE Only */
 498         u32     pad44;
 499
 500         u32     RSVD3;          /* TOE Only */
 501         u32     pad45;
 502
 503         u32     RSVD4;          /* TOE Only */
 504         u32     pad46;
 505
 506         u32     slic_ticks_per_sec; /* Write card ticks per second */
 507         u32     pad47;
 508 #define SLIC_TICKS_PER_SEC      0x0170
 509 };
 510
 511 enum UPR_REQUEST {
 512         SLIC_UPR_STATS,
 513         SLIC_UPR_RLSR,
 514         SLIC_UPR_WCFG,
 515         SLIC_UPR_RCONFIG,
 516         SLIC_UPR_RPHY,
 517         SLIC_UPR_ENLB,
 518         SLIC_UPR_ENCT,
 519         SLIC_UPR_PDWN,
 520         SLIC_UPR_PING,
 521         SLIC_UPR_DUMP,
 522 };
 523
 524 struct inicpm_wakepattern {
 525         u32 patternlength;
 526         u8 pattern[SLIC_PM_PATTERNSIZE];
 527         u8 mask[SLIC_PM_PATTERNSIZE];
 528 };
 529
 530 struct inicpm_state {
 531         u32 powercaps;
 532         u32 powerstate;
 533         u32 wake_linkstatus;
 534         u32 wake_magicpacket;
 535         u32 wake_framepattern;
 536         struct inicpm_wakepattern wakepattern[SLIC_PM_MAXPATTERNS];
 537 };
 538
 539 struct slicpm_packet_pattern {
 540         u32 priority;
 541         u32 reserved;
 542         u32 masksize;
 543         u32 patternoffset;
 544         u32 patternsize;
 545         u32 patternflags;
 546 };
 547
 548 enum slicpm_power_state {
 549         slicpm_state_unspecified = 0,
 550         slicpm_state_d0,
 551         slicpm_state_d1,
 552         slicpm_state_d2,
 553         slicpm_state_d3,
 554         slicpm_state_maximum
 555 };
 556
 557 struct slicpm_wakeup_capabilities {
 558         enum slicpm_power_state min_magic_packet_wakeup;
 559         enum slicpm_power_state min_pattern_wakeup;
 560         enum slicpm_power_state min_link_change_wakeup;
 561 };
 562
 563 struct slic_pnp_capabilities {
 564         u32 flags;
 565         struct slicpm_wakeup_capabilities wakeup_capabilities;
 566 };
 567
 568 struct xmt_stats {
 569         u32 xmit_tcp_bytes;
 570         u32 xmit_tcp_segs;
 571         u32 xmit_bytes;
 572         u32 xmit_collisions;
 573         u32 xmit_unicasts;
 574         u32 xmit_other_error;
 575         u32 xmit_excess_collisions;
 576 };
 577
 578 struct rcv_stats {
 579         u32 rcv_tcp_bytes;
 580         u32 rcv_tcp_segs;
 581         u32 rcv_bytes;
 582         u32 rcv_unicasts;
 583         u32 rcv_other_error;
 584         u32 rcv_drops;
 585 };
 586
 587 struct xmt_statsgb {
 588         u64 xmit_tcp_bytes;
 589         u64 xmit_tcp_segs;
 590         u64 xmit_bytes;
 591         u64 xmit_collisions;
 592         u64 xmit_unicasts;
 593         u64 xmit_other_error;
 594         u64 xmit_excess_collisions;
 595 };
 596
 597 struct rcv_statsgb {
 598         u64 rcv_tcp_bytes;
 599         u64 rcv_tcp_segs;
 600         u64 rcv_bytes;
 601         u64 rcv_unicasts;
 602         u64 rcv_other_error;
 603         u64 rcv_drops;
 604 };
 605
 606 struct slic_stats {
 607         union {
 608                 struct {
 609                         struct xmt_stats xmt100;
 610                         struct rcv_stats rcv100;
 611                 } stats_100;
 612                 struct {
 613                         struct xmt_statsgb xmtGB;
 614                         struct rcv_statsgb rcvGB;
 615                 } stats_GB;
 616         } u;
 617 };
 618
 619 #define xmit_tcp_segs100                u.stats_100.xmt100.xmit_tcp_segs
 620 #define xmit_tcp_bytes100               u.stats_100.xmt100.xmit_tcp_bytes
 621 #define xmit_bytes100                   u.stats_100.xmt100.xmit_bytes
 622 #define xmit_collisions100              u.stats_100.xmt100.xmit_collisions
 623 #define xmit_unicasts100                u.stats_100.xmt100.xmit_unicasts
 624 #define xmit_other_error100             u.stats_100.xmt100.xmit_other_error
 625 #define xmit_excess_collisions100       u.stats_100.xmt100.xmit_excess_collisions
 626 #define rcv_tcp_segs100                 u.stats_100.rcv100.rcv_tcp_segs
 627 #define rcv_tcp_bytes100                u.stats_100.rcv100.rcv_tcp_bytes
 628 #define rcv_bytes100                    u.stats_100.rcv100.rcv_bytes
 629 #define rcv_unicasts100                 u.stats_100.rcv100.rcv_unicasts
 630 #define rcv_other_error100              u.stats_100.rcv100.rcv_other_error
 631 #define rcv_drops100                    u.stats_100.rcv100.rcv_drops
 632 #define xmit_tcp_segs_gb                u.stats_GB.xmtGB.xmit_tcp_segs
 633 #define xmit_tcp_bytes_gb               u.stats_GB.xmtGB.xmit_tcp_bytes
 634 #define xmit_bytes_gb                   u.stats_GB.xmtGB.xmit_bytes
 635 #define xmit_collisions_gb              u.stats_GB.xmtGB.xmit_collisions
 636 #define xmit_unicasts_gb                u.stats_GB.xmtGB.xmit_unicasts
 637 #define xmit_other_error_gb             u.stats_GB.xmtGB.xmit_other_error
 638 #define xmit_excess_collisions_gb       u.stats_GB.xmtGB.xmit_excess_collisions
 639
 640 #define rcv_tcp_segs_gb                 u.stats_GB.rcvGB.rcv_tcp_segs
 641 #define rcv_tcp_bytes_gb                u.stats_GB.rcvGB.rcv_tcp_bytes
 642 #define rcv_bytes_gb                    u.stats_GB.rcvGB.rcv_bytes
 643 #define rcv_unicasts_gb                 u.stats_GB.rcvGB.rcv_unicasts
 644 #define rcv_other_error_gb              u.stats_GB.rcvGB.rcv_other_error
 645 #define rcv_drops_gb                    u.stats_GB.rcvGB.rcv_drops
 646
 647 struct slic_config_mac {
 648         u8 macaddrA[6];
 649 };
 650
 651 #define ATK_FRU_FORMAT          0x00
 652 #define VENDOR1_FRU_FORMAT      0x01
 653 #define VENDOR2_FRU_FORMAT      0x02
 654 #define VENDOR3_FRU_FORMAT      0x03
 655 #define VENDOR4_FRU_FORMAT      0x04
 656 #define NO_FRU_FORMAT           0xFF
 657
 658 struct atk_fru {
 659         u8 assembly[6];
 660         u8 revision[2];
 661         u8 serial[14];
 662         u8 pad[3];
 663 };
 664
 665 struct vendor1_fru {
 666         u8 commodity;
 667         u8 assembly[4];
 668         u8 revision[2];
 669         u8 supplier[2];
 670         u8 date[2];
 671         u8 sequence[3];
 672         u8 pad[13];
 673 };
 674
 675 struct vendor2_fru {
 676         u8 part[8];
 677         u8 supplier[5];
 678         u8 date[3];
 679         u8 sequence[4];
 680         u8 pad[7];
 681 };
 682
 683 struct vendor3_fru {
 684         u8 assembly[6];
 685         u8 revision[2];
 686         u8 serial[14];
 687         u8 pad[3];
 688 };
 689
 690 struct vendor4_fru {
 691         u8 number[8];
 692         u8 part[8];
 693         u8 version[8];
 694         u8 pad[3];
 695 };
 696
 697 union oemfru {
 698         struct vendor1_fru vendor1_fru;
 699         struct vendor2_fru vendor2_fru;
 700         struct vendor3_fru vendor3_fru;
 701         struct vendor4_fru vendor4_fru;
 702 };
 703
 704 /*
 705  * SLIC EEPROM structure for Mojave
 706  */
 707 struct slic_eeprom {
 708         u16 Id;                 /* 00 EEPROM/FLASH Magic code 'A5A5'*/
 709         u16 EecodeSize;         /* 01 Size of EEPROM Codes (bytes * 4)*/
 710         u16 FlashSize;          /* 02 Flash size */
 711         u16 EepromSize;         /* 03 EEPROM Size */
 712         u16 VendorId;           /* 04 Vendor ID */
 713         u16 DeviceId;           /* 05 Device ID */
 714         u8 RevisionId;          /* 06 Revision ID */
 715         u8 ClassCode[3];        /* 07 Class Code */
 716         u8 DbgIntPin;           /* 08 Debug Interrupt pin */
 717         u8 NetIntPin0;          /*    Network Interrupt Pin */
 718         u8 MinGrant;            /* 09 Minimum grant */
 719         u8 MaxLat;              /*    Maximum Latency */
 720         u16 PciStatus;          /* 10 PCI Status */
 721         u16 SubSysVId;          /* 11 Subsystem Vendor Id */
 722         u16 SubSysId;           /* 12 Subsystem ID */
 723         u16 DbgDevId;           /* 13 Debug Device Id */
 724         u16 DramRomFn;          /* 14 Dram/Rom function */
 725         u16 DSize2Pci;          /* 15 DRAM size to PCI (bytes * 64K) */
 726         u16 RSize2Pci;          /* 16 ROM extension size to PCI (bytes * 4k) */
 727         u8 NetIntPin1;          /* 17 Network Interface Pin 1
 728                                  *  (simba/leone only)
 729                                  */
 730         u8 NetIntPin2;          /* Network Interface Pin 2 (simba/leone only)*/
 731         union {
 732                 u8 NetIntPin3;  /* 18 Network Interface Pin 3 (simba only) */
 733                 u8 FreeTime;    /* FreeTime setting (leone/mojave only) */
 734         } u1;
 735         u8 TBIctl;              /* 10-bit interface control (Mojave only) */
 736         u16 DramSize;           /* 19 DRAM size (bytes * 64k) */
 737         union {
 738                 struct {
 739                         /* Mac Interface Specific portions */
 740                         struct slic_config_mac  MacInfo[SLIC_NBR_MACS];
 741                 } mac;                          /* MAC access for all boards */
 742                 struct {
 743                         /* use above struct for MAC access */
 744                         struct slic_config_mac  pad[SLIC_NBR_MACS - 1];
 745                         u16 DeviceId2;  /* Device ID for 2nd PCI function */
 746                         u8 IntPin2;     /* Interrupt pin for 2nd PCI function */
 747                         u8 ClassCode2[3]; /* Class Code for 2nd PCI function */
 748                 } mojave;       /* 2nd function access for gigabit board */
 749         } u2;
 750         u16 CfgByte6;           /* Config Byte 6 */
 751         u16 PMECapab;           /* Power Mgment capabilities */
 752         u16 NwClkCtrls;         /* NetworkClockControls */
 753         u8 FruFormat;           /* Alacritech FRU format type */
 754         struct atk_fru  AtkFru; /* Alacritech FRU information */
 755         u8 OemFruFormat;        /* optional OEM FRU format type */
 756         union oemfru OemFru;    /* optional OEM FRU information */
 757         u8      Pad[4];         /* Pad to 128 bytes - includes 2 cksum bytes
 758                                  * (if OEM FRU info exists) and two unusable
 759                                  * bytes at the end
 760                                  */
 761 };
 762
 763 /* SLIC EEPROM structure for Oasis */
 764 struct oslic_eeprom {
 765         u16 Id;                 /* 00 EEPROM/FLASH Magic code 'A5A5' */
 766         u16 EecodeSize;         /* 01 Size of EEPROM Codes (bytes * 4)*/
 767         u16 FlashConfig0;       /* 02 Flash Config for SPI device 0 */
 768         u16 FlashConfig1;       /* 03 Flash Config for SPI device 1 */
 769         u16 VendorId;           /* 04 Vendor ID */
 770         u16 DeviceId;           /* 05 Device ID (function 0) */
 771         u8 RevisionId;          /* 06 Revision ID */
 772         u8 ClassCode[3];        /* 07 Class Code for PCI function 0 */
 773         u8 IntPin1;             /* 08 Interrupt pin for PCI function 1*/
 774         u8 ClassCode2[3];       /* 09 Class Code for PCI function 1 */
 775         u8 IntPin2;             /* 10 Interrupt pin for PCI function 2*/
 776         u8 IntPin0;             /*    Interrupt pin for PCI function 0*/
 777         u8 MinGrant;            /* 11 Minimum grant */
 778         u8 MaxLat;              /*    Maximum Latency */
 779         u16 SubSysVId;          /* 12 Subsystem Vendor Id */
 780         u16 SubSysId;           /* 13 Subsystem ID */
 781         u16 FlashSize;          /* 14 Flash size (bytes / 4K) */
 782         u16 DSize2Pci;          /* 15 DRAM size to PCI (bytes / 64K) */
 783         u16 RSize2Pci;          /* 16 Flash (ROM extension) size to PCI
 784                                  *      (bytes / 4K)
 785                                  */
 786         u16 DeviceId1;          /* 17 Device Id (function 1) */
 787         u16 DeviceId2;          /* 18 Device Id (function 2) */
 788         u16 CfgByte6;           /* 19 Device Status Config Bytes 6-7 */
 789         u16 PMECapab;           /* 20 Power Mgment capabilities */
 790         u8 MSICapab;            /* 21 MSI capabilities */
 791         u8 ClockDivider;        /*    Clock divider */
 792         u16 PciStatusLow;       /* 22 PCI Status bits 15:0 */
 793         u16 PciStatusHigh;      /* 23 PCI Status bits 31:16 */
 794         u16 DramConfigLow;      /* 24 DRAM Configuration bits 15:0 */
 795         u16 DramConfigHigh;     /* 25 DRAM Configuration bits 31:16 */
 796         u16 DramSize;           /* 26 DRAM size (bytes / 64K) */
 797         u16 GpioTbiCtl;         /* 27 GPIO/TBI controls for functions 1/0 */
 798         u16 EepromSize;         /* 28 EEPROM Size */
 799         struct slic_config_mac MacInfo[2];      /* 29 MAC addresses (2 ports) */
 800         u8 FruFormat;           /* 35 Alacritech FRU format type */
 801         struct atk_fru  AtkFru; /* Alacritech FRU information */
 802         u8 OemFruFormat;        /* optional OEM FRU format type */
 803         union oemfru OemFru;    /* optional OEM FRU information */
 804         u8 Pad[4];              /* Pad to 128 bytes - includes 2 checksum bytes
 805                                  * (if OEM FRU info exists) and two unusable
 806                                  * bytes at the end
 807                                  */
 808 };
 809
 810 #define MAX_EECODE_SIZE sizeof(struct slic_eeprom)
 811 #define MIN_EECODE_SIZE 0x62    /* code size without optional OEM FRU stuff */
 812
 813 /*
 814  * SLIC CONFIG structure
 815  *
 816  * This structure lives in the CARD structure and is valid for all board types.
 817  * It is filled in from the appropriate EEPROM structure by
 818  * SlicGetConfigData()
 819  */
 820 struct slic_config {
 821         bool EepromValid;       /* Valid EEPROM flag (checksum good?) */
 822         u16 DramSize;           /* DRAM size (bytes / 64K) */
 823         struct slic_config_mac MacInfo[SLIC_NBR_MACS]; /* MAC addresses */
 824         u8 FruFormat;           /* Alacritech FRU format type */
 825         struct atk_fru  AtkFru; /* Alacritech FRU information */
 826         u8 OemFruFormat;        /* optional OEM FRU format type */
 827         union {
 828                 struct vendor1_fru vendor1_fru;
 829                 struct vendor2_fru vendor2_fru;
 830                 struct vendor3_fru vendor3_fru;
 831                 struct vendor4_fru vendor4_fru;
 832         } OemFru;
 833 };
 834
 835 #pragma pack()
 836
 837 #endif