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tty: serial: 8250_core: allow to set ->throttle / ->unthrottle callbacks
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250_core.c
1 /*
2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
18
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20 #define SUPPORT_SYSRQ
21 #endif
22
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_core.h>
35 #include <linux/serial.h>
36 #include <linux/serial_8250.h>
37 #include <linux/nmi.h>
38 #include <linux/mutex.h>
39 #include <linux/slab.h>
40 #include <linux/uaccess.h>
41 #ifdef CONFIG_SPARC
42 #include <linux/sunserialcore.h>
43 #endif
44
45 #include <asm/io.h>
46 #include <asm/irq.h>
47
48 #include "8250.h"
49
50 /*
51 * Configuration:
52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
54 */
55 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
56
57 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
59 static struct uart_driver serial8250_reg;
60
61 static int serial_index(struct uart_port *port)
62 {
63 return (serial8250_reg.minor - 64) + port->line;
64 }
65
66 static unsigned int skip_txen_test; /* force skip of txen test at init time */
67
68 /*
69 * Debugging.
70 */
71 #if 0
72 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
73 #else
74 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
75 #endif
76
77 #if 0
78 #define DEBUG_INTR(fmt...) printk(fmt)
79 #else
80 #define DEBUG_INTR(fmt...) do { } while (0)
81 #endif
82
83 #define PASS_LIMIT 512
84
85 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
86
87
88 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89 #define CONFIG_SERIAL_DETECT_IRQ 1
90 #endif
91 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
92 #define CONFIG_SERIAL_MANY_PORTS 1
93 #endif
94
95 /*
96 * HUB6 is always on. This will be removed once the header
97 * files have been cleaned.
98 */
99 #define CONFIG_HUB6 1
100
101 #include <asm/serial.h>
102 /*
103 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * standard enumeration mechanism. Platforms that can find all
105 * serial ports via mechanisms like ACPI or PCI need not supply it.
106 */
107 #ifndef SERIAL_PORT_DFNS
108 #define SERIAL_PORT_DFNS
109 #endif
110
111 static const struct old_serial_port old_serial_port[] = {
112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
113 };
114
115 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
116
117 #ifdef CONFIG_SERIAL_8250_RSA
118
119 #define PORT_RSA_MAX 4
120 static unsigned long probe_rsa[PORT_RSA_MAX];
121 static unsigned int probe_rsa_count;
122 #endif /* CONFIG_SERIAL_8250_RSA */
123
124 struct irq_info {
125 struct hlist_node node;
126 int irq;
127 spinlock_t lock; /* Protects list not the hash */
128 struct list_head *head;
129 };
130
131 #define NR_IRQ_HASH 32 /* Can be adjusted later */
132 static struct hlist_head irq_lists[NR_IRQ_HASH];
133 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
134
135 /*
136 * Here we define the default xmit fifo size used for each type of UART.
137 */
138 static const struct serial8250_config uart_config[] = {
139 [PORT_UNKNOWN] = {
140 .name = "unknown",
141 .fifo_size = 1,
142 .tx_loadsz = 1,
143 },
144 [PORT_8250] = {
145 .name = "8250",
146 .fifo_size = 1,
147 .tx_loadsz = 1,
148 },
149 [PORT_16450] = {
150 .name = "16450",
151 .fifo_size = 1,
152 .tx_loadsz = 1,
153 },
154 [PORT_16550] = {
155 .name = "16550",
156 .fifo_size = 1,
157 .tx_loadsz = 1,
158 },
159 [PORT_16550A] = {
160 .name = "16550A",
161 .fifo_size = 16,
162 .tx_loadsz = 16,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .rxtrig_bytes = {1, 4, 8, 14},
165 .flags = UART_CAP_FIFO,
166 },
167 [PORT_CIRRUS] = {
168 .name = "Cirrus",
169 .fifo_size = 1,
170 .tx_loadsz = 1,
171 },
172 [PORT_16650] = {
173 .name = "ST16650",
174 .fifo_size = 1,
175 .tx_loadsz = 1,
176 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
177 },
178 [PORT_16650V2] = {
179 .name = "ST16650V2",
180 .fifo_size = 32,
181 .tx_loadsz = 16,
182 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
183 UART_FCR_T_TRIG_00,
184 .rxtrig_bytes = {8, 16, 24, 28},
185 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
186 },
187 [PORT_16750] = {
188 .name = "TI16750",
189 .fifo_size = 64,
190 .tx_loadsz = 64,
191 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
192 UART_FCR7_64BYTE,
193 .rxtrig_bytes = {1, 16, 32, 56},
194 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
195 },
196 [PORT_STARTECH] = {
197 .name = "Startech",
198 .fifo_size = 1,
199 .tx_loadsz = 1,
200 },
201 [PORT_16C950] = {
202 .name = "16C950/954",
203 .fifo_size = 128,
204 .tx_loadsz = 128,
205 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
206 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
207 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
208 },
209 [PORT_16654] = {
210 .name = "ST16654",
211 .fifo_size = 64,
212 .tx_loadsz = 32,
213 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
214 UART_FCR_T_TRIG_10,
215 .rxtrig_bytes = {8, 16, 56, 60},
216 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
217 },
218 [PORT_16850] = {
219 .name = "XR16850",
220 .fifo_size = 128,
221 .tx_loadsz = 128,
222 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
223 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
224 },
225 [PORT_RSA] = {
226 .name = "RSA",
227 .fifo_size = 2048,
228 .tx_loadsz = 2048,
229 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
230 .flags = UART_CAP_FIFO,
231 },
232 [PORT_NS16550A] = {
233 .name = "NS16550A",
234 .fifo_size = 16,
235 .tx_loadsz = 16,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 .flags = UART_CAP_FIFO | UART_NATSEMI,
238 },
239 [PORT_XSCALE] = {
240 .name = "XScale",
241 .fifo_size = 32,
242 .tx_loadsz = 32,
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
245 },
246 [PORT_OCTEON] = {
247 .name = "OCTEON",
248 .fifo_size = 64,
249 .tx_loadsz = 64,
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
251 .flags = UART_CAP_FIFO,
252 },
253 [PORT_AR7] = {
254 .name = "AR7",
255 .fifo_size = 16,
256 .tx_loadsz = 16,
257 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
258 .flags = UART_CAP_FIFO | UART_CAP_AFE,
259 },
260 [PORT_U6_16550A] = {
261 .name = "U6_16550A",
262 .fifo_size = 64,
263 .tx_loadsz = 64,
264 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
265 .flags = UART_CAP_FIFO | UART_CAP_AFE,
266 },
267 [PORT_TEGRA] = {
268 .name = "Tegra",
269 .fifo_size = 32,
270 .tx_loadsz = 8,
271 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
272 UART_FCR_T_TRIG_01,
273 .rxtrig_bytes = {1, 4, 8, 14},
274 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
275 },
276 [PORT_XR17D15X] = {
277 .name = "XR17D15X",
278 .fifo_size = 64,
279 .tx_loadsz = 64,
280 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
281 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
282 UART_CAP_SLEEP,
283 },
284 [PORT_XR17V35X] = {
285 .name = "XR17V35X",
286 .fifo_size = 256,
287 .tx_loadsz = 256,
288 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
289 UART_FCR_T_TRIG_11,
290 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
291 UART_CAP_SLEEP,
292 },
293 [PORT_LPC3220] = {
294 .name = "LPC3220",
295 .fifo_size = 64,
296 .tx_loadsz = 32,
297 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
298 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
299 .flags = UART_CAP_FIFO,
300 },
301 [PORT_BRCM_TRUMANAGE] = {
302 .name = "TruManage",
303 .fifo_size = 1,
304 .tx_loadsz = 1024,
305 .flags = UART_CAP_HFIFO,
306 },
307 [PORT_8250_CIR] = {
308 .name = "CIR port"
309 },
310 [PORT_ALTR_16550_F32] = {
311 .name = "Altera 16550 FIFO32",
312 .fifo_size = 32,
313 .tx_loadsz = 32,
314 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
315 .flags = UART_CAP_FIFO | UART_CAP_AFE,
316 },
317 [PORT_ALTR_16550_F64] = {
318 .name = "Altera 16550 FIFO64",
319 .fifo_size = 64,
320 .tx_loadsz = 64,
321 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
322 .flags = UART_CAP_FIFO | UART_CAP_AFE,
323 },
324 [PORT_ALTR_16550_F128] = {
325 .name = "Altera 16550 FIFO128",
326 .fifo_size = 128,
327 .tx_loadsz = 128,
328 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
329 .flags = UART_CAP_FIFO | UART_CAP_AFE,
330 },
331 };
332
333 /* Uart divisor latch read */
334 static int default_serial_dl_read(struct uart_8250_port *up)
335 {
336 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
337 }
338
339 /* Uart divisor latch write */
340 static void default_serial_dl_write(struct uart_8250_port *up, int value)
341 {
342 serial_out(up, UART_DLL, value & 0xff);
343 serial_out(up, UART_DLM, value >> 8 & 0xff);
344 }
345
346 #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
347
348 /* Au1x00/RT288x UART hardware has a weird register layout */
349 static const u8 au_io_in_map[] = {
350 [UART_RX] = 0,
351 [UART_IER] = 2,
352 [UART_IIR] = 3,
353 [UART_LCR] = 5,
354 [UART_MCR] = 6,
355 [UART_LSR] = 7,
356 [UART_MSR] = 8,
357 };
358
359 static const u8 au_io_out_map[] = {
360 [UART_TX] = 1,
361 [UART_IER] = 2,
362 [UART_FCR] = 4,
363 [UART_LCR] = 5,
364 [UART_MCR] = 6,
365 };
366
367 static unsigned int au_serial_in(struct uart_port *p, int offset)
368 {
369 offset = au_io_in_map[offset] << p->regshift;
370 return __raw_readl(p->membase + offset);
371 }
372
373 static void au_serial_out(struct uart_port *p, int offset, int value)
374 {
375 offset = au_io_out_map[offset] << p->regshift;
376 __raw_writel(value, p->membase + offset);
377 }
378
379 /* Au1x00 haven't got a standard divisor latch */
380 static int au_serial_dl_read(struct uart_8250_port *up)
381 {
382 return __raw_readl(up->port.membase + 0x28);
383 }
384
385 static void au_serial_dl_write(struct uart_8250_port *up, int value)
386 {
387 __raw_writel(value, up->port.membase + 0x28);
388 }
389
390 #endif
391
392 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
393 {
394 offset = offset << p->regshift;
395 outb(p->hub6 - 1 + offset, p->iobase);
396 return inb(p->iobase + 1);
397 }
398
399 static void hub6_serial_out(struct uart_port *p, int offset, int value)
400 {
401 offset = offset << p->regshift;
402 outb(p->hub6 - 1 + offset, p->iobase);
403 outb(value, p->iobase + 1);
404 }
405
406 static unsigned int mem_serial_in(struct uart_port *p, int offset)
407 {
408 offset = offset << p->regshift;
409 return readb(p->membase + offset);
410 }
411
412 static void mem_serial_out(struct uart_port *p, int offset, int value)
413 {
414 offset = offset << p->regshift;
415 writeb(value, p->membase + offset);
416 }
417
418 static void mem32_serial_out(struct uart_port *p, int offset, int value)
419 {
420 offset = offset << p->regshift;
421 writel(value, p->membase + offset);
422 }
423
424 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
425 {
426 offset = offset << p->regshift;
427 return readl(p->membase + offset);
428 }
429
430 static unsigned int io_serial_in(struct uart_port *p, int offset)
431 {
432 offset = offset << p->regshift;
433 return inb(p->iobase + offset);
434 }
435
436 static void io_serial_out(struct uart_port *p, int offset, int value)
437 {
438 offset = offset << p->regshift;
439 outb(value, p->iobase + offset);
440 }
441
442 static int serial8250_default_handle_irq(struct uart_port *port);
443 static int exar_handle_irq(struct uart_port *port);
444
445 static void set_io_from_upio(struct uart_port *p)
446 {
447 struct uart_8250_port *up = up_to_u8250p(p);
448
449 up->dl_read = default_serial_dl_read;
450 up->dl_write = default_serial_dl_write;
451
452 switch (p->iotype) {
453 case UPIO_HUB6:
454 p->serial_in = hub6_serial_in;
455 p->serial_out = hub6_serial_out;
456 break;
457
458 case UPIO_MEM:
459 p->serial_in = mem_serial_in;
460 p->serial_out = mem_serial_out;
461 break;
462
463 case UPIO_MEM32:
464 p->serial_in = mem32_serial_in;
465 p->serial_out = mem32_serial_out;
466 break;
467
468 #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
469 case UPIO_AU:
470 p->serial_in = au_serial_in;
471 p->serial_out = au_serial_out;
472 up->dl_read = au_serial_dl_read;
473 up->dl_write = au_serial_dl_write;
474 break;
475 #endif
476
477 default:
478 p->serial_in = io_serial_in;
479 p->serial_out = io_serial_out;
480 break;
481 }
482 /* Remember loaded iotype */
483 up->cur_iotype = p->iotype;
484 p->handle_irq = serial8250_default_handle_irq;
485 }
486
487 static void
488 serial_port_out_sync(struct uart_port *p, int offset, int value)
489 {
490 switch (p->iotype) {
491 case UPIO_MEM:
492 case UPIO_MEM32:
493 case UPIO_AU:
494 p->serial_out(p, offset, value);
495 p->serial_in(p, UART_LCR); /* safe, no side-effects */
496 break;
497 default:
498 p->serial_out(p, offset, value);
499 }
500 }
501
502 /*
503 * For the 16C950
504 */
505 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
506 {
507 serial_out(up, UART_SCR, offset);
508 serial_out(up, UART_ICR, value);
509 }
510
511 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
512 {
513 unsigned int value;
514
515 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
516 serial_out(up, UART_SCR, offset);
517 value = serial_in(up, UART_ICR);
518 serial_icr_write(up, UART_ACR, up->acr);
519
520 return value;
521 }
522
523 /*
524 * FIFO support.
525 */
526 static void serial8250_clear_fifos(struct uart_8250_port *p)
527 {
528 if (p->capabilities & UART_CAP_FIFO) {
529 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
530 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
531 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
532 serial_out(p, UART_FCR, 0);
533 }
534 }
535
536 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
537 {
538 serial8250_clear_fifos(p);
539 serial_out(p, UART_FCR, p->fcr);
540 }
541 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
542
543 /*
544 * IER sleep support. UARTs which have EFRs need the "extended
545 * capability" bit enabled. Note that on XR16C850s, we need to
546 * reset LCR to write to IER.
547 */
548 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
549 {
550 /*
551 * Exar UARTs have a SLEEP register that enables or disables
552 * each UART to enter sleep mode separately. On the XR17V35x the
553 * register is accessible to each UART at the UART_EXAR_SLEEP
554 * offset but the UART channel may only write to the corresponding
555 * bit.
556 */
557 if ((p->port.type == PORT_XR17V35X) ||
558 (p->port.type == PORT_XR17D15X)) {
559 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
560 return;
561 }
562
563 if (p->capabilities & UART_CAP_SLEEP) {
564 if (p->capabilities & UART_CAP_EFR) {
565 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
566 serial_out(p, UART_EFR, UART_EFR_ECB);
567 serial_out(p, UART_LCR, 0);
568 }
569 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
570 if (p->capabilities & UART_CAP_EFR) {
571 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
572 serial_out(p, UART_EFR, 0);
573 serial_out(p, UART_LCR, 0);
574 }
575 }
576 }
577
578 #ifdef CONFIG_SERIAL_8250_RSA
579 /*
580 * Attempts to turn on the RSA FIFO. Returns zero on failure.
581 * We set the port uart clock rate if we succeed.
582 */
583 static int __enable_rsa(struct uart_8250_port *up)
584 {
585 unsigned char mode;
586 int result;
587
588 mode = serial_in(up, UART_RSA_MSR);
589 result = mode & UART_RSA_MSR_FIFO;
590
591 if (!result) {
592 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
593 mode = serial_in(up, UART_RSA_MSR);
594 result = mode & UART_RSA_MSR_FIFO;
595 }
596
597 if (result)
598 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
599
600 return result;
601 }
602
603 static void enable_rsa(struct uart_8250_port *up)
604 {
605 if (up->port.type == PORT_RSA) {
606 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
607 spin_lock_irq(&up->port.lock);
608 __enable_rsa(up);
609 spin_unlock_irq(&up->port.lock);
610 }
611 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
612 serial_out(up, UART_RSA_FRR, 0);
613 }
614 }
615
616 /*
617 * Attempts to turn off the RSA FIFO. Returns zero on failure.
618 * It is unknown why interrupts were disabled in here. However,
619 * the caller is expected to preserve this behaviour by grabbing
620 * the spinlock before calling this function.
621 */
622 static void disable_rsa(struct uart_8250_port *up)
623 {
624 unsigned char mode;
625 int result;
626
627 if (up->port.type == PORT_RSA &&
628 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
629 spin_lock_irq(&up->port.lock);
630
631 mode = serial_in(up, UART_RSA_MSR);
632 result = !(mode & UART_RSA_MSR_FIFO);
633
634 if (!result) {
635 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
636 mode = serial_in(up, UART_RSA_MSR);
637 result = !(mode & UART_RSA_MSR_FIFO);
638 }
639
640 if (result)
641 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
642 spin_unlock_irq(&up->port.lock);
643 }
644 }
645 #endif /* CONFIG_SERIAL_8250_RSA */
646
647 /*
648 * This is a quickie test to see how big the FIFO is.
649 * It doesn't work at all the time, more's the pity.
650 */
651 static int size_fifo(struct uart_8250_port *up)
652 {
653 unsigned char old_fcr, old_mcr, old_lcr;
654 unsigned short old_dl;
655 int count;
656
657 old_lcr = serial_in(up, UART_LCR);
658 serial_out(up, UART_LCR, 0);
659 old_fcr = serial_in(up, UART_FCR);
660 old_mcr = serial_in(up, UART_MCR);
661 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
662 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
663 serial_out(up, UART_MCR, UART_MCR_LOOP);
664 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
665 old_dl = serial_dl_read(up);
666 serial_dl_write(up, 0x0001);
667 serial_out(up, UART_LCR, 0x03);
668 for (count = 0; count < 256; count++)
669 serial_out(up, UART_TX, count);
670 mdelay(20);/* FIXME - schedule_timeout */
671 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
672 (count < 256); count++)
673 serial_in(up, UART_RX);
674 serial_out(up, UART_FCR, old_fcr);
675 serial_out(up, UART_MCR, old_mcr);
676 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
677 serial_dl_write(up, old_dl);
678 serial_out(up, UART_LCR, old_lcr);
679
680 return count;
681 }
682
683 /*
684 * Read UART ID using the divisor method - set DLL and DLM to zero
685 * and the revision will be in DLL and device type in DLM. We
686 * preserve the device state across this.
687 */
688 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
689 {
690 unsigned char old_dll, old_dlm, old_lcr;
691 unsigned int id;
692
693 old_lcr = serial_in(p, UART_LCR);
694 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
695
696 old_dll = serial_in(p, UART_DLL);
697 old_dlm = serial_in(p, UART_DLM);
698
699 serial_out(p, UART_DLL, 0);
700 serial_out(p, UART_DLM, 0);
701
702 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
703
704 serial_out(p, UART_DLL, old_dll);
705 serial_out(p, UART_DLM, old_dlm);
706 serial_out(p, UART_LCR, old_lcr);
707
708 return id;
709 }
710
711 /*
712 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
713 * When this function is called we know it is at least a StarTech
714 * 16650 V2, but it might be one of several StarTech UARTs, or one of
715 * its clones. (We treat the broken original StarTech 16650 V1 as a
716 * 16550, and why not? Startech doesn't seem to even acknowledge its
717 * existence.)
718 *
719 * What evil have men's minds wrought...
720 */
721 static void autoconfig_has_efr(struct uart_8250_port *up)
722 {
723 unsigned int id1, id2, id3, rev;
724
725 /*
726 * Everything with an EFR has SLEEP
727 */
728 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
729
730 /*
731 * First we check to see if it's an Oxford Semiconductor UART.
732 *
733 * If we have to do this here because some non-National
734 * Semiconductor clone chips lock up if you try writing to the
735 * LSR register (which serial_icr_read does)
736 */
737
738 /*
739 * Check for Oxford Semiconductor 16C950.
740 *
741 * EFR [4] must be set else this test fails.
742 *
743 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
744 * claims that it's needed for 952 dual UART's (which are not
745 * recommended for new designs).
746 */
747 up->acr = 0;
748 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
749 serial_out(up, UART_EFR, UART_EFR_ECB);
750 serial_out(up, UART_LCR, 0x00);
751 id1 = serial_icr_read(up, UART_ID1);
752 id2 = serial_icr_read(up, UART_ID2);
753 id3 = serial_icr_read(up, UART_ID3);
754 rev = serial_icr_read(up, UART_REV);
755
756 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
757
758 if (id1 == 0x16 && id2 == 0xC9 &&
759 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
760 up->port.type = PORT_16C950;
761
762 /*
763 * Enable work around for the Oxford Semiconductor 952 rev B
764 * chip which causes it to seriously miscalculate baud rates
765 * when DLL is 0.
766 */
767 if (id3 == 0x52 && rev == 0x01)
768 up->bugs |= UART_BUG_QUOT;
769 return;
770 }
771
772 /*
773 * We check for a XR16C850 by setting DLL and DLM to 0, and then
774 * reading back DLL and DLM. The chip type depends on the DLM
775 * value read back:
776 * 0x10 - XR16C850 and the DLL contains the chip revision.
777 * 0x12 - XR16C2850.
778 * 0x14 - XR16C854.
779 */
780 id1 = autoconfig_read_divisor_id(up);
781 DEBUG_AUTOCONF("850id=%04x ", id1);
782
783 id2 = id1 >> 8;
784 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
785 up->port.type = PORT_16850;
786 return;
787 }
788
789 /*
790 * It wasn't an XR16C850.
791 *
792 * We distinguish between the '654 and the '650 by counting
793 * how many bytes are in the FIFO. I'm using this for now,
794 * since that's the technique that was sent to me in the
795 * serial driver update, but I'm not convinced this works.
796 * I've had problems doing this in the past. -TYT
797 */
798 if (size_fifo(up) == 64)
799 up->port.type = PORT_16654;
800 else
801 up->port.type = PORT_16650V2;
802 }
803
804 /*
805 * We detected a chip without a FIFO. Only two fall into
806 * this category - the original 8250 and the 16450. The
807 * 16450 has a scratch register (accessible with LCR=0)
808 */
809 static void autoconfig_8250(struct uart_8250_port *up)
810 {
811 unsigned char scratch, status1, status2;
812
813 up->port.type = PORT_8250;
814
815 scratch = serial_in(up, UART_SCR);
816 serial_out(up, UART_SCR, 0xa5);
817 status1 = serial_in(up, UART_SCR);
818 serial_out(up, UART_SCR, 0x5a);
819 status2 = serial_in(up, UART_SCR);
820 serial_out(up, UART_SCR, scratch);
821
822 if (status1 == 0xa5 && status2 == 0x5a)
823 up->port.type = PORT_16450;
824 }
825
826 static int broken_efr(struct uart_8250_port *up)
827 {
828 /*
829 * Exar ST16C2550 "A2" devices incorrectly detect as
830 * having an EFR, and report an ID of 0x0201. See
831 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
832 */
833 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
834 return 1;
835
836 return 0;
837 }
838
839 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
840 {
841 unsigned char status;
842
843 status = serial_in(up, 0x04); /* EXCR2 */
844 #define PRESL(x) ((x) & 0x30)
845 if (PRESL(status) == 0x10) {
846 /* already in high speed mode */
847 return 0;
848 } else {
849 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
850 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
851 serial_out(up, 0x04, status);
852 }
853 return 1;
854 }
855
856 /*
857 * We know that the chip has FIFOs. Does it have an EFR? The
858 * EFR is located in the same register position as the IIR and
859 * we know the top two bits of the IIR are currently set. The
860 * EFR should contain zero. Try to read the EFR.
861 */
862 static void autoconfig_16550a(struct uart_8250_port *up)
863 {
864 unsigned char status1, status2;
865 unsigned int iersave;
866
867 up->port.type = PORT_16550A;
868 up->capabilities |= UART_CAP_FIFO;
869
870 /*
871 * XR17V35x UARTs have an extra divisor register, DLD
872 * that gets enabled with when DLAB is set which will
873 * cause the device to incorrectly match and assign
874 * port type to PORT_16650. The EFR for this UART is
875 * found at offset 0x09. Instead check the Deice ID (DVID)
876 * register for a 2, 4 or 8 port UART.
877 */
878 if (up->port.flags & UPF_EXAR_EFR) {
879 status1 = serial_in(up, UART_EXAR_DVID);
880 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
881 DEBUG_AUTOCONF("Exar XR17V35x ");
882 up->port.type = PORT_XR17V35X;
883 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
884 UART_CAP_SLEEP;
885
886 return;
887 }
888
889 }
890
891 /*
892 * Check for presence of the EFR when DLAB is set.
893 * Only ST16C650V1 UARTs pass this test.
894 */
895 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
896 if (serial_in(up, UART_EFR) == 0) {
897 serial_out(up, UART_EFR, 0xA8);
898 if (serial_in(up, UART_EFR) != 0) {
899 DEBUG_AUTOCONF("EFRv1 ");
900 up->port.type = PORT_16650;
901 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
902 } else {
903 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
904 }
905 serial_out(up, UART_EFR, 0);
906 return;
907 }
908
909 /*
910 * Maybe it requires 0xbf to be written to the LCR.
911 * (other ST16C650V2 UARTs, TI16C752A, etc)
912 */
913 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
914 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
915 DEBUG_AUTOCONF("EFRv2 ");
916 autoconfig_has_efr(up);
917 return;
918 }
919
920 /*
921 * Check for a National Semiconductor SuperIO chip.
922 * Attempt to switch to bank 2, read the value of the LOOP bit
923 * from EXCR1. Switch back to bank 0, change it in MCR. Then
924 * switch back to bank 2, read it from EXCR1 again and check
925 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
926 */
927 serial_out(up, UART_LCR, 0);
928 status1 = serial_in(up, UART_MCR);
929 serial_out(up, UART_LCR, 0xE0);
930 status2 = serial_in(up, 0x02); /* EXCR1 */
931
932 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
933 serial_out(up, UART_LCR, 0);
934 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
935 serial_out(up, UART_LCR, 0xE0);
936 status2 = serial_in(up, 0x02); /* EXCR1 */
937 serial_out(up, UART_LCR, 0);
938 serial_out(up, UART_MCR, status1);
939
940 if ((status2 ^ status1) & UART_MCR_LOOP) {
941 unsigned short quot;
942
943 serial_out(up, UART_LCR, 0xE0);
944
945 quot = serial_dl_read(up);
946 quot <<= 3;
947
948 if (ns16550a_goto_highspeed(up))
949 serial_dl_write(up, quot);
950
951 serial_out(up, UART_LCR, 0);
952
953 up->port.uartclk = 921600*16;
954 up->port.type = PORT_NS16550A;
955 up->capabilities |= UART_NATSEMI;
956 return;
957 }
958 }
959
960 /*
961 * No EFR. Try to detect a TI16750, which only sets bit 5 of
962 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
963 * Try setting it with and without DLAB set. Cheap clones
964 * set bit 5 without DLAB set.
965 */
966 serial_out(up, UART_LCR, 0);
967 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
968 status1 = serial_in(up, UART_IIR) >> 5;
969 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
970 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
971 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
972 status2 = serial_in(up, UART_IIR) >> 5;
973 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
974 serial_out(up, UART_LCR, 0);
975
976 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
977
978 if (status1 == 6 && status2 == 7) {
979 up->port.type = PORT_16750;
980 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
981 return;
982 }
983
984 /*
985 * Try writing and reading the UART_IER_UUE bit (b6).
986 * If it works, this is probably one of the Xscale platform's
987 * internal UARTs.
988 * We're going to explicitly set the UUE bit to 0 before
989 * trying to write and read a 1 just to make sure it's not
990 * already a 1 and maybe locked there before we even start start.
991 */
992 iersave = serial_in(up, UART_IER);
993 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
994 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
995 /*
996 * OK it's in a known zero state, try writing and reading
997 * without disturbing the current state of the other bits.
998 */
999 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1000 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1001 /*
1002 * It's an Xscale.
1003 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1004 */
1005 DEBUG_AUTOCONF("Xscale ");
1006 up->port.type = PORT_XSCALE;
1007 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1008 return;
1009 }
1010 } else {
1011 /*
1012 * If we got here we couldn't force the IER_UUE bit to 0.
1013 * Log it and continue.
1014 */
1015 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1016 }
1017 serial_out(up, UART_IER, iersave);
1018
1019 /*
1020 * Exar uarts have EFR in a weird location
1021 */
1022 if (up->port.flags & UPF_EXAR_EFR) {
1023 DEBUG_AUTOCONF("Exar XR17D15x ");
1024 up->port.type = PORT_XR17D15X;
1025 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1026 UART_CAP_SLEEP;
1027
1028 return;
1029 }
1030
1031 /*
1032 * We distinguish between 16550A and U6 16550A by counting
1033 * how many bytes are in the FIFO.
1034 */
1035 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1036 up->port.type = PORT_U6_16550A;
1037 up->capabilities |= UART_CAP_AFE;
1038 }
1039 }
1040
1041 /*
1042 * This routine is called by rs_init() to initialize a specific serial
1043 * port. It determines what type of UART chip this serial port is
1044 * using: 8250, 16450, 16550, 16550A. The important question is
1045 * whether or not this UART is a 16550A or not, since this will
1046 * determine whether or not we can use its FIFO features or not.
1047 */
1048 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1049 {
1050 unsigned char status1, scratch, scratch2, scratch3;
1051 unsigned char save_lcr, save_mcr;
1052 struct uart_port *port = &up->port;
1053 unsigned long flags;
1054 unsigned int old_capabilities;
1055
1056 if (!port->iobase && !port->mapbase && !port->membase)
1057 return;
1058
1059 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1060 serial_index(port), port->iobase, port->membase);
1061
1062 /*
1063 * We really do need global IRQs disabled here - we're going to
1064 * be frobbing the chips IRQ enable register to see if it exists.
1065 */
1066 spin_lock_irqsave(&port->lock, flags);
1067
1068 up->capabilities = 0;
1069 up->bugs = 0;
1070
1071 if (!(port->flags & UPF_BUGGY_UART)) {
1072 /*
1073 * Do a simple existence test first; if we fail this,
1074 * there's no point trying anything else.
1075 *
1076 * 0x80 is used as a nonsense port to prevent against
1077 * false positives due to ISA bus float. The
1078 * assumption is that 0x80 is a non-existent port;
1079 * which should be safe since include/asm/io.h also
1080 * makes this assumption.
1081 *
1082 * Note: this is safe as long as MCR bit 4 is clear
1083 * and the device is in "PC" mode.
1084 */
1085 scratch = serial_in(up, UART_IER);
1086 serial_out(up, UART_IER, 0);
1087 #ifdef __i386__
1088 outb(0xff, 0x080);
1089 #endif
1090 /*
1091 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1092 * 16C754B) allow only to modify them if an EFR bit is set.
1093 */
1094 scratch2 = serial_in(up, UART_IER) & 0x0f;
1095 serial_out(up, UART_IER, 0x0F);
1096 #ifdef __i386__
1097 outb(0, 0x080);
1098 #endif
1099 scratch3 = serial_in(up, UART_IER) & 0x0f;
1100 serial_out(up, UART_IER, scratch);
1101 if (scratch2 != 0 || scratch3 != 0x0F) {
1102 /*
1103 * We failed; there's nothing here
1104 */
1105 spin_unlock_irqrestore(&port->lock, flags);
1106 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1107 scratch2, scratch3);
1108 goto out;
1109 }
1110 }
1111
1112 save_mcr = serial_in(up, UART_MCR);
1113 save_lcr = serial_in(up, UART_LCR);
1114
1115 /*
1116 * Check to see if a UART is really there. Certain broken
1117 * internal modems based on the Rockwell chipset fail this
1118 * test, because they apparently don't implement the loopback
1119 * test mode. So this test is skipped on the COM 1 through
1120 * COM 4 ports. This *should* be safe, since no board
1121 * manufacturer would be stupid enough to design a board
1122 * that conflicts with COM 1-4 --- we hope!
1123 */
1124 if (!(port->flags & UPF_SKIP_TEST)) {
1125 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1126 status1 = serial_in(up, UART_MSR) & 0xF0;
1127 serial_out(up, UART_MCR, save_mcr);
1128 if (status1 != 0x90) {
1129 spin_unlock_irqrestore(&port->lock, flags);
1130 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1131 status1);
1132 goto out;
1133 }
1134 }
1135
1136 /*
1137 * We're pretty sure there's a port here. Lets find out what
1138 * type of port it is. The IIR top two bits allows us to find
1139 * out if it's 8250 or 16450, 16550, 16550A or later. This
1140 * determines what we test for next.
1141 *
1142 * We also initialise the EFR (if any) to zero for later. The
1143 * EFR occupies the same register location as the FCR and IIR.
1144 */
1145 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1146 serial_out(up, UART_EFR, 0);
1147 serial_out(up, UART_LCR, 0);
1148
1149 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1150 scratch = serial_in(up, UART_IIR) >> 6;
1151
1152 switch (scratch) {
1153 case 0:
1154 autoconfig_8250(up);
1155 break;
1156 case 1:
1157 port->type = PORT_UNKNOWN;
1158 break;
1159 case 2:
1160 port->type = PORT_16550;
1161 break;
1162 case 3:
1163 autoconfig_16550a(up);
1164 break;
1165 }
1166
1167 #ifdef CONFIG_SERIAL_8250_RSA
1168 /*
1169 * Only probe for RSA ports if we got the region.
1170 */
1171 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1172 int i;
1173
1174 for (i = 0 ; i < probe_rsa_count; ++i) {
1175 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1176 port->type = PORT_RSA;
1177 break;
1178 }
1179 }
1180 }
1181 #endif
1182
1183 serial_out(up, UART_LCR, save_lcr);
1184
1185 port->fifosize = uart_config[up->port.type].fifo_size;
1186 old_capabilities = up->capabilities;
1187 up->capabilities = uart_config[port->type].flags;
1188 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1189
1190 if (port->type == PORT_UNKNOWN)
1191 goto out_lock;
1192
1193 /*
1194 * Reset the UART.
1195 */
1196 #ifdef CONFIG_SERIAL_8250_RSA
1197 if (port->type == PORT_RSA)
1198 serial_out(up, UART_RSA_FRR, 0);
1199 #endif
1200 serial_out(up, UART_MCR, save_mcr);
1201 serial8250_clear_fifos(up);
1202 serial_in(up, UART_RX);
1203 if (up->capabilities & UART_CAP_UUE)
1204 serial_out(up, UART_IER, UART_IER_UUE);
1205 else
1206 serial_out(up, UART_IER, 0);
1207
1208 out_lock:
1209 spin_unlock_irqrestore(&port->lock, flags);
1210 if (up->capabilities != old_capabilities) {
1211 printk(KERN_WARNING
1212 "ttyS%d: detected caps %08x should be %08x\n",
1213 serial_index(port), old_capabilities,
1214 up->capabilities);
1215 }
1216 out:
1217 DEBUG_AUTOCONF("iir=%d ", scratch);
1218 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1219 }
1220
1221 static void autoconfig_irq(struct uart_8250_port *up)
1222 {
1223 struct uart_port *port = &up->port;
1224 unsigned char save_mcr, save_ier;
1225 unsigned char save_ICP = 0;
1226 unsigned int ICP = 0;
1227 unsigned long irqs;
1228 int irq;
1229
1230 if (port->flags & UPF_FOURPORT) {
1231 ICP = (port->iobase & 0xfe0) | 0x1f;
1232 save_ICP = inb_p(ICP);
1233 outb_p(0x80, ICP);
1234 inb_p(ICP);
1235 }
1236
1237 /* forget possible initially masked and pending IRQ */
1238 probe_irq_off(probe_irq_on());
1239 save_mcr = serial_in(up, UART_MCR);
1240 save_ier = serial_in(up, UART_IER);
1241 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1242
1243 irqs = probe_irq_on();
1244 serial_out(up, UART_MCR, 0);
1245 udelay(10);
1246 if (port->flags & UPF_FOURPORT) {
1247 serial_out(up, UART_MCR,
1248 UART_MCR_DTR | UART_MCR_RTS);
1249 } else {
1250 serial_out(up, UART_MCR,
1251 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1252 }
1253 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1254 serial_in(up, UART_LSR);
1255 serial_in(up, UART_RX);
1256 serial_in(up, UART_IIR);
1257 serial_in(up, UART_MSR);
1258 serial_out(up, UART_TX, 0xFF);
1259 udelay(20);
1260 irq = probe_irq_off(irqs);
1261
1262 serial_out(up, UART_MCR, save_mcr);
1263 serial_out(up, UART_IER, save_ier);
1264
1265 if (port->flags & UPF_FOURPORT)
1266 outb_p(save_ICP, ICP);
1267
1268 port->irq = (irq > 0) ? irq : 0;
1269 }
1270
1271 static inline void __stop_tx(struct uart_8250_port *p)
1272 {
1273 if (p->ier & UART_IER_THRI) {
1274 p->ier &= ~UART_IER_THRI;
1275 serial_out(p, UART_IER, p->ier);
1276 }
1277 }
1278
1279 static void serial8250_stop_tx(struct uart_port *port)
1280 {
1281 struct uart_8250_port *up = up_to_u8250p(port);
1282
1283 __stop_tx(up);
1284
1285 /*
1286 * We really want to stop the transmitter from sending.
1287 */
1288 if (port->type == PORT_16C950) {
1289 up->acr |= UART_ACR_TXDIS;
1290 serial_icr_write(up, UART_ACR, up->acr);
1291 }
1292 }
1293
1294 static void serial8250_start_tx(struct uart_port *port)
1295 {
1296 struct uart_8250_port *up = up_to_u8250p(port);
1297
1298 if (up->dma && !serial8250_tx_dma(up)) {
1299 return;
1300 } else if (!(up->ier & UART_IER_THRI)) {
1301 up->ier |= UART_IER_THRI;
1302 serial_port_out(port, UART_IER, up->ier);
1303
1304 if (up->bugs & UART_BUG_TXEN) {
1305 unsigned char lsr;
1306 lsr = serial_in(up, UART_LSR);
1307 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1308 if (lsr & UART_LSR_TEMT)
1309 serial8250_tx_chars(up);
1310 }
1311 }
1312
1313 /*
1314 * Re-enable the transmitter if we disabled it.
1315 */
1316 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1317 up->acr &= ~UART_ACR_TXDIS;
1318 serial_icr_write(up, UART_ACR, up->acr);
1319 }
1320 }
1321
1322 static void serial8250_throttle(struct uart_port *port)
1323 {
1324 port->throttle(port);
1325 }
1326
1327 static void serial8250_unthrottle(struct uart_port *port)
1328 {
1329 port->unthrottle(port);
1330 }
1331
1332 static void serial8250_stop_rx(struct uart_port *port)
1333 {
1334 struct uart_8250_port *up = up_to_u8250p(port);
1335
1336 up->ier &= ~UART_IER_RLSI;
1337 up->port.read_status_mask &= ~UART_LSR_DR;
1338 serial_port_out(port, UART_IER, up->ier);
1339 }
1340
1341 static void serial8250_enable_ms(struct uart_port *port)
1342 {
1343 struct uart_8250_port *up = up_to_u8250p(port);
1344
1345 /* no MSR capabilities */
1346 if (up->bugs & UART_BUG_NOMSR)
1347 return;
1348
1349 up->ier |= UART_IER_MSI;
1350 serial_port_out(port, UART_IER, up->ier);
1351 }
1352
1353 /*
1354 * serial8250_rx_chars: processes according to the passed in LSR
1355 * value, and returns the remaining LSR bits not handled
1356 * by this Rx routine.
1357 */
1358 unsigned char
1359 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1360 {
1361 struct uart_port *port = &up->port;
1362 unsigned char ch;
1363 int max_count = 256;
1364 char flag;
1365
1366 do {
1367 if (likely(lsr & UART_LSR_DR))
1368 ch = serial_in(up, UART_RX);
1369 else
1370 /*
1371 * Intel 82571 has a Serial Over Lan device that will
1372 * set UART_LSR_BI without setting UART_LSR_DR when
1373 * it receives a break. To avoid reading from the
1374 * receive buffer without UART_LSR_DR bit set, we
1375 * just force the read character to be 0
1376 */
1377 ch = 0;
1378
1379 flag = TTY_NORMAL;
1380 port->icount.rx++;
1381
1382 lsr |= up->lsr_saved_flags;
1383 up->lsr_saved_flags = 0;
1384
1385 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1386 if (lsr & UART_LSR_BI) {
1387 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1388 port->icount.brk++;
1389 /*
1390 * We do the SysRQ and SAK checking
1391 * here because otherwise the break
1392 * may get masked by ignore_status_mask
1393 * or read_status_mask.
1394 */
1395 if (uart_handle_break(port))
1396 goto ignore_char;
1397 } else if (lsr & UART_LSR_PE)
1398 port->icount.parity++;
1399 else if (lsr & UART_LSR_FE)
1400 port->icount.frame++;
1401 if (lsr & UART_LSR_OE)
1402 port->icount.overrun++;
1403
1404 /*
1405 * Mask off conditions which should be ignored.
1406 */
1407 lsr &= port->read_status_mask;
1408
1409 if (lsr & UART_LSR_BI) {
1410 DEBUG_INTR("handling break....");
1411 flag = TTY_BREAK;
1412 } else if (lsr & UART_LSR_PE)
1413 flag = TTY_PARITY;
1414 else if (lsr & UART_LSR_FE)
1415 flag = TTY_FRAME;
1416 }
1417 if (uart_handle_sysrq_char(port, ch))
1418 goto ignore_char;
1419
1420 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1421
1422 ignore_char:
1423 lsr = serial_in(up, UART_LSR);
1424 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1425 spin_unlock(&port->lock);
1426 tty_flip_buffer_push(&port->state->port);
1427 spin_lock(&port->lock);
1428 return lsr;
1429 }
1430 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1431
1432 void serial8250_tx_chars(struct uart_8250_port *up)
1433 {
1434 struct uart_port *port = &up->port;
1435 struct circ_buf *xmit = &port->state->xmit;
1436 int count;
1437
1438 if (port->x_char) {
1439 serial_out(up, UART_TX, port->x_char);
1440 port->icount.tx++;
1441 port->x_char = 0;
1442 return;
1443 }
1444 if (uart_tx_stopped(port)) {
1445 serial8250_stop_tx(port);
1446 return;
1447 }
1448 if (uart_circ_empty(xmit)) {
1449 __stop_tx(up);
1450 return;
1451 }
1452
1453 count = up->tx_loadsz;
1454 do {
1455 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1456 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1457 port->icount.tx++;
1458 if (uart_circ_empty(xmit))
1459 break;
1460 if (up->capabilities & UART_CAP_HFIFO) {
1461 if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1462 BOTH_EMPTY)
1463 break;
1464 }
1465 } while (--count > 0);
1466
1467 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1468 uart_write_wakeup(port);
1469
1470 DEBUG_INTR("THRE...");
1471
1472 if (uart_circ_empty(xmit))
1473 __stop_tx(up);
1474 }
1475 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1476
1477 /* Caller holds uart port lock */
1478 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1479 {
1480 struct uart_port *port = &up->port;
1481 unsigned int status = serial_in(up, UART_MSR);
1482
1483 status |= up->msr_saved_flags;
1484 up->msr_saved_flags = 0;
1485 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1486 port->state != NULL) {
1487 if (status & UART_MSR_TERI)
1488 port->icount.rng++;
1489 if (status & UART_MSR_DDSR)
1490 port->icount.dsr++;
1491 if (status & UART_MSR_DDCD)
1492 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1493 if (status & UART_MSR_DCTS)
1494 uart_handle_cts_change(port, status & UART_MSR_CTS);
1495
1496 wake_up_interruptible(&port->state->port.delta_msr_wait);
1497 }
1498
1499 return status;
1500 }
1501 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1502
1503 /*
1504 * This handles the interrupt from one port.
1505 */
1506 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1507 {
1508 unsigned char status;
1509 unsigned long flags;
1510 struct uart_8250_port *up = up_to_u8250p(port);
1511 int dma_err = 0;
1512
1513 if (iir & UART_IIR_NO_INT)
1514 return 0;
1515
1516 spin_lock_irqsave(&port->lock, flags);
1517
1518 status = serial_port_in(port, UART_LSR);
1519
1520 DEBUG_INTR("status = %x...", status);
1521
1522 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1523 if (up->dma)
1524 dma_err = serial8250_rx_dma(up, iir);
1525
1526 if (!up->dma || dma_err)
1527 status = serial8250_rx_chars(up, status);
1528 }
1529 serial8250_modem_status(up);
1530 if (!up->dma && (status & UART_LSR_THRE))
1531 serial8250_tx_chars(up);
1532
1533 spin_unlock_irqrestore(&port->lock, flags);
1534 return 1;
1535 }
1536 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1537
1538 static int serial8250_default_handle_irq(struct uart_port *port)
1539 {
1540 unsigned int iir = serial_port_in(port, UART_IIR);
1541
1542 return serial8250_handle_irq(port, iir);
1543 }
1544
1545 /*
1546 * These Exar UARTs have an extra interrupt indicator that could
1547 * fire for a few unimplemented interrupts. One of which is a
1548 * wakeup event when coming out of sleep. Put this here just
1549 * to be on the safe side that these interrupts don't go unhandled.
1550 */
1551 static int exar_handle_irq(struct uart_port *port)
1552 {
1553 unsigned char int0, int1, int2, int3;
1554 unsigned int iir = serial_port_in(port, UART_IIR);
1555 int ret;
1556
1557 ret = serial8250_handle_irq(port, iir);
1558
1559 if ((port->type == PORT_XR17V35X) ||
1560 (port->type == PORT_XR17D15X)) {
1561 int0 = serial_port_in(port, 0x80);
1562 int1 = serial_port_in(port, 0x81);
1563 int2 = serial_port_in(port, 0x82);
1564 int3 = serial_port_in(port, 0x83);
1565 }
1566
1567 return ret;
1568 }
1569
1570 /*
1571 * This is the serial driver's interrupt routine.
1572 *
1573 * Arjan thinks the old way was overly complex, so it got simplified.
1574 * Alan disagrees, saying that need the complexity to handle the weird
1575 * nature of ISA shared interrupts. (This is a special exception.)
1576 *
1577 * In order to handle ISA shared interrupts properly, we need to check
1578 * that all ports have been serviced, and therefore the ISA interrupt
1579 * line has been de-asserted.
1580 *
1581 * This means we need to loop through all ports. checking that they
1582 * don't have an interrupt pending.
1583 */
1584 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1585 {
1586 struct irq_info *i = dev_id;
1587 struct list_head *l, *end = NULL;
1588 int pass_counter = 0, handled = 0;
1589
1590 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1591
1592 spin_lock(&i->lock);
1593
1594 l = i->head;
1595 do {
1596 struct uart_8250_port *up;
1597 struct uart_port *port;
1598
1599 up = list_entry(l, struct uart_8250_port, list);
1600 port = &up->port;
1601
1602 if (port->handle_irq(port)) {
1603 handled = 1;
1604 end = NULL;
1605 } else if (end == NULL)
1606 end = l;
1607
1608 l = l->next;
1609
1610 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1611 /* If we hit this, we're dead. */
1612 printk_ratelimited(KERN_ERR
1613 "serial8250: too much work for irq%d\n", irq);
1614 break;
1615 }
1616 } while (l != end);
1617
1618 spin_unlock(&i->lock);
1619
1620 DEBUG_INTR("end.\n");
1621
1622 return IRQ_RETVAL(handled);
1623 }
1624
1625 /*
1626 * To support ISA shared interrupts, we need to have one interrupt
1627 * handler that ensures that the IRQ line has been deasserted
1628 * before returning. Failing to do this will result in the IRQ
1629 * line being stuck active, and, since ISA irqs are edge triggered,
1630 * no more IRQs will be seen.
1631 */
1632 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1633 {
1634 spin_lock_irq(&i->lock);
1635
1636 if (!list_empty(i->head)) {
1637 if (i->head == &up->list)
1638 i->head = i->head->next;
1639 list_del(&up->list);
1640 } else {
1641 BUG_ON(i->head != &up->list);
1642 i->head = NULL;
1643 }
1644 spin_unlock_irq(&i->lock);
1645 /* List empty so throw away the hash node */
1646 if (i->head == NULL) {
1647 hlist_del(&i->node);
1648 kfree(i);
1649 }
1650 }
1651
1652 static int serial_link_irq_chain(struct uart_8250_port *up)
1653 {
1654 struct hlist_head *h;
1655 struct hlist_node *n;
1656 struct irq_info *i;
1657 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1658
1659 mutex_lock(&hash_mutex);
1660
1661 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1662
1663 hlist_for_each(n, h) {
1664 i = hlist_entry(n, struct irq_info, node);
1665 if (i->irq == up->port.irq)
1666 break;
1667 }
1668
1669 if (n == NULL) {
1670 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1671 if (i == NULL) {
1672 mutex_unlock(&hash_mutex);
1673 return -ENOMEM;
1674 }
1675 spin_lock_init(&i->lock);
1676 i->irq = up->port.irq;
1677 hlist_add_head(&i->node, h);
1678 }
1679 mutex_unlock(&hash_mutex);
1680
1681 spin_lock_irq(&i->lock);
1682
1683 if (i->head) {
1684 list_add(&up->list, i->head);
1685 spin_unlock_irq(&i->lock);
1686
1687 ret = 0;
1688 } else {
1689 INIT_LIST_HEAD(&up->list);
1690 i->head = &up->list;
1691 spin_unlock_irq(&i->lock);
1692 irq_flags |= up->port.irqflags;
1693 ret = request_irq(up->port.irq, serial8250_interrupt,
1694 irq_flags, "serial", i);
1695 if (ret < 0)
1696 serial_do_unlink(i, up);
1697 }
1698
1699 return ret;
1700 }
1701
1702 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1703 {
1704 /*
1705 * yes, some broken gcc emit "warning: 'i' may be used uninitialized"
1706 * but no, we are not going to take a patch that assigns NULL below.
1707 */
1708 struct irq_info *i;
1709 struct hlist_node *n;
1710 struct hlist_head *h;
1711
1712 mutex_lock(&hash_mutex);
1713
1714 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1715
1716 hlist_for_each(n, h) {
1717 i = hlist_entry(n, struct irq_info, node);
1718 if (i->irq == up->port.irq)
1719 break;
1720 }
1721
1722 BUG_ON(n == NULL);
1723 BUG_ON(i->head == NULL);
1724
1725 if (list_empty(i->head))
1726 free_irq(up->port.irq, i);
1727
1728 serial_do_unlink(i, up);
1729 mutex_unlock(&hash_mutex);
1730 }
1731
1732 /*
1733 * This function is used to handle ports that do not have an
1734 * interrupt. This doesn't work very well for 16450's, but gives
1735 * barely passable results for a 16550A. (Although at the expense
1736 * of much CPU overhead).
1737 */
1738 static void serial8250_timeout(unsigned long data)
1739 {
1740 struct uart_8250_port *up = (struct uart_8250_port *)data;
1741
1742 up->port.handle_irq(&up->port);
1743 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1744 }
1745
1746 static void serial8250_backup_timeout(unsigned long data)
1747 {
1748 struct uart_8250_port *up = (struct uart_8250_port *)data;
1749 unsigned int iir, ier = 0, lsr;
1750 unsigned long flags;
1751
1752 spin_lock_irqsave(&up->port.lock, flags);
1753
1754 /*
1755 * Must disable interrupts or else we risk racing with the interrupt
1756 * based handler.
1757 */
1758 if (up->port.irq) {
1759 ier = serial_in(up, UART_IER);
1760 serial_out(up, UART_IER, 0);
1761 }
1762
1763 iir = serial_in(up, UART_IIR);
1764
1765 /*
1766 * This should be a safe test for anyone who doesn't trust the
1767 * IIR bits on their UART, but it's specifically designed for
1768 * the "Diva" UART used on the management processor on many HP
1769 * ia64 and parisc boxes.
1770 */
1771 lsr = serial_in(up, UART_LSR);
1772 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1773 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1774 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1775 (lsr & UART_LSR_THRE)) {
1776 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1777 iir |= UART_IIR_THRI;
1778 }
1779
1780 if (!(iir & UART_IIR_NO_INT))
1781 serial8250_tx_chars(up);
1782
1783 if (up->port.irq)
1784 serial_out(up, UART_IER, ier);
1785
1786 spin_unlock_irqrestore(&up->port.lock, flags);
1787
1788 /* Standard timer interval plus 0.2s to keep the port running */
1789 mod_timer(&up->timer,
1790 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1791 }
1792
1793 static unsigned int serial8250_tx_empty(struct uart_port *port)
1794 {
1795 struct uart_8250_port *up = up_to_u8250p(port);
1796 unsigned long flags;
1797 unsigned int lsr;
1798
1799 spin_lock_irqsave(&port->lock, flags);
1800 lsr = serial_port_in(port, UART_LSR);
1801 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1802 spin_unlock_irqrestore(&port->lock, flags);
1803
1804 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1805 }
1806
1807 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1808 {
1809 struct uart_8250_port *up = up_to_u8250p(port);
1810 unsigned int status;
1811 unsigned int ret;
1812
1813 status = serial8250_modem_status(up);
1814
1815 ret = 0;
1816 if (status & UART_MSR_DCD)
1817 ret |= TIOCM_CAR;
1818 if (status & UART_MSR_RI)
1819 ret |= TIOCM_RNG;
1820 if (status & UART_MSR_DSR)
1821 ret |= TIOCM_DSR;
1822 if (status & UART_MSR_CTS)
1823 ret |= TIOCM_CTS;
1824 return ret;
1825 }
1826
1827 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1828 {
1829 struct uart_8250_port *up = up_to_u8250p(port);
1830 unsigned char mcr = 0;
1831
1832 if (mctrl & TIOCM_RTS)
1833 mcr |= UART_MCR_RTS;
1834 if (mctrl & TIOCM_DTR)
1835 mcr |= UART_MCR_DTR;
1836 if (mctrl & TIOCM_OUT1)
1837 mcr |= UART_MCR_OUT1;
1838 if (mctrl & TIOCM_OUT2)
1839 mcr |= UART_MCR_OUT2;
1840 if (mctrl & TIOCM_LOOP)
1841 mcr |= UART_MCR_LOOP;
1842
1843 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1844
1845 serial_port_out(port, UART_MCR, mcr);
1846 }
1847
1848 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1849 {
1850 struct uart_8250_port *up = up_to_u8250p(port);
1851 unsigned long flags;
1852
1853 spin_lock_irqsave(&port->lock, flags);
1854 if (break_state == -1)
1855 up->lcr |= UART_LCR_SBC;
1856 else
1857 up->lcr &= ~UART_LCR_SBC;
1858 serial_port_out(port, UART_LCR, up->lcr);
1859 spin_unlock_irqrestore(&port->lock, flags);
1860 }
1861
1862 /*
1863 * Wait for transmitter & holding register to empty
1864 */
1865 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1866 {
1867 unsigned int status, tmout = 10000;
1868
1869 /* Wait up to 10ms for the character(s) to be sent. */
1870 for (;;) {
1871 status = serial_in(up, UART_LSR);
1872
1873 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1874
1875 if ((status & bits) == bits)
1876 break;
1877 if (--tmout == 0)
1878 break;
1879 udelay(1);
1880 }
1881
1882 /* Wait up to 1s for flow control if necessary */
1883 if (up->port.flags & UPF_CONS_FLOW) {
1884 unsigned int tmout;
1885 for (tmout = 1000000; tmout; tmout--) {
1886 unsigned int msr = serial_in(up, UART_MSR);
1887 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1888 if (msr & UART_MSR_CTS)
1889 break;
1890 udelay(1);
1891 touch_nmi_watchdog();
1892 }
1893 }
1894 }
1895
1896 #ifdef CONFIG_CONSOLE_POLL
1897 /*
1898 * Console polling routines for writing and reading from the uart while
1899 * in an interrupt or debug context.
1900 */
1901
1902 static int serial8250_get_poll_char(struct uart_port *port)
1903 {
1904 unsigned char lsr = serial_port_in(port, UART_LSR);
1905
1906 if (!(lsr & UART_LSR_DR))
1907 return NO_POLL_CHAR;
1908
1909 return serial_port_in(port, UART_RX);
1910 }
1911
1912
1913 static void serial8250_put_poll_char(struct uart_port *port,
1914 unsigned char c)
1915 {
1916 unsigned int ier;
1917 struct uart_8250_port *up = up_to_u8250p(port);
1918
1919 /*
1920 * First save the IER then disable the interrupts
1921 */
1922 ier = serial_port_in(port, UART_IER);
1923 if (up->capabilities & UART_CAP_UUE)
1924 serial_port_out(port, UART_IER, UART_IER_UUE);
1925 else
1926 serial_port_out(port, UART_IER, 0);
1927
1928 wait_for_xmitr(up, BOTH_EMPTY);
1929 /*
1930 * Send the character out.
1931 */
1932 serial_port_out(port, UART_TX, c);
1933
1934 /*
1935 * Finally, wait for transmitter to become empty
1936 * and restore the IER
1937 */
1938 wait_for_xmitr(up, BOTH_EMPTY);
1939 serial_port_out(port, UART_IER, ier);
1940 }
1941
1942 #endif /* CONFIG_CONSOLE_POLL */
1943
1944 int serial8250_do_startup(struct uart_port *port)
1945 {
1946 struct uart_8250_port *up = up_to_u8250p(port);
1947 unsigned long flags;
1948 unsigned char lsr, iir;
1949 int retval;
1950
1951 if (port->type == PORT_8250_CIR)
1952 return -ENODEV;
1953
1954 if (!port->fifosize)
1955 port->fifosize = uart_config[port->type].fifo_size;
1956 if (!up->tx_loadsz)
1957 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1958 if (!up->capabilities)
1959 up->capabilities = uart_config[port->type].flags;
1960 up->mcr = 0;
1961
1962 if (port->iotype != up->cur_iotype)
1963 set_io_from_upio(port);
1964
1965 if (port->type == PORT_16C950) {
1966 /* Wake up and initialize UART */
1967 up->acr = 0;
1968 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1969 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1970 serial_port_out(port, UART_IER, 0);
1971 serial_port_out(port, UART_LCR, 0);
1972 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1973 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1974 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1975 serial_port_out(port, UART_LCR, 0);
1976 }
1977
1978 #ifdef CONFIG_SERIAL_8250_RSA
1979 /*
1980 * If this is an RSA port, see if we can kick it up to the
1981 * higher speed clock.
1982 */
1983 enable_rsa(up);
1984 #endif
1985
1986 /*
1987 * Clear the FIFO buffers and disable them.
1988 * (they will be reenabled in set_termios())
1989 */
1990 serial8250_clear_fifos(up);
1991
1992 /*
1993 * Clear the interrupt registers.
1994 */
1995 serial_port_in(port, UART_LSR);
1996 serial_port_in(port, UART_RX);
1997 serial_port_in(port, UART_IIR);
1998 serial_port_in(port, UART_MSR);
1999
2000 /*
2001 * At this point, there's no way the LSR could still be 0xff;
2002 * if it is, then bail out, because there's likely no UART
2003 * here.
2004 */
2005 if (!(port->flags & UPF_BUGGY_UART) &&
2006 (serial_port_in(port, UART_LSR) == 0xff)) {
2007 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2008 serial_index(port));
2009 return -ENODEV;
2010 }
2011
2012 /*
2013 * For a XR16C850, we need to set the trigger levels
2014 */
2015 if (port->type == PORT_16850) {
2016 unsigned char fctr;
2017
2018 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2019
2020 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2021 serial_port_out(port, UART_FCTR,
2022 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2023 serial_port_out(port, UART_TRG, UART_TRG_96);
2024 serial_port_out(port, UART_FCTR,
2025 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2026 serial_port_out(port, UART_TRG, UART_TRG_96);
2027
2028 serial_port_out(port, UART_LCR, 0);
2029 }
2030
2031 if (port->irq) {
2032 unsigned char iir1;
2033 /*
2034 * Test for UARTs that do not reassert THRE when the
2035 * transmitter is idle and the interrupt has already
2036 * been cleared. Real 16550s should always reassert
2037 * this interrupt whenever the transmitter is idle and
2038 * the interrupt is enabled. Delays are necessary to
2039 * allow register changes to become visible.
2040 */
2041 spin_lock_irqsave(&port->lock, flags);
2042 if (up->port.irqflags & IRQF_SHARED)
2043 disable_irq_nosync(port->irq);
2044
2045 wait_for_xmitr(up, UART_LSR_THRE);
2046 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2047 udelay(1); /* allow THRE to set */
2048 iir1 = serial_port_in(port, UART_IIR);
2049 serial_port_out(port, UART_IER, 0);
2050 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2051 udelay(1); /* allow a working UART time to re-assert THRE */
2052 iir = serial_port_in(port, UART_IIR);
2053 serial_port_out(port, UART_IER, 0);
2054
2055 if (port->irqflags & IRQF_SHARED)
2056 enable_irq(port->irq);
2057 spin_unlock_irqrestore(&port->lock, flags);
2058
2059 /*
2060 * If the interrupt is not reasserted, or we otherwise
2061 * don't trust the iir, setup a timer to kick the UART
2062 * on a regular basis.
2063 */
2064 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2065 up->port.flags & UPF_BUG_THRE) {
2066 up->bugs |= UART_BUG_THRE;
2067 pr_debug("ttyS%d - using backup timer\n",
2068 serial_index(port));
2069 }
2070 }
2071
2072 /*
2073 * The above check will only give an accurate result the first time
2074 * the port is opened so this value needs to be preserved.
2075 */
2076 if (up->bugs & UART_BUG_THRE) {
2077 up->timer.function = serial8250_backup_timeout;
2078 up->timer.data = (unsigned long)up;
2079 mod_timer(&up->timer, jiffies +
2080 uart_poll_timeout(port) + HZ / 5);
2081 }
2082
2083 /*
2084 * If the "interrupt" for this port doesn't correspond with any
2085 * hardware interrupt, we use a timer-based system. The original
2086 * driver used to do this with IRQ0.
2087 */
2088 if (!port->irq) {
2089 up->timer.data = (unsigned long)up;
2090 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2091 } else {
2092 retval = serial_link_irq_chain(up);
2093 if (retval)
2094 return retval;
2095 }
2096
2097 /*
2098 * Now, initialize the UART
2099 */
2100 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2101
2102 spin_lock_irqsave(&port->lock, flags);
2103 if (up->port.flags & UPF_FOURPORT) {
2104 if (!up->port.irq)
2105 up->port.mctrl |= TIOCM_OUT1;
2106 } else
2107 /*
2108 * Most PC uarts need OUT2 raised to enable interrupts.
2109 */
2110 if (port->irq)
2111 up->port.mctrl |= TIOCM_OUT2;
2112
2113 serial8250_set_mctrl(port, port->mctrl);
2114
2115 /* Serial over Lan (SoL) hack:
2116 Intel 8257x Gigabit ethernet chips have a
2117 16550 emulation, to be used for Serial Over Lan.
2118 Those chips take a longer time than a normal
2119 serial device to signalize that a transmission
2120 data was queued. Due to that, the above test generally
2121 fails. One solution would be to delay the reading of
2122 iir. However, this is not reliable, since the timeout
2123 is variable. So, let's just don't test if we receive
2124 TX irq. This way, we'll never enable UART_BUG_TXEN.
2125 */
2126 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2127 goto dont_test_tx_en;
2128
2129 /*
2130 * Do a quick test to see if we receive an
2131 * interrupt when we enable the TX irq.
2132 */
2133 serial_port_out(port, UART_IER, UART_IER_THRI);
2134 lsr = serial_port_in(port, UART_LSR);
2135 iir = serial_port_in(port, UART_IIR);
2136 serial_port_out(port, UART_IER, 0);
2137
2138 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2139 if (!(up->bugs & UART_BUG_TXEN)) {
2140 up->bugs |= UART_BUG_TXEN;
2141 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2142 serial_index(port));
2143 }
2144 } else {
2145 up->bugs &= ~UART_BUG_TXEN;
2146 }
2147
2148 dont_test_tx_en:
2149 spin_unlock_irqrestore(&port->lock, flags);
2150
2151 /*
2152 * Clear the interrupt registers again for luck, and clear the
2153 * saved flags to avoid getting false values from polling
2154 * routines or the previous session.
2155 */
2156 serial_port_in(port, UART_LSR);
2157 serial_port_in(port, UART_RX);
2158 serial_port_in(port, UART_IIR);
2159 serial_port_in(port, UART_MSR);
2160 up->lsr_saved_flags = 0;
2161 up->msr_saved_flags = 0;
2162
2163 /*
2164 * Request DMA channels for both RX and TX.
2165 */
2166 if (up->dma) {
2167 retval = serial8250_request_dma(up);
2168 if (retval) {
2169 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2170 serial_index(port));
2171 up->dma = NULL;
2172 }
2173 }
2174
2175 /*
2176 * Finally, enable interrupts. Note: Modem status interrupts
2177 * are set via set_termios(), which will be occurring imminently
2178 * anyway, so we don't enable them here.
2179 */
2180 up->ier = UART_IER_RLSI | UART_IER_RDI;
2181 serial_port_out(port, UART_IER, up->ier);
2182
2183 if (port->flags & UPF_FOURPORT) {
2184 unsigned int icp;
2185 /*
2186 * Enable interrupts on the AST Fourport board
2187 */
2188 icp = (port->iobase & 0xfe0) | 0x01f;
2189 outb_p(0x80, icp);
2190 inb_p(icp);
2191 }
2192
2193 return 0;
2194 }
2195 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2196
2197 static int serial8250_startup(struct uart_port *port)
2198 {
2199 if (port->startup)
2200 return port->startup(port);
2201 return serial8250_do_startup(port);
2202 }
2203
2204 void serial8250_do_shutdown(struct uart_port *port)
2205 {
2206 struct uart_8250_port *up = up_to_u8250p(port);
2207 unsigned long flags;
2208
2209 /*
2210 * Disable interrupts from this port
2211 */
2212 up->ier = 0;
2213 serial_port_out(port, UART_IER, 0);
2214
2215 if (up->dma)
2216 serial8250_release_dma(up);
2217
2218 spin_lock_irqsave(&port->lock, flags);
2219 if (port->flags & UPF_FOURPORT) {
2220 /* reset interrupts on the AST Fourport board */
2221 inb((port->iobase & 0xfe0) | 0x1f);
2222 port->mctrl |= TIOCM_OUT1;
2223 } else
2224 port->mctrl &= ~TIOCM_OUT2;
2225
2226 serial8250_set_mctrl(port, port->mctrl);
2227 spin_unlock_irqrestore(&port->lock, flags);
2228
2229 /*
2230 * Disable break condition and FIFOs
2231 */
2232 serial_port_out(port, UART_LCR,
2233 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2234 serial8250_clear_fifos(up);
2235
2236 #ifdef CONFIG_SERIAL_8250_RSA
2237 /*
2238 * Reset the RSA board back to 115kbps compat mode.
2239 */
2240 disable_rsa(up);
2241 #endif
2242
2243 /*
2244 * Read data port to reset things, and then unlink from
2245 * the IRQ chain.
2246 */
2247 serial_port_in(port, UART_RX);
2248
2249 del_timer_sync(&up->timer);
2250 up->timer.function = serial8250_timeout;
2251 if (port->irq)
2252 serial_unlink_irq_chain(up);
2253 }
2254 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2255
2256 static void serial8250_shutdown(struct uart_port *port)
2257 {
2258 if (port->shutdown)
2259 port->shutdown(port);
2260 else
2261 serial8250_do_shutdown(port);
2262 }
2263
2264 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2265 {
2266 unsigned int quot;
2267
2268 /*
2269 * Handle magic divisors for baud rates above baud_base on
2270 * SMSC SuperIO chips.
2271 */
2272 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2273 baud == (port->uartclk/4))
2274 quot = 0x8001;
2275 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2276 baud == (port->uartclk/8))
2277 quot = 0x8002;
2278 else
2279 quot = uart_get_divisor(port, baud);
2280
2281 return quot;
2282 }
2283
2284 void
2285 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2286 struct ktermios *old)
2287 {
2288 struct uart_8250_port *up = up_to_u8250p(port);
2289 unsigned char cval;
2290 unsigned long flags;
2291 unsigned int baud, quot;
2292
2293 switch (termios->c_cflag & CSIZE) {
2294 case CS5:
2295 cval = UART_LCR_WLEN5;
2296 break;
2297 case CS6:
2298 cval = UART_LCR_WLEN6;
2299 break;
2300 case CS7:
2301 cval = UART_LCR_WLEN7;
2302 break;
2303 default:
2304 case CS8:
2305 cval = UART_LCR_WLEN8;
2306 break;
2307 }
2308
2309 if (termios->c_cflag & CSTOPB)
2310 cval |= UART_LCR_STOP;
2311 if (termios->c_cflag & PARENB) {
2312 cval |= UART_LCR_PARITY;
2313 if (up->bugs & UART_BUG_PARITY)
2314 up->fifo_bug = true;
2315 }
2316 if (!(termios->c_cflag & PARODD))
2317 cval |= UART_LCR_EPAR;
2318 #ifdef CMSPAR
2319 if (termios->c_cflag & CMSPAR)
2320 cval |= UART_LCR_SPAR;
2321 #endif
2322
2323 /*
2324 * Ask the core to calculate the divisor for us.
2325 */
2326 baud = uart_get_baud_rate(port, termios, old,
2327 port->uartclk / 16 / 0xffff,
2328 port->uartclk / 16);
2329 quot = serial8250_get_divisor(port, baud);
2330
2331 /*
2332 * Oxford Semi 952 rev B workaround
2333 */
2334 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2335 quot++;
2336
2337 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2338 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2339 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2340 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2341 up->fcr |= UART_FCR_TRIGGER_1;
2342 }
2343 }
2344
2345 /*
2346 * MCR-based auto flow control. When AFE is enabled, RTS will be
2347 * deasserted when the receive FIFO contains more characters than
2348 * the trigger, or the MCR RTS bit is cleared. In the case where
2349 * the remote UART is not using CTS auto flow control, we must
2350 * have sufficient FIFO entries for the latency of the remote
2351 * UART to respond. IOW, at least 32 bytes of FIFO.
2352 */
2353 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2354 up->mcr &= ~UART_MCR_AFE;
2355 if (termios->c_cflag & CRTSCTS)
2356 up->mcr |= UART_MCR_AFE;
2357 }
2358
2359 /*
2360 * Ok, we're now changing the port state. Do it with
2361 * interrupts disabled.
2362 */
2363 spin_lock_irqsave(&port->lock, flags);
2364
2365 /*
2366 * Update the per-port timeout.
2367 */
2368 uart_update_timeout(port, termios->c_cflag, baud);
2369
2370 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2371 if (termios->c_iflag & INPCK)
2372 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2373 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2374 port->read_status_mask |= UART_LSR_BI;
2375
2376 /*
2377 * Characteres to ignore
2378 */
2379 port->ignore_status_mask = 0;
2380 if (termios->c_iflag & IGNPAR)
2381 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2382 if (termios->c_iflag & IGNBRK) {
2383 port->ignore_status_mask |= UART_LSR_BI;
2384 /*
2385 * If we're ignoring parity and break indicators,
2386 * ignore overruns too (for real raw support).
2387 */
2388 if (termios->c_iflag & IGNPAR)
2389 port->ignore_status_mask |= UART_LSR_OE;
2390 }
2391
2392 /*
2393 * ignore all characters if CREAD is not set
2394 */
2395 if ((termios->c_cflag & CREAD) == 0)
2396 port->ignore_status_mask |= UART_LSR_DR;
2397
2398 /*
2399 * CTS flow control flag and modem status interrupts
2400 */
2401 up->ier &= ~UART_IER_MSI;
2402 if (!(up->bugs & UART_BUG_NOMSR) &&
2403 UART_ENABLE_MS(&up->port, termios->c_cflag))
2404 up->ier |= UART_IER_MSI;
2405 if (up->capabilities & UART_CAP_UUE)
2406 up->ier |= UART_IER_UUE;
2407 if (up->capabilities & UART_CAP_RTOIE)
2408 up->ier |= UART_IER_RTOIE;
2409
2410 serial_port_out(port, UART_IER, up->ier);
2411
2412 if (up->capabilities & UART_CAP_EFR) {
2413 unsigned char efr = 0;
2414 /*
2415 * TI16C752/Startech hardware flow control. FIXME:
2416 * - TI16C752 requires control thresholds to be set.
2417 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2418 */
2419 if (termios->c_cflag & CRTSCTS)
2420 efr |= UART_EFR_CTS;
2421
2422 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2423 if (port->flags & UPF_EXAR_EFR)
2424 serial_port_out(port, UART_XR_EFR, efr);
2425 else
2426 serial_port_out(port, UART_EFR, efr);
2427 }
2428
2429 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2430 if (is_omap1510_8250(up)) {
2431 if (baud == 115200) {
2432 quot = 1;
2433 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2434 } else
2435 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2436 }
2437
2438 /*
2439 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2440 * otherwise just set DLAB
2441 */
2442 if (up->capabilities & UART_NATSEMI)
2443 serial_port_out(port, UART_LCR, 0xe0);
2444 else
2445 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
2446
2447 serial_dl_write(up, quot);
2448
2449 /*
2450 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2451 *
2452 * We need to recalculate all of the registers, because DLM and DLL
2453 * are already rounded to a whole integer.
2454 *
2455 * When recalculating we use a 32x clock instead of a 16x clock to
2456 * allow 1-bit for rounding in the fractional part.
2457 */
2458 if (up->port.type == PORT_XR17V35X) {
2459 unsigned int baud_x32 = (port->uartclk * 2) / baud;
2460 u16 quot = baud_x32 / 32;
2461 u8 quot_frac = DIV_ROUND_CLOSEST(baud_x32 % 32, 2);
2462
2463 serial_dl_write(up, quot);
2464 serial_port_out(port, 0x2, quot_frac & 0xf);
2465 }
2466
2467 /*
2468 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2469 * is written without DLAB set, this mode will be disabled.
2470 */
2471 if (port->type == PORT_16750)
2472 serial_port_out(port, UART_FCR, up->fcr);
2473
2474 serial_port_out(port, UART_LCR, cval); /* reset DLAB */
2475 up->lcr = cval; /* Save LCR */
2476 if (port->type != PORT_16750) {
2477 /* emulated UARTs (Lucent Venus 167x) need two steps */
2478 if (up->fcr & UART_FCR_ENABLE_FIFO)
2479 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2480 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2481 }
2482 serial8250_set_mctrl(port, port->mctrl);
2483 spin_unlock_irqrestore(&port->lock, flags);
2484 /* Don't rewrite B0 */
2485 if (tty_termios_baud_rate(termios))
2486 tty_termios_encode_baud_rate(termios, baud, baud);
2487 }
2488 EXPORT_SYMBOL(serial8250_do_set_termios);
2489
2490 static void
2491 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2492 struct ktermios *old)
2493 {
2494 if (port->set_termios)
2495 port->set_termios(port, termios, old);
2496 else
2497 serial8250_do_set_termios(port, termios, old);
2498 }
2499
2500 static void
2501 serial8250_set_ldisc(struct uart_port *port, int new)
2502 {
2503 if (new == N_PPS) {
2504 port->flags |= UPF_HARDPPS_CD;
2505 serial8250_enable_ms(port);
2506 } else
2507 port->flags &= ~UPF_HARDPPS_CD;
2508 }
2509
2510
2511 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2512 unsigned int oldstate)
2513 {
2514 struct uart_8250_port *p = up_to_u8250p(port);
2515
2516 serial8250_set_sleep(p, state != 0);
2517 }
2518 EXPORT_SYMBOL(serial8250_do_pm);
2519
2520 static void
2521 serial8250_pm(struct uart_port *port, unsigned int state,
2522 unsigned int oldstate)
2523 {
2524 if (port->pm)
2525 port->pm(port, state, oldstate);
2526 else
2527 serial8250_do_pm(port, state, oldstate);
2528 }
2529
2530 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2531 {
2532 if (pt->port.iotype == UPIO_AU)
2533 return 0x1000;
2534 if (is_omap1_8250(pt))
2535 return 0x16 << pt->port.regshift;
2536
2537 return 8 << pt->port.regshift;
2538 }
2539
2540 /*
2541 * Resource handling.
2542 */
2543 static int serial8250_request_std_resource(struct uart_8250_port *up)
2544 {
2545 unsigned int size = serial8250_port_size(up);
2546 struct uart_port *port = &up->port;
2547 int ret = 0;
2548
2549 switch (port->iotype) {
2550 case UPIO_AU:
2551 case UPIO_TSI:
2552 case UPIO_MEM32:
2553 case UPIO_MEM:
2554 if (!port->mapbase)
2555 break;
2556
2557 if (!request_mem_region(port->mapbase, size, "serial")) {
2558 ret = -EBUSY;
2559 break;
2560 }
2561
2562 if (port->flags & UPF_IOREMAP) {
2563 port->membase = ioremap_nocache(port->mapbase, size);
2564 if (!port->membase) {
2565 release_mem_region(port->mapbase, size);
2566 ret = -ENOMEM;
2567 }
2568 }
2569 break;
2570
2571 case UPIO_HUB6:
2572 case UPIO_PORT:
2573 if (!request_region(port->iobase, size, "serial"))
2574 ret = -EBUSY;
2575 break;
2576 }
2577 return ret;
2578 }
2579
2580 static void serial8250_release_std_resource(struct uart_8250_port *up)
2581 {
2582 unsigned int size = serial8250_port_size(up);
2583 struct uart_port *port = &up->port;
2584
2585 switch (port->iotype) {
2586 case UPIO_AU:
2587 case UPIO_TSI:
2588 case UPIO_MEM32:
2589 case UPIO_MEM:
2590 if (!port->mapbase)
2591 break;
2592
2593 if (port->flags & UPF_IOREMAP) {
2594 iounmap(port->membase);
2595 port->membase = NULL;
2596 }
2597
2598 release_mem_region(port->mapbase, size);
2599 break;
2600
2601 case UPIO_HUB6:
2602 case UPIO_PORT:
2603 release_region(port->iobase, size);
2604 break;
2605 }
2606 }
2607
2608 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2609 {
2610 unsigned long start = UART_RSA_BASE << up->port.regshift;
2611 unsigned int size = 8 << up->port.regshift;
2612 struct uart_port *port = &up->port;
2613 int ret = -EINVAL;
2614
2615 switch (port->iotype) {
2616 case UPIO_HUB6:
2617 case UPIO_PORT:
2618 start += port->iobase;
2619 if (request_region(start, size, "serial-rsa"))
2620 ret = 0;
2621 else
2622 ret = -EBUSY;
2623 break;
2624 }
2625
2626 return ret;
2627 }
2628
2629 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2630 {
2631 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2632 unsigned int size = 8 << up->port.regshift;
2633 struct uart_port *port = &up->port;
2634
2635 switch (port->iotype) {
2636 case UPIO_HUB6:
2637 case UPIO_PORT:
2638 release_region(port->iobase + offset, size);
2639 break;
2640 }
2641 }
2642
2643 static void serial8250_release_port(struct uart_port *port)
2644 {
2645 struct uart_8250_port *up = up_to_u8250p(port);
2646
2647 serial8250_release_std_resource(up);
2648 if (port->type == PORT_RSA)
2649 serial8250_release_rsa_resource(up);
2650 }
2651
2652 static int serial8250_request_port(struct uart_port *port)
2653 {
2654 struct uart_8250_port *up = up_to_u8250p(port);
2655 int ret;
2656
2657 if (port->type == PORT_8250_CIR)
2658 return -ENODEV;
2659
2660 ret = serial8250_request_std_resource(up);
2661 if (ret == 0 && port->type == PORT_RSA) {
2662 ret = serial8250_request_rsa_resource(up);
2663 if (ret < 0)
2664 serial8250_release_std_resource(up);
2665 }
2666
2667 return ret;
2668 }
2669
2670 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2671 {
2672 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2673 unsigned char bytes;
2674
2675 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2676
2677 return bytes ? bytes : -EOPNOTSUPP;
2678 }
2679
2680 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2681 {
2682 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2683 int i;
2684
2685 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2686 return -EOPNOTSUPP;
2687
2688 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2689 if (bytes < conf_type->rxtrig_bytes[i])
2690 /* Use the nearest lower value */
2691 return (--i) << UART_FCR_R_TRIG_SHIFT;
2692 }
2693
2694 return UART_FCR_R_TRIG_11;
2695 }
2696
2697 static int do_get_rxtrig(struct tty_port *port)
2698 {
2699 struct uart_state *state = container_of(port, struct uart_state, port);
2700 struct uart_port *uport = state->uart_port;
2701 struct uart_8250_port *up =
2702 container_of(uport, struct uart_8250_port, port);
2703
2704 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2705 return -EINVAL;
2706
2707 return fcr_get_rxtrig_bytes(up);
2708 }
2709
2710 static int do_serial8250_get_rxtrig(struct tty_port *port)
2711 {
2712 int rxtrig_bytes;
2713
2714 mutex_lock(&port->mutex);
2715 rxtrig_bytes = do_get_rxtrig(port);
2716 mutex_unlock(&port->mutex);
2717
2718 return rxtrig_bytes;
2719 }
2720
2721 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2722 struct device_attribute *attr, char *buf)
2723 {
2724 struct tty_port *port = dev_get_drvdata(dev);
2725 int rxtrig_bytes;
2726
2727 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2728 if (rxtrig_bytes < 0)
2729 return rxtrig_bytes;
2730
2731 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2732 }
2733
2734 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2735 {
2736 struct uart_state *state = container_of(port, struct uart_state, port);
2737 struct uart_port *uport = state->uart_port;
2738 struct uart_8250_port *up =
2739 container_of(uport, struct uart_8250_port, port);
2740 int rxtrig;
2741
2742 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2743 up->fifo_bug)
2744 return -EINVAL;
2745
2746 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2747 if (rxtrig < 0)
2748 return rxtrig;
2749
2750 serial8250_clear_fifos(up);
2751 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2752 up->fcr |= (unsigned char)rxtrig;
2753 serial_out(up, UART_FCR, up->fcr);
2754 return 0;
2755 }
2756
2757 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2758 {
2759 int ret;
2760
2761 mutex_lock(&port->mutex);
2762 ret = do_set_rxtrig(port, bytes);
2763 mutex_unlock(&port->mutex);
2764
2765 return ret;
2766 }
2767
2768 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2769 struct device_attribute *attr, const char *buf, size_t count)
2770 {
2771 struct tty_port *port = dev_get_drvdata(dev);
2772 unsigned char bytes;
2773 int ret;
2774
2775 if (!count)
2776 return -EINVAL;
2777
2778 ret = kstrtou8(buf, 10, &bytes);
2779 if (ret < 0)
2780 return ret;
2781
2782 ret = do_serial8250_set_rxtrig(port, bytes);
2783 if (ret < 0)
2784 return ret;
2785
2786 return count;
2787 }
2788
2789 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2790 serial8250_get_attr_rx_trig_bytes,
2791 serial8250_set_attr_rx_trig_bytes);
2792
2793 static struct attribute *serial8250_dev_attrs[] = {
2794 &dev_attr_rx_trig_bytes.attr,
2795 NULL,
2796 };
2797
2798 static struct attribute_group serial8250_dev_attr_group = {
2799 .attrs = serial8250_dev_attrs,
2800 };
2801
2802 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2803 {
2804 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2805
2806 if (conf_type->rxtrig_bytes[0])
2807 up->port.attr_group = &serial8250_dev_attr_group;
2808 }
2809
2810 static void serial8250_config_port(struct uart_port *port, int flags)
2811 {
2812 struct uart_8250_port *up = up_to_u8250p(port);
2813 int probeflags = PROBE_ANY;
2814 int ret;
2815
2816 if (port->type == PORT_8250_CIR)
2817 return;
2818
2819 /*
2820 * Find the region that we can probe for. This in turn
2821 * tells us whether we can probe for the type of port.
2822 */
2823 ret = serial8250_request_std_resource(up);
2824 if (ret < 0)
2825 return;
2826
2827 ret = serial8250_request_rsa_resource(up);
2828 if (ret < 0)
2829 probeflags &= ~PROBE_RSA;
2830
2831 if (port->iotype != up->cur_iotype)
2832 set_io_from_upio(port);
2833
2834 if (flags & UART_CONFIG_TYPE)
2835 autoconfig(up, probeflags);
2836
2837 /* if access method is AU, it is a 16550 with a quirk */
2838 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2839 up->bugs |= UART_BUG_NOMSR;
2840
2841 /* HW bugs may trigger IRQ while IIR == NO_INT */
2842 if (port->type == PORT_TEGRA)
2843 up->bugs |= UART_BUG_NOMSR;
2844
2845 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2846 autoconfig_irq(up);
2847
2848 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
2849 serial8250_release_rsa_resource(up);
2850 if (port->type == PORT_UNKNOWN)
2851 serial8250_release_std_resource(up);
2852
2853 /* Fixme: probably not the best place for this */
2854 if ((port->type == PORT_XR17V35X) ||
2855 (port->type == PORT_XR17D15X))
2856 port->handle_irq = exar_handle_irq;
2857
2858 register_dev_spec_attr_grp(up);
2859 up->fcr = uart_config[up->port.type].fcr;
2860 }
2861
2862 static int
2863 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2864 {
2865 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2866 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2867 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2868 ser->type == PORT_STARTECH)
2869 return -EINVAL;
2870 return 0;
2871 }
2872
2873 static int serial8250_ioctl(struct uart_port *port, unsigned int cmd,
2874 unsigned long arg)
2875 {
2876 struct uart_8250_port *up =
2877 container_of(port, struct uart_8250_port, port);
2878 int ret;
2879 struct serial_rs485 rs485_config;
2880
2881 if (!up->rs485_config)
2882 return -ENOIOCTLCMD;
2883
2884 switch (cmd) {
2885 case TIOCSRS485:
2886 if (copy_from_user(&rs485_config, (void __user *)arg,
2887 sizeof(rs485_config)))
2888 return -EFAULT;
2889
2890 ret = up->rs485_config(up, &rs485_config);
2891 if (ret)
2892 return ret;
2893
2894 memcpy(&up->rs485, &rs485_config, sizeof(rs485_config));
2895
2896 return 0;
2897 case TIOCGRS485:
2898 if (copy_to_user((void __user *)arg, &up->rs485,
2899 sizeof(up->rs485)))
2900 return -EFAULT;
2901 return 0;
2902 default:
2903 break;
2904 }
2905
2906 return -ENOIOCTLCMD;
2907 }
2908
2909 static const char *
2910 serial8250_type(struct uart_port *port)
2911 {
2912 int type = port->type;
2913
2914 if (type >= ARRAY_SIZE(uart_config))
2915 type = 0;
2916 return uart_config[type].name;
2917 }
2918
2919 static struct uart_ops serial8250_pops = {
2920 .tx_empty = serial8250_tx_empty,
2921 .set_mctrl = serial8250_set_mctrl,
2922 .get_mctrl = serial8250_get_mctrl,
2923 .stop_tx = serial8250_stop_tx,
2924 .start_tx = serial8250_start_tx,
2925 .throttle = serial8250_throttle,
2926 .unthrottle = serial8250_unthrottle,
2927 .stop_rx = serial8250_stop_rx,
2928 .enable_ms = serial8250_enable_ms,
2929 .break_ctl = serial8250_break_ctl,
2930 .startup = serial8250_startup,
2931 .shutdown = serial8250_shutdown,
2932 .set_termios = serial8250_set_termios,
2933 .set_ldisc = serial8250_set_ldisc,
2934 .pm = serial8250_pm,
2935 .type = serial8250_type,
2936 .release_port = serial8250_release_port,
2937 .request_port = serial8250_request_port,
2938 .config_port = serial8250_config_port,
2939 .verify_port = serial8250_verify_port,
2940 .ioctl = serial8250_ioctl,
2941 #ifdef CONFIG_CONSOLE_POLL
2942 .poll_get_char = serial8250_get_poll_char,
2943 .poll_put_char = serial8250_put_poll_char,
2944 #endif
2945 };
2946
2947 static struct uart_8250_port serial8250_ports[UART_NR];
2948
2949 /**
2950 * serial8250_get_port - retrieve struct uart_8250_port
2951 * @line: serial line number
2952 *
2953 * This function retrieves struct uart_8250_port for the specific line.
2954 * This struct *must* *not* be used to perform a 8250 or serial core operation
2955 * which is not accessible otherwise. Its only purpose is to make the struct
2956 * accessible to the runtime-pm callbacks for context suspend/restore.
2957 * The lock assumption made here is none because runtime-pm suspend/resume
2958 * callbacks should not be invoked if there is any operation performed on the
2959 * port.
2960 */
2961 struct uart_8250_port *serial8250_get_port(int line)
2962 {
2963 return &serial8250_ports[line];
2964 }
2965 EXPORT_SYMBOL_GPL(serial8250_get_port);
2966
2967 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2968 unsigned short *capabilities);
2969
2970 void serial8250_set_isa_configurator(
2971 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2972 {
2973 serial8250_isa_config = v;
2974 }
2975 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2976
2977 static void __init serial8250_isa_init_ports(void)
2978 {
2979 struct uart_8250_port *up;
2980 static int first = 1;
2981 int i, irqflag = 0;
2982
2983 if (!first)
2984 return;
2985 first = 0;
2986
2987 if (nr_uarts > UART_NR)
2988 nr_uarts = UART_NR;
2989
2990 for (i = 0; i < nr_uarts; i++) {
2991 struct uart_8250_port *up = &serial8250_ports[i];
2992 struct uart_port *port = &up->port;
2993
2994 port->line = i;
2995 spin_lock_init(&port->lock);
2996
2997 init_timer(&up->timer);
2998 up->timer.function = serial8250_timeout;
2999 up->cur_iotype = 0xFF;
3000
3001 /*
3002 * ALPHA_KLUDGE_MCR needs to be killed.
3003 */
3004 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
3005 up->mcr_force = ALPHA_KLUDGE_MCR;
3006
3007 port->ops = &serial8250_pops;
3008 }
3009
3010 if (share_irqs)
3011 irqflag = IRQF_SHARED;
3012
3013 for (i = 0, up = serial8250_ports;
3014 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
3015 i++, up++) {
3016 struct uart_port *port = &up->port;
3017
3018 port->iobase = old_serial_port[i].port;
3019 port->irq = irq_canonicalize(old_serial_port[i].irq);
3020 port->irqflags = old_serial_port[i].irqflags;
3021 port->uartclk = old_serial_port[i].baud_base * 16;
3022 port->flags = old_serial_port[i].flags;
3023 port->hub6 = old_serial_port[i].hub6;
3024 port->membase = old_serial_port[i].iomem_base;
3025 port->iotype = old_serial_port[i].io_type;
3026 port->regshift = old_serial_port[i].iomem_reg_shift;
3027 set_io_from_upio(port);
3028 port->irqflags |= irqflag;
3029 if (serial8250_isa_config != NULL)
3030 serial8250_isa_config(i, &up->port, &up->capabilities);
3031
3032 }
3033 }
3034
3035 static void
3036 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
3037 {
3038 up->port.type = type;
3039 if (!up->port.fifosize)
3040 up->port.fifosize = uart_config[type].fifo_size;
3041 if (!up->tx_loadsz)
3042 up->tx_loadsz = uart_config[type].tx_loadsz;
3043 if (!up->capabilities)
3044 up->capabilities = uart_config[type].flags;
3045 }
3046
3047 static void __init
3048 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
3049 {
3050 int i;
3051
3052 for (i = 0; i < nr_uarts; i++) {
3053 struct uart_8250_port *up = &serial8250_ports[i];
3054
3055 if (up->port.dev)
3056 continue;
3057
3058 up->port.dev = dev;
3059
3060 if (up->port.flags & UPF_FIXED_TYPE)
3061 serial8250_init_fixed_type_port(up, up->port.type);
3062
3063 uart_add_one_port(drv, &up->port);
3064 }
3065 }
3066
3067 #ifdef CONFIG_SERIAL_8250_CONSOLE
3068
3069 static void serial8250_console_putchar(struct uart_port *port, int ch)
3070 {
3071 struct uart_8250_port *up = up_to_u8250p(port);
3072
3073 wait_for_xmitr(up, UART_LSR_THRE);
3074 serial_port_out(port, UART_TX, ch);
3075 }
3076
3077 /*
3078 * Print a string to the serial port trying not to disturb
3079 * any possible real use of the port...
3080 *
3081 * The console_lock must be held when we get here.
3082 */
3083 static void
3084 serial8250_console_write(struct console *co, const char *s, unsigned int count)
3085 {
3086 struct uart_8250_port *up = &serial8250_ports[co->index];
3087 struct uart_port *port = &up->port;
3088 unsigned long flags;
3089 unsigned int ier;
3090 int locked = 1;
3091
3092 touch_nmi_watchdog();
3093
3094 if (port->sysrq || oops_in_progress)
3095 locked = spin_trylock_irqsave(&port->lock, flags);
3096 else
3097 spin_lock_irqsave(&port->lock, flags);
3098
3099 /*
3100 * First save the IER then disable the interrupts
3101 */
3102 ier = serial_port_in(port, UART_IER);
3103
3104 if (up->capabilities & UART_CAP_UUE)
3105 serial_port_out(port, UART_IER, UART_IER_UUE);
3106 else
3107 serial_port_out(port, UART_IER, 0);
3108
3109 uart_console_write(port, s, count, serial8250_console_putchar);
3110
3111 /*
3112 * Finally, wait for transmitter to become empty
3113 * and restore the IER
3114 */
3115 wait_for_xmitr(up, BOTH_EMPTY);
3116 serial_port_out(port, UART_IER, ier);
3117
3118 /*
3119 * The receive handling will happen properly because the
3120 * receive ready bit will still be set; it is not cleared
3121 * on read. However, modem control will not, we must
3122 * call it if we have saved something in the saved flags
3123 * while processing with interrupts off.
3124 */
3125 if (up->msr_saved_flags)
3126 serial8250_modem_status(up);
3127
3128 if (locked)
3129 spin_unlock_irqrestore(&port->lock, flags);
3130 }
3131
3132 static int __init serial8250_console_setup(struct console *co, char *options)
3133 {
3134 struct uart_port *port;
3135 int baud = 9600;
3136 int bits = 8;
3137 int parity = 'n';
3138 int flow = 'n';
3139
3140 /*
3141 * Check whether an invalid uart number has been specified, and
3142 * if so, search for the first available port that does have
3143 * console support.
3144 */
3145 if (co->index >= nr_uarts)
3146 co->index = 0;
3147 port = &serial8250_ports[co->index].port;
3148 if (!port->iobase && !port->membase)
3149 return -ENODEV;
3150
3151 if (options)
3152 uart_parse_options(options, &baud, &parity, &bits, &flow);
3153
3154 return uart_set_options(port, co, baud, parity, bits, flow);
3155 }
3156
3157 static int serial8250_console_early_setup(void)
3158 {
3159 return serial8250_find_port_for_earlycon();
3160 }
3161
3162 static struct console serial8250_console = {
3163 .name = "ttyS",
3164 .write = serial8250_console_write,
3165 .device = uart_console_device,
3166 .setup = serial8250_console_setup,
3167 .early_setup = serial8250_console_early_setup,
3168 .flags = CON_PRINTBUFFER | CON_ANYTIME,
3169 .index = -1,
3170 .data = &serial8250_reg,
3171 };
3172
3173 static int __init serial8250_console_init(void)
3174 {
3175 serial8250_isa_init_ports();
3176 register_console(&serial8250_console);
3177 return 0;
3178 }
3179 console_initcall(serial8250_console_init);
3180
3181 int serial8250_find_port(struct uart_port *p)
3182 {
3183 int line;
3184 struct uart_port *port;
3185
3186 for (line = 0; line < nr_uarts; line++) {
3187 port = &serial8250_ports[line].port;
3188 if (uart_match_port(p, port))
3189 return line;
3190 }
3191 return -ENODEV;
3192 }
3193
3194 #define SERIAL8250_CONSOLE &serial8250_console
3195 #else
3196 #define SERIAL8250_CONSOLE NULL
3197 #endif
3198
3199 static struct uart_driver serial8250_reg = {
3200 .owner = THIS_MODULE,
3201 .driver_name = "serial",
3202 .dev_name = "ttyS",
3203 .major = TTY_MAJOR,
3204 .minor = 64,
3205 .cons = SERIAL8250_CONSOLE,
3206 };
3207
3208 /*
3209 * early_serial_setup - early registration for 8250 ports
3210 *
3211 * Setup an 8250 port structure prior to console initialisation. Use
3212 * after console initialisation will cause undefined behaviour.
3213 */
3214 int __init early_serial_setup(struct uart_port *port)
3215 {
3216 struct uart_port *p;
3217
3218 if (port->line >= ARRAY_SIZE(serial8250_ports))
3219 return -ENODEV;
3220
3221 serial8250_isa_init_ports();
3222 p = &serial8250_ports[port->line].port;
3223 p->iobase = port->iobase;
3224 p->membase = port->membase;
3225 p->irq = port->irq;
3226 p->irqflags = port->irqflags;
3227 p->uartclk = port->uartclk;
3228 p->fifosize = port->fifosize;
3229 p->regshift = port->regshift;
3230 p->iotype = port->iotype;
3231 p->flags = port->flags;
3232 p->mapbase = port->mapbase;
3233 p->private_data = port->private_data;
3234 p->type = port->type;
3235 p->line = port->line;
3236
3237 set_io_from_upio(p);
3238 if (port->serial_in)
3239 p->serial_in = port->serial_in;
3240 if (port->serial_out)
3241 p->serial_out = port->serial_out;
3242 if (port->handle_irq)
3243 p->handle_irq = port->handle_irq;
3244 else
3245 p->handle_irq = serial8250_default_handle_irq;
3246
3247 return 0;
3248 }
3249
3250 /**
3251 * serial8250_suspend_port - suspend one serial port
3252 * @line: serial line number
3253 *
3254 * Suspend one serial port.
3255 */
3256 void serial8250_suspend_port(int line)
3257 {
3258 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3259 }
3260
3261 /**
3262 * serial8250_resume_port - resume one serial port
3263 * @line: serial line number
3264 *
3265 * Resume one serial port.
3266 */
3267 void serial8250_resume_port(int line)
3268 {
3269 struct uart_8250_port *up = &serial8250_ports[line];
3270 struct uart_port *port = &up->port;
3271
3272 if (up->capabilities & UART_NATSEMI) {
3273 /* Ensure it's still in high speed mode */
3274 serial_port_out(port, UART_LCR, 0xE0);
3275
3276 ns16550a_goto_highspeed(up);
3277
3278 serial_port_out(port, UART_LCR, 0);
3279 port->uartclk = 921600*16;
3280 }
3281 uart_resume_port(&serial8250_reg, port);
3282 }
3283
3284 /*
3285 * Register a set of serial devices attached to a platform device. The
3286 * list is terminated with a zero flags entry, which means we expect
3287 * all entries to have at least UPF_BOOT_AUTOCONF set.
3288 */
3289 static int serial8250_probe(struct platform_device *dev)
3290 {
3291 struct plat_serial8250_port *p = dev_get_platdata(&dev->dev);
3292 struct uart_8250_port uart;
3293 int ret, i, irqflag = 0;
3294
3295 memset(&uart, 0, sizeof(uart));
3296
3297 if (share_irqs)
3298 irqflag = IRQF_SHARED;
3299
3300 for (i = 0; p && p->flags != 0; p++, i++) {
3301 uart.port.iobase = p->iobase;
3302 uart.port.membase = p->membase;
3303 uart.port.irq = p->irq;
3304 uart.port.irqflags = p->irqflags;
3305 uart.port.uartclk = p->uartclk;
3306 uart.port.regshift = p->regshift;
3307 uart.port.iotype = p->iotype;
3308 uart.port.flags = p->flags;
3309 uart.port.mapbase = p->mapbase;
3310 uart.port.hub6 = p->hub6;
3311 uart.port.private_data = p->private_data;
3312 uart.port.type = p->type;
3313 uart.port.serial_in = p->serial_in;
3314 uart.port.serial_out = p->serial_out;
3315 uart.port.handle_irq = p->handle_irq;
3316 uart.port.handle_break = p->handle_break;
3317 uart.port.set_termios = p->set_termios;
3318 uart.port.pm = p->pm;
3319 uart.port.dev = &dev->dev;
3320 uart.port.irqflags |= irqflag;
3321 ret = serial8250_register_8250_port(&uart);
3322 if (ret < 0) {
3323 dev_err(&dev->dev, "unable to register port at index %d "
3324 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3325 p->iobase, (unsigned long long)p->mapbase,
3326 p->irq, ret);
3327 }
3328 }
3329 return 0;
3330 }
3331
3332 /*
3333 * Remove serial ports registered against a platform device.
3334 */
3335 static int serial8250_remove(struct platform_device *dev)
3336 {
3337 int i;
3338
3339 for (i = 0; i < nr_uarts; i++) {
3340 struct uart_8250_port *up = &serial8250_ports[i];
3341
3342 if (up->port.dev == &dev->dev)
3343 serial8250_unregister_port(i);
3344 }
3345 return 0;
3346 }
3347
3348 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3349 {
3350 int i;
3351
3352 for (i = 0; i < UART_NR; i++) {
3353 struct uart_8250_port *up = &serial8250_ports[i];
3354
3355 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3356 uart_suspend_port(&serial8250_reg, &up->port);
3357 }
3358
3359 return 0;
3360 }
3361
3362 static int serial8250_resume(struct platform_device *dev)
3363 {
3364 int i;
3365
3366 for (i = 0; i < UART_NR; i++) {
3367 struct uart_8250_port *up = &serial8250_ports[i];
3368
3369 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3370 serial8250_resume_port(i);
3371 }
3372
3373 return 0;
3374 }
3375
3376 static struct platform_driver serial8250_isa_driver = {
3377 .probe = serial8250_probe,
3378 .remove = serial8250_remove,
3379 .suspend = serial8250_suspend,
3380 .resume = serial8250_resume,
3381 .driver = {
3382 .name = "serial8250",
3383 .owner = THIS_MODULE,
3384 },
3385 };
3386
3387 /*
3388 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3389 * in the table in include/asm/serial.h
3390 */
3391 static struct platform_device *serial8250_isa_devs;
3392
3393 /*
3394 * serial8250_register_8250_port and serial8250_unregister_port allows for
3395 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3396 * modems and PCI multiport cards.
3397 */
3398 static DEFINE_MUTEX(serial_mutex);
3399
3400 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3401 {
3402 int i;
3403
3404 /*
3405 * First, find a port entry which matches.
3406 */
3407 for (i = 0; i < nr_uarts; i++)
3408 if (uart_match_port(&serial8250_ports[i].port, port))
3409 return &serial8250_ports[i];
3410
3411 /*
3412 * We didn't find a matching entry, so look for the first
3413 * free entry. We look for one which hasn't been previously
3414 * used (indicated by zero iobase).
3415 */
3416 for (i = 0; i < nr_uarts; i++)
3417 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3418 serial8250_ports[i].port.iobase == 0)
3419 return &serial8250_ports[i];
3420
3421 /*
3422 * That also failed. Last resort is to find any entry which
3423 * doesn't have a real port associated with it.
3424 */
3425 for (i = 0; i < nr_uarts; i++)
3426 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3427 return &serial8250_ports[i];
3428
3429 return NULL;
3430 }
3431
3432 /**
3433 * serial8250_register_8250_port - register a serial port
3434 * @up: serial port template
3435 *
3436 * Configure the serial port specified by the request. If the
3437 * port exists and is in use, it is hung up and unregistered
3438 * first.
3439 *
3440 * The port is then probed and if necessary the IRQ is autodetected
3441 * If this fails an error is returned.
3442 *
3443 * On success the port is ready to use and the line number is returned.
3444 */
3445 int serial8250_register_8250_port(struct uart_8250_port *up)
3446 {
3447 struct uart_8250_port *uart;
3448 int ret = -ENOSPC;
3449
3450 if (up->port.uartclk == 0)
3451 return -EINVAL;
3452
3453 mutex_lock(&serial_mutex);
3454
3455 uart = serial8250_find_match_or_unused(&up->port);
3456 if (uart && uart->port.type != PORT_8250_CIR) {
3457 if (uart->port.dev)
3458 uart_remove_one_port(&serial8250_reg, &uart->port);
3459
3460 uart->port.iobase = up->port.iobase;
3461 uart->port.membase = up->port.membase;
3462 uart->port.irq = up->port.irq;
3463 uart->port.irqflags = up->port.irqflags;
3464 uart->port.uartclk = up->port.uartclk;
3465 uart->port.fifosize = up->port.fifosize;
3466 uart->port.regshift = up->port.regshift;
3467 uart->port.iotype = up->port.iotype;
3468 uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF;
3469 uart->bugs = up->bugs;
3470 uart->port.mapbase = up->port.mapbase;
3471 uart->port.private_data = up->port.private_data;
3472 uart->port.fifosize = up->port.fifosize;
3473 uart->tx_loadsz = up->tx_loadsz;
3474 uart->capabilities = up->capabilities;
3475 uart->rs485_config = up->rs485_config;
3476 uart->rs485 = up->rs485;
3477 uart->port.throttle = up->port.throttle;
3478 uart->port.unthrottle = up->port.unthrottle;
3479
3480 /* Take tx_loadsz from fifosize if it wasn't set separately */
3481 if (uart->port.fifosize && !uart->tx_loadsz)
3482 uart->tx_loadsz = uart->port.fifosize;
3483
3484 if (up->port.dev)
3485 uart->port.dev = up->port.dev;
3486
3487 if (up->port.flags & UPF_FIXED_TYPE)
3488 serial8250_init_fixed_type_port(uart, up->port.type);
3489
3490 set_io_from_upio(&uart->port);
3491 /* Possibly override default I/O functions. */
3492 if (up->port.serial_in)
3493 uart->port.serial_in = up->port.serial_in;
3494 if (up->port.serial_out)
3495 uart->port.serial_out = up->port.serial_out;
3496 if (up->port.handle_irq)
3497 uart->port.handle_irq = up->port.handle_irq;
3498 /* Possibly override set_termios call */
3499 if (up->port.set_termios)
3500 uart->port.set_termios = up->port.set_termios;
3501 if (up->port.startup)
3502 uart->port.startup = up->port.startup;
3503 if (up->port.shutdown)
3504 uart->port.shutdown = up->port.shutdown;
3505 if (up->port.pm)
3506 uart->port.pm = up->port.pm;
3507 if (up->port.handle_break)
3508 uart->port.handle_break = up->port.handle_break;
3509 if (up->dl_read)
3510 uart->dl_read = up->dl_read;
3511 if (up->dl_write)
3512 uart->dl_write = up->dl_write;
3513 if (up->dma)
3514 uart->dma = up->dma;
3515
3516 if (serial8250_isa_config != NULL)
3517 serial8250_isa_config(0, &uart->port,
3518 &uart->capabilities);
3519
3520 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3521 if (ret == 0)
3522 ret = uart->port.line;
3523 }
3524 mutex_unlock(&serial_mutex);
3525
3526 return ret;
3527 }
3528 EXPORT_SYMBOL(serial8250_register_8250_port);
3529
3530 /**
3531 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3532 * @line: serial line number
3533 *
3534 * Remove one serial port. This may not be called from interrupt
3535 * context. We hand the port back to the our control.
3536 */
3537 void serial8250_unregister_port(int line)
3538 {
3539 struct uart_8250_port *uart = &serial8250_ports[line];
3540
3541 mutex_lock(&serial_mutex);
3542 uart_remove_one_port(&serial8250_reg, &uart->port);
3543 if (serial8250_isa_devs) {
3544 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3545 uart->port.type = PORT_UNKNOWN;
3546 uart->port.dev = &serial8250_isa_devs->dev;
3547 uart->capabilities = uart_config[uart->port.type].flags;
3548 uart_add_one_port(&serial8250_reg, &uart->port);
3549 } else {
3550 uart->port.dev = NULL;
3551 }
3552 mutex_unlock(&serial_mutex);
3553 }
3554 EXPORT_SYMBOL(serial8250_unregister_port);
3555
3556 static int __init serial8250_init(void)
3557 {
3558 int ret;
3559
3560 serial8250_isa_init_ports();
3561
3562 printk(KERN_INFO "Serial: 8250/16550 driver, "
3563 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3564 share_irqs ? "en" : "dis");
3565
3566 #ifdef CONFIG_SPARC
3567 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3568 #else
3569 serial8250_reg.nr = UART_NR;
3570 ret = uart_register_driver(&serial8250_reg);
3571 #endif
3572 if (ret)
3573 goto out;
3574
3575 ret = serial8250_pnp_init();
3576 if (ret)
3577 goto unreg_uart_drv;
3578
3579 serial8250_isa_devs = platform_device_alloc("serial8250",
3580 PLAT8250_DEV_LEGACY);
3581 if (!serial8250_isa_devs) {
3582 ret = -ENOMEM;
3583 goto unreg_pnp;
3584 }
3585
3586 ret = platform_device_add(serial8250_isa_devs);
3587 if (ret)
3588 goto put_dev;
3589
3590 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3591
3592 ret = platform_driver_register(&serial8250_isa_driver);
3593 if (ret == 0)
3594 goto out;
3595
3596 platform_device_del(serial8250_isa_devs);
3597 put_dev:
3598 platform_device_put(serial8250_isa_devs);
3599 unreg_pnp:
3600 serial8250_pnp_exit();
3601 unreg_uart_drv:
3602 #ifdef CONFIG_SPARC
3603 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3604 #else
3605 uart_unregister_driver(&serial8250_reg);
3606 #endif
3607 out:
3608 return ret;
3609 }
3610
3611 static void __exit serial8250_exit(void)
3612 {
3613 struct platform_device *isa_dev = serial8250_isa_devs;
3614
3615 /*
3616 * This tells serial8250_unregister_port() not to re-register
3617 * the ports (thereby making serial8250_isa_driver permanently
3618 * in use.)
3619 */
3620 serial8250_isa_devs = NULL;
3621
3622 platform_driver_unregister(&serial8250_isa_driver);
3623 platform_device_unregister(isa_dev);
3624
3625 serial8250_pnp_exit();
3626
3627 #ifdef CONFIG_SPARC
3628 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3629 #else
3630 uart_unregister_driver(&serial8250_reg);
3631 #endif
3632 }
3633
3634 module_init(serial8250_init);
3635 module_exit(serial8250_exit);
3636
3637 EXPORT_SYMBOL(serial8250_suspend_port);
3638 EXPORT_SYMBOL(serial8250_resume_port);
3639
3640 MODULE_LICENSE("GPL");
3641 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3642
3643 module_param(share_irqs, uint, 0644);
3644 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3645 " (unsafe)");
3646
3647 module_param(nr_uarts, uint, 0644);
3648 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3649
3650 module_param(skip_txen_test, uint, 0644);
3651 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3652
3653 #ifdef CONFIG_SERIAL_8250_RSA
3654 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3655 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3656 #endif
3657 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
3658
3659 #ifdef CONFIG_SERIAL_8250_DEPRECATED_OPTIONS
3660 #ifndef MODULE
3661 /* This module was renamed to 8250_core in 3.7. Keep the old "8250" name
3662 * working as well for the module options so we don't break people. We
3663 * need to keep the names identical and the convenient macros will happily
3664 * refuse to let us do that by failing the build with redefinition errors
3665 * of global variables. So we stick them inside a dummy function to avoid
3666 * those conflicts. The options still get parsed, and the redefined
3667 * MODULE_PARAM_PREFIX lets us keep the "8250." syntax alive.
3668 *
3669 * This is hacky. I'm sorry.
3670 */
3671 static void __used s8250_options(void)
3672 {
3673 #undef MODULE_PARAM_PREFIX
3674 #define MODULE_PARAM_PREFIX "8250_core."
3675
3676 module_param_cb(share_irqs, &param_ops_uint, &share_irqs, 0644);
3677 module_param_cb(nr_uarts, &param_ops_uint, &nr_uarts, 0644);
3678 module_param_cb(skip_txen_test, &param_ops_uint, &skip_txen_test, 0644);
3679 #ifdef CONFIG_SERIAL_8250_RSA
3680 __module_param_call(MODULE_PARAM_PREFIX, probe_rsa,
3681 &param_array_ops, .arr = &__param_arr_probe_rsa,
3682 0444, -1);
3683 #endif
3684 }
3685 #else
3686 MODULE_ALIAS("8250_core");
3687 #endif
3688 #endif
Linux kernel - Deliverables
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