2 * Base port operations for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * A note about mapbase / membase
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
18 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/console.h>
27 #include <linux/sysrq.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/ratelimit.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial.h>
34 #include <linux/serial_8250.h>
35 #include <linux/nmi.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/timer.h>
51 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
53 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
56 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
59 * Here we define the default xmit fifo size used for each type of UART.
61 static const struct serial8250_config uart_config
[] = {
86 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
87 .rxtrig_bytes
= {1, 4, 8, 14},
88 .flags
= UART_CAP_FIFO
,
99 .flags
= UART_CAP_FIFO
| UART_CAP_EFR
| UART_CAP_SLEEP
,
105 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_01
|
107 .rxtrig_bytes
= {8, 16, 24, 28},
108 .flags
= UART_CAP_FIFO
| UART_CAP_EFR
| UART_CAP_SLEEP
,
114 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
|
116 .rxtrig_bytes
= {1, 16, 32, 56},
117 .flags
= UART_CAP_FIFO
| UART_CAP_SLEEP
| UART_CAP_AFE
,
125 .name
= "16C950/954",
128 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
129 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
130 .flags
= UART_CAP_FIFO
| UART_CAP_SLEEP
,
136 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_01
|
138 .rxtrig_bytes
= {8, 16, 56, 60},
139 .flags
= UART_CAP_FIFO
| UART_CAP_EFR
| UART_CAP_SLEEP
,
145 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
146 .flags
= UART_CAP_FIFO
| UART_CAP_EFR
| UART_CAP_SLEEP
,
152 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_11
,
153 .flags
= UART_CAP_FIFO
,
159 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
160 .flags
= UART_CAP_FIFO
| UART_NATSEMI
,
166 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
167 .flags
= UART_CAP_FIFO
| UART_CAP_UUE
| UART_CAP_RTOIE
,
173 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
174 .flags
= UART_CAP_FIFO
,
180 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_00
,
181 .flags
= UART_CAP_FIFO
| UART_CAP_AFE
,
187 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
188 .flags
= UART_CAP_FIFO
| UART_CAP_AFE
,
194 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_01
|
196 .rxtrig_bytes
= {1, 4, 8, 14},
197 .flags
= UART_CAP_FIFO
| UART_CAP_RTOIE
,
203 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
204 .flags
= UART_CAP_FIFO
| UART_CAP_AFE
| UART_CAP_EFR
|
211 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_11
|
213 .flags
= UART_CAP_FIFO
| UART_CAP_AFE
| UART_CAP_EFR
|
220 .fcr
= UART_FCR_DMA_SELECT
| UART_FCR_ENABLE_FIFO
|
221 UART_FCR_R_TRIG_00
| UART_FCR_T_TRIG_00
,
222 .flags
= UART_CAP_FIFO
,
224 [PORT_BRCM_TRUMANAGE
] = {
228 .flags
= UART_CAP_HFIFO
,
233 [PORT_ALTR_16550_F32
] = {
234 .name
= "Altera 16550 FIFO32",
237 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
238 .flags
= UART_CAP_FIFO
| UART_CAP_AFE
,
240 [PORT_ALTR_16550_F64
] = {
241 .name
= "Altera 16550 FIFO64",
244 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
245 .flags
= UART_CAP_FIFO
| UART_CAP_AFE
,
247 [PORT_ALTR_16550_F128
] = {
248 .name
= "Altera 16550 FIFO128",
251 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
252 .flags
= UART_CAP_FIFO
| UART_CAP_AFE
,
255 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
256 * workaround of errata A-008006 which states that tx_loadsz should
257 * be configured less than Maximum supported fifo bytes.
259 [PORT_16550A_FSL64
] = {
260 .name
= "16550A_FSL64",
263 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
|
265 .flags
= UART_CAP_FIFO
,
268 .name
= "Palmchip BK-3103",
271 .fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_R_TRIG_10
,
272 .rxtrig_bytes
= {1, 4, 8, 14},
273 .flags
= UART_CAP_FIFO
,
277 /* Uart divisor latch read */
278 static int default_serial_dl_read(struct uart_8250_port
*up
)
280 return serial_in(up
, UART_DLL
) | serial_in(up
, UART_DLM
) << 8;
283 /* Uart divisor latch write */
284 static void default_serial_dl_write(struct uart_8250_port
*up
, int value
)
286 serial_out(up
, UART_DLL
, value
& 0xff);
287 serial_out(up
, UART_DLM
, value
>> 8 & 0xff);
290 #ifdef CONFIG_SERIAL_8250_RT288X
292 /* Au1x00/RT288x UART hardware has a weird register layout */
293 static const s8 au_io_in_map
[8] = {
301 -1, /* UART_SCR (unmapped) */
304 static const s8 au_io_out_map
[8] = {
310 -1, /* UART_LSR (unmapped) */
311 -1, /* UART_MSR (unmapped) */
312 -1, /* UART_SCR (unmapped) */
315 static unsigned int au_serial_in(struct uart_port
*p
, int offset
)
317 if (offset
>= ARRAY_SIZE(au_io_in_map
))
319 offset
= au_io_in_map
[offset
];
322 return __raw_readl(p
->membase
+ (offset
<< p
->regshift
));
325 static void au_serial_out(struct uart_port
*p
, int offset
, int value
)
327 if (offset
>= ARRAY_SIZE(au_io_out_map
))
329 offset
= au_io_out_map
[offset
];
332 __raw_writel(value
, p
->membase
+ (offset
<< p
->regshift
));
335 /* Au1x00 haven't got a standard divisor latch */
336 static int au_serial_dl_read(struct uart_8250_port
*up
)
338 return __raw_readl(up
->port
.membase
+ 0x28);
341 static void au_serial_dl_write(struct uart_8250_port
*up
, int value
)
343 __raw_writel(value
, up
->port
.membase
+ 0x28);
348 static unsigned int hub6_serial_in(struct uart_port
*p
, int offset
)
350 offset
= offset
<< p
->regshift
;
351 outb(p
->hub6
- 1 + offset
, p
->iobase
);
352 return inb(p
->iobase
+ 1);
355 static void hub6_serial_out(struct uart_port
*p
, int offset
, int value
)
357 offset
= offset
<< p
->regshift
;
358 outb(p
->hub6
- 1 + offset
, p
->iobase
);
359 outb(value
, p
->iobase
+ 1);
362 static unsigned int mem_serial_in(struct uart_port
*p
, int offset
)
364 offset
= offset
<< p
->regshift
;
365 return readb(p
->membase
+ offset
);
368 static void mem_serial_out(struct uart_port
*p
, int offset
, int value
)
370 offset
= offset
<< p
->regshift
;
371 writeb(value
, p
->membase
+ offset
);
374 static void mem16_serial_out(struct uart_port
*p
, int offset
, int value
)
376 offset
= offset
<< p
->regshift
;
377 writew(value
, p
->membase
+ offset
);
380 static unsigned int mem16_serial_in(struct uart_port
*p
, int offset
)
382 offset
= offset
<< p
->regshift
;
383 return readw(p
->membase
+ offset
);
386 static void mem32_serial_out(struct uart_port
*p
, int offset
, int value
)
388 offset
= offset
<< p
->regshift
;
389 writel(value
, p
->membase
+ offset
);
392 static unsigned int mem32_serial_in(struct uart_port
*p
, int offset
)
394 offset
= offset
<< p
->regshift
;
395 return readl(p
->membase
+ offset
);
398 static void mem32be_serial_out(struct uart_port
*p
, int offset
, int value
)
400 offset
= offset
<< p
->regshift
;
401 iowrite32be(value
, p
->membase
+ offset
);
404 static unsigned int mem32be_serial_in(struct uart_port
*p
, int offset
)
406 offset
= offset
<< p
->regshift
;
407 return ioread32be(p
->membase
+ offset
);
410 static unsigned int io_serial_in(struct uart_port
*p
, int offset
)
412 offset
= offset
<< p
->regshift
;
413 return inb(p
->iobase
+ offset
);
416 static void io_serial_out(struct uart_port
*p
, int offset
, int value
)
418 offset
= offset
<< p
->regshift
;
419 outb(value
, p
->iobase
+ offset
);
422 static int serial8250_default_handle_irq(struct uart_port
*port
);
423 static int exar_handle_irq(struct uart_port
*port
);
425 static void set_io_from_upio(struct uart_port
*p
)
427 struct uart_8250_port
*up
= up_to_u8250p(p
);
429 up
->dl_read
= default_serial_dl_read
;
430 up
->dl_write
= default_serial_dl_write
;
434 p
->serial_in
= hub6_serial_in
;
435 p
->serial_out
= hub6_serial_out
;
439 p
->serial_in
= mem_serial_in
;
440 p
->serial_out
= mem_serial_out
;
444 p
->serial_in
= mem16_serial_in
;
445 p
->serial_out
= mem16_serial_out
;
449 p
->serial_in
= mem32_serial_in
;
450 p
->serial_out
= mem32_serial_out
;
454 p
->serial_in
= mem32be_serial_in
;
455 p
->serial_out
= mem32be_serial_out
;
458 #ifdef CONFIG_SERIAL_8250_RT288X
460 p
->serial_in
= au_serial_in
;
461 p
->serial_out
= au_serial_out
;
462 up
->dl_read
= au_serial_dl_read
;
463 up
->dl_write
= au_serial_dl_write
;
468 p
->serial_in
= io_serial_in
;
469 p
->serial_out
= io_serial_out
;
472 /* Remember loaded iotype */
473 up
->cur_iotype
= p
->iotype
;
474 p
->handle_irq
= serial8250_default_handle_irq
;
478 serial_port_out_sync(struct uart_port
*p
, int offset
, int value
)
486 p
->serial_out(p
, offset
, value
);
487 p
->serial_in(p
, UART_LCR
); /* safe, no side-effects */
490 p
->serial_out(p
, offset
, value
);
497 static void serial_icr_write(struct uart_8250_port
*up
, int offset
, int value
)
499 serial_out(up
, UART_SCR
, offset
);
500 serial_out(up
, UART_ICR
, value
);
503 static unsigned int serial_icr_read(struct uart_8250_port
*up
, int offset
)
507 serial_icr_write(up
, UART_ACR
, up
->acr
| UART_ACR_ICRRD
);
508 serial_out(up
, UART_SCR
, offset
);
509 value
= serial_in(up
, UART_ICR
);
510 serial_icr_write(up
, UART_ACR
, up
->acr
);
518 static void serial8250_clear_fifos(struct uart_8250_port
*p
)
520 if (p
->capabilities
& UART_CAP_FIFO
) {
521 serial_out(p
, UART_FCR
, UART_FCR_ENABLE_FIFO
);
522 serial_out(p
, UART_FCR
, UART_FCR_ENABLE_FIFO
|
523 UART_FCR_CLEAR_RCVR
| UART_FCR_CLEAR_XMIT
);
524 serial_out(p
, UART_FCR
, 0);
528 static inline void serial8250_em485_rts_after_send(struct uart_8250_port
*p
)
530 unsigned char mcr
= serial8250_in_MCR(p
);
532 if (p
->port
.rs485
.flags
& SER_RS485_RTS_AFTER_SEND
)
535 mcr
&= ~UART_MCR_RTS
;
536 serial8250_out_MCR(p
, mcr
);
539 static void serial8250_em485_handle_start_tx(unsigned long arg
);
540 static void serial8250_em485_handle_stop_tx(unsigned long arg
);
542 void serial8250_clear_and_reinit_fifos(struct uart_8250_port
*p
)
544 serial8250_clear_fifos(p
);
545 serial_out(p
, UART_FCR
, p
->fcr
);
547 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos
);
549 void serial8250_rpm_get(struct uart_8250_port
*p
)
551 if (!(p
->capabilities
& UART_CAP_RPM
))
553 pm_runtime_get_sync(p
->port
.dev
);
555 EXPORT_SYMBOL_GPL(serial8250_rpm_get
);
557 void serial8250_rpm_put(struct uart_8250_port
*p
)
559 if (!(p
->capabilities
& UART_CAP_RPM
))
561 pm_runtime_mark_last_busy(p
->port
.dev
);
562 pm_runtime_put_autosuspend(p
->port
.dev
);
564 EXPORT_SYMBOL_GPL(serial8250_rpm_put
);
567 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
568 * @p: uart_8250_port port instance
570 * The function is used to start rs485 software emulating on the
571 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
572 * transmission. The function is idempotent, so it is safe to call it
575 * The caller MUST enable interrupt on empty shift register before
576 * calling serial8250_em485_init(). This interrupt is not a part of
577 * 8250 standard, but implementation defined.
579 * The function is supposed to be called from .rs485_config callback
580 * or from any other callback protected with p->port.lock spinlock.
582 * See also serial8250_em485_destroy()
584 * Return 0 - success, -errno - otherwise
586 int serial8250_em485_init(struct uart_8250_port
*p
)
588 if (p
->em485
!= NULL
)
591 p
->em485
= kmalloc(sizeof(struct uart_8250_em485
), GFP_ATOMIC
);
592 if (p
->em485
== NULL
)
595 setup_timer(&p
->em485
->stop_tx_timer
,
596 serial8250_em485_handle_stop_tx
, (unsigned long)p
);
597 setup_timer(&p
->em485
->start_tx_timer
,
598 serial8250_em485_handle_start_tx
, (unsigned long)p
);
599 p
->em485
->active_timer
= NULL
;
601 serial8250_em485_rts_after_send(p
);
605 EXPORT_SYMBOL_GPL(serial8250_em485_init
);
608 * serial8250_em485_destroy() - put uart_8250_port into normal state
609 * @p: uart_8250_port port instance
611 * The function is used to stop rs485 software emulating on the
612 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
613 * call it multiple times.
615 * The function is supposed to be called from .rs485_config callback
616 * or from any other callback protected with p->port.lock spinlock.
618 * See also serial8250_em485_init()
620 void serial8250_em485_destroy(struct uart_8250_port
*p
)
622 if (p
->em485
== NULL
)
625 del_timer(&p
->em485
->start_tx_timer
);
626 del_timer(&p
->em485
->stop_tx_timer
);
631 EXPORT_SYMBOL_GPL(serial8250_em485_destroy
);
634 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
635 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
636 * empty and the HW can idle again.
638 static void serial8250_rpm_get_tx(struct uart_8250_port
*p
)
640 unsigned char rpm_active
;
642 if (!(p
->capabilities
& UART_CAP_RPM
))
645 rpm_active
= xchg(&p
->rpm_tx_active
, 1);
648 pm_runtime_get_sync(p
->port
.dev
);
651 static void serial8250_rpm_put_tx(struct uart_8250_port
*p
)
653 unsigned char rpm_active
;
655 if (!(p
->capabilities
& UART_CAP_RPM
))
658 rpm_active
= xchg(&p
->rpm_tx_active
, 0);
661 pm_runtime_mark_last_busy(p
->port
.dev
);
662 pm_runtime_put_autosuspend(p
->port
.dev
);
666 * IER sleep support. UARTs which have EFRs need the "extended
667 * capability" bit enabled. Note that on XR16C850s, we need to
668 * reset LCR to write to IER.
670 static void serial8250_set_sleep(struct uart_8250_port
*p
, int sleep
)
672 unsigned char lcr
= 0, efr
= 0;
674 * Exar UARTs have a SLEEP register that enables or disables
675 * each UART to enter sleep mode separately. On the XR17V35x the
676 * register is accessible to each UART at the UART_EXAR_SLEEP
677 * offset but the UART channel may only write to the corresponding
680 serial8250_rpm_get(p
);
681 if ((p
->port
.type
== PORT_XR17V35X
) ||
682 (p
->port
.type
== PORT_XR17D15X
)) {
683 serial_out(p
, UART_EXAR_SLEEP
, sleep
? 0xff : 0);
687 if (p
->capabilities
& UART_CAP_SLEEP
) {
688 if (p
->capabilities
& UART_CAP_EFR
) {
689 lcr
= serial_in(p
, UART_LCR
);
690 efr
= serial_in(p
, UART_EFR
);
691 serial_out(p
, UART_LCR
, UART_LCR_CONF_MODE_B
);
692 serial_out(p
, UART_EFR
, UART_EFR_ECB
);
693 serial_out(p
, UART_LCR
, 0);
695 serial_out(p
, UART_IER
, sleep
? UART_IERX_SLEEP
: 0);
696 if (p
->capabilities
& UART_CAP_EFR
) {
697 serial_out(p
, UART_LCR
, UART_LCR_CONF_MODE_B
);
698 serial_out(p
, UART_EFR
, efr
);
699 serial_out(p
, UART_LCR
, lcr
);
703 serial8250_rpm_put(p
);
706 #ifdef CONFIG_SERIAL_8250_RSA
708 * Attempts to turn on the RSA FIFO. Returns zero on failure.
709 * We set the port uart clock rate if we succeed.
711 static int __enable_rsa(struct uart_8250_port
*up
)
716 mode
= serial_in(up
, UART_RSA_MSR
);
717 result
= mode
& UART_RSA_MSR_FIFO
;
720 serial_out(up
, UART_RSA_MSR
, mode
| UART_RSA_MSR_FIFO
);
721 mode
= serial_in(up
, UART_RSA_MSR
);
722 result
= mode
& UART_RSA_MSR_FIFO
;
726 up
->port
.uartclk
= SERIAL_RSA_BAUD_BASE
* 16;
731 static void enable_rsa(struct uart_8250_port
*up
)
733 if (up
->port
.type
== PORT_RSA
) {
734 if (up
->port
.uartclk
!= SERIAL_RSA_BAUD_BASE
* 16) {
735 spin_lock_irq(&up
->port
.lock
);
737 spin_unlock_irq(&up
->port
.lock
);
739 if (up
->port
.uartclk
== SERIAL_RSA_BAUD_BASE
* 16)
740 serial_out(up
, UART_RSA_FRR
, 0);
745 * Attempts to turn off the RSA FIFO. Returns zero on failure.
746 * It is unknown why interrupts were disabled in here. However,
747 * the caller is expected to preserve this behaviour by grabbing
748 * the spinlock before calling this function.
750 static void disable_rsa(struct uart_8250_port
*up
)
755 if (up
->port
.type
== PORT_RSA
&&
756 up
->port
.uartclk
== SERIAL_RSA_BAUD_BASE
* 16) {
757 spin_lock_irq(&up
->port
.lock
);
759 mode
= serial_in(up
, UART_RSA_MSR
);
760 result
= !(mode
& UART_RSA_MSR_FIFO
);
763 serial_out(up
, UART_RSA_MSR
, mode
& ~UART_RSA_MSR_FIFO
);
764 mode
= serial_in(up
, UART_RSA_MSR
);
765 result
= !(mode
& UART_RSA_MSR_FIFO
);
769 up
->port
.uartclk
= SERIAL_RSA_BAUD_BASE_LO
* 16;
770 spin_unlock_irq(&up
->port
.lock
);
773 #endif /* CONFIG_SERIAL_8250_RSA */
776 * This is a quickie test to see how big the FIFO is.
777 * It doesn't work at all the time, more's the pity.
779 static int size_fifo(struct uart_8250_port
*up
)
781 unsigned char old_fcr
, old_mcr
, old_lcr
;
782 unsigned short old_dl
;
785 old_lcr
= serial_in(up
, UART_LCR
);
786 serial_out(up
, UART_LCR
, 0);
787 old_fcr
= serial_in(up
, UART_FCR
);
788 old_mcr
= serial8250_in_MCR(up
);
789 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
|
790 UART_FCR_CLEAR_RCVR
| UART_FCR_CLEAR_XMIT
);
791 serial8250_out_MCR(up
, UART_MCR_LOOP
);
792 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
793 old_dl
= serial_dl_read(up
);
794 serial_dl_write(up
, 0x0001);
795 serial_out(up
, UART_LCR
, 0x03);
796 for (count
= 0; count
< 256; count
++)
797 serial_out(up
, UART_TX
, count
);
798 mdelay(20);/* FIXME - schedule_timeout */
799 for (count
= 0; (serial_in(up
, UART_LSR
) & UART_LSR_DR
) &&
800 (count
< 256); count
++)
801 serial_in(up
, UART_RX
);
802 serial_out(up
, UART_FCR
, old_fcr
);
803 serial8250_out_MCR(up
, old_mcr
);
804 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
805 serial_dl_write(up
, old_dl
);
806 serial_out(up
, UART_LCR
, old_lcr
);
812 * Read UART ID using the divisor method - set DLL and DLM to zero
813 * and the revision will be in DLL and device type in DLM. We
814 * preserve the device state across this.
816 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port
*p
)
818 unsigned char old_lcr
;
819 unsigned int id
, old_dl
;
821 old_lcr
= serial_in(p
, UART_LCR
);
822 serial_out(p
, UART_LCR
, UART_LCR_CONF_MODE_A
);
823 old_dl
= serial_dl_read(p
);
824 serial_dl_write(p
, 0);
825 id
= serial_dl_read(p
);
826 serial_dl_write(p
, old_dl
);
828 serial_out(p
, UART_LCR
, old_lcr
);
834 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
835 * When this function is called we know it is at least a StarTech
836 * 16650 V2, but it might be one of several StarTech UARTs, or one of
837 * its clones. (We treat the broken original StarTech 16650 V1 as a
838 * 16550, and why not? Startech doesn't seem to even acknowledge its
841 * What evil have men's minds wrought...
843 static void autoconfig_has_efr(struct uart_8250_port
*up
)
845 unsigned int id1
, id2
, id3
, rev
;
848 * Everything with an EFR has SLEEP
850 up
->capabilities
|= UART_CAP_EFR
| UART_CAP_SLEEP
;
853 * First we check to see if it's an Oxford Semiconductor UART.
855 * If we have to do this here because some non-National
856 * Semiconductor clone chips lock up if you try writing to the
857 * LSR register (which serial_icr_read does)
861 * Check for Oxford Semiconductor 16C950.
863 * EFR [4] must be set else this test fails.
865 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
866 * claims that it's needed for 952 dual UART's (which are not
867 * recommended for new designs).
870 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
871 serial_out(up
, UART_EFR
, UART_EFR_ECB
);
872 serial_out(up
, UART_LCR
, 0x00);
873 id1
= serial_icr_read(up
, UART_ID1
);
874 id2
= serial_icr_read(up
, UART_ID2
);
875 id3
= serial_icr_read(up
, UART_ID3
);
876 rev
= serial_icr_read(up
, UART_REV
);
878 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1
, id2
, id3
, rev
);
880 if (id1
== 0x16 && id2
== 0xC9 &&
881 (id3
== 0x50 || id3
== 0x52 || id3
== 0x54)) {
882 up
->port
.type
= PORT_16C950
;
885 * Enable work around for the Oxford Semiconductor 952 rev B
886 * chip which causes it to seriously miscalculate baud rates
889 if (id3
== 0x52 && rev
== 0x01)
890 up
->bugs
|= UART_BUG_QUOT
;
895 * We check for a XR16C850 by setting DLL and DLM to 0, and then
896 * reading back DLL and DLM. The chip type depends on the DLM
898 * 0x10 - XR16C850 and the DLL contains the chip revision.
902 id1
= autoconfig_read_divisor_id(up
);
903 DEBUG_AUTOCONF("850id=%04x ", id1
);
906 if (id2
== 0x10 || id2
== 0x12 || id2
== 0x14) {
907 up
->port
.type
= PORT_16850
;
912 * It wasn't an XR16C850.
914 * We distinguish between the '654 and the '650 by counting
915 * how many bytes are in the FIFO. I'm using this for now,
916 * since that's the technique that was sent to me in the
917 * serial driver update, but I'm not convinced this works.
918 * I've had problems doing this in the past. -TYT
920 if (size_fifo(up
) == 64)
921 up
->port
.type
= PORT_16654
;
923 up
->port
.type
= PORT_16650V2
;
927 * We detected a chip without a FIFO. Only two fall into
928 * this category - the original 8250 and the 16450. The
929 * 16450 has a scratch register (accessible with LCR=0)
931 static void autoconfig_8250(struct uart_8250_port
*up
)
933 unsigned char scratch
, status1
, status2
;
935 up
->port
.type
= PORT_8250
;
937 scratch
= serial_in(up
, UART_SCR
);
938 serial_out(up
, UART_SCR
, 0xa5);
939 status1
= serial_in(up
, UART_SCR
);
940 serial_out(up
, UART_SCR
, 0x5a);
941 status2
= serial_in(up
, UART_SCR
);
942 serial_out(up
, UART_SCR
, scratch
);
944 if (status1
== 0xa5 && status2
== 0x5a)
945 up
->port
.type
= PORT_16450
;
948 static int broken_efr(struct uart_8250_port
*up
)
951 * Exar ST16C2550 "A2" devices incorrectly detect as
952 * having an EFR, and report an ID of 0x0201. See
953 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
955 if (autoconfig_read_divisor_id(up
) == 0x0201 && size_fifo(up
) == 16)
962 * We know that the chip has FIFOs. Does it have an EFR? The
963 * EFR is located in the same register position as the IIR and
964 * we know the top two bits of the IIR are currently set. The
965 * EFR should contain zero. Try to read the EFR.
967 static void autoconfig_16550a(struct uart_8250_port
*up
)
969 unsigned char status1
, status2
;
970 unsigned int iersave
;
972 up
->port
.type
= PORT_16550A
;
973 up
->capabilities
|= UART_CAP_FIFO
;
976 * XR17V35x UARTs have an extra divisor register, DLD
977 * that gets enabled with when DLAB is set which will
978 * cause the device to incorrectly match and assign
979 * port type to PORT_16650. The EFR for this UART is
980 * found at offset 0x09. Instead check the Deice ID (DVID)
981 * register for a 2, 4 or 8 port UART.
983 if (up
->port
.flags
& UPF_EXAR_EFR
) {
984 status1
= serial_in(up
, UART_EXAR_DVID
);
985 if (status1
== 0x82 || status1
== 0x84 || status1
== 0x88) {
986 DEBUG_AUTOCONF("Exar XR17V35x ");
987 up
->port
.type
= PORT_XR17V35X
;
988 up
->capabilities
|= UART_CAP_AFE
| UART_CAP_EFR
|
997 * Check for presence of the EFR when DLAB is set.
998 * Only ST16C650V1 UARTs pass this test.
1000 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
1001 if (serial_in(up
, UART_EFR
) == 0) {
1002 serial_out(up
, UART_EFR
, 0xA8);
1003 if (serial_in(up
, UART_EFR
) != 0) {
1004 DEBUG_AUTOCONF("EFRv1 ");
1005 up
->port
.type
= PORT_16650
;
1006 up
->capabilities
|= UART_CAP_EFR
| UART_CAP_SLEEP
;
1008 serial_out(up
, UART_LCR
, 0);
1009 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
|
1011 status1
= serial_in(up
, UART_IIR
) >> 5;
1012 serial_out(up
, UART_FCR
, 0);
1013 serial_out(up
, UART_LCR
, 0);
1016 up
->port
.type
= PORT_16550A_FSL64
;
1018 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1020 serial_out(up
, UART_EFR
, 0);
1025 * Maybe it requires 0xbf to be written to the LCR.
1026 * (other ST16C650V2 UARTs, TI16C752A, etc)
1028 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
1029 if (serial_in(up
, UART_EFR
) == 0 && !broken_efr(up
)) {
1030 DEBUG_AUTOCONF("EFRv2 ");
1031 autoconfig_has_efr(up
);
1036 * Check for a National Semiconductor SuperIO chip.
1037 * Attempt to switch to bank 2, read the value of the LOOP bit
1038 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1039 * switch back to bank 2, read it from EXCR1 again and check
1040 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1042 serial_out(up
, UART_LCR
, 0);
1043 status1
= serial8250_in_MCR(up
);
1044 serial_out(up
, UART_LCR
, 0xE0);
1045 status2
= serial_in(up
, 0x02); /* EXCR1 */
1047 if (!((status2
^ status1
) & UART_MCR_LOOP
)) {
1048 serial_out(up
, UART_LCR
, 0);
1049 serial8250_out_MCR(up
, status1
^ UART_MCR_LOOP
);
1050 serial_out(up
, UART_LCR
, 0xE0);
1051 status2
= serial_in(up
, 0x02); /* EXCR1 */
1052 serial_out(up
, UART_LCR
, 0);
1053 serial8250_out_MCR(up
, status1
);
1055 if ((status2
^ status1
) & UART_MCR_LOOP
) {
1056 unsigned short quot
;
1058 serial_out(up
, UART_LCR
, 0xE0);
1060 quot
= serial_dl_read(up
);
1063 if (ns16550a_goto_highspeed(up
))
1064 serial_dl_write(up
, quot
);
1066 serial_out(up
, UART_LCR
, 0);
1068 up
->port
.uartclk
= 921600*16;
1069 up
->port
.type
= PORT_NS16550A
;
1070 up
->capabilities
|= UART_NATSEMI
;
1076 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1077 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1078 * Try setting it with and without DLAB set. Cheap clones
1079 * set bit 5 without DLAB set.
1081 serial_out(up
, UART_LCR
, 0);
1082 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
| UART_FCR7_64BYTE
);
1083 status1
= serial_in(up
, UART_IIR
) >> 5;
1084 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
);
1085 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
1086 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
| UART_FCR7_64BYTE
);
1087 status2
= serial_in(up
, UART_IIR
) >> 5;
1088 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
);
1089 serial_out(up
, UART_LCR
, 0);
1091 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1
, status2
);
1093 if (status1
== 6 && status2
== 7) {
1094 up
->port
.type
= PORT_16750
;
1095 up
->capabilities
|= UART_CAP_AFE
| UART_CAP_SLEEP
;
1100 * Try writing and reading the UART_IER_UUE bit (b6).
1101 * If it works, this is probably one of the Xscale platform's
1103 * We're going to explicitly set the UUE bit to 0 before
1104 * trying to write and read a 1 just to make sure it's not
1105 * already a 1 and maybe locked there before we even start start.
1107 iersave
= serial_in(up
, UART_IER
);
1108 serial_out(up
, UART_IER
, iersave
& ~UART_IER_UUE
);
1109 if (!(serial_in(up
, UART_IER
) & UART_IER_UUE
)) {
1111 * OK it's in a known zero state, try writing and reading
1112 * without disturbing the current state of the other bits.
1114 serial_out(up
, UART_IER
, iersave
| UART_IER_UUE
);
1115 if (serial_in(up
, UART_IER
) & UART_IER_UUE
) {
1118 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1120 DEBUG_AUTOCONF("Xscale ");
1121 up
->port
.type
= PORT_XSCALE
;
1122 up
->capabilities
|= UART_CAP_UUE
| UART_CAP_RTOIE
;
1127 * If we got here we couldn't force the IER_UUE bit to 0.
1128 * Log it and continue.
1130 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1132 serial_out(up
, UART_IER
, iersave
);
1135 * Exar uarts have EFR in a weird location
1137 if (up
->port
.flags
& UPF_EXAR_EFR
) {
1138 DEBUG_AUTOCONF("Exar XR17D15x ");
1139 up
->port
.type
= PORT_XR17D15X
;
1140 up
->capabilities
|= UART_CAP_AFE
| UART_CAP_EFR
|
1147 * We distinguish between 16550A and U6 16550A by counting
1148 * how many bytes are in the FIFO.
1150 if (up
->port
.type
== PORT_16550A
&& size_fifo(up
) == 64) {
1151 up
->port
.type
= PORT_U6_16550A
;
1152 up
->capabilities
|= UART_CAP_AFE
;
1157 * This routine is called by rs_init() to initialize a specific serial
1158 * port. It determines what type of UART chip this serial port is
1159 * using: 8250, 16450, 16550, 16550A. The important question is
1160 * whether or not this UART is a 16550A or not, since this will
1161 * determine whether or not we can use its FIFO features or not.
1163 static void autoconfig(struct uart_8250_port
*up
)
1165 unsigned char status1
, scratch
, scratch2
, scratch3
;
1166 unsigned char save_lcr
, save_mcr
;
1167 struct uart_port
*port
= &up
->port
;
1168 unsigned long flags
;
1169 unsigned int old_capabilities
;
1171 if (!port
->iobase
&& !port
->mapbase
&& !port
->membase
)
1174 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1175 serial_index(port
), port
->iobase
, port
->membase
);
1178 * We really do need global IRQs disabled here - we're going to
1179 * be frobbing the chips IRQ enable register to see if it exists.
1181 spin_lock_irqsave(&port
->lock
, flags
);
1183 up
->capabilities
= 0;
1186 if (!(port
->flags
& UPF_BUGGY_UART
)) {
1188 * Do a simple existence test first; if we fail this,
1189 * there's no point trying anything else.
1191 * 0x80 is used as a nonsense port to prevent against
1192 * false positives due to ISA bus float. The
1193 * assumption is that 0x80 is a non-existent port;
1194 * which should be safe since include/asm/io.h also
1195 * makes this assumption.
1197 * Note: this is safe as long as MCR bit 4 is clear
1198 * and the device is in "PC" mode.
1200 scratch
= serial_in(up
, UART_IER
);
1201 serial_out(up
, UART_IER
, 0);
1206 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1207 * 16C754B) allow only to modify them if an EFR bit is set.
1209 scratch2
= serial_in(up
, UART_IER
) & 0x0f;
1210 serial_out(up
, UART_IER
, 0x0F);
1214 scratch3
= serial_in(up
, UART_IER
) & 0x0f;
1215 serial_out(up
, UART_IER
, scratch
);
1216 if (scratch2
!= 0 || scratch3
!= 0x0F) {
1218 * We failed; there's nothing here
1220 spin_unlock_irqrestore(&port
->lock
, flags
);
1221 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1222 scratch2
, scratch3
);
1227 save_mcr
= serial8250_in_MCR(up
);
1228 save_lcr
= serial_in(up
, UART_LCR
);
1231 * Check to see if a UART is really there. Certain broken
1232 * internal modems based on the Rockwell chipset fail this
1233 * test, because they apparently don't implement the loopback
1234 * test mode. So this test is skipped on the COM 1 through
1235 * COM 4 ports. This *should* be safe, since no board
1236 * manufacturer would be stupid enough to design a board
1237 * that conflicts with COM 1-4 --- we hope!
1239 if (!(port
->flags
& UPF_SKIP_TEST
)) {
1240 serial8250_out_MCR(up
, UART_MCR_LOOP
| 0x0A);
1241 status1
= serial_in(up
, UART_MSR
) & 0xF0;
1242 serial8250_out_MCR(up
, save_mcr
);
1243 if (status1
!= 0x90) {
1244 spin_unlock_irqrestore(&port
->lock
, flags
);
1245 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1252 * We're pretty sure there's a port here. Lets find out what
1253 * type of port it is. The IIR top two bits allows us to find
1254 * out if it's 8250 or 16450, 16550, 16550A or later. This
1255 * determines what we test for next.
1257 * We also initialise the EFR (if any) to zero for later. The
1258 * EFR occupies the same register location as the FCR and IIR.
1260 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
1261 serial_out(up
, UART_EFR
, 0);
1262 serial_out(up
, UART_LCR
, 0);
1264 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
);
1265 scratch
= serial_in(up
, UART_IIR
) >> 6;
1269 autoconfig_8250(up
);
1272 port
->type
= PORT_UNKNOWN
;
1275 port
->type
= PORT_16550
;
1278 autoconfig_16550a(up
);
1282 #ifdef CONFIG_SERIAL_8250_RSA
1284 * Only probe for RSA ports if we got the region.
1286 if (port
->type
== PORT_16550A
&& up
->probe
& UART_PROBE_RSA
&&
1288 port
->type
= PORT_RSA
;
1291 serial_out(up
, UART_LCR
, save_lcr
);
1293 port
->fifosize
= uart_config
[up
->port
.type
].fifo_size
;
1294 old_capabilities
= up
->capabilities
;
1295 up
->capabilities
= uart_config
[port
->type
].flags
;
1296 up
->tx_loadsz
= uart_config
[port
->type
].tx_loadsz
;
1298 if (port
->type
== PORT_UNKNOWN
)
1304 #ifdef CONFIG_SERIAL_8250_RSA
1305 if (port
->type
== PORT_RSA
)
1306 serial_out(up
, UART_RSA_FRR
, 0);
1308 serial8250_out_MCR(up
, save_mcr
);
1309 serial8250_clear_fifos(up
);
1310 serial_in(up
, UART_RX
);
1311 if (up
->capabilities
& UART_CAP_UUE
)
1312 serial_out(up
, UART_IER
, UART_IER_UUE
);
1314 serial_out(up
, UART_IER
, 0);
1317 spin_unlock_irqrestore(&port
->lock
, flags
);
1320 * Check if the device is a Fintek F81216A
1322 if (port
->type
== PORT_16550A
)
1323 fintek_8250_probe(up
);
1325 if (up
->capabilities
!= old_capabilities
) {
1326 pr_warn("ttyS%d: detected caps %08x should be %08x\n",
1327 serial_index(port
), old_capabilities
,
1331 DEBUG_AUTOCONF("iir=%d ", scratch
);
1332 DEBUG_AUTOCONF("type=%s\n", uart_config
[port
->type
].name
);
1335 static void autoconfig_irq(struct uart_8250_port
*up
)
1337 struct uart_port
*port
= &up
->port
;
1338 unsigned char save_mcr
, save_ier
;
1339 unsigned char save_ICP
= 0;
1340 unsigned int ICP
= 0;
1344 if (port
->flags
& UPF_FOURPORT
) {
1345 ICP
= (port
->iobase
& 0xfe0) | 0x1f;
1346 save_ICP
= inb_p(ICP
);
1351 if (uart_console(port
))
1354 /* forget possible initially masked and pending IRQ */
1355 probe_irq_off(probe_irq_on());
1356 save_mcr
= serial8250_in_MCR(up
);
1357 save_ier
= serial_in(up
, UART_IER
);
1358 serial8250_out_MCR(up
, UART_MCR_OUT1
| UART_MCR_OUT2
);
1360 irqs
= probe_irq_on();
1361 serial8250_out_MCR(up
, 0);
1363 if (port
->flags
& UPF_FOURPORT
) {
1364 serial8250_out_MCR(up
, UART_MCR_DTR
| UART_MCR_RTS
);
1366 serial8250_out_MCR(up
,
1367 UART_MCR_DTR
| UART_MCR_RTS
| UART_MCR_OUT2
);
1369 serial_out(up
, UART_IER
, 0x0f); /* enable all intrs */
1370 serial_in(up
, UART_LSR
);
1371 serial_in(up
, UART_RX
);
1372 serial_in(up
, UART_IIR
);
1373 serial_in(up
, UART_MSR
);
1374 serial_out(up
, UART_TX
, 0xFF);
1376 irq
= probe_irq_off(irqs
);
1378 serial8250_out_MCR(up
, save_mcr
);
1379 serial_out(up
, UART_IER
, save_ier
);
1381 if (port
->flags
& UPF_FOURPORT
)
1382 outb_p(save_ICP
, ICP
);
1384 if (uart_console(port
))
1387 port
->irq
= (irq
> 0) ? irq
: 0;
1390 static void serial8250_stop_rx(struct uart_port
*port
)
1392 struct uart_8250_port
*up
= up_to_u8250p(port
);
1394 serial8250_rpm_get(up
);
1396 up
->ier
&= ~(UART_IER_RLSI
| UART_IER_RDI
);
1397 up
->port
.read_status_mask
&= ~UART_LSR_DR
;
1398 serial_port_out(port
, UART_IER
, up
->ier
);
1400 serial8250_rpm_put(up
);
1403 static void __do_stop_tx_rs485(struct uart_8250_port
*p
)
1408 serial8250_em485_rts_after_send(p
);
1410 * Empty the RX FIFO, we are not interested in anything
1411 * received during the half-duplex transmission.
1412 * Enable previously disabled RX interrupts.
1414 if (!(p
->port
.rs485
.flags
& SER_RS485_RX_DURING_TX
)) {
1415 serial8250_clear_fifos(p
);
1417 serial8250_rpm_get(p
);
1419 p
->ier
|= UART_IER_RLSI
| UART_IER_RDI
;
1420 serial_port_out(&p
->port
, UART_IER
, p
->ier
);
1422 serial8250_rpm_put(p
);
1426 static void serial8250_em485_handle_stop_tx(unsigned long arg
)
1428 struct uart_8250_port
*p
= (struct uart_8250_port
*)arg
;
1429 struct uart_8250_em485
*em485
= p
->em485
;
1430 unsigned long flags
;
1432 spin_lock_irqsave(&p
->port
.lock
, flags
);
1434 em485
->active_timer
== &em485
->stop_tx_timer
) {
1435 __do_stop_tx_rs485(p
);
1436 em485
->active_timer
= NULL
;
1438 spin_unlock_irqrestore(&p
->port
.lock
, flags
);
1441 static void __stop_tx_rs485(struct uart_8250_port
*p
)
1443 struct uart_8250_em485
*em485
= p
->em485
;
1449 * __do_stop_tx_rs485 is going to set RTS according to config
1450 * AND flush RX FIFO if required.
1452 if (p
->port
.rs485
.delay_rts_after_send
> 0) {
1453 em485
->active_timer
= &em485
->stop_tx_timer
;
1454 mod_timer(&em485
->stop_tx_timer
, jiffies
+
1455 p
->port
.rs485
.delay_rts_after_send
* HZ
/ 1000);
1457 __do_stop_tx_rs485(p
);
1461 static inline void __do_stop_tx(struct uart_8250_port
*p
)
1463 if (p
->ier
& UART_IER_THRI
) {
1464 p
->ier
&= ~UART_IER_THRI
;
1465 serial_out(p
, UART_IER
, p
->ier
);
1466 serial8250_rpm_put_tx(p
);
1470 static inline void __stop_tx(struct uart_8250_port
*p
)
1472 struct uart_8250_em485
*em485
= p
->em485
;
1475 unsigned char lsr
= serial_in(p
, UART_LSR
);
1477 * To provide required timeing and allow FIFO transfer,
1478 * __stop_tx_rs485 must be called only when both FIFO and
1479 * shift register are empty. It is for device driver to enable
1480 * interrupt on TEMT.
1482 if ((lsr
& BOTH_EMPTY
) != BOTH_EMPTY
)
1485 del_timer(&em485
->start_tx_timer
);
1486 em485
->active_timer
= NULL
;
1492 static void serial8250_stop_tx(struct uart_port
*port
)
1494 struct uart_8250_port
*up
= up_to_u8250p(port
);
1496 serial8250_rpm_get(up
);
1500 * We really want to stop the transmitter from sending.
1502 if (port
->type
== PORT_16C950
) {
1503 up
->acr
|= UART_ACR_TXDIS
;
1504 serial_icr_write(up
, UART_ACR
, up
->acr
);
1506 serial8250_rpm_put(up
);
1509 static inline void __start_tx(struct uart_port
*port
)
1511 struct uart_8250_port
*up
= up_to_u8250p(port
);
1513 if (up
->dma
&& !up
->dma
->tx_dma(up
))
1516 if (!(up
->ier
& UART_IER_THRI
)) {
1517 up
->ier
|= UART_IER_THRI
;
1518 serial_port_out(port
, UART_IER
, up
->ier
);
1520 if (up
->bugs
& UART_BUG_TXEN
) {
1523 lsr
= serial_in(up
, UART_LSR
);
1524 up
->lsr_saved_flags
|= lsr
& LSR_SAVE_FLAGS
;
1525 if (lsr
& UART_LSR_THRE
)
1526 serial8250_tx_chars(up
);
1531 * Re-enable the transmitter if we disabled it.
1533 if (port
->type
== PORT_16C950
&& up
->acr
& UART_ACR_TXDIS
) {
1534 up
->acr
&= ~UART_ACR_TXDIS
;
1535 serial_icr_write(up
, UART_ACR
, up
->acr
);
1539 static inline void start_tx_rs485(struct uart_port
*port
)
1541 struct uart_8250_port
*up
= up_to_u8250p(port
);
1542 struct uart_8250_em485
*em485
= up
->em485
;
1545 if (!(up
->port
.rs485
.flags
& SER_RS485_RX_DURING_TX
))
1546 serial8250_stop_rx(&up
->port
);
1548 del_timer(&em485
->stop_tx_timer
);
1549 em485
->active_timer
= NULL
;
1551 mcr
= serial8250_in_MCR(up
);
1552 if (!!(up
->port
.rs485
.flags
& SER_RS485_RTS_ON_SEND
) !=
1553 !!(mcr
& UART_MCR_RTS
)) {
1554 if (up
->port
.rs485
.flags
& SER_RS485_RTS_ON_SEND
)
1555 mcr
|= UART_MCR_RTS
;
1557 mcr
&= ~UART_MCR_RTS
;
1558 serial8250_out_MCR(up
, mcr
);
1560 if (up
->port
.rs485
.delay_rts_before_send
> 0) {
1561 em485
->active_timer
= &em485
->start_tx_timer
;
1562 mod_timer(&em485
->start_tx_timer
, jiffies
+
1563 up
->port
.rs485
.delay_rts_before_send
* HZ
/ 1000);
1571 static void serial8250_em485_handle_start_tx(unsigned long arg
)
1573 struct uart_8250_port
*p
= (struct uart_8250_port
*)arg
;
1574 struct uart_8250_em485
*em485
= p
->em485
;
1575 unsigned long flags
;
1577 spin_lock_irqsave(&p
->port
.lock
, flags
);
1579 em485
->active_timer
== &em485
->start_tx_timer
) {
1580 __start_tx(&p
->port
);
1581 em485
->active_timer
= NULL
;
1583 spin_unlock_irqrestore(&p
->port
.lock
, flags
);
1586 static void serial8250_start_tx(struct uart_port
*port
)
1588 struct uart_8250_port
*up
= up_to_u8250p(port
);
1589 struct uart_8250_em485
*em485
= up
->em485
;
1591 serial8250_rpm_get_tx(up
);
1594 em485
->active_timer
== &em485
->start_tx_timer
)
1598 start_tx_rs485(port
);
1603 static void serial8250_throttle(struct uart_port
*port
)
1605 port
->throttle(port
);
1608 static void serial8250_unthrottle(struct uart_port
*port
)
1610 port
->unthrottle(port
);
1613 static void serial8250_disable_ms(struct uart_port
*port
)
1615 struct uart_8250_port
*up
= up_to_u8250p(port
);
1617 /* no MSR capabilities */
1618 if (up
->bugs
& UART_BUG_NOMSR
)
1621 mctrl_gpio_disable_ms(up
->gpios
);
1623 up
->ier
&= ~UART_IER_MSI
;
1624 serial_port_out(port
, UART_IER
, up
->ier
);
1627 static void serial8250_enable_ms(struct uart_port
*port
)
1629 struct uart_8250_port
*up
= up_to_u8250p(port
);
1631 /* no MSR capabilities */
1632 if (up
->bugs
& UART_BUG_NOMSR
)
1635 mctrl_gpio_enable_ms(up
->gpios
);
1637 up
->ier
|= UART_IER_MSI
;
1639 serial8250_rpm_get(up
);
1640 serial_port_out(port
, UART_IER
, up
->ier
);
1641 serial8250_rpm_put(up
);
1644 static void serial8250_read_char(struct uart_8250_port
*up
, unsigned char lsr
)
1646 struct uart_port
*port
= &up
->port
;
1648 char flag
= TTY_NORMAL
;
1650 if (likely(lsr
& UART_LSR_DR
))
1651 ch
= serial_in(up
, UART_RX
);
1654 * Intel 82571 has a Serial Over Lan device that will
1655 * set UART_LSR_BI without setting UART_LSR_DR when
1656 * it receives a break. To avoid reading from the
1657 * receive buffer without UART_LSR_DR bit set, we
1658 * just force the read character to be 0
1664 lsr
|= up
->lsr_saved_flags
;
1665 up
->lsr_saved_flags
= 0;
1667 if (unlikely(lsr
& UART_LSR_BRK_ERROR_BITS
)) {
1668 if (lsr
& UART_LSR_BI
) {
1669 lsr
&= ~(UART_LSR_FE
| UART_LSR_PE
);
1672 * We do the SysRQ and SAK checking
1673 * here because otherwise the break
1674 * may get masked by ignore_status_mask
1675 * or read_status_mask.
1677 if (uart_handle_break(port
))
1679 } else if (lsr
& UART_LSR_PE
)
1680 port
->icount
.parity
++;
1681 else if (lsr
& UART_LSR_FE
)
1682 port
->icount
.frame
++;
1683 if (lsr
& UART_LSR_OE
)
1684 port
->icount
.overrun
++;
1687 * Mask off conditions which should be ignored.
1689 lsr
&= port
->read_status_mask
;
1691 if (lsr
& UART_LSR_BI
) {
1692 pr_debug("%s: handling break\n", __func__
);
1694 } else if (lsr
& UART_LSR_PE
)
1696 else if (lsr
& UART_LSR_FE
)
1699 if (uart_handle_sysrq_char(port
, ch
))
1702 uart_insert_char(port
, lsr
, UART_LSR_OE
, ch
, flag
);
1706 * serial8250_rx_chars: processes according to the passed in LSR
1707 * value, and returns the remaining LSR bits not handled
1708 * by this Rx routine.
1710 unsigned char serial8250_rx_chars(struct uart_8250_port
*up
, unsigned char lsr
)
1712 struct uart_port
*port
= &up
->port
;
1713 int max_count
= 256;
1716 serial8250_read_char(up
, lsr
);
1717 if (--max_count
== 0)
1719 lsr
= serial_in(up
, UART_LSR
);
1720 } while (lsr
& (UART_LSR_DR
| UART_LSR_BI
));
1722 tty_flip_buffer_push(&port
->state
->port
);
1725 EXPORT_SYMBOL_GPL(serial8250_rx_chars
);
1727 void serial8250_tx_chars(struct uart_8250_port
*up
)
1729 struct uart_port
*port
= &up
->port
;
1730 struct circ_buf
*xmit
= &port
->state
->xmit
;
1734 serial_out(up
, UART_TX
, port
->x_char
);
1739 if (uart_tx_stopped(port
)) {
1740 serial8250_stop_tx(port
);
1743 if (uart_circ_empty(xmit
)) {
1748 count
= up
->tx_loadsz
;
1750 serial_out(up
, UART_TX
, xmit
->buf
[xmit
->tail
]);
1751 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
1753 if (uart_circ_empty(xmit
))
1755 if ((up
->capabilities
& UART_CAP_HFIFO
) &&
1756 (serial_in(up
, UART_LSR
) & BOTH_EMPTY
) != BOTH_EMPTY
)
1758 } while (--count
> 0);
1760 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
1761 uart_write_wakeup(port
);
1763 pr_debug("%s: THRE\n", __func__
);
1766 * With RPM enabled, we have to wait until the FIFO is empty before the
1767 * HW can go idle. So we get here once again with empty FIFO and disable
1768 * the interrupt and RPM in __stop_tx()
1770 if (uart_circ_empty(xmit
) && !(up
->capabilities
& UART_CAP_RPM
))
1773 EXPORT_SYMBOL_GPL(serial8250_tx_chars
);
1775 /* Caller holds uart port lock */
1776 unsigned int serial8250_modem_status(struct uart_8250_port
*up
)
1778 struct uart_port
*port
= &up
->port
;
1779 unsigned int status
= serial_in(up
, UART_MSR
);
1781 status
|= up
->msr_saved_flags
;
1782 up
->msr_saved_flags
= 0;
1783 if (status
& UART_MSR_ANY_DELTA
&& up
->ier
& UART_IER_MSI
&&
1784 port
->state
!= NULL
) {
1785 if (status
& UART_MSR_TERI
)
1787 if (status
& UART_MSR_DDSR
)
1789 if (status
& UART_MSR_DDCD
)
1790 uart_handle_dcd_change(port
, status
& UART_MSR_DCD
);
1791 if (status
& UART_MSR_DCTS
)
1792 uart_handle_cts_change(port
, status
& UART_MSR_CTS
);
1794 wake_up_interruptible(&port
->state
->port
.delta_msr_wait
);
1799 EXPORT_SYMBOL_GPL(serial8250_modem_status
);
1801 static bool handle_rx_dma(struct uart_8250_port
*up
, unsigned int iir
)
1803 switch (iir
& 0x3f) {
1804 case UART_IIR_RX_TIMEOUT
:
1805 serial8250_rx_dma_flush(up
);
1810 return up
->dma
->rx_dma(up
);
1814 * This handles the interrupt from one port.
1816 int serial8250_handle_irq(struct uart_port
*port
, unsigned int iir
)
1818 unsigned char status
;
1819 unsigned long flags
;
1820 struct uart_8250_port
*up
= up_to_u8250p(port
);
1822 if (iir
& UART_IIR_NO_INT
)
1825 spin_lock_irqsave(&port
->lock
, flags
);
1827 status
= serial_port_in(port
, UART_LSR
);
1829 pr_debug("%s: status = %x\n", __func__
, status
);
1831 if (status
& (UART_LSR_DR
| UART_LSR_BI
)) {
1832 if (!up
->dma
|| handle_rx_dma(up
, iir
))
1833 status
= serial8250_rx_chars(up
, status
);
1835 serial8250_modem_status(up
);
1836 if ((!up
->dma
|| up
->dma
->tx_err
) && (status
& UART_LSR_THRE
))
1837 serial8250_tx_chars(up
);
1839 spin_unlock_irqrestore(&port
->lock
, flags
);
1842 EXPORT_SYMBOL_GPL(serial8250_handle_irq
);
1844 static int serial8250_default_handle_irq(struct uart_port
*port
)
1846 struct uart_8250_port
*up
= up_to_u8250p(port
);
1850 serial8250_rpm_get(up
);
1852 iir
= serial_port_in(port
, UART_IIR
);
1853 ret
= serial8250_handle_irq(port
, iir
);
1855 serial8250_rpm_put(up
);
1860 * These Exar UARTs have an extra interrupt indicator that could
1861 * fire for a few unimplemented interrupts. One of which is a
1862 * wakeup event when coming out of sleep. Put this here just
1863 * to be on the safe side that these interrupts don't go unhandled.
1865 static int exar_handle_irq(struct uart_port
*port
)
1867 unsigned int iir
= serial_port_in(port
, UART_IIR
);
1870 ret
= serial8250_handle_irq(port
, iir
);
1872 if ((port
->type
== PORT_XR17V35X
) ||
1873 (port
->type
== PORT_XR17D15X
)) {
1874 serial_port_in(port
, 0x80);
1875 serial_port_in(port
, 0x81);
1876 serial_port_in(port
, 0x82);
1877 serial_port_in(port
, 0x83);
1883 static unsigned int serial8250_tx_empty(struct uart_port
*port
)
1885 struct uart_8250_port
*up
= up_to_u8250p(port
);
1886 unsigned long flags
;
1889 serial8250_rpm_get(up
);
1891 spin_lock_irqsave(&port
->lock
, flags
);
1892 lsr
= serial_port_in(port
, UART_LSR
);
1893 up
->lsr_saved_flags
|= lsr
& LSR_SAVE_FLAGS
;
1894 spin_unlock_irqrestore(&port
->lock
, flags
);
1896 serial8250_rpm_put(up
);
1898 return (lsr
& BOTH_EMPTY
) == BOTH_EMPTY
? TIOCSER_TEMT
: 0;
1901 unsigned int serial8250_do_get_mctrl(struct uart_port
*port
)
1903 struct uart_8250_port
*up
= up_to_u8250p(port
);
1904 unsigned int status
;
1907 serial8250_rpm_get(up
);
1908 status
= serial8250_modem_status(up
);
1909 serial8250_rpm_put(up
);
1912 if (status
& UART_MSR_DCD
)
1914 if (status
& UART_MSR_RI
)
1916 if (status
& UART_MSR_DSR
)
1918 if (status
& UART_MSR_CTS
)
1921 return mctrl_gpio_get(up
->gpios
, &ret
);
1923 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl
);
1925 static unsigned int serial8250_get_mctrl(struct uart_port
*port
)
1927 if (port
->get_mctrl
)
1928 return port
->get_mctrl(port
);
1929 return serial8250_do_get_mctrl(port
);
1932 void serial8250_do_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1934 struct uart_8250_port
*up
= up_to_u8250p(port
);
1935 unsigned char mcr
= 0;
1937 if (mctrl
& TIOCM_RTS
)
1938 mcr
|= UART_MCR_RTS
;
1939 if (mctrl
& TIOCM_DTR
)
1940 mcr
|= UART_MCR_DTR
;
1941 if (mctrl
& TIOCM_OUT1
)
1942 mcr
|= UART_MCR_OUT1
;
1943 if (mctrl
& TIOCM_OUT2
)
1944 mcr
|= UART_MCR_OUT2
;
1945 if (mctrl
& TIOCM_LOOP
)
1946 mcr
|= UART_MCR_LOOP
;
1948 mcr
= (mcr
& up
->mcr_mask
) | up
->mcr_force
| up
->mcr
;
1950 serial8250_out_MCR(up
, mcr
);
1952 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl
);
1954 static void serial8250_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1956 if (port
->set_mctrl
)
1957 port
->set_mctrl(port
, mctrl
);
1959 serial8250_do_set_mctrl(port
, mctrl
);
1962 static void serial8250_break_ctl(struct uart_port
*port
, int break_state
)
1964 struct uart_8250_port
*up
= up_to_u8250p(port
);
1965 unsigned long flags
;
1967 serial8250_rpm_get(up
);
1968 spin_lock_irqsave(&port
->lock
, flags
);
1969 if (break_state
== -1)
1970 up
->lcr
|= UART_LCR_SBC
;
1972 up
->lcr
&= ~UART_LCR_SBC
;
1973 serial_port_out(port
, UART_LCR
, up
->lcr
);
1974 spin_unlock_irqrestore(&port
->lock
, flags
);
1975 serial8250_rpm_put(up
);
1979 * Wait for transmitter & holding register to empty
1981 static void wait_for_xmitr(struct uart_8250_port
*up
, int bits
)
1983 unsigned int status
, tmout
= 10000;
1985 /* Wait up to 10ms for the character(s) to be sent. */
1987 status
= serial_in(up
, UART_LSR
);
1989 up
->lsr_saved_flags
|= status
& LSR_SAVE_FLAGS
;
1991 if ((status
& bits
) == bits
)
1998 /* Wait up to 1s for flow control if necessary */
1999 if (up
->port
.flags
& UPF_CONS_FLOW
) {
2000 for (tmout
= 1000000; tmout
; tmout
--) {
2001 unsigned int msr
= serial_in(up
, UART_MSR
);
2002 up
->msr_saved_flags
|= msr
& MSR_SAVE_FLAGS
;
2003 if (msr
& UART_MSR_CTS
)
2006 touch_nmi_watchdog();
2011 #ifdef CONFIG_CONSOLE_POLL
2013 * Console polling routines for writing and reading from the uart while
2014 * in an interrupt or debug context.
2017 static int serial8250_get_poll_char(struct uart_port
*port
)
2019 struct uart_8250_port
*up
= up_to_u8250p(port
);
2023 serial8250_rpm_get(up
);
2025 lsr
= serial_port_in(port
, UART_LSR
);
2027 if (!(lsr
& UART_LSR_DR
)) {
2028 status
= NO_POLL_CHAR
;
2032 status
= serial_port_in(port
, UART_RX
);
2034 serial8250_rpm_put(up
);
2039 static void serial8250_put_poll_char(struct uart_port
*port
,
2043 struct uart_8250_port
*up
= up_to_u8250p(port
);
2045 serial8250_rpm_get(up
);
2047 * First save the IER then disable the interrupts
2049 ier
= serial_port_in(port
, UART_IER
);
2050 if (up
->capabilities
& UART_CAP_UUE
)
2051 serial_port_out(port
, UART_IER
, UART_IER_UUE
);
2053 serial_port_out(port
, UART_IER
, 0);
2055 wait_for_xmitr(up
, BOTH_EMPTY
);
2057 * Send the character out.
2059 serial_port_out(port
, UART_TX
, c
);
2062 * Finally, wait for transmitter to become empty
2063 * and restore the IER
2065 wait_for_xmitr(up
, BOTH_EMPTY
);
2066 serial_port_out(port
, UART_IER
, ier
);
2067 serial8250_rpm_put(up
);
2070 #endif /* CONFIG_CONSOLE_POLL */
2072 int serial8250_do_startup(struct uart_port
*port
)
2074 struct uart_8250_port
*up
= up_to_u8250p(port
);
2075 unsigned long flags
;
2076 unsigned char lsr
, iir
;
2079 if (!port
->fifosize
)
2080 port
->fifosize
= uart_config
[port
->type
].fifo_size
;
2082 up
->tx_loadsz
= uart_config
[port
->type
].tx_loadsz
;
2083 if (!up
->capabilities
)
2084 up
->capabilities
= uart_config
[port
->type
].flags
;
2087 if (port
->iotype
!= up
->cur_iotype
)
2088 set_io_from_upio(port
);
2090 serial8250_rpm_get(up
);
2091 if (port
->type
== PORT_16C950
) {
2092 /* Wake up and initialize UART */
2094 serial_port_out(port
, UART_LCR
, UART_LCR_CONF_MODE_B
);
2095 serial_port_out(port
, UART_EFR
, UART_EFR_ECB
);
2096 serial_port_out(port
, UART_IER
, 0);
2097 serial_port_out(port
, UART_LCR
, 0);
2098 serial_icr_write(up
, UART_CSR
, 0); /* Reset the UART */
2099 serial_port_out(port
, UART_LCR
, UART_LCR_CONF_MODE_B
);
2100 serial_port_out(port
, UART_EFR
, UART_EFR_ECB
);
2101 serial_port_out(port
, UART_LCR
, 0);
2104 #ifdef CONFIG_SERIAL_8250_RSA
2106 * If this is an RSA port, see if we can kick it up to the
2107 * higher speed clock.
2112 if (port
->type
== PORT_XR17V35X
) {
2114 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2115 * MCR [7:5] and MSR [7:0]
2117 serial_port_out(port
, UART_XR_EFR
, UART_EFR_ECB
);
2120 * Make sure all interrups are masked until initialization is
2121 * complete and the FIFOs are cleared
2123 serial_port_out(port
, UART_IER
, 0);
2127 * Clear the FIFO buffers and disable them.
2128 * (they will be reenabled in set_termios())
2130 serial8250_clear_fifos(up
);
2133 * Clear the interrupt registers.
2135 serial_port_in(port
, UART_LSR
);
2136 serial_port_in(port
, UART_RX
);
2137 serial_port_in(port
, UART_IIR
);
2138 serial_port_in(port
, UART_MSR
);
2141 * At this point, there's no way the LSR could still be 0xff;
2142 * if it is, then bail out, because there's likely no UART
2145 if (!(port
->flags
& UPF_BUGGY_UART
) &&
2146 (serial_port_in(port
, UART_LSR
) == 0xff)) {
2147 printk_ratelimited(KERN_INFO
"ttyS%d: LSR safety check engaged!\n",
2148 serial_index(port
));
2154 * For a XR16C850, we need to set the trigger levels
2156 if (port
->type
== PORT_16850
) {
2159 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
2161 fctr
= serial_in(up
, UART_FCTR
) & ~(UART_FCTR_RX
|UART_FCTR_TX
);
2162 serial_port_out(port
, UART_FCTR
,
2163 fctr
| UART_FCTR_TRGD
| UART_FCTR_RX
);
2164 serial_port_out(port
, UART_TRG
, UART_TRG_96
);
2165 serial_port_out(port
, UART_FCTR
,
2166 fctr
| UART_FCTR_TRGD
| UART_FCTR_TX
);
2167 serial_port_out(port
, UART_TRG
, UART_TRG_96
);
2169 serial_port_out(port
, UART_LCR
, 0);
2175 * Test for UARTs that do not reassert THRE when the
2176 * transmitter is idle and the interrupt has already
2177 * been cleared. Real 16550s should always reassert
2178 * this interrupt whenever the transmitter is idle and
2179 * the interrupt is enabled. Delays are necessary to
2180 * allow register changes to become visible.
2182 spin_lock_irqsave(&port
->lock
, flags
);
2183 if (up
->port
.irqflags
& IRQF_SHARED
)
2184 disable_irq_nosync(port
->irq
);
2186 wait_for_xmitr(up
, UART_LSR_THRE
);
2187 serial_port_out_sync(port
, UART_IER
, UART_IER_THRI
);
2188 udelay(1); /* allow THRE to set */
2189 iir1
= serial_port_in(port
, UART_IIR
);
2190 serial_port_out(port
, UART_IER
, 0);
2191 serial_port_out_sync(port
, UART_IER
, UART_IER_THRI
);
2192 udelay(1); /* allow a working UART time to re-assert THRE */
2193 iir
= serial_port_in(port
, UART_IIR
);
2194 serial_port_out(port
, UART_IER
, 0);
2196 if (port
->irqflags
& IRQF_SHARED
)
2197 enable_irq(port
->irq
);
2198 spin_unlock_irqrestore(&port
->lock
, flags
);
2201 * If the interrupt is not reasserted, or we otherwise
2202 * don't trust the iir, setup a timer to kick the UART
2203 * on a regular basis.
2205 if ((!(iir1
& UART_IIR_NO_INT
) && (iir
& UART_IIR_NO_INT
)) ||
2206 up
->port
.flags
& UPF_BUG_THRE
) {
2207 up
->bugs
|= UART_BUG_THRE
;
2211 retval
= up
->ops
->setup_irq(up
);
2216 * Now, initialize the UART
2218 serial_port_out(port
, UART_LCR
, UART_LCR_WLEN8
);
2220 spin_lock_irqsave(&port
->lock
, flags
);
2221 if (up
->port
.flags
& UPF_FOURPORT
) {
2223 up
->port
.mctrl
|= TIOCM_OUT1
;
2226 * Most PC uarts need OUT2 raised to enable interrupts.
2229 up
->port
.mctrl
|= TIOCM_OUT2
;
2231 serial8250_set_mctrl(port
, port
->mctrl
);
2234 * Serial over Lan (SoL) hack:
2235 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2236 * used for Serial Over Lan. Those chips take a longer time than a
2237 * normal serial device to signalize that a transmission data was
2238 * queued. Due to that, the above test generally fails. One solution
2239 * would be to delay the reading of iir. However, this is not
2240 * reliable, since the timeout is variable. So, let's just don't
2241 * test if we receive TX irq. This way, we'll never enable
2244 if (up
->port
.flags
& UPF_NO_TXEN_TEST
)
2245 goto dont_test_tx_en
;
2248 * Do a quick test to see if we receive an interrupt when we enable
2251 serial_port_out(port
, UART_IER
, UART_IER_THRI
);
2252 lsr
= serial_port_in(port
, UART_LSR
);
2253 iir
= serial_port_in(port
, UART_IIR
);
2254 serial_port_out(port
, UART_IER
, 0);
2256 if (lsr
& UART_LSR_TEMT
&& iir
& UART_IIR_NO_INT
) {
2257 if (!(up
->bugs
& UART_BUG_TXEN
)) {
2258 up
->bugs
|= UART_BUG_TXEN
;
2259 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2260 serial_index(port
));
2263 up
->bugs
&= ~UART_BUG_TXEN
;
2267 spin_unlock_irqrestore(&port
->lock
, flags
);
2270 * Clear the interrupt registers again for luck, and clear the
2271 * saved flags to avoid getting false values from polling
2272 * routines or the previous session.
2274 serial_port_in(port
, UART_LSR
);
2275 serial_port_in(port
, UART_RX
);
2276 serial_port_in(port
, UART_IIR
);
2277 serial_port_in(port
, UART_MSR
);
2278 up
->lsr_saved_flags
= 0;
2279 up
->msr_saved_flags
= 0;
2282 * Request DMA channels for both RX and TX.
2285 retval
= serial8250_request_dma(up
);
2287 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2288 serial_index(port
));
2294 * Set the IER shadow for rx interrupts but defer actual interrupt
2295 * enable until after the FIFOs are enabled; otherwise, an already-
2296 * active sender can swamp the interrupt handler with "too much work".
2298 up
->ier
= UART_IER_RLSI
| UART_IER_RDI
;
2300 if (port
->flags
& UPF_FOURPORT
) {
2303 * Enable interrupts on the AST Fourport board
2305 icp
= (port
->iobase
& 0xfe0) | 0x01f;
2311 serial8250_rpm_put(up
);
2314 EXPORT_SYMBOL_GPL(serial8250_do_startup
);
2316 static int serial8250_startup(struct uart_port
*port
)
2319 return port
->startup(port
);
2320 return serial8250_do_startup(port
);
2323 void serial8250_do_shutdown(struct uart_port
*port
)
2325 struct uart_8250_port
*up
= up_to_u8250p(port
);
2326 unsigned long flags
;
2328 serial8250_rpm_get(up
);
2330 * Disable interrupts from this port
2332 spin_lock_irqsave(&port
->lock
, flags
);
2334 serial_port_out(port
, UART_IER
, 0);
2335 spin_unlock_irqrestore(&port
->lock
, flags
);
2337 synchronize_irq(port
->irq
);
2340 serial8250_release_dma(up
);
2342 spin_lock_irqsave(&port
->lock
, flags
);
2343 if (port
->flags
& UPF_FOURPORT
) {
2344 /* reset interrupts on the AST Fourport board */
2345 inb((port
->iobase
& 0xfe0) | 0x1f);
2346 port
->mctrl
|= TIOCM_OUT1
;
2348 port
->mctrl
&= ~TIOCM_OUT2
;
2350 serial8250_set_mctrl(port
, port
->mctrl
);
2351 spin_unlock_irqrestore(&port
->lock
, flags
);
2354 * Disable break condition and FIFOs
2356 serial_port_out(port
, UART_LCR
,
2357 serial_port_in(port
, UART_LCR
) & ~UART_LCR_SBC
);
2358 serial8250_clear_fifos(up
);
2360 #ifdef CONFIG_SERIAL_8250_RSA
2362 * Reset the RSA board back to 115kbps compat mode.
2368 * Read data port to reset things, and then unlink from
2371 serial_port_in(port
, UART_RX
);
2372 serial8250_rpm_put(up
);
2374 up
->ops
->release_irq(up
);
2376 EXPORT_SYMBOL_GPL(serial8250_do_shutdown
);
2378 static void serial8250_shutdown(struct uart_port
*port
)
2381 port
->shutdown(port
);
2383 serial8250_do_shutdown(port
);
2387 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2388 * Calculate divisor with extra 4-bit fractional portion
2390 static unsigned int xr17v35x_get_divisor(struct uart_8250_port
*up
,
2394 struct uart_port
*port
= &up
->port
;
2395 unsigned int quot_16
;
2397 quot_16
= DIV_ROUND_CLOSEST(port
->uartclk
, baud
);
2398 *frac
= quot_16
& 0x0f;
2400 return quot_16
>> 4;
2403 static unsigned int serial8250_get_divisor(struct uart_8250_port
*up
,
2407 struct uart_port
*port
= &up
->port
;
2411 * Handle magic divisors for baud rates above baud_base on
2412 * SMSC SuperIO chips.
2415 if ((port
->flags
& UPF_MAGIC_MULTIPLIER
) &&
2416 baud
== (port
->uartclk
/4))
2418 else if ((port
->flags
& UPF_MAGIC_MULTIPLIER
) &&
2419 baud
== (port
->uartclk
/8))
2421 else if (up
->port
.type
== PORT_XR17V35X
)
2422 quot
= xr17v35x_get_divisor(up
, baud
, frac
);
2424 quot
= uart_get_divisor(port
, baud
);
2427 * Oxford Semi 952 rev B workaround
2429 if (up
->bugs
& UART_BUG_QUOT
&& (quot
& 0xff) == 0)
2435 static unsigned char serial8250_compute_lcr(struct uart_8250_port
*up
,
2440 switch (c_cflag
& CSIZE
) {
2442 cval
= UART_LCR_WLEN5
;
2445 cval
= UART_LCR_WLEN6
;
2448 cval
= UART_LCR_WLEN7
;
2452 cval
= UART_LCR_WLEN8
;
2456 if (c_cflag
& CSTOPB
)
2457 cval
|= UART_LCR_STOP
;
2458 if (c_cflag
& PARENB
) {
2459 cval
|= UART_LCR_PARITY
;
2460 if (up
->bugs
& UART_BUG_PARITY
)
2461 up
->fifo_bug
= true;
2463 if (!(c_cflag
& PARODD
))
2464 cval
|= UART_LCR_EPAR
;
2466 if (c_cflag
& CMSPAR
)
2467 cval
|= UART_LCR_SPAR
;
2473 static void serial8250_set_divisor(struct uart_port
*port
, unsigned int baud
,
2474 unsigned int quot
, unsigned int quot_frac
)
2476 struct uart_8250_port
*up
= up_to_u8250p(port
);
2478 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2479 if (is_omap1510_8250(up
)) {
2480 if (baud
== 115200) {
2482 serial_port_out(port
, UART_OMAP_OSC_12M_SEL
, 1);
2484 serial_port_out(port
, UART_OMAP_OSC_12M_SEL
, 0);
2488 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2489 * otherwise just set DLAB
2491 if (up
->capabilities
& UART_NATSEMI
)
2492 serial_port_out(port
, UART_LCR
, 0xe0);
2494 serial_port_out(port
, UART_LCR
, up
->lcr
| UART_LCR_DLAB
);
2496 serial_dl_write(up
, quot
);
2498 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2499 if (up
->port
.type
== PORT_XR17V35X
)
2500 serial_port_out(port
, 0x2, quot_frac
);
2503 static unsigned int serial8250_get_baud_rate(struct uart_port
*port
,
2504 struct ktermios
*termios
,
2505 struct ktermios
*old
)
2507 unsigned int tolerance
= port
->uartclk
/ 100;
2510 * Ask the core to calculate the divisor for us.
2511 * Allow 1% tolerance at the upper limit so uart clks marginally
2512 * slower than nominal still match standard baud rates without
2513 * causing transmission errors.
2515 return uart_get_baud_rate(port
, termios
, old
,
2516 port
->uartclk
/ 16 / 0xffff,
2517 (port
->uartclk
+ tolerance
) / 16);
2521 serial8250_do_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
2522 struct ktermios
*old
)
2524 struct uart_8250_port
*up
= up_to_u8250p(port
);
2526 unsigned long flags
;
2527 unsigned int baud
, quot
, frac
= 0;
2529 cval
= serial8250_compute_lcr(up
, termios
->c_cflag
);
2531 baud
= serial8250_get_baud_rate(port
, termios
, old
);
2532 quot
= serial8250_get_divisor(up
, baud
, &frac
);
2535 * Ok, we're now changing the port state. Do it with
2536 * interrupts disabled.
2538 serial8250_rpm_get(up
);
2539 spin_lock_irqsave(&port
->lock
, flags
);
2541 up
->lcr
= cval
; /* Save computed LCR */
2543 if (up
->capabilities
& UART_CAP_FIFO
&& port
->fifosize
> 1) {
2544 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2545 if ((baud
< 2400 && !up
->dma
) || up
->fifo_bug
) {
2546 up
->fcr
&= ~UART_FCR_TRIGGER_MASK
;
2547 up
->fcr
|= UART_FCR_TRIGGER_1
;
2552 * MCR-based auto flow control. When AFE is enabled, RTS will be
2553 * deasserted when the receive FIFO contains more characters than
2554 * the trigger, or the MCR RTS bit is cleared. In the case where
2555 * the remote UART is not using CTS auto flow control, we must
2556 * have sufficient FIFO entries for the latency of the remote
2557 * UART to respond. IOW, at least 32 bytes of FIFO.
2559 if (up
->capabilities
& UART_CAP_AFE
&& port
->fifosize
>= 32) {
2560 up
->mcr
&= ~UART_MCR_AFE
;
2561 if (termios
->c_cflag
& CRTSCTS
)
2562 up
->mcr
|= UART_MCR_AFE
;
2566 * Update the per-port timeout.
2568 uart_update_timeout(port
, termios
->c_cflag
, baud
);
2570 port
->read_status_mask
= UART_LSR_OE
| UART_LSR_THRE
| UART_LSR_DR
;
2571 if (termios
->c_iflag
& INPCK
)
2572 port
->read_status_mask
|= UART_LSR_FE
| UART_LSR_PE
;
2573 if (termios
->c_iflag
& (IGNBRK
| BRKINT
| PARMRK
))
2574 port
->read_status_mask
|= UART_LSR_BI
;
2577 * Characteres to ignore
2579 port
->ignore_status_mask
= 0;
2580 if (termios
->c_iflag
& IGNPAR
)
2581 port
->ignore_status_mask
|= UART_LSR_PE
| UART_LSR_FE
;
2582 if (termios
->c_iflag
& IGNBRK
) {
2583 port
->ignore_status_mask
|= UART_LSR_BI
;
2585 * If we're ignoring parity and break indicators,
2586 * ignore overruns too (for real raw support).
2588 if (termios
->c_iflag
& IGNPAR
)
2589 port
->ignore_status_mask
|= UART_LSR_OE
;
2593 * ignore all characters if CREAD is not set
2595 if ((termios
->c_cflag
& CREAD
) == 0)
2596 port
->ignore_status_mask
|= UART_LSR_DR
;
2599 * CTS flow control flag and modem status interrupts
2601 up
->ier
&= ~UART_IER_MSI
;
2602 if (!(up
->bugs
& UART_BUG_NOMSR
) &&
2603 UART_ENABLE_MS(&up
->port
, termios
->c_cflag
))
2604 up
->ier
|= UART_IER_MSI
;
2605 if (up
->capabilities
& UART_CAP_UUE
)
2606 up
->ier
|= UART_IER_UUE
;
2607 if (up
->capabilities
& UART_CAP_RTOIE
)
2608 up
->ier
|= UART_IER_RTOIE
;
2610 serial_port_out(port
, UART_IER
, up
->ier
);
2612 if (up
->capabilities
& UART_CAP_EFR
) {
2613 unsigned char efr
= 0;
2615 * TI16C752/Startech hardware flow control. FIXME:
2616 * - TI16C752 requires control thresholds to be set.
2617 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2619 if (termios
->c_cflag
& CRTSCTS
)
2620 efr
|= UART_EFR_CTS
;
2622 serial_port_out(port
, UART_LCR
, UART_LCR_CONF_MODE_B
);
2623 if (port
->flags
& UPF_EXAR_EFR
)
2624 serial_port_out(port
, UART_XR_EFR
, efr
);
2626 serial_port_out(port
, UART_EFR
, efr
);
2629 serial8250_set_divisor(port
, baud
, quot
, frac
);
2632 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2633 * is written without DLAB set, this mode will be disabled.
2635 if (port
->type
== PORT_16750
)
2636 serial_port_out(port
, UART_FCR
, up
->fcr
);
2638 serial_port_out(port
, UART_LCR
, up
->lcr
); /* reset DLAB */
2639 if (port
->type
!= PORT_16750
) {
2640 /* emulated UARTs (Lucent Venus 167x) need two steps */
2641 if (up
->fcr
& UART_FCR_ENABLE_FIFO
)
2642 serial_port_out(port
, UART_FCR
, UART_FCR_ENABLE_FIFO
);
2643 serial_port_out(port
, UART_FCR
, up
->fcr
); /* set fcr */
2645 serial8250_set_mctrl(port
, port
->mctrl
);
2646 spin_unlock_irqrestore(&port
->lock
, flags
);
2647 serial8250_rpm_put(up
);
2649 /* Don't rewrite B0 */
2650 if (tty_termios_baud_rate(termios
))
2651 tty_termios_encode_baud_rate(termios
, baud
, baud
);
2653 EXPORT_SYMBOL(serial8250_do_set_termios
);
2656 serial8250_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
2657 struct ktermios
*old
)
2659 if (port
->set_termios
)
2660 port
->set_termios(port
, termios
, old
);
2662 serial8250_do_set_termios(port
, termios
, old
);
2666 serial8250_set_ldisc(struct uart_port
*port
, struct ktermios
*termios
)
2668 if (termios
->c_line
== N_PPS
) {
2669 port
->flags
|= UPF_HARDPPS_CD
;
2670 spin_lock_irq(&port
->lock
);
2671 serial8250_enable_ms(port
);
2672 spin_unlock_irq(&port
->lock
);
2674 port
->flags
&= ~UPF_HARDPPS_CD
;
2675 if (!UART_ENABLE_MS(port
, termios
->c_cflag
)) {
2676 spin_lock_irq(&port
->lock
);
2677 serial8250_disable_ms(port
);
2678 spin_unlock_irq(&port
->lock
);
2684 void serial8250_do_pm(struct uart_port
*port
, unsigned int state
,
2685 unsigned int oldstate
)
2687 struct uart_8250_port
*p
= up_to_u8250p(port
);
2689 serial8250_set_sleep(p
, state
!= 0);
2691 EXPORT_SYMBOL(serial8250_do_pm
);
2694 serial8250_pm(struct uart_port
*port
, unsigned int state
,
2695 unsigned int oldstate
)
2698 port
->pm(port
, state
, oldstate
);
2700 serial8250_do_pm(port
, state
, oldstate
);
2703 static unsigned int serial8250_port_size(struct uart_8250_port
*pt
)
2705 if (pt
->port
.mapsize
)
2706 return pt
->port
.mapsize
;
2707 if (pt
->port
.iotype
== UPIO_AU
) {
2708 if (pt
->port
.type
== PORT_RT2880
)
2712 if (is_omap1_8250(pt
))
2713 return 0x16 << pt
->port
.regshift
;
2715 return 8 << pt
->port
.regshift
;
2719 * Resource handling.
2721 static int serial8250_request_std_resource(struct uart_8250_port
*up
)
2723 unsigned int size
= serial8250_port_size(up
);
2724 struct uart_port
*port
= &up
->port
;
2727 switch (port
->iotype
) {
2737 if (!request_mem_region(port
->mapbase
, size
, "serial")) {
2742 if (port
->flags
& UPF_IOREMAP
) {
2743 port
->membase
= ioremap_nocache(port
->mapbase
, size
);
2744 if (!port
->membase
) {
2745 release_mem_region(port
->mapbase
, size
);
2753 if (!request_region(port
->iobase
, size
, "serial"))
2760 static void serial8250_release_std_resource(struct uart_8250_port
*up
)
2762 unsigned int size
= serial8250_port_size(up
);
2763 struct uart_port
*port
= &up
->port
;
2765 switch (port
->iotype
) {
2775 if (port
->flags
& UPF_IOREMAP
) {
2776 iounmap(port
->membase
);
2777 port
->membase
= NULL
;
2780 release_mem_region(port
->mapbase
, size
);
2785 release_region(port
->iobase
, size
);
2790 static void serial8250_release_port(struct uart_port
*port
)
2792 struct uart_8250_port
*up
= up_to_u8250p(port
);
2794 serial8250_release_std_resource(up
);
2797 static int serial8250_request_port(struct uart_port
*port
)
2799 struct uart_8250_port
*up
= up_to_u8250p(port
);
2801 return serial8250_request_std_resource(up
);
2804 static int fcr_get_rxtrig_bytes(struct uart_8250_port
*up
)
2806 const struct serial8250_config
*conf_type
= &uart_config
[up
->port
.type
];
2807 unsigned char bytes
;
2809 bytes
= conf_type
->rxtrig_bytes
[UART_FCR_R_TRIG_BITS(up
->fcr
)];
2811 return bytes
? bytes
: -EOPNOTSUPP
;
2814 static int bytes_to_fcr_rxtrig(struct uart_8250_port
*up
, unsigned char bytes
)
2816 const struct serial8250_config
*conf_type
= &uart_config
[up
->port
.type
];
2819 if (!conf_type
->rxtrig_bytes
[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00
)])
2822 for (i
= 1; i
< UART_FCR_R_TRIG_MAX_STATE
; i
++) {
2823 if (bytes
< conf_type
->rxtrig_bytes
[i
])
2824 /* Use the nearest lower value */
2825 return (--i
) << UART_FCR_R_TRIG_SHIFT
;
2828 return UART_FCR_R_TRIG_11
;
2831 static int do_get_rxtrig(struct tty_port
*port
)
2833 struct uart_state
*state
= container_of(port
, struct uart_state
, port
);
2834 struct uart_port
*uport
= state
->uart_port
;
2835 struct uart_8250_port
*up
= up_to_u8250p(uport
);
2837 if (!(up
->capabilities
& UART_CAP_FIFO
) || uport
->fifosize
<= 1)
2840 return fcr_get_rxtrig_bytes(up
);
2843 static int do_serial8250_get_rxtrig(struct tty_port
*port
)
2847 mutex_lock(&port
->mutex
);
2848 rxtrig_bytes
= do_get_rxtrig(port
);
2849 mutex_unlock(&port
->mutex
);
2851 return rxtrig_bytes
;
2854 static ssize_t
serial8250_get_attr_rx_trig_bytes(struct device
*dev
,
2855 struct device_attribute
*attr
, char *buf
)
2857 struct tty_port
*port
= dev_get_drvdata(dev
);
2860 rxtrig_bytes
= do_serial8250_get_rxtrig(port
);
2861 if (rxtrig_bytes
< 0)
2862 return rxtrig_bytes
;
2864 return snprintf(buf
, PAGE_SIZE
, "%d\n", rxtrig_bytes
);
2867 static int do_set_rxtrig(struct tty_port
*port
, unsigned char bytes
)
2869 struct uart_state
*state
= container_of(port
, struct uart_state
, port
);
2870 struct uart_port
*uport
= state
->uart_port
;
2871 struct uart_8250_port
*up
= up_to_u8250p(uport
);
2874 if (!(up
->capabilities
& UART_CAP_FIFO
) || uport
->fifosize
<= 1 ||
2878 rxtrig
= bytes_to_fcr_rxtrig(up
, bytes
);
2882 serial8250_clear_fifos(up
);
2883 up
->fcr
&= ~UART_FCR_TRIGGER_MASK
;
2884 up
->fcr
|= (unsigned char)rxtrig
;
2885 serial_out(up
, UART_FCR
, up
->fcr
);
2889 static int do_serial8250_set_rxtrig(struct tty_port
*port
, unsigned char bytes
)
2893 mutex_lock(&port
->mutex
);
2894 ret
= do_set_rxtrig(port
, bytes
);
2895 mutex_unlock(&port
->mutex
);
2900 static ssize_t
serial8250_set_attr_rx_trig_bytes(struct device
*dev
,
2901 struct device_attribute
*attr
, const char *buf
, size_t count
)
2903 struct tty_port
*port
= dev_get_drvdata(dev
);
2904 unsigned char bytes
;
2910 ret
= kstrtou8(buf
, 10, &bytes
);
2914 ret
= do_serial8250_set_rxtrig(port
, bytes
);
2921 static DEVICE_ATTR(rx_trig_bytes
, S_IRUSR
| S_IWUSR
| S_IRGRP
,
2922 serial8250_get_attr_rx_trig_bytes
,
2923 serial8250_set_attr_rx_trig_bytes
);
2925 static struct attribute
*serial8250_dev_attrs
[] = {
2926 &dev_attr_rx_trig_bytes
.attr
,
2930 static struct attribute_group serial8250_dev_attr_group
= {
2931 .attrs
= serial8250_dev_attrs
,
2934 static void register_dev_spec_attr_grp(struct uart_8250_port
*up
)
2936 const struct serial8250_config
*conf_type
= &uart_config
[up
->port
.type
];
2938 if (conf_type
->rxtrig_bytes
[0])
2939 up
->port
.attr_group
= &serial8250_dev_attr_group
;
2942 static void serial8250_config_port(struct uart_port
*port
, int flags
)
2944 struct uart_8250_port
*up
= up_to_u8250p(port
);
2948 * Find the region that we can probe for. This in turn
2949 * tells us whether we can probe for the type of port.
2951 ret
= serial8250_request_std_resource(up
);
2955 if (port
->iotype
!= up
->cur_iotype
)
2956 set_io_from_upio(port
);
2958 if (flags
& UART_CONFIG_TYPE
)
2961 /* if access method is AU, it is a 16550 with a quirk */
2962 if (port
->type
== PORT_16550A
&& port
->iotype
== UPIO_AU
)
2963 up
->bugs
|= UART_BUG_NOMSR
;
2965 /* HW bugs may trigger IRQ while IIR == NO_INT */
2966 if (port
->type
== PORT_TEGRA
)
2967 up
->bugs
|= UART_BUG_NOMSR
;
2969 if (port
->type
!= PORT_UNKNOWN
&& flags
& UART_CONFIG_IRQ
)
2972 if (port
->type
== PORT_UNKNOWN
)
2973 serial8250_release_std_resource(up
);
2975 /* Fixme: probably not the best place for this */
2976 if ((port
->type
== PORT_XR17V35X
) ||
2977 (port
->type
== PORT_XR17D15X
))
2978 port
->handle_irq
= exar_handle_irq
;
2980 register_dev_spec_attr_grp(up
);
2981 up
->fcr
= uart_config
[up
->port
.type
].fcr
;
2985 serial8250_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
2987 if (ser
->irq
>= nr_irqs
|| ser
->irq
< 0 ||
2988 ser
->baud_base
< 9600 || ser
->type
< PORT_UNKNOWN
||
2989 ser
->type
>= ARRAY_SIZE(uart_config
) || ser
->type
== PORT_CIRRUS
||
2990 ser
->type
== PORT_STARTECH
)
2995 static const char *serial8250_type(struct uart_port
*port
)
2997 int type
= port
->type
;
2999 if (type
>= ARRAY_SIZE(uart_config
))
3001 return uart_config
[type
].name
;
3004 static const struct uart_ops serial8250_pops
= {
3005 .tx_empty
= serial8250_tx_empty
,
3006 .set_mctrl
= serial8250_set_mctrl
,
3007 .get_mctrl
= serial8250_get_mctrl
,
3008 .stop_tx
= serial8250_stop_tx
,
3009 .start_tx
= serial8250_start_tx
,
3010 .throttle
= serial8250_throttle
,
3011 .unthrottle
= serial8250_unthrottle
,
3012 .stop_rx
= serial8250_stop_rx
,
3013 .enable_ms
= serial8250_enable_ms
,
3014 .break_ctl
= serial8250_break_ctl
,
3015 .startup
= serial8250_startup
,
3016 .shutdown
= serial8250_shutdown
,
3017 .set_termios
= serial8250_set_termios
,
3018 .set_ldisc
= serial8250_set_ldisc
,
3019 .pm
= serial8250_pm
,
3020 .type
= serial8250_type
,
3021 .release_port
= serial8250_release_port
,
3022 .request_port
= serial8250_request_port
,
3023 .config_port
= serial8250_config_port
,
3024 .verify_port
= serial8250_verify_port
,
3025 #ifdef CONFIG_CONSOLE_POLL
3026 .poll_get_char
= serial8250_get_poll_char
,
3027 .poll_put_char
= serial8250_put_poll_char
,
3031 void serial8250_init_port(struct uart_8250_port
*up
)
3033 struct uart_port
*port
= &up
->port
;
3035 spin_lock_init(&port
->lock
);
3036 port
->ops
= &serial8250_pops
;
3038 up
->cur_iotype
= 0xFF;
3040 EXPORT_SYMBOL_GPL(serial8250_init_port
);
3042 void serial8250_set_defaults(struct uart_8250_port
*up
)
3044 struct uart_port
*port
= &up
->port
;
3046 if (up
->port
.flags
& UPF_FIXED_TYPE
) {
3047 unsigned int type
= up
->port
.type
;
3049 if (!up
->port
.fifosize
)
3050 up
->port
.fifosize
= uart_config
[type
].fifo_size
;
3052 up
->tx_loadsz
= uart_config
[type
].tx_loadsz
;
3053 if (!up
->capabilities
)
3054 up
->capabilities
= uart_config
[type
].flags
;
3057 set_io_from_upio(port
);
3059 /* default dma handlers */
3061 if (!up
->dma
->tx_dma
)
3062 up
->dma
->tx_dma
= serial8250_tx_dma
;
3063 if (!up
->dma
->rx_dma
)
3064 up
->dma
->rx_dma
= serial8250_rx_dma
;
3067 EXPORT_SYMBOL_GPL(serial8250_set_defaults
);
3069 #ifdef CONFIG_SERIAL_8250_CONSOLE
3071 static void serial8250_console_putchar(struct uart_port
*port
, int ch
)
3073 struct uart_8250_port
*up
= up_to_u8250p(port
);
3075 wait_for_xmitr(up
, UART_LSR_THRE
);
3076 serial_port_out(port
, UART_TX
, ch
);
3080 * Restore serial console when h/w power-off detected
3082 static void serial8250_console_restore(struct uart_8250_port
*up
)
3084 struct uart_port
*port
= &up
->port
;
3085 struct ktermios termios
;
3086 unsigned int baud
, quot
, frac
= 0;
3088 termios
.c_cflag
= port
->cons
->cflag
;
3089 if (port
->state
->port
.tty
&& termios
.c_cflag
== 0)
3090 termios
.c_cflag
= port
->state
->port
.tty
->termios
.c_cflag
;
3092 baud
= serial8250_get_baud_rate(port
, &termios
, NULL
);
3093 quot
= serial8250_get_divisor(up
, baud
, &frac
);
3095 serial8250_set_divisor(port
, baud
, quot
, frac
);
3096 serial_port_out(port
, UART_LCR
, up
->lcr
);
3097 serial8250_out_MCR(up
, UART_MCR_DTR
| UART_MCR_RTS
);
3101 * Print a string to the serial port trying not to disturb
3102 * any possible real use of the port...
3104 * The console_lock must be held when we get here.
3106 void serial8250_console_write(struct uart_8250_port
*up
, const char *s
,
3109 struct uart_port
*port
= &up
->port
;
3110 unsigned long flags
;
3114 touch_nmi_watchdog();
3116 serial8250_rpm_get(up
);
3120 else if (oops_in_progress
)
3121 locked
= spin_trylock_irqsave(&port
->lock
, flags
);
3123 spin_lock_irqsave(&port
->lock
, flags
);
3126 * First save the IER then disable the interrupts
3128 ier
= serial_port_in(port
, UART_IER
);
3130 if (up
->capabilities
& UART_CAP_UUE
)
3131 serial_port_out(port
, UART_IER
, UART_IER_UUE
);
3133 serial_port_out(port
, UART_IER
, 0);
3135 /* check scratch reg to see if port powered off during system sleep */
3136 if (up
->canary
&& (up
->canary
!= serial_port_in(port
, UART_SCR
))) {
3137 serial8250_console_restore(up
);
3141 uart_console_write(port
, s
, count
, serial8250_console_putchar
);
3144 * Finally, wait for transmitter to become empty
3145 * and restore the IER
3147 wait_for_xmitr(up
, BOTH_EMPTY
);
3148 serial_port_out(port
, UART_IER
, ier
);
3151 * The receive handling will happen properly because the
3152 * receive ready bit will still be set; it is not cleared
3153 * on read. However, modem control will not, we must
3154 * call it if we have saved something in the saved flags
3155 * while processing with interrupts off.
3157 if (up
->msr_saved_flags
)
3158 serial8250_modem_status(up
);
3161 spin_unlock_irqrestore(&port
->lock
, flags
);
3162 serial8250_rpm_put(up
);
3165 static unsigned int probe_baud(struct uart_port
*port
)
3167 unsigned char lcr
, dll
, dlm
;
3170 lcr
= serial_port_in(port
, UART_LCR
);
3171 serial_port_out(port
, UART_LCR
, lcr
| UART_LCR_DLAB
);
3172 dll
= serial_port_in(port
, UART_DLL
);
3173 dlm
= serial_port_in(port
, UART_DLM
);
3174 serial_port_out(port
, UART_LCR
, lcr
);
3176 quot
= (dlm
<< 8) | dll
;
3177 return (port
->uartclk
/ 16) / quot
;
3180 int serial8250_console_setup(struct uart_port
*port
, char *options
, bool probe
)
3187 if (!port
->iobase
&& !port
->membase
)
3191 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
3193 baud
= probe_baud(port
);
3195 return uart_set_options(port
, port
->cons
, baud
, parity
, bits
, flow
);
3198 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3200 MODULE_LICENSE("GPL");